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| -1 - [channe l lab] 4 v x p o 1 0 # 0 9
. b f u b o e p o h
: p v o h u p o h h v
4 v x p o t j
( z f p o h h j e p
, p s f b 5 S5H1420 [channel decoder for dvb-s/dss] da t a sheet samsung electronics co, lt d. 10 jan. 20 04 (v ersion 4.5. 1) note: this d o cument atio n is prelimin ar y and is s ubject to ch ange. sams ung electron i cs co, lt d. reserv es the right to do a n y kind of modification i n this dat a s h eet r e gardi ng hard w a re or sof t w a re imp l ement a tion s w i th out no tice. sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation
s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 2 t a b l e o f c o n t e n t s p a g e 1. introductio n...???? ? ???? ? ???? ? ???? ? ???? ? ???? ? ? ? 3 1.1 overvie w ?????????? ??????????????...???????.????.3 1.2 f eat ure s ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?..3 1.3 applications?? ?? ?????? ?????? ?????? ?????? ?????? ??3 1.4 ord e ri ng information ? ???? ?? ???? ?? ???? ?? ???? ?? ???? ?? ??3 1.5 function al bock diagram ???? ???? ?? ???? ?? ???? ?? ???? ?? ??.4 2 . in inf o r m at ion ...? ? ? ??? ?? ??? ?? ??? ?? ??? ?? ??? ?? ??? ? 4 2.1 pin a ssi gnme n t?? ???? ?? ???? ?? ???? ?? ???? ?? ???? ?? ???4 2.2 pin de scripti on ?? ? ??? ?? ? ??? ?? ? ??? ?? ? ??? ?? ? ??? ?? ? ??5 3. functio n al description ...????? ?? ???? ?? ???? ?? ???? ?? ???? 6 3.1 signal proc ess i ng ??? ????????????? ?????????? ??????...6 3.1.1 i & q inpu ts ?? ??????????????????????????????6 3.1.2 pre ? agc?? ? ???? ?? ???? ?? ???? ?? ???? ?? ???? ?? ?6 3.1.3 root ra ised co sine a nd rate conv ersion filter ???? ?? ???? ?? ???? ?? ?6 3.1.3 offset can c ell a tion ...????? ???? ?? ???? ?? ???? ?? ???? ?? ?.6 3.1.4 post ? agc ........ ???????????? ???????????? ???????6 3 . 2 t i m i ng reco ver y .? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ?? ..6 3.2.1 timing control?? ?????? ?????? ?????? ?????? ?????? ...6 3.2.2 loop e quation???????? ?????? ?????? ?????? ?????? . 7 3.2.3 timing lock indicato r? ???????????????? ...????????????.7 3.3 carrie r recovery a nd derotator loop ?? ? ???? ?? ???? ?? ???? ?? ????.7 3.3.1 loop equation ? ?????? ?????? ?????? ?????? ?????? ?7 3.3.2 ca rri er lock dete c to r?? ??? ???? ?? ???? ?? ???? ?? ???? ?? ?.8 3.3.3 derotator frequency??????????????????????????????..8 3.3.4 autom a tic fre que ncy detecto r? ???? ?? ???? ?? ???? ?? ???? ?? ?.8 3.3.5 false l o ck?? ?? ???? ?? ???? ?? ???? ?? ???? ?? ???? ?? ?8 3 . 4 forward error correc t ion???? ?????? ?????? ?????? ?????? ??8 3.4.1 f e c modes??? ?????? ?????? ?????? ?????? ?????? ..8 3.4 . 2 soft d e cision?? ?????? ?????? ?????? ?????? ?????? ?8 3.4 . 3 vi terb i decoder and synchron ization?? ? ? ??????????????????? 8 3.4.4 synchr onization? ??????????????????????????????...9 3.4.5 error monitoring? ??????????????????????????????..9 3.4.6 convol utional deint erleave r ?? ????? ? ????? ? ????? ? ????? ? ? 9 3.4.7 reed-solomon decoder and descramble?? ???????????????????9 3.4.8 s p e c tru m inverse of cod e rate 5/ 6??? ??..???? ?? ???? ?? ???? ?? 10 3.4.9 mpeg interfa c e? ? ???? ?? ???? ?? ???? ?? ???? ?? ???? ?? 10 3.4.9.1 parall el output interface? ???? ?? ???? ?? ???? ?? ???? ?? ?1 0 3.4.9.2 serial outp u t interfa c e? ? ???? ?? ???? ?? ???? ?? ???? ?? ?10 3.4.9.3 m peg clock cont rol ?? ???? ?? ???? ?? ???? ?? ???? ?? ?12 3.5 front e nd int e rfa c e?? ? ? ? ??? ?? ??? ?? ??? ?? ??? ?? ??? ?1 3 3. 5. 1 i 2 c in ter f ac e????? ?????? ?????? ?????? ?????? ????.1 3 3.5.2 write o peration (normal mod e )? ???? ?? ???? ?? ???? ?? ???? ?? 13 3.5.3 rea d operation (normal mode )? ???? ?? ???? ?? ???? ?? ???? ?? 13 3.5 . 4 id enti f i c ation reg i ster????? ?????? ?????? ?????? ?????? ..13 3.5.5 sa mpli ng frequency??????????????????????????????13 3.5 . 6 clock genera t ion? ?????? ?????? ?????? ?????? ?????? .13 3.5.7 i 2 c bus re peate r ? ???? ?? ???? ?? ???? ?? ???? ?? ???? ?? ..14 3 . 5 . 8 d i seqc in terface??? ?????? ?????? ?????? ?????? ????1 4 4 . r e g i st er l i st? ? ? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ?? .. 16 5. elec trical charact eristic s ????? ?????????????????????? 26 5.1 absolute maximu m rating s? ???? ?? ???? ?? ???? ?? ???? ?? ????.2 6 5.2 recommended op erating condi tions???? ?????? ?????? ?????? ???2 6 5 . 3 dc el ectrical char acteris t ics? ?????? ?????????????????????..2 6 5 . 4 a/d con v er ter ???? ?????? ?????? ?????? ?????? ?????? ?26 5.5 timing ch aract e ri stics?? ? ? ??? ??? ??? ??? ??? ??? ??? ??? ???.2 7 5.6 i 2 c bus ch ara c teri stics???? ????? ? ????? ? ????? ? ????? ? ???28 6 . a p pl icat ion exa mpl e s? ??? ??? ??? ??? ??? ??? ??? ??? ??? ?? .. 29 6.1 applicati on example s with dvb-s tuner??? ???? ?? ???? ?? ???? ?? ??29 7. package d i mensio n????????????????????????????????. 30 8. data sheet update hist or y ???????????????? ????????????...??. 31 sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 3 1. introduction 1.1 ov er v i e w the S5H1420 is a singl e chip chann el decoder ic f o r dbs (di g ital br oadcasti ng system for satellite) receiver. it consi s ts of a m u lt i-standard qpsk/bpsk demodulator and fec (forward error correction) decode r com p liant with dvb-s and dss standa rd. for multi-an tenna control it provide s diseqc1.x and 2.0 sta n d a rd s. 1.2 features 1.3 applica t ions dvb-s re cei v er and stb digit a l satellit e tv pci satellite card 1.4 ordering information t y pe nu mbe r packag e de scriptio n 1. s5h1 420x0 1 64 lqfp -10 1 0 plastic l o w p r ofile qu ad fl at package; 64 lead s (l ea d length 1.0m m) body 10x10x 1.0 mm sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 4 1.5 function al bock diag ram agc phas e r o tator di git a l fi lter ti m i n g phas e re c o v e ry dual ad c viter b i d e coder byt e sy nc rs de c o d e r de - sc ra m b l e r lock in dic a tor e rro r m oni tor de - inter l e a v e r m peg i/ f d i seq c i/ f i2c i/ f cl o c k gener ator 2. pin information 2.1 pin assign ment figure1: pin-out for 64-pin lqfp S5H1420 64-lqf p top view vsel r ese t _ n err o r syn c vdd 2 5 da ta 0 da ta 1 da ta 2 v dd2 5 vss25 i d _sel 1 i d _sel 0 c l k_sel sc l sd a v dd2 5 vss25 rfs d a f m hz cl k o ut t est _sel 0 da ta 6 nc 27 26 25 23 22 20 19 18 17 32 31 29 28 a v dd_ p l l da ta 7 vss33 av d d _ a d c ad c_ o s c_ i n vd d 2 5 rf s c l vss25 vd d 3 3 52 54 55 56 57 59 61 49 50 51 vref _h ag c vss25 a vss_ a d c v dd2 5 b y te _ c lk ln b_e n vr ef _l a v bb _a dc qn a vss_ a d c qp olf d i seq c t est _sel 1 a v dd _a dc cml vali d nc v ss25 ip 38 39 40 42 43 44 45 47 48 34 36 37 33 1 62 64 v ss33 vdd 3 3 da ta 3 da ta 4 da ta 5 a vss_pl l avb b _ p l l avd d _ p l l xt a l _ou t xatl _i n a vss_ pl l 2 3 4 5 6 7 8 10 1 1 12 13 14 15 16 21 24 30 35 41 46 53 58 60 63 in 9 sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 5 2.2 pin desc riptions p i n n a me i/o c e l l t y pe p i n n u mber d e scr i p ti on olf input 1 lnb over loa d flag re se t_ n schm it t t r igg e r 2 h/ w res e t ( a ct i v e low ) error error_out 3 error indicator output sy n c s y n c _ o u t 4 sy nchronization o u t p u t v a lid v a lid_out 5 v a lid dat a perio d n c n c 6 n c da t a output [7] 30 mpeg2 s t ream seria l dat a d a t a output [7:0] [:] mp e g 2 s t ream p a rall el d a t a [pin 30,17,16,1 5 ,12,1 1 ,10,9] sda i/o-open drain(5v) 21 seria l dat a from host scl input(5v) 22 seria l clock fro m host clk _ s e l input 23 master cloc k s e lect id_s e l 0 i n p u t 2 4 i2c a d d r e s s select[t 0 ] id_s e l 1 i n p u t 2 4 i2c a d d r e s s select[t 1 ] tes t _ sel 0 input 28 t e st mode sele ct[t 2] tes t _ sel 1 input 29 t e st mode sele ct[t 3] n c n c 1 8 n o conn ect i o n xt al_i n o s c i l l a t o r i n p u t 3 6 cry s t a l oscillato r input xt al_o ut o s c i l l a t o r o u t p u t 37 cry s t a l oscillato r output fmhzclko ut output 38 referenc e cloc k output rfsda i/o-open drain (5v) 41 rf mod u le con t rol sda rf scl n-ch-open dra i n (5v) 42 rf mod u le con t rol scl adc_os c_i n o s c i l l a t o r i n p u t 4 5 o s c i l l a t o r i n p u t a v d d _ a d c d i git a l pow e r 4 6 ad c t o t a l pow e r ip inphase po sitiv e 47 adc ana l og inp u t in inphase negative 48 adc ana l og inp u t qn quadrature neg a tive 50 adc ana l og inp u t qp quadrature pos i tive 51 adc ana l og inp u t vref_ l ana l og referen c e 53 adc bottom re ference v o lt ag e vref_ h ana l og referen c e 54 adc t op refer ence v o lt age cml ana l og referen c e 55 common mo de level v o lt age agc n-ch open dra i n(5v) 60 gain co ntrol ou tput diseq c bid i rectiona l ( 5 v ) 6 1 a n t e n n a s e le c t by te_ c lo ck output (3.3v) 62 dat a t r ansfer clock vs el output 63 lnb v o lt ag e se lect fla g lnb _ e n o u t p u t 6 4 l n b enab l e f l a g rf interface & adc pow e r supply (24) av dd_a d c 4 6 , 5 7 av ss_ a d c 5 6 , 4 9 ad c av bb_ a d c 5 2 av dd_pl l 3 1 av ss_ p l l 3 2 av bb_ p l l 3 3 av dd_pl l 3 4 pll av ss_ p l l 3 5 vs s 3 3 1 3 , 3 9 io v d d 3 3 1 4 , 4 0 vs s25 7, 19, 26, 43, 5 8 logic vdd25 8, 20, 27, 44, 5 9 sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 6 3. functi o nal de scriptio n 3.1 signal proces sing 3.1.1 i and q inputs the dual adc can get differe ntial (ip/in, qp/qn) o r singl e input s (ip, qp), i/ q signal s fro m the tuner are fe d to th e ip and qp inputs th ro u gh a dc co u p ling cap a cit o r a nd in an d qn mu st b e set dc voltage as cml (typical: 1/2vdd). th e refere nce voltage of high [vref-h] and low [vref-l] sho u ld be supplied from exter nal generator for app lication flexibility. 3.1.2 pre-agc the po wer o f i/q signal is com pared to a progra mmable thre shol d value, and the differe n ce is integrated. this si gnal i s then conve r te d into a pu lse width mo d u lation (p wm ) sig nal to dri v e the agc output and it will be lo w pa ss filtered by a simpl e rc analo g filter to cont rol the gain comma n d of any amplifier bef ore th e a/d conve r ter. t h e pwm o u tp ut ope rate s at f clk / (1, 4, 8 and 16 ) i n order to decre ase the radi ated noi se and to sim p lify the filter desig n, and is a 5 v tolerant open d r ain stage. the pre-a g c co ntrol s are in addre s s 0x07 and the pr e-ag c integrator regi ster is in add r e ss 0x1 5 . 3.1.3 roo t ra ised cosine and rate con v ersion filter the root rai s ed cosi ne (rrc) and ra te conversion f ilter performs anti-ali a si ng filtering, root raise d co sine sha p in g, rate co nversion, timing synch r oni zatio n and tra c kin g with the timing loop. two roll-off factors are avai labl e: 0.35 (dvb-s) and 0. 20 (dss). 3.1.4 offse t canc e llation this device sup p resse s the resi dual i/q dc comp onent in the qpsk system control registe r in addre s se s 0x05 and 0x0 6 . 3.1.5 post-ag c the post-a gc sh all be able to adjust the gain of the incomi ng i/q sample from the rrc and rate conve r sion filter and imple m ent the closed loop that sets the gain adjustm ent. the reset value (0x80 0 0 ) of the post-agc integ r at or re giste r ca n allow an in it ial set t ling t i me of less t h an 50 k mast er clo c k peri o d s . the post -agc cont rol s are i n add r e ss 0x08 a nd t he post-a gc inte grato r re giste r i s i n address 0x16. 3.2 timing recov e r y 3.2.1 timing contr o l the timing lo op is p r og ram m ed with the expecte d sy mbol freq uen cy. we have ( 1 + ) fs ym > cl k f 2 for (1+ ) fs ym < cl k f 2 for sym clk f f 2 24 sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 7 3.2.2 loop e quation the timing loop may be co nsid ered as a seco nd order loop. the loop equation m a y be calcul ated usin g the followin g formul a: p g +8) ? i g ) = t (1 < < i g ) whe r e, p g is pro pag ational gain, i g is integral gain a n d t is timing fac t or. t = 5.0 and we ca n cho o se loop band width ( bl ), as follows : 1 sym cl k f f 24 2 ) 4 1 1 ( 2 1 2 + = bl whe r e and 2 3.2.3 timing lock indicato r the timing detecto r need to a lot of symbol s for stab ilizatio n in orde r to lock after tuning freq uen cy cha nge of rf and it take s a 1-bit in put signal, an d us es the p r e s e n c e o r ab se nce of locking i n formatio n to either coun t up or co unt down re sp ect i vely. the co unte r ope rate s up to rea c he s its maximum value wh en the lock si gnal g oes a c tive. two cases can cau s e th e lock sign al to go to unlocked stat e; one is assertio n of the active-low re set and the other the counte r go ze ro agai n. use r can monitor the m sb 8 bits of tll (timing lock loo p ) cou n ter in addre s s 0x1a and the tll l o ck flag in ad dre s s 0x14. 3.3 carrie r recov e r y the tra cki ng range of the d e rotato r is f clk /2 ( f sa mplin g /2 ). this algorithm is used wit h qpsk reception, over a sm all range of capture pha ses and with a channel noise value o v er 3.0 db. 3.3.1 loop e quation like the timin g loop, the ca rrie r loo p is a se con d -ord er system where two pa rame ters, p g +8) ? i g ) p (1< < i g ) whe r e, p g is pro pag ational gain, i g is integral gain a n d p is phase factor. 1 sym cl k f f 24 2 p = 75.4 also, we can cho o se loo p band width ( bl ), as follows : ) 4 1 1 ( 2 1 2 + = bl whe r e and . 2 3.3.2 carrie r lock detecto r sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 8 the carrier lo ck d e tecto r o perates the same a s the timing lo ck d e tecto r in the phase locke d loop (pl l ). user ca n mo nitor the msb 8 bits of pll lock cou n ter in address 0x19 an d t he p ll lo ck fl ag i n address 0x14. 3.3.3 dero ta tor frequ e ncy the de rotato r freque ncy ca n be eithe r measured (rea d ope ration ) or forced (write ope ration ). f derot = 24 2 sy m clk f f 3.3.4 automatic fr equen c y detec t or the automati c freque n c y detecto r (afd) can evaluate the carrie r freque ncy offset quickly, an d may b e cou p led to th e ca rrie r re co very loop. the digital loop filter of pll has two path s , pr opo rtional an d integral, with program mable gai n re spe c tively. the integ r a l path co ntai ns an accu mulator wh o s e conte n ts can b e an al yzed a s a avera ged carrier frequ en cy offset. the pha se error si gnal go e s into two paths, the respe c tive gains a r e applied, the ?i? path is integrated, and the two are add ed togethe r. a kicke r of afd c an hel p pll to achieve lock fast. the kicker find s the phase error sig nal for larg e transitio ns, inse rts a larg e value, into the ?i? path. therefore, pll can trace the larg e frequ en cy offset. 3.3.5 false lock a false lo ck o c curs whe n p hase lo ck ha s be en dete c ted in th e qp sk, but the correct cent ral frequ en cy has not yet been reached. this situat ion occurs in qpsk for frequency offset points that are multiples of f sy m /4, where f sym is the qpsk symbol rate, and al so at othe r of fsets di ctated by the discrete nat ur e of the carri er recove ry loo p . therefo r e, the carri er recove ry loop must be ha ndled to take care of a false lock condition. 3.4 for w a r d error corr ec tion 3.4.1 fec modes since the s5 h14 20 is a m u lti-sta nda rd decode r, sev e ra l combi nat ions a r e p o ssible, at differe nt levels: the demodulator may accept either qpsk or bpsk signal s - the only impact is on the carrier algo rithm ch o i ce. the al gorithm choi ce al so affect s the carrie r lock d e tecto r and th e noise evalu a tion. there are two prim ary o p tions con c e r ning the fec operatio n - betwee n dvb-s, dss and re se rved mode. there a r e t w o optio n s concerning th e fec feedi n g . t he first is iq flow, whi c h is th e usu a l ca se in qpsk modes dvb-s or dss. the second mode is i-only flow, used for bpsk. the fec mo de re giste r is in addre ss hex 22. in mode s dv b-s and dss , data is fed to the soft decisi on s. 3.4.2 soft de cisions the ada ptive equalizer out put is conve r ted into 4-bit sign -ma gnitu de format by the soft decision block, for use by the viterbi decode r. the msb corre sp o nds to the sliced bit value. the 3 lsbs of the soft deci s io ns rep r e s ent the co nfiden ce of the sli c ed bi t value, whe r e 111 a r e hig h confid en ce, a nd 000 i s low confide n c e. a prog ra mmable set of thresh old s can be u s e d in gene rati ng the three lsbs and, con s e que ntly, in optimizing the viterbi deco d e r perfo rman ce a s a functio n of co de rate. 3.4.3 viterbi decod e r and s y nchronization the co nvoluti onal co de s are gen erate d by the polynomial g x = 171 octet s and g y = 133 octets in mode s dvb - s or dss. th e viterbi d e code r co mput es for ea ch symbol the me trics of the fo ur po ssible paths, p r op ortional to the squ a re of the euc lidi an d i stan ce b e tween the re ce ived i and q and th e theoretical symbol value. the pun ctu r e rate and pha se are estima ted on the error rate ba si s. several rate s are allo wed and may be ena bled/di sabl ed throug h regi ster p r o g ram m ing: sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 9 1/2, 2/3, 3/4, 5/6, 7/8 for dvb-s 1/2, 2/3, 6/7 for dss for ea ch e n a b led rate, the cu rre nt error rate is co mpa r ed to a pro g rammabl e thre shol d. if it is greate r than this thre shol d, anothe r pha se (or a nothe r rate ) is tried u n til the right rate i s obtaine d. a prog ram m a b le hyste r i cs is ad ded to a v oid losi ng th e pha se du ri ng sho r t-term pertu rbatio n. the rate may also be impo sed by external softwa r e, and th e pha se is in cremente d o n ly upon re q uest by th e microp ro ce ssor. the e r ror rate may be read at any ti me in ord e r to use a n al gorithm other than that impleme n ted. the viterbi d e co de r prod u c e s an absol ute deco d ing . the decod er is cont roll ed via several viterbi thre sh old re giste r s (regi sters 29, 2a , 2 b , 2c, 2d an d 2e). fo r e a c h viterbi th resh old regi st er, bits 7 to 0 re pre s e n t a norm a liza t ion rate th re shol d ? t he a v erag e num b e r of n o rm ali z ation occu rri ng du rin g sync pe riod s. the sync pe riod i s control l ed via vite rbi sync regi ster (re g iste r 2 f ). the pun ct ure rate and viterbi in itial configu r a t ion is in add r e ss 30, 31. the autom atic rate research is o n ly do ne thro ugh the ena bled rates (se e the corre s p ondi n g bit set in th e punctu re re giste r). in ds s, it is reco m m end ed that you disa ble pun ctu r e rates 3/4, 5/6 and 7/8 in o r d e r to save tim e in the synchro n ization proce s s. the v i t e rbi d e co de r sy n c sea r ch c an control u s in g the pun c ture registe r . 3.4.4 sy nchroniza tion in dvb-s, th e packet leng th after inner decodin g is 2 04. the sync wo rd is the first byte of each packet. its value is hex 47, but this value is co mpleme nted every 8 packets. in dss, the pa cket len g th is 147 and the syn c wo rd is hex 1 d . an up/down sync co unte r co unts w h e never a syn c word is re co gnized with the corre c t timing an d cou n ts do wn duri ng ea ch missing sync wo rd. this co unter i s bo und ed by a prog ramm able m a ximu m - whe n this value i s re ached, the sy nc_f lag bit (?lo c ked?) is set in the sync0 2 regi ster. wh en th e event count er co unts d o w n to until 0, this flag is res e t. 3.4.5 error monitoring a 16-bit co un ter, errcnt , allows the counting of e r ro rs at differen t levels. er rcnt is fed eit her by: the input qpsk bit errors (that are corrected by the vite rbi decoder), or, the bit, or, the byte error (it will be correc ted by the reed -sol omon decoder) the packet error (it is un co rre ctabl e a nd lead to a p u lse at the e r ror o u tput ) the conte n t of errcnt may be transferre d to t he rea d only reg i sters err_cnt_ l (lsb) and err- cnt_ h (msb ). two fun c tio nal mod e s a r e pro p o s ed, d epen ding o n a cont rol re gi ster bit: 1. err_ disp = 0. the un correcta ble blo ck flag e r ro r that error count is not in cremente d . 2. err_ disp = 1. the un correcta ble blo ck flag e r ro r that error i s counte d as 2 7 errone ou s bits (it has nin e erron eou s byte s with three corrupted bit s per byte). 3.4.6 conv olutional deinterleav er in dvb-s, the convol utio nal deinte r le aver is 17 12. the peri odi city of 204 bytes per sync byte is retain ed. in dss, the co nvolutional d e interl eaver i s 146 13, and there is al so a perio dicity of 147 bytes pe r syn c byte. the d e interl eaver may be bypa ssed. 3.4.7 ree d -s olomon dec oder and de scrambler the input blo c ks are 204-b y te long with 16 parity bytes in dvb-s. the syn c byte is the first byte of the block. up to 8 byte erro rs may be fixed. the code g e n e rato r polyno m ial is: g( ) = ( ? 0 ) ( ? 1 ) (...) ( ? 15 ) over the gal o is fiel d gen erate d by: 8 + 4 + 3 + 2 + 1=0 energy di spe r sal de scram b ler a nd outp u t energy dispersal d e scra mbler g ene ra tor: 15 + 14 + 1 the polyn omi a l is initialize d every eight blocks with th e seq uen ce 1 0010 101 000 0 000. the syn c words a r e un scra mbled a nd th e scram b le r is re set every 8 packet s . sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 10 the output interfa c e may be forced i n to high imp edan ce mo d e by setting mpeg_oen =0 in the addre s s 39. doin g this affects th e dat a [7:0], byt e_cl ock, s y nc, valid and e r ror pins. t h e output stream is either p a ra llel (byt e stre am) o r se rial (bit stre am) d epen ding o n bit 1 of addre ss 3 9 . 3.4.8 s p ectr u m in v e rse of cod e ra te 5/6 in case of co de rate 5/ 6, becau se of it s ch aracte r , rega rdle ss of con d ition of spect r um it ca n be locke d . re st of the c ode rate s except 5/6, if v i terbi is locke d , byte becom es syn c but in case of cod e rate 5/6, even if v i terbi is locke d there are cha n c e s byte does not beco m e sync. therefore, in ca se of code rate 5/6, it should b e processed u s in g s/w . processin g proce d u r e is li ke belo w . 1. when the rest is lo cked except byte sync, cod e rat e che c k 5/6. - co de rate m onitori ng : addr [ 0x3 2 ], bit pos ition[ 0-2 ] 2. when cod e rate is 5/6, che ck inve rse spe c trum st atus. - s pect r um in verse monito ring : addr [ 0x 32 ], bit pois i tion[ 3 ] 3. inverse inv e rsion spe c trum. - s pect r um in verse setting : addr [ 0x31 ], bit pois i tion[ 3 ], set 1 a d d r [ 0x3 1 ], bit pois i tion[4], set 1 or 0 3.4.9.1 parallel output interfa ce a sch ematic diag ram of th e parallel out put interfa c e i s sh own in fi gure 4. the p a rall el output format is com p liant wit h the dvb-s comm on inte rface p r oto c ol. whe n the byte sync is not found (sync_flag = 0 in the sync02 registe r), valid (corre spo nding to the mival si gnal of the dvb-s commo n inte rfa c e st anda rd ) rem a ins at a low le vel. byte_clo c k has a duty cycle b e twe e n 40 an d 60 %. the valid sig nal i s ge nerated de pe nding o n bit 2 of address 39. th e byte_clo c k, sync, val id and e r ror sig n a l polarity is cont rolle d depe ndin g on content s in the re giste r 3 8 . 3.4.9.2 serial output inter f ac e the serial o u tput interfa c e i s sh own in figure5. the serial bit strea m is availabl e on d7, wh ere msb is first to recon s truct the ori g i nal ord e r. if mpeg_dou t = 1, then the parity bits a r e output (re g iste r 39). if mpeg_do u t =0, the da ta is null du ri ng the pa rity time slot s. sync is o n ly high du ring t he first bit of each pa cket, instea d of during the first b y te in parallel mode. error h a s t he sa me fun c tion as in pa rallel mod e . b y t e _ clo c k is t he serial bit clock; it is same the master clo ck, fclk. all of the o u tputs are synchrono us of the same maste r clo c k edge. d7, sync, valid a nd error m a y be prop erl y sampled externally by the risi ng ed g e of byte_clock. the first bit detecte d in a valid pa cket may be d e co ded if it is foun d on the ap pro p ri ate edg e of byte_clo c k, where sync = 1, error = 0, valid = 1. the fol l owin g bits on ly requi re the asse rtion of valid (while valid = 1,). outputs d0 to d6 remai n at low level in serial mode. sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation - - 11 s5h 1 420 dbs channel dec o der for dvb-s/ d ss b y t e _clo ck c dcl k_ po l = 1 sy nc va l i d err o r m peg _err=1 n o err o r n o er ro r pa ri ty data uncorrectibl e p a cket figure4 : parall el output interf ace cdclk_p o l=0 m p e g _clk =1 mp e g _clk =0 m p e g _c lk =1 m p e g _c lk =0 m peg_e rr=0 sy nc va lid d0 mpe g _ d o u t = 1 erro r data par i t y par i t y useful data fi r s t bit of the packet 1 pack e t 1/ fc l k fig u re5 : serial ou tpu t int e rf ace by t e _clo ck cdclk_p o l= 1 cdclk_p o l= 0 mpeg_dout = 0 mpe g _e rr=0 mp eg _err=1 table 0 bit1 of 0x39 bit4 of 0x02 s e r _ p a r s e r _ s e l _ m o d e mpeg data mpeg cloc k parallel 0 1 data [7:0] byte_clk serial 1 1 data[7] byte_clk sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 12 3.4.9.3 m p eg c l o c k co ntr o l - th ro ugh re giste r setting, s5h14 20 ca n cont rol mp eg clo c k to mcu. stb mcu 60m hz 81m hz symbol rate symbol rate >= 2 5 symbol rate < 25 symbol rate >= 2 5 symbol rate < 25 s5h1 420 ma ster clo ck 59m h z 8 8 m h z 80m h z 88m h z s a m p l i n g 1 2 1 2 - co ntrol regi ster , 3 - bit, uses add r e s s 0 x 22 ( mpeg_cl k _intl [2:0]) - if control registers changes, some blocks will be reset autom atically . - in ca se, auto re set doe s not wo rk, the s e blo c ks? re set can be d o n e manu ally . - mpec if cl ock is ma de by control re giste r and the rule s are as follows - tmp = (fm c lk/fsr)* ( 1/(2*cr)), fmclk : system clo ck frequ e n cy ,fsr : symbol rate, cr : code rate mclk =88 m h z mpeg clo ck (mh z ) cont rol regi ste r (0x 2 2 ) mpeg clock(parallel) mpeg cloc k (seri a l) ran g e d i v i d e s e r i a l p a r a l l e l 0 f mc l k / 8 f mc l k 1 < < < < < < < < sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 13 3.5 front en d interface s 3.5.1 i 2 c inte rfac e the stand ard i 2 c protocol i s u s e d whe r e b y the first byte is h e x a0 fo r a wr ite op er a t io n , or h e x a1 fo r a read operation. 3.5.2 write o p era t ion the byte s equenc e is as follows : 3.5.3 rea d opera tion the add r e s s of the first regi ster to read is p r o g rammed in a write op erat ion witho u t data, and terminate d by the stop con d ition. then, anothe r sta r t is followed by the device ad dre s s and r/ w= 1. all followin g bytes are no w dat a to be read at succe ssive position s sta r ting from the initial address. figure 2 sho w s the i 2 c no rmal m ode write an d rea d re gisters. figure 2 : i 2 c rea d and wri te operation s in mode write regi ster 0 to 3 with aa, bb, cc, and dd 4 u b s u " $ , % f w j d f " e e s f t t 8 s j u f % 3 f h j t u f s " e e s f t t " $ , " $ , % b u b " " % b u b # # " $ , % b u b $ $ " $ , % b u b % % " $ , 4 u p q rea d re giste r 2 and 3 4 u b s u % f w j d f " e e s f t t 3 f b e % " $ , % b u b 3 f b e $ $ " $ , % b u b 3 f b e % % " $ , 4 u p q 4 u p q 4 u b s u % f w j d f " e e s f t t 8 s j u f % " $ , 3 f h j t u f s " e e s f t t " $ , 3.5.4 identifi cation re gister the identifica t ion regi ste r (at address hex 00) give s the rel e a s e nu mber of the ci rcuit. the content o f this regi ster at reset is pre s ently (hex02 ) 3.5.5 sampling frequ e nc y the s5 h1 42 0 convert s th e an alog i n p u ts into digita l 6 bit i an d q flow. t he samplin g fre q u ency i s f cl k whi c h is derived from a n external refere nce de scri bed in se ction 3.5.6 ? c lo ck g ene ration?. the maximum val ue of fclk is 90 mhz. the samplin g cau s e s the repetition of the input spe c trum at ea ch intege r mul t iple of f clk o ne ha s to ensure that n o frequen cy compo nent is fol ded in the useful sig nal b and width of f sy m (1+ f sy m is the symb ol frequ en cy, and 3.5.6 clock g e nera tion an integ r ated pll i s the ci rcuit syn c h r o n izin g a n out put si gnal (g ene rated by a vco with a refe ren c e sign al in freq uen cy as wel l as in pha se . in this application, it incl ude s the follo wing b a si c bl ocks. th e pha se freq ue ncy detecto r to detect the phase diffe rence betwe e n the referen c e freq uen cy and the output frequ e n cy (after divi sion ) and to control the cha r ge pu mp s voltage. regi ste r setting can pro g ra m the desi r e d f r e q u e ncy. f out = ( m u f in )/ ( p u s ) f in : input frequency, m =m+8 , p =p +2, s =2 ^s m: regi ster 0 3 , p: register 04 [5:0], s: registe r 04[7:6 ] sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 14 3.5.7 i 2 c bus repea t er in low symbo l rate applica t ions, sign al pollution ge n e rate d by the sda/scl lines of the i 2 c bus may dram atically wo rsen tune r phase noi se. in orde r to a v oid this prob lem, the S5H1420 offe rs a n i2c bu s rep eater so that the rfs d a an d rfscl a r e active only when n e ce ssa r y. both rfsda an d rfs c l pins a r e set high at re set. when th e mi croprocesso r write s a 1 int o regi ster bit i2c_ rpt, the next i 2 c messa ge on sda and scl is re peat ed on the rfsda and rfscl pins resp ectively, until stop con d ition s are detecte d. to write to th e tuner, the e x ternal micro p ro ce ssor m u st, for each tuner me ssag e, perform the followi ng: 3.5.9 diseqc inter f ac e this interface allows for the simplif i c atio n of real tim e pro c e ssi ng o f the dialog from micro p ro cesso r to lnb. it includes regi ster set (8 bytes) that is filled by the micro p ro ce ssor via the i 2 c bus, and the n tran smitted by modulating to 22 khz clo ck. the s5h1 420 su ppo rt diseqc2.0 for bi-directio n a l interface betwe en mi croprocesso r to lnb and can chan ge the tone fre que ncy by register setting. < tran smiss i on > the s5h142 0 have thre e mode s for di seqc interfa c e. < re cei v e > the s5h142 0 receives th e data from l n bs u s ing di seq c pin. in ord e r to re cei v e the data from lnb s sho u ld set the regi ster rcv_en to 1. the rec e ived data is s t ored t o regis t er s e t. two control signal s are available o n the i 2 c bus: dis_ rdy (t ransfe r ready /finish ) and dis_le ngt h (me s sag e length ) . a typical byte transfe r loop, as se en from the micro p ro ce ssor, may be the followi ng: while (there is data to tran sfer) 1 rea d the di s_rdy sign a l s 2 if dis_rdy = 0 , write byt e to trans fer in the regis t er s e t. 3 set the dis_length. 4 set the dis_rdy = 1 . note, for the above tra n sfe r loop, the foll owin g: sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 15 figure3 : sch e matic sho w ing bit trans m ission tran smis s i on of 1's trans mis s i on of 0's b 4 8 * 5 $ ) @ $ 0 / b ) sw i t c h_co n = 0 id le 11 pe riods 1 1 perio d s 1 1 perio d s nex t b i t table1 lnb_ co n s w i t c h _ c o n regi ste r set o u t p u t 0 0 x e m p t y contin uou s t o n e 0 data=00 unm odul ated tone burst 01 1 d a t a = f for0 0 modul e t o n e b u r s t 1 0 x n o t e 1 d i s e p c sign a l 1 1 x x x re se r v e d note: 1 byt e to trans fer in diseqc mode. 2 i n m ode l n b _ c on ( 1 : 0 ) =1 0, t h e di seqc pi n ret u rn t o hi gh 2 m ode once t h e t r ansm i ssi on i s co m p leted . sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 16 4. register list 3 a d d n a m e b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 b i t 0 i d 0 x 0 0 i d 0 1 s5h142 0 _ i d 0 x 0 1 c o n _ 0 0 soft _rst 0 0 dss_dv b s y st em 0 x 0 2 c o n _ 1 0 0 ser_se l 0 0 p w r _ d n i 2 c _ r p t 0 x 0 3 p l l 0 1 m pll 0 x 0 4 p l l 0 2 s p 0 x 0 5 q p s k 0 1 kick_e n 0 1 dc_en 1 1 mode q_st ar t 0 x 0 6 q p s k 0 2 1 1 0 1 du m p _a cc dc_ w i n 0 x 0 7 p r e 0 1 inv_pu l s e 0 1 pre_t h 0 x 0 8 p o s t 0 1 0 0 post _t h 0 x 0 9 l o o p 0 1 w t _ t n c o w t _ p n c o 1 1 0 0 0 0 0 x 0 a l o o p 0 2 loop_ o ut kick_v a l kick_ m u l 0 x 0 b l o o p 0 3 iga_pl f pga_pl f 0 x 0 c l o o p 0 4 igt _ p l f pgt _ p l f 0 x 0 d l o o p 0 5 ig_t l f pg_t l f 0 x 0 e p n c o 0 1 pnco0[ 3 1 : 2 4 ] 0 x 0 f p n c o 0 2 pnco1[ 2 3 : 1 6 ] 0 x 1 0 p n c o 0 3 pnco2[ 1 5 : 0 8 ] 0x1 1 t n c o 0 1 t n c o 0 [ 3 1 : 2 4 ] 0 x 1 2 t n c o 0 2 t n c o 1 [ 2 3 : 1 6 ] 0 x 1 3 t n c o 0 3 t n c o 2 [ 1 5 : 0 8 ] 0 x 1 4 m o nitor0 1 reser v e d t l o c k p l o c k 0 x 1 5 m o nitor0 2 pre_le v e l 0 x 1 6 m o nitor0 3 post _ l e v e l 0 x 1 7 m o nitor0 4 dc_i_le v e l 0 x 1 8 m o nitor0 5 dc_q_l e v e l qpsk 0 x 1 9 m o nitor0 6 reser v e d 0 x 1 a m o nitor0 7 reser v e d 0 x 1 f m o nitor1 2 qpsk_ out dc_fre e ze 0 x 2 2 f e c 0 1 0 0 0 0 m p eg_c lk_int l 0 x 2 3 s o f t 0 1 reser v e d 0 x 2 4 s o f t 0 2 reser v e d 0 x 2 5 s o f t 0 3 reser v e d 0 x 2 6 s o f t 0 4 reser v e d 0 x 2 7 s o f t 0 5 reser v e d 0 x 2 8 s o f t 0 6 reser v e d 0 x 2 9 v i t 0 1 reser v e d 0 x 2 a v i t 0 2 reser v e d 0 x 2 b v i t 0 3 reser v e d 0 x 2 c v i t 0 4 reser v e d 0 x 2 d v i t 0 5 reser v e d 0 x 2 e v i t 0 6 reser v e d 0 x 2 f v i t 0 7 reser v e d 0 x 3 0 v i t 0 8 0 0 vit _ sr78 vit _ s r 6 7 v i t _ s r 5 6 vit _ s r 3 4 vit _ s r 2 3 vit _ s r 1 2 0 x 3 1 v i t 0 9 p a r m _fi x inv_sp e c vit _ f r 0 x 3 2 v i t 1 0 vit _ spec_st s vit _ c r 0 x 3 3 v i t1 1 0 x 3 4 v i t 1 2 0 x 3 5 s y n c 0 1 s y nc_ miss_t h s y nc_hit _ t h 0 x 3 6 s y n c 0 2 by te _ s y n c reser v e d vit _ sync 0 x 3 7 r s 0 1 0 x 3 8 m p e g 0 1 err_po l s y nc_p o l v a lid_ p o l cdclk_ pol 0 x 3 9 m p e g 0 2 1 1 1 clk_co nt 1 ser_p a r d s s _ s y nc 0 x 3 a d i s 0 1 t o n e _ f r e q 0 x 3 b d i s 0 2 r c v _ e n dis_le ngt h dis_rd y s w i t c h _ c o n lnb_co n 0 x 3 c d i s 0 3 o l f _ n l n b _ d n v18_13 v 0 x 3 d d i s 0 4 lnb_ m e s g e 0 0 x 3 e d i s 0 5 lnb_ m e s g e 1 0 x 3 f d i s 0 6 lnb_ m e s g e 2 0 x 4 0 d i s 0 7 lnb_ m e s g e 3 0 x 4 1 d i s 0 8 lnb_ m e s g e 4 0 x 4 2 d i s 0 9 lnb_ m e s g e 5 0 x 4 3 d i s 1 0 lnb_ m e s g e 6 0 x 4 4 d i s 1 1 lnb_ m e s g e 7 0 x 4 5 r f 0 1 sla ve_ a d d r 0 x 4 6 e r r 0 1 alar m _ m od e e rr_cnt _ p r d err_sr c 0 x 4 7 e r r 0 2 err_cnt _ l 0 x 4 8 e r r 0 3 err_cnt _ h fec 0 x 4 9 e r r 0 4 p a rit y _ e r r sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 17 id control register ( a d d r e ss: 0x 00) a ddr . regna m e (reset v a l) signal name wid t h propert y d escripti on 0x0 0 id01 (0x03 ) s 5 h 1 4 2 0 _ i d [ 7 : 0 ] r r e v i s i o n i d sy stem control register s ( a d d r e ss: 0x 0 1 -0x 02) a ddr . regna m e (reset v a l) signal name wid t h propert y d escripti on [ 4 ] r / w set to ?0? s y stem sof t rese t mode (active high) so f t _ r s t [ 3 ] r / w [1] enable [0] disable [ 2 ] r / w set to ?0? [ 1 ] r / w set to ?0? dss/dvb mode selection 0x0 1 con_ 0 (0x00 ) dss_ dvb [0] r/w [1] dss [0] dvb [ 6 ] r / w set to ?0? [ 5 ] r / w set to ?0? s e r _ s e l [ 4 ] r / w set to ?1? [ 3 ] r / w set to ?0? [ 2 ] r / w set to ?0? pow e r do wn mo de [1] po w e r do wn enable p w r _ d n [ 1 ] r / w [0] po w e r do wn disable i2c repeat er con t rol [1] i2c rep eater enable, [0] i2c rep eater disable. note: the maste r should be set th is bit to ?1? in ord e r to interface w i th the tuner . 0x0 2 con_ 1 (0x00 ) i 2 c _ r p t [ 0 ] r / w when the master is not communicated w i th the tun e r , this bit should be set to ? 0 ? pll control registers ( a d d ress: 0 x03- 0 x04) a d d r . r e g n a m e signal n a m e wid t h propert y d escripti o n pll prog ramming information 0x03 pll01 (0x50 ) m [ 7 : 0 ] r / w f out = (( m+ 8 ) ? f in )/(( p+2 ) 2 s ) p [ 5 : 0 ] r / w f in = 4 mh z 0x04 pll02 (0x40 ) s [ 7 : 6 ] r / w sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 18 qpsk con t r o l register s (a d d re ss: 0 x 0 5 ? 0x0 6) a ddr . regna m e (reset v a l) signal name wid t h propert y d escripti on kick_en [7] r/w [1] pll kicker enable [0] disable [ 6 ] r / w set to ?0? [ 5 ] r / w set to ?1? dc of fset remov e d c _ e n [ 4 ] r / w [1] enable [0] disable [ 3 ] r / w set to ?1? [ 2 ] r / w set to ?1? qpsk opera t ion mode [1] 1 sampling/1 sy m bol m o d e [ 1 ] r / w [0] 2 sampling/1 sy m bol q psk st art signa l 0x0 5 q psk01 (0xbc ) q _ st ar t [ 0 ] r / w [1] s t art [0] idle [7] r/w set to ?1? [6] r/w set to ?1? [5] r/w set to ?0? [4] r/w set to ?0? dump phase loo p filter & timing lo op filter accumulator d u m p _ a c c [ 3 ] r / w [0 and then 1] th e read ope ration enabled, w hen u s er set dump_acc ?0? and then ?1 ?. 0x0 6 q psk02 (0xc 1) d c _ w i n [ 2 : 0 ] r / w window position from msb remov i ng dc of fset. un signed integer (0 ? dc_win ? 7) ag c con t rol register s ( a d d r ess: 0x 07 ? 0x0 8) a ddr . regna m e (reset v a l) signal name wid t h propert y d escripti on pwm signal is reversed [1] pwm signal active low i n v _ p u l s e [ 7 ] r / w [0] pwm signal active high [6] r/w set to ?0? [5] r/w set to ?1? 0x0 7 pre01 (0x30 ) p r e _ t h [ 4 : 0 ] r / w pre-ag c thresh o l d [ 7 : 6 ] r / w set to ?0? 0x0 8 post01 (0x10 ) post_ t h [ 5 : 0 ] r / w post -a gc th r e s h o l d sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 19 loop filter c ontrol regis t ers ( a d d r es s: 0x09 ? 0 x 0 d ) a ddr . regna m e (reset v a l) signal name wid t h propert y d escripti on w r ite tnco cent er frequ enc y wt_tnc o [ 7 ] r / w [0 and then 1] th e write oper ation enabled, w hen u s er set wt_tnc o ?0? a nd then ?1 ? w r ite pnco cent er frequ enc y wt_pnc o [ 6 ] r/w [0 and then 1] th e write oper ation enabled, w hen u s er set wt_pnc o ?0 ? a nd then ?1 ? [5] r/w s et to ?1? [4] r/w s et to ?1? [3] r/w s et to ?0? [2] r/w s et to ?0? [1] r/w s et to ?0? 0x0 9 loop01 (0x30 ) [0] r/w s et to ?0? loop filter monito ring selection [1] loop filter accumulator + nc o l o o p _ o u t [ 7 ] r / w [0] loop filter accumulator kick_v a l [ 6 : 4 ] r/w the value that g e t s injected into the accumulator w h en a ?kick? is needed. 0x0 a loop02 (0x65 ) k i c k _ m u l [ 3 : 0 ] r/w the numbe r of bi t s kick_v al is up-shif ted (2 n ) bef ore it is injected into the accumulator . pg a _ p l f [ 3 : 0 ] r / w phase loop, prop ortional gain (2 pg a_p l f ) in the acqui sition mode (default +8 adde d) 0x0b loop03 (0x78 ) iga_plf [7:4] r/w p hase loop, integral gain (2 i g a_ pl f ) in the acquisitio n mode pgt_pl f [ 3 : 0 ] r / w phase loop, prop ortional gain in the tracking mode (default +8 adde d) 0x0c loop04 (0x28 ) igt_pl f [7:4] r/w i ntegral gain in th e tracking mode pg_tl f [3:0] r/w t i ming loop, pro portional gain (d efault +8 added) 0x0d loop05 (0x17 ) ig_t lf [7:4] r/w t iming loop, integral gain nco con t rol register s ( a d d r ess: 0x 0e ? 0x1 3) a ddr . regna m e (reset v a l) signal name wid t h propert y d escripti on loop_out [1] 0x0e pnco01 (0x00 ) pnco1 [ 31:24] [7:0] r/w read plf accu mulator + pnc o loop_out [0] 0x0f pnco02 (0x00 ) pnco2 [ 23:16] [7:0] r/w read plf accu mulator 0x1 0 pnco03 (0x00 ) pnco3 [ 15:08] [7:0] r/w loop_out [1] 0x1 1 tnco01 (0x00 ) tnc o 1 [31:2 4 ] [7:0] r/w read tlf accumulator + tnc o loop_out [0] 0x1 2 tnco02 (0x00 ) tnc o 2 [23:1 6 ] [7:0] r/w read tlf accumulator 0x1 3 tnco03 (0x00 ) tnc o 3 [15:0 8 ] [7:0] r/w sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 20 qpsk monitoring registe r s ( a d d r es s: 0x1 4 ? 0x 1f ) a ddr . regna m e (reset v a l) signal name wid t h propert y d escripti on [ 7 : 4 ] r r e s e r v e d [ 3 : 2 ] r reserved t i ming loop lock (s y m bol s y nc) [1] t i ming loop has locked t l o c k [ 1 ] r [0] t i ming loop has not locked phase loop lock (carrier s y nc) [1] phase loop h a s locked 0x1 4 monitor01 (0x00 ) plo c k [ 0 ] r [0] phase loop h a s not locked 0x1 5 monitor02 (0x00 ) p r e _ l e v e l [ 7 : 0 ] r pre-ag c gain l e v e l 0x1 6 monitor03 (0x00 ) po s t _ l e v e l [ 7 : 0 ] r po st -a g c gain l e v e l 0x1 7 monitor04 (0x00 ) dc_i_level [7:0] r dc of fset of i sa mples 0x1 8 monitor05 (0x00 ) dc_q_level [7:0] r dc of fset of q sa mples 0x1 9 monitor06 (0x00 ) [ 7 : 0 ] r reserved 0x1 a monitor07 (0x00 ) [ 7 : 0 ] r reserved (0x1b ~ 0x1e ) r e s e r v e d [ 7 ] r e s e r v e d q psk_out [6:1] r q psk output mo nitoring 0x1f monitor12 (0x00 ) dc_free ze [0] r/w [ 1] do not up date dc_offse t (0x20 ~ 0x21 ) r e s e r v e d sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 21 fec con t rol registers ( a d d ress: 0 x22 ) a ddr . regna m e (reset v a l) signal name wid t h propert y d escripti on [ 6 ] r / w set to ?0? [ 5 ] r / w set to ?0? [ 4 ] r / w set to ?0? [ 3 ] r / w set to ?0? tmp=(fm c l k /fsr) ? (1/ ( 2 ? cr )) fmclk: s y stem clock frequenc y fsr: s y m bol ra te, cr: cod e rat e 0: 1 s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 23 mpeg contr o l register s (a d d re ss: 0 x 3 8 ~ 0x3 9) a ddr . regna m e (reset v a l) signal name wid t h propert y d escripti on pac k e t error pol a r i t y e r r _ p o l [ 3 ] r / w [1] active low [0] active high s y nc polarit y s y nc _ p o l [ 2 ] r/w [1] active low [0] active high dat a valid polarity v a l i d _ p o l [ 1 ] r/w [1] active low [0] active high cdclk polarit y [1] falling edge e v ent 0x3 8 mpeg01 (0x00 ) cdclk_p o l [ 0 ] r/w [0] rising edge event [ 6 ] r / w set to ?1? [ 5 ] r/w set to ?1? [ 4 ] r/w set to ?1? clock continuous mode c l k _ c o n t [ 3 ] r/w [1] continuous clock, [0] cloc k is enable duri ng p a y l oa d dat a transfer [ 2 ] r/w set to ?1? serial / parallel mode ser_p a r [ 1 ] r/w [1] serial mode, [ 0 ] parallel mode dss s y nc mode 0x3 9 mpeg02 (0x3 d) dss_s y n c [ 0 ] r/w [1] outp ut s y nc, [ 0 ] no output s y n c diseqc con t rol register s ( a d d r e ss: 0x 3 a ~ 0x 3c) a ddr . regna m e (reset v a l) signal name wid t h propert y d escripti on t one f r equenc y r a tio 0x3 a dis01 (0x01 ) t o ne_ f r e q [ 7 : 0 ] r / w *note: f ton e = f cl k / ( t o ne _fre q 32) diseqc receive enable mode r c v _ e n [ 7 ] r / w [1] receive enable [0] receive disable d i s _ l e n g t h [ 6 : 4 ] r/w m essage l e n g t h dat a t r a n sfer re ad y / finish [1] read y [0] fini sh dis_rd y [ 3 ] r/w *note: the micro p rocessor set to ?1? onl y w hen thi s bit is ?0?. when this bit is ?1?, the slaver is not y e t received message. the slaver is st arting to receive t he signal at the rising edge detection satellite sw itch in tone burst mode s w i c h _ c o n [ 2 ] r/w [1] satellite b [0] satellite a lnb control mod e [0] continuous m ode [1] t one bu rst m ode [2] diseqc mod e 0x3b dis02 (0x00 ) l n b _ c o n [ 1 : 0 ] r/w [3] reserved sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 24 a ddr . regna m e (reset v a l) signal name wid t h propert y d escripti on olf_ n [2] r/w [1] disable [0] olf (active low) lnb_dn [1] r/w [1] lnb do w n [ 0 ] disable (active high) 13v/18v select register 0x3c dis03 (0x04 ) 1 8 v _ 1 3 v [ 0 ] r / w [1] 18v [0] 13v diseqc mes sage re giste r s ( a d d r es s: 0x3d~ 0 x4 4) a ddr . regna m e (reset v a l) signal name wid t h propert y d escripti on lnb message content s 0x3d dis04 (0x00 ) lnb_mesg e0 [ 7 : 0 ] r / w *msb sent first on each b y te 0x3e dis05 (0x3e ) lnb_mesg e1 [ 7 : 0 ] r / w 0x3f dis06 (0x00 ) lnb_mesg e2 [ 7 : 0 ] r / w 0x4 0 dis07 (0x00 ) lnb_mesg e3 [ 7 : 0 ] r / w 0x4 1 dis08 (0x00 ) lnb_mesg e4 [ 7 : 0 ] r / w 0x4 2 dis09 (0x00 ) lnb_mesg e5 [ 7 : 0 ] r / w 0x4 3 dis10 (0x00 ) lnb_mesg e6 [ 7 : 0 ] r / w 0x4 4 dis1 1 (0x00 ) lnb_mesg e7 [ 7 : 0 ] r / w rf slav e register ( a d d r es s: 0x4 5) a ddr . regna m e (reset v a l) signal name wid t h propert y d escripti on 0x4 5 rf01 (0x61 ) sla ve_addr [6:0] r/w rf tune r slave address (soc version ) sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 25 error control register ( a d d ress: 0 x46) a ddr . regna m e (reset v a l) signal name wid t h propert y d escripti on [ 4 ] r / w set to ?1? [ 3 : 2 ] r / w set to ?1? error mo nitoring source [0] q psk bit erro rs [1] v i terbi bit erro rs [2] v i terbi b y te errors 0x4 6 err01 (0x00 ) e r r _ s r c [ 1 : 0 ] r / w [3] packet errors error monito ring registe r s ( a d d r e ss: 0 x47- 0x4 9) a ddr . regna m e (reset v a l) signal name wid t h propert y d escripti on 0x4 7 err02 (0x00 ) err_cn t_l [7:0] r error count er value register (lsb 8 bit s ) 0x4 8 err03 (0x00 ) err_cn t_h [7:0] r error count er value register (msb 8 bit s ) 0x4 9 err04 (0x00 ) p a rit y _err [7:0] r error flag fo r dis e qc receive dat a sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 26 5. electe rical characte r istics 5.1 absolu te maximum ratings sy m b o l p a r a m e t e r rang e u n i t v cc dc su pply voltage -0.3 to 4.6 v v in 3.3v input voltage -0.3 to v dd +0. 3 v i in dc 3.3v inp u t current +/- 10 ma t stg s t orage t e m perature -40 to +125 oc t opr ope r ation t e mperature 0 to +70 oc 5.2 rec o mmended op era t ing conditio n s sy m b o l p a r a m e t e r rang e u n i t v cc dc su pply v o lt age 3.0 to 3.6 v t j jun c tion t e m perature max 125 oc t r thermal resi st an ce 45 oc /w v in dc input 0 to v cc v v out output v o lt ag e 0 to v cc t lt lead t e m perature (sol de ri ng 10 sec) 300 oc 5.3 dc ele c tr ical charac te ristics (v dd = 3.3+/-10%, ta = - 4 0(c ~ -8 5 ( c , un l e ss ot he r w i s e speci fi ed ) sy m b o l d e s c r i p tio n t e s t co nd itio n min t y p max un i t vc c 3 3 i / o su p p l y v o l t a g e 3. 0 3. 3 3. 6 v vc c 2 5 i n t e r n al s u ppl y v o l t a g e 2. 2 2. 5 2. 7 v al l i n out 0. 7 vd d v i h i n p u t v o ltag e l o w r s t _n, s _ cl k - - 2. 1 v all in pu t 0 . 3 v d d - - v v i l i n p u t v o ltag e high r s t _n, s _ cl k 0. 8 - - ii h hi g h le vel i n p u t c u rre nt vi n = v d d - 10 - + 10 ua i il low l e vel input cu rre nt v in = v ss - 1 0 - + 1 0 u a v ol output lo w voltage i ol = 8ma - - 0.4 v v oh output hig h voltage i oh = -6ma 2.4 - v dd v i oz 3-state outp ut leakage cu rre nt v oh = v ss or v dd - 1 0 - + 1 0 u a i cc dynami c sup p ly current f in = 4.0mhz, v dd = 3.6v - - t b d m a 5.4 a/d conv erte r (v cc25 = 2.5+/-5%, ta = -4 0( c ~ -8 5(c , unl e ss ot her w i s e s p eci fi ed) sy m b o l d e s c r i p tio n t e s t co nd itio n min t yp max un it vref-h refe ren c e vo ltage hig h input vref-h valu e 1.5 1.6 1.7 v vref-l refe ren c e vo ltage lo w inp u t v ref-l val u e 0.8 0.9 1.0 v ain analog inp u t (ip/in/qp/qn) (vref - h)-(v r ef-l) 0.5 0.7 0.9 vpp cml comm on mo de level cml o u tput - 1.25 - 7 i dd 45m average v dd_ 2.5v curre n t v dd=2.6 v = 59mh z - - ma i dd 45m average v dd_ 2.5v curre n t v dd=2.6 v = 88mh z - - ma ine integral li nea rity error f in =30m hz, f s =90m h z - - ? 1.0 db dle differe ntial li nea rity error f in =30m hz, f s =90m h z - - ? 2.0 db off offset erro r voltage f in =30m hz, f s =90m h z - ? 1.0 - d b gain gain error vo ltage f in =30m hz, f s =90m h z - ? 2.0 - d b sndr signal to noi s e & disto r tion rat i o f in =30m hz, f s =90m h z - 3 2 - 3 0 - 2 8 d b fin analog inp u t band width - - 30 mhz f s s a m p l i n g f r e quen c y - - 9 0 mhz sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 27 5.5 timing charac teris t ic s cl k_ o u t d [ 7: 0] , d / p st r_ o u t , error t cksu t ckh fi gur e 6 fi g u r e 8 t cks u t ckh cl k _ out d [ 7: 0] , d / p st r _ o u t , er ro r fi g u r e 7 t cksu t ckh cl k _ o u t d [ 7: 0] , d / p st r _ o u t , err o r cl k_ out d [ 7: 0] , d / p st r_ o u t , e rror t ck su t ck h fi g u r e 9 s y m b ol p a r a m e t e r m i n t y p m a x u n i t f vc o i n t e r n a l v c o f r e que nc y 300 40 0 m h z f cl k _ i n c l k _ i n o r x t a l f r eq uenc y 4 30 m h z pa r a l l e l ou tp u t d [ 7 : 0 ] , d/ p , cl k _ o u t , s t r_ ou t , e r r o r ou t p u t c h a r ac t e r i t i cs b i t rs= 1 i n rs c o ntro l re g i s t e r ( a d d r e s s 3 3 ) . r e f e r t o f i g u r e 6 t cl k _ du t y c l k _ o u t duty c y c l e 40 50 60 % t cks u d[ 7 : 0 ] , d / p , s t r_ o u t , e rro r s t a b l e b e f o r e c l k _ o u t f a l l i n g e dge 2* t m ( 1 ) ns t ck h d [ 7: 0] , d / p , s t r _ o u t , e r r o r s t abl e a f t e r c l k _ o u t f a llin g e d g e 2* t m ( 1 ) ns b i t rs= 0 i n rs c o ntro l re g i s t e r ( a d d r e s s 3 3 ) . r e f e r t o f i g u r e 7 t cks u d[ 7 : 0 ] , d / p , s t r_ o u t , e rro r s t a b l e b e f o r e c l k _ o u t f a l l i n g e dge 2* t m ( 1 ) ns t ck h d [ 7: 0] , d / p , s t r _ o u t , e r r o r s t abl e a f t e r c l k _ o u t f a llin g e d g e 2* t m ( 1 ) ns s e r i a l o u tp u t d[ 7 : 0 ] , d/ p , cl k _ o u t, s t r_ o u t , e r r o r o u t p u t c h a r a c te ri t i cs b i t rs= 1 i n rs co ntro l re gi s t e r ( a d d r e s s 3 3 ) . f clk = 9 0 m h z . r e f e r to f i g u r e 8 t cks u d[ 7 : 0 ] , d / p , s t r_ o u t , e rro r s t a b l e b e f o r e c l k _ o u t f a l l i n g e dge 3. 5 ns t ck h d [ 7: 0] , d / p , s t r _ o u t , e r r o r s t abl e a f t e r c l k _ o u t f a llin g e d g e 2 ns b i t rs= 0 i n r s co ntro l re g i s t e r ( a d d r e s s 3 3 ) . f cl k = 90m h z . r e f e r t o f i gure 9 t cks u d[ 7 : 0 ] , d / p , s t r_ o u t , e rro r s t a b l e b e f o r e c l k _ o u t f a l l i n g e dge 3. 5 ns t ck h d [ 7: 0] , d / p , s t r _ o u t , e r r o r s t abl e a f t e r c l k _ o u t f a llin g e d g e 2 ns sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 28 5.6 i 2 c bus c h arac teris t ic s s y mbol p a r a me te r t e s t co ndi ti on s m in t y p m a x u n i t v il v ih low lev el input vol t age h i gh lev el input voltage pull up to 5v 10% - 0.5 2.0 0.8 5.5 v v v oh v ol h i g h lev el output voltage low lev el output v o ltage pull up to 5v 10% 5.5 0.4 v v i lk input leak age cur r ent vin = 0v to 5v - 1 0 1 0 u a c in input c apacitance 0 3.5 p f i ol output s i nk c u rrent vol = 0.5v 10 m a f sc l n f sc l s sc l c l oc k f r e quenc y n orm a l mode standby mode 0 0 f m_c l k /40 f m_c l k /10 _ _ t bu f bus f r ee t i m e betw een a s t op and st ar t condit i on 1.3 u s t hd , s t a h o l d t i m e (r e peated)st ar t conditi on. af ter this per i od, the f i rs t c l oc k pul s e is generated 0.6 u s t low t hi g h low period of the sc l c l oc k h i gh period of the scl cloc k 1.3 0.6 us us t su ,s t a setup t i m e f o r a repeated st ar t conditi on 0.6 u s t su ,sto setup t i m e f o r st op c ondi tion 0.6 u s t su ,d at d a ta setup t i m e 100 ns t r , t f r i s e and f a ll t i m e of both sd a and sc l s i gnals 300 ns c b capac itiv e l oad f o r eac h bus line 400 pf i 2 c bus timing diagram u # 6 ' u - 0 8 u 3 u ' u ) % 4 5 " u 4 6 % " 5 u 4 6 4 5 " u 4 6 4 5 0 4 % " 4 $ - u ) * ( ) u ) % 4 5 " u 4 1 u ) % % " 5 sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 29 6. application examp les # applicati on example (w i t h dv b-s i/q tuner) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 vs s2 5 d ln b _ e n v d d 25d vs el ag c err o r sy n c vali d av bb _ p l l av s s _ p l l avd d _ p l l ol f vs s3 3 scl sd a av s s _ p l l vd d2 5 vd d2 5 vs s2 5 dat a 0 dat a 1 vs s2 5 vs s3 3 in av dd _ a d c rf s c l f m h z cl ko u t vd d 3 3 da t a 7 di s e q c t e st _ s el 1 rf s d a vd d 2 5 nc dat a 2 dat a 3 dat a 4 dat a 5 da t a 6 nc av bb _ a d c av ss _a dc ip avdd _a dc qn av ss _a dc qp cm l vref_ l vre f _ h id _ s el 0 id _ s el 1 vs s2 5 vdd 2 5 xt a l _ o u t xt a l _ i n t e st _ s el 0 vs s2 5 vd d 3 3 cl k_ s e l 1 2 3 4 5 6 7 8 9 1 0 1 11 2 1 31 4 1 5 1 6 48 47 46 45 4 4 43 42 41 40 3 9 38 37 36 35 3 4 33 by t e _ c l k res e t _ n a d c_osc_i n S5H1420 (64 l qfp-1 010) $ . - 7 3 & ' @ ) 7 3 & ' @ - $ q ' $ q ' . ) [ 7 3 & ' @ ) 7 3 & ' @ - 3 ? 3 ? 3 ? $ o ' $ o ' 3 l? 3 l? 7 @ % 7 @ " lnbp sm p s 7 @ % 7 % % 7 % % @ % 7 % % @ " 7 4 4 @ % 7 4 4 @ " mpe g 2 se rial in terfac e mpe g 2 pa r a llel inter f ace $ o ' 3 l ? 3 l? $ o ' $ o ' $ o ' 3 l ? 3 l ? $ . - av dd _ p l l $ . - $ . - 3 .? 3 ? 3 ? 3 ? 3 ? 4 b u f m m j u f e j t i , ) [ " ( $ 3 ' 4 % " 3 ' 4 $ - * 1 2 1 dat a 7 sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 30 7. package dimension #64 note : dimensions are in millimeters. 10.00 12.00 + 0.20 10.00 12.00 + 0.20 #1 0.50 0.127 + 0.073 - 0.037 0.45 - 0.75 0.05 min 1.40 + 0.05 1.60 max 0.20 + 0.07 - 0.03 0.08 max m 0.08 max 0-7 0.25typ sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation s5h 1 420 dbs channel dec o der for dvb-s/ d ss - - 31 8. dat a sh ee t up date histor y - 200 4-0 1 -05 : rele ase v e rsion : 4.5 add chapter : 3.4.8 s pectrum inverse of code rate 5/6 (page 10 ). add chapter : 3.4.9.3 mpeg clo ck co ntrol (pa g e 1 2 ) . change regi ster map : ) j e f v o o f d f t t b s z s f h j t u f s ' j f m e u p v t f s (pa g e 1 6 ) . - 200 4-0 1 -10 : rele ase v e rsion : 4.5.1 upda te ch ap ter : 3.2.2 l o op equ ation (page 7). upda te ch ap ter : 3.3.1 l o op equ ation (page 7). upda te ch ap ter : 3.4.9.2 serial outp u t interfa c e (pa g e 10). upda te ch ap ter : 3.4.9.3 m p eg c l ock c ont r o l (pa g e 12 ). samsung electr onics co , ltd. www . s am su ng.com t : 82-31-279 -76 4 0 su w o n p . o.box 41 6 ma et an -3don g, y oungt ong-gu, su w o n - s i, g y eonggi-do, korea 4 4 2 -7 42 sa m s ung elect r onics co, ltd. p r opriet ary inf o rm ation |
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