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? 1 ? e02y23a35 sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXA7004R 48 pin lqfp (plastic) description the CXA7004R is a driver ic developed for use with sony polycrystalline silicon tft lcd panels. it supports 12-bit digital input, and the input data is demultiplexed into 6 phases and output. the CXA7004R can directly drive an lcd panel, and the vcom setting circuit and precharge pulse waveform generator are also on-chip. features ? supports 12-bit input low output deviation various adjustment functions using a 3-wire serial interface supports signals up to xga supports dot and line inversion vcom voltage generation circuit precharge pulse waveform generation circuit applications lcd projectors and other video equipment absolute maximum ratings (v ss = 0v) supply voltage v cc 16 v v dd 5v operating temperature topr ?20 to +70 c storage temperature tstg ?65 to +150 c allowable power dissipation p d 1200 mw recommended operating conditions supply voltage v cc 15.0 to 15.5 v v dd 3.0 to 3.6 v operating temperature topr ?20 to +70 c lcd driver
? 2 ? CXA7004R block diagram d_in1 d_in2 d_in3 d_in4 d_in5 d_in8 d_in9 d_in10 d_in11 d_in0 d_in7 d_in6 clk frp prg dirc dgnd v dd agnd agnd agnd status v cc frinv pv cc vcom_out sig_out6 sig_out5 sig_out4 sig_out3 sig_out2 sig_out1 sid_out pv cc pgnd pgnd addr0 addr1 ref_in ref_out agnd agnd v cc senb sclk sdat sif tg sid dc_gen d/a d/a d/a d/a d/a d/a driver ref d/a driver driver driver driver driver digital dgnd dgnd 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 48 47 46 45 44 43 42 41 40 39 38 37
? 3 ? CXA7004R pin description symbol equivalent circuit pin no. description i/o standard voltage level senb enable input for 3-wire serial interface. data is written only while this pin is low. i high: 2.0v low: 0.8v 3 sclk clock input for 3-wire serial interface. supports a clock from 100khz to 1mhz. i high: 2.0v low: 0.8v 4 sdat data input for 3-wire serial interface. i high: 2.0v low: 0.8v 5 addr0 addr1 ic address setting for 3-wire serial interface. addresses from 0h to 7h can be set by changing this setting. i high = v dd low = gnd 6 7 v dd 1k gnd 3 v dd 1k gnd 4 v dd 1k g nd 5 v dd 20k g nd 6 7 40k 40k v cc gnd 10 8k 8k 25 16 k 16k 12.5 36k 145 2k ref_in reference voltage (signal center) input. when using multiple CXA7004Rs, connect to ref_out that differs from the reference. i 6.0v 10
? 4 ? CXA7004R symbol equivalent circuit pin no. description i/o standard voltage level ref_out signal center voltage (inversion folded voltage) output. when using multiple CXA7004Rs, connect to ref_in through a 1k ? resistor. o 6.0v 12 v cc g nd 1 2 145 2k 2k 124k vcom_out common voltage output of lcd panel. adjustment is possible by the 3-wire serial interface setting. o 5.5 to 7.5v demultiplexed output of ac inverse driven video signals. can be directly connected to the lcd panel. o 1.5 to 13.5v sid_out precharge waveform output. adjustment is possible by the 3-wire serial interface setting. this pin cannot directly drive the lcd panel, so input to the lcd panel through a buffer. o 1.5 to 13.5v frinv input for switching the output polarity to inverted or non-inverted relative to the lcd panel ac drive inversion timing (frp) pulse. i high: 2.0v low: 0.8v v cc 1k gnd 1 3 1k 500 145 500 v cc pv cc gnd pgnd 16 15 17 21 20 22 400 400 400 v cc pv cc g nd pgn d 24 145 400 v dd 20k g nd 29 13 15 16 17 20 21 22 24 29 sig_out6 to sig_out1
? 5 ? CXA7004R symbol equivalent circuit pin no. description i/o standard voltage level status master/slave setting when using two CXA7004Rs. when set high, this chip operates as the master ic; when set low, this chip operates as the slave ic. when using only one CXA7004R, leave this pin open. i high: 2.0v low: 0.8v v dd 20k gnd 30 30 dirc scan direction setting. the scan direction is set in combination with the 3-wire serial interface setting dircr. i high: 2.0v low: 0.8v 31 prg timing pulse input for switching the pin 24 (sid_out) output level. this pin is also used as the circuit reset pulse. i high: 2.0v low: 0.8v 32 frp lcd panel ac drive inversion timing input. high: inverted low: non-inverted i high: 2.0v low: 0.8v 33 clk dot clock input. the polarity is determined by the 3-wire serial interface setting ckpol. high: reverse polarity low: positive polarity i high: 2.0v low: 0.8v 34 v dd 20k g nd 31 v dd 1k g nd 32 v dd 1k gnd 33 v dd 1k gnd 34
? 6 ? CXA7004R symbol equivalent circuit pin no. description i/o standard voltage level d_in11 to d_in0 digital data input. d_in0: lsb d_in11: msb i high: 2.0v low: 0.8v 37 to 48 v dd 1k gnd 48 37 to v dd v cc pv cc dgnd agnd pgnd 3.3v power supply. 15v power supply. power v cc . gnd. gnd. power gnd. 3.3v 15.5v 15.5v dgnd agnd pgnd 35 11, 25 14, 23 1, 2, 36 8, 9, 26, 27, 28 18, 19
? 7 ? CXA7004R electrical characteristics measurement circuit 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 d_in9 d_in8 d_in7 d_in6 d_in5 d_in4 d_in3 d_in2 d_in1 d_in0 d_in10 d_in11 250pf 250pf 250pf 250pf 250pf 250pf a 47pf a a v dd v dd pv cc 15.25v v cc 15.25v v dd 3.3v clk frp prg dirc dgnd v dd agnd agnd agnd status v cc frinv pv cc vcom_out sig_out6 sig_out5 sig_out4 sig_out3 sig_out2 sig_out1 sid_out pv cc pgnd pgnd addr0 addr1 ref_in ref_out agnd agnd v cc senb sclk sdat dgnd dgnd
? 8 ? CXA7004R electrical characteristics (ta = 50c) item symbol measurement description digital input resolution digital input setup time 1 digital input setup time 2 digital input hold time 1 digital input hold time 2 clk input frequency range 1 clk input frequency range 2 sig_out output voltage range sig_out output amplitude adjustable range sig_out slew rate sig_out offset adjustable range signal center adjustable range sid amplitude adjustable range 1 sid amplitude adjustable range 2 vcom adjustable range v dd current consumption v cc current consumption 2 n ts1 ts2 th1 th2 f clk1 f clk2 v sigout v sigoutpp sr out v ofst v sig a sid1 a sid2 vcom i dd i cc ckpol: 3.3v, prg and d_in[11:0] setup time relative to clk input. ckpol: 0v, prg and d_in[11:0] setup time relative to clk input. ckpol: 3.3v, prg and d_in[11:0] hold time relative to clk input. ckpol: 0v, prg and d_in[11:0] hold time relative to clk input. sldat: 3.3v, maximum frequency at which the internal timing generator and d/a converter operate normally. sldat: 0v, maximum frequency at which the internal timing generator and d/a converter operate normally. output voltage range of sig_out1 to sig_out6. gain control: 00h, measure the sig_out voltage difference at d_in[11:0] = 000h and fffh. load capacitance c = 270pf; measure the slew rate at 10 to 90% of sig_out1 to sig_out6 rise and fall when d_in[11:0] is varied from 000h to fffh or from fffh to 000h. offset adjustable range of sig_out1 to sig_out6 by bright control. signal center voltage adjustable range when sig center is varied. sid_out amplitude adjustable range by sid control a. sid_out amplitude adjustable range by sid control b. vcom_out adjustable range relative to signal center voltage when vcom control is varied. clk = 80mhz, v dd current consumption. clk = 80mhz, inversion signal every d_in = 000h, frp = 60clk, v cc + pv cc current consumption when sig_out load capacitance = 250pf. no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 min. typ. max. unit 12 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 100 80 13.5 6 ? 1.175 8.625 6 6 0 28 68 bit ns ns ns ns mhz mhz v v v/s v v v v v ma ma ? 0 0.5 2.5 2 ? ? 1.5 2 170 0 6.375 0 0 ?2 23 38
? 9 ? CXA7004R item symbol measurement description output deviation between sig_out channels 1 output deviation between sig_out channels 2 output deviation between sig_out ics 1 output deviation between sig_out ics 2 maindac differential linearity error d out1 d out2 d ic1 d ic2 dle d_in[11:0] = 7ffh, value obtained by subtracting minimum value from maximum value of sig_out1 to sig_out6 output at gain control = bfh. d_in[11:0] = 000h or fffh, value obtained by subtracting minimum value from maximum value of sig_out1 to sig_out6 at gain control = bfh. d_in[11:0] = 7ffh, value obtained by subtracting minimum value from maximum value of sig_out1 to sig_out6 at gain control = bfh. d_in[11:0] = 000h or fffh, value obtained by subtracting minimum value from maximum value of sig_out1 to sig_out6 at gain control = bfh. maindac differential linearity error no. 18 19 20 21 22 min. typ. max. unit ? ? ? ? ? 2 10 2 10 1 mv mv mv mv lsb ? ? ? ? ?1
? 10 ? CXA7004R 3-wire serial interface the CXA7004R makes the various register settings using a 3-wire serial interface. up to 8 ic addresses can be designated by the addr0 and addr1 (pins 6 and 7) settings, and these settings can be adjusted individually. the relationship between the ic address and addr0 and addr1 is shown below. in addition, the adjustable settings include the mode settings, gain, offset, signal center voltage, precharge, and common voltage (vcom) settings. (see the register function setting table.) ac characteristics (topr = ?20 to +75c, v dd = 3.3 0.3v, v ss = 0v) timing definition max. ? ? ? ? min. 100 100 100 100 ty p. ? ? ? ? symbol tes teh tds tdh item senb setup time relative to the rising edge of sclk senb hold time relative to the rising edge of sclk sdat setup time relative to the rising edge of sclk sdat hold time relative to the rising edge of sclk unit ns ns ns ns v dd senb tes teh tdh tds sclk sdat v ss v dd v ss v dd v ss enable high ykfvj 400ns qtoqtg
? 11 ? CXA7004R input format write designation byte write designation byte data dummy data senb sclk sdat 0d2d1d00 reg addr2 reg addr1 reg addr0 senb sclk sdat ic address register address input format and initialization the 3-wire serial interface input format is shown below. the minimum configuration is the 3 bytes of one write designation byte, one data byte, and one dummy data byte. in addition, the register address is automatically incremented by the number of input data. initialization this ic must initialize the registers before setting the registers. write "1" to register address (00h) reset after power is turned on. this setting initializes this ic. after initialization, register setting is performed by returning reset to "0". when initialization is not performed, the setting value of a register may not be reflected correctly. external pin l l l c c h h h l c h l h l c h ic address 0 1 2 3 4 5 6 7 addr1 addr0 d2 l l l l h h h h d1 l l h h l l h h d0 l h l h l h l h ic address for serial interface l: gnd c: 1/2v dd or open h: v dd ic address definition
? 12 ? CXA7004R register function setting table d2 sidon sigc2 g2 b2 vc2 sida2 sidb2 d1 prpol sigc1 g1 b1 vc1 sida1 sidb1 d0 ckpol sigc0 g0 b0 vc0 sida0 sidb0 d5 slinv sigc5 g5 b5 vc5 sida5 sidb5 d4 fhcnt sigc4 g4 b4 vc4 sida4 sidb5 d3 dircr sigc3 g3 b3 vc3 sida3 sidb3 d7 reset g7 b7 d6 sidat g6 b6 vc6 sida6 sidb6 function mode sig center gain control bright control vcom control sid control a sid control b reg addr 00 01 02 03 04 05 06 mode: various function settings sig center: signal center voltage setting gain control: voltage amplitude setting between sig_out white and black levels bright control: offset adjustment from sig_out signal center voltage vcom control: vcom voltage setting sid control a: precharge signal voltage setting a sid control b: precharge signal voltage setting b
? 13 ? CXA7004R description of operation the flow of internal operations is described below. the digital signals input to d_in0 to d_in11 are internally demultiplexed into 6 phases, and then data processed according to the various mode settings. after that, the signals are d/a converted into analog signals for each channel, amplified at the rear end, and output. the output level relative to the output level setting changes according to the following settings. a: register gain control setting b: register bright control setting c: signal center voltage signal center voltage adjustment (c) the signal center voltage is determined by the register setting sig center. the signal center voltage can be adjusted in 35mv/lsb steps from 00h: 6.5v to 3fh: 8.5v. offset adjustment relative to the signal center voltage (b) the output voltage at digital input fffh is determined by the sig_c voltage and the register setting bright control. the offset relative to the signal center voltage can be adjusted in 4mv/lsb steps from 00h: sig_c 0.2v to ffh: sig_c 1v. white-black amplitude gain adjustment (a) the white-black voltage amplitude when the digital input is varied from 000h to fffh is determined by the register setting gain control in the condition with the white level fixed. the gain relative to the signal center voltage can be adjusted in 16mv/lsb steps from 00h: sig_c 2v to ffh: sig_c 5.5v. 4 095 2 048 0 b b a a c digital in sig_out
? 14 ? CXA7004R other settings are as follows. mode setting the CXA7004R can be set to master/slave mode, single mode, and right/left inversion, etc. this makes it possible to support various systems. (various mode setting is designated with register and external pins.) the various operating modes are described below. operating mode setting the digital input of two ics can be used together in master/slave mode by setting the mode setting: sldat to high level, or single mode can be set by setting sldat to low level. in master/slave mode, the 12-bit input is shorted between the two ics, and the odd or even data is selected by status (pin 30), dirc (pin 31) and the mode setting: dircr. input a clock having the same period as the input data rate to clk (pin 34) in both modes. sldat: l sig_out1: 1 sig_out2: 2 sig_out3: 3 sig_out4: 4 sig_out5: 5 sig_out6: 6 sig_out1: 6 sig_out2: 5 sig_out3: 4 sig_out4: 3 sig_out5: 2 sig_out6: 1 sldat: h sig_out1: 2 sig_out2: 4 sig_out3: 6 sig_out4: 8 sig_out5: 10 sig_out6: 12 sig_out1: 11 sig_out2: 9 sig_out3: 7 sig_out4: 5 sig_out5: 3 sig_out6: 1 sig_out1: 1 sig_out2: 3 sig_out3: 5 sig_out4: 7 sig_out5: 9 sig_out6: 11 sig_out1: 12 sig_out2: 10 sig_out3: 8 sig_out4: 6 sig_out5: 4 sig_out6: 2 dirc ex-or dircr: h dirc ex-or dircr: l status: l status: h clock polarity setting the polarity of the internal circuit operation clock (mclk) is determined by the mode setting: ckpol. the internal circuits operate at reverse polarity from clk when ckpol is high, and at the same polarity as clk when ckpol is low. 123456789101112131415 input data d_in[11:0]
? 15 ? CXA7004R horizontal sync timing the horizontal sync signal prg is also used as the internal circuit reset function. the mode setting: prpol sets whether to apply the reset at the rising edge or the falling edge of prg. the reset is applied at the rising edge of the prg pulse when prpol is high, and at the falling edge of the prg pulse when prpol is low. output phase setting the sig_out output timing phase can be set by the mode setting: fhcnt. when fhcnt is low, all sig_out outputs are output at the same timing. when fhcnt is high, sig_out1 to sig_out3 and sig_out4 to sig_out6 are output at phases offset by 1/2 clock period from each other. polarity setting output polarity inversion/non-inversion relative to the signal center voltage is set by the frp input and the external pin frinv (pin 29). when set to the combinations shown in the table below, sig_out is output non- inverted (solid line) or inverted (dotted line) relative to frp. frinv: h non-inverted inverted frp: h frp: l frinv: l inverted non-inverted frp sig_c sig_out gnd inverted non-inverted prg mclk reset pulse prpol: h prpol: l sig_out4 to 6 sig_out1 to 3 gnd sig_out4 to 6 sig_out1 to 3 gnd fhcnt: l fhcnt: h
? 16 ? CXA7004R dot inversion and line inversion mode setting when mode setting: slinv is set to low level, all sig_out channels are output at the same polarity as shown by the solid line in the figure below. when set to high level, the odd-numbered and even-numbered sig_out outputs are output at inverse polarities. at this time the odd-numbered outputs are inverted when the frp pulse is high, and non-inverted when the frp pulse is low. conversely, the even-numbered outputs are inverted when the frp pulse is low, and non-inverted when the frp pulse is high. frp sig_c sig_out gnd inverted non-inverted
? 17 ? CXA7004R master/slave mode d_in clk prg prg_x enb_f enb_f cnt6 sout1 sout2 sout3 sout4 sout5 sout6 fhcnt: l stb1_3 stb4_6 stb1_3 stb4_6 fhcnt: h enb rclk cnt6 sout1 sout2 sout3 sout4 sout5 sout6 fhcnt: l stb1_3 stb4_6 stb1_3 stb4_6 fhcnt: h enb rclk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 113 315 517 719 921 11 23 45 214 416 618 820 10 22 12 24 status: h dirc ex-or dircr: h status: l
? 18 ? CXA7004R master/slave mode d_in clk prg prg_x enb_f enb_f cnt6 sout1 sout2 sout3 sout4 sout5 sout6 fhcnt: l stb1_3 stb4_6 stb1_3 stb4_6 fhcnt: h enb rclk cnt6 sout1 sout2 sout3 sout4 sout5 sout6 fhcnt: l stb1_3 stb4_6 stb1_3 stb4_6 fhcnt: h enb rclk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 12 24 10 22 820 618 416 214 45 11 23 921 719 517 315 113 status: h dirc ex-or dircr: l status: l
? 19 ? CXA7004R single mode d_in clk prg prg_x cnt6 sout1 sout2 sout3 sout4 sout5 sout6 fhcnt: l stb1_3 stb4_6 stb1_3 stb4_6 fhcnt: h enb, enb_f cnt6 sout1 sout2 sout3 sout4 sout5 sout6 fhcnt: l stb1_3 stb4_6 stb1_3 stb4_6 fhcnt: h enb, enb_f 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 0 6121824 0 1 7131925 1 2 8142026 2 3 9152127 3 4 10 16 22 28 4 5 11 17 23 29 5 4 5 d ir (dirc ex-or dircr): h d ir (dirc ex-or dircr) : l
? 20 ? CXA7004R sid signal generator block this circuit generates the precharge signal waveform used by the lcd panel. the sid_out output level switching function is set on and off by the mode setting (d2): sidon. when sidon is low level, adjustment uses only the register setting: sid control a. when sidon is high level, adjustment is possible using both the register settings: sid control a and sid control b. in addition, the sid_out output level relative to the signal center voltage can be set by the register settings: sid control a and sid control b. adjustment is possible in 50mv/lsb steps from 00h: sig_c 5.5v to 7fh: sig_c 0.1v for both settings. sid_out cannot directly drive the precharge signal input of the lcd panel, so it should be connected through a buffer having sufficient current supply capability. vcom voltage generator block this block sets the dc common potential for the lcd panel. the sig_out center potential set by the sig_c voltage can be adjusted by the register setting vcom control. adjustment is possible in 17.5mv/lsb steps from 00h: sig_c ? 2v to 7fh: sig_c ? 0.1v. sidon: h adjusted by sida6 to sida0 adjusted by sidb6 to sidb0 sidon: l adjusted by only sida6 to sida0 sid_out sig_c
? 21 ? CXA7004R example of representative characteristics (v cc = 15.25v, v dd = 3.3v, ta = 25c) sigc control characteristics sigc control code (dec) sig_out [v] 0 6.0 6.5 7.0 7.5 8.0 8.5 9.0 60 50 40 30 20 10 gain control characteristics gain control code (dec) sig_out amplitude [v] 1.0 1.5 2.5 2.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 250 200 150 100 50 0 bright control characteristics bright control code (dec) inversion sig_out [v] 50 100 150 200 250 0 6.0 6.5 7.0 7.5 8.0 8.5 9.0 vcom control characteristics vcom control code (dec) vcom_out [v] 0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 120 100 80 60 40 20 sid control characteristics sid control code (dec) sid_out [v] 20 40 60 80 100 120 0 0 1.0 0.5 2.0 1.5 2.5 3.5 3.0 4.5 4.0 6.0 5.5 5.0 7.0 6.5 7.5 8.0 d_in sig_out characteristics d_in code (dec) non-inverted sig_out [v] 1000 500 1500 2000 2500 3000 3500 4000 0 0 1 3 2 4 6 5 9 10 8 7 11 12 13 d_in: fffh sigc: 00h to 3fh bright: 00h d_in: fffh sigc: 20h bright: 00h to ffh sigc: 20h sid a: 00h to 7fh sid b: 00h to 7fh d_in: 000h to fffh sigc: 20h gain: bfh bright: 00h gain: 00h to ffh vcom: 00h to 7fh inversion non-inversion non-inversion
? 22 ? CXA7004R maindac dle characteristics d_in code (dec) dle ?1.0 ?0.4 ?0.6 ?0.8 ?0.2 0 0.2 0.8 0.6 0.4 1.0 d_in: 000h to fffh 500 1000 1500 2000 2500 3000 3500 4000
? 23 ? CXA7004R application circuit 1 ? application circuit to svga panel 20k ? 0.1f 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 d_in9 d_in8 d_in7 d_in6 d_in5 d_in4 d_in3 d_in2 d_in1 d_in0 d_in10 d_in11 v cc 15.5v pv cc 15.5v v dd 3.3v clk frp prg dirc dgnd v dd agnd agnd agnd v cc frinv status pv cc vcom_out sig_out6 sig_out5 sig_out4 sig_out3 sig_out2 sig_out1 sid_out pv cc pgnd pgnd addr0 addr1 ref_in ref_out agnd agnd v cc senb sclk sdat dgnd dgnd micro- controller fb fb 47f/35v fb lcd panel (svga) dsd cxd3531r fb com vsig6 vsig5 vsig4 vsig3 vsig2 vsig1 psig d_in9 d_in8 d_in7 d_in6 d_in5 d_in4 d_in3 d_in2 d_in1 d_in0 d_in10 d_in11 clk frp prg rgt 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? buffer 20k ? 0.1f 20k ? 0.1f 20k ? 0.1f CXA7004R 0.1f 47f/35v 0.1f 47f/35v 0.1f 47f/35v 1k ? 0.1f 0.1f application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 24 ? CXA7004R application circuit 2 ? application circuit to xga panel 20k ? 0.1f 20k ? 0.1f 20k ? 0.1f d_in9 d_in8 d_in7 d_in6 d_in5 d_in4 d_in3 d_in2 d_in1 d_in0 d_in10 d_in11 v cc 15.5v pv cc 15.5v v dd 3.3v clk frp prg dirc dgnd v dd agnd agnd agnd v cc frinv status pv cc vcom_out sig_out6 sig_out5 sig_out4 sig_out3 sig_out2 sig_out1 sid_out pv cc pgnd pgnd addr0 addr1 ref_in ref_out agnd agnd v cc senb sclk sdat dgnd dgnd micro- controller fb fb fb lcd panel (xga) dsd cxd3531r fb com vsig11 vsig9 vsig7 vsig5 vsig3 vsig1 psig d_in9 d_in8 d_in7 d_in6 d_in5 d_in4 d_in3 d_in2 d_in1 d_in0 d_in10 d_in11 clk frp prg rgt 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? buffer 20k ? 0.1f 20k ? 0.1f 20k ? 0.1f 20k ? 0.1f 20k ? 0.1f d_in9 d_in8 d_in7 d_in6 d_in5 d_in4 d_in3 d_in2 d_in1 d_in0 d_in10 d_in11 clk frp prg dirc dgnd v dd agnd agnd agnd v cc frinv status pv cc vcom_out sig_out6 sig_out5 sig_out4 sig_out3 sig_out2 sig_out1 sid_out pv cc pgnd pgnd addr0 addr1 ref_in ref_out agnd agnd v cc senb sclk sdat dgnd dgnd micro- controller fb fb vsig12 vsig10 vsig8 vsig6 vsig4 vsig2 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? CXA7004R CXA7004R 47f/35v 0.1f 47f/35v 0.1f 47f/35v 0.1f 47f/35v 0.1f 47f/35v 0.1f 47f/35v 0.1f 1k ? 0.1f 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 25 ? CXA7004R sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin copper alloy package structure 48pin lqfp (plastic) 9.0 0.2 ? 7.0 0.1 1 12 13 24 25 36 37 48 (0.22) 0.18 ? 0.03 + 0.08 0.2g lqfp-48p-l01 p-lqfp48-7x7-0.5 (8.0) 0.5 0.2 0.127 ? 0.02 + 0.05 a 1.5 ? 0.1 + 0.2 0.1 palladium plating note: dimension ? ? ? does not include mold protrusion. 0.1 0.1 0.5 0.2 0? to 10? detail a 0.13 m 0.5 s s b detail b : palladium 0.127 0.04 0.18 0.03 sony corporation package outline unit: mm

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