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ht49ru80/ht49cu80 lcd type 8-bit mcu rev. 1.40 1 july 30, 2012 features operating voltage: f sys =4mhz: 2.2v~5.5v f sys =8mhz: 3.3v~5.5v 8 input lines and 7 output lines 16 bidirectional i/o lines two external interrupt inputs one 8-bit and two 16-bit programmable timer/event counters with pfd - programmable frequency divider function lcd driver with 48 2, 48 3or47 4 segments 16k 16 program memory 576 8 data memory ram real time clock - rtc rtc 8-bit prescaler watchdog timer buzzer output on-chip crystal, rc and 32768hz crystal oscillator halt function and wake-up feature reduce power consumption 16-level subroutine nesting uart - universal asynchronous receiver transmitter bit manipulation instruction 16-bit table read instruction up to 0.5 s instruction cycle with 8mhz system clock 63 powerful instructions all instructions executed within 1 or 2 machine cycles low voltage reset/detector functions 64/100-pin lqfp packages general description these devices are 8-bit, high performance, risc archi - tecture microcontrollers specifically designed for a wide range of lcd applications. the mask version, the ht49cu80, is fully pin and functionally compatible with the otp version ht49ru80 device. the advantages of low power consumption, i/o flexibil - ity, programmable frequency divider, timer functions, oscillator options, power-down and wake-up functions and buzzer driver in addition to a flexible and configurable lcd interface, enhance the versatility of these devices to control a wide range of lcd-based ap - plication possibilities such as measuring scales, elec - tronic multimeters, gas meters, timers, calculators, remote controllers and many other lcd-based indus - trial and home appliance applications. technical document tools information faqs application note ha0017e controlling the read/write function of the ht24 series eeprom using the ht49 series mcus ha0024e using the rtc in the ht49 mcu series ha0025e using the time base in the ht49 mcu series ha0026e using the i/o ports on the ht49 mcu series ha0027e using the timer/event counter in the ht49 mcu series
block diagram ht49ru80/ht49cu80 rev. 1.40 2 july 30, 2012

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pin assignment ht49ru80/ht49cu80 rev. 1.40 3 july 30, 2012 0 1 6 6 1 0 8 9 - 6 1 0 8 9 - 1 1 1 1 1 - 6 9 6 8 6 0 6 1 6 6 6 6 6 6 6 - 9 8 6 1 0 8 9 - 6 1 0 8 9 - $ 6 $ 1 $ 0 ) - / ! - ) / ! ) / - ) / ) / ) 6 ) 1 ) 0 - / # / # $ # - 6 1 / 0 - % 1 0 8 9 - 6 1 0 8 9 - - 9 8 $ - / ) 7 $ / ) 7 $ $ / 5 $
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pad description pad name i/o options description pa0/bz pa1/bz pa2 pa3/pfd pa4~pa7 i/o wake-up cmos or nmos pull-high pa0/pa1 or bz/bz pa3 or pfd bidirectional 8-bit input/output port. each pin on this port can be configured as a wake-up input by a configuration option. configuration options deter - mine whether pins pa0~pa3 are configured as cmos outputs or nmos in - put/output pins. if pa0~pa3 are configured as nmos input/output pins, then pull-high options are available but apply to all 4 pins, not individual pins. pins pa4~pa7 are always configured as nmos input/output pins with pull-high resistors connected. all inputs are schmitt trigger types. pins pa0, pa1 and pa3 are pin-shared with bz, bz and pfd respectively, the function of which is chosen via configuration options. pb0/int0 pb1/int1 pb2/tmr0 pb3/tmr1 pb4/tmr2 pb5~pb7 i 8-bit schmitt trigger input port. each input pin is connected to an internal pull-high resistor. pins pb0 and pb1 are pin-shared with int0 and int1 respectively. pins pb2, pb3 and pb4 are pin-shared with tmr0, tmr1 and tmr2 respectively. pc0/tx pc1/rx pc2~pc7 i/o cmos or nmos pull-high bidirectional 8-bit input/output port. two configuration options determine whether the four pins pc0~pc3 and the four pins pc4~pc7 are config - ured as cmos outputs or nmos input/output pins. pins must be config - ured as cmos outputs or nmos input/output pins in blocks of four pins, individual pins cannot be selected. if pins pc0~pc3 or pc4~pc7 are con - figured as nmos input/output pins, then a pull-high option is available for each block of four pins. individual pins cannot be selected to have a pull-high option. all inputs are schmitt trigger types. pins pc0 and pc1 are pin-shared with uart pins tx and rx respectively. pd0/seg40~ pd6/seg46 o cmos output or seg output 7-bit output port. each pin can be setup as either a cmos output or a seg output via configuration options. vlcd i lcd power supply. this pad is implemented for lcd power only. the vlcd levels can be greater or less than the vdd levels. vmax ic maximum voltage, connect to vdd, vlcd or v1. v1, v2, c1, c2 i lcd voltage pump com0~com2 com3/seg47 o 1 / 2, 1/3 or 1/4 duty the 1/4 lcd duty cycle configuration option will determine whether pin com3/seg47 is configured as a seg47 segment driver or as a common com3 output driver for the lcd panel. com0~com2 are the lcd com - mon outputs. seg0~seg39 o lcd driver outputs for lcd panel segments osc1 osc2 i o crystal or rc osc1 and osc2 are connected to an external rc network or external crystal (determined by configuration option) for the internal system clock. for external rc system clock operation, osc2 is an output pin for 1/4 system clock. if an rtc oscillator on pins osc3 and osc4 is used as a system clock, then the osc1 and osc2 pins should be left floating. osc3 osc4 i o rtc or system clock osc3 and osc4 are connected to a 32768hz crystal to form a real time clock for timing purposes or to form a system clock. res i schmitt trigger reset input, active low. vdd positive power supply vss negative power supply, ground ht49ru80/ht49cu80 rev. 1.40 4 july 30, 2012
absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage lvr disabled, f sys =4mhz 2.2 5.5 v lvr disabled, f sys =8mhz 3.3 5.5 v v lcd lcd power supply (note *) va 5.5v 2.2 5.5 v i dd1 operating current (crystal osc, rc osc) 3v no load, f sys =4mhz, uart off 12ma 5v 35ma i dd2 operating current (crystal osc, rc osc) 3v no load, f sys =4mhz, uart on 1.5 3.0 ma 5v 36ma i dd3 operating current (crystal osc, rc osc) 5v no load, f sys =8mhz, uart off 48ma i dd4 operating current (crystal osc, rc osc) 5v no load, f sys =8mhz, uart on 510ma i dd5 operating current (f sys =rtc osc) 3v no load, uart off 0.3 0.6 ma 5v 0.6 1 ma i stb1 standby current (*f s =f sys /4) 3v no load, system halt, lcd off at halt, uart off 1 a 5v 2 a i stb2 standby current (*f s =rtc osc) 3v no load, system halt, lcd on at halt, c type, uart off 2.5 5.0 a 5v 10 20 a i stb3 standby current (*f s =wdt osc) 3v no load, system halt lcd on at halt, c type, uart off 25 a 5v 610 a i stb4 standby current (*f s =rtc osc) 3v no load, system halt, lcd on at halt, r type, 1 / 2 bias, uart off 17 30 a 5v 34 60 a i stb5 standby current (*f s =rtc osc) 3v no load, system halt, lcd on at halt, r type, 1 / 3 bias, uart off 13 25 a 5v 26 50 a i stb6 standby current (*f s =wdt osc) 3v no load, system halt, lcd on at halt, r type, 1 / 2 bias, uart off 14 25 a 5v 28 50 a i stb7 standby current (*f s =wdt osc) 3v no load, system halt, lcd on at halt, r type, 1 / 3 bias, uart off 10 20 a 5v 20 40 a ht49ru80/ht49cu80 rev. 1.40 5 july 30, 2012
symbol parameter test conditions min. typ. max. unit v dd conditions v il1 input low voltage for i/o ports, tmr0, tmr1, tmr2, int0 and int1 0 0.3v dd v v ih1 input high voltage for i/o ports, tmr0, tmr1, tmr2, int0 and int1 0.7v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v i ol1 i/o port sink current 3v v ol =0.1v dd 612 ma 5v 10 25 ma i oh1 i/o port source current 3v v oh =0.9v dd 2 -4 ma 5v 5 8 ma i ol2 lcd common and segment current 3v v ol =0.1v a 210 420 a 5v 350 700 a i oh2 lcd common and segment current 3v v oh =0.9v a 80 160 a 5v 180 360 a r ph pull-high resistance 3v 20 60 100 k
5v 10 30 50 k
v lvr low voltage reset voltage 2.7 3.0 3.3 v v lvd low voltage detector voltage 3.0 3.3 3.6 v note: * for the value of va refer to the lcd driver section. *f s please refer to the wdt clock option a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (crystal osc, rc osc) 2.2v~5.5v 400 4000 khz 3.3v~5.5v 400 8000 khz f sys2 system clock (32768hz crystal osc) 32768 hz f rtcosc rtc frequency 32768 hz f timer timer i/p frequency (50% duty) 2.2v~5.5v 0 4000 khz 3.3v~5.5v 0 8000 khz t wdtosc watchdog oscillator period 3v 45 90 180 s 5v 32 65 130 s t res external reset low pulse width 1 s t sst system start-up timer period wake-up from halt 1024 *t sys t lvr low voltage width to reset 0.25 1 2 ms t int interrupt pulse width 1 s note: *t sys = 1/f sys1 or 1/f sys2 ht49ru80/ht49cu80 rev. 1.40 6 july 30, 2012
ht49ru80/ht49cu80 rev. 1.40 7 july 30, 2012 functional description execution flow the system clock is derived from either a crystal or an rc oscillator or a 32768hz crystal oscillator. it is inter - nally divided into four non-overlapping clocks. one in - struction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de - coding and execution takes the next instruction cycle. the pipelining scheme makes it possible for each in - struction to be effectively executed in a cycle. if an in - struction changes the value of the program counter, two cycles are required to complete the instruction. program counter pc the program counter (pc) is 14 bits wide and controls the sequence in which the instructions stored in the pro - gram rom are executed. the contents of the pc can specify a maximum of 16384 addresses. after accessing a program memory word to fetch an in - struction code, the value of the pc is incremented by 1 . the pc then points to the memory word containing the next instruction code. when executing a jump instruction, a conditional skip execution, loading a pcl register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the pc manages the pro - gram transfer by loading the address corresponding to each instruction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; oth - erwise the program proceeds to the next instruction. 5 & ( ! ( : ; < ( ! ( : = ; 5 & ( ! ( : > ; < ( ! ( : ; 5 & ( ! ( : > ; < ( ! ( : > ; > > ( ? @ ( : (
? ; execution flow mode program counter *13 *12~*8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 0 00000 00000000 external interrupt 0 0 00000 00000100 external interrupt 1 0 00000 00001000 timer/event counter 0 overflow 0 00000 00001100 timer/event counter 1 overflow 0 00000 00010000 uart interrupt 0 00000 00010100 multi function interrupt 0 00000 00011000 skip program counter + 2 (within the current bank) loading pcl *13 *12~*8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch bp.5 #12~#8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s13 s12~s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *13~*0: program counter bits s13~s0: stack register bits #12~#0: instruction code bits @7~@0: pcl bits 8 0 -
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ht49ru80/ht49cu80 rev. 1.40 8 july 30, 2012 the lower byte of the pc, known as pcl, is a readable and writeable register. moving data into the pcl performs a short jump. the destination is within 256 locations. when a control transfer takes place, an additional dummy cycle is required. program memory rom the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organised into 819216 2 banks which are addressed by the program counter and table pointer. the bp register bits5~bits7 are used to select the pro - gram memory bank. when bp.7~bp.5 = 000b, program memory bank 0 is selected and ranges from 0000h to 1fffh. when bp.7~bp.5 = 001b, program memory bank 1 is selected which ranges from 2000h to 3fffh. the call and jmp instruction provide for a full 13 bits of addressing to allow branching anywhere within the 8k program memory bank. when executing a call or jmp instruction, the highest bit of the address is provided by bp.5. when executing a call or jmp instruction, the bank select bit must be correctly programmed to ensure that the desired program memory bank is addressed. if a return from a call instruction or an interrupt is exe - cuted, the entire 14-bit program counter is popped off the stack. certain locations in the rom are reserved for special usage: location 000h location 000h is reserved for program initialisation. after a chip reset, the program always begins execu - tion at this location. location 004h location 004h is reserved for the external interrupt service program. if the int0 input pin is activated, and the interrupt is enabled, and the stack is not full, the program will jump to this location and begin execution. location 008h location 008h is reserved for the external interrupt service program also. if the int1 input pin is activated, and the interrupt is enabled, and the stack is not full, the program will jump to this location and begin execution. location 00ch location 00ch is reserved for the timer/event coun - ter 0 interrupt service program. if a timer interrupt re - sults from a timer/event counter 0 overflow, and if the interrupt is enabled and the stack is not full, the pro- gram will jump to this location and begin execution. location 010h location 010h is reserved for the timer/event coun- ter 1 interrupt service program. if a timer interrupt re- sults from a timer/event counter 1 overflow, and if the interrupt is enabled and the stack is not full, the pro- gram will jump to this location and begin execution. location 014h this location is reserved for the uart interrupt ser - vice program. if a uart interrupt results from a uart tx or rx, and the interrupt is enabled and the stack is not full, the program will jump to this location and be - gin execution. location 018h this location is reserved for the multi function interrupt service program. if a multi function interrupt results from a timer/event counter 2 overflow, a time base interrupt occurs, or an rtc counter overflow, and the related interrupts are enabled and the multi function interrupt is enabled and the stack is not full, the pro - gram will jump to this location and begin execution. , (
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5 5 3 % @ = ( c ? ( : 6 1 ( e ; 5 - - 3 program memory instruction(s) table location *13~*8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] tbhp @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 111111 @7 @6 @5 @4 @3 @2 @1 @0 table location note: *13~*0: table location bits tbhp: table pointer higher-order bits @7~@0: bits of tblp
ht49ru80/ht49cu80 rev. 1.40 9 july 30, 2012 table location any location in the program memory can be used as look-up tables. the instructions tabrdc [m] (page specified by tbhp and tblp) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). the higher-order byte table pointer tbhp (1fh) and lower-order byte table pointer tblp (07h) are read/write registers, which in - dicate the table locations. before accessing the table data, the location has to be placed in the tbhp and tblp. the tblh register is read only and cannot be restored. if the main routine and the interrupt service routine both employ the table read instruction, the contents of the tblh register in the main routine are likely to be changed by the table read instruction used in the interrupt service routine. if this happens errors can occur. therefore, using the table read instruction in the main routine and in the interrupt service routine simultaneously should be avoided. however, if the ta - ble read instruction has to be used in both the main routine and in the interrupt service routine the interrupt should be disabled prior to executing the table read in - struction. it should not be re-enabled until tblh in the main routine has been backed up. all table related in - structions require 2 cycles to execute. stack register stack the stack register is a special part of the memory used to save the contents of the program counter. the stack is organised into 16 levels and is neither part of the data memory nor part of the program memory, and is neither readable nor writeable. its activated level is indexed by a stack pointer, known as sp, and is neither readable nor writeable. at the start of a subroutine call or an inter- rupt acknowledge, the contents of the program counter are pushed onto the stack. at the end of the subroutine or interrupt routine, indicated by a return instruction, ret or reti, the contents of the program counter are restored to their previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the ac - knowledge is still inhibited. once the stack pointer is decremented, by ret or reti, the interrupt is serviced. this feature prevents stack overflow, allowing the pro - grammer to use the structure easily. likewise, if the stack is full, and a call is subsequently executed, a stack overflow occurs and the first entry is lost. only the most recent 16 return addresses are stored. data memory ram not including the lcd memory, the data memory, has a total capacity of 608 8 bits, and is divided into two func - tional groups, namely, the special function registers and the general purpose data memory most of which are readable/ writeable, although some are read only. the general purpose data memory is subdivided into three banks, banks 0, 2 and 3 each of which has a capacity of 192 8bits. the bank pointer, bp, selects which bank is to be used, however care should be exercised when manipulating the bank pointer as it is also used to select the program memory bank. bp ram bank 00000 0 00001 1 00010 2 00011 3 the general purpose data memory, addressed from 40h to ffh (bank0, 2, 3), is used for data and control infor - mation under instruction commands. the ram areas can directly handle arithmetic, logic, in - crement, decrement, and rotate operations. except for some dedicated bits, each bit in the ram can be set and reset by the bit manipulation instructions set [m].i and clr [m].i . they are also indirectly accessible through memory pointer register 0, mp0, or memory pointer register 1, mp1. there is also a special part of memory for the lcd mem - ory. bits in this special part memory are mapped to the lcd pixel one by one. this lcd memory is located in data memory bank 1. indirect addressing registers locations 00h and 02h are indirect addressing regis- ters that are not physically implemented. any read/write operation of [00h] and [02h] accesses the data memory pointed to by mp0 and mp1, respectively. reading lo- cations 00h or 02h indirectly returns the result 00h. writing to it indirectly leads to no operation. the direct transfer of data between two indirect ad - dressing registers is not supported. the memory pointer registers, mp0 and mp1, are both 8-bit registers used to access the data memory by combining the correspond - ing indirect addressing registers. mp0 can only be ap - plied to memory located at bank 0, while mp1 can be applied to data memory from bank 0, bank 2 and bank 3 as well as the lcd display memory which is located in bank 1. accumulator acc the accumulator, acc, is related to alu operations. it is also mapped to location 05h in the data memory and is capable of operating with immediate data. any data transfers between two data memory locations must pass through the acc.
ht49ru80/ht49cu80 rev. 1.40 10 july 30, 2012 arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic opera - tions and provides the following functions: arithmetic operations - add, adc, sub, sbc, daa logical operations - and, or, xor, cpl rotations - rl, rr, rlc, rrc increment and decrement - inc, dec branch decisions - sz, snz, siz, sdz etc. the alu not only saves the results of a data operation but also changes the status register. status register status the status register is 8 bits wide and contains, a carry flag (c), an auxiliary carry flag (ac), a zero flag (z), an overflow flag (ov), a power down flag (pdf), and a watchdog time-out flag (to). it also records the status information and controls the operation sequence. except for the to and pdf flags, bits in the status reg - ister can be altered by instructions similar to other reg - isters. data written into the status register does not alter the to or pdf flags. operations related to the status register, however, may yield different results from those intended. the to and pdf flags can only be changed by a watchdog timer overflow, device power-on, or clearing the watchdog timer and executing the halt instruction. the z, ov, ac, and c flags reflect the status of the latest operations. on entering the interrupt sequence or executing the sub- routine call, the status register will not be automatically pushed onto the stack. if the contents of the status is im- portant, and if the subroutine is likely to corrupt the status register, precautions should be taken to save it properly. interrupts the device provides two external interrupts, three inter - nal timer/event counters interrupts, an internal time base interrupt, an internal real time clock interrupt, and an uart tx/rx interrupt. the interrupt control register 0, intc0, and interrupt control register 1, intc1, both contain the interrupt control bits that are used to set the enable/disable status and to record the interrupt request flags. once an interrupt subroutine is serviced, other interrupts are all blocked, by clearing the emi bit. this scheme may prevent any further interrupt nesting. other interrupt re - quests may take place during this interval, but only the in - terrupt request flag will be recorded. if a certain interrupt requires servicing within the service routine, the emi bit and the corresponding bit in the intc0 or of intc1 regis - ter may be set in order to allow interrupt nesting. once the stack is full, the interrupt request will not be acknowl - edged, even if the related interrupt is enabled, until the sp is decremented. if immediate service is desired, the stack should be prevented from becoming full. ? ( ( d ( "
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ht49ru80/ht49cu80 rev. 1.40 11 july 30, 2012 all interrupts provide a wake-up function. as an interrupt is serviced, a control transfer occurs by pushing the con - tents of the program counter onto the stack followed by a branch to a subroutine at a specified program memory location. only the contents of the program counter is pushed onto the stack. if the contents of the register or of the status register is altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. external interrupts are triggered by a high to low transi- tion on the int0 or int1 pins, which will result in their their related interrupt request flags, eif0 and eef1, be- ing set. after the interrupt is enabled, the stack is not full, and a high to low transition occurs on the external inter- rupt pins, a subroutine call to location 04h or 08h occurs. when the interrupt service routine is serviced, the inter- rupt request flags, eif0 and eif1, and the global enable bit, emi, are all cleared to disable other interrupts. the internal timer/event counter 0 interrupt is initialised by setting the timer/event counter 0 interrupt request flag, t0f. this will occur when the timer over - flows. after the interrupt is enabled, and the stack is not full, and t0f bit is set, a subroutine call to location 0ch occurs. the related interrupt request flag, t0f, is reset, and the emi bit is cleared to disable further interrupts. the timer/event counter 1 is operated in the same manner but its related interrupt request flag is t1f, and its subroutine call location is 10h. the uart interrupt is initialised by setting the interrupt request flag, urf, that is caused by a regular uart re - ceive signal, caused by a uart transmit signal. after the interrupt is enabled, the stack is not full, and the urf bit is set, a subroutine call to location 14h occurs. the related interrupt request flag, urf, is reset and the emi bit is cleared to disable further interrupts. the multi function interrupt is initialised by setting the in - terrupt request flag, mff, that is caused by a regular internal timer/event counter 2 overflow, caused by a time base signal or caused by a real time clock signal. after the interrupt is enabled, the stack is not full, and the mff bit is set, a subroutine call to location 18h oc - curs. the related interrupt request flag, mff, is reset and the emi bit is cleared to disable further interrupts. during the execution of an interrupt subroutine, other in - terrupt acknowledgments are all held until a reti in - struction is executed or the emi bit and the related inter- rupt control bit are both set to 1 (if the stack is not full). to return from the interrupt subroutine a ret or reti may be executed. reti sets the emi bit and enables an interrupt service, but ret does not. interrupts occurring in the interval between the rising edges of two consecutive t2 pulses are serviced on the latter of the two t2 pulses if the corresponding interrupts are enabled. in the case of simultaneous requests, the priorities in the following table apply. these can be masked by resetting the emi bit. interrupt source priority vector external interrupt 0 1 004h external interrupt 1 2 008h timer/event counter 0 overflow 3 00ch timer/event counter 1 overflow 4 010h uart interrupt 5 014h multi function interrupt (timer 2, time base, rtc) 6 018h it is recommended that a program should not use the call subroutine within the interrupt subroutine. it sbe - cause interrupts often occur in an unpredictable manner or require to be serviced immediately in some applica - tions. during that period, if only one stack is left, and en - abling the interrupt is not well controlled, operation of the call in the interrupt subroutine may damage the origi - nal control sequence. bit no. label function 0c c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation, otherwise c is cleared. c is also affected by a rotate through carry instruction. 1ac ac is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction, otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is zero, otherwise z is cleared. 3ov ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa, otherwise ov is cleared. 4 pdf pdf is cleared by either a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5to to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6, 7 unused bit, read as 0 status (0ah) register
ht49ru80/ht49cu80 rev. 1.40 12 july 30, 2012 bit no. label function 0 emi controls the master (global) interrupt (1=enable; 0=disable) 1 eei0 controls the external interrupt 0 (1=enable; 0=disable) 2 eei1 controls the external interrupt 1 (1=enable; 0=disable) 3 et0i controls the timer/event counter 0 overflow interrupt (1=enable; 0=disable) 4 eif0 external interrupt 0 request flag (1=active; 0=inactive) 5 eif1 external interrupt 1 request flag (1=active; 0=inactive) 6 t0f timer/event counter 0 overflow request flag (1=active; 0=inactive) 7 unused bit, read as 0 intc0 (0bh) register bit no. label function 0 et1i controls the timer/event counter 1 overflow interrupt (1=enable; 0=disable) 1 euri controls the uart tx or rx interrupt (1=enable; 0:disable) 2 emfi controls the multi-function interrupt (1=enable; 0:disable) 3, 7 unused bit, read as 0 4 t1f timer/event counter 1 overflow request flag (1=active; 0=inactive) 5 urf uart tx or rx interrupt request flag (1=active; 0=inactive) 6 mff multi function interrupt request flag (1=active; 0=inactive) intc1 (1eh) register bit no. label function 0 et2i controls the timer/event counter 2 overflow interrupt (1=enable; 0=disable) 1 etbi controls the time base interrupt (1=enable; 0=disable) 2 erti controls the real time clock interrupt (1=enable; 0=disable) 3, 7 unused bit, read as 0 4 t2f timer/event counter 2 interrupt request flag (1=active; 0=inactive) 5 tbf time base interrupt request flag (1=active; 0=inactive) 6 rtf real time clock interrupt request flag (1=active; 0=inactive) mfic (23h) register
ht49ru80/ht49cu80 rev. 1.40 13 july 30, 2012 oscillator configuration these devices contain three kinds of system clocks, an rc oscillator, a crystal oscillator and a 32768hz crystal oscillator, the choice of which is determined by configu - ration options. no matter what type of oscillator is se - lected, the signal is used for the system clock. the power down mode stops the system oscillator if it is an rc or crystal oscillator type. the 32768hz crystal sys - tem oscillator will continue to run even if in the power down mode. if the 32768hz crystal oscillator is selected as the system oscillator, the system oscillator will con - tinue to run but f sys and instruction execution will cease. since the system oscillator is also designed for timing purposes, the internal timing such as that for the rtc, the time base and wdt operation continues to run even if the system enters the power down mode. of the three oscillators, if the rc oscillator is used, an external resistor between osc1 and vss is required, whose range should be from 24k
to 1m
. a frequency equal to the system clock divided by 4, is available on pin osc2. this pin can be used for synchronisation pur - poses but as it is an open drain output a pull-high resis - tor should be connected. the rc oscillator provides the most cost effective solution, but, the frequency of the os - cillation may vary with vdd, temperature, and process variations. it is therefore, not suitable for timing sensitive operations where accurate oscillator frequencies are desired. if the crystal oscillator is selected, a crystal connected between osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator. no other external components are required. a resonator may be connected between osc1 and osc2 to replace the crystal and to get a frequency reference, but two ex - ternal capacitors connected between osc1/osc2 and ground are required. a further oscillator circuit designed for the real time clock also exists. this operates at a sole frequency of 32768hz, for which a 32768hz crystal should be con - nected between pins osc3 and osc4. the rtc oscillator circuit can be controlled to start up quickly by clearing the qosc bit in the rtcc register. after power on, as the rtc oscillator will be in the quick start up mode, it is recommended that it be turned off af - ter about 2 seconds to conserve power. the wdt oscillator is a free running on-chip rc oscilla - tor requiring no external components. although when the system enters the power down mode, the system clock stops, the wdt oscillator will continue to run with a period of approximately 65 s at 5v. the wdt oscillator can be disabled by a configuration option to conserve power. watchdog timer wdt the wdt clock source is sourced from its own dedi - cated rc oscillator (wdt oscillator), from the instruction clock (system clock/4) or the real time clock oscillator (rtc oscillator). the timer is designed to prevent a soft- ware malfunction or sequence from jumping to an un- known location with unpredictable results. the wdt can be disabled by a configuration option. if the wdt is dis- abled, all instruction executions relating to the wdt will lead to no operation. the wdt time-out period is f s /2 15 ~f s /2 16 . ? ( ? ? ( ? ? ' 4 / 0 1 8 3 b ( ? / ( ? ? 0 - 5 system oscillator symbol parameter min. typ. max. unit f o nominal frequency 32.768 khz esr series resistance 50 65 k
c l load capacitance 9 pf note: 1. it is strongly recommended to use a crystal with load capacitance 9pf. 2. the oscillator selection can be optimized using a high quality resonator with small esr value. refer to crystal manufacturer for more details: www.microcrystal.com crystal specifications
ht49ru80/ht49cu80 rev. 1.40 14 july 30, 2012 if the wdt clock source chooses the internal wdt oscil - lator as its clock source, the time-out period may vary with temperature, vdd, and process variations. if the clock source is chosen to be the instruction clock, then when the power down mode is entered, it must be noted that the wdt will stop counting and lose its protective function. when the device operates in a noisy environment, using the wdt oscillator is strongly recommended, since the power down mode will stop the system clock. the wdt overflow under normal operation initialises a chip reset and sets the status bit to . in the power down mode, the overflow initialises a warm reset , and only the program counter and sp are reset to zero. to clear the wdt contents, there are three methods to be adopted. these are an external reset (a low level on the res pin), a software instruction, and a halt instruction. there are two methods of using software instructions to clear the watchdog timer, one of which must be chosen by configuration option. the first option is to use the sin - gle clr wdt instruction while the second is to use the two commands clr wdt1 and clr wdt2 . for the first option, a simple execution of clr wdt will clear the wdt while for the second option, both clr wdt1 and clr wdt2 must both be executed to successfully clear the wdt. note that for this second option, if clr wdt1 is used to clear the wdt, succes- sive executions of this instruction will have no effect, only the execution of a clr wdt2 instruction will clear the wdt. similarly after the clr wdt2 instruc- tion has been executed, only a successive clr wdt1 instruction can clear the watchdog timer. multi-function timer these devices provide a multi-function timer for the wdt, time base and rtc but with different time-out pe - riods. the multi-function timer consists of an 8-stage di - vider and a 7-bit prescaler, with the clock source coming from the wdt osc, the rtc osc or the instruction clock which is the system clock divided by 4. the multi-function timer also provides a selectable fre - quency signal, ranging from f s /2 2 to f s /2 8 , for the lcd driver circuits, and a selectable frequency signal, ranging from f s /2 2 to f s /2 9 , for the buzzer output selectable by configuration options. to obtain a proper display, it is recommended that a frequency as near as possible to 4khz is selected for the lcd driver circuits. time base the time base offers a periodic time-out period to gener - ate a regular internal interrupt. its time-out period ranges from /2 12 to f s /2 15 selected by a configuration op - tion. if a time base time-out occurs, the related interrupt request flag, tbf, will be set. if the interrupt is enabled, and the stack is not full, a subroutine call to location 18h will take place. the time base time-out signal can also be applied as a clock source to timer/event counter 1 in order to get a longer time-out period. real time clock rtc the real time clock, abbreviated as rtc, is operated in the same manner as the time base in that it is used to supply a regular internal interrupt. its time-out period ranges from f s /2 8 to f s /2 15 the actual value setup by soft- ware programming . writing data to the rt2, rt1 and rt0 bits in the rtcc register provides various time-out periods. if an rtc time-out occurs, the related interrupt request flag, rtf, will be set. if the interrupt is enabled, and the stack is not full, a subroutine call to location 18h will take place. the real time clock time-out signal can also be used as a clock source for timer/event counter 0 in order to get longer time-out periods. , ( ( ( ( ( ( ( ( ' 8 ( ( < a ? - (
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ht49ru80/ht49cu80 rev. 1.40 15 july 30, 2012 rt2 rt1 rt0 rtc clock divided factor 000 2 8 * 001 2 9 * 010 2 10 * 011 2 11 * 100 2 12 101 2 13 110 2 14 111 2 15 note: * not recommended to be used power down mode halt the power down mode is initialised when a halt in - struction is executed and results in the following. the system oscillator and f sys turn off but the wdt or rtc oscillator keeps running, if the wdt oscillator or the real time clock is selected. the contents of the data memory and registers remain unchanged. the wdt is cleared and starts recounting, if the wdt clock source is sourced from the wdt oscillator or the real time clock oscillator. all i/o ports maintain their original status. the pdf flag is set but the to flag is cleared. the lcd driver keeps running, if the wdt osc or rtc osc is selected. the system will exit from power down mode by way of an external reset, an interrupt, an external falling edge signal on port a or a wdt overflow. an external reset causes a device initialisation, while a wdt overflow per- forms a warm reset . after examining the to and pdf flags, the reason for a chi p reset can be determined. the pdf flag is cleared by a system power-up or by executing the clr wdt instruction, and is set by executing the halt instruction. however if the to flag is set and a wdt time-out occurs, the corresponding wake-up only resets the program counter and the stack pointer, and leaves the other registers in their original state. the port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each pin on port a can be independently selected to wake up the device using configuration options. awakening from an i/o port stimulus, the program resumes execution at the next instruction. when awakening from an interrupt, two sequences may occur. if the related interrupt is disabled or the interrupt is enabled but the stack is full, the pro - gram resumes execution at the next instruction. but if the interrupt is enabled, and the stack is not full, the reg - ular interrupt response takes place. when an interrupt request flag is set before entering the power down mode, the system cannot be awakened us - ing that interrupt. if a wake-up event occurs, it takes 1024 t sys system clock periods to resume normal operation. in other words, a dummy period is inserted after the wake-up. if the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. however, if the wake-up results in the next instruction execution, the execution will be per - formed immediately after the dummy period is finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the power down mode. reset there are three ways in which a reset may occur. res is reset during normal operation res is reset during halt wdt time-out is reset during normal operation the wdt time-out during a power down differs from other chip reset conditions, as it will perform only a warm reset that resets only the program counter and sp and leaves the other circuits in their original state. some registers remain unaffected during other reset conditions. most registers are reset to their initial condi - tion once the reset conditions are met. by examining the pdf and to flags, the program can distinguish be- tween different chip resets. to pdf reset conditions 0 0 res reset during power-on u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchanged - - @ - @ - a 5 g - a - 5 g reset circuit note: * make the length of the wiring, which is con - nected to the res pin as short as possible, to avoid noise interference.
ht49ru80/ht49cu80 rev. 1.40 16 july 30, 2012 to guarantee that the system oscillator is running and stabilised, the sst (system start-up timer) provides an extra delay of 1024 system clock pulses when the sys - tem awakes from the power down mode. after awaken - ing from the power down mode, an sst delay is added. an extra option load time delay is added during a reset and power on. the functional unit chip reset status is shown below. program counter 000h interrupt disabled prescaler cleared wdt cleared. after master reset, wdt starts counting timer/event counter off input/output ports input mode stack pointer points to the top of the stack timer/event counter three timer/event counters are implemented in the de - vice, one 8-bit programmable count-up counter and two 16-bit programmable count-up counter. the timer/event counter 0 clock source may be sourced from the system clock, the system clock/4, the rtc time-out signal or from an external source. the system clock source or the system clock/4 source is se - lected by a configuration option. the timer/event counter 1 clock source may be sourced from the tmr0 overflow, the system clock, the time base time-out signal, the system clock/4 or an ex - ternal source. the three former clock sources are se - lected by configuration options. using the external clock input allows external events to be counted, time intervals or pulse widths to be measured, or an accurate time base to be generated. using the internal clock al - lows an accurate time base to be generated. the timer/event counter 2 contains a 16-bit program - mable count-up counter whose clock may be sourced from an external source or an internal clock source. the internal clock source comes from f sys /4. the external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. there are two registers related to the timer/event counter 0; tmr0 and tmr0c. two physical registers are mapped to the tmr0 location. writing to tmr0 places the starting value in the timer/event counter 0 register while reading tmr0 takes the contents of the timer/event counter 0. the tmr0c register is a timer/event counter control register, which defines the timer options. there are three registers related to the timer/event counter 1; tmr1h, tmr1l and tmr1c. writing to tmr1l will only transfer the data into an internal lower-order byte buffer (8-bit) and writing tmr1h will transfer the specified data and the contents of the lower-order byte buffer to tmr1h and tmr1l registers, respectively. the timer/event counter 1 preload regis- ter is changed by each writing trm1h operations. reading tmr1h will latch the contents of tmr1h and tmr1l counters to the destination and the lower-order byte buffer, respectively. reading the tmr1l will read the contents of the lower-order byte buffer. the tmr1c is the timer/event counter 1 control register, which de- fines the operating mode, counting enable or disable and an active edge. there are three registers related to the timer/event counter 2; tmr2h (20h), tmr2l (21h), tmr2c (22h). writing tmr2l will only place the written data to an in - ternal lower-order byte buffer (8-bit) and writing tmr2h will transfer the specified data and the contents of the lower-order byte buffer to tmr2h and tmr2l registers, respectively. the timer/event counter 2 preload regis - ter is changed by each writing trm2h operations. reading tmr2h will latch the contents of the tmr2h and tmr2l counters to the destination and the lower-order byte buffer, respectively. reading the tmr2l will read the contents of the lower-order byte buffer. the tmr2c is the timer/event counter 2 control register, which defines the operating mode, counting en - able or disable and an active edge. the t0m0, t0m1 (tmr0c), t1m0, t1m1 (tmr1c) and t2m0, t2m1 (tmr2c) bits define the operation mode. the event count mode is used to count external events, which means that the clock source is from an external (tmr0/tmr1/tmr2) pin. the timer mode functions as a normal timer with the clock source coming from the in - ( = & ( ( reset timing chart * 3 $ % <
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ht49ru80/ht49cu80 rev. 1.40 17 july 30, 2012 the register states are summarised below: register reset (power on) wdt time-out (norma operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu program counter 0000h 0000h 0000h 0000h 0000h tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu rtcc 0000 0111 0000 0111 0000 0111 0000 0111 00uu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu tmr0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0c 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u--- tmr1h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1c 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u--- pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pd -111 1111 -111 1111 -111 1111 -111 1111 -uuu uuuu intc1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu tbhp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr2h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr2l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr2c 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- mfic -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu usr 0000 1011 0000 1011 0000 1011 0000 1011 uuuu uuuu ucr1 0000 00x0 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu ucr2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu txr/rxr xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu brg xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu note: * stands for warm reset u stands for unchanged x stands for unknown
ht49ru80/ht49cu80 rev. 1.40 18 july 30, 2012 ternal selected clock source. finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (tmr0/tmr1/ tmr2), and the counting is based on the internal se - lected clock source. in the event count or timer mode, the timer/event coun - ter starts counting at the current contents in the timer/event counter and ends at ffh (ffffh). once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (t0f: bit 6 of the intc0; t1f: bit 4 of the intc1; t2f: bit 4 of the mfic). in the pulse width measurement mode with the values of the t0on/t1on/t2on and t0e/t1e/t2e bits equal to 1 , after the tmr0/tmr1/tmr2 has received a tran - sient from low to high (or high to low if the t0e/t1e/t2e bit is 0 ), it will start counting until the tmr0/tmr1/ tmr2) returns to the original level and resets the t0on/t1on/t2on. the measured result remains in the timer/event counter even if the activated transient occurs again. in other words, only 1-cycle measurement can be made until the t0on/t1on/t2on is set. the cy - cle measurement will re-function as long as it receives further transient pulse. in this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt re- quest, as in the other two modes, i.e., event and timer modes. to enable the counting operation, the timer on bit (t0on/t1on/t2on; bit 4 of the tmr0c/tmr1c/ tmr2c) should be set to 1 . in the pulse width mea- surement mode, the t0on/t1on/t2on is automati- cally cleared after the measurement cycle is completed. but in the other two modes, the t0on/t1on/t2on can only be reset by instructions. the overflow of the timer/event counter 0/1 is one of the wake-up sources and can also be applied to a pfd (programmable fre - quency divider) output at pa3 by options. only one pfd (pfd0 or pfd1) can be applied to pa3 by options. no matter what the operation mode is, writin ga0to et0i/et1i/et2i disables the related interrupt service. when the pfd function is selected, executing clr [pa].3 instruction to enable pfd output and executing set [pa].3 instruction to disable pfd output. in the case of timer/event counter off condition, writing data to the timer/event counter preload register also re - loads that data to the timer/event counter. but if the timer/event counter is turned on, data written to the timer/event counter is kept only in the timer/event coun - ter preload register. the timer/event counter still contin - ues its operation until an overflow occurs. when the timer/event counter (reading tmr0/tmr1/ tmr2) is read, the clock is blocked to avoid errors, as this may results in a counting error. blocking of the clock should be taken into account by the programmer. it is strongly recommended to load a desired value into the tmr0/tmr1/tmr2 register first, before turning on the related timer/event counter, for proper operation since the initial value of tmr0/tmr1/tmr2 is un - known. due to the timer/event counter scheme, the pro - grammer should pay special attention on the instruction to enable then disable the timer for the first time, when - ever there is a need to use the timer/event counter func - tion, to avoid unpredictable result. after this procedure, the timer/event counter function can be operated nor - mally. the following example is given, using one 8-bit and one 16-bit width timer (timer 0; timer 1) cascaded into 24-bit width. start: mov a, 09h ; set et0i & emi bits to mov intc0, a ; enable timer 0 and ; global interrupt mov a, 01h ; set et1i bit to enable mov intc1, a ; timer 1 interrupt mov a, 80h ; set the operating mode as mov tmr1c, a ; timer mode and select the mask ; option clock source mov a, 0a0h ; set the operating mode as timer mov tmr0c, a ; mode and select the system ; clock/4 set tmr1c.4 ; enable then disable timer 1 clr tmr1c.4 ; for the first time mov a, 00h ; load a desired value into mov tmr0, a ; the tmr0/tmr1 register mov a, 00h ; mov tmr1l, a ; mov tmr1h, a ; set tmr0c.4 ; normal operating set tmr1c.4 ; end
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ht49ru80/ht49cu80 rev. 1.40 20 july 30, 2012 bit no. label function 0~2 unused bit, read as 0 3 t0e defines the tmr0 active edge of the timer/event counter: in event counter mode (t0m1,t0m0)=(0,1): 1= count on falling edge; 0= count on rising edge in pulse width measurement mode (t0m1,t0m0)=(1,1): 1= start counting on the rising edge, stop on the falling edge; 0= start counting on the falling edge, stop on the rising edge 4 t0on enables/disables the timer counting (0=disable; 1=enable) 5 t0s 2 to 1 multiplexer control inputs which selects the timer/event counter clock source (0=rtc outputs; 1= system clock or system clock/4) 6 7 t0m0 t0m1 defines the operating mode (t0m1, t0m0) 01= event count mode (external clock) 10= timer mode (internal clock) 11= pulse width measurement mode (external clock) 00= unused tmr0c (0eh) register bit no. label function 0~2 unused bit, read as 0 3 t1e defines the tmr1 active edge of the timer/event counter: in event counter mode (t1m1,t1m0)=(0,1): 1= count on falling edge; 0= count on rising edge in pulse width measurement mode (t1m1,t1m0)=(1,1): 1= start counting on the rising edge, stop on the falling edge; 0= start counting on the falling edge, stop on the rising edge 4 t1on enables/disables timer counting (0= disable; 1= enabled) 5 t1s 2 to 1 multiplexer control inputs to select the timer/event counter clock source (0= option clock source; 1= system clock/4) 6 7 t1m0 t1m1 defines the operating mode (t1m1, t1m0) 01= event count mode (external clock) 10= timer mode (internal clock) 11= pulse width measurement mode (external clock) 00= unused tmr1c (11h) register bit no. label function 0~2 unused bit, read as 0 3 t2e defines the tmr2 active edge of the timer/event counter: in event counter mode (t2m1,t2m0)=(0,1): 1= count on falling edge; 0= count on rising edge in pulse width measurement mode (t2m1,t2m0)=(1,1): 1= start counting on the rising edge, stop on the falling edge; 0= start counting on the falling edge, stop on the rising edge 4 t2on enables/disables the timer counting (0=disable; 1=enable) 5 unused bit, read as 0 6 7 t2m0 t2m1 defines the operating mode (t2m1, t2m0): 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode (external clock) 00=unused tmr2c (22h) register
ht49ru80/ht49cu80 rev. 1.40 21 july 30, 2012 input/output ports there are two 8-bit bidirectional input/output ports, pa and pc and one 8-bit input pb and one 7-bit output pd. pa, pb, pc and pd are mapped to [12h], [14h], [16h] and [18h] of the ram, respectively. pa0~pa3 can be configured as cmos (output) or nmos (input/output) with or without pull-high resistor by options. pa4~pa7 are always pull-high and nmos (input/output). if nmos (input) is chosen, each bit on the port (pa0~pa7) can be configured as a wake-up input. pb can only be used for input operation. pc can be configured as cmos output or nmos input/output with or without pull-high resistor by options. pd can only be used for cmos output oper - ation. all the ports for the input operation (pa, pb and pc), are non-latched, that is, the inputs should be ready at the t2 rising edge of the instruction mov a, [m] (m=12h, 14h or 16h). for pa, pc, pd output operation, all data are latched and remain unchanged until the out - put latch is rewritten. when the pa and pc structures are open drain nmos type, it should be noted that, before reading data from the pads, a 1 should be written to the related bits to disable the nmos device. that is, executing first the in - struction set [m].i (i=0~7 for pa) to disable related nmos device, and then mov a, [m] to get stable data. after a chip reset, these input lines remain at high level or are left floating (by options). each bit of these output latches can be set or cleared by the mov [m], a (m=12h or 16h) instruction. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i, cpl [m], cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or to the accumulator. when a pa or pc line is used as an i/o line, the related pa or pc line options should be configured as nmos with or without pull-high resistor. once a pa or pc line is selected as a cmos output, the input function cannot be used. the input state of a pa or pc line is read from the related pa or pc pad. when the pa or pc is configured as nmos with or without pull-high resistor, one should be careful when applying a read-modify-write instruction to pa or pc. since the read-modify-write will read the en - tire port state (pads state) first, execute the specified in - struction and then write the result to the port data register. when the read operation is executed, a fault pad state (caused by the load effect or floating state) may be read. errors will then occur. there are three function pins that share with the pa port: pa0/bz, pa1/bz and pa3/pfd. the bz and bz are buzzer driving output pair and the pfd is a programmable frequency divider output. if user wants to use the bz/bz or pfd function, the related pa port should be set as a cmos output. the buzzer output signals are controlled by pa0 and pa1 data registers as defined in the following table. pa1 data register pa0 data register pa0/pa1 pad state 0 0 pa0=bz, pa1=bz 1 0 pa0=bz, pa1=0 x 1 pa0=0, pa1=0 note: x stands for unused the pfd output signal function is controlled by the pa3 data register and the timer/event counter state. the pfd output signal frequency is also dependent on the timer/event counter overflow period. the definitions of the pfd control signal and pfd output frequency are listed in the following table. timer timer preload value pa3 data register pa3 pad state pfd frequency off x 0 u x off x 1 0 x on n 0 pfd f int / [2(256n)] on n 1 0 x note: x stands for unused u stands for unknown 256 is for tmr0. if tmr1 is used to generate pfd, the number should be 65536. after a chip reset, these input/output lines remain at high levels (pull-high options) or floating state (non-pull-high options). it is suggested not to apply the read-modify- write instructions to the i/o port (since a reading error may occur). using mov instruction to avoid the read - ing error is suggested. the pb is a 8-bit input port and its configuration is schmitt trigger with pull-high resistors. each line of pa has the capability of waking-up the de - vice. the pb0, pb1, pb2, pb3 and pb4 are pin-shared with int0 , int1 , tmr0, tmr1 and tmr2 input func - tions, respectively.
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ht49ru80/ht49cu80 rev. 1.40 24 july 30, 2012 lcd display memory the device provides an area of embedded data memory for the lcd display. this area is located from 40h to 6fh in bank 1 of the data memory. the bank pointer, bp, is used to switch between the general purpose data memory and the lcd display memory. when bp has the value 01h , any data written into the locations 40h~6fh will influence the lcd display. when bp is cleared to 00h , any data written into the locations 40h~6fh will access the general purpose data memory. the lcd display memory can be read and written to only using the indirect addressing mode using memory pointer mp1. when data is written into the display data area, it is automatically read by the lcd driver which then generates the corresponding lcd driving signals. to turn the display on or off, a 1 or a 0 is written to the corresponding bit of the display memory, respec - tively. the figure illustrates the mapping between the display memory and the lcd pattern for the device. lcd driver output the output number of the lcd driver device can be 48 2, 48 3or47 4 selected by configuration options, i.e., 1 / 2 duty, 1 / 3 duty or 1/4 duty. there are two types of biasing, r type or c type. if the r bias type is se - lected, no external capacitors are required. if the c bias type is selected, a capacitor mounted between c1 and c2 pins is required. if 1 / 2 bias is selected, a capaci - tor mounted between the v2 pin and ground is required. if 1 / 3 bias is selected, two capacitors are required to be connected between the v1 and v2 pins and v ss . a sug - gested value of 0.1 f is recommended for all the ca - pacitors. - 3 - ! 3 3 3 1 3 1 3 1 5 3 ) - - 6 1 0 display memory - ( ( ( ( % (
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ht49ru80/ht49cu80 rev. 1.40 26 july 30, 2012 the lcd driver requires a clock source for proper operation. the lcd clock source is sourced from the general pur - pose prescaler whose frequency value is determined by configuration options. the lcd clock frequency should be se - lected to be as close to 4khz as possible. the lcd clock frequency options are listed in the following table. lcd clock source prescaler stages same as wdt clock source f s f s /2 2 ~f s /2 8 lcd segments as output port the seg40~seg46 lines, via individual configuration options, can be chosen to be either lcd segment outputs or pd outputs. when a segment output is selected, the connection to the vmax pin depends upon the bias and the voltage that is applied to vlcd. the details are shown in the table. when used as a pd output, v max should be connected to v dd . lcd type r type c type bias type 1 / 2 bias 1 / 3 bias 1 / 2 bias 1 / 3 bias v max if v dd >v lcd , user should connect v max to v dd , else connect v max to v lcd if v dd > 3/2v lcd , user should connect v max to v dd , else connect v max to v 1 low voltage reset/detector functions the device contains low voltage detector, lvd, and low voltage reset, lvr, circuits. these two functions are enabled or disabled using configuration options. if the configuration options enable the lvd, it can be further enabled or disabled using software, by changing the value of the rtcc.3 bit. the rtcc.5 bit can be used to read the status of the lvd. the low voltate reset function, lvr, has the same effect as the external res signal which executes a chip reset.its function is selected via a configuration option. when the device is in the power down mode, the lvr is disabled. the rtcc register definitions are shown in the table. bit no. label read/write function 0~2 rt0~rt2 r/w 8 to 1 multiplexer control inputs to select the real time clock prescaler output 3 lvdc r/w lvd enable/disable (1/0) 4 qosc r/w 32768hz osc quick start-up - 0/1: quick/slow start 5 lvdo r lvd detector output (1/0) - 1: low voltage detected 6, 7 unused bit, read as 0 rtcc (09h) register
ht49ru80/ht49cu80 rev. 1.40 27 july 30, 2012 uart bus serial interface the ht49ru80/ht49cu80 devices contain an inte - grated full-duplex asynchronous serial communications uart interface that enables communication with exter - nal devices that contain a serial interface. the uart function has many features and can transmit and re - ceive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or in - correctly framed. the uart function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. uart features the integrated uart function contains the following features: full-duplex, asynchronous communication 8 or 9 bits character length even, odd or no parity options one or two stop bits baud rate generator with 8-bit prescaler parity, framing, noise and overrun error detection support for interrupt on address detect (last character bit=1) separately enabled transmitter and receiver 2-byte deep fifo receive data buffer transmit and receive interrupts interrupts can be initialized by the following conditions: transmitter empty transmitter idle receiver full receiver overrun address mode detect uart external pin interfacing to communicate with an external serial interface, the internal uart has two external pins known as tx and rx. the tx pin is the uart transmitter pin, which can be used as a general purpose i/o pin if the pin is not configured as a uart transmitter, which occurs when the txen bit in the ucr2 control register is equal to zero. similarly, the rx pin is the uart receiver pin, which can also be used as a general purpose i/o pin, if the pin is not configured as a receiver, which occurs if the rxen bit in the ucr2 register is equal to zero. along with the uarten bit, the txen and rxen bits, if set, will automatically setup these i/o pins to their re - spective tx output and rx input conditions and dis - able any pull-high resistor option which may exist on the rx pin. uart data transfer scheme the block diagram shows the overall data transfer structure arrangement for the uart. the actual data to be transmitted from the mcu is first transferred to the txr register by the application program. the data will then be transferred to the transmit shift register from where it will be shifted out, lsb first, onto the tx pin at a rate controlled by the baud rate generator. only the txr register is mapped onto the mcu data memory, the transmit shift register is not mapped and is therefore inaccessible to the application pro - gram. data to be received by the uart is accepted on the external rx pin, from where it is shifted in, lsb first, to the receiver shift register at a rate controlled by the baud rate generator. when the shift register is full, the data will then be transferred from the shift register to the internal rxr register, where it is buffered and can be manipulated by the application program. only the rxr register is mapped onto the mcu data mem - ory, the receiver shift register is not mapped and is therefore inaccessible to the application program. it should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate txr and rxr registers, only exists as a single shared reg- ister in the data memory. this shared register known as the txr/rxr register is used for both data trans- mission and data reception. uart status and control registers there are five control registers associated with the uart function. the usr, ucr1 and ucr2 registers control the overall function of the uart, while the brg register controls the baud rate. the actual data to be transmitted and received on the serial interface is managed through the txr/rxr data registers. # ( # ( ) % )
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ht49ru80/ht49cu80 rev. 1.40 28 july 30, 2012 usr register the usr register is the status register for the uart, which can be read by the program to determine the present status of the uart. all flags within the usr register are read only. further explanation on each of the flags is given below: txif the txif flag is the transmit data register empty flag. when this read only flag is 0 it indicates that the character is not transferred to the transmit shift registers. when the flag is 1 it indicates that the transmit shift register has received a character from the txr data register. the txif flag is cleared by reading the uart status register (usr) with txif set and then writing to the txr data register. note that when the txen bit is set, the txif flag bit will also be set since the transmit buffer is not yet full. tidle the tidle flag is known as the transmission com - plete flag. when this read only flag is 0 it indicates that a transmission is in progress. this flag will be set to 1 when the txif flag is 1 and when there is no transmit data, or break character being trans - mitted. when tidle is 1 the tx pin becomes idle. the tidle flag is cleared by reading the usr regis - ter with tidle set and then writing to the txr regis - ter. the flag is not generated when a data character, or a break is queued and ready to be sent. rxif the rxif flag is the receive register status flag. when this read only flag is 0 it indicates that the rxr read data register is empty. when the flag is 1 it indicates that the rxr read data register con- tains new data. when the contents of the shift regis- ter are transferred to the rxr register, an interrupt is generated if rie=1 in the ucr2 register. if one or more errors are detected in the received word, the appropriate receive-related flags nf, ferr, and/or perr are set within the same clock cycle. the rxif flag is cleared when the usr register is read with rxif set, followed by a read from the rxr reg - ister, and if the rxr register has no data available. ridle the ridle flag is the receiver status flag. when this read only flag is 0 it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. when the flag is 1 it in - dicates that the receiver is idle. between the com - pletion of the stop bit and the detection of the next start bit, the ridle bit is 1 indicating that the uart is idle. oerr the oerr flag is the overrun error flag, which indi - cates when the receiver buffer has overflowed. when this read only flag is 0 there is no overrun er - ror. when the flag is 1 an overrun error occurs which will inhibit further transfers to the rxr receive data register. the flag is cleared by a software se - quence, which is a read to the status register usr followed by an access to the rxr data register. ferr the ferr flag is the framing error flag. when this read only flag is 0 it indicates no framing error. when the flag is 1 it indicates that a framing error has been detected for the current character. the flag can also be cleared by a software sequence which will involve a read to the usr status register followed by an access to the rxr data register. nf the nf flag is the noise flag. when this read only flag is 0 it indicates a no noise condition. when the flag is 1 it indicates that the uart has de- tected noise on the receiver input. the nf flag is set during the same cycle as the rxif flag but will not be set in the case of an overrun. the nf flag can be cleared by a software sequence which will involve a read to the usr status register, followed by an ac - cess to the rxr data register. + ) c 0 % ! 5 c - # 5 % # 5
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! perr the perr flag is the parity error flag. when this read only flag is 0 it indicates that a parity error has not been detected. when the flag is 1 it indi - cates that the parity of the received word is incor - rect. this error flag is applicable only if parity mode (odd or even) is selected. the flag can also be cleared by a software sequence which involves a read to the usr status register, followed by an ac - cess to the rxr data register. ucr1 register the ucr1 register together with the ucr2 register are the two uart control registers that are used to set the various options for the uart function, such as overall on/off control, parity control, data transfer bit length etc. further explanation on each of the bits is given below: tx8 this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data, known as tx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format. rx8 this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data, known as rx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format. txbrk the txbrk bit is the transmit break character bit. when this bit is 0 there are no break characters and the tx pin operates normally. when the bit is 1 there are transmit break characters and the transmitter will send logic zeros. when equal to 1 after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the txbrk bit is reset. stops this bit determines if one or two stop bits are to be used. when this bit is equal to 1 two stop bits are used, if the bit is equal to 0 then only one stop bit is used. prt this is the parity type selection bit. when this bit is equal to 1 odd parity will be selected, if the bit is equal to 0 then even parity will be selected. pren this is parity enable bit. when this bit is equal to 1 the parity function will be enabled, if the bit is equal to 0 then the parity function will be disabled. bno this bit is used to select the data length format, which can have a choice of either 8-bits or 9-bits. if this bit is equal to 1 then a 9-bit data length will be selected, if the bit is equal to 0 then an 8-bit data length will be selected. if 9-bit data length is se - lected then bits rx8 and tx8 will be used to store the 9th bit of the received and transmitted data re - spectively. uarten the uarten bit is the uart enable bit. when the bit is 0 the uart will be disabled and the rx and tx pins will function as general purpose i/o pins. when the bit is 1 the uart will be enabled and the tx and rx pins will function as defined by the txen and rxen control bits. when the uart is disabled it will empty the buffer so any character re- maining in the buffer will be discarded. in addition, the baud rate counter value will be reset. when the uart is disabled, all error and status flags will be reset. the txen, rxen, txbrk, rxif, oerr, ferr, perr, and nf bits will be cleared, while the tidle, txif and ridle bits will be set. other con- trol bits in ucr1, ucr2, and brg registers will re- main unaffected. if the uart is active and the uarten bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. when the uart is re-enabled it will restart in the same configuration.
ht49ru80/ht49cu80 rev. 1.40 30 july 30, 2012
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( c ? ) 3 ucr2 register the ucr2 register is the second of the two uart control registers and serves several purposes. one of its main functions is to control the basic enable/dis - able operation of the uart transmitter and receiver as well as enabling the various uart interrupt sources. the register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. further explanation on each of the bits is given below: teie this bit enables or disables the transmitter empty interrupt. if this bit is equal to 1 when the transmit - ter empty txif flag is set, due to a transmitter empty condition, the uart interrupt request flag will be set. if this bit is equal to 0 the uart inter - rupt request flag will not be influenced by the condi - tion of the txif flag. tiie this bit enables or disables the transmitter idle in - terrupt. if this bit is equal to 1 when the transmitter idle tidle flag is set, the uart interrupt request flag will be set. if this bit is equal to 0 the uart in - terrupt request flag will not be influenced by the condition of the tidle flag. rie this bit enables or disables the receiver interrupt. if this bit is equal to 1 when the receiver overrun oerr flag or receive data available rxif flag is set, the uart interrupt request flag will be set. if this bit is equal to 0 the uart interrupt will not be influenced by the condition of the oerr or rxif flags. wake this bit enables or disables the receiver wake-up function. if this bit is equal to 1 and if the mcu is in the power down mode, a low going edge on the rx input pin will wake-up the device. if this bit is equal to 0 and if the mcu is in the power down mode, any edge transitions on the rx pin will not wake-up the device. adden the adden bit is the address detect mode bit. when this bit is 1 the address detect mode is en - abled. when this occurs, if the 8th bit, which corre - sponds to rx7 if bno=0, or the 9th bit, which corresponds to rx8 if bno=1, has a value of 1 then the received word will be identified as an ad - dress, rather than data. if the corresponding inter - rupt is enabled, an interrupt request will be generated each time the received word has the ad - dress bit set, which is the 8 or 9 bit depending on the value of bno. if the address bit is 0 an interrupt will not be generated, and the received data will be discarded. brgh the brgh bit selects the high or low speed mode of the baud rate generator. this bit, together with the value placed in the brg register, controls the baud rate of the uart. if this bit is equal to 1 the high speed mode is selected. if the bit is equal to 0 the low speed mode is selected. rxen the rxen bit is the receiver enable bit. when this bit is equal to 0 the receiver will be disabled with any pending data receptions being aborted. in addi- tion the buffer will be reset. in this situation the rx pin can be used as a general purpose i/o pin. if the rxen bit is equal to 1 the receiver will be enabled and if the uarten bit is equal to 1 the rx pin will be controlled by the uart. clearing the rxen bit during a transmission will cause the data reception to be aborted and will reset the receiver. if this oc- curs, the rx pin can be used as a general purpose i/o pin.
ht49ru80/ht49cu80 rev. 1.40 31 july 30, 2012 txen the txen bit is the transmitter enable bit. when this bit is equal to 0 the transmitter will be disabled with any pending transmissions being aborted. in addition the buffer will be reset. in this situation the tx pin can be used as a general purpose i/o pin. if the txen bit is equal to 1 the transmitter will be enabled and if the uarten bit is equal to 1 the tx pin will be controlled by the uart. clearing the txen bit during a transmission will cause the trans - mission to be aborted and will reset the transmitter. if this occurs, the tx pin can be used as a general purpose i/o pin. baud rate generator to setup the speed of the serial data communication, the uart function contains its own dedicated baud rate generator. the baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. the first of these is the value placed in the brg register and the second is the value of the brgh bit within the ucr2 control regis - ter. the brgh bit decides, if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. the value in the brg register determines the division factor, n, which is used in the following baud rate calculation formula. note that n is the decimal value placed in the brg register and has a range of between 0 and 255. ucr2 brgh bit 0 1 baud rate f [64 (n + 1)] sys f [16 (n + 1)] sys by programming the brgh bit which allows selection of the related formula and programming the required value in the brg register, the required baud rate can be setup. note that because the actual baud rate is determined using a discrete value, n, placed in the brg register, there will be an error associated be - tween the actual and requested value. the following example shows how the brg register value n and the error value can be calculated. calculating the register and error values for a clock frequency of 8mhz, and with brgh set to 0 determine the brg register value n, the actual baud rate and the error value for a desired baud rate of 9600. from the above table the desired baud rate br f [64 (n + 1)] sys re-arranging this equation gives n f (brx64) sys 1 giving a value for n 8000000 9600 64 () x 1 12.0208 to obtain the closest value, a decimal value of 12 should be placed into the brg register. this gives an actual or calculated baud rate value of br 8000000 [64(12 + 1)] 9615 therefore the error is equal to = 0.16% 9 1 6 ( 9 1 - - 9 1 - - the following tables show actual values of baud rate and error values for the two values of brgh. baud rate k/bps baud rates for brgh=0 f sys =8mhz f sys =7.159mhz f sys =4mhz f sys =3.579545mhz brg kbaud error brg kbaud error brg kbaud error brg kbaud error 0.3 207 0.300 0.00 185 0.300 0.00 1.2 103 1.202 0.16 92 1.203 0.23 51 1.202 0.16 46 1.19 -0.83 2.4 51 2.404 0.16 46 2.38 -0.83 25 2.404 0.16 22 2.432 1.32 4.8 25 4.807 0.16 22 4.863 1.32 12 4.808 0.16 11 4.661 -2.9 9.6 12 9.615 0.16 11 9.322 -2.9 6 8.929 -6.99 5 9.321 -2.9 19.2 6 17.857 -6.99 5 18.64 -2.9 2 20.83 8.51 2 18.643 -2.9 38.4 2 41.667 8.51 2 37.29 -2.9 1 1 57.6 1 62.5 8.51 1 55.93 -2.9 0 62.5 8.51 0 55.93 -2.9 115.2 0 125 8.51 0 111.86 -2.9 baud rates and error values for brgh 0
ht49ru80/ht49cu80 rev. 1.40 32 july 30, 2012 baud rate k/bps baud rates for brgh=1 f sys =8mhz f sys =7.159mhz f sys =4mhz f sys =3.579545mhz brg kbaud error brg kbaud error brg kbaud error brg kbaud error 0.3 1.2 207 1.202 0.16 185 1.203 0.23 2.4 207 2.404 0.16 185 2.405 0.23 103 2.404 0.16 92 2.406 0.23 4.8 103 4.808 0.16 92 4.811 0.23 51 4.808 0.16 46 4.76 -0.83 9.6 51 9.615 0.16 46 9.520 -0.832 25 9.615 0.16 22 9.727 1.32 19.2 25 19.231 0.16 22 19.454 1.32 12 19.231 0.16 11 18.643 -2.9 38.4 12 38.462 0.16 11 37.287 -2.9 6 35.714 -6.99 5 37.286 -2.9 57.6 8 55.556 -3.55 7 55.93 -2.9 3 62.5 8.51 3 55.930 -2.9 115.2 3 125 8.51 3 111.86 -2.9 1 125 8.51 1 111.86 -2.9 250 1 250 0 0 250 0 baud rates and error values for brgh 1 setting up and controlling the uart introduction for data transfer, the uart function utilizes a non-return-to-zero, more commonly known as nrz, format. this is composed of one start bit, eight or nine data bits, and one or two stop bits. parity is supported by the uart hardware, and can be setup to be even, odd or no parity. for the most common data format, 8 data bits along with no par- ity and one stop bit, denoted as 8, n, 1, is used as the default setting, which is the setting at power-on. the number of data bits and stop bits, along with the parity, are setup by programming the corresponding bno, prt, pren, and stops bits in the ucr1 register. the baud rate used to transmit and receive data is setup using the internal 8-bit baud rate gen - erator, while the data is transmitted and received lsb first. although the uarts transmitter and re - ceiver are functionally independent, they both use the same data format and baud rate. in all cases stop bits will be used for data transmission. enabling/disabling the uart the basic on/off function of the internal uart func - tion is controlled using the uarten bit in the ucr1 register. as the uart transmit and receive pins, tx and rx respectively, are pin-shared with normal i/o pins, one of the basic functions of the uarten con - trol bit is to control the uart function of these two pins. if the uarten, txen and rxen bits are set, then these two i/o pins will be setup as a tx output pin and an rx input pin respectively, in effect dis - abling the normal i/o pin function. if no data is being transmitted on the tx pin then it will default to a logic high value. clearing the uarten bit will disable the tx and rx pins and allow these two pins to be used as normal i/o pins. when the uart function is disabled the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. disabling the uart will also reset the error and sta- tus flags with bits txen, rxen, txbrk, rxif, oerr, ferr, perr and nf being cleared while bits tidle, txif and ridle will be set. the remain- ing control bits in the ucr1, ucr2 and brg regis- ters will remain unaffected. if the uarten bit in the ucr1 register is cleared while the uart is active, then all pending transmissions and receptions will be immediately suspended and the uart will be re- set to a condition as defined above. if the uart is then subsequently re-enabled, it will restart again in the same configuration. data, parity and stop bit selection the format of the data to be transferred, is com - posed of various factors such as data bit length, parity on/off, parity type, address bits and the num - ber of stop bits. these factors are determined by the setup of various bits within the ucr1 register. the bno bit controls the number of data bits which can be set to either 8 or 9, the prt bit controls the choice of odd or even parity, the pren bit controls the parity on/off function and the stops bit decides whether one or two stop bits are to be used. the fol - lowing table shows various formats for data trans - mission. the address bit identifies the frame as an address character. the number of stop bits, which can be either one or two, is independent of the data length.
ht49ru80/ht49cu80 rev. 1.40 33 july 30, 2012 ( ) ) ( - ) ( ) ( ) ( ) ( ) ( 6 ) ( 1 ) ( 0 ( ) ! < ) ( ) ( ( ) ) ( - ) ( ) ( ) ( ) ( ) ( 6 ) ( 1 ) ( 0 ( ) ! < ) ( ) ( ) ( 8 start bit data bits address bits parity bits stop bit example of 8-bit data formats 18001 17011 171 1 01 example of 9-bit data formats 19001 18011 181 1 01 transmitter receiver data format the following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. uart transmitter data word lengths of either 8 or 9 bits, can be selected by programming the bno bit in the ucr1 register. when bno bit is set, the word length will be set to 9 bits. in this case the 9th bit, which is the msb, needs to be stored in the tx8 bit in the ucr1 register. at the transmitter core lies the transmitter shift register, more commonly known as the tsr, whose data is ob - tained from the transmit data register, which is known as the txr register. the data to be transmitted is loaded into this txr register by the application pro- gram. the tsr register is not written to with new data until the stop bit from the previous transmission has been sent out. as soon as this stop bit has been trans- mitted, the tsr can then be loaded with new data from the txr register, if it is available. it should be noted that the tsr register, unlike many other regis- ters, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. an actual transmis- sion of data will normally be enabled when the txen bit is set, but the data will not be transmitted until the txr register has been loaded with data and the baud rate generator has defined a shift clock source. how - ever, the transmission can also be initiated by first loading data into the txr register, after which the txen bit can be set. when a transmission of data be - gins, the tsr is normally empty, in which case a transfer to the txr register will result in an immediate transfer to the tsr. if during a transmission the txen bit is cleared, the transmission will immediately cease and the transmitter will be reset. the tx output pin will then return to having a normal general purpose i/o pin function. transmitting data when the uart is transmitting data, the data is shifted on the tx pin from the shift register, with the least significant bit first. in the transmit mode, the txr register forms a buffer between the internal bus and the transmitter shift register. it should be noted that if 9-bit data format has been selected, then the msb will be taken from the tx8 bit in the ucr1 register. the steps to initiate a data transfer can be summarized as follows: make the correct selection of the bno, prt, pren and stops bits to define the required word length, parity type and number of stop bits. setup the brg register to select the desired baud rate. set the txen bit to ensure that the tx pin is used as a uart transmitter pin and not as an i/o pin. access the usr register and write the data that is to be transmitted into the txr register. note that this step will clear the txif bit. this sequence of events can now be repeated to send additional data. it should be noted that when txif=0, data will be in - hibited from being written to the txr register. clear - ing the txif flag is always achieved using the following software sequence: 1. a usr register access 2. a txr register write execution the read-only txif flag is set by the uart hard- ware and if set indicates that the txr register is empty and that other data can now be written into the txr register without overwriting the previous data. if the teie bit is set then the txif flag will gen- erate an interrupt. during a data transmission, a write instruction to the txr register will place the data into the txr regis - ter, which will be copied to the shift register at the end of the present transmission. when there is no data transmission in progress, a write instruction to the txr register will place the data directly into the shift register, resulting in the commencement of data transmission, and the txif bit being immedi - ately set. when a frame transmission is complete, which happens after stop bits are sent or after the break frame, the tidle bit will be set. to clear the tidle bit the following software sequence is used: 1. a usr register access 2. a txr register write execution note that both the txif and tidle bits are cleared by the same software sequence.
ht49ru80/ht49cu80 rev. 1.40 34 july 30, 2012 transmit break if the txbrk bit is set then break characters will be sent on the next transmission. break character transmission consists of a start bit, followed by 13 n 0 bits and stop bits, where n=1, 2, etc. if a break character is to be transmitted then the txbrk bit must be first set by the application program, then cleared to generate the stop bits. transmitting a break character will not generate a transmit inter - rupt. note that a break condition length is at least 13 bits long. if the txbrk bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. after the ap - plication program has cleared the txbrk bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. the automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized. uart receiver introduction the uart is capable of receiving word lengths of ei - ther 8 or 9 bits. if the bno bit is set, the word length will be set to 9 bits with the msb being stored in the rx8 bit of the ucr1 register. at the receiver core lies the receive serial shift register, commonly known as the rsr. the data which is received on the rx external input pin, is sent to the data recovery block. the data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. after the rx pin is sampled for the stop bit, the received data in rsr is transferred to the receive data register, if the register is empty. the data which is received on the external rx input pin is sampled three times by a majority de- tect circuit to determine the logic level that has been placed onto the rx pin. it should be noted that the rsr register, unlike many other registers, is not di - rectly mapped into the data memory area and as such is not available to the application program for direct read/write operations. receiving data when the uart receiver is receiving data, the data is serially shifted in on the external rx input pin, lsb first. in the read mode, the rxr register forms a buffer between the internal bus and the receiver shift register. the rxr register is a two byte deep fifo data buffer, where two bytes can be held in the fifo while a third byte can continue to be received. note that the application program must ensure that the data is read from rxr before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error oerr will be subsequently indicated. the steps to initiate a data transfer can be summarized as follows: make the correct selection of bno, prt, pren and stops bits to define the word length, parity type and number of stop bits. setup the brg register to select the desired baud rate. set the rxen bit to ensure that the rx pin is used as a uart receiver pin and not as an i/o pin. at this point the receiver will be enabled which will begin to look for a start bit. when a character is received the following se - quence of events will occur: the rxif bit in the usr register will be set when rxr register has data available, at least one more character can be read. when the contents of the shift register have been transferred to the rxr register, then if the rie bit is set, an interrupt will be generated. if during reception, a frame error, noise error, par - ity error, or an overrun error has been detected, then the error flags can be set. the rxif bit can be cleared using the following software sequence: 1. a usr register access 2. an rxr register read execution receive break any break character received by the uart will be managed as a framing error. the receiver will count and expect a certain number of bit times as speci - fied by the values programmed into the bno and stops bits. if the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by bno and stops. the rxif bit is set, ferr is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the ridle bit is set. if a long break signal has been detected and the re- ceiver has received a start bit, the data bits and the invalid stop bit, which sets the ferr flag, the re- ceiver must wait for a valid stop bit before looking for the next start bit. the receiver will not make the assumption that the break condition on the line is the next start bit. a break is regarded as a character that contains only zeros with the ferr flag set. the break character will be loaded into the buffer and no further data will be received until stop bits are re - ceived. it should be noted that the ridle read only flag will go high when the stop bits have not yet been received. the reception of a break character on the uart registers will result in the following: the framing error flag, ferr, will be set. the receive data register, rxr, will be cleared. the oerr, nf, perr, ridle or rxif flags will possibly be set. idle status when the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the usr register, otherwise known as the ridle flag, will have a zero value. in between the reception of a stop bit and the detection of the next start bit, the ridle flag will have a high value, which indicates the receiver is in an idle condition.
ht49ru80/ht49cu80 rev. 1.40 35 july 30, 2012 receiver interrupt the read only receive interrupt flag rxif in the usr register is set by an edge generated by the receiver. an interrupt is generated if rie=1, when a word is transferred from the receive shift register, rsr, to the receive data register, rxr. an overrun error can also generate an interrupt if rie=1. managing receiver errors several types of reception errors can occur within the uart module, the following section describes the various types and how they are managed by the uart. overrun error oerr flag the rxr register is composed of a two byte deep fifo data buffer, where two bytes can be held in the fifo register, while a third byte can continue to be received. before this third byte has been entirely shifted in, the data should be read from the rxr register. if this is not done, the overrun error flag oerr will be consequently indicated. in the event of an overrun error occurring, the fol - lowing will happen: the oerr flag in the usr register will be set. the rxr contents will not be lost. the shift register will be overwritten. an interrupt will be generated if the rie bit is set. the oerr flag can be cleared by an access to the usr register followed by a read to the rxr register. noise error nf flag over-sampling is used for data recovery to identify valid incoming data and noise. if noise is detected within a frame the following will occur: the read only noise flag, nf, in the usr register will be set on the rising edge of the rxif bit. data will be transferred from the shift register to the rxr register. no interrupt will be generated. however this bit rises at the same time as the rxif bit which itself generates an interrupt. note that the nf flag is reset by a usr register read operation followed by an rxr register read operation. framing error ferr flag the read only framing error flag, ferr, in the usr register, is set if a zero is detected instead of stop bits. if two stop bits are selected, both stop bits must be high, otherwise the ferr flag will be set. the ferr flag is buffered along with the received data and is cleared on any reset. parity error perr flag the read only parity error flag, perr, in the usr register, is set if the parity of the received word is in - correct. this error flag is only applicable if the parity is enabled, pren = 1, and if the parity type, odd or even is selected. the read only perr flag is buf - fered along with the received data bytes. it is cleared on any reset. it should be noted that the ferr and perr flags are buffered along with the corresponding word and should be read before reading the data word. uart interrupt scheme the uart internal function possesses its own internal interrupt and independent interrupt vector. several in - dividual uart conditions can generate an internal uart interrupt. these conditions are, a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an rx pin wake-up. when any of these conditions are cre- ated, if the uart interrupt is enabled and the stack is not full, the program will jump to the uart interrupt vector where it can be serviced before returning to the main program. four of these conditions, have a corre- sponding usr register flag, which will generate a uart interrupt if its associated interrupt enable flag in " (
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ht49ru80/ht49cu80 rev. 1.40 36 july 30, 2012 the ucr2 register is set. the two transmitter interrupt conditions have their own corresponding enable bits, while the two receiver interrupt conditions have a shared enable bit. these enable bits can be used to mask out individual uart interrupt sources. the address detect condition, which is also a uart interrupt source, does not have an associated flag, but will generate a uart interrupt when an address detect condition occurs if its function is enabled by setting the adden bit in the ucr2 register. an rx pin wake-up, which is also a uart interrupt source, does not have an associated flag, but will generate a uart interrupt if the microcontroller is woken up by a low go - ing edge on the rx pin, if the wake and rie bits in the ucr2 register are set. note that in the event of an rx wake-up interrupt occurring, there will be a delay of 1024 system clock cycles before the system re - sumes normal operation. note that the usr register flags are read only and cannot be cleared or set by the application program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the case for some of the other interrupts. the flags will be cleared automatically when certain actions are taken by the uart, the details of which are given in the uart register section. the overall uart interrupt can be disabled or enabled by the euri bit in the intc1 interrupt control register to prevent a uart in - terrupt from occurring. address detect mode setting the address detect mode bit, adden, in the ucr2 register, enables this special mode. if this bit is enabled then an additional qualifier will be placed on the generation of a receiver data available interrupt, which is requested by the rxif flag. if the adden bit is enabled, then when data is available, an interrupt will only be generated, if the highest received bit has a high value. note that the euri and emi interrupt en- able bits must also be enabled for correct interrupt generation. this highest address bit is the 9th bit if bno=1 or the 8th bit if bno=0. if this bit is high, then the received word will be defined as an address rather than data. a data available interrupt will be generated every time the last bit of the received word is set. if the adden bit is not enabled, then a receiver data avail - able interrupt will be generated each time the rxif flag is set, irrespective of the data last bit status. the address detect mode and parity enable are mutually exclusive functions. therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the par - ity enable bit to zero. adden bit 9 if bno=1, bit 8 if bno=0 uart interrupt generated 0 0 1 1 0x 1 adden bit function uart operation in power down mode when the mcu is in the power down mode the uart will cease to function. when the device enters the power down mode, all clock sources to the module are shutdown. if the mcu enters the power down mode while a transmission is still in progress, then the transmission will be terminated and the external tx transmit pin will be forced to a logic high level. in a similar way, if the mcu enters the power down mode while receiving data, then the reception of data will likewise be terminated. when the mcu enters the power down mode, note that the usr, ucr1, ucr2, transmit and receive registers, as well as the brg register will not be affected. the uart function contains a receiver rx pin wake-up function, which is enabled or disabled by the wake bit in the ucr2 register. if this bit, along with the uart enable bit, uarten, the receiver enable bit, rxen and the receiver interrupt bit, rie, are all set before the mcu enters the power down mode, then a falling edge on the rx pin will wake-up the mcu from the power down mode. note that as it takes 1024 sys- tem clock cycles after a wake-up, before normal microcontroller operation resumes, any data received during this time on the rx pin will be ignored. for a uart wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global interrupt enable bit, emi, and the uart interrupt enable bit, euri must also be set. if these two bits are not set then only a wake up event will occur and no interrupt will be generated. note also that as it takes 1024 sys - tem clock cycles after a wake-up before normal microcontroller resumes, the uart interrupt will not be generated until after this time has elapsed.
ht49ru80/ht49cu80 rev. 1.40 37 july 30, 2012 configuration options the following shows the options in the device. all these options should be defined in order to ensure proper functioning system. configuration options refer to certain options within the mcu that are programmed into the device during the programming process. during the development process, these options are selected using the ht-ide software devel - opment tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later as the application software has no control over the configuration options. all op - tions must be defined for proper system function, the details of which are shown in the table. options i/o options pa0~pa7 wake-up enable/disable pa0~pa3 cmos/nmos selection pa0~pa3 pull-high enable/disable pc0~pc3 cmos/nmos selection pc4~pc7 cmos/nmos selection pc0~pc3 pull-high enable/disable pc4~pc7 pull-high enable/disable watchdog options wdt function: enable or disable clrwdt instructions: one or instructions oscillator options osc type selection: rc or crystal fsys clock source: osc or rtc fs internal clock source: f sys /4, rtc osc or wdt osc pfd options pfd output enable: enable or disable pfd clock selection: timer/event counter 0 or timer/event counter 1 timer options timer/event counter 0 clock source: f sys /4 or f sys timer/event counter 1 clock source: timer/event counter 0 overflow, time base out or f sys timer base options time base frequency: f s /2 12 ~f s /2 15 buzzer options buzzer output enable: enable or disable buzzer frequency : f s /2 2 ~f s /2 9 lvd/lvr options lvr function reset: enable or disable low voltage detect: enable or disable lcd options lcd clock: f s /2 2 ~f s /2 8 lcd duty: 1 / 2, 1 / 3, 1 / 4 lcd bias: 1 / 2, 1 / 3 lcd bias type: r type or c type lcd on/off during power down: enable or disable lcd segment seg40~seg46 output or pd0~pd6 output halt mode oscillator enable or disable
application circuits the following table shows the c1, c2 and r1 values corresponding to the different crystal values. (for reference only) crystal or resonator c1, c2 r1 4mhz crystal 0pf 12k
4mhz resonator 10pf 12k
3.58mhz crystal 0pf 12k
3.58mhz resonator 25pf 12k
2mhz crystal & resonator 25pf 12k
1mhz crystal 35pf 14k
480khz resonator 100pf 14k
455khz resonator 200pf 12k
429khz resonator 200pf 12k
400khz resonator 300pf 12k
the function of the resistor r1 is to ensure that the oscillator will switch off should low voltage condi - tions occur. such a low voltage, as mentioned here, is one which is less than the lowest value of the mcu operating voltage. note however that if the lvr is enabled then r1 can be removed. note: the resistance and capacitance for reset circuit should be designed in such a way as to ensure that the vdd is stable and remains within a valid operating voltage range before bringing res to high. * make the length of the wiring, which is connected to the res pin as short as possible, to avoid noise interference. ht49ru80/ht49cu80 rev. 1.40 38 july 30, 2012 0 1 8 3 b - 5 + , ) ' - a 5 g - - @ - a 5 - a - 5 g - @ ' 4 / 0 - 5 - +

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ht49ru80/ht49cu80 rev. 1.40 39 july 30, 2012 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits.
ht49ru80/ht49cu80 rev. 1.40 40 july 30, 2012 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z
ht49ru80/ht49cu80 rev. 1.40 41 july 30, 2012 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z ht49ru80/ht49cu80 rev. 1.40 42 july 30, 2012
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf ht49ru80/ht49cu80 rev. 1.40 43 july 30, 2012
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf ht49ru80/ht49cu80 rev. 1.40 44 july 30, 2012
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z ht49ru80/ht49cu80 rev. 1.40 45 july 30, 2012
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none ht49ru80/ht49cu80 rev. 1.40 46 july 30, 2012
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c ht49ru80/ht49cu80 rev. 1.40 47 july 30, 2012
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none ht49ru80/ht49cu80 rev. 1.40 48 july 30, 2012
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c ht49ru80/ht49cu80 rev. 1.40 49 july 30, 2012
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none ht49ru80/ht49cu80 rev. 1.40 50 july 30, 2012
xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z ht49ru80/ht49cu80 rev. 1.40 51 july 30, 2012
package information note that the package information provided here is for consultation purposes only. as this information may be updated at regu - lar intervals users are reminded to consult the holtek website ( http://www.holtek.com.tw/english/literature/package.pdf ) for the latest version of the package information. 64-pin lqfp (7mm 7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.350 0.358 b 0.272 0.280 c 0.350 0.358 d 0.272 0.280 e 0.016 f 0.005 0.009 g 0.053 0.057 h 0.063 i 0.002 0.006 j 0.018 0.030 k 0.004 0.008 07 symbol dimensions in mm min. nom. max. a 8.90 9.10 b 6.90 7.10 c 8.90 9.10 d 6.90 7.10 e 0.40 f 0.13 0.23 g 1.35 1.45 h 1.60 i 0.05 0.15 j 0.45 0.75 k 0.09 0.20 07 ht49ru80/ht49cu80 rev. 1.40 52 july 30, 2012 8 9 1 1 0 $ ) 5 3 m +
100-pin lqfp (14mm 14mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.626 0.634 b 0.547 0.555 c 0.626 0.634 d 0.547 0.555 e 0.020 f 0.008 g 0.053 0.057 h 0.063 i 0.004 j 0.018 0.030 k 0.004 0.008 07 symbol dimensions in mm min. nom. max. a 15.90 16.10 b 13.90 14.10 c 15.90 16.10 d 13.90 14.10 e 0.50 f 0.20 g 1.35 1.45 h 1.60 i 0.10 j 0.45 0.75 k 0.10 0.20 07 ht49ru80/ht49cu80 rev. 1.40 53 july 30, 2012 - - 6 $ ) 6 - 1 5 3 m + 6 0 6 0 1
ht49ru80/ht49cu80 rev. 1.40 54 july 30, 2012 copyright 2012 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com

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