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? semiconductor components industries, llc, 2011 october, 2011 ? rev. 3 1 publication order number: ncv7340/d ncv7340 high speed low power can transceiver description the ncv7340 can transceiver is the interface between a controller area network (can) protocol controller and the physical bus and may be used in both 12 v and 24 v systems. the transceiver provides differential transmit capability to the bus and differential receive capability to the can controller. the ncv7340 is a new addition to the can high ? speed transceiver family and is an improved drop ? in replacement for the amis ? 42665. due to the wide common ? mode voltage range of the receiver inputs, the ncv7340 is able to reach outstanding levels of electromagnetic susceptibility (ems). similarly, extremely low electromagnetic emission (eme) is achieved by the excellent matching of the output signals. features ? compatible with the iso 1 1898 standard (iso 11898 ? 2, iso 11898 ? 5 and sae j2284) ? low quiescent current ? high speed (up to 1 mbps) ? ideally suited for 12 v and 24 v industrial and automotive applications ? extremely low current standby mode with wakeup via the bus ? low eme common ? mode choke is no longer required ? voltage source via v split pin for stabilizing the recessive bus level (further emc improvement) ? no disturbance of the bus lines with an un ? powered node ? transmit data (txd) dominant time ? out function ? thermal protection ? bus pins protected against transients in an automotive environment ? bus and v split pins short ? circuit proof to supply voltage and ground ? logic level inputs compatible with 3.3 v devices ? up to 110 nodes can be connected to the same bus in function of topology ? these are pb ? free devices typical applications ? automotive ? industrial networks http://onsemi.com (top view) 5 6 7 8 1 2 3 4 txd rxd stb gnd canl ncv7340 see detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. ordering information v cc v split canh 1 8 soic ? 8 case 751az pin assignment
ncv7340 http://onsemi.com 2 table 1. key technical characteristics and operating ranges symbol parameter conditions min max unit v cc power supply voltage 4.75 5.25 v v stb dc voltage at pin stb 0 v cc v v txd dc voltage at pin txd 0 v cc v v rxd dc voltage at pin rxd 0 v cc v v canh dc voltage at pin canh 0 < v cc < 5.25 v; no time limit ? 50 +50 v v canl dc voltage at pin canl 0 < v cc < 5.25 v; no time limit ? 50 +50 v v split dc voltage at pin v split 0 < v cc < 5.25 v; no time limit ? 40 +40 v v o(dif)(bus_dom) differential bus output voltage in dominant state 42.5 < r lt < 60 1.5 3 v cm ? range input common ? mode range for comparator guaranteed differential receiver threshold and leakage current ? 35 +35 v c load load capacitance on ic outputs 15 pf t pd(rec ? dom) propagation delay txd to rxd see figure 7 75 230 ns t pd(dom ? rec) propagation delay txd to rxd see figure 7 75 245 ns t j junction temperature ? 40 150 c block diagram v split mode & wakeup control wakeup filter ncv7340 stb gnd rxd v cc 2 3 7 6 comp comp 5 timer vcc txd 1 driver control thermal shutdown vcc 8 4 v split vcc por canh canl figure 1. block diagram
ncv7340 http://onsemi.com 3 typical application application schematics ncv7340 v cc stb rxd txd 1 4 can controller gnd v cc vbat 5v ? reg in out gnd 2 3 8 canh canl v split 5 6 7 can bus r lt =60 r lt =60 c lt =47nf figure 2. application diagram pin description 5 6 7 8 1 2 3 4 txd rxd stb v split gnd canl canh vcc ncv7340 figure 3. ncv7340 pin assignment table 2. pin function description pin name description 1 txd transmit data input; low input dominant driver; internal pullup current 2 gnd ground 3 vcc supply voltage 4 rxd receive data output; dominant transmitter low output 5 v split common ? mode stabilization output 6 canl low ? level can bus line (low in dominant mode) 7 canh high ? level can bus line (high in dominant mode) 8 stb standby mode control input
ncv7340 http://onsemi.com 4 functional description operating modes ncv7340 provides two modes of operation as illustrated in table 3. these modes are selectable through pin stb. table 3. operating modes pin stb mode pin rxd low high low normal bus dominant bus recessive high standby wakeup request detected no wakeup request detected normal mode in the normal mode, the transceiver is able to communicate via the bus lines. the signals are transmitted and received to the can controller via the pins txd and rxd. the slopes on the bus lines outputs are optimized to give extremely low eme. standby mode in standby mode both the transmitter and receiver are disabled and a very low ? power differential receiver monitors the bus lines for can bus activity. the bus lines are terminated to ground and supply current is reduced to a minimum, typically 10 a. when a wake ? up request is detected by the low ? power differential receiver, the signal is first filtered and then verified as a valid wake signal after a time period of t dbus , the rxd pin is driven low by the transceiver to inform the controller of the wake ? up request. split circuit the v split pin is operational only in normal mode. in standby mode this pin is floating. the v split can be connected as shown in figure 2 or, if it?s not used, can be left floating. its purpose is to provide a stabilized dc voltage of 0.5 x v cc to the bus avoiding possible steps in the common ? mode signal therefore reducing eme. these unwanted steps could be caused by an un ? powered node on the network with excessive leakage current from the bus that shifts the recessive voltage from its nominal 0.5 x v cc voltage. wakeup when a valid wakeup (dominant state longer than t dbus ) is received during the standby mode the rxd pin is driven low. the wakeup detection is not latched: rxd returns to high state after t dbus when the bus signal is released back to recessive ? see figure 4. wake ? up behavior in case of a permanent dominant ? due to, for example, a bus short ? represents the only dif ference between the circuit functional sub ? versions listed in the ordering information table. when the standby mode is entered while a dominant is present on the bus, the ?unconditioned bus wake ? up? versions will signal a bus ? wakeup immediately after the state transition (signal rxd 1 in figure 4). the other version will signal bus ? wakeup only after the initial dominant is released (signal rxd 2 in figure 4). in this way it?s ensured, that a can bus can be put to a low ? power mode even if the nodes have a level sensitivity to rxd pin and a permanent dominant is present on the bus. figure 4. ncv7340 wakeup behavior time canh canl stb rxd 1 normal standby t dbus t dbus rxd 2 pd20100520.01 overtemperature detection a thermal protection circuit protects the ic from damage by switching off the transmitter if the junction temperature exceeds a value of approximately 160 c. because the transmitter dissipates most of the power, the power dissipation and temperature of the ic is reduced. all other ic functions continue to operate. the transmitter off ? state resets when the temperature decreases below the shutdown threshold and pin txd goes high. the thermal protection circuit is particularly needed when a bus line short circuits. txd dominant time ? out function a txd dominant time ? out timer circuit prevents the bus lines being driven to a permanent dominant state (blocking all network communication) if pin txd is forced permanently low by a hardware and/or software application failure. the timer is triggered by a negative edge on pin txd. if the duration of the low ? level on pin txd exceeds the
ncv7340 http://onsemi.com 5 internal timer value t dom(txd) , the transmitter is disabled, driving the bus into a recessive state. the timer is reset by a positive edge on pin txd. this txd dominant time ? out time (t dom(txd) ) defines the minimum possible bit rate to 40 kbps. fail safe features a current ? limiting circuit protects the transmitter output stage from damage caused by accidental short circuit to either positive or negative supply voltage, although power dissipation increases during this fault condition. the pins canh and canl are protected from automotive electrical transients (according to iso 7637; see figure 5). pins txd and stb are pulled high internally should the input become disconnected. pins txd, stb and rxd will be floating, preventing reverse supply should the v cc supply be removed. electrical characteristics definitions all voltages are referenced to gnd (pin 2). positive currents flow into the ic. sinking current means the current is flowing into the pin; sourcing current means the current is flowing out of the pin. absolute maximum ratings table 4. absolute maximum ratings symbol parameter conditions min max unit v cc supply voltage ? 0.3 +6 v v canh dc voltage at pin canh 0 < v cc < 5.25 v; no time limit ? 50 +50 v v canl dc voltage at pin canl 0 < v cc < 5.25 v; no time limit ? 50 +50 v v split dc voltage at pin v split 0 < v cc < 5.25 v; no time limit ? 40 +40 v v txd dc voltage at pin txd ? 0.3 6 v v rxd dc voltage at pin rxd ? 0.3 6 v v stb dc voltage at pin stb ? 0.3 6 v v esd electrostatic discharge voltage at all pins note 1 note 2 ? 6 ? 500 6 500 kv v electrostatic discharge voltage at canh and canl pins note 3 ? 12 12 kv latchup static latchup at all pins note 4 120 ma t stg storage temperature ? 55 +150 c t a ambient temperature ? 40 +125 c t j maximum junction temperature ? 40 +170 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. standardized human body model electrostatic discharge (esd) pulses in accordance to eia ? jesd22. equivalent to discharging a 100 pf capacitor through a 1.5 k resistor. 2. standardized charged device model esd pulses when tested according to esd ? stm5.3.1 ? 1999. 3. system human body model electrostatic discharge (esd) pulses. equivalent to discharging a 150 pf capacitor through a 330 resistor. 4. static latchup immunity: static latchup protection level when tested according to eia/jesd78.
ncv7340 http://onsemi.com 6 table 5. characteristics v cc = 4.75 v to 5.25 v; t j = ? 40 to +150 c; r lt = 60 unless specified otherwise. symbol parameter conditions min typ max unit supply (pin v cc ) i cc supply current dominant; v txd = 0 v recessive; v txd = v cc 35 5 75 10 ma i ccs supply current in standby mode t j,max = 100 c 10 15 a transmitter data input (pin txd) v ih high ? level input voltage output recessive 2.0 ? v cc v v il low ? level input voltage output dominant ? 0.3 ? +0.8 v i ih high ? level input current v txd = v cc ? 5 0 +5 a i il low ? level input current v txd = 0 v ? 350 ? 200 ? 75 a c i input capacitance not tested ? 5 10 pf transmitter mode select (pin stb) v ih high ? level input voltage standby mode 2.0 ? v cc v v il low ? level input voltage normal mode ? 0.3 ? +0.8 v i ih high ? level input current v stb = v cc ? 5 0 +5 a i il low ? level input current v stb = 0 v ? 10 ? 4 ? 1 a c i input capacitance not tested ? 5 10 pf receiver data output (pin rxd) i oh high ? level output current normal mode v rxd = v cc ? 0.4 v ? 1 ? 0.4 ? 0.1 ma i ol low ? level output current v rxd = 0.4 v 2 6 12 ma v oh high ? level output voltage standby mode i rxd = ? 100 a v cc ? 1.1 v cc ? 0.7 v cc ? 0.4 v bus lines (pins canh and canl) v o(reces) (norm) recessive bus voltage on pins canh and canl v txd = v cc ; no load normal mode 2.0 2.5 3.0 v v o(reces) (stby) recessive bus voltage on pins canh and canl v txd = v cc ; no load standby mode ? 100 0 100 mv i o(reces) (canh) recessive output current at pin canh ? 35 v < v canh < +35 v; 0 v < v cc < 5.25 v ? 2.5 ? +2.5 ma i o(reces) (canl) recessive output current at pin canl ? 35 v < v canl < +35 v; 0 v < v cc < 5.25 v ? 2.5 ? +2.5 ma i li(canh) input leakage current to pin canh v cc = 0 v v canl = v canh = 5 v ? 10 0 10 a i li(canl_ input leakage current to pin canl v cc = 0 v v canl = v canh = 5 v ? 10 0 10 a v o(dom) (canh) dominant output voltage at pin canh v txd = 0 v 3.0 3.6 4.25 v v o(dom) (canl) dominant output voltage at pin canl v txd = 0 v 0. 5 1.4 1.75 v v o(dif) (bus_dom) differential bus output voltage (v canh ? v canl ) v txd = 0 v; dominant; 42.5 < r lt < 60 1.5 2.25 3.0 v v o(dif) (bus_rec) differential bus output voltage (v canh ? v canl ) v txd = v cc ; recessive; no load ? 120 0 +50 mv i o(sc) (canh) short circuit output current at pin canh for the ncv7340d13(r2)g v canh = 0 v; v txd = 0 v ? 100 ? 70 ? 45 ma short circuit output current at pin canh for ncv7340d12(r2)g & ncv7340d14(r2)g v canh = 0 v; v txd = 0 v ? 120 ? 70 ? 45 ma
ncv7340 http://onsemi.com 7 table 5. characteristics v cc = 4.75 v to 5.25 v; t j = ? 40 to +150 c; r lt = 60 unless specified otherwise. symbol unit max typ min conditions parameter bus lines (pins canh and canl) i o(sc) (canl) short circuit output current at pin canl for the ncv7340d13(r2)g v canl = 36 v; v txd = 0 v 45 70 100 ma short circuit output current at pin canl for ncv7340d12(r2)g & ncv7340d14(r2)g v canl = 36 v; v txd = 0 v 45 70 120 ma v i(dif) (th) differential receiver threshold voltage (see figure 6) ? 5 v < v canl < +12 v; ? 5 v < v canh < +12 v; 0.5 0.7 0.9 v v ihcm(dif) (th) differential receiver threshold voltage for high common ? mode (see figure 6) ? 35 v < v canl < +35 v; ? 35 v < v canh < +35 v; 0.40 0.7 1.0 v v i(dif) (th)_stdby differential receiver threshold voltage in standby mode (see figure 6) ? 12 v < v canl < +12 v; ? 12 v < v canh < +12 v; 0.4 0.8 1.15 v r i(cm) (canh) common ? mode input resistance at pin canh 15 26 37 k r i(cm) (canl) common ? mode input resistance at pin canl 15 26 37 k r i(cm) (m) matching between pin canh and pin canl common mode input resistance v canh = v canl ? 3 0 +3 % r i(dif) differential input resistance 25 50 75 k c i(canh) input capacitance at pin canh v txd = v cc ; not tested 7.5 20 pf c i(canl) input capacitance at pin canl v txd = v cc ; not tested 7.5 20 pf c i(dif) differential input capacitance v txd = v cc ; not tested 3.75 10 pf common ? mode stabilization (pin v split ) v split reference output voltage at pin v split normal mode; ? 500 a < i split < 500 a 0.3 x v cc ? 0.7 x v cc i split(i) v split leakage current standby mode ? 5 +5 a i split(lim) v split limitation current normal mode 1.3 5 ma thermal shutdown t j(sd) shutdown junction temperature junction temperature rising 150 160 185 c timing characteristics (see figures 7 and 8) t d(txd ? buson) delay txd to bus active c l = 100 pf between canh to canl 20 85 105 ns t d(txd ? busoff) delay txd to bus inactive c l = 100 pf between canh to canl 30 60 105 ns t d(buson ? rxd) delay bus active to rxd c rxd = 15 pf 25 55 105 ns t d(busoff ? rxd) delay bus inactive to rxd c rxd = 15 pf 30 100 105 ns t pd(rec ? dom) propagation delay txd to rxd from recessive to dominant c l = 100 pf between canh to canl 75 230 ns t d(dom ? rec) propagation delay txd to rxd from dominant to recessive c l = 100 pf between canh to canl 75 245 ns t d(stb ? nm) delay standby mode to normal mode 5 7.5 10 s t dbus dominant time for wakeup via bus v dif(dom) > 1.4 v 0.75 2.5 5 s v dif(dom) > 1.2 v 0.75 3 5.8 s t dom(txd) txd dominant time for time out v txd = 0 v 300 650 1000 s
ncv7340 http://onsemi.com 8 measurement setups and definitions ncv7340 v cc gnd 2 3 canh canl v split 5 6 7 stb 8 rxd 4 txd 1 1 nf 100 nf +5 v 15 pf 1 nf transient generator figure 5. test circuit for automotive transients v rxd v i(dif)(hys) high low 0.5 0.9 hysteresis figure 6. hysteresis of the receiver ncv7340 v cc gnd 2 3 canh canl v split 5 6 7 r lt c lt stb 8 rxd 4 txd 1 60 100 pf 100 nf +5 v 15 pf figure 7. test circuit for timing characteristics
ncv7340 http://onsemi.com 9 canh canl txd rxd dominant 0.9v 0.5v recessive 0.7 x v cc v i(dif) = v canh ? v canl t d(txd ? buson) t d(buson ? rxd) t pd(rec ? dom) t d(txd ? busoff) t d(busoff ? rxd) t pd(dom ? rec) 0.3 x v cc high low figure 8. timing diagram for ac characteristics device ordering information part number description temperature range package type shipping ? ncv7340d12g hs lp can transceiver (unconditioned bus wakeup) ? 40 c to +125 c soic 150 8 (mate sn, jedec ms ? 012) (pb ? free) 96 tube / tray ncv7340d12r2g 3000 / tape & reel NCV7340D13G emc improved hs lp can transceiver (unconditioned bus wakeup) 96 tube / tray ncv7340d13r2g 3000 / tape & reel ncv7340d14g hs lp can transceiver (bus wakeup inactive in case of bus fault) 96 tube / tray ncv7340d14r2g 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv7340 http://onsemi.com 10 package dimensions soic 8 case 751az ? 01 issue o
ncv7340 http://onsemi.com 11 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncv7340/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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