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june 2011 ? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAB1200 ? rev 1.2.6 FAB1200 ? ground-referenced class-g headphone amplifier with integrated buck converter FAB1200 class-g ground-referenced headphone amplifier with integrated buck converter features ? class-g headphone amplifier uses multiple rails for high efficiency ? integrated inductive buck converter for direct battery connection ? differential analog inputs ? capable of driving 16 ? to 600 ? loads and line level inputs ? ground-referenced output ? ground-sense input eliminates ground-loop noise ? i 2 c controls ? 32-step volume control ? channel-independent shutdown control and short-circuit protection ? 16-bump, 0.4mm pitch, 1.56mm x 1.56mm wlcsp package applications ? cellular handsets ? mp3 and portable media players ? personal navigation devices description the FAB1200 is a stereo class-g headphone amplifier. a charge pump generates a negative supply voltage that allows its out put to be ground centered. an integrated buck regulator adjusts the voltage supplies between two different levels based on the output signal level to reduce power consumption. figure 1. typical application circuit ordering information part number operating temperature range package packing method FAB1200ucx -40 to +85c 16-bump, 0.4mm pitch, 1,56mm x 1.56mm, wafer-level chip-scale package (wlcsp) 4000 units on tape & reel
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAB1200 ? rev 1.2.6 2 FAB1200 ? ground-referenced class-g headphone amplifier with integrated buck converter pin configuration figure 2. 16-bump, 0.4mm pitch wlcsp package (top view) pin definitions wlcsp name description type a1 sw buck converter switching node output a2 av dd power supply for the device; connect to battery power a3 outl left channel output output a4 inl- left channel input, negative terminal input b1 agnd main ground power b2 cpp charge pump flying capacitor, positive terminal power b3 hpv dd power supply for headphone amplifier (dc-dc output) power b4 inl+ left channel input, positive terminal input c1 cpn charge pump flying capacitor, negative terminal power c2 hpv ss charge pump output power c3 sgnd ground sense; connect to headphone jack ground input c4 inr+ right channel input, positive terminal input d1 sda i 2 c serial data (sda) line bi-directional d2 scl i 2 c serial clock (scl) line input d3 outr right channel output output d4 inr- right channel input, negative terminal input
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAB1200 ? rev 1.2.6 3 FAB1200 ? ground-referenced class-g headphone amplifier with integrated buck converter absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and st ressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit av dd supply voltage -0.3 6.0 v hpv dd_amp amplifier supply voltage, hpv dd pin -0.3 2.5 v v ia inl+, inl-, inr+, inr- voltage hpv ss - 0.3 hpv dd + 0.3 v v i2c i 2 c voltage -0.3 av dd + 0.3 v v out outl, outr voltage -hpv ss - 0.3 hpv dd + 0.3 v i bkd output protection diodes breakd own continuous current 200 ma reliability information symbol parameter min. typ. max. unit t j junction temperature +150 c t stg storage temperature range -65 +85 c storage relative humidity range 15 70 % t l peak reflow temperature +260 c ? ja thermal resistance, jedec standar d, multilayer test boards, still air 75 c/w electrostatic discharge capability symbol parameter condition level unit esd human body model, jesd22-a114 according to jesd22-a114-b level 2, compatible with iec61340-3-1: 2002 level 2 or esd-stm5.1- 2001 level 2 or mil-std-883e 3015.7 level 2 4000 v charged device model, jesd22-c101 according to jesd22-c101 -c level iii, compatible with iec61340-3-3 level c4 or esd-stm5.3.1-1999 level c4 1500 recommended operating conditions the recommended operating conditions table defines th e conditions for actual device operation. recommended operating conditions are specified to en sure optimal performance to the datash eet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit t a operating temperature range -40 +85 c av dd supply voltage range 2.5 5.5 v t slew power supply slew rate 1 v/s
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAB1200 ? rev 1.2.6 4 FAB1200 ? ground-referenced class-g headphone amplifier with integrated buck converter electrical characteristics unless otherwise noted, av dd = 3.6v, gain = 0db, r l = 15 ? + 32 ? || 5nf with audio measurements across the 32 ? || 5nf load, f = 1khz, t a = 25c. symbol parameter condition min. typ. max. unit i dd quiescent current both channels enabled, no audio signal 1.2 2.2 ma i s supply current output: 2 x 100w at 3db crest factor, r l = 32 ?? only 2.6 3.5 ma output: 2 x 500w at 3db crest factor, r l = 32 ?? only 4.4 5.5 output: 2 x 1mw at 3db crest factor, r l = 32 ?? only 5.7 7.5 hizl = hizr = 1 1.0 2.3 i sd shutdown current swsby = 1, inputs ac grounded, scl and sda pulled high 1.8 6.0 a t wk wake-up time 1.5 5.0 ms p o output power per channel (outputs in phase) av dd = 2.7v, thd < 1%, f = 1khz, r l = 32 ?? only 36 mw av dd = 2.7v, thd < 10%, f = 1khz, r l = 32 ?? only 48 av dd = 2.7v, thd < 1%, f = 1khz, r l = 16 ?? only 51 hpv dd high rail voltages buck and cp output outer rail 1.70 1.80 1.90 v inner rail 1.20 1.25 1.30 hpv ss low rail voltages outer rail -1.9 0 -1.80 -1.70 inner rail -1.30 -1.25 -1.20 thd+n total harmonic distortion + noise 700mv rms , 1khz 0.01 0.02 % psrr power supply rejection ratio (1) gain 0db, 200mv pp ripple at 217hz 80 100 db v in input voltage range input st age does not clip 1.4 vp cmrr common mode rejection ratio 1v pp , f = 1khz, gain 0db, r l = 32 ?? only 65 db snr signal-to-noise ratio 1v rms , f = 1khz, r l = 32 ?? only 100 106 db channel separation p o = 15mw, f = 1khz 80 db r l 16 ? 75 db line out >10k ? (1) 80 v n output noise gain 0db, a-weight, r l = 32 ?? only 4.7 9.0 v rms dc-out output dc-offset both chan nels enabled -500 500 v gain matching 1 % mute attenuation mutex = 1 -110 -80 db hizx = 1 -80 continued on the following page?
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAB1200 ? rev 1.2.6 5 FAB1200 ? ground-referenced class-g headphone amplifier with integrated buck converter electrical characteristics (continued) unless otherwise noted, av dd = 3.6v, gain = 0db, r l = 15 ? + 32 ? || 5nf with audio measurements across the 32 ? || 5nf load, f = 1khz, t a = 25c. symbol parameter condition min. typ. max. unit z in input impedance differential 20.0 k ? differential input impedance gain = 0db, per input node 38 single ended input impedance gain = 0db, per input node 18 z out output impedance hizx = 1, swsby = 0 <40khz 10.0 11.5 k ? 6mhz 500 1200 ? 13mhz 800 ? 36mhz 75 380 ? c load capacitive load esd protection, external capacitor 0.8 5.0 100.0 nf t sd thermal shutdown threshold 150 c t hys thermal shutdown hysteresis 55 c note: 1. guaranteed by characterization.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAB1200 ? rev 1.2.6 6 FAB1200 ? ground-referenced class-g headphone amplifier with integrated buck converter i 2 c dc characteristics unless otherwise noted, av dd = 2.5v to 5.5v and t a = 25c. symbol parameter conditions fast mode (400khz) min. max. unit v il low-level input voltage av dd 2.9 to 4.5 v -0.3 0.6 v v ih high-level input voltage av dd 2.9 to 4.5 v 1.2 v v ol low-level output voltage at 3ma sink current (open-drain or open-collector) 0 0.4 v i ih high-level input current of each i/o pin input voltage = av dd -1 1 a i il low-level input current of each i/o pin input voltage = 0v -1 1 a i 2 c ac electrical characteristics unless otherwise noted, av dd = 2.5v to 5.5v and t a = 25c. symbol parameter fast mode min. max. unit f scl scl clock frequency 0 400 khz t hd;sta hold time (repeated) start condition 0.6 s t low low period of scl clock 1.3 s t high high period of scl clock 0.6 s t su;sta set-up time for repeated start condition 0.6 s t hd;dat data hold time 0 0.9 s t su;dat data set-up time (2) 100 ns t r rise time of sda and scl signals (3) 20+0.1c b 300 ns t f fall time of sda and scl signals (3) 20+0.1c b 300 ns t su;sto set-up time for stop condition 0.6 s t buf bus free time between stop and start conditions 1.3 s t sp pulse width of spikes that must be suppressed by the input filter 0 50 ns notes: 2. a fast-mode i 2 c-bus ? device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat ? 250ns low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r_max + t su;dat = 1000 + 250 = 1250ns (according to the standard-mode i 2 c bus specification) before the scl line is released. 3. c b equals the total capacitance of one bus line in pf. if mixe d with high-speed mode devices, faster fall times are allowed according to the i 2 c specification. figure 3. definition of timing for full-speed mode devices on the i 2 c bus ? all marks are the property of their respective owners.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAB1200 ? rev 1.2.6 7 FAB1200 ? ground-referenced class-g headphone amplifier with integrated buck converter typical characteristics 2.5 supply voltage (v) supply current (ma) 3.0 3.5 4.0 4.5 5.0 5.5 0 1 3 4 5 6 7 8 9 10 2 figure 4. quiescent supply current vs. supply voltage figure 5. shutdown supply current vs. supply voltage 0.001 10 1 100 r l = 32ohm f = 1khz outputs in-phase avdd = 2.5v avdd = 3.6v avdd = 5.0v 0.01 0.1 1 10 100 total output power (mw) supply current (ma) figure 6. supply current vs. total output powe r 32 ? figure 7. supply current vs. total output powe r 16 ? 0 2.5 supply voltage (v) output power (mw) 3.0 3.5 4.0 4.5 5.0 5.5 10 30 40 50 60 70 80 90 100 20 f = 1khz r l = 32ohm outputs in-phase thd+n = 10% thd+n = 1% 0 2.5 supply voltage (v) output power (mw) 3.0 3.5 4.0 4.5 5.0 5.5 10 30 40 50 60 70 80 90 100 20 f = 1khz r l = 16ohm outputs in-phase thd+n = 10% thd+n = 1% figure 8. output power vs. supply voltage at 32 ? figure 9. output powe r vs. supply voltage at 16 ?
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAB1200 ? rev 1.2.6 8 FAB1200 ? ground-referenced class-g headphone amplifier with integrated buck converter typical characteristics figure 10. thd+n vs. output powe r at 32 ? figure 11. thd+n vs. output powe r at 16 ? figure 12. thd+n vs. output powe r figure 13. psrr vs. frequency 1 0.1 0.01 0.001 100 frequency (hz) 1k 20k 20 10k avdd = 2.5v to 5.5v r l = 16ohm 1mw per channel 20mw per channel figure 14. thd+n vs. frequency at 32 ? figure 15. thd vs. frequency at 16 ?
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAB1200 ? rev 1.2.6 9 FAB1200 ? ground-referenced class-g headphone amplifier with integrated buck converter typical characteristics crosstalk (db) figure 16. crosstalk vs. frequency at 32 ? figure 17. cmrr vs. frequency output (dbv) figure 18. output vs. frequency at 32 ?
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAB1200 ? rev 1.2.6 10 FAB1200 ? ground-referenced class-g headphone amplifier with integrated buck converter functional description class g the FAB1200 uses a class-g headphone architecture for low power dissipation. an integrated converter creates the headphone amplifier positive supply voltage, hpv dd . a charge pump inverts hpv dd and creates an amplifier negative supply voltage, hpv ss . this allows the headphone amplifier out put to be centered at 0v and eliminates the need for dc blocking capacitors. when the output signal am plitude is low, the buck converter generates a low hpv dd voltage. when needed, the buck converter generates a higher hpv dd to accommodate higher amplitude output signals. this change occurs faster than audio signals so no distortion or clipping is introduced. thermal and current protection if the junction temperature of the regulator or headphone amplifier exceeds limits ( see the electrical characteristics table ), the system is disabled for approximately one second and the therm bit is set to one. after one second, the system is enabled. if the fault condition still exists, the system is disabled again. this cycle repeats until the fault condition is removed. the therm bit stays set to 1 until the fault condition is removed and it is read. output current is limited to prevent internal damage. a signal that would exceeds current limits is clipped so that it falls within limits. shutdown setting the swsby bit to 1 places the device in a low- current shutdown state. the i 2 c port is still active and register values are not lost. during shutdown, hpv dd and hpv ss are powered down. therefore, no signal should be present at the inputs during shutdown. during shutdown, junction temperature is not monitored. if junction temperature exceeds limits during shutdown, the therm bit does not set to 1. output impedance the FAB1200 headphone outputs can be placed in high-impedance mode by setting the hizx bits to 1. this can be useful if the system ?s headphone jack is shared with other devices. for proper high-impedance operation, the device must not be in a shutdown or protection mode and voltages on outl and outr must not exceed 1.8v. actual impedance values are shown in the electrical characteristics table. applications information layout considerations general layout and supply bypassing play a major role in analog performance and thermal characteristics. fairchild offers a demonstration board to guide layout and aid device evaluation. contact a fairchild representative for demonstration board information. following this layout configuration provides optimum performance for the device. for the best results, follow the steps and recommended routing rules listed below. recommended routing/layout rules ? do not run analog and digital signals in parallel. ? use separate analog and digital power planes to supply power. ? traces should always run on top of the ground plane. ? no trace should run over ground/power splits. ? avoid routing at 90-degree angles. ? place bypass capacitors within 0.1 inches of the device power pin. ? minimize all trace lengths to reduce series inductance.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAB1200 ? rev 1.2.6 11 FAB1200 ? ground-referenced class-g headphone amplifier with integrated buck converter i 2 c control writing to and reading from the registers is accomplished via the i 2 c interface. the i 2 c protocol requires that one device on the bus initiates and controls all read and write operations. this device is called the ?master? device. the master device also generates the scl signal, which is the clock signal for all other ?slave? devices on the bus. the FAB1200 is a slave device. both the master and slave devices can send and receive data on the bus. during i 2 c operations, one data bit is transmitted per clock cycle. all i 2 c operations follow a repeating nine- clock-cycle pattern that consis ts of eight bits (one byte) of transmitted data followed by an acknowledge (ack) or not acknowledge (nack) from the receiving device. note that there are no unused clock cycles during any operation; therefore, ther e must be no breaks in the stream of data and acks/nacks during data transfers. for most operations, i 2 c protocol requires the serial data (sda) line remain stable (unmoving) whenever serial clock line (scl) is high: transitions on the sda line can only occur when scl is low. the exceptions to this rule are when the master device issues a start or stop condition. the slave device cannot issue a start or stop condition. start condition: this condition occurs when the sda line transitions from high to low while scl is high. the master device uses this c ondition to indicate that a data transfer is about to begin. stop condition: this condition occurs when the sda line transitions from low to high while scl is high. the master device uses this condition to signal the end of a data transfer. acknowledge (ack) and not acknowledge (nack): when data is transferred to the slave device, it sends an acknowledge (ack) after receiving every byte of data. the receiving device sends an ack by pulling sda low for one clock cycle. when the master device is reading data from the slave device, the master sends an ack after receiving every byte of data. following the last byte, a master device sends a "not acknowledge" (nack) instead of an ack, followed by a stop condition. a nack is indicated by leaving sda high during the clock after the last byte. slave address each slave device on the bus has a unique address so the master can identify which device is sending or receiving data. the FAB1200 slave address is 1100000x binary where ?x? is the read/write bit. master write operations are indicated when x=0. master read operations are indicated when x=1. writing to and reading from the FAB1200 all read and write operations must begin with a start condition generated by the master device. after the start condition, the master device must immediately send a slave address (7 bits), followed by a read/write bit. if the slave address matches the address of the FAB1200, the FAB1200 sends an ack after receiving the read/write bit by pulling the sda line low for one clock cycle. setting the pointer for all operations, the pointer stored in the command register must be pointing to the register to be written to or read from. to change the pointer value in the command register, the read/write bit following the address must be 0. this indica tes that the master will write new information into the command register. after the FAB1200 sends an ack in response to receiving the address and read/write bit, the master device must transmit an appropriate 8-bit pointer value, as explained in the i 2 c registers section. the FAB1200 sends an ack after receiving the new pointer data. the pointer set operation is illustrated in figure 21 and figure 22. any time a pointer set is performed, it must be immediately followed by a read or write operation. the command register retains the current pointer value between operations; therefore, once a register is indicated, subsequent read o perations do not require a pointer set cycle. write operations always require the pointer be reset. reading if the pointer is already pointing to the desired register, the master can read from t hat register by setting the read/write bit (following the slave address) to 1. after sending an ack, the FAB1200 begins transmitting data during the following clock cycle. the master should respond with a nack, followed by a stop condition (see figure 19) . the master can read multiple bytes by responding to the data with an ack instead of a nack and continuing to send scl pulses, as shown in figure 20. the FAB1200 increments the pointer by one and sends the data from the next register. the master indicates the last data byte by responding with a nack, followed by a stop. to read from a register other than the one currently indicated by the command register, a pointer to the desired register must be set. immediately following the pointer set, the master must perform a repeat start condition ( see figure 22 ), which indicates to the FAB1200 that a new operation is about to occur. if the repeat start condition does not occur, the FAB1200 assumes that a write is taking place and the selected register is overwritten by the upcoming data on the data bus. after the star t condition, the master must again send the device address and read/write bit. this time, the read/write bit must be set to 1 to indicate a read. the rest of the read cycle is the same as described in the previous paragraphs for reading from a preset pointer location.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAB1200 ? rev 1.2.6 12 FAB1200 ? ground-referenced class-g headphone amplifier with integrated buck converter writing all writes must be preceded by a pointer set, even if the pointer is already pointing to the desired register. immediately following the po inter set, the master must begin transmitting the data to be written. after transmitting each byte of data, the master must release the sda line for one clock cycle to allow the FAB1200 to acknowledge receiving the byte. the write operation should be terminated by a stop condition from the master (see figure 21). as with reading, the master can write multiple bytes by continuing to send data. the FAB1200 increments the pointer by ones and accept data for the next register. the master indicates the last data byte by issuing a stop condition. figure 19. i 2 c read sda scl d3 d7 d6 d5 d4 d2 d1 d0 a3 a7 a6 a5 a4 a2 a1 ack r/w slave address (from master) data (from slave) ack (from slave) ack (from master) d3 d7 d6 d5 d4 d2 d1 d0 ack nack data (from slave) nack (from master) stop (from master) start (from master) figure 20. i 2 c multiple-byte read figure 21. i 2 c write figure 22. i 2 c write followed by read
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAB1200 ? rev 1.2.6 13 FAB1200 ? ground-referenced class-g headphone amplifier with integrated buck converter i 2 c registers table 1. register map table 2. register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x01 hpenl hpenr 0 0 0 0 therm swsby 0x02 mutel muter vol4 vol3 vol2 vol1 vol0 0 0x03 0 0 0 0 0 0 hizl hizr 0x04 id id 0 0 revision 3 revision 2 revision 1 revision 0 notes: 4. bits labeled ?0? have no effect if writt en. when read, their value is always 0. 5. bits not mentioned in the register map are for testing only. these bits s hould never be written. when read, they may return any value. table 3. register 0x01 bit label r/w default description 0 swsby r/w 1 1 = low-power software standby. charge pumps are turned off. i 2 c is still active. register values are not lost during shutdown. 0 = normal operation. 1 therm r 0 1 = a thermal shutdown has occurred. th is bit stays set until it is read. 0 = no thermal shutdown. 5:2 0 r 0000 value is always 0. no effect if written. 6 hpenr r/w 0 1 = enable right headphone amplifier. 0 = disable right headphone amplifier. 7 hpenl r/w 0 1 = enable left headphone amplifier. 0 = disable left headphone amplifier. table 4. register 0x02 bit label r/w default description 0 0 r 0 value is always 0. no effect if written. 5:1 vol[4:0] r/w 00000 00000 : -59db 11111 : +4db audio taper over entire range (see table 7) 6 muter r/w 1 1 = mute right channel. 0 = un-mute right channel. 7 mutel r/w 1 1 = mute left channel. 0 = un-mute left channel. table 5. register 0x03 bit label r/w default description 0 hizr r/w 0 1 = 3-state right channel. 0 = normal operation. 1 hizl r/w 0 1 = 3-state left channel. 0 = normal operation. 7:2 0 r 000000 value is always 0. no effect if written.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAB1200 ? rev 1.2.6 14 FAB1200 ? ground-referenced class-g headphone amplifier with integrated buck converter table 6. register 0x04 bit label r/w default description 3:0 revision[3:0] r 0101 denotes silicon revision. 5:4 0 r 00 value is always 0. no effect if written. 7:6 id[1:0] r 00 supp lier identification. table 7. volume control volume control word gain (db) volume control word gain (db) 10xxxxxx mute_l 0001111x -13 01xxxxxx mute_r 0010000x -11 0000000x -59 0010001x -10 0000001x -55 0010010x -9 0000010x -51 0010011x -8 0000011x -47 0010100x -7 0000100x -43 0010101x -6 0000101x -39 0010110x -5 0000110x -35 0010111x -4 0000111x -31 0011000x -3 0001000x -27 0011001x -2 0001001x -25 0011010x -1 0001010x -23 0011011x 0 0001011x -21 0011100x +1 0001100x -19 0011101x +2 0001101x -17 0011110x +3 0001110x -15 0011111x +4
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAB1200 ? rev 1.2.6 15 FAB1200 ? ground-referenced class-g headphone amplifier with integrated buck converter physical dimensions figure 23. 16-ball wlcsp, 4x4 array, 0.4mm pitch, 250m ball product-specific dimensions product d e x y FAB1200ucx 1.56mm 1.56mm 0.18mm 0.18mm package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent version. package s pecifications do not expand fairchild?s worldw ide terms and conditions, specifically t he warranty therein, which covers fairchild products. always visit fairchild semiconductors on line packaging area for the most recent packaging drawings and tape and reel specifications http://www.fairchildsemi.com/packaging/ . bottom view side views top view recommended land pattern ball a1 index area 1 2 3 4 a b c d seating plane 16x a1 0.005 cab f (nsmd pad type) ?0.2600.02 0.40 0.40 (x) 0.018 (y) 0.018 0.625 0.547 0.06 c 0.05 c e d f 0.3780.018 0.2080.021 notes: a. no jedec registration applies. b. dimensions are in millimeters. c. dimensions and tolerance per asme y14.5m, 1994. d. datum c is defined by the spherical crowns of the balls. e. package nominal height is 586 microns 39 microns (547-625 microns). f. for dimensions d, e, x, and y see product datasheet. g. drawing filname: mkt-uc016aarev2. 0.03 c 2x 0.03 c 2x e d b c a 0.40 0.40 (?0.20) cu pad (?0.30) solder mask opening
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAB1200 ? rev 1.2.6 16 FAB1200 ? ground-referenced class-g headphone amplifier with integrated buck converter

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