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description the a4402 is a power management ic that combines a 2% constant on-time buck regulator and a 2% linear regulator. ideal for applications that require two regulated voltages. the buck regulator output supplies the adjustable linear regulator to reduce power dissipation and increase overall efficiency. the switching regulator is capable of operating above 2 mhz. a greater than 2 mhz switching frequency enables the customer to select low value inductors and capacitors while avoiding emi. protection features include undervoltage lockout and thermal shutdown. in case of a shorted load, each regulator features overcurrent protection. the a4402 also features a power-on reset with adjustable delay for the microprocessor output. the a4402 is provided in a 16-pin, 1.20 mm nominal overall height tssop, with exposed pad for enhanced thermal dissipation. it is lead (pb) free, with 100% matte tin leadframe plating. 4402-ds, rev. 2 features and benefits ? 2 mhz switching frequency ? adjustable soft start timer ? watchdog input ? power-on reset output ? adjustable 2% buck regulator ? adjustable 2% linear regulator ? enable input ? 6 to 50 v supply voltage range ? overcurrent protection ? undervoltage lockout (uvlo) ? thermal shutdown protection constant on-time buck converter with integrated linear regulator package: 16-pin tssop with exposed thermal pad (suffix lp) typical application not to scale a4402 enb vo2 npor gnd gnd gnd 1 f 3.3 v 300 ma v o2 l1 33 h vin1 lx fb1 10 f v bat fb2 vin2 por c por tset c tset 5v 0.1 f isen v lin v sw switching regulator output linear regulator output a 4402 ton 0.01 f 4 r sense .7 f 20 r ton 750 k k k wdi 0.33 f 0.15 f k r1 31.6 k r2 9.76 r3 10 r4 5.62 k 4.7 k boot ? photo and inkjet printers ? industrial controls ? distributed power systems ? network applications applications:
constant on-time buck converter with integrated linear regulator a4402 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pin-out diagram absolute maximum ratings characteristic symbol notes rating units vin1 pin v in1 ?0.3 to 50 v vin2 pin v in2 ?0.3 to 7 v lx pin v lx ?1 to 50 v isen pin v isen ?0.5 to 1 v enb pin v enb ?0.3 to 7 v vo2 pin v o2 ?0.3 to 7 v wdi pin v wdi ?0.3 to 6 v ton pin v ton ?0.3 to 7 v fb1 and fb2 pins v fbx ?0.3 to 7 v npor v npor ?0.3 to 6.5 v ambient operating temperature t a range e ?40 to 85 c junction temperature t j(max) 150 c storage temperature range t stg ?40 to 150 c selection guide part number packing package a4402elptr-t 4000 pieces per 13-in. reel 16-pin tssop with exposed thermal pad thermal characteristics characteristic symbol test conditions* value units package thermal resistance r ja on 4-layer pcb based on jedec standard 34 oc/w *additional thermal information available on the allegro website. terminal list table number name function 1 ton on time setting terminal 2 gnd ground 3 fb2 feedback for v lin 4 vin2 input voltage 2 5 vo2 regulator 2 output 6 wdi watchdog input 7 tset soft start and watchdog timing capacitor terminal 8 npor fault output 9 fb1 feedback for v sw 10 por por delay 11 isen current sense, limit setting for switching regulator, connect to gnd through series resistor 12 boot boot node for lx 13 lx switching regulator output 14 gnd ground 15 vin1 input voltage 1 16 enb enable input ? pad exposed thermal pad ton gnd fb2 vin2 vo2 wdi tset npor enb vin1 gnd lx boot isen por fb1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 pad
constant on-time buck converter with integrated linear regulator a4402 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional block diagram enb vo2 npor v fb2 internal regulator vin1 enb 1 3.3 v 300 ma v o2 fault tsd l1 33 h lx fb1 boot switch pwm control switch disable boot charge 10 v bat fb2 vin2 por c por soft start ramp generator watchdog timer tset c tset v ref v ref v ref v sw v lin 5v 0.1 isen v sw ton v reg v reg 0.01 4.7 20 vin1 r ton 750 k k k k 4.7 k k k wdi wdi 0.15 f f 0.33 r3 10 r4 5.62 r r sense 1 31.6 r2 9.76 gnd gnd f f f f f
constant on-time buck converter with integrated linear regulator a4402 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com continued on the next page? electrical characteristics 1,2 valid at t j = 25c, v in = 13.5 v (unless otherwise noted) characteristics symbol test conditions min. typ. max. units input voltage supply 1 v in1 6 13.5 50 v input voltage supply 2 v in2 vin2 = v sw 3.3 ? 5 v supply quiescent current i in(q) enb = 5 v, i out = i sw + i lin = 0 ma, v in = 13.5 v ? 10 ? ma vin1 = 13.5 v, enb = 0 v, i out = i sw + i lin = 0 ma ? ? 1 a enb logic input voltage v enb v enb rising 2.0 2.28 2.56 v enb hysteresis v enbhys ? 100 ? mv enb logic input current i enb high input level, v enb = 3 v ? ? 100 a low input level, v enb < 0.4 v ?2 ? 2 a linear regulator output voltage range v o2 1.8 ? 3.3 v feedback voltage v fb2 1 ma < i o2 < 250 ma, 3.3 v < v in2 < 5 v 1.156 1.180 1.204 v v o2 undervoltage lockout threshold v o2uvlo v o2 rising based on fb voltage 0.896 0.944 0.990 v v o2 undervoltage lockout hysteresis v o2uvhys 30 50 70 mv feedback input bias current i fb2 ?100 100 400 na current limit i o2 250 ? 350 ma dropout voltage v drop i out = i sw + i lin = 250 ma ? ? 1.2 v switching regulator output voltage range v sw 3.3 ? 5 v feedback voltage v fb1 i out = i sw + i lin = 1 ma to 1.0 a, 8 v < v in < 18 v 1.156 1.180 1.204 v feedback input bias current i fb1 ?400 ?100 100 na switcher on time t on v in = 19.25 v, r ton = 750 k ? 670 ? ns v in = 13.5 v, r ton = 750 k 185 235 285 ns v in = 8 v, r ton = 750 k ? 1.4 ? s t on low voltage threshold v pl v in rising 8.1 9 9.9 v t on high voltage threshold v ph v in rising 15.75 17.5 19.25 v changeover hysteresis v hys ? 250 ? mv on-time accuracy err ton ?30 ? 30 % minimum on-time t onmin 80 ? ? ns minimum off-time t offmin 130 ? ? ns buck switch on-resistance r ds(on) t j = 25c, i load = 1 a ? 400 ? m t j = 125c, i load = 1 a ? 650 ? m isen voltage v isen ? ?200 ? mv valley current limit threshold i lim r sense = 0.27 ? 740 ? ma 6 v < v in < 8 v ? ? 550 ma
constant on-time buck converter with integrated linear regulator a4402 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com protection circuitry npor output voltage v npor i npor = 1 ma ? ? 400 mv npor leakage current i npor v npor = 5 v ? ? 1 a npor reset v nporreset 20 k pullup connected to vout2, v in < ? ? 0.7 v thermal shutdown threshold t jtsd t j rising ? 170 ? oc thermal shutdown hysteresis t jtsdhys ? 15 ? oc timing circuitry tset current, watchdog mode i tsetwdi npor = high 7 10 14 a tset valley voltage, watchdog mode v trip ? 1.2 ? v tset reset voltage, watchdog mode v reset ? 0.48 ? v wdi frequency f wdi ? ? 100 khz wdi duty cycle dc wdi 10 ? 90 % wdi logic input v wdi(0) v in2 0.55 ? ? v wdi logic input current i wdi v wdi = 0 to 5 v ?20 < 1.0 20 a wdi input hysteresis v wdihys ? 300 ? mv tset current, soft start mode i tsetss npor = low 14 20 26 a por current i por 3.92 5.60 7.28 a 1 for input and output current specifications, negative current is defined as coming out of (sourcing) the specified pin. 2 performance in the range ?40c to 85c guaranteed by design and characterization. electrical characteristics 1,2 (continued) valid at t j = 25c, v in = 13.5 v (unless otherwise noted) characteristics symbol test conditions min. typ. max. units
constant on-time buck converter with integrated linear regulator a4402 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com vin1 vin1 enb v sw v lin npor uvlo rising uvlo rising t por t ss uvlo falling uvlo falling 6 v 18 v v sw v lin npor t por t ss vpor vctset uvlo rising t por uvlo rising t por t ss power-up and power-down timing diagrams using enb using vin1
constant on-time buck converter with integrated linear regulator a4402 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com watchdog timing diagram enb uvlo rising v reset v trip v sw npor t por t ss wdi vo2 v tset t wait t por t wait
constant on-time buck converter with integrated linear regulator a4402 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description basic operation the a4402 contains a fixed on-time, adjust- able voltage buck switching regulator with valley sensing current mode control, and an adjustable linear regulator designed to run off the buck regulator output. the constant on-time converter maintains a constant output frequency because the on-time is inversely proportional to the supply voltage. as the input voltage decreases, the on-time is increased, maintaining a relatively con- stant period. valley mode current control allows the converter to achieve very short on-times because current is measured during the off-time. the device is enabled via the enb input. when the enb pin is pulled high, the converter starts-up under the control of an adjustable soft start routine whose ramp time is controlled by an external capacitor. under light load conditions, the switch enters pulse-skipping mode to ensure regulation is maintained. this effectively changes the switcher frequency. the frequency also is affected when the switcher is operating in discontinuous mode. in order to maintain a wide input voltage range, the switcher period is extended when either the minimum off-time at low v in , is reached or the mini- mum on-time at high v in . switcher overcurrent protection the converter utilizes pulse-by-pulse valley current limiting, which operates when the current through the sense resistor creates a voltage on the sense pin (isen) that equals ?0.2 v. during an overload condition, the switch is turned on for a period determined by the constant on- time circuitry. the switch off-time is extended until the current decays to the current limit value set by the selection of the sense resistor, at which point the switch turns on again. because no slope compensation is required in this control scheme, the current limit is maintained at a reasonably constant level across the input voltage range. figure 1 illustrates how the current is limited during an overload condition. the current decay (period with switch off) is propor- tional to the output voltage. as the overload is increased, the out- put voltage tends to decrease and the switching period increases. vin1 and vin2 vin1 is a high voltage input, designed to with- stand 50 v. bulk capacitance of at least 10 f should be used to decouple input supply vin1. the vin2 input is used to supply the linear regulator and should be connected directly to the output of the switching regulator. output voltage selection the output voltage on each of the two regulators is set by a voltage divider off the regulator output, as follows: v sw v fb1 =, ? ? ? ? ? ? ? ? r2 r1 + r2 v lin v fb2 =. ? ? ? ? ? ? ? ? r2 r1 + r2 (1) in order to maintain accuracy on the regulators the equivalent impedance on the fb node (r1 parallel with r2) should be approximately 10 k . current limit level inductor current operating at maximum load maximum load constant on-time constant on-time current current time constant period current limit level inductor current operating in a ?soft? overload overload time extended period figure 1. current limiting during overload
constant on-time buck converter with integrated linear regulator a4402 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com tset the tset pin serves a dual function by controlling the timing for both the soft start ramp and the wdi input. the current sourced from the tset pin is dependant on the state of npor. there are two formulas for calculating the time constants. c tset must be selected so that both the wdi frequency and soft start requirements are met. the formulas for calculating wdi and soft start timing are: t wdi 7.2 9.6 10 4 c tset , and = (2) t ss 6.0 6.0 10 4 c tset , = (3) where c tset is the value of the capacitor and the results, t x , are in s. watchdog the wdi input is used to monitor the state of a dsp or microcontroller. a constant current is driven into the capacitor on tset, causing the voltage on the tset pin to ramp upward until, at each rising edge on the wdi input, the ramp is pulled down to v reset . if no edge is seen on the wdi pin before the ramp reaches v trip , the npor pin is pulled low. the watchdog timer is not activated until the wdi input sees one rising edge. the wdi pin should be pulled to ground with a 4.7 k resistor. soft start during soft start, an internal ramp generator and the external capacitor on tset are used to ramp the output voltage in a controlled fashion. this reduces the demand on the exter- nal power supply by limiting the current that charges the output capacitor and any dc load at startup. either of the following conditions are required to trigger a soft start: ? enb pin input rising edge ? reset of a tsd event when a soft start event occurs, vo2 is held in the off state until the soft start ramp timer expires. then the regulator will power up normally. refer to timing diagrams for details. boot a bootstrap capacitor is used to provide adequate charge to the nmos switch. the boot capacitor is referenced to lx and supplies the gate drive with a voltage larger than the supply voltage. the size of the capacitor must be 0.01 f, x7r type, and rated for at least 25 v. ton a resistor from the ton input to vin1 sets the on-time of the converter for a given input voltage. the formula to calculate the on-time is: t on 3.12 ?12 + 30 10 ?9 =. v in1 r ton (4) when the supply voltage is between 9 and 17.5 v, the switcher period remains constant, at a level based on the selected value of r ton . at voltages lower than 9 v and higher than 17.5 v, the period is reduced by a factor of 3.5. if a constant period is desired over varying input voltages, it is important to select an on-time that under worst case conditions will not exceed the minimum off-time or minimum on-time of the converter. for reasonable input voltage ranges, the period of the converter can be held constant, resulting in a constant operating frequency over the input supply range. more information on how to choose r ton can be found in the application information section. isen the sense input is used to sense the current in the diode during the off-time cycle. the value for r sense is obtained by the formula: r sense = 0.2 / i valley , (5) where i valley is the lowest current measured through the induc- tor during the off-time cycle. it is recommended that the current sense resistor be sized so that, at peak output current, the voltage on isen does not exceed ?0.5 v. because the diode current is measured when the inductor current is at the valley, the average output current is greater than the i valley value. the value for i valley should be: i valley = i out(av) ? 0.5 i ripple + k , (6) where: i out(av) is the average of both output currents, i ripple is the inductor ripple current, and k is a guardband margin. the peak current in the switch is then: i peak = i valley + i ripple . (7)
constant on-time buck converter with integrated linear regulator a4402 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the valley current must be calculated so that, at the worst-case ripple, the converter can still supply the required current to the load. further information on how to calculate the ripple current is included in the application information section. enb an active high input enables the device. when set low, the device enters sleep mode; all internal circuitry is disabled, and the part draws a maximum of 1 a. thermal shutdown when the device junction temperature, t j , is sensed to be at t jtsd , a thermal shutdown circuit disables the regulator output, protecting the a4402 from damage. power-on reset delay the por function monitors the v fb2 voltage and provides a signal that can be used to reset a dsp or microcontroller. a por event is triggered by either of the follow- ing conditions: ? v fb2 falls below its uvlo threshold. this occurs if the current limit on either regulator is exceeded, or if the switcher voltage falls due to tsd. ? after a rising edge on the wdi input, the voltage on tset reaches v trip . an open drain output, through the npor pin, is provided to signal a por event to the dsp or microcontroller. the reset occurs after an adjustable delay, t por , set by an external capacitor connected to the por pin. the value of t por is calculated using the following formula: t por = 2.4 102 c por , (8) where c por is the value of the capacitor and t por is in s. shutdown the buck regulator will shutdown if one of the fol- lowing conditions is present: ? tsd ? enb falling edge
constant on-time buck converter with integrated linear regulator a4402 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com switcher on-time and switching frequency in order for the switcher to maintain regulation, the energy that is transferred to the inductor during the on-time must be transferred to the capacitor during the off-time. because of this relationship, the load current, ir drops, as well as input and output voltages, affect the on-time of the converter. the equation that governs switcher on-time is: t on = . v in1 + r ds(on) i peak + v f t sw ( v sw + r load i peak + v f + r sense i peak ) (9) the effects of the voltage drop on the inductor and trace resis- tance affect the switching frequency. however, the frequency variation due to these factors is small and is covered in the varia- tion of the switcher period, t sw , which is 25% of the target. removing these current dependant terms simplifies the equation: t on = . v in1 + v f + ( v sense i peak ) v sw + v f + ( v sense i peak ) f sw 1 (10) be sure to use worst-case sense voltage and forward voltage of the diode, including any effects due to temperature. for example, given a 1 a converter with a supply voltage of 13.5 v, output voltage is 5 v, v f is 0.5 v, v sense is 0.15 v and the desired fre- quency is 2.0 mhz. we can solve for t on as follows: t on 199 ns == . 13.5 + 0.5 + 0.15 5 + 0.5 + 0.15 210 6 1 the formulas above describe how t on changes based on input and load conditions. because load changes are minimal, and the out- put voltage is fixed, the dominant factor that affects the on-time is the input voltage. the converter is able to maintain a constant period over a varying supply voltage because the on-time change is based on the input voltage. the current into the ton terminal is derived from a resistor tied to vin1, which sets the on-time proportional to the supply voltage. selecting the resistor value, based on the t on calculated above, is done using the following formula: r ton = . 3.12 10 ?12 v in1 ( t on + 10 ns) (11) after the resistor is selected and a suitable t on is found, it must be demonstrated that t on does not, under worst-case conditions, exceed the minimum on-time or minimum off-time of the con- verter. the minimum on-time occurs at maximum input voltage and minimum load. the maximum off time is occurs at minimum supply voltage and maximum load. for supply voltages below 9.5 v and above 7 v, refer to the low voltage operation section. low voltage operation the converter can run at very low input voltages. with a 5 v output, the minimum input supply can be as low as 6 v. when operating at high frequencies, the on-time of the converter must be very short because the available period is short. at high input voltages the converter must maintain very short on-times, while at low input voltages the converter must maintain long off-times. rather than limit the supply voltage range, the converter solves this problem by automatically increas- ing the period by a factor of 3.5. with the period extended, the converter will not violate the minimum on-time or off-time. if the input voltage is between 9.5 v and 17 v, the converter will main- tain a constant period. when calculating worst-case on-times and off-times, make sure to use the multiplier if the supply voltage is between those values. when operating at voltages below 8 v, additional care must be taken when selecting the inductor and diode. at low voltages the maximum current may be limited due to the ir drops in the current path. when selecting external components for low voltage operation, the ir drops must be considered when determining on-time, so the complete formula should be used to make sure the converter does not violate the timing specification. inductor selection choosing the right inductor is critical to the correct operation of the switcher. the converter is capable of running at frequencies above 2 mhz. this makes it possible to use small inductor values, which reduces cost and board area. the inductor value is what determines the ripple current. it is important to size the inductor so that under worst-case conditions i valley equals i av minus half the ripple current plus reasonable margin. if the ripple current is too large, the converter will be current limited. typically peak-to-peak ripple current should be limited to 20% to 25% of the maximum average load current. application information
constant on-time buck converter with integrated linear regulator a4402 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com worst-case ripple current occurs at maximum supply voltage. after calculating the duty cycle, dc, for this condition, the ripple current can be calculated. first to calculate dc: dc = . v in1 (max) + v f + ( v sense i peak ) v sw + v f + ( v sense i peak ) (12) using the duty cycle, a ripple current can be calculated using the following formula: ldc = , i ripple v in1 ? v sw f sw (min) 1 (13) where i ripple is 25% of the maximum load current, and f sw (min) is the minimum switching frequency (nominal frequency minus 25%). for the example used above, a 1 a converter with a supply voltage of 13.5 v was the design objective. the supply voltage can vary by 10%. the output voltage is 5 v, v f is 0.5 v, v sense is 0.15, and the desired frequency is 2.0 mhz. the duty cycle is calculated to be 36.45%. the worst-case frequency is 2 mhz minus 20% or 1.6 mhz. using these numbers in the above formula shows that the minimum inductance for this converter is 9.6 h. output capacitor the converter is designed to operate with a low-value ceramic output capacitor. when choosing a ceramic capacitor, make sure the rated voltage is at least 3 times the maximum output voltage of the converter. this is because the capacitance of a ceramic decreases as they operate closer to their rated voltage. it is recommended that the output be decoupled with a 10 f, x7r ceramic capacitor. larger capacitance may be required on the outputs if load surges dramatically influence the output voltage. output ripple is determined by the output capacitance and the effects of esr and esl can be ignored assuming recommended layout techniques are followed. the output voltage ripple is approximated by: = . i ripple v ripple 4 f sw c out (14) input capacitor the value of the input capacitance affects the amount of current ripple on the input. this current ripple is usually the source of supply side emi. the amount of interfer- ence depends on the impedance from the input capacitor and the bulk capacitance located on the supply bus. adding a small value, 0.1 f , ceramic capacitor as close to the input supply pin as possible can reduce emi effects. the small capacitor will help reduce high frequency transient currents on the supply line. if further filtering is needed it, is recommended that two ceramic capacitors be used in parallel to further reduce emissions. rectification diode the diode conducts the current during the off-cycle. a schottky diode is needed to minimize the forward drop and switching losses. in order to size the diode correctly, it is necessary to find the average diode conduction current using the formula below: = , i d(av) i load (1 ? dc(min)) (15) where dc (min) is defined as: dc (min) = , v sw +v f v in1 +v f (16) where v in1 is the maximum input voltage and v f is the maximum forward voltage of the diode. average power dissipation in the diode is: = , p d(diode) i load(av) dc(min) v f (17) the power dissipation in the sense resistor must also be consid- ered using i 2 r and the minimum duty cycle. pcb layout the board layout has a large impact on the per- formance of the device. it is important to isolate high current ground returns, to minimize ground bounce that could produce reference errors in the device. the method used to isolate power ground from noise sensitive circuitry is to use a star ground. this approach makes sure the high current components such as the input capacitor, output capacitor, and diode have very low imped- ance paths to each other. figure 2 illustrates the technique. star ground current path (on-cycle ) current path (off-cycle ) c in l q1 d r sense c out r load figure 2. star ground connection
constant on-time buck converter with integrated linear regulator a4402 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the ground from each of the components should be very close to each other and be connected on the same surface as the com- ponents. internal ground planes should not be used for the star ground connection, as vias add impedance to the current path. in order to further reduce noise effects on the pcb, noise sensi- tive traces should not be connected to internal ground planes. the feedback network from the switcher output should have an independent ground trace that goes directly to the exposed pad underneath the device. the exposed pad should be connected to internal ground planes and to any exposed copper used for heat dissipation. if the grounds from the device are also connected directly to the exposed pad the ground reference from the feed- back network will be less susceptible to noise injection or ground bounce. to reduce radiated emissions from the high frequency switching nodes it is important to have an internal ground plane directly under the lx node. the plane should not be broken directly under the node as the lowest impedance path back to the star ground would be directly under the signal trace. if another trace does break the return path, the energy will have to find another path, which is through radiated emissions. pad a4402 c5 c2 c3 c4 c7 r2 r3 l1 c1 c8 ton gnd fb2 vin2 vo2 wdi tset npor enb vin1 gnd lx boot isen por fb1 c6 d1 v in1 v sw v lin r5 r4 r6 r7 r1 pcb layout diagram c2 l1 r5 gnd u1 c4 vin2 d1 c1 c8 r3 r2 c7 vsw vlin r6 r7 c6 r4 c5 r1 vin1 gnd gnd gnd c3 gnd gnd pcb thermal vias trace (2 oz.) signal (1 oz.) ground (1 oz.) thermal (2 oz.) a4402 solder star ground
constant on-time buck converter with integrated linear regulator a4402 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pin circuit diagrams power terminals lx gnd gnd 54 v gnd gnd 7 v vin1 gnd 54 v v in1 ton gnd vin2 fb1 fb2 wdi tset npor por isen enb logic terminals v in1 boot gnd 10 v 10 v v in2 vo2 gnd
constant on-time buck converter with integrated linear regulator a4402 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com c seating plane c 0.10 16x 6.10 0.65 0.45 1.70 3.00 5.00 0.10 3.00 3.00 3.00 1.20 max 0.15 max 0.65 0.25 (1.00) 4.40 0.10 6.40 0.20 0.60 0.15 4 4 0.25 +0.05 ?0.06 0.15 +0.05 ?0.06 2 1 16 gauge plane seating plane b a 16 2 1 a terminal #1 mark area b all dimensions nominal, not for tooling use (reference jedec mo-153 abt) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown reference land pattern layout (reference ipc7351 sop65p640x110-17m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) pcb layout reference view exposed thermal pad (bottom surface) c c package lp, 16-pin tssop copyright ?2008-2009, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com

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