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document number: mc33883 rev 10.0, 10/2012 freescale semiconductor ? advance information * this document contains certain information on a new product. ? specifications and information herein are subject to change without notice. ? freescale semiconductor, inc. , 2007-2012. all rights reserved. h-bridge gate driver ic the 33883 is an h-bridge gate driver (also known as a full-bridge pre-driver) ic with integrated char ge pump and independent high and low side gate driver channels. the gate driver channels are independently controlled by four separate input pins, thus allowing the device to be optionally configured as two independent high side gate drivers and two independent low side gate drivers. the low side channels are referenced to ground. the high side channels are floating. the gate driver outputs can sour ce and sink up to 1.0 a peak current pulses, permitting large gate-charge mosfets to be driven and/or high pulse- width modulation (pwm) frequencies to be utilized. a linear regulator is incorporated, pr oviding a 15 v typical gate supply to the low side gate drivers. features ?v cc operating voltage range from 5.5 v up to 55 v ?v cc2 operating voltage range from 5.5 v up to 28 v ? cmos / lsttl compatible i / o ? 1.0 a peak gate driver current ? built-in high side charge pump ? under-voltage lockout (uvlo) ? over-voltage lockout (ovlo) ? global enable with <10 ? a sleep mode ? supports pwm up to 100 khz figure 1. 33883 simplified application diagram h-bridge gate driver ic 33883 ordering information device (add r2 suffix for tape and reel ) temperature range (t a ) package MC33883HEG - 40 c to 125 c 20 soicw eg suffix (pb-free) 98asb42343b 20-pin soicw mcu 33883 v boost v bat gnd src_hs2 gate_ls2 cp_out lr_out gate_hs1 src_hs1 gate_ls1 gate_hs2 in_hs1 in_ls1 in_hs2 in_ls2 vcc vcc2 g_en c1 c2 dc motor gnd_a /2
analog integrated circuit device data ? 2 freescale semiconductor 33883 internal block diagram internal block diagram figure 2. 33883 simplifi ed internal block diagram undervolt- age/over- voltage g_en in_hs1 in_ls1 in_hs2 in_ls2 gate_ls1 src_hs1 gate_hs cp_out lr_out gate_ls2 src_hs2 gate_hs pulse generator v dd / v cc level shift pulse generator v dd / v pos level shift in ou con- trol and logic linear reg v cc2 en gnd +5.0 v +14.5 v v dd high- and low-side charge pump en gnd c2 v pos v cc c1 v cc2 v cc v cc v cc2 vcc vcc2 cp_out lr_out v cc, v cc2 v dd c2 c1 brg_en pulse generator v dd / v cc level shift pulse generator v dd / v pos level shift gnd control with charge pump cp_out v cc output driver in ou cp_out v cc output driver in ou lr_out output driver in ou lr_out output driver con- trol and logic con- trol and logic con- trol and logic brg_en brg_en brg_en high-side channel low-side channel high-side channel low-side channel gnd2 gnd2 gnd1 gnd gnd_ gnd2 gnd_a t sd 1 thermal shutdown t sd 1 t sd 1 t sd 2 thermal shutdown t sd 2 t sd 2
analog integrated circuit device data ? freescale semiconductor 3 33883 pin connections pin connections figure 3. 33883 20-soicw pin connections a functional description of each pin can be found in the functional pin description section beginning on page 10 . table 1. 20-soicw pin definitions pin pin name formal name definition 1vcc supply voltage 1 device power supply 1. 2c2 charge pump capacitor external capacitor for internal charge pump. 3cp_out charge pump out external reservoir capacitor for internal charge pump. 4 src_hs1 source 1 output high side source of high-side 1 mosfet 5 gate_hs 1 gate 1 output high side gate of high-side 1 mosfet. 6 in_hs1 input high side 1 logic input control of high-side 1 gate (i.e ., in_hs1 logic high = gate_hs1 high). 7 in_ls1 input low side 1 logic input control of low-side 1 gate (i .e., in_ls1 logic high = gate_ls1 high). 8 gate_ls1 gate 1 output low side gate of low-side 1 mosfet. 9gnd1 ground 1 device ground 1. 10 lr_out linear regulator output output of internal linear regulator. 11 vcc2 supply voltage 2 device power supply 2. 12 gnd_a analog ground device analog ground. 13 c1 charge pump capacitor external capacitor for internal charge pump. 14 gnd2 ground 2 device ground 2. 15 gate_ls2 gate 2 output low side gate of low-side 2 mosfet. 16 in_ls2 input low side 2 logic input control of low-side 2 gate (i.e., in_ls2 logic high = gate_ls2 high). 17 in_hs2 input high side 2 logic input control of high-side 2 gate (i.e ., in_hs2 logic high = gate_hs2 high). 18 gate_hs 2 gate 2 output high side gate of high-side 2 mosfet. 19 src_hs2 source 2 output high side source of high-side 2 mosfet. 20 g_en global enable logic input enable control of device (i.e., g_ en logic high = full operation, g_en logic low = sleep mode). vcc cp_out in_ls1 gate_ls1 gnd1 lr_out src_hs1 gate_hs1 in_hs1 c2 g_en in_hs2 in_ls2 gate_ls2 gnd2 c1 gnd_a vcc2 src_hs2 gate_hs2 4 5 6 7 8 9 10 2 3 20 18 14 13 12 11 17 16 15 19 1
analog integrated circuit device data ? 4 freescale semiconductor 33883 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. rating symbol value unit electrical ratings supply voltage 1 v cc -0.3 to 65 v supply voltage 2 (1) v cc2 -0.3 to 35 v linear regulator output voltage v lr_out -0.3 to 18 v high-side floating supply absolute voltage v cp_out -0.3 to 65 v high-side floating source voltage v src_hs -2.0 to 65 v high-side source current from cp_out in switch on state i s 250 ma high-side gate voltage v gate_hs -0.3 to 65 v high-side gate source voltage (2) v gate_hs - v src_hs -0.3 to 20 v high-side floating supply gate voltage v cp_out - v gate_hs -0.3 to 65 v low-side gate voltage v gate_ls -0.3 to 17 v wake-up voltage v g_en -0.3 to 35 v logic input voltage v in -0.3 to 10 v charge pump capacitor voltage v c1 -0.3 to v lr_out v charge pump capacitor voltage v c2 -0.3 to 65 v esd voltage (3) human body model on all pins (v cc and v cc2 as two power supplies) machine model v esd1 v esd2 1500 130 v notes 1. v cc2 can sustain load dump pulse of 40 v, 400 ms, 2.0 ? . 2. in case of high current (src_hs >100 ma) and high voltage (>20 v) between gate_hsx and src_hs an external zener of 18 v is needed as shown in figure 14 . 3. esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ? ), esd2 testing is performed in accordance with the machine model (c zap = 200 pf, r zap = 0 ? ).
analog integrated circuit device data ? freescale semiconductor 5 33883 electrical characteristics maximum ratings power dissipation and thermal characteristics maximum power dissipation @ 25c thermal resistance (junction to ambient) operating junction temperature storage temperature p d r ? ja t j t stg 1.25 100 -40 to 150 -65 to 150 w c / w c c peak package reflow temperature during reflow (4) , (5) t pprt note 5 c notes 4. pin soldering temperature limit is for 10 seconds maximum duration. not designed fo r immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 5. freescale?s package reflow capability meets pb-free requirem ents for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), ? go to www.freescale.com, search by part number [e.g. remove pref ixes/suffixes and enter the core id to view all orderable parts . (i.e. mc33xxxd enter 33xxx), and review parametrics. table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. rating symbol value unit
analog integrated circuit device data ? 6 freescale semiconductor 33883 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electr ical characteristics characteristics noted under conditions v cc = 12 v, v cc2 = 12 v, c cp = 33 nf, g_en = 4.5 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit operating conditions supply voltage 1 for output high-side driver and charge pump v cc 5.5 ? 55 v supply voltage 2 for linear regulation v cc2 5.5 ? 28 v high-side floating supply absolute voltage v cp_out v cc +4 ? v cc + 11 but < 65 v logic logic 1 input voltage (in_ls and in_hs) v ih 2.0 ? 10 v logic 0 input voltage (in_ls and in_hs) v il ??0.8v logic 1 input current v in = 5.0 v i in+ 200 ? 1000 ? a wake-up input voltage (g_en) v g_en 4.5 5.0 v cc2 v wake-up input current (g_en) v g_en = 14 v i g_en ? 200 500 ? a wake-up input current (g_en) v g_en = 28 v i g_en2 ??1.5 ma linear regulator linear regulator v lr_out @ v cc2 from 15 v to 28 v, i load from 0 ma to 20 ma v lr_out @ i load = 20 ma v lr_out @ i load = 20 ma, v cc2 = ? 5.5 ? v, v cc ?? 5.5 ? v v lr_out 12.5 v cc2 - 1.5 4.0 ? ? ? 16.5 ? ? v charge pump charge pump output voltage, reference to vcc v cc = 12 v, i load = 0 ma, c cp_out = 1.0 ? f v cc = 12 v, i load = 7.0 ma, c cp_out = 1.0 ? f v cc2 = v cc = 5.5 v, i load = 0 ma, c cp_out = 1.0 ? f v cc2 = v cc = 5.5 v, i load = 7.0 ma, c cp_out = 1.0 ? f v cc = 55 v, i load = 0 ma, c cp_out = 1.0 ? f v cc = 55 v, i load = 7.0 ma, c cp_out = 1.0 ? f v cp_out 7.5 7.0 2.3 1.8 7.5 7.0 ? ? ? ? ? ? ? ? ? ? ? ? v peak current through pin c1 under rapidly changing vcc voltages (see figure 13 , page 17 ) i c1 -2.0 ? 2.0 a minimum peak voltage at pin c1 under rapidly changing vcc voltages (see figure 13 , page 17 ) v c1 min -1.5 ? ? v
analog integrated circuit device data ? freescale semiconductor 7 33883 electrical characteristics static electrical characteristics supply voltage quiescent vcc supply current v g_en = 0 v and v cc = 55 v v g_en = 0 v and v cc = 12 v iv ccsleep ? ? ? ? 10 10 ? a operating vcc supply current (6) v cc = 55 v and v cc2 = 28 v v cc = 12 v and v cc2 = 12 v iv ccop ? ? 2.2 0.7 ? ? ma additional operating v cc supply current for each logic input pin active v cc = 55 v and v cc2 = 28 v (7) iv cclog ??5.0 ma quiescent vcc2 supply current v g_en = 0 v and v cc = 12 v v g_en = 0 v and v cc = 28 v iv cc2sleep ? ? ? ? 5.0 5.0 ? a operating vcc2 supply current (6) v cc = 55 v and v cc2 = 28 v v cc = 12 v and v cc2 = 12 v iv cc2op ? ? ? ? 12 9.0 ma additional operating vcc2 supply curr ent for each logic input pin active v cc = 55 v and v cc2 = 28 v (7) iv cc2log ??5.0 ma undervoltage shutdown vcc uv 4.0 5.0 5.5 v undervoltage shutdown vcc2 (8) uv2 4.0 5.0 5.5 v overvoltage shutdown vcc ov 57 61 65 v overvoltage shutdown vcc2 ov2 29.5 31 35 v output output sink resistance (turned off) i discharge lss = 50 ma , v src_hs = 0 v (8) r ds ??22 ? output source resistance (turned on) i charge hss = 50 ma, v cp_out = 20 v (8) r ds ??22 ? charge current of the external high-side mosfet through gate_hsn pin (9) i charge hss ? 100 200 ma maximum voltage (v gate_hs - v src_hs ) inh = logic 1, i s max = 5.0 ma vmax ??18 v notes 6. logic input pin inactive (high impedance). 7. high-frequency pwm-ing ( ? 20 khz) of the logic inputs will result in greater po wer dissipation within the device. care must be taken to remain within the package power handling rating. 8. the device may exhibit predictable behavior between 4.0 v and 5.5 v. 9. see figure 5 , page 12 , for a description of charge current. table 3. static electrical characteristics (continued) characteristics noted under conditions v cc = 12 v, v cc2 = 12 v, c cp = 33 nf, g_en = 4.5 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? 8 freescale semiconductor 33883 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electr ical characteristics characteristics noted under conditions 7.0 v ? v sup ? 18 v, -40 ? c ? t a ? 125 ? c, gnd = 0.0 v unle ss otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit timing characteristics propagation delay high side and low side c load = 5.0 nf, between 50% input to 50% output (10) (see figure 4 ) t pd ? 200 300 ns turn-on rise time c load = 5.0 nf, 10% to 90% (10) , (11) (see figure 4 ) t r ? 80 180 ns turn-off fall time c load = 5.0 nf, 10% to 90% (10) , (11) (see figure 4 ) t f ? 80 180 ns 10. c load corresponds to a capacitor between gate_hs and src_hs fo r the high side and between gate_ls and ground for low side. 11. rise time is given by time needed to change the gat e from 1.0 v to 10 v (vice versa for fall time).
analog integrated circuit device data ? freescale semiconductor 9 33883 timing diagrams timing diagrams figure 4. timing characteristics 50% 50% 90% t f in_hs gate_hs 10% 50% 50% 90% 10% t pd t pd t r or in_ls or gate_ls
analog integrated circuit device data ? 10 freescale semiconductor 33883 functional description introduction functional description introduction the 33883 is an h-bridge gate driver (or full-bridge pre- driver) with integrated charge pump and independent high- and low-side driver channels. it has the capability to drive large gate-charge mosfets and supports high pwm frequency. in sleep mode its supply current is very low. functional pin description supply voltage pins (vcc and vcc2) the vcc and vcc2 pins are the power supply inputs to the device. v cc is used for the output high-side drivers and the charge pump. v cc2 is used for the linear regulation. they can be connected together or independent with different voltage values. the device can operate with v cc up to 55 v and v cc2 up to 28 v. the vcc and vcc2 pins have undervoltage (uv) and overvoltage (ov) shutdown. if one of the supply voltage drops below the undervoltage threshold or rises above the overvoltage threshold, the gate outputs are switched low in order to switch off the extern al mosfets. when the supply returns to a level that is above the uv threshold or below the ov threshold, the device resumes normal operation according to the established condition of the input pins. input high- and low-side pins ? (in_hs1, in_hs2, and in_ls1, in_ls2) the in_hsn and in_lsn pins are input control pins used to control the gate outputs. these pins are 5.0 v cmos- compatible inputs with hysteresis. in_hsn and in_lsn independently control gate_hsn and gate_lsn, respectively. during wake-up, the logic is supplied from the g_en pin. there is no internal circuit to prevent the external high-side and low-side mosfets from conducting at the same time. source output high-side pins (src_hs1 and src_hs2) the src_hsn pins are the sources of the external high- side mosfets. the external high-side mosfets are controlled using the in_hsn inputs. gate high- and low-side pins ? (gate_hs1, gate_hs2, and gate_ls1, gate_ls2) the gate_hsn and gate_lsn pi ns are the gates of the external high- and low-side mosfets. the external high- and low-side mosfets are controlled using the in_hsn and in_lsn inputs. global enable (g_en) the g_en pin is used to place the device in a sleep mode. when the g_en pin voltage is a logic low state, the device is in sleep mode. the device is enabled and fully operational when the g_en pin voltage is logic high, typically 5.0 v. charge pump out (cp_out) the cp_out pin is used to connect an external reservoir capacitor for the charge pump. charge pump capacitor pins ? (c1 and c2) the c1 and c2 pins are used to connect an external capacitor for the charge pump. linear regulator output (lr_out) the lr_out pin is the output of the internal regulator. it is used to connect an external capacitor. ground pins ? (gnd_a, gnd1 and gnd2) these pins are the ground pins of the device. they should be connected together with a very low impedance connection.
analog integrated circuit device data freescale semiconductor 11 33883 functional description functional pin description table 5. conditions g_en in_hsn in_lsn gate_hsn gate_lsn comments sleep 0 x x 0 0 device is in sleep mode. the gates are at low state. normal 1 1 1 1 1 normal mode. the gates are controlled independently. normal 1 0 0 0 0 normal mode. the gates are controlled independently. undervoltage 1 x x 0 0 the device is currently in fault mode. the gates are at low state. once the fault is removed, the 33883 recovers its normal mode. overvoltage 1 x x 0 0 the device is currently in fault mode. the gates are at low state. once the fault is removed, the 33883 recovers its normal mode. overtemperature on high-side gate driver 1 1 x 0 x the device is currently in fault mode. the high-side gate is at low state. once the fault is removed, the 33883 recovers its normal mode. overtemperature on low-side gate driver 1 x 1 x 0 the device is currently in fault mode. the low-side gate is at low state. once the fault is removed, the 33883 recovers its normal mode. x = don?t care. functional truth table
analog integrated circuit device data 12 freescale semiconductor 33883 functional device operation functional device operation driver characteristics figure 5 represents the external circuit of the high-side gate driver. in the schematic, h ss rep resents the switch that is used to charge the extern al high-side mosfet through the gate_hs pin. lss represents the switch that is used to discharge the external high-side mosfet through the gate_hs pin. a 180k : internal typical passive discharge resistance and a 18 v typical protection zener are in parallel with lss. the same schematic can be applied to the external low-side mosfet driver simply by replacing pin cp_out with pin lr_out, pin gate_hs with pin gate_ls, and pin src_hs with gnd. hss cp_out i gate_hs i charge hss i discharge lss gate_hs1 lss src_hs1 180 k: 18v hsspulse_in lss_in hssdc_in in_hs1 figure 5. high-side gate driver functional schematic the different voltages and curr ent of the high-side gate driver are illustrated in figure 6 . the output driver sources a peak current of up to 1.0 a for 200 ns to turn on the gate. after 20 0 ns, 100 ma is continuously provided to maintain the gate charg ed. the output driver sinks a high current to turn off the gate. this current can be up to 1.0 a peak for a 100 nf load. 1.0 a peak 1.0 a peak 100 ma typical 0 0 0 0 0 0 1.0 a peak 100 ma typical -1.0 a peak in_hs1 hsspulse_in hss dc_in lss_in i discharge lss i gate_hs i charge hss note gate_hs is loaded with a 100 nf capacitor in the chronogr ams. a smaller load will give lower peak and dc charge or discharge currents. figure 6. high-side gate driver chronograms
analog integrated circuit device data freescale semiconductor 13 33883 functional device operation operational modes operational modes turn-on for turn-on, the current requir ed to charge the gate source capacitor c iss in the specified time can be calculated as follows: i p = q g / t r = 80 nc / 80 ns | 1.0 a where q g is power mosfet gate charge and t r is peak current for rise time. turn-off the peak current for turn-off can be obtained in the same way as for turn-on, with the exce ption that peak current for fall time, t f , is substituted for t r : i p = q g / t f = 80 nc / 80 ns | 1.0 a in addition to the dynamic current required to turn off or on the mosfet , various application-related switching scenarios must be considered. these scenarios are presented in figure 7 . in order to withstand high dv/dt spikes, a low resistive path between gate and source is implemented du ring the off-state. driver requirement: low resistive gate- source path during off-state flyback spike charges low- side gate via c rss charge current i rss up to 2.0 a. causes increased uncon- trolled turn-on of low-side mosfet. c iss c iss c rss c rss v bat driver requirement: low resistive gate- source path during off-state. high peak sink current capability flyback spike pulls down high-side source v gs . delays turn-off of high- side mosfet. c iss c iss c rss c rss v bat driver requirement: high peak sink current capability flyback spike charges low- side gate via c rss charge current i rss up to 2.0 a. delays turn-off of low-side mosfet. c iss c iss c rss c rss v bat driver requirement: low resistive gate- source path during off-state c iss c iss c rss c rss v bat flyback spike pulls down high-side source v gs . causes increased uncon- trolled turn-on of high-side off off off off gate_ls i load l1 i load l1 i load l1 i load l1 i rss v gate v gate -v drn gate_hs gate_ls gate_hs gate_hs gate_ls gate_hs gate_ls figure 7. off-state driver requirement
analog integrated circuit device data 14 freescale semiconductor 33883 functional device operation operational modes low-drop linear regulator the low-drop linear regulator is supplied by v cc2 . if v cc2 exceeds 15.0 v, the output is limited to 14.5 v (typical). the low-drop linear regulator provides the 5.0 v for the log ic section of the driver, the v gs_ls buffered at lr_out, and the +14.5 v for the charge pump, which generates the cp_out the low-d rop linear regulator provides 4.0 ma averag e current per driver stage. in case of the full bridge, tha t means approximately 16 ma ? 8.0 ma for the high side and 8.0 ma for the low side. note: the average current requir ed to switch a gate with a frequency of 100 khz is: i cp = q g * f pwm = 80 nc * 100 khz = 8.0 ma in a full-bridge application only one high side and one low side switches on or off at the same time. charge pump the charge pump generates the high-side driver supply voltage (cp_out), buffered at c cp_out . figure 8 shows the charge pump basic circuit without load. osc. vbat v cp_out ccp_out v lr_out ccp d1 d2 a (1) (2) v lr_out osc. c cp v cc cp_out c cp_out c2 d2 d1 c1 figure 8. charge pump basic circuit when the oscillator is in low state [(1) in figure 8 ], c cp is charged through d2 until its voltage reaches v cc - v d2 . when the oscillator is in high state (2), c cp is discharged though d1 in c cp_out, and final voltage of the charge pump, v cp_out , is v cc + v lr_out - 2v d . the frequency of the 33883 oscillator is about 330 khz. external capacitors choice external capacitors on the charge pump and on the linear regulator are necessary to supply high peak current absorbed during switching. figure 9 represents a simplified circuitry of the high-side gate driver. transistors tosc1 and tosc2 are the oscillator- sw itching mosfets. when tosc1 is on, the oscillator is at low level. when tosc2 is on, the o scillator is at high level. the capacitor c cp_out provides peak current to the high-side mosfet through hss during turn-on (3). ccp_out v lr-out ccp d1 d2 c1 vcc c2 cp_out src_hs hs mosfet ls mosfet t1 t2 rg tosc1 tosc2 gate_hs pins (3) high-side mosfet low-side mosfet src_hs gate_hs v cc c1 c2 c cp d2 d1 cp_out v lr_out tosc2 tosc1 hss lss pins c cp_out rg figure 9. high-side gate driver
analog integrated circuit device data freescale semiconductor 15 33883 functional device operation operational modes c cp c cp choice depends on power mosfet characteristics and the working switching frequency. figure 10 contains two diagrams that depict the influence of c cp value on v cp_out average voltage level. the di agrams represent two different frequencies for two power mosfets, mtp60n06hd and mpt36n06v. mtp60n06hd (q g =50nc) 18.5 19 19.5 20 20.5 21 21.5 5 25 45 65 85 ccp ( nf ) v cp_out (v) 20 khz 100 khz 18 18.5 19 19.5 20 20.5 21 5 25456585 ccp (nf) vcp_out (v) 20khz 100 khz mtp60n06hd (q g = 50 nc) mtp36n06v (q g = 40 nc) mtp60n06hd (q g = 50 nc) c cp (nf) v cp_out (v) c cp (nf) v cp_out (v) 20 khz 100 khz figure 10. v cp_out versus c cp the smaller the c cp value is, the smaller the v cp_out value is. moreover, for the same c cp value, when the switching frequency increases, the average v cp_out level decreases. for most of the applications, a typical value of 33 nf is recommended. c cp_out figure 11 depicts the simplified c cp_out current and voltage waveforms. f pwm is the working switching frequency. v cp_out oscillator in high state oscillator in low state i cp_out peak current f=330khz f pwm outccp v _ ' high side turn on rage v cp_out oscillator in high state oscillator in low state f = 330 khz f pwm ' v cp_out high side turn on v cp_out v cp_out average i cp_out peak current figure 11. simplified c cp_out current and voltage waveforms as shown above, at high-side mosfet turn-on v cp_out voltage decreases. this decrease can be calculated according to the c cp_out value as follows: ' v cp_out = c cp_out q g where q g is power mosfet gate charge. c lr_out c lr_out provides peak current needed by the low-side mosfet turn-on. v lr_out decrease is as follows: ' v lr_out = c lr_out q g typical values of capacitors in most working cases the following typical values are recommended for a well-performing charge pump: c cp = 33 nf, c cp_out = 470 nf, and c lr_out = 470 nf these values give a typical 100 mv voltage ripple on v cp_out and v lr_out with q g = 50 nc.
analog integrated circuit device data 16 freescale semiconductor 33883 functional device operation protection and di agnostic features protection and diagnostic features gate protection the low-side driver is supplied from the built-in low-drop regulator. the high-side driver is supplied from the internal charge pump buffered at cp_out. the low-side gate is protected by the internal linear regu lator, which ensures that v gate_ls does not exceed the maximum v gs . especially when working with the charge pump, the voltage at cp _out can be up to 65 v. the high- side gate is clamped internally in order to avoid a v gs exceeding 18 v. gate protection does not include a fly-back voltage clamp th at protects the driver and t he external mosfet from a fly- back voltage that can occur when driving inductive load. this fly-back voltage can reach high negative voltage values and needs to be clamped externally, as shown in figure 12 . output driver out output driver out in l 1 m 2 gate_ls src_hs gate_hs inductive flyback voltage clamp in d c l m 1 v cc cp_out lr_out v gs < 14 v under all conditions figure 12. gate protection and flyback voltage clamp load dump and reverse battery v cc and v cc2 can sustain load a dump pulse of 40 v and do uble battery of 24 v. protection against reverse polarity is en sured by the external power mosfet with the free- wheeling diodes forming a conducting pass from ground to v cc . additional protection is not provided within the circuit. to protect the circuit an exte rnal diode can be put on the battery line. it is not recommended putting the diode on the ground line. temperature protection there is temperatur e shutdown protection per each half- bridge. temperature shutdown protects the circuitry against temperature damage by switchin g off the output drivers. its typical value is 175c with an hysteresis of 15c. dv/dt at v cc v cc voltage must be higher than (src_hs voltage minus a diode drop voltage) to avoid perturbation of the high-side driver. in some applications a large dv / dt at pin c2 owing to sudd en changes at v cc can cause large peak currents flowing through pin c1, as shown in figure 13 . for positive transitions at pin c2, the absolute value of the mini mum peak current, i c1 min, is specified at 2.0 a for a t c1 min duration of 600 ns. for negative transitions at pin c2, the maximum peak current, i c1 max, is specified at 2.0 a for a t c1 max duration of 600 ns. current sourced by pin c1 during a large dv / dt will resul t in a negative voltage at pin c1 ( figure 13 ). the minimum peak voltage v c1 min is specified at -1.5 v for a du ration of t c1 max = 600 ns. a series resistor with the charge pu mp capacitor (ccp) capacitor can be added in order to limit the surge current.
t c1 max t c1 min v cc i (c1+c2) i c1 max i c1 min v (lr_out) 0 v v (c1) 0 a v c1 min analog integrated circuit device data freescale semiconductor 17 33883 functional device operation protection and di agnostic features figure 13. limits of c1 current and voltage with large values of dv/dt in the case of rapidly changing v cc voltages, the large dv/ dt may result in perturbations of the high-side driver, thereby forcing the driver into an off state. the addition of capacitors c3 and c4, as shown in figure 14 , reduces the dv/dt of the source line, con sequently reducing driver perturbation. typical values for r3 / r4 and c3 / c4 are 10 : and 10 nf, respectively. dv/dt at v cc2 when the external high-side mosfet is on, in case of rapid negative change of v cc2 the voltage (v gate_hs - v src_hs ) can be higher than the specified 18 v. in this case a resistance in the src line is necessary to limit the current to 5.0 ma max. it will protect the internal zener placed be tween gate_hs and src pins. in case of high current (src_hs >100 ma) and high voltag e (>20 v) between gate_hsx and src_hs an externa l zener of 18 v is needed as shown in figure 14 .
in_ls2 in_hs2 in_ls1 in_hs1 v bat g_en c1 c2 c cp c lr_out c cp_out mcu vcc2 vcc v boost 33883 m1 m2 m3 m4 r1 r2 470 nf 470 nf 50 : 50 : 50 : 50 : 33 nf dc motor r3 10 : 10 nf c3 10 nf c4 10 : r4 in_ls2 in_hs2 in_ls1 in_hs1 g_en c1 c2 vcc2 vcc gnd gate_ls2 src_hs2 gate_hs2 gate_ls1 src_hs1 gate_hs1 lr_out cp_out 18 v 18 v analog integrated circuit device data 18 freescale semiconductor 33883 typical applications typical applications figure 14. application schematic with external protection circuit
analog integrated circuit device data ? freescale semiconductor 19 33883 packaging packaging dimensions packaging packaging dimensions important for the most current revision of the package, visit www.freescale.com and do a keyword search on the 98asb42343b drawing num ber below. dimensions shown ar e provided for re ference only. dw suffix eg suffix (pb-free) 20-pin soicw plastic package 98asb42343b issue j
analog integrated circuit device data ? 20 freescale semiconductor 33883 revision history packaging dimensions revision history revision date description of changes 9.0 1/2007 ? implemented revision history page ? updated to the current freescale format and style ? added mcz33883eg/r2 to the ordering information ? updated the package drawing to rev. j ? removed peak package reflow temperature during reflow (solder reflow) parameter from maximum ratings on page 4 . added note with instructions from www.freescale.com. 10.0 10/2012 ? updated orderable part number from mcz33883eg to MC33883HEG. ? updated freescale form and style ? removed mc33883dw from the ordering information
document number: mc33883 rev 10.0 10/2012 information in this document is provi ded solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabric ate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be pr ovided in freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: store.esellerate.net/store/p olicy.aspx?selector=rt&s=str0326182960&pc. how to reach us: home page: freescale.com web support: freescale.com/support freescale, the freescale logo, altivec, c-5, codetest, codewarrior, coldfire, c- ware, energy efficient solutions logo, kinetis, mobilegt, powerquicc, processor expert, qoriq, qorivva, starcore, symphony, and vortiqa are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. airfast, beekit, beestack, coldfire+, corenet, flexis, magniv, mxc, platform in a package, qoriq qonverge, quicc engine, ready play, safeassure, sm artmos, turbolink, vybrid, and xtrinsic are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? ? 2012 freescale semiconductor, inc.

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