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| 1. general description the greenchip iii is the third generation of green switched mode power supply (smps) controller ics. the TEA1753T combines a controller for power factor correction (pfc) and a flyback controller. its high level of integration allows the design of a cost-effective power supply with a very low number of external components. the special built-in green functions provide high efficiency at all powe r levels. this applies to quasi-resonant operation at high power levels, quasi-resonan t operation with valley skipping, as well as to reduced frequency opera tion at lower power levels. at low power levels, the pfc switches off to maintain high efficiency. during low power condit ions, the flyback controller switches to frequency reduction mode and limits the peak current to an adjustable minimum value. this will ensure high efficiency at low power and good standby po wer performance while minimizing audible noise from the transformer. for no-load operation, the controller can be switched to the power down mode. in this mode the controller is shutdown for very low standby power applications. the TEA1753T is a multichip module, (mcm), containing 2 chips. the proprietary high voltage bcd800 process which makes direct st art-up possible from the rectified universal mains voltage in an effective and green way. the second low voltage silicon on insulator (soi) is used for accu rate, high s peed protection functions and control. the TEA1753T enables highly efficient and reliable supplies with power requirements of up to 250 w to be designed easily and wit h a minimum number of external components. remark: it should be noted that all values provided throughout the running text, are typical values unless otherwise stated. TEA1753T greenchip iii smps control ic rev. 2 ? 8 april 2011 product data sheet
TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 2 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic 2. features and benefits 2.1 distinctive features ? integrated pfc and flyback controller ? universal mains supply operation (70 v ac to 276 v ac) ? dual boost pfc with accurate maximum output voltage (nxp patented) ? high level of integration, re sulting in a very low external component count and a cost-effective design ? adjustable pfc switch-off delay 2.2 green features ? on-chip start-up current source ? power down functionality for very low standby power 2.3 pfc green features ? valley/zero voltage switching for mi nimum switching losses (nxp patented) ? frequency limitation to reduce switching losses ? pfc is switched off when a low load is detected at the flyback output 2.4 flyback green features ? valley switching for minimum switching losses (nxp patented) ? frequency reduction with adjustable minimum peak current at low power operation to maintain high efficiency at low output power levels 2.5 protection features ? safe restart mode for system fault conditions ? continuous mode protection by means of demagnetization detection for both converters (nxp patented) ? undervoltage protection (uvp) (foldback during overload) ? accurate overvoltage protection (ovp) for both converters (adjustable for flyback converter) ? mains voltage independent overpower protection (opp) ? open control loop protection for both converters. the open-loop protection on the flyback converter is safe restart ? ic overtemperature protection (otp) ? low and adjustable overcurrent protection (ocp) trip level for both converters ? general purpose input for latched protection, e.g. to be used for system overtemperature protection (otp) 3. applications ? the device can be used in all applications that require an efficient and cost-effective power supply solution for up to 250 w. notebook adapte rs in particular can benefit from the high level of integration TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 3 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic 4. ordering information table 1. ordering information type number package name description version TEA1753T so16 plastic small outline packa ge; 16 leads; body width 3.9 mm sot109-1 TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 4 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic 5. block diagram fig 1. block diagram timer 50 s timer 4 s pfc protection v o ovp v o start flyback v o short ocp pfc driver enable pfc start stop pfc 500 mv pfc gate valley detect blank 2.50 v 3.5 v 2.5 v 1.25 v maximum external protection protection external protection v startup charge control safe restart protection start flyback start stop pfc protection v cc good v cc good charge pfc protection protection latch reset enable pfc r s q v o start flyback low power delay pfc clamp smps control start soft start flyback enable flyback enable flyback blank q r s flyback oscillator t on(max) frequency reduction external protection time-out flyback driver flyback gate 12 13 pfc driver pfc gate vinsense pfccomp vosense pfcsense pfcaux otp charge valley detect otp internal supply zero current signal zero current signal flyback gate fbaux fbsense counter ovp ovp flyback 3.5 v 7 6 11 8 9 hv v cc 16 1 gnd 5 3 10 4 fbctrl latch 80 mv pfcdriver fbdriver v startup v th(uvlo) v th(uvlo) 001aan849 protection 80 a 60 a 30 a 3.7 v clamp ocp frequency reduction 1.25 v flyback driver 2.5 v 3.5 v temperature -100 mv 8 a boost boost boost low vin power down ton max power down power down opp opp opp minimum 2 low power delay low power pfctimer 14 delay 60 a 3 a ovp flyback external protection otp latch reset s s s r latched protection pfc clamp clamp soft start soft stop low power low power delay time-out r s s v o short low vin v uvlo driver driver pfc oscillator TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 5 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin configuration: TEA1753T (sot109-1) TEA1753T v cc hv gnd hvs fbctrl pfctimer fbaux fbdriver latch pfcdriver pfccomp pfcsense vinsense fbsense pfcaux vosense 001aan780 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 table 2. pin description symbol pin description v cc 1 supply voltage gnd 2 ground fbctrl 3 control input for flyback fbaux 4 input from auxiliary winding for demagnetization timing and overvoltage protection for flyback latch 5 general purpose protection input pfccomp 6 frequency compensation pin for pfc vinsense 7 sense input for mains voltage pfcaux 8 input from auxiliary winding for demagnetization timing for pfc vosense 9 sense input for pfc output voltage fbsense 10 programmable current sense input for flyback pfcsense 11 programmable current sense input for pfc pfcdriver 12 gate driver output for pfc fbdriver 13 gate driver output for flyback pfctimer 14 delay timer pin for pfc on/off control hvs 15 high voltage safety spacer, not connected hv 16 high voltage start-up and valley sensing of flyback part TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 6 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic 7. functional description 7.1 general control the TEA1753T contains a controller for a power factor correction circuit as well as a controller for a flyback circuit. a typical configuration is shown in figure 3 . 7.1.1 start-up and undervoltage lockout (uvlo) initially the capa citor on the v cc pin is charged from the high voltage mains via the hv pin. as long as v cc is below v trip , the charge current is low. this protects the ic in case the v cc pin is shorted to ground. for a short start-up time the charge current above v trip is increased until v cc reaches v th(uvlo) . if v cc is between v th(uvlo) and v startup , the charge current is low again, ens uring a low duty cycle during fault conditions. the control logic activates the internal circui try and switches off the hv charge current when the voltage on pin v cc passes the v startup level. first, the latch pin current source is activated and the soft start capacito rs on the pfcsense and fbsense pins are charged. also the clamp circuit on the pfcco mp pin is activated. when the latch pin voltage exceeds the v en(latch) voltage, the pfccomp pin voltage reaches the v en(pfccomp) voltage and the soft start capacitor on the pfcsense pin is charged, the pfc circuit is activated. also the flyback conv erter is activated (providing the soft start capacitor on the fbsense pin is charged). the output voltage of the flyback converter is then regulated to its nominal output voltage. the ic supply is taken over by the auxiliary winding of the flyback converter. see figure 4 . if during start-up the latch pin does not reach the v en(latch) level before v cc reaches v th(uvlo) , the latch pin output is deactivated an d the charge current is switched on again. fig 3. a typical configuration of the TEA1753T ic 12 11 9 16 13 8 6 7 3 2 10 4 1 5 TEA1753T 001aan781 TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 7 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic as soon as the flyback converter is started, the voltage on the fbctrl pin is monitored. if the output voltage of the flyback converter does not reach its intended regulation level within a predefined time, the voltag e on the fbctrl pin reaches the v to(fbctrl) level, an error is assumed and a safe restart is initiated. when one of the protection functions is activa ted, both converters stop switching and the v cc voltage drops to v th(uvlo) . a latched protection recharges the capacitor c vcc via the hv pin, but does not restart the converters. fo r a safe restart protection, the capacitor is recharged via the hv pin and the device restarts (see block diagram, figure 1 ). in the event of an overvoltage protection of the pfc circuit, v vosense >v ovp(vosense) , only the pfc controller stops switching until the vosense pin voltage drops below v ovp(vosense) again. also, if a mains undervoltage is detected v vinsense TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 8 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic 7.1.2 power down for very low standby power applications the power-down mode can be activated by pulling the vinsense pin below the v th(pd) level. the TEA1753T will stop switching and the safe restart protection will be activated. because the high volt age start-up current source is also disabled during power-dow n, the TEA1753T will no t restart until the vinsense pin voltage is raised again. during power down all internal circuitry is disabled except for a voltage detection circuit on the vinsense pin. this circuit is supplied by the hv pin and will draw 16 a from the hv pin for biasing. fig 4. start-up sequence, normal operation and restart sequence v cc latch protection pfcsense pfcdriver fbsense fbdriver fbctrl vosense v o charging vcc capacitor starting converters normal operation protection restart soft start soft start i hv v start(vinsense) v to(fbctrl) v startup v th(uvlo) v trip v en(la tch) v start(fb) vinsense 014aaa744 pfccomp v en(pfccomp) TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 9 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic 7.1.3 supply management all internal reference voltages are derived from a temperature compensated and trimmed on-chip band gap circuit. internal reference currents are derived from a temperature compensated and trimmed on-chip current reference circuit. 7.1.4 latch input pin latch is a general purpose input pin, which is used to switch off both converters. the pin sources a current i o(latch) of 80 a. switching off both converters is stopped as soon as the voltage on this pin drops below 1.25 v. at initial start-up the switchin g is inhibited until the capacitor on the latch pin is charged above 1.35 v. no internal filtering is done on this pin. an internal zener clamp of 2.9 v protects this pin from excessive voltages. 7.1.5 fast latch reset in a typical application the main s can be interrupted briefly to reset the latched protection. the pfc bus capacitor, c bus , does not have to discharge for this latched protection to reset. the pfc bus capacitor, c bus , must discharge to allow the v cc to drop to the reset level. when the latched protection is set, the clamping circuit of the vinsense circuit is disabled (see also section 7.2.10 ). as soon as the vinsense voltage drops below 750 mv and after that is raised to 870 mv, the latched protection is reset. the latched protection is also reset by removing both the voltage on pin v cc and on pin hv. 7.1.6 overtemperature protection an accurate internal temperature protection is provided in the circuit. when the junction temperature exceeds the thermal shut-down temp erature, the ic stops switching. as long as otp is active, the capacitor c vcc is not recharged from the hv mains. the otp circuit is supplied from the hv pin if the v cc supply voltage is not sufficient. otp is a latched protection. it can be reset by removing both the voltage on pin v cc and on pin hv or by the fast latch reset function (see section 7.1.5 ). 7.2 power factor correction circuit the power factor correction circuit oper ates in quasi-resonant or discontinuous conduction mode with valley switching. the ne xt primary stroke is only started when the previous secondary stroke has ended and the voltage across the pfc mosfet has reached a minimum value. the voltage on the pfcaux pin is used to detect transformer demagnetization and the minimum voltage ac ross the external pfc mosfet switch. 7.2.1 t on control the power factor correction circuit is operated in t on control. the resulting mains harmonic reduction of a typical application is well within the class-d requirements. TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 10 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic 7.2.2 valley switching and demagnetization (pfcaux pin) the pfc mosfet is switched on after the trans former is demagnetized. internal circuitry connected to the pfcaux pin detects the end of the secondary stroke. it also detects the voltage across the pfc mosfet. the next stroke is started if the voltage across the pfc mosfet is at its minimum in order to reduce switching losses and electromagnetic interference (emi) (valley switching). if no demagnetization signal is detected on the pfcaux pin, the controller generates a zero current signal (zcs), 50 s after the last pfcgate signal. if no valley signal is detected on the pfcaux pin, the controller generates a valley signal 4 s after demagnetization is detected. to protect the internal circuitry during lightning events, for example, it is advisable to add a 5k series resistor to this pin. to prevent in correct switching due to external disturbance, the resistor should be placed close to the ic on the printed-circuit board. 7.2.3 frequency limitation to optimize the transformer and minimize s witching losses, the s witching frequency is limited to f sw(pfc)max . if the frequency for quasi-res onant operation is above the f sw(pfc)max limit, the system switches over to discon tinuous conduction mode. also here, the pfc mosfet is only switched on at a minimum vo ltage across the switch (valley switching). 7.2.4 mains voltage compensation (vinsense pin) the mathematical equation for the transfer fu nction of a power factor corrector contains the square of the mains inpu t voltage. in a typical application this results in a low bandwidth for low mains input voltages, while at high mains input voltages the mains harmonic reduction (m hr) requirements may be hard to meet. to compensate for the mains input voltage infl uence, the TEA1753T contains a correction circuit. via the vinsense pin the average input voltage is measured and the information is fed to an internal compensation circuit. with this compensation it is possible to keep the regulation loop bandwidth constant over the fu ll mains input range, yielding a fast transient response on load steps, while still comp lying with class-d mhr requirements. in a typical application, the bandwidth of the re gulation loop is set by a resistor and two capacitors on the pfccomp pin. 7.2.5 soft start-up (pin pfcsense) to prevent audible transformer noise at start- up or during hiccup, the transformer peak current is increased slowly by the soft start function. this can be achieved by inserting r ss1 and c ss1 between pin pfcsense and current sense resistor r sense1 . an internal current source charges the capacitor to: (1) the voltage is limited to v start(soft)pfc . the start level and the time constant of the increasing primary current level can be adjusted externally by changing the values of r ss1 and c ss1 . (2) v pfcsense i start soft () pfc r ss1 = softstart 3 r ss1 c ss1 = TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 11 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic the charging current i start(soft)pfc flows as long as the voltage on pin pfcsense is below 0.5 v. if the voltage on pin pfcsense exceeds 0.5 v, the soft start current source starts limiting current i start(soft)pfc . as soon as the pfc starts switching, the i start(soft)pfc current source is switched off; see figure 5 . 7.2.6 low power mode when the output power of the flyback converter (see section 7.3 ) is low, the flyback converter switches over to frequency re duction mode. when the maximum switching frequency of the flyback drops below 48 khz, the power factor correction circuit is switched off to maintain high efficiency. the switch-off can be delayed by connecting a capacitor to the pf ctimer pin (see section 7.2.7 ). during low power mode operation, the pfccomp pin is clamped to a minimum voltage of 3.5 v or 2.5 v, dependent on the voltage on vinsense pin, and a maximum voltage of 3.7 v. the lower clamp voltage limits the maximum power that is delivered when the pfc is switched on again. the upper clamp voltage ensures that the pfc can return to its normal regulation point in a limited amount of time when returning from low power mode. as soon as the maximum switching frequency of the flyback converter exceeds 86 khz, the power factor correction ci rcuit restores normal operation. 7.2.7 pfc off delay (pin pfctimer) when the maximum switching frequency of the flyback controller drops below 48 khz, the pfc is switched off. to prevent the pfc from switching off due to a fast changing load at the flyback output, the pfc switch-off can be delayed by connecting a capacitor to the pfctimer pin. when the flyback controller part detects a lo w power, it enters frequency reduction mode and the ic outputs a 5 a current to the pfctimer pin. when the voltage on the pfctimer pin reaches 3.6 v, the pfc is sw itched off by performing a soft stop. when the flyback controller part leaves the frequency reduction mode, a switch discharges the pfctimer pin capacitor. wh en the voltage on the pctimer pin drops below 1.27 v, the pfc is switched on (see figure 6 ). fig 5. soft start-up of pfc soft start soft stop control ocp 11 pfcsense 0.5 v i start(soft)pfc 60 a s1 r ss1 c ss1 r sense1 014aaa75 6 TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 12 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic 7.2.8 dual boost pfc the pfc output voltage is modulated by the mains input voltage. the mains input voltage is measured via the vinsense pin. the current is sourced from the vosense pin if the voltage on the vinsense pin drops below 2.2 v. to ensure the stable switch-over, a 200 mv transition region is inserted around the 2.2 v, see figure 7 . for low vinsense input voltag es, the output current is 8 a. this output current, in combination with the resistors on the vosense pin, sets the lower pfc output voltage level at low mains voltages. at high mains input voltages the current is switched to zero. the pfc output voltage will then be at its maximum. as this current is zero in this situation, it does not effect the ac curacy of the pfc output voltage. for proper switch-off behavior, the vosense cu rrent is switched to its maximum value of 8 a, as soon as the voltage on pin vosense drops below 2.1 v . 7.2.9 overcurrent protection (pfcsense pin) the maximum peak current is limited cycle-by-c ycle by sensing the voltage across an external sense resistor, r sense1 , on the source of the external mosfet. the voltage is measured via the pfcsense pin. 7.2.10 mains undervoltage lockout/brownout protection (vinsense pin) to prevent the pfc from operating at very low mains input voltages, the voltage on the vinsense pin is sensed continuou sly. as soon as the voltage on this pin drops below the v stop(vinsense) level, switching of the pfc is stopped. fig 6. pfc start/stop via ppfctimer pin r s q 1.27 v low power delay (pfc on) 3.6 v 5 a 14 pfctimer low power 014aaa740 fig 7. voltage to current transfer function for dual boost pfc v vinsense i i(vosense) 014aaa09 7 ? 8 a 2.2 v TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 13 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic 7.2.11 overvoltage protection (vosense pin) to prevent output overvoltage during load steps and mains transients an overvoltage protection circuit is built in. as soon as the voltage on the vosense pin exceeds the v ovp(vosense) level, switching of the power factor correction circuit is in hibited. switching of the pfc recommences as soon as the vosense pin voltage drops below the v ovp(vosense) level again. when the resistor between pin vosense and ground is open, the overvoltage protection is also triggered. 7.2.12 pfc open-loop protection (vosense pin) the power factor correction circuit does not start switching until the voltage on the vosense pin is above the v th(ol)(vosense) level. this protects the circuit from open-loop and vosense short situations. 7.2.13 driver (pfcdriver pin) the driver circuit to the gate of the power mosfet has a current so urcing capability of ? 500 ma and a current sink capability of 1.2 a. th is permits fast turn-on and turn-off of the power mosfet for efficient operation. 7.3 flyback controller the TEA1753T includes a controller for a flyback converter. the flyback converter operates in quasi-resonant or discontinuous conduction mode with valley switching. the auxiliary winding of the flyback transforme r provides demagnetiz ation detection and powers the ic after start-up. 7.3.1 multimode operation the TEA1753T flyback controller can operate in several modes; see figure 8 . fig 8. multimode operation flyback discontinuous with valley switching quasi-resonant pfc off frequency reduction output power flyback switching frequency 014aaa745 pfc on 86 khz 48 khz 125 khz i pmin adjust TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 14 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic at high output power the co nverter switches to quasi-resonant mode. the next converter stroke is started after demagnetization of th e transformer current. in quasi-resonant mode switching losses are minimized as the converter only switches on when the voltage across the external mosfet is at its mi nimum (valley switching, see also section 7.3.2 ). to prevent high frequency operation at lowe r loads, the quasi-resonant operation changes to discontinuous mode operation with valley skip ping in which the switching frequency is limited for emi to f sw(fb)max (125 khz). again, the external mosfet is only switched on when the voltage across the mosfet is at its minimum. at very low power and standby levels the frequency is controlled down by a voltage controlled oscillato r (vco). the minimum frequency c an be reduced to zero. during frequency reduction mode, the primary peak current is kept at an adjustable minimal level to maintain a high efficiency. as the primary peak current is low in frequency reduction operation, no audible noise is noticeable at switching frequencies in the audible range. valley switching is also active in this mode. in frequency reduction mode the pfc controller is switched off and the flyback maximum frequency changes linearly with the control voltage on the fbctrl pin (see figure 9 ). for stable on and off switching of the pfc, hysteresis has been added. at no load operation the switching frequency can be reduced to (almost) zero. 7.3.2 valley switching (hv pin) refer to figure 10 . a new cycle starts when the extern al mosfet is activated. after the on-time (determined by the fbsense voltage and the fbctrl voltage), the mosfet is switched off and the secondary stroke starts. after the secondary stroke, the drain voltage shows an oscillation with a frequency of approximately: (3) where l p is the primary self-inductance of the flyback transformer and c d is the capacitance on the drain node. fig 9. frequency control of flyback v fbctrl 1.5 v discontinuous with valley switching quasi-resonant frequency reduction pfc off flyback switching frequency 014aaa74 6 pfc on f sw(fb)max f 1 2 l p c d () [] -------------------------------------------------- - = TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 15 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic as soon as the internal osc illator voltage is high again a nd the secondary stroke has ended, the circuit waits for the lowest drain voltage before starting a new primary stroke. figure 10 shows the drain voltage, valley signal, se condary stroke signal and the internal oscillator signal. valley switching allows high frequency operat ion as capacitive switching losses are reduced, see equation 4 . high frequency operation makes small and cost-effective magnetics possible. (4) 7.3.3 current mode control (fbsense pin) current mode control is used for the flyb ack converter for its good line regulation. the primary current is sensed by the fbse nse pin across an external resistor and compared with an internal control voltage. the internal control voltage is proportional to the fbctrl pin voltage, see figure 11 . the fbsense pins outputs a current of 3 a. this current runs through the resistors from the fbsense pin to the sense resistor and cr eates an offset volt age. the minimum peak current of the flyback is adjusted using this offset voltage. adjusting the minimum peak current level, will change the fr equency reduction slope (see figure 8 ). (1) start of new cycle at lowest drain voltage. (2) start of new cycle in a cl assical pulse width modulation (pwm) system without valley detection. fig 10. signals for valley switching p 1 2 -- - c d v 2 f = drain secondary stroke 014aaa02 7 secondary ringing primary stroke valley (2) (1) secondary stroke oscillator TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 16 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic the driver output is latched in the logic, preventing multiple switch-on. 7.3.4 demagnetization (fbaux pin) the system is always in quasi-resonant or discontinuous conduction mode. the internal oscillator does not start a new primary stroke unt il the previous secondary stroke has ended. demagnetization features a cycl e-by-cycle output short circuit protection by immediately lowering the frequency (longer off-time ), thereby reducing the power level. demagnetization recognition is suppressed during the first t sup(xfmr_ring) time of 2 s. this suppression may be necessary at low output voltages and at start-up and in applications where the transformer has a large leakage inductance. if pin fbaux is open circuit or not connecte d, a fault condition is assumed and the converter stops operating immediately. operation restarts as soon as the fault condition is removed. 7.3.5 flyback control/time-out (fbctrl pin) the pin fbctrl is connected to an internal voltage source of 3.5 v via an internal resistor of 3 k . as soon as the voltage on this pin exceeds 2.5 v, the connection is disabled and the pin is biased with a small current. when the voltage on this pin exceeds 4.5 v, a fault is assumed, switching is inhibited and a restart is made. when a small capacitor is connected to this pi n, a time-out function is created to protect against an open control loop situation (see figure 12 and figure 13 ). the time-out function is disabled by connecting a resistor (100 k ) to ground on the fbctrl pin. if the pin is shorted to ground, switching of the flyback controller is inhibited. during normal operating conditions, when the converter is regulating the output voltage, the voltage on the fbctrl pin is between 1.3 v and 2.0 v from minimum to maximum output power. fig 11. peak current control of flyback part v fbctrl 1.5 v 2.0 v 0.65 v flyback frequency reduction pfc off fbsense peak voltage 014aaa74 7 pfc on flyback discontinuous or qr flyback cycle skip mode sense resistor peak voltage fbsense offset voltage v sense(fb)max 0.325 v TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 17 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic 7.3.6 soft start-up (fbsense pin) to prevent audible transformer noise during start-up, the transformer peak current is slowly increased by the soft start function. this can be achieved by inserting a resistor and a capacitor between pin 10 (fbsense) and the current sense resistor. an internal current source charges the capacitor to: (5) with a maximum of approximately 0.63 v. the start level and the time constant of the increasing primary current level can be adjusted externally by changing the values of r ss2 and c ss2 . (6) the soft start current i start(soft)fb is switched on as soon as v cc reaches v startup . when the voltage on pin fbsense has reached 0.63 v the flyback converter starts switching. fig 12. time-out protection circuit fig 13. time-out protection (signals), safe restart in the TEA1753T 014aaa049 fbctrl 2.5 v 4.5 v 30 a 3 k 3.5 v time-out 014aaa05 0 4.5 v 2.5 v v fbctrl output voltage intended output voltage not reached within time-out time. intended output voltage reached within time-out time. restart vi start soft () fb r ss2 = softstart 3 r ss2 c ss2 = TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 18 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic the charging current i start(soft)(fb) flows as long as the voltage on pin fbsense is below approximately 0.63 v. if the voltage on pin fbsense exceeds 0.63 v, the soft start current source starts limiting the current. after the flyback converter has started, the soft start current source is switched off. 7.3.7 maximum on-time the flyback controller limits the ?on-ti me? of the external mosfet to 40 s. when the ?on-time? is longer than 40 s, the ic stops switching and enters the safe restart mode. 7.3.8 overvoltage protection (fbaux pin) an output overvoltage protection is impl emented in the greenchip iii series. in the TEA1753T this works by sensing the auxilia ry voltage via the current flowing into pin fbaux during the secondary stroke. the auxiliary winding voltage is a well-defined replica of the output voltage. voltage spik es are averaged by an internal filter. if the output voltage exceeds the ovp trip level, an internal counter starts counting subsequent ovp events. the counter has been added to prevent incorrect ovp detection which might occur during esd or lightning ev ents. if the output voltage exceeds the ovp trip level a few times and not again in a subsequent cycle, the internal counter counts down at twice the speed it uses when counting up. however, after 8 cycles of subsequent ovp events are detected, the ic assumes a true ovp and the ovp circuit switches the power mosfet off. as the protection is latc hed, the converter only restarts after the internal latch is reset. in a typical application the mains should be interrupted to reset the internal latch. the output voltage v o(ovp) at which the ovp function trips, can be set by the demagnetization resistor, r fbaux : (7) where n s is the number of secondary turns and n aux is the number of au xiliary turns of the transformer. current i ovp(fbaux) is internally trimmed. the value of r fbaux can be adjusted to the turns ratio of the transformer, thus making an accurate ovp detection possible. fig 14. soft start-up of flyback. 014aaa74 8 soft start control ocp 10 fbsense s2 r ss2 c ss2 r sense2 3 a ocp level i start(soft)fb 60 a v oovp () n s n aux ---------- - i ovp fbaux () r fbaux v clamp fbaux () + () = TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 19 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic 7.3.9 overcurrent protection (fbsense pin) the primary peak current in the transformer is measured accurately cycle-by-cycle using the external sense resistor r sense2 . the ocp circuit limits the voltage on pin fbsense to an internal level (see also section 7.3.3 ). the ocp detection is suppressed during the leading edge blanking period, t leb , to prevent false triggering caused by switch-on spikes. 7.3.10 overpower protection during the primary stroke of the flyback converter the input voltage of the flyback converter is measured by sensing the curr ent that is drawn from the pin fbaux. the current information is used to adjust the peak drain current of the flyback converter, which is measured via pin fbsense. the inte rnal compensation is such, that a maximum output power can be realized that is almost independent of the input voltage. the opp curve is given in figure 16 . 7.3.11 driver (fbdriver pin) the driver circuit to the gate of the external power mosfet has a current sourcing capability of ? 500 ma and a current sink capability of 1.2 a. this permits fast turn-on and turn-off of the power mosfet for efficient operation. fig 15. ocp leading edge blanking t leb ocp level v fbsense t 014aaa02 2 fig 16. overpower protection curve ? 360 0 ? 100 014aaa74 9 0.65 0.46 i fbaux ( a) v fbsense (v) TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 20 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic 8. limiting values [1] equivalent to discharging a 100 pf capacitor through a 1.5 k series resistor. [2] equivalent to discharging a 200 pf capacitor through a 0.75 h coil and a 10 resistor. table 3. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit voltages v cc supply voltage ? 0.4 +38 v v latch voltage on pin latch current limited ? 0.4 +5 v v fbctrl voltage on pin fbctrl ? 0.4 +5 v v pfccomp voltage on pin pfccomp ? 0.4 +5 v v vinsense voltage on pin vinsense ? 0.4 +5 v v vosense voltage on pin vosense ? 0.4 +5 v v pfcaux voltage on pin pfcaux ? 25 +25 v v fbsense voltage on pin fbsense current limited ? 0.4 +5 v v pfcsense voltage on pin pfcsense current limited ? 0.4 +5 v v pfctimer voltage on pin pfctimer ? 0.4 +5 v v hv voltage on pin hv ? 0.4 +650 v currents i fbctrl current on pin fbctrl ? 30 ma i fbaux current on pin fbaux ? 1+1ma i pfcsense current on pin pfcsense ? 1+10ma i fbsense current on pin fbsense ? 1+10ma i fbdriver current on pin fbdriver duty cycle < 10 % ? 0.8 +2 a i pfcdriver current on pin pfcdriver duty cycle < 10 % ? 0.8 +2 a i hv current on pin hv - 8 ma general p tot total power dissipation t amb <75 c-0.6w t stg storage temperature ? 55 +150 c t j junction temperature ? 40 +150 c esd v esd electrostatic discharge voltage class 1 human body model pins 1 to 13 [1] -2000v pin 16 (hv) [1] -1500v machine model [2] -200v charged device model -500v TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 21 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic 9. thermal characteristics 10. characteristics table 4. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air; jedec test board 124 k/w r th(j-c) thermal resistance from junction to case in free air; jedec test board 37 k/w table 5. characteristics t amb =25 c; v cc = 20 v; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the ic; unless otherwise specified. symbol parameter conditions min typ max unit start-up current source (pin hv) i hv current on pin hv v hv >80v v cc TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 22 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic v bst(dual) dual boost voltage current switch-over point - 2.2 - v switch-over region - 200 - mv v th(pd) power-down threshold voltage 305 355 405 mv v hys(pd) power-down hysteresis voltage 55 85 120 mv loop compensation pfc (pin pfccomp) g m transconductance v vosense to i o(pfccomp) 60 80 100 a/v i o(pfccomp) output current on pin pfccomp v vosense = 2.0 v 33 39 45 a v vosense = 3.3 v ? 45 ? 39 ? 33 a v en(pfccomp) enable voltage on pin pfccomp vinsense v bst(dual) 3.5 v vinsense < v bst(dual) 2.5 v v clamp(pfccomp) clamp voltage on pin pfccomp low power mode; pfc off; lower clamp voltage. [1] vinsense v bst(dual) -3.5-v vinsense < v bst(dual) -2.5-v upper clamp voltage - 3.7 - v v ton(pfccomp)zero zero on-time voltage on pin pfccomp 3.4 3.5 3.6 v v ton(pfccomp)max maximum on-time voltage on pin pfccomp 1.20 1.25 1.30 v pulse width modulator pfc t on(pfc) pfc on-time v vinsense =3.3v; v pfccomp =v ton(pfccomp)max 3.6 4.5 5.0 s v vinsense =0.9v; v pfccomp =v ton(pfccomp)max 30 40 53 s output voltage sensing pfc (pin vosense) v th(ol)(vosense) open-loop threshold voltage on pin vosense -1.15-v v reg(vosense) regulation voltage on pin vosense for i o(pfccomp) = 0 2.475 2.500 2.525 v v ovp(vosense) overvoltage protection voltage on pin vosense 2.60 2.63 2.67 v i bst(dual) dual boost current v vinsense TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 23 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic soft start pfc (pin pfcsense) i start(soft)pfc pfc soft start current ? 75 ? 60 ? 45 a v start(soft)pfc pfc soft start voltage enabling voltage 0.46 0.50 0.54 v v stop(soft)pfc pfc soft stop voltage disabling voltage 0.42 0.45 0.48 v r start(soft)pfc pfc soft start resistance 12 - - k oscillator pfc f sw(pfc)max maximum pfc switching frequency -250-khz t off(pfc)min minimum pfc off-time 0.8 1.1 1.4 s valley switching pfc (pin pfcaux) ( v/ t) vrec(pfc) pfc valley recognition voltage change with time --1.7v/ s t vrec(pfc) pfc valley recognition time v pfcaux = 1 v peak-peak [2] --300ns demagnetization to v/ t=0 [3] --50ns t to(vrec)pfc pfc valley recognition time-out time 346 s demagnetization management pfc (pin pfcaux) v th(comp)pfcaux comparator threshold voltage on pin pfcaux ? 150 ? 100 ? 50 mv t to(demag)pfc pfc demagnetization time-out time 40 50 60 s i prot(pfcaux) protection current on pin pfcaux v pfcaux =50mv ? 75 - ? 5na pfc off delay (pin pfctimer) i source(pfctimer) source current on pin pfctimer - ? 5- a i sink(pfctimer) sink current on pin pfctimer, v pfctimer = 5 v - 3.5 - ma v start(pfctimer) start voltage on pin pfctimer - 1.27 - v v stop(pfctimer) stop voltage on pin pfctimer - 3.6 - v driver (pin pfcdriver) i src(pfcdriver) source current on pin pfcdriver v pfcdriver =2v - ? 0.5 - a i sink(pfcdriver) sink current on pin pfcdriver v pfcdriver =2v - 0.7 - a v pfcdriver =10v -1.2-a v o(pfcdriver)max maximum output voltage on pin pfcdriver -1112v over voltage protect ion flyback (pin fbaux) i ovp(fbaux) overvoltage protection current on pin fbaux 279 300 321 a n cy(ovp) number of overvoltage protection cycles 6812 table 5. characteristics ?continued t amb =25 c; v cc = 20 v; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the ic; unless otherwise specified. symbol parameter conditions min typ max unit TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 24 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic demagnetization management flyback (pin fbaux) v th(comp)fbaux comparator threshold voltage on pin fbaux 60 80 110 mv i prot(fbaux) protection current on pin fbaux v fbaux =50mv ? 75 - ? 5na v clamp(fbaux) clamp voltage on pin fbaux i fbaux = ? 100 a ? 0.85 ? 0.7 ? 0.55 v i fbaux =300 a 0.79 0.94 1.09 v t sup(xfmr_ring) transformer ringing suppression time 1.5 2 2.5 s pulse width modulator flyback t on(fb)min minimum flyback on-time - t leb -ns t on(fb)max maximum flyback on-time 32 40 48 s oscillator flyback f sw(fb)max maximum flyback switching frequency 100 125 150 khz v start(vco)fbctrl vco start voltage on pin fbctrl 1.3 1.5 1.7 v f sw(fb)swon(pfc) pfc switch-on flyback switching frequency - 86 - khz f sw(fb)swoff(pfc) pfc switch-off flyback switching frequency - 48 - khz v vco(fbctrl) vco voltage difference on pin fbctrl - ? 0.2 - v peak current control flyback (pin fbctrl) v fbctrl voltage on pin fbctrl for maximum flyback peak current 1.85 2.0 2.15 v v to(fbctrl) time-out voltage on pin fbctrl enable voltage - 2.5 - v trip voltage 4.2 4.5 4.8 v r int(fbctrl) internal resistance on pin fbctrl -3-k i o(fbctrl) output current on pin fbctrl v fbctrl =0v ? 1.4 ? 1.19 ? 0.93 ma v fbctrl =2v ? 0.6 ? 0.5 ? 0.4 ma i to(fbctrl) time-out current on pin fbctrl v fbctrl =2.6v ? 36 ? 30 ? 24 a v fbctrl =4.1v ? 34.5 ? 28.5 ? 22.5 a valley switching flyback (pin hv) ( v/ t) vrec(fb) flyback valley recognition voltage change with time ? 75 - +75 v/ s t d(vrec-swon) valley recognition to switch-on delay time [4] -150-ns soft start flyback (pin fbsense) i start(soft)fb flyback soft start current ? 75 ? 60 ? 45 a v start(soft)fb flyback soft start voltage enable voltage 0.55 0.63 0.70 v r start(soft)fb flyback soft start resistance 16 - - k table 5. characteristics ?continued t amb =25 c; v cc = 20 v; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the ic; unless otherwise specified. symbol parameter conditions min typ max unit TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 25 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic [1] for a typical application with a compensation network on pin pfccomp, like the example in figure 3 . [2] minimum required voltage change time for valley recognition on pin pfcaux. [3] minimum time required between demagnetization detection and v/ t = 0 on pin pfcaux. [4] guaranteed by design. overcurrent protection flyback (pin fbsense) v sense(fb)max maximum flyback sense voltage v/ t=50mv/ s 0.61 0.65 0.69 v v/ t=200mv/ s 0.64 0.68 0.72 v sense(fb)min minimum flyback sense voltage v/ t=50mv/ s 0.305 0.325 0.345 v t leb(fb) flyback leading edge blanking time 255 305 355 ns i adj(fbsense) adjust current on pin fbsense ? 3.2 ? 3 ? 2.8 a overpower protection flyback (pin fbsense) v sense(fb)max maximum flyback sense voltage v/ t=50mv/ s i fbaux =80 a 0.61 0.65 0.69 v i fbaux =120 a 0.57 0.62 0.67 v i fbaux =240 a 0.47 0.52 0.57 v i fbaux =360 a 0.41 0.46 0.51 v driver (pin fbdriver) i src(fbdriver) source current on pin fbdriver v fbdriver =2v - ? 0.5 - a i sink(fbdriver) sink current on pin fbdriver v fbdriver =2v - 0.7 - a v fbdriver =10v -1.2-a v o(fbdriver)(max) maximum output voltage on pin fbdriver -1112v latch input (pin latch) v prot(latch) protection voltage on pin latch 1.23 1.25 1.27 v i o(latch) output current on pin latch v prot(latch) TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 27 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic 12. package outline fig 18. package outline sot109-1 (so16) x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot109-1 99-12-27 03-02-19 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale s o16: plastic small outline package; 16 leads; body width 3.9 mm sot109 -1 TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 28 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic 13. revision history table 6. revision history document id release date data sheet status change notice supersedes TEA1753T v.2 20110408 product data sheet - TEA1753T v.1 TEA1753T v.1 20110304 objective data sheet - - TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 29 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic 14. legal information 14.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 14.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 14.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification. TEA1753T all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 8 april 2011 30 of 31 nxp semiconductors TEA1753T greenchip iii smps control ic non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 14.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. greenchip ? is a trademark of nxp b.v. 15. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors TEA1753T greenchip iii smps control ic ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 8 april 2011 document identifier: TEA1753T please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 16. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 distinctive features . . . . . . . . . . . . . . . . . . . . . . 2 2.2 green features . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 pfc green features . . . . . . . . . . . . . . . . . . . . . 2 2.4 flyback green features . . . . . . . . . . . . . . . . . . . 2 2.5 protection features . . . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 6 7.1 general control . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.1.1 start-up and undervoltage lockout (uvlo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.1.2 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.1.3 supply management. . . . . . . . . . . . . . . . . . . . . 9 7.1.4 latch input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.1.5 fast latch reset . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.1.6 overtemperat ure protection . . . . . . . . . . . . . . . 9 7.2 power factor correction circuit . . . . . . . . . . . . . 9 7.2.1 t on control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.2.2 valley switchin g and demagnetization (pfcaux pin) . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.2.3 frequency limitation . . . . . . . . . . . . . . . . . . . . 10 7.2.4 mains voltage compensation (vinsense pin) . . . . . . . . . . . . . . . . . . . . . . . 10 7.2.5 soft start-up (pin pfcsense) . . . . . . . . . . . . 10 7.2.6 low power mode . . . . . . . . . . . . . . . . . . . . . . 11 7.2.7 pfc off delay (pin pfctimer) . . . . . . . . . . . 11 7.2.8 dual boost pfc . . . . . . . . . . . . . . . . . . . . . . . 12 7.2.9 overcurrent protection (pfcsense pin) . . . . 12 7.2.10 mains undervoltage lockout/brownout protection (vinsense pin) . . . . . . . . . . . . . . 12 7.2.11 overvoltage protection (vosense pin) . . . . . 13 7.2.12 pfc open-loop protection (vosense pin) . . 13 7.2.13 driver (pfcdriver pin) . . . . . . . . . . . . . . . . 13 7.3 flyback controller . . . . . . . . . . . . . . . . . . . . . . 13 7.3.1 multimode operation . . . . . . . . . . . . . . . . . . . . 13 7.3.2 valley switching (hv pin) . . . . . . . . . . . . . . . . 14 7.3.3 current mode control (fbsense pin) . . . . . . 15 7.3.4 demagnetization (fbaux pin) . . . . . . . . . . . . 16 7.3.5 flyback control/time-out (fbctrl pin) . . . . . 16 7.3.6 soft start-up (fbsense pin) . . . . . . . . . . . . . 17 7.3.7 maximum on-time . . . . . . . . . . . . . . . . . . . . . . 18 7.3.8 overvoltage protection (fbaux pin) . . . . . . . 18 7.3.9 overcurrent protection (fbsense pin) . . . . . 19 7.3.10 overpower protection. . . . . . . . . . . . . . . . . . . 19 7.3.11 driver (fbdriver pin) . . . . . . . . . . . . . . . . . 19 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 20 9 thermal characteristics . . . . . . . . . . . . . . . . . 21 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . 21 11 application information . . . . . . . . . . . . . . . . . 26 12 package outline. . . . . . . . . . . . . . . . . . . . . . . . 27 13 revision history . . . . . . . . . . . . . . . . . . . . . . . 28 14 legal information . . . . . . . . . . . . . . . . . . . . . . 29 14.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 29 14.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 14.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 29 14.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 30 15 contact information . . . . . . . . . . . . . . . . . . . . 30 16 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 |
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