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king billion electronics co., ltd E | ? he8p160e he80000 series 1 preliminary v1.3e a. he8p160 introduction he8p160 is a member of 8-bit microcontroller otp series product developed by king billion electronics ltd. this ic uses otp (one time programming) rom, which can be written by the otp writer provided by king billion. it can provide user with fast verification, pilot-run product, and more versatile application requests. he8p160 is a super-set of seven ics, he82005 he83000 he83005 he83115 he83116 he89a21 he89r21) and internal build in 8 channel 12-bit adc converter. if user wants to emulate any one of the seven ics, the otp ez-writer tool will automatically set the hardware resource, such as rom ram size and it is very convenient to use . this ic has build-in lcd driver which have many configuration and can use mask option to select the configuration, such as 128 pixel lcd driver + 16 bit i/o port ? 64 pixel lcd driver + 32bit i/o port . build-in voltage regulator let lcd display st able when external battery voltage drop. the built-in op operation amplifie r can be used with (light voice temperature humility) sensor and used as battery low detection. the 7-bit current-type d/a converter and pwm device provide complete speech output mechanism. the instruction set of he8p160 is quite easy to learn and simple to use. only about thirty instructions with four-type addressing mode are provided. most of instruc tions take 3 oscillator clocks (machine cycles). the processing power is enough for most of battery operation system. b. he8p160 features ? operation voltage: 2.4v ? 5.5v ? system clock: dc ~ 8mhz @ 5.0v dc ~ 4mhz @ 2.4v ? internal rom: 64k bytes (64k program rom) ? internal ram: 512 bytes. ? dual clock system: normal (fast) clock: 32.768k ~ 8mhz slow clock: 32.768 khz ? operation mode: dual fast slow idle sleep mode. ? build-in wdt (watch dog timer) to prevent deadlock or abnormal condition. ? 16~32 bit bi-directional i/o port. mask option can select push-pull or open drain output mode for each i/o pin. the each of i/o prtd[3:0] has 5 ma sink capability. ? build-in op amplifier . this op operating range between 0 ~ (vdd-1) , that is different from previous op comparator operating range between 0.8~vdd, the us er should notice this. please set the operation range on 0.8 ~ (vdd-1) if users want to design a circuit working both on 8p160 and target ic. ? build-in 125 khz, 8-channel 12-bit adc block. ? build-in voltage regulator which provide lcd stable operating voltage. ? 4 com*32 seg lcd driver which have a, b type . voltage regulator circuit pleases refer to application circuit. the lcd highest voltage lv3 must less than 9.0 v. ? contain a 7-bit current-type d/a converter.
king billion electronics co., ltd E | ? he8p160e he80000 series 2 preliminary v1.3e ? provide pwm output device.(users can select with or without rate selection, connect with ?vdd+pwm? or ?pwmp+pwmn?) ? two external interrupts and three internal timer interrupts. ? two 16-bit timers and one time base timer. ? instruction set: 32 instructions , 4 addressing mode. 9-bit data pointer for ram and 16-bit table pointer for rom. c. mask option comparison table when user uses kb otp writer(include application so ftware& hardware) to write data to otp, user can select specific ic from software application, in the mean time, the kb ot p writer will set all the configuration automatically. the foll owing table describes the configura tion relative setting, if users want to use he8p160 full function setting, please reference following setting. name description 82005 83000 83005 83115 83116 89a21 89r21 0: tp not changed at ldv mo_ldvinc 1: tp++ at ldv user 1 1 1 1 1 1 0: internal fast osc mo_fosce 1: external fast osc, use it now 1 user user user user user user 0: r/c osc. for fast clock mo_fxtal 1: x'tal osc. for fast clock user user user user user user user 000: rfrc_i ~= 500k 001: rfrc_i ~= 1m 010: rfrc_i ~= 1.5m 011: rfrc_i ~= 2m 100: rfrc_i ~= 2.5m 101: rfrc_i ~= 3m 110: rfrc_i ~= 3.5m mo_frci_s[2:0] 111: rfrc_i ~= 4m 000: not exist user user user user user user 0: r/c osc. for 32k clock mo_sxtal 1: x'tal osc. for 32k clock 0: not exist user user user user user user 00: slow clock only 01: illegal 10: dual clock mo_fck/sckn 11: fast clock only 11 user user user user user user 0: wdt disable mo_wdte 1: wdt enable 0 user user user user user user 0: open-drain output mo_cpp[7:4] 1: push-pull output 1 1 user 1 user user user 0: open-drain output mo_cpp[3:0] 1: push-pull output 1 user user user user user user 0: open-drain output mo_dpp[7:0] 1: push-pull output user user user user user user user 0: open-drain output mo_14pp[7:0] 1: push-pull output 1 1 1 user 1 user user 0: open-drain output mo_15pp[7:0] 1: push-pull output 1 1 1 1 1 user user 0: io pin mo_lio14[7:0] 1: lcd pin 0 0 0 user 1 user user
king billion electronics co., ltd E | ? he8p160e he80000 series 3 preliminary v1.3e name description 82005 83000 83005 83115 83116 89a21 89r21 0: io pin mo_lio15[7:0] 1: lcd pin 0 0 0 0 1 user user 0: dtmf clock source 3.58m hz mo_dtmfsck 1: dtmf clock source 32768 hz 0 0 0 0 0 user user 0: lcd regulator disable mo_lvrg 1: lcd regulator enable 0 0 0 0 0 0 user 0: i/o pin 0 0 0 0 0 0 mo_prtc_adc[7:0] 1: adc input 0 0: 2ma iol mo_prtd_hic[3:0] 1: 5ma iol 0 0 0 0 0 0 0 0: otp read protect mo_protectn 1: otp not protect user user user user user user user 00: rom 4k byte 01: rom 8k byte 10: rom 16k byte mo_rom[1:0] 11: rom 64k byte 11 00 11 11 11 10 10 00: ram 64 byte 01: ram 128 byte 10: ram 256 byte mo_ram[1:0] 11: ram 512 byte 01 00 01 10 10 11 11 0: tc2 not exist mo_tc2 1: tc2 exist 0 1 1 1 1 1 1 0: tb not exist mo_tb 1: tb exist 0 0 0 0 0 1 1 00: prt0c not exist 01: only prt0c[3:0] exist 10: only prt0c[7:4] exist mo_prt0c[1:0] 11: prt0c exist 00 01 11 01 11 11 11 0: prt14 not exist mo_prt14 1: prt14 exist 0 0 0 1 0 1 1 0: prt15 not exist mo_prt15 1: prt15 exist 0 0 0 0 0 1 1 0: prt14[7:0]=seg[19:12] mo_prt14_ss 1: prt14[7:0]=seg[23:16] 0 0 0 0 1 1 1 0: lcd not exist mo_lcd 1: lcd exist 0 0 0 1 1 1 1 00: pwm not exist 01: pwm logic 10: pwm1 logic mo_pwm[1:0] 11: pwm not exist 10 00 10 10 01 00 00 0: pwmp/pwmn output mo_pmd 1: pwm/gnd_pwm output 1 0 0 0 0 0 0 0: dac not exist mo_vo 1: dac exist 1 0 1 1 1 0 0 0: op amp. not exist mo_opamp 1: op amp. exist 0 1 1 1 1 0 0 0: dtmf not exist mo_dtmf 1: dtmf exist 0 0 0 0 0 1 1
king billion electronics co., ltd E | ? he8p160e he80000 series 4 preliminary v1.3e d. pin description pin# pin name i/o function description 52, 51 fxi, fxo b/ o external fast clock pin. connecting to crystal or rc to generate 32.768 khz ~ 8mhz frequency. 55, 54 sxi, sxo i/ o external slow clock pin. connecting with 32768 hz crystal or resistor as slow clock and providing clock source for lcd display, timer1, time-base and other internal blocks. mask option setting mo_fck/sckn= 00 slow clock only 01 illegal 10 dual clock 11 fast clock only mo_fosce = 0 internal fast osc. = 1 external fast osc. mo_fxtal = 0 rc osc. for fast clock = 1 x?tal osc. for fast clock mo_sxtal = 0 rc for 32768 hz clock = 1 x?tal for 32768 hz clock use op1 and op2 to switch among different operation mode (normal, slow, idel and sleep). in dual clock mode, the main system clock is still the fast clock. the 32768 hz clock is for lcd and timer 1 only. 50 rstp_n i system reset. level trigger, active low. except for using this pin, using mask option (mo_pore=1) could enable ic build-in power-on reset circuit. besides, mo_wdte can set watch dog timer mo_wdte=0 disable watch dog timer =1 enable watch dog timer 53 tstp_p i test pin, active high. please bond this pin and add a test point on pcb for debugging. but for improving esd, please connect this point with zero ohm resistor to gnd. 82, 83 1..6 prtc[7:0] /adc[7:0]; b port c bi-directional i/o pin total 8 pin or adc[7:0] can be used as 8-channel adc data input pin. mask options mo_cpp[7..0]=1 ~ push-pull. = 0 ~ open-drain. when use them as input (no tri-state structure), it must output ?1? before reading. 70..77 prtd[7:0] b 8-pin bi-directional i/o port. prtd[7..2] as wake-up pin. prtd[7..6] as external interrupt pin. mask options mo_dpp[7..0]=1 ~ push-pull. = 0 ~ open-drain. when use them as input (no tri-state structure), it must output ?1? before reading. 16..23 prt14[7:0]/ seg[23:16] b/ o 8-pin bi-directional i/o port that is shared with lcd segment pin. mask options mo_lio14[7..0]=1 ~ lcd pin. = 0 ~ i/o pin. mo_14pp[7..0]=1 ~ push-pull. =0 ~ open-drain. when use them as input (no tri-state structure), it must output ?1? before reading. 8..15 prt15[7:0]/ seg[31:24] b/ o 8-pin bi-directional i/o port that is shared with lcd segment pin. mask options mo_lio15[7..0]=1 ~ lcd pin. =0 ~ i/o pin. mo_15pp[7..0]=1 ~ push-pull. =0 ~ open-drain. output must be ?1? before reading whenever uses them as input (no tri-state structure). 40..43 com[3:0] o lcd com output please reference lcd and ram map. 24..31 seg[15:8]/ d[7:0] o lcd segment output/ otp writing pin 32 seg[7]/sdo o segment/ otp writing pin 33 seg[6]/sdi o segment/ otp writing pin these are lcd segment and otp writer shared pin, user must refer standard interface to arrange these pins on pcb board, let kb writer can write data to otp. these pins are lcd segment pin on normal mode.
king billion electronics co., ltd E | ? he8p160e he80000 series 5 preliminary v1.3e pin# pin name i/o function description 34 seg[5]/sclk o segment/ otp writing pin 35 seg[4]/d_cn o segment/ otp writing pin 36 seg[3]/r_wn o segment/ otp writing pin 37 seg[2]/p_sn o segment/ otp writing pin 38, 39 seg[1:0] o lcd segment output 45 lc2 b charge pump switch 1 44 lc1 b charge pump switch 2 48 l v3 b charge pump v3 47 l v2 b charge pump v2 46 l v1 b charge pump v1 refer to application circuit. 63 pwm o the pwm output can drive speaker or buzzer directly. set bit2 (pwm=1) of voc register to turn on pwm. 65 pwmp o the pwm positive output can drive speaker or buzzer directly. set bit2 (pwm=1) of voc register to turn on pwm. 64 pwmn o the pwm negative output can drive speaker or buzzer directly. s set bit2 (pwm=1) of voc register to turn on pwm. 69 vo o d/a voice output. set bit1 (da=1) of voc register to turn on vo. 67 opin i negative input of op comparator 68 opip i positive input of op comparator 66 opo o opamp output pin set the bit0 (op=1) of voc register to turn on op comparator. the operating range be tween 0 ~ (vdd-1). 59 dtmfo o dtmf output through port12 can turn on/off dtmf & write data . use mask option mo_dtmfsck set clock source mo_dtmfsck=0, clock source=3.579545 mhz =1 clock source=32768 hz 58 mute o mute output for dialer mute can be turned on/off by port12. 60 sdo o sdo for dialer application sdo & write data can be turned on/off by port12. 61 keytone o 1024 hz 50% duty square wave keytone can be turned on/off by port12. 57 loader i define loader mode used for program download 78 vrefp i adc positive voltage reference tie this pin to reference input: 1v to vdda 79 vrefn i adc negative voltage reference tie this pin to vssa 56 vdd p digital positive power 49 gnd p digital power ground 81 vdda p analog positive power 80 vssa p analog power ground 7 vpp p otp high voltage power 62 gnd_pwm p dedicated gnd for pwm adding 0.1 f capacitor as by- p ass capacitor on each set is necessary. vdda and vssa must always be tied to high and low.
king billion electronics co., ltd E | ? he8p160e he80000 series 6 preliminary v1.3e e. lcd ram map page 0: seg1 seg0 seg17 seg16 f0h com[3:0] com[3:0] f8h com[3:0] com[3:0] seg3 seg2 seg19 seg18 f1h com[3:0] com[3:0] f9h com[3:0] com[3:0] seg5 seg4 seg21 seg20 f2h com[3:0] com[3:0] fah com[3:0] com[3:0] seg7 seg6 seg23 seg22 f3h com[3:0] com[3:0] fbh com[3:0] com[3:0] seg9 seg8 seg25 seg24 f4h com[3:0] com[3:0] fch com[3:0] com[3:0] seg11 seg10 seg27 seg26 f5h com[3:0] com[3:0] fdh com[3:0] com[3:0] seg13 seg12 seg29 seg28 f6h com[3:0] com[3:0] feh com[3:0] com[3:0] seg15 seg14 seg31 seg30 f7h com[3:0] com[3:0] ffh com[3:0] com[3:0] f. build-in 8-channel adc he8p160 built in 8-channel 12-bit adc with 125 khz sampling rate ar e pin-shared with port c, it contain sample and hold circuit. user can set mo_prtc_adc [3:0] to select what kind of input. user can set the adc control register by writing setting to prtc or obtain the adc converted data by reading the prtc, refer to following table for more details; the read data is high byte or low nibble, depends on adc control register setting. the adc data register has only one set, so if there is more than one channel application, it should be sa ved previous adc sample data, th en switch to another channel to sample adc data again. when adc[7]=0, the whole adc block will turn on. this chip provides two kind of method to start adc converting which are software interrupt and hardware interrupt (timer). when adc[5]=1, the start of covert adc sample is tr iggered by rising edge of adc[6]; the adc hardware will begin to sample, the translation time must large than 150 s and the user should notice this point, otherwise it will fetch the unstable data. the disadvantage of so ftware trigger is that adc may produce jitter effect in sample data, such as voice sample, but the advantage of software trigger is that it can process 1 to 8 channel sample data; it is suitab le for the application less sensitive on phase jitter issue. the other way to trigger adc to convert data is by timer 1 interrupt; when interrupt happen, the sample data will be sampled and store in adc data register, user can read back the sampled data. the advantage of using timer 1 inte rrupt to trigger adc is to avoid the phase jitter and calculation the delay sample time. the adc[4] bit is used to select the high byte or low nibble of sampled data and adc[3] is the clock source selection used to se lect the clock source of adc whic h comes from fast clock divided
king billion electronics co., ltd E | ? he8p160e he80000 series 7 preliminary v1.3e by 4 or divided by 2. if fast clock is greater than 8 mhz, then set adc[3]=0, otherwise set adc[3]=1. the adc[2:0] is used to select one of the 7 adc input si gnal channel, there is only one channel selected at the same time. address name function r/w width reset 0ch: (prtc) adc adc cont rol/data register r/w 8 zzzzzzzz adc control register (write bit field) 0: adc enable adc[7] enb 1: adc disable; power-down adc[6] start 0 -> 1: s/w start a adc conversion 0: select t2 interrupt as "start of conversion" adc[5] seltm 1: select adc[6]'s rising edge as "start of conversion" 0: adc read value = { data[3:0], 0, 0, 0, 0 }, high nibble= data[3:0]; low nibble= ?0000?. adc[4] datasel 1: adc read value = data[11:4] 0: adc clock= fast clock /4, (clock > 8mhz ) adc[3] clks 1: adc clock = fast clock /2, (clock < 8mhz ) adc[2:0] chnl 7~0: select adc input channel 7~0 adc data register (read bit field) adc[7:0] data[11:4], or { data[3:0], 0, 0 ,0, 0 } following program is a adc sample data example, please reference. timer2:: : ; adc section ; use adc channel: pc7 lda #00111111b sta prt17 ; write adc control register lda prt17 ; get result[11..4] from result register sta mema ; store in ?memory location a? lda #0010 1111b sta prt17 ; write adc control register lda prt17 ; get result[3..0] from result register sta memb ; store in ?memory location b? ; end adc sectio : reti
king billion electronics co., ltd E | ? he8p160e he80000 series 8 preliminary v1.3e
king billion electronics co., ltd E | ? he8p160e he80000 series 9 preliminary v1.3e f. qfp 52 packages
king billion electronics co., ltd E | ? he8p160e he80000 series 10 preliminary v1.3e he8p160-qfp52 31 26 27 30 29 28 25 24 48 47 46 45 44 43 42 41 6 5 4 3 21 20 19 18 17 2 1 52 51 39 38 37 34 33 36 35 40 32 49 50 7 16 8 9 10 11 12 13 14 15 22 23 vdd fxo fxi sxi sxo tstp_p rstp_n gnd prtd[0] prtd[1] prtd[2] prtd[3] prtd[4] prtd[5] prtd[6] prtd[7] prtc[0] prtc[1] prtc[2] prtc[3] p_sn r_wn d_cn sclk sdi prtc[4] prtc[5] prtc[6] prtc[7] opip opin opo pwm gnd_pwm pwmp pwmn vo loader vssa vdda vpp sdo nc nc nc nc nc nc nc nc nc nc
king billion electronics co., ltd E | ? he8p160e he80000 series 11 preliminary v1.3e g. qfp 100 packages
king billion electronics co., ltd E | ? he8p160e he80000 series 12 preliminary v1.3e he8p160-qfp100 63 58 59 62 61 46 47 48 49 50 60 65 67 66 57 51 68 92 91 90 89 88 87 86 85 8 7 6 5 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 17 16 15 14 4 3 98 97 13 12 11 10 25 24 23 22 21 20 19 18 75 74 73 70 69 72 71 84 64 93 94 95 96 9 2 1 52 53 54 55 56 76 77 78 79 80 81 82 83 99 100 vdd fxo fxi sxi sxo lc1 lc2 lv1 lv2 lv3 tstp_p mu te sdo dtmfo rstp_n gnd key tone prtd[0] prtd[1] prtd[2] prtd[3] prtd[4] prtd[5] prtd[6] prtd[7] prtc[0]/adc[0] prtc[1]/adc[1] prtc[2]/adc[2] prtc[3]/adc[3] com[0] com[1] com[2] com[3] seg[0] seg[1] p_sn/seg[2] r_wn/seg[3] d_cn/seg[4] sclk/seg[5] sdi/seg[6] sdo/seg[7] d[0]/seg[8] d[1]/seg[9] d[2]/seg[10] d[3]/seg[11] d[4]/seg[12] d[5]/seg[13] d[6]/seg[14] d[7]/seg[15] prt15[0]/seg[24] prt15[1]/seg[25] prt15[2]/seg[26] prt15[3]/seg[27] prtc[4]/adc[4] prtc[5]/adc[5] prtc[6]/adc[6] prtc[7]/adc[7] prt15[4]/seg[28] prt15[5]/seg[29] prt15[6]/seg[30] prt15[7]/seg[31] prt14[0]/seg[16] prt14[1]/seg[17] prt14[2]/seg[18] prt14[3]/seg[19] prt14[4]/seg[20] prt14[5]/seg[21] prt14[6]/seg[22] prt14[7]/seg[23] opip opin opo pwm gnd_pwm pwmp pwmn vo loader vrefp vrefn vssa vdda vpp nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc
king billion electronics co., ltd E | ? he8p160e he80000 series 13 preliminary v1.3e h. 32-pins cob package
king billion electronics co., ltd E | ? he8p160e he80000 series 14 preliminary v1.3e i. dc/ac characteristics absolute maximum rating item symbol rating condition supply voltage v dd -0.5v ~ 8v input voltage v in -0.5v ~ v dd +0.5v output voltage v o -0.5v ~ v dd +0.5v operating temperature t op 0 ~ 70 storage temperature t st -50 ~ 100 recommended operating conditions item symbol rating condition supply voltage v dd 2.4v ~ 5.5v v ih 0.9 v dd ~ v dd input voltage v il 0.0v ~ 0.1v dd 8mhz v dd =5.0v operating frequency fmax. 4mhz v dd =2.4v operating temperature t op 0 0 c ~ 70 0 c storage temperature t st -50 0 c ~ 100 0 c
king billion electronics co., ltd E | ? he8p160e he80000 series 15 preliminary v1.3e testing condition: temp. =25 , v dd =3v10%, gnd=0v parameter condition min typ max unit i fast normal mode current system 4m ext. crystal 1.90 2.0 ma i slow slow mode current system 32.768khz x?tal lcd disable 50 60 a i idle idle mode current system 32.768khz x?tal lcd disable 12 15 a i lcd extra current if lcd on system lcd enable a i sleep sleep mode current system 2.0 3.0 a with 32 ? loading 10 14 ma with 64 ? loading 6 8 ma i pwm pwm output current pwmp, pwmn *2 with 100 ? loading 4 5 ma i ovo dac output current vo v dd =3v;vo=0~2v,data=7f 2.5 3 ma v ih input high voltage i/o pins 0.8 v dd v v il input low voltage i/o pins 0.2 v dd v v hys input hysteresis width i/o, rstp_n threshold=2/3v dd (input from low to high) threshold=1/3v dd (input from high to low) 1/3 v dd v i oh output drive current i/o pull-high *1 v ol =2.0v 50 a i ol_1 output sink current i/o pull-low *1 v ol =0.4v 1.0 ma i ol_2 output sink current prtd[3:0] v ol =0.4v 5.0 ma i il_1 input low current rstp_n v il =gnd, pull high internally 20 a i il_2 input low current i/o v il =gnd, if pull high internally by user 100 a note: *1: drive current specification ? for push-pull i/o port only sink current specification ? for both push-pull and open-drain i/o port. *2: this spec. bases on one driver only. there are five build-in drivers actually, so user can multiply the number of driver to obtain the ne cessary driver current to drive the speak. ( i pwm * n; n=0, 1, 2, 3, 4, 5)
king billion electronics co., ltd E | ? he8p160e he80000 series 16 preliminary v1.3e j. application circuit about 82005 83000 83005 83115 83116 89a21 89r21 and general he80000 series application, please refer individual data sheet. the following circuit is focus on adc and writer application. vref vdd vdd vdd vdd vdd vdd vdd vdd vdd sxo sxi fxi sxo sxo fxo fxi sxi fxi fxo sxi sxo lc1 lc2 loader vpp sclk sdo r_wn p_sn sdi gnd d_cn loader vpp lv1 lv1 lv2 lv1 lv2 lv2 lv3 lv3 vdd lv3 lv2 lv3 lv1 lv1 lv2 lv3 0.1u 0.1u 0 con1 otp in-system programming 1 2 3 4 5 6 7 8 9 10 0.1u 0.1u 10k 0.1u 0.1u 0.1u d1 1n4148 0.1u 32 ohm speaker 0.1u 0.1u 0.1u 32 ohm speaker 8 ohm speaker npn (8050) 0.1u b1 bead 0.1u 0.1u r: please ref . an016 c: please ref . an016 20p 33p 33p 20p r > 8.2 kohm 32.768k 6mhz sw1 reset battery 1 3v 100uf 100k he8p160 vdd fxo fxi sxi sxo lc1 lc2 lv1 lv2 tstp_p com[3:0] seg[15:0] prtd[7:0] prtc[7:0] rstp_n gnd dtmfo mu te sdo key tone lv3< 9 volt prt14[7:0]/seg[23:16] prt15[7:0]/seg[31:24] padvpp vdda vssa vrefn vrefp opip opin opo loader pwmp pwmn pwm gndpwm vo 0.1u 0.1u 0.1u 0.1u external rc slow clock: no external parts is necessary if user adopt internal fas t rc clock external crystal fast clock: extern al rc fas t clo ck: external crystal slow clock: four charge pump is selected lcd max. voltage=lv3=3*vdd four charge pump is selected lcd max. voltage=lv3=3/2*vdd four charge pump is selected lcd max. voltage=lv3=vdd maskoption ==> regulator disable maskoption ==> regulator disable maskoption ==> regulator disable four charge pump is selected lcd max. voltage=lv3=3*lv1 maskoption ==> regulator enable lv1 ~ 1v lcd panel vref is used as adc controler referenced votage. user can connect vref to vdd or another stable voltage. please refer an022 for speech output circuit loader and vpp pins are dedicated used to program otp. the seg[15:2] pins are switched for otp programming when he8p160 is in programming mode passive bias & filiter circuit
king billion electronics co., ltd E | ? he8p160e he80000 series 17 preliminary v1.3e writer mode connection pins definition: pin number he8p160 pin name writer mode pin name 24 seg[15] data[7] 25 seg[14] data[6] 26 seg[13] data[5] 27 seg[12] data[4] 28 seg[11] data[3] 29 seg[10] data[2] 30 seg[9] data[1] 31 seg[8] data[0] 32 seg[7] sdo 33 seg[6] sdi 34 seg[5] sclk 35 seg[4] d_cn 36 seg[3] r_wn 37 seg[2] p_sn k. updated record version date section original content new content v1.1 feb 7, 2002 f adc software conversion is not in pilot sample. only t2 conversion in pilot version. b op comparator op operating amplifier ?operating range? v1.11 mar 7,2002 d vdda tie high, vssa tie low v1.12 mar 25, 2002 f. example 00110 111b 0010 1111b v1.13 oct. 03, 2002 j add qfp100 package spec. v1.2 dec. 10, 2002 i add qfp52 package spec. v1.2 dec. 10, 2002 i add qfp52 package spec. v1.3 jan. 03, 2003 l power consumption error (slow mode current)

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