f s g ear sy s c r 3 < s c o se l 1 :0 > sc o u t f g ear sy s c r1 < s y s c k > t0 s y sc r 1 < s g e ar > a d c c o nver si on cl oc k cl o c k t i m e r kw up hs i o 1/2 sy s c r0 f s gear fsy s /2 fs to w a r m - u p t i m e r fig. 5-3 cl ock and s t a ndb y related blo ck diag ram tmp19a43 (rev2.0) 5-3 clock/s t andby control
tmp19a43 5.2 cg registers 5.2.1 sy stem co ntrol registers 7 6 5 4 3 2 1 0 bit s y mbol x e n x t en rx en rx ten w u ef prck1 prck0 read/w r i t e r/w r / w r / w r / w r r/w r/w r/w af ter re set 1 0 functio n h i g h - s p e e d oscillator 0: s t op 1: oscilla- tion low -speed oscillator 0: s t op 1: oscilla- tion high-spee d oscillator af ter th e st op mode is r e lea s ed 0: s t op 1: oscilla- tion low -speed oscillator af ter th e st op mode is r e lea s ed 0: s t op 1: oscilla- tion this c a n be read a s "0 ." control of w a rm-up t i me r (w up ) for oscilla tor 0 w r ite: don't care 1 w r ite: w u p st a r t 0 read : wu p fini shed 1 read : wu p operati ng selec t pres cal e r clo ck 00: f periph / 16 01: f periph / 8 10: f periph / 4 1 1 : f p eriph / 2 7 6 5 4 3 2 1 0 bit sy mbol sy sc kflg sy s c k f p s e l s g e a r g e a r 2 g e a r 1 g e a r 0 read/w r i t e r r r/w r / w r/w r / w r/w r/w af ter re set 0 0 0 1 1 1 functio n t h i s can be read a s "0 ." sy stem c l oc k st atus flag 0: high speed (fc) 1: l o w speed ( f s) select sy stem clo ck 0: high speed (fgear) 1: l o w speed ( f s) select f periph 0: fgear 1: fc select gear of low - speed clo ck 0: fs / 1 1: fs / 2 select gear of high- speed clock (fc) 000: fc 100: fc/2 001: re serv ed 101: re serv ed 010: fc3 / 4 1 10: fc/4 01 1: re serv ed 1 1 1 : fc/8 7 6 5 4 3 2 1 0 bit sy mbol dr vosch w u pt1 w u pt0 stby 1 stby 0 dr ve read/w r i t e r/w r / w r / w r / w r/w r / w r r/w af ter re s e t 0 0 1 0 1 1 0 functio n h i g h - s p e e d oscillator curren t con t rol 0: high cap abili ty 1: l o w cap abili ty this c a n be read a s "0 ." select oscilla tor w a rm-up tim e 00: no w u p 01: 2 /inp u t fr eque ncy 10: 2 14 /input freque ncy 11 : 2 16 /inp u t fr eque ncy select st a ndby mode 00: re serv ed 01: st op 10: sleep 1 1 : id le this c a n be read a s "0 ." 1: driv e th e pin ev en in the st op mode . 7 6 5 4 3 2 1 0 bit sy mbol scosel1 s cosel0 a lesel read/w r i t e r r/w r / w r / w r af ter re set 0 1 1 0 sy scr0 (0x f f ff_ee00 ) (0x f f ff_ee03 ) sy scr1 (0x f f ff_ee01 ) (0x f f ff_ee02 ) sy scr2 (0x f f ff_ee02 ) (0x f f ff_ee01 ) sy scr3 (0x f f ff_ee03 ) (0x f f ff_ee00 ) functio n t h i s can be read a s "0 ." select scout ou tp ut 00: fsgear 01: fsy s /2 10: fsy s 11 : t0 set ale outpu t wi dt h 0: fs y s 1 1: fs y s 2 this can be read a s "0 ." l i tt le big l i tt le big l i tt le big l i tt le big ? don't s w itch th e sysck an d th e ge a r <2 :0> si mul t a ne ous l y . ? if the s y s t e m e n ters the st op mo de w i th syscr2 set at 1 (l o w cap abilit y ) , the se ttin g w ill chan ge to 0 (hig h ca p a bili t y ) a f ter the st op mo de is release d. ? sysck can be s w itched w h en both o f xen a n d xten are s e t to "1." ? be sure to set t h e rxen and t h e rxten to 1 (o scillati on) f o r th e oscillat or sele cted at t h e sysck. if a w r ong setti ng is mad e , the oscilla tor s elected b y the s ysck w ill oscillate. ? the cl ock t h at h as bee n selec te d w i th sysck o scillates w i thou t fail a f ter maki n g clear t h e st op mode. tmp19a43 (rev2.0) 5-4 clock/s t andby control
tmp19a43 tmp19a43 (rev2.0) 5-5 clock/standby control 5.3 system clock controller by resetting the system clock controller, the controller status is initialized to = "1," = "0" and = "111," and the system clock fsys changes to fc/8. (fc = fosc (original oscillation frequency) 4, because the original oscillation is quadrupled by pll.) for exam ple, when a 10-mhz oscillator is connected to the x1 or x2 pin, fsys becomes 5 mhz (=10 4 1/8) after the reset. similarly, when the oscillator is not connected and an external oscillator is used to input a clock instead, fsys becomes the frequency obtained from the calculation "input frequency 4 1/8." 5.3.1 oscillation stabilization time (switching between the normal and slow modes) the warm-up timer is provided to confirm the oscillation stability of the oscillator when it is connected to the oscillator connection pin. the warm-up time can be sel ected by setting the syscr2 depending on the characteristics of the oscillator. th e syscr0 is used to confirm the start and completion of warm-up through software (instruction). after the completion of warm-up is confirmed, switch the system clock (syscr1). when clock switching occurs, the current system clock can be checked by monitoring the syscr1. table 5-1 shows the warm-up time when switching occurs. (note 1) the time for warm-up is required even when an external clock (oscillator, etc.) is used and providing stable oscillation because the internal pll is used even in this case. (note 2) the warm-up timer operates accordi ng to the oscillation clock, and it can contain errors if there is any fluctuation in the oscillation frequency. therefore, the warm-up time should be taken as approximate time. table 5-1 warm-up time warm-up time options syscr2 high-speed clock (fosc) low-speed clock (fs) 01 (2 8 /oscillation frequency) 25.6 ( s) 7.8 (ms) 10 (2 14 /oscillation frequency) 1.638 (ms) 500 (ms) 11 (2 16 / oscillation frequency) 6.554 (ms) 2000 (ms) these values are calculated under the following conditions: fosc = 10 mhz, fs = 32.768 khz
tmp19a43 t r an sition from th e normal m o d e t o the slow m o d e syscr 2 < w upt1: 0 >="xx": select the wa rm -up tim e syscr 0 ="1 " : en ab le th e l o w-sp eed o s cillatio n (fs) syscr 0 < w uef>="1": s t art the warm -up timer (wup) syscr 0 read : w a i t u n til th e state b e co m e s "0 " (wup is fin i sh ed ) syscr 1 ="1": swi t ch the sy ste m clock t o low speed (fs) syscr 1 read: confirm that the c u rrent state is " 1 " (the curre nt system clock is fs ) syscr 0 ="0": disable the hi gh-speed oscillation (fosc) t r an sition from th e slow m o d e to th e normal m o d e syscr 2 < w upt1: 0 >="xx": select the wa rm -up tim e syscr 0 ="1": enab l e the high-speed oscillation (fosc) syscr 0 < w uef>="1": s t art the warm -up timer (wup) syscr 0 read : w a i t u n til th e state b e co m e s "0 " (wup is fin i sh ed ) syscr 1 ="0": swi t ch the syst e m clock t o high speed (fgea r) syscr 1 read: confirm th at the c u rre nt st ate is "0" (t he current system cloc k is fgea r) syscr 0 ="0 " : disab l e th e l o w-sp eed o s cillatio n (fs) (no t e ) in the slo w mode, the cpu o p era t e s w i th the lo w - s p eed clock, and the i n t c , the clock ti mer , the 2-p h ase pulse input coun te r , the kwup (d y n amic p u ll-up), the io port and the ebi f (external bus interfac e) are oper a ble. s t op other internal peri pheral fun c ti ons before the s y stem enter s the sl ow mode. 5.3.2 sy stem clo c k pin outp ut function th e syste m clo c k , fsys, fsys/2 o r fs, can b e outp u t fro m th e p4 4 / sc out p i n. by settin g the po rt 4 related reg i sters, p4c r < p 44c > t o " 1 " an d p 4 f c t o " 1 ," t h e p 4 4/ sc ou t pi n beco m e s t h e sc o u t out put pi n. the o u t p ut clo c k is selected b y settin g th e syscr3 . t a bl e 5 - 2 s h o w s t h e pi n st at es i n eac h st a n dby m ode w h e n t h e p 44/ sc o u t pi n i s set t o t h e sc out out put . t able 5-2 scout o u tput s t ate in each s t andby mod e sta n dby mode mode sco u t selectio n norm a l s l o w i d l e s l e e p s t o p = "00" output th e fs ge a r clo c k. = "01" output th e fs y s /2 clo c k. = "10" output th e fs y s clock. fixed to "0" or " 1 ." = "11" output th e t0 clock . (no t e ) the phase differ e nc e (ac timing) bet w e e n the s y stem clo ck outpu t by the sco u t and the inte rnal clock is not guaran t e e d. tmp19a43 (rev2.0) 5-6 clock/s t andby control
tmp19a43 5.3.3 reducing the oscillator driving cap ability th is fun c tio n is in tend ed fo r restrictin g o s ci llatio n no ise gen e rated fro m th e o s c illato r an d red u c i n g the po wer d i ssip a tion o f th e o s cillato r wh en it is conn ected to t h e o s ci llato r conn ectio n p i n . settin g th e syscr2 to "1" redu ces t h e d r i v ing cap ab ility o f th e h i gh -sp e ed oscillato r . (low cap ab ility) th is is reset to th e d e fau lt settin g "0 ." wh en th e power is tu rn ed on, oscillat i o n st arts with th e normal d r i v ing cap ab ility (h igh cap a b ility). th is is au to m a ticall y set to t h e h i gh d r iv i n g cap a b ility state ( ="0 " ) wh en ev er th e oscillato r starts o s cillatio n d u e to m o d e tran sitio n . z redu cing t h e driv ing cap a b ility o f th e h i g h -sp eed oscillato r os c illa to r c2 c1 e nabl e o s c i l l a t i on x1 p i n s y s cr2 f os c x 2 pin fig. 5-4 oscill ator driving cap a bility 5.3.4 clock frequenc y divis i on for low-s peed sy s t em clock th e low-sp eed clo c k (fs) can b e d i v i d e d i n to two b y settin g th e system co n t ro l reg i ster syscr1 t o "1 ." th is redu ces t h e po wer d i ssipatio n in th e slow m o d e . set th e clo c k freq u e n c y d i v i si o n during h i gh-sp eed o s cillatio n. tmp19a43 (rev2.0) 5-7 clock/s t andby control
tmp19a43 5.4 prescaler clock con t roller each in ter n al i/o ( t mrb0 -f , tmrc, si o0 -2 an d sbi) has a prescaler for divi ding a cl ock. the cloc k t0 to be in pu t to each prescaler is ob tain ed b y selectin g t h e "f peri ph" cl ock at t h e s y sc r 1 < fps e l > an d t h e syscr 0 an d t h en d i v i d i n g t h e clo c k accord i n g to th e settin g of syscr 0 . after th e co n t ro ller is reset, fp eri p h / 1 6 is selected as t0 . for d e t a ils, p l ease refer to fi g . 5-5 syste m clo c k t r an sition diag ram . 5.5 clock multiplication circuit (pll) th is circu it o u t p u t s t h e fp ll clo c k t h at is qu ad rup l e o f t h e hi g h -sp e ed o s cillato r ou tpu t clock , fo sc. th is lo wers th e o s cillato r inpu t frequ en cy wh ile in creasing t h e in tern al clo c k sp eed . tmp19a43 (rev2.0) 5-8 clock/s t andby control
tmp19a43 5.6 s t andby controller the tx 1 9 a c o re has se veral l o w - di ssi pat i o n m odes. t o sh i f t to th e st op , sleep or idle (halt o r doze) m o d e , set th e rp b it i n th e cpo statu s reg i ster , and then exec ute t h e w a it in st ru ctio n. before sh ifting to th e m o d e , y o u n e ed t o select th e st an d b y m ode at t h e sy st em cont r o l re gi st er (s ysc r 2) . the id le, sl eep a n d st o p m odes ha ve t h e f o l l o wi ng fea t ures: i d le: on ly the cpu is stopped in th is m o d e . th e in tern al i/ o h a s o n e b it of t h e on/off settin g reg i ster for operation in t h e idle m ode i n the re gist er of eac h m odule. t h is enables operati o n settings for the idle m ode. whe n the i n ternal i/o ha s bee n set not to operate i n th e idle m o d e , it stop s o p e ratio n an d ho lds th e state wh en th e system en ters th e idle m o d e . t a b l e 5-3 sh ows a list o f idle settin g reg i sters. t able 5-3 internal i/o settin g regi sters for the idle mode internal i/o idle m o d e settin g reg i ster t m r b 0 - f t b xrun tmrc tccr sio0 -3 s c x m od1 < i2 sx > h s i o 0 - 3 h s c x m o d 1 < i 2 s x > i2c/sio(sbi) s b i b r 1 < i 2 s b i x > a/d converter admo d1< i 2ad> wd t w d mod < i2 w d t > (no t e 1 ) the halt mo de is activ ated b y setting the rp bit in the st atus register to "0," exec uting th e w a it com m and and shif ting to the st andb y mo de. in this mode, the tx1 9 a proce ssor c ore s t op s the proc ess e r opera tion w h ile h o lding the st atus o f th e pipeline. the tx19 a giv e s no res pon se to the b u s contr o l auth orit y reque st from the intern al dm a, so the bus control autho r it y is maint a ined in this mode. (no t e 2 ) the do ze mode is activ a t ed b y settin g the rp bit in the st atus register to "1" and shif ting to th e st an db y mode. in this mode, the t x 19a proc es sor cor e s t o p s the proce sser o p era t ion w h i l e holding the st a t us of the pip e line. the tx19 a c a n respon d to the bus co n t rol autho r ity request giv e n from the out side of the proce ssor c ore. sleep: only t h e inte rnal lo w-speed oscillator , the cl ock tim er , the 2- phase pulse i n put c o unter a n d the dy nam i c p u ll-up circu it (kwup) op erate. st op: all th e in tern al circu its are b r o ugh t to a stop. the stand b y mod e select ion ..status< r p > of cp 0.. is se le cte d by the co mbinatio n. pleas e d o not execut e the w a it instru ction in th e sett ing of " x " in the follow ing tab l e. s tby h alt d oze 1 : 0 r p=0 r p=1 re s e r v ed 00 x x s top 0 1 s top x sl e ep 10 sl e ep x i dle 1 1 h alt d oze tmp19a43 (rev2.0) 5-9 clock/s t andby control
tmp19a43 5.6.1 cg operations in each mode t able 5-4 s t atus of cg in e a ch o p e r atio n mode cloc k s ourc e mode oscillation circu i t pll clo ck su p p l y to p e rip h eral i/o clock supply to cpu o s c i l l a t o r n o r m a l { { { { s l o w { partial supply ( n ote) { idle (halt) { { s e lect abl e idle (doze) { { s e lect abl e s l e e p fs onl y clock timer, 2-p h ase pulse inpu t counter and kwup s t o p { : on or clo c k supply : off or no clo c k supply (no t e) peripheral function s th at c a n w o r k in the slo w mode : intc, ex tern al bu s interface, io port, clock ti mer , 2-pha se pulse input counter and kwup 5.6.2 block operations in each mode t able 5-5 block o p e r ating s t atus in each ope r ation mode b l o c k n o r m a l slow idle (doze) idle (halt) sleep stop tx19a processor core dmac intc extern al bus i/f io port { { { { { { { { { { { { { { adc dac sio hs io i2c tmrb tmrc wdt { { { { { { { { 2-phase pulse input counter { { on/of f s e lecta b le for e ach module { (fs only ) d y namic pull-up (kwup) { { { { { { sta t ic pull-up rtc { { { { { cg { { { { { high-speed oscilla tor (f c) { ? (note) { { low-s p eed oscilla tor (fs) { { { { { { : on : off (note) when the sy stem enters the slow mode, the high-speed oscillator m u st be stopp ed b y setting the s yscr1 . tmp19a43 (rev2.0) 5-10 clock/s t andby control
tmp19a43 5.6.3 releasing the s t andb y s t ate the standby state can be rele ased by a n i n terru p t req u e st wh en th e in terrup t lev e l is h i g h er th an th e i n terru p t m a sk level, or by the reset. the sta n dby release s o urce t h at ca n be use d i s det e rm i n ed by a c o m b i n at i on o f t h e st a n d b y m ode and t h e st at e of t h e i n t e rr upt m a sk re gi st er assi gne d t o t h e st at us regi st er i n t h e sy st e m cont r o l cop r ocess o r (c po ) of t h e t x 19 a p r oce sso r core . details are s h own in t a ble 5-6. z release by an interrupt re ques t o p er ation s of r e leasin g th e st an db y state usin g an in terr up t r e qu est v a r y dep e nd ing on the in terr up t en ab led state. if th e i n t e rru p t lev e l specified b e fo re th e system en ters th e standb y m o d e is equ a l to o r h i gh er th an th e val u e of t h e i n t e rr upt m a sk re gi st er , a n i n t e r r upt ha ndl i n g o p erat i o n i s e x e c ut ed by t h e t r i gge r a f t e r t h e s t and b y is released , and th e pro cessin g is started at th e in stru ctio n n e x t to the stan db y sh ift in stru ction (w ait in stru ction). if th e i n terrup t req u e st lev e l is lo wer th an t h e val u e o f t h e i n t e rr upt m a sk re gi st er , t h e pr oc essi ng is started with th e in stru ctio n n e x t to th e stan db y sh i f t in stru ction (w ait in stru ction) with ou t ex ecu t in g an in terru p t h a n d l in g op eration . (th e i n terrup t req u e st flag is main tain ed at "1 .") for a no n m askab l e in terrup t, an in terru p t h a n d ling is ex ec uted after the standby state is re leased irrespec tively of t h e m a sk re gi st er val u e. z release by the reset any standby st ate can be released by the res e t. no te th at releasin g o f th e st op m o d e req u i res suf f icien t reset ti m e to all o w th e o s cillato r o p e ration t o b eco m e stable. (t a b le 5 - 1 w a rm -up t i m e ). please refer t o "6 . in terrup t" fo r d e tails of i n terru p t s fo r st op , slee p a n d idl e rel ease an d or di na ry i n t e rr u p t s . tmp19a43 (rev2.0) 5-1 1 clock/s t andby control
tmp19a43 s t andb y release sour ce s and s t and b y release opera t ions (interrupt level)>(interrupt mask) t able 5-6 in terru p t acce p t in g state in terru p t en abled ei= "1" in terru p t d i sa b l ed ei= "0" sta ndby mode idle (progra mma ble ) sleep stop idle (programmable) slee p stop intwdt ? ? int0-b (note 1) { { { (note 1) kwup00-31 (note 1) { { { (note 1) intrtc { { inttb2-3 (note 2) { { inttb0-f { intrx0-2,inttx0-2 hintrx00-2,hinttx0-2 { ints0 { standby release source interrupt intad/intadhp/intadm { : starts th e in terru pt hand ling aft e r the standb y m o de is r e l eased . ( t he lsi is initi al ized b y th e r e set . ) { : starts th e pro ces sing at the addr ess next to th e standb y instruction (without execu ting the interrupt handling) after the standb y mode is released. : cannot b e used f o r releasing the standb y mode ? : cannot execu te masking with an interruption mask when a nonmaskable interrupt is selected. (no t e 1 ) the st an db y mode is released af ter th e w a rm-u p time has elap sed. (no t e 2 ) these op era t ions are ap plicable only w h e n the 2-phase puls e input coun te r mode is selected. if an y other modes are selec ted, the operations w ill be the same as thos e for th e inttb0 to intt bf . (no t e 3 ) t o rele ase th e st an db y mode b y using the lev e l mode inte rrup t in th e inte r ruptible st ate, keep the lev e l until the interru pt handling is st arted. chan ging th e le v e l befor e the n w i ll pr ev ent the interru pt proce ssing from st arting properly . (no t e 4 ) t o recov e r from the st an db y mode w h en the cp u has disable d the acce pt ance of interrup t s , set the interr upt le v e l hig h er than the interrupt mask (inte rrup t le v e l > interrup t ma sk). if th e in terru pt lev e l is equal to o r lo w e r than the in terru pt mask (inter rupt le v e l inte rru pt mas k ), th e s y stem ca nnot r ecov e r from the s t andb y mode. tmp19a43 (rev2.0) 5-12 clock/s t andby control
tmp19a43 5.6.4 st op mode in th e st op m o d e , all th e i n tern al circu its, i n clu d i ng t h e in t e rn al o s cillato rs, are bro ugh t to a stop . th e pin states in th e st op m o de v a ry d e p e nd in g o n th e setting o f th e sysc r2 . t a b l e 5.8 sho w s th e p i n states in th e st op m ode. when t h e st op m ode is released, the system clock o u t p u t is started after th e elapse o f warm -u p ti m e at th e warm -u p coun ter to allo w th e in tern al o s cillato rs t o stab ilize. after th e st op m o d e is rel eased , th e syst e m ret u r n s to th e o p e ration m o d e th at was activ e imm e d i ately b e fo re th e st op m o de (norm a l o r slow), and starts th e ope rat i o n. it is necessary to m a ke these settings before the inst ructi o n to e n ter the st op m ode is e x ecute d. specify t h e warm -u p ti m e at th e syscr2. (no t e ) t o shif t from the norm al mode to the st op mod e on the tmp19a43, do not set the syscr2 to "00" or "01" for the w a r m -u p time setting. the internal sy stem recov e r y time can no t be satis fie d w h en the s y stem reco v e rs from the st op mode. t able 5-7 w a rm-up setting s for t r an sitio n s of ope r ati on mod e s tra n s i tion of ope ra tion mo de wa rm-up s e tting normal idle not requir e d normal s leep not requir e d normal sl ow not requir e d normal st op not requir e d idle normal not requir e d s leep normal required s leep sl o w not requir e d sl ow nor mal required (note 1) sl ow s lee p not requir e d sl ow st op not requir e d st op normal required st op sl ow required (note 1) when the high-speed os cill ator is stopped in the slow mode tmp19a43 (rev2.0) 5-13 clock/s t andby control
tmp19a43 5.6.5 recovery from the st op or sleep mode 1 . t r an sition o f op eration m o d e s: norm a l st op norma l n or m a l n or m a l st o p fsy s (hi gh-s peed c l o c k ) m ode cg (hi gh-s peed c l o c k ) sy ste m cl o c k o f f wa r m -up ( w -up) s t art of hi gh-s peed c l o c k osc i l l at i o n s t art of w a rm -up e nd of w a rm -up whe n @fosc= 10 m h z se le c t ion of w a rm-up time syscr2 wa rm-up time (fosc) 01 (2 8 / f o s c ) s e t t i n g d i sabled 10 (2 14 / f o s c ) 1 . 6 3 8 m s 11 (2 16 / f o s c ) 6 . 5 5 4 m s (no t e ) the inte rnal s y stem reco v e r y time cannot b e sa tisfied. do no t se t to " 01." 2 . t r an sition o f op eration m o d e s: norm a l slee p no rm al n or m a l n or m a l sl e e p s y s t em c l oc k o f f fsy s ( h igh - sp ee d c l o c k ) mo d e cg ( h igh - sp ee d c l o c k ) cg (lo w -s peed c l o c k ) wa r m -up ( w -u p) l o w - s p ee d c l o c k ( f s ) con t in u e s o s cilla t i o n s t art of h i g h -s p e e d c l o c k osc i l l at io n s t a r t of w a r m -u p e n d of w a r m -u p whe n @fosc= 10 m h z se le c t ion of w a rm-up time syscr2 wa rm-up time (fosc) 01 (2 8 / f o s c ) s e t t i n g d i sabled 10 (2 14 / f o s c ) 1 . 6 3 8 m s 11 (2 16 / f o s c ) 6 . 5 5 4 m s (no t e ) the inte rnal s y stem reco v e r y time cannot b e sa tisfied. do no t se t to " 01." tmp19a43 (rev2.0) 5-14 clock/s t andby control
tmp19a43 3. t r an sition o f op eration m o d e s: slow st o p sl ow sl ow sl ow st o p sy ste m cl o c k o f f fsy s (lo w -s peed c l o c k ) m ode cg (lo w -s peed c l o c k ) wa r m -up ( w -up) s t art of l o w - s peed c l o c k osc i l l at i o n s t art of w a rm -up e nd of w a rm -up w h en @fs=32 .7 68 kh z se le c t ion of w a rm-up time syscr2 warm-up time (fs) 11 (2 16 / f s ) 2 0 0 0 m s 4 . t r an sition o f op eration m o d e s: slow s l eep sl ow sl ow sl ow s l eep sy ste m cl o c k o f f fsy s (lo w -s peed c l o c k ) m ode cg (f s ) (lo w -s peed c l o c k ) (note) the lo w - speed clock (fs) continues os cillation. there is no need to make a w a r m -u p setting. tmp19a43 (rev2.0) 5-15 clock/s t andby control
tmp19a43 t able 5-8 pin s t ates in the st op mode i n each s t ate of syscr2 (1/2) pin na me input /ou t put = 0 < d r v e > = 1 p 0 0 - p 0 7 i n p u t m o d e output mode a d 0-ad7, d0-d7 ? ? ? output p 1 0 - p 1 7 i n p u t m o d e output mode, a8-a15 ad8-ad15, d8-d15 a8-a7 (output mode) ? ? output ? output output p 2 0 - p 2 7 i n p u t m o d e output mode, a0-a7/a16-a23 (output mode) ? ? output input output output p30 (/rd), p31 (/wr) output pin /rd,/wr(output mode) ? output output output p32(/hwr) p35(/busak, p36(r/w) input mode output mode /hwr,/busak r/w(output mode) ? ? output input output output p37 (ale) input mode output mode ale (output mode) ? ? "l" lev e l output input output "l" lev e l ou tput p 4 0 - p 4 3 i n p u t m o d e output mode /cs0-/cs2 (output mode) key24-key27 (input mode) ? ? output input input output output input p44 ?p47 input mode output mode ? ? input output p 5 0 - p 5 5 i n p u t m o d e output mode, a0-a5 (output mode) ? ? output input output p56, p57 input mode output mode a6, a7 (outp u t mode) key28, key29 (input mode) ? ? output input input output input p61, p64 input mode output mode a9, a12 (outpu t mode) inta, intb ( i n put mode) ? ? output input ? output input p60, p62, p63, p65-p67 input mode output mode, a8 , a1 0 , a11 , a13 - a1 5 (output mod e ) ? ? output ? output p 7 0 - 7 3 i n p u t m o d e ? ? p 7 4 - 7 7 i n p u t m o d e key00-key03 (input mode) input input ? input p 8 0 - p 8 3 i n p u t m o d e key04-key07 (input mode) input input ? input p 8 4 - p 8 7 i n p u t m o d e int6-int9 (inp u t mode) input input ? input p 9 i n p u t m o d e output mode ? ? input output p a 0 - p a 5 i n p u t m o d e output mode int0-int5 (inp u t mode) ? ? input input output input pa6, pa7 input mode output mode ? ? input output p b 0 - p b 7 i n p u t m o d e output mode ? ? input output p c 0 i n p u t m o d e output mode key30 (input m ode) ? ? input input output input p c 1 - p c 7 i n p u t m o d e output mode ? ? input output tmp19a43 (rev2.0) 5-16 clock/s t andby control
tmp19a43 pin na me input /out put = 0 < d r v e > = 1 p d 0 - p d 5 i n p u t m o d e output mode ? ? input output p d 6 i n p u t m o d e output mode key30 (input m ode) ? ? input input output input p e 0 - p e 7 i n p u t m o d e output mode key08-key15 (input mode) ? ? input input output input p f 0 - p f 7 i n p u t m o d e output mode key16-key23 (input mode) ? ? input input output input pg, ph input mode output mode ? ? input output reset input pin input input t e s t i n p u t p i n i n p u t i n p u t x 1 i n p u t p i n ? ? x2 output pin "h" leve l output "h" level output x t 1 i n p u t p i n ? ? xt2 output pin "h" leve l output "h" level output ? : in di cat es t h at t h e i n put i s di sa bl ed fo r t h e i n p u t m ode an d t h e i n p u t pi n an d t h e i m pedance becom e s hi g h fo r t h e o u t p ut m ode and t h e out put pi n . n o t e t h at t h e i n put i s e n a b l e d whe n t h e po rt fu nct i o n re gi st er (p xfc) is "1" a n d the p o rt c o n t rol re gister (p xcr) is " 0 ." inpu t : th e inpu t g a te is activ e. t o prev en t th e i n put p i n fr om fl oat i ng, fi x t h e i n put v o l t a ge t o t h e "l" or "h" lev e l. ou t p u t : th e p i n is in t h e ou tpu t state. pu * : th is is th e p r og ramm ab le p u l l-up p i n. th e in pu t g a te is al w a ys d i sab l ed . no f e ed thr oug h cu rr en t f l ow s even if t h e high im pedance is selected. tmp19a43 (rev2.0) 5-17 clock/s t andby control
tmp19a43 tmp19a43 (rev2.0) 5-18 clock/s t andby control ( n ote) 1 9 a43 r eq ui re s a r ec ov er y t im e fr om wa rm in g up st at e as f oll ow i ng sle ep m o de ( f s ) no rm al m ode ( f c / g ear) i d l e m ode reset res e t r e l e a s e so f t w a r e in te r r u p t s t o p m ode so f t w a r e so f t w a r in te r r u p t (cpu s t op) (s e l ect i ve i/o ) int e rr upt s l o w m o de (fs ) in te r r u p t so f t w a r soft w a r i n terrup t so f t al l s t oped a b c d e f g h st ate t r ansit i on d i agr a m wu p tr ig ge r st at e tr an si ti on r u n n i n g m ode a ft er w up m i n i m u m r equ ir ed o pe rat io n ti me b e f o r e w a it in st ru ct ion d on e ( sec ) a st op /s le ep 64 / fsy s i n no ma l mo de stop release b st op /s le ep 16 / fsy s i n sl ow mod e c st op /s le ep 64 / fsy s i n no ma l mo de sleep release d st op /s le ep - wu p tr ig ge r st at e t r a n s i t i on m i n i m u m r equ ir ed o pe rat io n ti me b e f o r e w a it in st ru ct ion d on e ( sec ) e st op 16 / f s i n no mal mode so ft wa re re le as e f sl ee p 16 x f s in nom al m ode
tmp19a43 tmp19a43 (rev2.0) 6-1 exceptions/interrupts 6. exceptions/interrupts 6.1 overview the tmp19a43 device is configured with the following 50 maskable interrupt factors and 15 exceptions including nmi. in this section, general exceptions and debug exceptions are described simply as "exceptions" and interrupts are described as "interrupts." ? general exceptions reset exception non-maskable interrupt (nmi) address error exception (instruction fetch) address error exception (load/store) bus error exception (instruction fetch) bus error excep tion (data access) co-processor unusable exception reserved instruction exception integer overflow exception trap exception system call exception breakpoint exception ? debug exception single step exception debug breakpoint exception ? interrupts maskable software interrupts (2 factors) maskable hardware interrupts: 46 internal fact ors and 48 external factors (int0 - f, key00 - 31) the tmp19a43 device not only processes interrupt requests from internal hardware peripherals and external inputs but also forces transition to exception handling processes as a means of notifying any error status generated in normal instruction sequences. by using the register bank called "shadow register set" newly implemented in the tx19a processor core, it is now unnecessary to save the general purpose register (gpr) contents elsewhere upon interrupt response thus leading to very fast interrupt response. the device is capable of handling multiple interrupts accord ing to seven programmable interrupt levels (priority orders). also, it can mask interrupt requests with a priority level the same or lower than a specified mask level.
tmp19a43 tmp19a43 (rev2.0) 6-2 exceptions/interrupts 6.2 exception vector the starting address of an exception handler is defined to be "exception vector address." the exception vector address for a reset exceptio n and non-maskable interrupts is 0xbfc0_0000. the exception vector address for a debug exception can be either 0xbfc0_0480 (ejtag proben = 0) or 0xff20_0200 (ejtag proben = 1) depending on the internal signal . for other exceptions, the corresponding exception vector addresses are determined depending on the values of status and cause of the system control coprocessor register (cp0). table 6.21 exception vector table (virtual address) exception bev=0 bev=1 reset, nmi 0xbfc0_0000 0xbfc0_0000 debug exceptions (en=0) 0xbfc0_0480 0xbfc0_0480 debug exceptions (en=1) 0xff20_0200 0xff20_0200 interrupts (iv=0) 0x8000_0180 0xbfc0_0380 interrupts (iv=1) 0x8000_0200 0xbfc0_0400 others general exceptions 0x8000_0180 0xbfc0_0380 (note 1) if exception vector addresses are to be placed in internal rom, set the status bit of the system control coprocessor register (cp0) to "1." 6.3 reset exception a reset exception is generated by either setting the ex ternal reset pin to "l" or counting the wdt beyond a "reset" count. when a reset exception is generated, pe ripheral hardware registers and the cp0 register are initialized and it jumps to the exception vector address 0xbfc0_0000. the pc value of reset exception generation will be stored in errorepc of the cp0 register. since a reset exception causes to set the status bit of the cp0 register to "1" disabling interrupt requests, the status bit must be cleared to "0" in a start up routine (reset exception handler) or by any other means if interrupts are to be used. refer to the section "exception handling, reset exceptio n" of the separate volume "tx19a core architecture" for detailed operation upon generation of reset exception.
tmp19a43 tmp19a43 (rev2.0) 6-3 exceptions/interrupts 6.4 non-maskable interrupt (nmi) an nmi interrupt is generated when wdt is counted to an nmi set count or when a bus error area is accessed by store access including dma transfer. when an nmi interrupt is generated, the status bits and of the cp0 register are set to "1" and it jump s to the exception vector address 0xbfc0_0000. the pc value of nmi generation will be stored in errorepc of the cp0 register. note that any nmi due to a bus error upon a store instruction causes an exception that is not synchroni zed with instruction sequence. therefore, the pc value of an instruction being executed at the time of error generation will be stored instead of the pc value for the instruction that actually caused the error. upon nmi generation, when the shadow register set is enabled, sscr will be overwritten by the value of sscr but the register bank will not be switched because the value of sscr is not updated. the reason why only the sscr value is updated is because it is necessary to prevent the regi ster bank from being changed when sscr is overwritten by the value of sscr due to an eret instruction executed upon returning from nmi. the cause of nmi generation can be determined by nmiflg and of cg. (refer to the section 6.10, nmi flag register reference.) refer to the section "exception handling, non-maskable interruptions" of the separate volume "tx19a core architecture" for detailed operation upon generation of nmi. 6.5 general exceptions (other than reset exception and nmi) a general exception will be generated when a specific in struction such as syscall is executed or when any abnormalities such as an illegal instruction fetch is detected. when a general exception is generated and if status of the cp0 register is "1," it jumps to the ex ception vector address 0xbfc0_ 380. the cause of a general exception can be determined by cause of the cp0 register. the pc value at a general exception will be stored in epc of the cp0 register. note that any bus error exception (data access) is not synchronized with instruction sequence so the pc value of an instruction being executed at the time of error generation will be stored instead of the pc value for the instruction that actually caused the error. upon a general exception, when the shadow regi ster set is enabled, sscr will be overwritten by the value of sscr but the register bank will not be switched because the value of sscr is not updated. the reason why only the ssc r value is updated is becaus e it is necessary to prevent the register bank from being changed when sscr is overwritten by the value of sscr due to an eret instruction executed upon returning from the exception. any illegal address that caused an address error exce ption (instruction fetch or load/store) or bus error (instruction fetch/data access) will be stored in badvad dr of the cp0 register. refer to the corresponding sections of "exception handlin g" of the separate volume "tx19a core architecture" for detailed operation upon generation of general exceptions. (note 1) address error exceptions (load/store) will not be generated in dms transfer operations. in dma transfer, address errors can be detected as configuration errors (csrx of dmac). (note 2) bus errors (data access) may be generated either by load instructions or by load accesses of dma transfer operations.
tmp19a43 tmp19a43 (rev2.0) 6-4 exceptions/interrupts fig. 6-1 example sequence of general exceptions (other than reset exception and nmi) (note 1) since general exceptions (other than reset exception/nmi and excluding trap exceptions, system call exceptions, and breakpoint exceptions ) indicate some sort of abnormal conditions, the system tends to be reset. (note 2) upon generation of a general exception other than reset exception/nmi, excluding bus error exceptions (instruction fetch/data access), the pc that caused the exception will be stored in epc. therefore, returning the system by si mply using eret may cause the same exception again. read cause to determine the factor of generation jump to exception handling return necessary registers eret return to exception generation address read table for the address of exception handling if necessary processes of tx19a core processes of user software automatically jump to exception vector address exception handling (note 1) save registers as necessary
tmp19a43 tmp19a43 (rev2.0) 6-5 exceptions/interrupts 6.6 debug exceptions single step exceptions and debug breakpoint exceptions are the types of debug exceptions. these types of exceptions are seldom used in user programs. also note that enabling the shadow register set will not be effective in debug exceptions. refer to the section "exception handling, debug exception" of the separate volume "tx19a core architecture" for detailed operation upon generation of debug exceptions. 6.7 maskable software interrupts two-factor maskable software interrupts (hereinafter referred to simply as "software interrupts") can be generated by individually setting "1" to the cause bits of the cp0 register. software interrupts can be accepted in no less than three clocks after setting values to the cause bits of the cp0 register. in order for a software interrupt reques t to be accepted, it is necessary regarding the cp0 register that its status is set to "1" and status is cleared to "0" while status is "1." also, software interrupts can be individually masked by setting status of the cp0 register to "0." if software and hardware interrupts coincide, the hardware interrupt overrides the software interrupt. upon software interrupts, when the shadow register set is enabled, sscr will be overwritten by the value of sscr but the register bank will not be switched because the value of sscr is not updated. the reason why only the ssc r value is updated is becaus e it is necessary to prevent the register bank from being changed when sscr is overwritten by the value of sscr due to an eret instruction executed upon returning from the softwa re interrupt. software in terrupts are processed in a process flow such as shown in fig. 6-2. (note 1) please read out the data in ivr after a software in terrupt is generated. to read out the data is a trigger to notify the core of a hardware interrupt. (note 2) the "software interrupt," which is a maskable interrupt, can be generated by setting ip [1:0] of the cause register of cp0. this "software interr upt" is different from th e "software set," which is one of the hardware interrupt factors. the "software set" interrupt is generated by setting of the imc0 register in the interrupt controller (intc) to any value other than "0."
tmp19a43 tmp19a43 (rev2.0) 6-6 exceptions/interrupts fig. 6-2 example of software interrupt operation (note 1) a software interrupt is accepted in no less than th ree clocks after the instruction that enabled the interrupt and the pc at the time of acceptance is stored in epc. processes of tx19a core processes of user software processes of user software automatically jump to exception vector address read cause to determi ne the factor of generation jump to interrupt handler interrupt processing return necessary registers eret instruction return to interrupt generation address save registers as necessary set cause =1 to generate interrupt set cause = 0 to clear interrupt
tmp19a43 tmp19a43 (rev2.0) 6-7 exceptions/interrupts 6.8 maskable hardware interrupts 6.8.1 features the maskable hardware interrupts (h ereinafter referred to as "hardware interrupts") are 64 factor interrupt requests for which the interrupt controller (intc) can individually assign an interrupt level out of seven interrupt (priority) levels. in order for a hardware interrupt request to be accepted , it is necessary regarding the cp0 register that its status is set to "1" and status is cleared to "0" while status is set to "1." if more than one interrupts are generated at the sa me time, the hardware interrupts are accepted in accordance with the priority or der of the interrupt levels. if more th an one interrupts of a same interrupt level are generated at the same time, these interrupt s are accepted in the order of the interrupt number as listed in table 6.8.1. when an interrupt request is accepted, the status bit of the cp0 register is set to "1," further interrupts are disabled, and ilev of intc is automatically updated to the interrupt level set for the interrupt request. note that status of the cp 0 register remains set to "1" in interrupt response operations. in processing hardware interrupts, each interrupt level is associated w ith a register bank called a "shadow register set." when an interrupt reque st is accepted, the register bank is switched to the register bank of which number is the same as with the corresponding interrupt level. through this mechanism, it is unnecessary for the user program to save the general purpose register (gpr) contents elsewhere upon interrupt response thus ensuring fast interrupt response. cp0 register sscr=0) for accepting multiple interrupts, status of th e cp0 register is cleared to "0" to permit further interrupts. in this, because ilev of intc has been updated to the interrupt level set for the interrupt request already accepted, only further interrupts of which level is higher than the present interrupt level can be accepted. refer to section 6.8.7 "example of multiple interrupt setting" for more details of multiple interrupts. also, by appropriately setting the ilev register of intc, you can mask interrupt requests of which interrupt level is lower than a programmed mask level. any interrupt request can be used as a tr igger to start a dma transfer sequence. while detailed operation of hardware interrupts is provided below, please also refer to the section "exception handling, maskable interrupts (interrupts)" of the separate volume "tx19a core architecture" for more details. fig. 6-3 interrupt notification diagram tx19a core intc cg interrupts to clear standby other interrupts notification response
tmp19a43 tmp19a43 (rev2.0) 6-8 exceptions/interrupts table 6.8.1 list of hardware interrupt factors interrupt number ivr[7:0] interrupt factor interrupt control register address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 0x000 0x004 0x008 0x00c 0x010 0x014 0x018 0x01c 0x020 0x024 0x028 0x02c 0x030 0x034 0x038 0x03c 0x040 0x044 0x048 0x04c 0x050 0x054 0x058 0x05c 0x060 0x064 0x068 0x06c 0x070 0x074 0x078 0x07c 0x080 0x084 0x088 0x08c 0x090 0x094 0x098 0x09c 0x0a0 0x0a4 0x0a8 0x0ac 0x0b0 0x0b4 0x0b8 0x0bc 0x0c0 0x0c4 0x0c8 0x0cc 0x0d0 0x0d4 0x0d8 0x0dc 0x0e0 0x0e4 0x0e8 0x0ec 0x0f0 0x0f4 0x0f8 0x0fc software set int0 pin int1 pin int2 pin int3 pin int4 pin int5 pin int6 pin int7 pin int8 pin int9 pin inta pin intb pin intc pin intd pin inte pin intf pin kwup intrx0 : serial receive (channel.0) inttx0 : serial transmit (channel.0) intrx1 : serial receive (channel.1) inttx1 : serial transmit (channel.1) intrx2 : serial receive (channel.2) inttx2 : serial transmit (channel.2) hintrx0 : high speed serial receive (hchannel.0) hinttx0 : high speed serial transmit (hchannel.0) hintrx1 : high speed serial receive (hchannel.1) hinttx1 : high speed serial transmit (hchannel.1) hintrx2 : high speed serial receive (hchannel.2) hinttx2 : high speed serial transmit (hchannel.2) ints0 : serial bus interface 0 intadhp : highest priority adc complete interrupt intadm : adc monitor function interrupt inttb0 : 16-bit timer 0 inttb1 : 16-bit timer 1 inttb2 : 16-bit timer 2 inttb3 : 16-bit timer 3 inttb4 : 16-bit timer 4 inttb5 : 16-bit timer 5 inttb6 : 16-bit timer 6 inttb7 : 16-bit timer 7 inttb8 : 16-bit timer 8 inttb9 : 16-bit timer 9 inttba : 16-bit timer a inttbb : 16-bit timer b inttbc : 16-bit timer c inttbd : 16-bit timer d inttbe : 16-bit timer e inttbf : 16-bit timer f intcapg0 : input capture group 0 reserved intcmp0 : compare interrupt 0 intcmp1 : compare interrupt 1 intcmp2 : compare interrupt 2 intcmp3 : compare interrupt 3 intcmp4 : compare interrupt 4 intcmp5 : compare interrupt 5 intcmp6 : compare interrupt 6 intcmp7 : compare interrupt 7 inttbt : overflow interrupt intrtc : clock timer interrupt intad : adc completed intdma0 : completion of dma transfer (channel.0) intdma1 : completion of dma transfer (channel.1) imc0 imc1 imc2 imc3 imc4 imc5 imc6 imc7 imc8 imc9 imca imcb imcc imcd imce imcf 0xffff_e000 0xffff_e004 0xffff_e008 0xffff_e00c 0xffff_e010 0xffff_e014 0xffff_e018 0xffff_e01c 0xffff_e020 0xffff_e024 0xffff_e028 0xffff_e02c 0xffff_e030 0xffff_e034 0xffff_e038 0xffff_e03c
tmp19a43 tmp19a43 (rev2.0) 6-9 exceptions/interrupts (note 1) while imcxx is a 32 bit register, 8 bit/16 bit access is also accepted. (note 2) each factor can clear the idle mode. table 6.8.2 interrupt factors to cancel stop/sleep modes number interrupt factor note 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int0 int1 int2 int3 int4 int5 int6 int7 int8 int9 inta intb kwup intrtc inttb2 inttb3 external interrupt 0 external interrupt 1 external interrupt 2 external interrupt 3 external interrupt 4 external interrupt 5 external interrupt 6 external interrupt 7 external interrupt 8 external interrupt 9 external interrupt a external interrupt b key on wake up interrupt clock timer interrupt two-phase pulse input counter interrupt 2 two-phase pulse input counter interrupt 3 * number 0 to 12 interrupt factors can cancel stop, sleep, and idle modes. * number 13 to 15 interrupt factors can cancel the sleep mode.
tmp19a43 tmp19a43 (rev2.0) 6-10 exceptions/interrupts 6.8.2 detecting interrupt requests each of interrupt factors has its own interrupt detectio n sequence as described in table 6.8. upon detection, an interrupt request is notified to intc for priority arbitration and then notified to the tx19a processor core. refer to table 6.8 for the detection level available for each interrupt factor. table 6.8.3 location of interrupt request detection interrupt detected by interrupt notification route cg port cg (detection) intc (arbitration) tx19a core (1) interrupts from external pins int0 - intb intc port intc (detection/arbitration) tx19a core (2) interrupts from external pins intc - intf intc port intc (detection/arbitration) tx19a core cg port cg (detection) intc (arbitration) tx19a core (3) key on wakeup interrupt kwup00-31 intc port intc (detection/arbitration) tx19a core (4) rtc interrupt rtc cg port cg (detection) intc (arbitration) tx19a core (5) other interrupts intc peripheral circuit intc (detection/arbitration) tx19a core 6.8.3 interrupt priority arbitration 1. seven levels of interrupt priority each of interrupt factors can be individually set to one of the seven interrupt priority levels by intc. the interrupt level to be applied is set by imcxx of intc. the higher the interrupt level set, the higher the priority. if the value is set to "000" meaning interrupt level of 0, no interrupts will be generated by the factor. also note that any factors of interrupt level 0 are not suspended. 2. interrupt level notification when an interrupt request is generated, intc compar es the interrupt level with the mask level. if the interrupt level is higher than the mask level set in ilev , it notifies the tx19a processor of the interrupt request. if more than one interrupts are generated at the same time, the interrupts are notified in accordance with the priority order of these interrupt levels. if more than one interrupts of a same interrupt level are generated at the same time, these interrupts are notif ied in the order of the interrupt number as listed in table 6.8.1. when an interrupt request of the same interrupt factor is received again before the previous interrupt has been cleared, only the first interrupt can be accepted. 3. intc register update when an interrupt request is accepte d by the tx19a core, the highest in terrupt level at that point in time will be set to ilev and the correspon ding vector value is set to ivr. once cmask and ivr are set, any interrupt with a higher interrupt level cannot update them or cause notification to the core until the ivr value is read. (note 1) so, be sure to read the ivr value before atte mpting to change the ilev value. if the ilev value is changed before reading ivr, an unexpected interrupt request may be generated.
tmp19a43 tmp19a43 (rev2.0) 6-11 exceptions/interrupts 6.8.4 hardware interrupt operation when a hardware interrupt is generated, the tx19a core will go through the following steps to jump to the corresponding exception vector address as given in table 6.21 according to the status and cause bits of the cp0 register. (1) sets status of cp0 register to "1." (2) sets the pc value at the interrupt generation to epc of the cp0 register. (3) if the shadow register set is enabled (cp0 register sscr = 0), sscr of the cp0 register will be updated and it switches to the re gister bank of the same interrupt level number. (4) the values of ilev of intc will be updated and the mask level is set to the interrupt level of the interrupt request accepted. (5) sets ivr [7:0] to the corresponding value listed in table 6.8.1.
tmp19a43 tmp19a43 (rev2.0) 6-12 exceptions/interrupts fig. 6.8.4 basic operation of hardware interrupts (example) (note 1) by using the shadow register set (setting cp 0 register sscr = 0), most of general purpose register contents can be automatically saved in tx19a core. processes of tx19a core processes of user software clear interrupt factor by intclr automatically jump to the exception vector address after interrupt generation read ivr to generate interrupt vector address read interrupt handler address from interrupt vector jump to interrupt handler interrupt processing return necessary registers (note 1) eret instruction return the mask level by setting ilev = 0 save necessary registers (note 1) return to interrupt generation address
tmp19a43 tmp19a43 (rev2.0) 6-13 exceptions/interrupts 6.8.5 initialization for interrupts before using interrupts, it is necessary to appropriatel y configure them. necessary settings that have to be made regardless of the interrupt factors are descri bed in section 6.8.5.1 "common initialization" and settings specifically required for certain factors and applications are described in section 6.8.5.2 "initialization for individual interrupt factors." 6.8.5.1 common initialization in order to use interrupts, the following settings are necessary: (1) set status of cp0 register to "111." (2) set the base address of the interrupt vector table to ivr [31:8] of intc. (3) set the interrupt handler addresses for the respec tive interrupt factors to the addresses obtained as the sum of the base address of "the interrupt vect or table and the ivr [7:0] values corresponding to the respective interrupt factors." example of the above step (1): when the interrupt exception vector address 0xbfc00400 is used lui r2,0x1040 ; cu0=1, bev =1 (r2 =0x1040_xxxx) addiu r2,r2,0x1c00 ; im4,im3,im2 =1 (r2 =0x1040_1c00) mtc0 r2,r12 example of the above step (2): if vector table is used as the label of the interrupt vector table lui r3,hi(vectortable) addiu r3,r3,lo(vectortable) ; r3 = vectortable address lui r2,hi(ivr) ; r2 =0xffff_xxxx (upper 16 bits of ivr address) sw r3,lo(ivr)(r2) ; set address of vectortable to ivr[31:8] example of the above step (3): if the base address of interrupt vector is set to 0xbfc20000 _vectortable section code isa32 abs=0xbfc20000 vectortable: dw _swint ; 0 --- software interrupt dw _int0 ; 1 --- int0 dw _int1 ; 2 --- int1 dw _int2 ; 3 --- int2 dw _int3 ; 4 --- int3 dw _int4 ; 5 --- int4 dw _int5 ; 6 --- int5 dw _int6 ; 7 --- int6 dw _int7 ; 8 --- int7 (note 1) the above examples assume the use of asse mbler made by toshiba. if any third party assembler is used, it may generate syntax errors; you are advised to modify the above statements according to the assembler to be used.
tmp19a43 tmp19a43 (rev2.0) 6-14 exceptions/interrupts 6.8.5.2 initialization for individual interrupt factors the registers to be set in using different interrupt factors are as listed below: table 6.8.4 registers to be set for detecting interrupts interrupt registers to be set interrupt detection levels available (setting in active condition) pxfc(port) pxcr(port) imcxx(intc) with intc, "l" and "h" levels and falling and rising edges can be set. (1) interrupts from external pins int0 - intb pxfc(port) pxcr(port) imcgx(cg) imcxx(intc) if it is to be used for recovery from standby mode, set "l" and "h" levels and falling and rising edges for cg while intc must be set to "h." (2) interrupts from external pins intc - intf pxfc(port) pxcr(port) imcxx(intc) with intc, "l" and "h" levels and falling and rising edges can be set. pxfc(port) pxcr(port) imcxx(intc) with intc and kwup circuit, "l " and "h" levels and falling and rising edges can be set. (3) key on wakeup interrupt kwup00 - 31 pxfc(port) pxcr(port) imcgx(cg) imcxx(intc) if it is to be used for recovery from standby mode, it must be set to "h" with intc. with the kwup ci rcuit, "l" and "h" levels and falling/rising edges can be set. (4) intrtc interrupt pxfc(port) pxcr(port) imcgx(cg) imcxx(intc) set for rising edge with cg; it must be set to "h" with intc. (5) other interrupts imcxx(intc) with intc, "l" and "h" levels and falling/rising edges can be set. (note 1) in level detection, the value is checked at in ternal clock timing each time. edge detection is made by comparing the previous value with the current value at internal clock timing. in interrupt initialization, follow the order of the in terrupt detection route as indicated in table 6.8 before enabling the interrupts with the cp0 register. if any diff erent setting order is used, an unexpected interrupt may be generated. so, be sure to clear interrupt factor s before setting interrupt permission. similarly, if interrupts are to be disabled, first disable the interr upt by the cp0 register and then set the registers accordingly in the reverse order of interrupt detection. (1) interrupts from external pins (int0 to intb) ? use port pxcr to enable an input por t. (refer to 7. port function) ? use port pxfc to set pin functions to int0 - intb. (refer to 7. port function) ? use port pxpe to set pull-up connections as appropriate. (refer to 7. port function) ? use intc imcx to set active state. (r efer to 5.3.3 interrupt-related registers) ? use imcgx of cg for setting to enable/d isable clearing of standby modes. (refer to intcg registers, interrupts to clear stop, sleep, and idle) ? use intc imcx to set active state of internal interrupt signals to be notified from cg. if rising or falling edge is set with intc im cx , set it to falling edge (set imcx to "10"). for h/l level setting, set it to "l" level (set imcx to "00"). (refer to 6.8.8 registers.)
tmp19a43 tmp19a43 (rev2.0) 6-15 exceptions/interrupts ? an example setting when an external interrupt "int3" is used to clear stop by the falling edge: status = "0" ; interrupt is disabled pacr = "0" ; the port is set to an input port pafc ="0" ; the port is assigned to int3 imcga ="010" ; int3 is set to falling edge imcga ="1" ; int3 is set to clear standby mode eicrcg ="0011" ; clears the int3 standby clear request imc1 ="01" ; int3 is set to level detection intclr ="010" ; clear s the int3 interrupt request imc1 ="101" ; interrupt level of int3 is set to "5." ilev/ ="1"/"xxx" ; ma sk level is set to "xxx." (to be set simultaneously with ilev ) sync instruction ; stall until interrupt settings are enabled. status = "1" ; interrupt is enabled ? an example setting when an external interrupt "int3" is to be disabled: status = "0" ; interrupt is disabled imc1 = "000" ; int3 interrupt is disabled. intclr ="010" ; clear s the int3 interrupt request (2) interrupts from external pins (intc to intf) ? use port pxier to enable an input port. (refer to 7. port function) ? use port pxfr to set pin functions to in tc - intf. (refer to 7. port function) ? use intc imcx to set active state. (refer to 6.8.8 registers.) ? an example setting when an external interrupt "intf" is detected by the "h" level: status = "0" ; interrupt is disabled p5cr = "0" ; the port is set to an input port p5fc = "0" ; the port is set to an input port imc4 = "01" ; intf is set to "h" level intclr = "0x040" ; clears the intf interrupt request imc4 = "010" ; interrupt level of intf is set to "2." ilev/ = "1"/ "xxx" ; mask level is set to "xxx." (to be set simultaneously with ilev ) status = "1" ; interrupt is enabled
tmp19a43 tmp19a43 (rev2.0) 6-16 exceptions/interrupts (3) key on wakeup interrupt, kwup00 to 31 ? use port pxcr to enable the input por t. (refer to 7. port function) ? use port pxfc to set the pin function to key. (refer to 7. port function) ? use port pxpe to set pull-up connections as appropriate. (refer to 7. port function) ? use kwupstxx to enable key on wakeup. (refer to 20. key on wakeup circuit) ? set active state of key. (refer to 20. key on wakeup circuit.) ? use intc imcx to set active state. (r efer to 5.3.3 interrupt-related registers) ? use imcgx of cg for setting to enab le/disable clearing of standby. (refer to intcg registers, interrupts to clear stop, sleep, and idle) ? an example setting when key08 is used as an in put to clear stop (dynamic pull-up, falling edge): status = "0" ; interrupt is disabled pecr = "0" ; the port is set to work as an input port. pefc = "0" ; the port is set to key input. pepe = "1" ; pull-up is set to the port. kwupcnt = "0x24" ; the period of dynamic pull-up is set. (example: period; 10:1024/fs, duration: 01:4/fs) kwupst08 = "1" ; dy namic pull-up is set. kwupst08 = "010" ; it is set to falling edge. kwupst08 = "1" ; key input is enabled. kwupclr = "1010" ; key input factor is cleared. imcgd = "10" ; standby clear setting is set to "h" level imcgd = "1" ; kwup is set to clear standby mode. eicrcg = "1100" ; clear s kwup standby clear request imc4 = "01" ; kwup is set to h level. imc4 = "110" ; interrupt level of kwup is set to "6." ilev/ ="1"/"xxx" ; ma sk level is set to "xxx." (to be set simultaneously with ilev ) sync instruction ; stall until interrupt settings are enabled. status = "1" ; interrupt is enabled
tmp19a43 tmp19a43 (rev2.0) 6-17 exceptions/interrupts (4) other hardware interrupts ? settings are made to use peripheral hardware devices. ? set intc imcxx to "10." (refer to 6.8.8 registers.) (note 1) in interrupt initialization, set intc registers before enabling interrupts with the cp0 register. similarly, if interrupt is to be disabled, first disable interrupt by the cp0 register and then set intc. 6.8.5.3 interrupt enable in order for an interrupt request to be accepted, all the following parameters must be set to enable the interrupt in addition to the initial settings described in section 6.8.5 "initialization for interrupts." ? set status of the cp0 register to "0." ? set status of the cp0 register to "0." ? set status of the cp0 register to "1." by these settings, interrupt is enabled two clocks after execution of the instruction and the registers are set. note that one of the following methods may be used in setting status of the cp0 register to "1." ? set ier of the cp0 register to any value other than "0" using the mtc0 instruction (32 bit isa instruction). (note 1) ? execute the ei instruction of 16 bit isa. (note 2) (note 1) if toshiba c compiler is used, this is executed by the 32 bit isa instruction "_ _ei ( ) embedded function." (note 2) if toshiba c compiler is used, this instruction is executed by the 16 bit isa instruction "_ _ei ( ) embedded function." (note 3) the following different methods may also be used to set status of the cp0 register to "1." ? set status of the cp0 register to "1" using the mtc0 instruction of 32 bit isa. ? set status of the cp0 register to "1" using the mtc0 instruction of 16 bit isa.
tmp19a43 tmp19a43 (rev2.0) 6-18 exceptions/interrupts 6.8.5.4 interrupt disable to disable interrupts, either one of the following se tting procedures must be performed in addition to the settings described in section 6.8.5 "initialization for interrupts." when interrupts are disabled, any interrupt request will be suspended. also note that tmp19a43 doesn't suspend any interrupt factor that is set to interrupt level 0. ? set status of the cp0 register to "1." ? set status of the cp0 register to "1." ? set status of the cp0 register to "0." by these settings, interrupts are disabled immediately af ter execution of the instruction and the registers are set two clocks later. note that either of the followi ng methods may be used in setting status of the cp0 register to "0." ? set ier of the cp0 register to "0" using the mtc0 instruction of 32 bit isa. (note 1) ? execute the di instruction of 16-bit mode isa. (note 2) (note 1) if toshiba c compiler is used, this instruction is executed by the 32 bit isa instruction "_ _di ( ) embedded function." (note 2) if toshiba c compiler is used, this instruction is executed by the 16 bit isa instruction "_ _di ( ) embedded function." (note 3) the following different methods may also be used to set status of the cp0 register to "0." ? set status of the cp0 register to "0" using the mtc0 instruction of 32 bit isa. ? set status of the cp0 register to "0" using the mtc0 instruction of 16 bit isa.
tmp19a43 tmp19a43 (rev2.0) 6-19 exceptions/interrupts if the factors once enabled are to be individually disabled again after setting interrupt levels by imcx of intc, first set the status bits of the cp0 register to disable interrupts and then disable relevant factors individually. example statements to individua lly disable interrupt factors: mtc0 r0, ier ; interrupt is disabled (status = "0") sb r0, imcxx ; disable interrupt factors sync ; stall until it is write-enabled. mtc0 r29, ier ; interrupt is enabled (status = "1") (note 4) the above examples assume use of assembler made by toshiba. if any third party assembler is used, it may generate syntax errors; you are advised to modify the above statements according to the assembler to be used.
tmp19a43 tmp19a43 (rev2.0) 6-20 exceptions/interrupts 6.8.6 interrupt processing this section describes detailed operation of interrupt processing using the basic flow chart of fig. 6.8. 6.8.6.1 interrupt response and return c hardware processes to accept interrupts after interrupt request arbitration, intc sets the interr upt vector and interrupt level of the interrupt request accepted to ivr and ilev, respectively, to notify the tx19a processor core of the interrupt level. when the interrupt level is notified, the tx19a processor core sets status of the cp0 register to "1" to disable interrupts and saves the pc value at th e interrupt generation to epc. if the shadow register set is enabled (cp0 register sscr = 0), the processor core sets the interrupt level to sscr of the cp0 register and switches the register bank. when an interrupt is accepted, an y ongoing execution is suspended and it automatically jumps to the exception vector address (for interrupts). fig. 6-4 shows the sequence of accepting interrupts. fig. 6-4 hardware process flow to accept interrupts ? set 1 to cause ? set the pc of jump or branch instruction to epc ? set 0 to cause ? set pc to epc if cause =0, then set 0xbfc0_0380 to pc if cause = 1, then set 0xbfc0_0400 to pc set 0x00 to cause set status = 1 set interrupt level to sscr . yes interrupt detection branch delay within slot? no jump to exception vector address 1 compared to ilev , interrupt level is higher lower interrupt suspended status? 0 yes no the highest priority interrupt request? yes no both status and are 0?
tmp19a43 tmp19a43 (rev2.0) 6-21 exceptions/interrupts d processes to be performed by the exception handler after an interrupt request is accepted, it automatically jumps to the exception ha ndler where the interrupt vector address is read from intc ivr and the user program generates the address of the interrupt handler. as in the example statements presented in section 6.8. 5, "initialization for interrupts," the interrupt vector base address is set to ivr[31:8] so that the ivr value becomes the interrupt vector address. after reading the intc ivr value, the interrupt factor is cleared. if the interrupt factor is cleared before ivr is read, correct value cannot be read because the ivr value is also cleared. example exception handler statem ent: exception vector address (interrupt) is 0xbfc0_0400. vector_int section code isa32 abs=0xbfc00400 __interruptvector: lui r26,hi(ivr) lw r26,lo(ivr)(r26) ; read ivr for interrupt vector address lui r27,hi(intclr) sh r26,lo(intclr)(r27) ; interrupt request is cleared lw r26,0(r26) ; read interrupt handler address from interrupt vector jr r26 ; jump to interrupt handler nop (note 1) the above example assumes use of assembler made by toshiba. if any third party assembler is used, it may generate syntax errors; you are advised to modify the above statement according to the assembler to be used. e processes to be performed by the interrupt handler typical tasks of the interrupt handler are to save ap propriate registers and to process interrupts. if the shadow register set is enabled (cp0 register sscr = 0), the general purpose register values other than r26, r27, r28, and r29 (shadow register set number 1 to 7) are automatically saved so the user program doesn't have to save these. refer to the separate volume "tx19a core architecture" for details of general purpose registers that are to be automatically saved. in general, registers other than gpr are dependent on user programs. the status, epc, sscr, hi, lo, cause, and config values of the cp0 register shall be saved as appropriate. for using multiple interrupts, interr upts are enabled by clearing status of the cp0 register to "0" after appropriate saving processes. (note 1) note that general exceptions can be accepted even when interrupts are disabled. so, even when you don't use multiple interrupts, it is desirable to save any general purpose register and the cp0 register that could be overwritten by general exceptions.
tmp19a43 tmp19a43 (rev2.0) 6-22 exceptions/interrupts example interrupt handler settings to be necessary: save from sscr to stack ; save sscr values (as appropriate) nop instruction ; stall until sscr is switched nop instruction ; stall until sscr is switched save from epc to stack ; save epc values (as appropriate) save from status to stack ; save status values (as appropriate) nop instruction ; stall before executing eret instruction nop instruction ; stall before executing eret instruction status = "0" ; interrupt enable (only for multiple interrupts) (note 1) after overwriting sscr of the cp0 register, wait for two cycles to allow for register bank switching before attempting a register access. f returning from the interrupt handler for returning from the interrupt handler to the main process, return the register values saved at the top of the interrupt handler process and set "0" to intc il ev to clear the interrupt mask level. by executing the eret instruction after all the return tasks are completed, status of the cp0 register is cleared to "0" and the epc address returns to pc for th e main process to be resume d. if the shadow register set has been enabled (cp0 register sscr = 0), sscr is updated by the eret instruction and the shadow register set number is automatically decremented for automatically returning the general purpose registers saved in the register bank. if multiple interrupts are used, it is necessary to set status of th e cp0 register to "1" to disable interrupts prior to executing the return process. example settings to return from the interrupt hander: status = "1" ; interrupt disable (only for multiple interrupts) ilev = "0" ; decrement the mask level sync instruction ; stall until mask level is decremented return to sscr ; return sscr values saved (as appropriate) nop instruction ; stall until sscr is switched nop instruction ; stall until sscr is switched return to epc ; return sscr values saved (as appropriate) return to status ; return status values saved (as appropriate) nop instruction ; stall before executing eret instruction nop instruction ; stall before executing eret instruction eret instruction ; status = "0," epc to pc, sscr to sscr (note 1) after overwriting sscr of the cp0 register, wait for two cycles to allow for register bank switching before attempting a register access. (note 2) don't access the cp0 register two instructions prior to executing th e eret instruction.
tmp19a43 tmp19a43 (rev2.0) 6-23 exceptions/interrupts 6.8.7 example of multiple interrupt setting in "multiple interrupt" processing, a higher interrupt le vel interrupt is processed while an interrupt is being processed. with tmp19a43, multiple interrupts are pr ocessed through the interrupt priority arbitration function of intc. when an interrupt request is accepted, ilev of intc is automatically updated to the interrupt level of the interrupt accepted to enable arbitration to use the priority preset by the user program. c additional processes required for multiple interrupts when an interrupt is accepted, status of the cp0 register is set to "1" disabling furthe r interrupts. in order to allow multiple interrupts, it is necessary to save the registers that could be overwritten by the second and the following interrupts before enabling the multiple interrupt process. for this purpose, in addition to the typical exception handler and interrupt handler processes, save the following registers before setting status of the cp0 register to "0" to enable interrupts. cp0 registers that must be saved: ? epc ? sscr ? status (note 1) some of the registers may be automatically saved and returned by using some interrupt function of toshiba c compiler. refer to "tx19a c compiler reference" provided with the toshiba c compiler for more details. d additional return processes required for multiple interrupts before returning registers in the interrupt return proc ess, it is necessary to disable interrupts using the method described in section 6.8.5.4 "interrupt disable." this is to prevent the returned register values from being corrupted by multiple interrupts. note that the eret instruction automatically clears status of the cp0 register to "0." so, by setting status of the cp0 register to "1" to disable interrupts in the returning process, you can return from the interrupt with interrupts enabled automatically. e proper use of status and status while there is no significant distinction between th e status and status parameters, status is automatically set to "1" upon interrupt generation and cleared to "0" by the eret instruction automatically. in saving and returning register values at the initial and final phases of an interrupt process, where interrupts have to be disabled, hardware controlled status is normally used. status is used for other general interrupt enable/disable control functions. applicable interrupt enable/disable control sequences are described in section 6.8.7.1, "interrupt control for multiple interrupts." save the hi, lo, cause, and conf ig registers as appropriate.
tmp19a43 tmp19a43 (rev2.0) 6-24 exceptions/interrupts 6.8.7.1 interrupt control for multiple interrupts fig. 6-5 interrupt enable/disable control sequence for multiple interrupts c status = 1 interrupts can be enabled by setting status of the cp0 register to "1" while status is set to "0." this optional setting is made by the software program when it is necessary. d interrupt generation when an interrupt is generated, status of the cp0 register is set to "1" disabling further interrupts. this process is automatically performed by hardware. e status = 0 if multiple interrupts are to be enabled, it is necessary to set status of the cp0 register to "0" to enable interrupts after relevant registers are saved. if interrupts are enabled before saving registers, a higher priority level interrupt could corrupt the register data . this optional setting is made by the software program when it is necessary. f multiple interrupts enabled this is the period multiple interrupts are enabled. inte rrupts with a level higher than the present interrupt level (ilev ) are to be accepted. if it is de sired to disable interrupts during this period, set status of the cp0 register to "0." g status = 1 if multiple interrupts are enabled, it is necessary to se t status of the cp0 register to "1" to disable interrupts before returning relevant register values. if registers are saved before disabling interrupts, a higher priority level interrupt could corrupt the register data. this optional setting is made by the software program when it is necessary. h eret instruction this instruction returns the system to the state before th e interrupt generation. if this instruction is executed while status of the cp0 register is set to "1," the status will be automatically set to "0" and interrupt is enabled (provided that status of the cp0 register is set to "1"). i status=0 interrupts can be disabled by setting status of the cp0 register to "0." this optional setting is made by the software program when it is necessary.
tmp19a43 tmp19a43 (rev2.0) 6-25 exceptions/interrupts 6.8.8 registers 6.8.8.1 register map table 6.8.5 intc register map address register symbol register corresponding interrupt number 0xffff_e000 imc0 interrupt mode control register 00 0 to 3 0xffff_e004 imc1 interrupt mode control register 04 4 to 7 0xffff_e008 imc2 interrupt mode control register 08 8 to 11 0xffff_e00c imc3 interrupt mode control register 12 12 to 15 0xffff_e010 imc4 interrupt mode control register 16 16 to 19 0xffff_e014 imc5 interrupt mode control register 20 20 to 23 0xffff_e018 imc6 interrupt mode control register 24 24 to 27 0xffff_e01c imc7 interrupt mode control register 28 28 to 31 0xffff_e020 imc8 interrupt mode control register 32 32 to 35 0xffff_e024 imc9 interrupt mode control register 36 36 to 39 0xffff_e028 imca interrupt mode control register 40 40 to 43 0xffff_e02c imcb interrupt mode control register 44 44 to 47 0xffff_e030 imcc interrupt mode control register 48 48 to 51 0xffff_e034 imcd interrupt mode control register 52 52 to 55 0xffff_e038 imce interrupt mode control register 56 56 to 9 0xffff_e03c imcf interrupt mode control register 60 60 to 63 0xffff_e040 ivr interrupt vector register 0xffff_e060 intclr interrupt request clear register 0xffff_e10c ilev interrupt mask level register (note 1) while the interrupt mode control register (imcxx) is a 32 bit register, 8 bit/16 bit access is also accepted.
tmp19a43 tmp19a43 (rev2.0) 6-26 exceptions/interrupts 6.8.8.2 interrupt vector registers (ivr) for an interrupt generated, the ivr register indicates the interrupt vector address of the corresponding interrupt factor. when an interrupt request is accep ted, the corresponding value as listed in table 6.8.1 is set to ivr [7:0]. by setting the base address of interrupt vectors to ivr [3 1:8], a read/write register, simply reading the ivr value can provide the corresponding interrupt vector address. table 6.8.6 interrupt vector register 7 6 5 4 3 2 1 0 ivr bit symbol ivr7 ivr6 ivr5 ivr4 ivr3 ivr2 ivr1 ivr0 (0xffff_e040) read/write r after reset 0 0 0 0 0 0 0 0 function the vector of the interrupt facto r generated is set. always reads "0." 15 14 13 12 11 10 9 8 bit symbol ivr15 ivr14 ivr13 ivr12 ivr11 ivr10 ivr9 ivr8 read/write r/w r after reset 0 0 0 0 0 0 0 0 function 23 22 21 20 19 18 17 16 bit symbol ivr23 ivr22 ivr21 ivr20 ivr19 ivr18 ivr17 ivr16 read/write r/w after reset 0 0 0 0 0 0 0 0 function 31 30 29 28 27 26 25 24 bit symbol ivr31 ivr30 ivr29 ivr28 ivr27 ivr26 ivr25 ivr24 read/write r/w after reset 0 0 0 0 0 0 0 0 function
tmp19a43 tmp19a43 (rev2.0) 6-27 exceptions/interrupts 6.8.8.3 interrupt level register (ilev) ilev is the register to control the interrupt level to be used by intc in notifying interrupt requests to the tx19a processor core. interrupts with interrupt levels not higher than ilev are suspended. the interrupt priority level "7" is the highest priority and "1" the lowest. note that any interrupt with interrupt level 0 is not suspended. when a new interrupt is generated, the correspond ing interrupt level is stored in and any previously stored values are incremented in mask levels such that the previous cmask is saved in pmask0 and pmask0 is saved in pmask1 and so on . for writing a new value to , set "1" to and write simultaneously. writing a new value to cannot be made. when is set to "0," the interrupt mask levels in the register shift back to the previous state such that pmask0 is moved to cmask and pmask1 is moved to pmask0, and so on. the last is set to "000." if it is used in returning from an in terrupt process, be sure to set to "0" before executing the eret instruction. always reads "0." table 6.8.7 interrupt level register 7 6 5 4 3 2 1 0 ilev bit symbol D pmask0 D cmask (0xffff_e10c) read/write r r/w after reset 0 000 0 000 function interrupt mask level (previous) 0 interrupt mask level (current) 15 14 13 12 11 10 9 8 bit symbol D pmask2 D pmask1 read/write r after reset 0 000 0 000 function interrupt mask level (previous) 2 interrupt mask level (previous) 1 23 22 21 20 19 18 17 16 bit symbol D pmask4 D pmask3 read/write r after reset 0 000 0 000 function interrupt mask level (previous) 4 interrupt mask level (previous) 3 31 30 29 28 27 26 25 24 bit symbol mlev pmask6 D pmask5 read/write w r after reset 0 000 0 000 function 0: return mask level 1: change cmask interrupt mask level (previous) 6 interrupt mask level (previous) 5 (note 1) this register must be 32-bit accessed. (note 2) be sure to read the ivr value before changing the ilev value. if the ilev value is changed before reading ivr, an unexpected interrupt request may be generated. (note 3) bit manipulation instructions cannot be used to access this register. pmask6 pmask5 pmask4 pmask3 pmask2 pmask1 pmask0 cmask pmask6 pmask5 pmask4 pmask3 pmask2 pmask1 pmask0 cmask pmask6 pmask5 pmask4 pmask3 pmask2 pmask1 pmask0 cmask new interrupt level "000" =0 interrupt generation
tmp19a43 tmp19a43 (rev2.0) 6-28 exceptions/interrupts 6.8.8.4 interrupt mode control registers (imcxx) imcxx is comprised of , which determines the interrupt levels of individual interrupt factors, , which is used to set activation factors of dma transfer, and , which determines active state of interrupt requests. 7 6 5 4 3 2 1 0 imc0 bit symbol eim01 eim00 dm0 il02 il01 il00 (0xffff_e000) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request: 00: "l" level 01: disable 10: disable 11: disable be sure to set "00." set as dmac activation factor. 0: non- activation factor 1: interrupt number 0 is set as the activation factor always reads "0." if dm0 = 0, select the interrupt level for interrupt number 0 (software set). 000: disable interrupt 001 to 111: 1 to 7 if dm0 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim11 eim10 dm1 il12 il11 il10 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge standby setting ?01? set as dmac activation factor. 0: non- activation factor 1: interrupt number 1 to be the activation factor. always reads "0." if dm1 = 0, select the interrupt level for interrupt number 1 (int0). 000: disable interrupt 001 to 111: 1 to 7 if dm1 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim21 eim20 dm2 il22 il21 il20 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge standby setting ?01? set as dmac activation factor. 0: non- activation factor 1: interrupt number 2 to be the activation factor. always reads "0." if dm2 = 0, select the interrupt level for interrupt number 2 (int1). 000: disable interrupt 001 to 111: 1 to 7 if dm2 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim31 eim30 dm3 il32 il31 il30 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge standby setting ?01? set as dmac activation factor. 0: non- activation factor 1: interrupt number 3 to be the activation factor. always reads "0." if dm3 = 0, select the interrupt level for interrupt number 3 (int2). 000: disable interrupt 001 to 111: 1 to 7 if dm3 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7
tmp19a43 tmp19a43 (rev2.0) 6-29 exceptions/interrupts 7 6 5 4 3 2 1 0 imc1 bit symbol eim41 eim40 dm4 il42 il41 il40 (0xffff_e004) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge standby setting ?01? set as dmac activation factor. 0: non- activation factor 1: interrupt number 4 is set as the activation factor always reads "0." if dm4 = 0, select the interrupt level for interrupt number 4 (int3) 000: disable interrupt 001 to 111: 1 to 7 if dm4 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim51 eim50 dm5 il52 il51 il50 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge standby setting ?01? set as dmac activation factor. 0: non- activation factor 1: interrupt number 5 to be the activation factor. always reads "0." if dm5 = 0, select the interrupt level for interrupt number 5 (int4). 000: disable interrupt 001 to 111: 1 to 7 if dm5 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim61 eim60 dm6 il62 il61 il60 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge standby setting ?01? set as dmac activation factor. 0: non- activation factor 1: interrupt number 6 to be the activation factor. always reads "0." if dm6 = 0, select the interrupt level for interrupt number 6 (int5). 000: disable interrupt 001 to 111: 1 to 7 if dm6 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim71 eim70 dm7 il72 il71 il70 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge standby setting ?01? set as dmac activation factor. 0: non- activation factor 1: interrupt number 7 to be the activation factor. always reads "0." if dm7 = 0, select the interrupt level for interrupt number 7 (int6). 000: disable interrupt 001 to 111: 1 to 7 if dm7 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7
tmp19a43 tmp19a43 (rev2.0) 6-30 exceptions/interrupts 7 6 5 4 3 2 1 0 imc2 bit symbol eim81 eim80 dm8 il82 il81 il80 (0xffff_e008) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge standby setting ?01? set as dmac activation factor. 0: non- activation factor 1: interrupt number 8 is set as the activation factor always reads "0." if dm8 = 0, select the interrupt level for interrupt number 8 (int7). 000: disable interrupt 001 to 111: 1 to 7 if dm8 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim91 eim90 dm9 il92 il91 il90 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge standby setting ?01? set as dmac activation factor. 0: non- activation factor 1: interrupt number 9 to be the activation factor. always reads "0." if dm9 = 0, select the interrupt level for interrupt number 9 (int8). 000: disable interrupt 001 to 111: 1 to 7 if dm9 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eima1 eima0 dma ila2 ila1 ila0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge standby setting ?01? set as dmac activation factor. 0: non- activation factor 1: interrupt number 10 to be the activation factor. always reads "0." if dma = 0, select the interrupt level for interrupt number 10 (int9). 000: disable interrupt 001 to 111: 1 to 7 if dma = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eimb1 eimb0 dmb ilb2 ilb1 ilb0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge standby setting ?01? set as dmac activation factor. 0: non- activation factor 1: interrupt number 11 to be the activation factor. always reads "0." if dmb = 0, select the interrupt level for interrupt number 11 (inta) 000: disable interrupt 001 to 111: 1 to 7 if dmb = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7
tmp19a43 tmp19a43 (rev2.0) 6-31 exceptions/interrupts 7 6 5 4 3 2 1 0 imc3 bit symbol eimc1 eimc0 dmc ilc2 ilc1 ilc0 (0xffff_e00c) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge standby setting ?01? set as dmac activation factor. 0: non- activation factor 1: interrupt number 12 is set as the activation factor always reads "0." if dmc = 0, select the interrupt level for interrupt number 12 (intb) 000: disable interrupt 001 to 111: 1 to 7 if dmc = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eimd1 eimd0 dmd ild2 ild1 ild0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge set as dmac activation factor. 0: non- activation factor 1: interrupt number 13 to be the activation factor. always reads "0." if dmd = 0, select the interrupt level for interrupt number 13 (intc) 000: disable interrupt 001 to 111: 1 to 7 if dmd = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eime1 eime0 dme ile2 ile1 ile0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge set as dmac activation factor. 0: non- activation factor 1: interrupt number 14 to be the activation factor. always reads "0." if dme = 0, select the interrupt level for interrupt number 14 (intd) 000: disable interrupt 001 to 111: 1 to 7 if dme = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eimf1 eimf0 dmf ilf2 ilf1 ilf0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge set as dmac activation factor. 0: non- activation factor 1: interrupt number 15 to be the activation factor. always reads "0." if dmf = 0, select the interrupt level for interrupt number 15 (inte) 000: disable interrupt 001 to 111: 1 to 7 if dmf = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7
tmp19a43 tmp19a43 (rev2.0) 6-32 exceptions/interrupts 7 6 5 4 3 2 1 0 imc4 bit symbol eim101 eim100 dm10 il102 il101 il100 (0xffff_e010) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge set as dmac activation factor. 0: non- activation factor 1: interrupt number 16 is set as the activation factor always reads "0." if dm10 = 0, select the interrupt level for interrupt number 16 (intf) 000: disable interrupt 001 to 111: 1 to 7 if dm10 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim111 eim110 dm11 il112 il111 il110 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 01: "h" level be sure to set "01." set as dmac activation factor. 0: non- activation factor 1: interrupt number 17 to be the activation factor. always reads "0." if dm11 = 0, select the interrupt level for interrupt number 17 (kwup) 000: disable interrupt 001 to 111: 1 to 7 if dm11 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim121 eim120 dm12 il122 il121 il120 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 18 to be the activation factor. always reads "0." if dm12 = 0, select the interrupt level for interrupt number 18 (intrx0). 000: disable interrupt 001 to 111: 1 to 7 if dm12 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim131 eim130 dm13 il132 il131 il130 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 19 to be the activation factor. always reads "0." if dm13 = 0, select the interrupt level for interrupt number 19 (inttx0) 000: disable interrupt 001 to 111: 1 to 7 if dm13 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use.
tmp19a43 tmp19a43 (rev2.0) 6-33 exceptions/interrupts 7 6 5 4 3 2 1 0 imc5 bit symbol eim141 eim140 dm14 il142 il141 il140 (0xffff_e014) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 20 is set as the activation factor always reads "0." if dm14 = 0, select the interrupt level for interrupt number 20 (intrx1). 000: disable interrupt 001 to 111: 1 to 7 if dm14 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim151 eim150 dm15 il152 il151 il150 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 21 to be the activation factor. always reads "0." if dm15 = 0, select the interrupt level for interrupt number 21 (inttx1) 000: disable interrupt 001 to 111: 1 to 7 if dm15 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim161 eim160 dm16 il162 il161 il160 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 22 to be the activation factor. always reads "0." if dm16 = 0, select the interrupt level for interrupt number 22 (intrx2). 000: disable interrupt 001 to 111: 1 to 7 if dm16 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim171 eim170 dm17 il172 il171 il170 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 23 to be the activation factor. always reads "0." if dm17 = 0, select the interrupt level for interrupt number 23 (inttx2). 000: disable interrupt 001 to 111: 1 to 7 if dm17 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use.
tmp19a43 tmp19a43 (rev2.0) 6-34 exceptions/interrupts 7 6 5 4 3 2 1 0 imc6 bit symbol eim181 eim180 dm18 il182 il181 il180 (0xffff_e018) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 24 is set as the activation factor always reads "0." if dm18 = 0, select the interrupt level for interrupt number 24 (intrx3). 000: disable interrupt 001 to 111: 1 to 7 if dm18 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim191 eim190 dm19 il192 il191 il190 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 25 to be the activation factor. always reads "0." if dm19 = 0, select the interrupt level for interrupt number 25 (inttx3). 000: disable interrupt 001 to 111: 1 to 7 if dm19 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim1a1 eim1a0 dm1a il1a2 il1a1 il1a0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 26 to be the activation factor. always reads "0." if dm1a = 0, select the interrupt level for interrupt number 26 (intrx4). 000: disable interrupt 001 to 111: 1 to 7 if dm1a = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim1b1 eim1b0 dm1b il1b2 il1b1 il1b0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 27 to be the activation factor. always reads "0." if dm1b = 0, select the interrupt level for interrupt number 27 (inttx4). 000: disable interrupt 001 to 111: 1 to 7 if dm1b = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use.
tmp19a43 tmp19a43 (rev2.0) 6-35 exceptions/interrupts 7 6 5 4 3 2 1 0 imc7 bit symbol eim1c1 eim1c0 dm1c il1c2 il1c1 il1c0 (0xffff_e01c) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 28 to be the activation factor. always reads "0." if dm1c = 0, select the interrupt level for interrupt number 28 (intrx5). 000: disable interrupt 001 to 111: 1 to 7 if dm1c = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim1d1 eim1d0 dm1d il1d2 il1d1 il1d0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 29 to be the activation factor. always reads "0." if dm1d = 0, select the interrupt level for interrupt number 29 (inttx5). 000: disable interrupt 001 to 111: 1 to 7 if dm1d = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim1e1 eim1e0 dm1e il1e2 il1e1 il1e0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 30 to be the activation factor. always reads "0." if dm1e = 0, select the interrupt level for interrupt number 30 (ints0). 000: disable interrupt 001 to 111: 1 to 7 if dm1e = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim1f1 eim1f0 dm1f il1f2 il1f1 il1f0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 31 to be the activation factor. always reads "0." if dm1f = 0, select the interrupt level for interrupt number 31 (intadhp) 000: disable interrupt 001 to 111: 1 to 7 if dm1f = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use.
tmp19a43 tmp19a43 (rev2.0) 6-36 exceptions/interrupts 7 6 5 4 3 2 1 0 imc8 bit symbol eim201 eim200 dm20 il202 il201 il200 (0xffff_e020) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 32 to be the activation factor. always reads "0." if dm20 = 0, select the interrupt level for interrupt number 32 (intadm) 000: disable interrupt 001 to 111: 1 to 7 if dm20 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim211 eim210 dm21 il212 il211 il210 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 33 to be the activation factor. always reads "0." if dm21 = 0, select the interrupt level for interrupt number 33 (inttb0). 000: disable interrupt 001 to 111: 1 to 7 if dm21 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim221 eim220 dm26 il222 il221 il220 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 34 to be the activation factor. always reads "0." if dm22 = 0, select the interrupt level for interrupt number 34 (inttb1). 000: disable interrupt 001 to 111: 1 to 7 if dm22 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim231 eim230 dm23 il232 il231 il230 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." standby setting ?01? set as dmac activation factor. 0: non- activation factor 1: interrupt number 35 to be the activation factor. always reads "0." if dm23 = 0, select the interrupt level for interrupt number 35 (inttb2) 000: disable interrupt 001 to 111: 1 to 7 if dm23 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use.
tmp19a43 tmp19a43 (rev2.0) 6-37 exceptions/interrupts 7 6 5 4 3 2 1 0 imc9 bit symbol eim241 eim240 dm24 il242 il241 il240 (0xffff_e024) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." standby setting ?01? set as dmac activation factor. 0: non- activation factor 1: interrupt number 36 to be the activation factor. always reads "0." if dm24 = 0, select the interrupt level for interrupt number 36 (inttb3). 000: disable interrupt 001 to 111: 1 to 7 if dm24 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim251 eim250 dm25 il252 il251 il250 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 37 to be the activation factor. always reads "0." if dm25 = 0, select the interrupt level for interrupt number 37 (inttb4). 000: disable interrupt 001 to 111: 1 to 7 if dm25 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim261 eim260 dm26 il262 il261 il260 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 38 to be the activation factor. always reads "0." if dm26 = 0, select the interrupt level for interrupt number 38 (inttb5). 000: disable interrupt 001 to 111: 1 to 7 if dm26 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim271 eim270 dm27 il272 il271 il270 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 39 to be the activation factor. always reads "0." if dm27 = 0, select the interrupt level for interrupt number 39 (inttb6). 000: disable interrupt 001 to 111: 1 to 7 if dm27 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use.
tmp19a43 tmp19a43 (rev2.0) 6-38 exceptions/interrupts 7 6 5 4 3 2 1 0 imca bit symbol eim281 eim280 dm28 il282 il281 il280 (0xffff_e028) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 40 to be the activation factor. always reads "0." if dm28 = 0, select the interrupt level for interrupt number 40 (inttb7). 000: disable interrupt 001 to 111: 1 to 7 if dm28 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim291 eim290 dm29 il292 il291 il290 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 41 to be the activation factor. always reads "0." if dm29 = 0, select the interrupt level for interrupt number 41 (inttb8). 000: disable interrupt 001 to 111: 1 to 7 if dm29 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim2a1 eim2a0 dm2a il2a2 il2a1 il2a0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 42 to be the activation factor. always reads "0." if dm2a = 0, select the interrupt level for interrupt number 42 (inttb9). 000: disable interrupt 001 to 111: 1 to 7 if dm2a = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim2b1 eim2b0 dm2b il2b2 il2b1 il2b0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 43 to be the activation factor. always reads "0." if dm2b = 0, select the interrupt level for interrupt number 43 (inttba). 000: disable interrupt 001 to 111: 1 to 7 if dm2b = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use.
tmp19a43 tmp19a43 (rev2.0) 6-39 exceptions/interrupts 7 6 5 4 3 2 1 0 imcb bit symbol eim2c1 eim2c0 dm2c il2c2 il2c1 il2c0 (0xffff_e02c) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 44 to be the activation factor. always reads "0." if dm2c = 0, select the interrupt level for interrupt number 44 (inttbb). 000: disable interrupt 001 to 111: 1 to 7 if dm2c = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim2d1 eim2d0 dm2d il2d2 il2d1 il2d0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 45 to be the activation factor. always reads "0." if dm2d = 0, select the interrupt level for interrupt number 45 (inttbc). 000: disable interrupt 001 to 111: 1 to 7 if dm2d = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim2e1 eim2e0 dm2e il2e2 il2e1 il2e0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 46 to be the activation factor. always reads "0." if dm2e = 0, select the interrupt level for interrupt number 46 (inttbd). 000: disable interrupt 001 to 111: 1 to 7 if dm2e = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim2f1 eim2f0 dm2f il2f2 il2f1 il2f0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 47 to be the activation factor. always reads "0." if dm2f = 0, select the interrupt level for interrupt number 47 (inttbe). 000: disable interrupt 001 to 111: 1 to 7 if dm2f = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use.
tmp19a43 tmp19a43 (rev2.0) 6-40 exceptions/interrupts 7 6 5 4 3 2 1 0 imcc bit symbol eim301 eim300 dm30 il302 il301 il300 (0xffff_e030) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 48 to be the activation factor. always reads "0." if dm30 = 0, select the interrupt level for interrupt number 48 (inttbf). 000: disable interrupt 001 to 111: 1 to 7 if dm30 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim311 eim310 dm31 il312 il311 il310 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 1: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 49 to be the activation factor. always reads "0." if dm31 = 0, select the interrupt level for interrupt number 49 (intcapg0) 000: disable interrupt 001 to 111: 1 to 7 if dm31 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol read/write r after reset 0 0 0 0 0 0 0 0 function always reads "0." 31 30 29 28 27 26 25 24 bit symbol eim331 eim330 dm33 il332 il331 il330 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 51 to be the activation factor. always reads "0." if dm33 = 0, select the interrupt level for interrupt number 51 (intcmp0) 000: disable interrupt 001 to 111: 1 to 7 if dm33 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use.
tmp19a43 tmp19a43 (rev2.0) 6-41 exceptions/interrupts 7 6 5 4 3 2 1 0 imcd bit symbol eim341 eim340 dm34 il342 il341 il340 (0xffff_e034) read/write r r/w r r/w after reset 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 52 to be the activation factor. always reads "0." if dm34 = 0, select the interrupt level for interrupt number 52 (intcmp1) 000: disable interrupt 001 to 111: 1 to 7 if dm34 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim351 eim350 dm35 il352 il351 il350 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 53 to be the activation factor. always reads "0." if dm35 = 0, select the interrupt level for interrupt number 53 (intcmp2) 000: disable interrupt 001 to 111: 1 to 7 if dm35 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim361 eim360 dm36 il362 il361 il360 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 54 to be the activation factor. always reads "0." if dm36 = 0, select the interrupt level for interrupt number 54 (intcmp3) 000: disable interrupt 001 to 111: 1 to 7 if dm36 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim371 eim370 dm37 il372 il371 il370 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 55 to be the activation factor. always reads "0." if dm37 = 0, select the interrupt level for interrupt number 55 (intcmp4) 000: disable interrupt 001 to 111: 1 to 7 if dm37 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use.
tmp19a43 tmp19a43 (rev2.0) 6-42 exceptions/interrupts 7 6 5 4 3 2 1 0 imce bit symbol eim381 eim380 dm38 il382 il381 il380 (0xffff_e038) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt requet. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 56 to be the activation factor. always reads "0." if dm38 = 0, select the interrupt level for interrupt number 56 (intcmp5) 000: disable interrupt 001 to 111: 1 to 7 if dm38 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim391 eim390 dm39 il392 il391 il390 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 57 to be the activation factor. always reads "0." if dm39 = 0, select the interrupt level for interrupt number 57 (intcmp6) 000: disable interrupt 001 to 111: 1 to 7 if dm39 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim3a1 eim3a0 dm3a il3a2 il3a1 il3a0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 58 to be the activation factor. always reads "0." if dm3a = 0, select the interrupt level for interrupt number 58 (intcmp7) 000: disable interrupt 001 to 111: 1 to 7 if dm3a = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim3b1 eim3b0 dm3b il3b2 il3b1 il3b0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 10: falling edge be sure to set "10." set as dmac activation factor. 0: non- activation factor 1: interrupt number 59 to be the activation factor. always reads "0." if dm3b = 0, select the interrupt level for interrupt number 59 (inttbt). 000: disable interrupt 001 to 111: 1 to 7 if dm3b = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use.
tmp19a43 tmp19a43 (rev2.0) 6-43 exceptions/interrupts 7 6 5 4 3 2 1 0 imcf bit symbol eim3c1 eim3c0 dm3c il3c2 il3c1 il3c0 (0xffff_e03c) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 10: falling edge be sure to set "10." standby setting ?01? set as dmac activation factor. 0: non- activation factor 1: interrupt number 60 to be the activation factor. always reads "0." if dm3c = 0, select the interrupt level for interrupt number 60 (intrtc) 000: disable interrupt 001 to 111: 1 to 7 if dm3c = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim3d1 eim3d0 dm3d il3d2 il3d1 il3d0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 61 to be the activation factor. always reads "0." if dm3d = 0, select the interrupt level for interrupt number 61 (intad) 000: disable interrupt 001 to 111: 1 to 7 if dm3d = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim3e1 eim3e0 dm3e il3e2 il3e1 il3e0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level be sure to set "00.". set as dmac activation factor. 0: non- activation factor 1: interrupt number 62 to be the activation factor. always reads "0." if dm3e = 0, select the interrupt level for interrupt number 62 (intdma0-3). 000: disable interrupt 001 to 111: 1 to 7 if dm3e = 1, select the dmac channel. 000 to 011:--- 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim3f1 eim3f0 dm3f il3f2 il3f1 il3f0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level be sure to set "00." set as dmac activation factor. 0: non- activation factor 1: interrupt number 63 to be the activation factor. always reads "0." if dm3f = 0, select the interrupt level for interrupt number 63 (intdma4-7). 000: disable interrupt 001 to 111: 1 to 7 if dm3f = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: --- note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use. the access to the dmac register by dmac is a prohibition.
tmp19a43 tmp19a43 (rev2.0) 6-44 exceptions/interrupts note 1: please ensure that the type of active state is selected before enabling an interrupt request. note 2: when making interrupt requests dmac activation factors, please ensure that you put the dmac into standby mode after setting the intc. note 3: when you change an active conditi on (when changing to the level detection)please change after putting the interrupt output of t he corresponding device into t he state of deasart. (1) don ? t il="0 setting il="0" (2) change detection condition (eim) (3) intclr pertinent interrupt is clear. (4) il it sets it to "excluding 0". 6.8.8.5 interrupt request clear registers (intclr) when it is desired to clear any interrupt request being suspended, you can do so by setting the ivr [7:0] for the corresponding interrupt factor into the intclr register. when an interrupt request is cleared, the ivr value is also cleared and the interrupt factor cannot be determined anymore. do not clear an interrupt request before reading the ivr value. table 6.8.8 set the ivr value that corresponds to the interrupt request that you would like to clear 7 6 5 4 3 2 1 0 intclr bit symbol eiclr7 eiclr6 eiclr5 eiclr4 eiclr3 eiclr2 eiclr1 eiclr0 (0xffff_e060) read/write r/w after reset 0 0 0 0 0 0 0 0 function set the ivr value that corresponds to the interrupt request that you would like to clear. 15 14 13 12 11 10 9 8 bit symbol read/write r after reset 0 function always reads "0." 23 22 21 20 19 18 17 16 bit symbol read/write r after reset 0 function always reads "0." 31 30 29 28 27 26 25 24 bit symbol read/write r after reset 0 function always reads "0." (note 1) this register must be 16-bit accessed. (note 2) in order to maintain interrupt factors regard less of the active state setting of intc imcx , i.e., either "h" level, "l" level, rising edge, or falling edge, clear the interrupt request. (note 3) bit manipulation instructions cannot be used to access this register. (note 4) external transfer requests due to dmac interr upt factors are not clear ed. once an external transfer request is accepted, it will not be canceled until the dma transfer is executed. therefore, any unnecessary exte rnal transfer request should be cleared by executing dma transfer. otherwise, such an unnecessary extern al transfer request should not be accepted by disabling interrupts using imcx or by canceling the corresponding dmac activation factors using imcx before acceptin g such external transfer requests.
tmp19a43 tmp19a43 (rev2.0) 6-45 exceptions/interrupts fig. 6-6 interrupt connection diagram set h/l level both edges or edge intnen standby clear control 16 detection circuit "h" level 1647 active h level 16 kwup int0-b 12 kwup0-31 1 cg other interrupts intc core 163 set h/l level or edge input enable/disable for each interrupt factor kwup status register imcxx register imcgxx register kwup0-31 register rising edge 2 1 rising edge wdt write bus error 2 rtc inttb2,3
tmp19a43 tmp19a43 (rev2.0) 6-46 exceptions/interrupts 6.9 intcg registers (interrupts to clear stop, sleep, and idle) int0 to intb, kwup0 to 31 (interrupts to clear stop, sleep, and idle modes) intrtc, inttb2, 3 (two-phase pulse input counter): sleep 7 6 5 4 3 2 1 0 imcga bit symbol emcg02 emcg 01 emcg00 emst01 emst00 int0en (0xffff_ee10) read/write r r/w r r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." set active state of int0 standby clear request. 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges active status of int0 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edges always reads "0." int0 clear input 0: disable 1: enable 15 14 13 12 11 10 9 8 bit symbol emcg12 emcg11 emcg10 emst11 emst10 int1en read/write r r/w r r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." set active state of int1 standby clear request. 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges active status of int1 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edges always reads "0." int1 clear input 0: disable 1: enable 23 22 21 20 19 18 17 16 bit symbol emcg22 emcg21 emcg20 emst21 emst20 int2en read/write r r/w r r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." set active state of int2 standby clear request. 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges active status of int2 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edges always reads "0." int2 clear input 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol emcg32 emcg31 emcg30 emst31 emst30 int3en read/write r r/w r r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." set active state of int3 standby clear request. 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges active status of int3 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edges always reads "0." int3 clear input 0: disable 1: enable
tmp19a43 tmp19a43 (rev2.0) 6-47 exceptions/interrupts 7 6 5 4 3 2 1 0 imcgb bit symbol emcg42 emcg 41 emcg40 emst41 emst40 int4en (0xffff_ee14) read/write r r/w r r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." set active state of int4 standby clear request. 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges active status of int4 standby clear request 00 ? 01: rising edge 10: falling edge 11: both edges always reads "0." int4 clear input 0: disable 1: enable 15 14 13 12 11 10 9 8 bit symbol emcg52 emcg51 emcg50 emst51 emst50 int5en read/write r r/w r r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." set active state of int5 standby clear request. 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges active status of int5 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edges always reads "0." int5 clear input 0: disable 1: enable 23 22 21 20 19 18 17 16 bit symbol emcg62 emcg61 emcg60 emst61 emst60 int6en read/write r r/w r r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." set active state of int6 standby clear request. 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges active status of int6 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edges always reads "0." int6 clear input 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol emcg72 emcg71 emcg70 emst71 emst70 int7en read/write r r/w r r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." set active state of int7 standby clear request. 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges active status of int7 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edges always reads "0." int7 clear input 0: disable 1: enable
tmp19a43 tmp19a43 (rev2.0) 6-48 exceptions/interrupts 7 6 5 4 3 2 1 0 imcgc bit symbol emcg82 emcg 81 emcg80 emst81 emst80 int8en (0xffff_ee18) read/write r r/w r r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." set active state of int8 standby clear request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge 100: both edges active status of int8 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edges always reads "0." int8 clear input 0: disable 1: enable 15 14 13 12 11 10 9 8 bit symbol emcg92 emcg91 emcg90 emst91 emst90 int9en read/write r r/w r r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." set active state of int9 standby clear request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge 100: both edges active status of int9 standby clear request 00: ? 01: rising edge 10: falling edge 11: both edges always reads "0." int9 clear input 0: disable 1: enable 23 22 21 20 19 18 17 16 bit symbol emcga2 emcga1 emcga0 emsta1 emsta0 intaen read/write r r/w r r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." set active state of inta standby clear request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge 100: both edges active status of inta standby clear request 00: ? 01: rising edge 10: falling edge 11: both edges always reads "0." int9 clear input 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol emcgb2 emcgb1 emcgb0 emstb1 emstb0 intben read/write r r/w r r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." set active state of intb standby clear request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge 100: both edges active status of intb standby clear request 00: ? 01: rising edge 10: falling edge 11: both edges always reads "0." intb clear input 0: disable 1: enable
tmp19a43 tmp19a43 (rev2.0) 6-49 exceptions/interrupts 7 6 5 4 3 2 1 0 imcgd bit symbol emcgc1 emcgc0 kwupen (0xffff_ee1c) read/write r r/w r/w r r/w after reset 0 0 1 0 D 0 function always reads "0." be sure to write "0." set active state of kwup standby clear request. 01: "h" level be sure to set "01." the lead value is irregular. always reads "0." kwup clear input 0: disable 1: enable 15 14 13 12 11 10 9 8 bit symbol emcgd1 emcgd0 intrtce n read/write r r/w r/w r r/w after reset 0 0 1 0 D 0 function always reads "0." be sure to write "0." set active state of intrtc standby clear request. 10: falling edge be sure to set "10." the lead value is irregular. always reads "0." intrtc clear input 0: disable 1: enable 23 22 21 20 19 18 17 16 bit symbol emcge1 emcge0 inttb2e n read/write r r/w r/w r r/w after reset 0 0 1 0 D 0 function always reads "0." be sure to write "0." set active state of inttb2 standby clear request. 11: rising edge be sure to set "11." the lead value is irregular. always reads "0." inttb2 clear input 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol emcgf1 emcgf0 inttb3e n read/write r r/w r/w r r/w after reset 0 0 1 0 D 0 function always reads "0." be sure to write "0." set active state of inttb3 standby clear request. 11: rising edge be sure to set "11." the lead value is irregular. always reads "0." inttb3 clear input 0: disable 1: enable note: default values of emcgx0 and emcgx1 are different from the values to be used. properly set them to the specified values before use.
tmp19a43 tmp19a43 (rev2.0) 6-50 exceptions/interrupts be sure to set active state of the clear request if interrupt is enabled for clearing the stop, sleep, or idle standby mode. (note1) when using interrupts, be sure to follow the following sequence of action: c if shared with other general ports, enable the target interrupt input. d set active state, etc., upon initialization. e clear interrupt requests. f enable interrupts (note 2) settings must be performed while interrupts are disabled. (note 3) for clearing the stop and sleep modes with tmp19a43, 16 factors, i.e., int0 to intb, intrtc, inttb2/inttb3, and kwup00 to 31 are available as clearing interrupts. whether or not int0 to intb are to be used as clearing interrupts as well as active state edge/level selection is set with cg. whether or not kwup00 to 31 are to be used as stop/sleep/idle clearing interrupts is set with cg and active state edge/level selection is set with kwupstn . set to high level with intc for the above 16 factors. (note 4) among the above 16 factors to be assigned as stop/sleep/idle clear request interrupts, int0 to intb don't have to be set with cg if they are to be used as normal interrupts. use intc to specify either h/l le vel, rising/falling edge, or both edges. if kwup00 to 31 are to be used as normal interrupts, set the active level by kwupstn and set high level with intc. no cg setting is necessary. also, if intrtc is to be used as a normal interrupt, use cg/intc for the setting. interrupt factors other than those assigned as stop/sleep/idle clear requests are set in the intc block.
tmp19a43 tmp19a43 (rev2.0) 6-51 exceptions/interrupts 7 6 5 4 3 2 1 0 eicrcg bit symbol icrcg3 icrcg2 icrcg1 icrcg0 (0xffff_ee20) read/write r r/w after reset 0 0 function always reads "0." always reads "0." clear interrupt requests. 0000: int0 0101: int5 1010: inta 0001: int1 0110: int6 1011: intb 0010: int2 0111: int7 1100: kwup 0011: int3 1000: int8 1101: intrc 0100: int4 1001: int9 1110: inttb2 1111:inttb3 15 14 13 12 11 10 9 8 bit symbol read/write r after reset 0 function always reads "0." 23 22 21 20 19 18 17 16 bit symbol read/write after reset function always reads "0." 31 30 29 28 27 26 25 24 bit symbol read/write r after reset 0 function always reads "0." (note) to clear interrupt request of the above 16 factors that are assigned to clear stop/sleep/idle modes, c for kwup, use kwupclr d for int0 to intb, ,intrtc,inttb2,inttb3 use the eircg register in the above cg block.
tmp19a43 tmp19a43 (rev2.0) 6-52 exceptions/interrupts 6.10 nmi flag register nmiflg 7 6 5 4 3 2 1 0 (0xffff_ee24) bit symbol wdt wber read/write r after reset 0 0 0 0 0 0 0 0 function always reads "0." nmi factor 1: nmi generated by wdt interrupt nmi factor 1: nmi generated by write bus error 15 14 13 12 11 10 9 8 bit symbol read/write r after reset 0 0 0 0 0 0 0 0 function always reads "0." 23 22 21 20 19 18 17 16 bit symbol read/write r after reset 0 0 0 0 0 0 0 0 function always reads "0." 31 30 29 28 27 26 25 24 bit symbol read/write r after reset 0 0 0 0 0 0 0 0 function always reads "0." ? wdt and wber are cleared to "0" when they are read. although tmp19a43 doesn't have nmi interrupts as external pin inputs, nmi interrupts are available as internal interrupt factors.
tmp19a43 tmp19a43 (rev2.0) 6-53 exceptions/interrupts 6.11 cautions in using interrupts the following paragraphs describe some points to be kept in mind in using interrupts. user programs must be written in a manner to satisfy the following details. 6.11.1 cautions related to tx19a processor core ? exceptions cannot be disabled. note that there are some cases where two different instructions can be distinguished only by exception generatio n. so, properly use them according to the specific usage. ? software interrupts are different from the "software set" to be used as one of hardware interrupt factors. ? immediately after overwriting sscr of the cp0 register, add two nop instructions to allow for register bank switching as it takes two clock cycles. ? in case multiple interrupts of the same interrupt level are accepted by changing ilev , it is necessary for the user program to save b ecause the register bank will not be switched. ? only 32-bit isa access can be used to access ier of the cp0 register. ? different stack pointers (r29) are used for shadow register set number 0 and shadow register set numbers 1 to 7; it is necessary to set them se parately (twice). if it is desired to use a common stack pointer, you can do so by setting sscr to "1" in the main process to use shadow register set number 1. in this case, when a level 1 interrupt is accepted, it is necessary for the user program to save because the register bank will not be switched. ? if an eret instruction is executed while interrupts are disabled by setting status of the cp0 register to "1," it returns to the main proces s by using errorepc of the cp0 register as the return address. as the tx19a processor core sa ves the interrupt return address to epc, you should be careful if status is to be used for disabling interrupts. ? don't execute an eret instructio n within two clock cycles after accessing status, errorepc, epc, or sscr of the cp0 register. ? if status of the cp0 register is set to disable interrupts, interrupts are disabled at the time of instruction execution (e stage) but any value set to the register is reflected only two clocks later. ? if status of the cp 0 register is set to enable interrupts, interrupts are enabled two clocks after the instruction execution (e stage); any value set to the register is also reflected two clocks after the instruction execution (e stage).
tmp19a43 tmp19a43 (rev2.0) 6-54 exceptions/interrupts 6.11.2 cautions related to intc ? if more than one interrupts of a same interrupt le vel are generated at the same time, interrupts are accepted from the factor of th e smallest interrupt number. ? any factor of interrupt level 0 is not suspended. ? if it is desired to individually disable interrupt f actors (by setting interrupt level 0), you can do so only while interrupts are disabled. ? default settings of imcx of intc may be different from the settings to be used. ? the intc ilev register must be 32-bit accessed. ? the intc intclr register must be 32-bit accessed. ? when an interrupt request is cleared by intclr before reading intc ivr, the interrupt factor cannot be determined becaus e the ivr value is cleared. ? when enabling interrupts, be sure to do so in the order of the detection route (from external to internal). when disabling, use the reverse order of the detection route (from internal to external). ? when a new value is written to intc ilev , set to "1" at the same time.
tmp19a43 tmp19a43 (rev2.0) 7-1 input/output ports 7. input/output ports 7.1 port 0 (p00 through p07) the port 0 is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register p0cr. a reset allows all bits of p0cr to be cleared to "0" and the port 0 to be put in input mode. besides the general-purpose input/output function, the port 0 performs other functions: d0 through d7 function as a data bus and ad0 through ad7 function as an address data bus. when external memory is accessed, the port 0 automatically functions as either a data bus or an address data bus, and all bits of p0cr are cleared to "0." if the busmd pin (port p45) is set to "l" level during a rese t, the port 0 is put in separate bus mode (d0 to d7). if it is set to "h" level during a reset, the port 0 is put in multiplexed mode (ad0 to ad7). fig. 7-1 port 0 (p00 through p07) internal data bus p0cr direction control (in units of bits) p0 ( output latch) p0read port0 p00top07 (d0tod7) (ad0toad7 ) 1 0 external access d0tod7/ ad0toad7 1 0 address/data output 1 0 externa read stop/reset drive disable d0tod7 external bus opening reset p0read pull-up control (in units of bits) p0pe
tmp19a43 tmp19a43 (rev2.0) 7-2 input/output ports port 0 register 7 6 5 4 3 2 1 0 p0 bit symbol p07 p06 p05 p04 p03 p02 p01 p00 (0xffff_f000) read/write r/w after reset input mode (output latch register is cleared to "0.") port 0 control register 7 6 5 4 3 2 1 0 p0cr bit symbol p07c p06c p05c p04c p03c p02c p01c p00c (0xffff_f002) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output (when an external area is accessed, d7-0 or ad7- 0 is used and this register is cleared to "0.") port 0 pull-up control register 7 6 5 4 3 2 1 0 p0pe bit symbol pe07 pe06 pe05 pe04 pe03 pe02 pe01 pe00 (0xffff_f00c) read/write r/w after reset 0 0 0 0 0 0 0 0 function pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up
tmp19a43 tmp19a43 (rev2.0) 7-3 input/output ports 7.2 port 1 (p10 through p17) the port 1 is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register p1cr and the function register p1fc. a reset allows all bits of the output latch p1, p1cr and p1fc to be cleared to "0" and the port 1 to be put in input mode. besides the general-purpose input/output function, the po rt 1 performs other functions: d8 through d15 function as a data bus, ad8 through ad15 function as an addre ss data bus, and a8 through a15 function as an address bus. to access external memory, registers p1cr and p1fc mu st be provisioned to allow the port 1 to function as either an address bus or an address data bus. if the busmd pin (port 45) is set to "l" level during a rese t, the port 1 is put in separate bus mode (d8 to d15). if it is set to "h" level during a reset, the port 1 is put in multiplexed mode (ad8 to ad15 or a8 to a15). fig. 7-2 port 1 (p10 through p17) internal data bus p1read 1 0 a8toa15 1 0 address/data output 1 0 ad8toad15 external bus opening port1 p10top17 (d8tod15) (ad8toad15/a8toa15) 1 0 t b 0 ad8toad15 p1pepull-up control (in units of bits ) p1crdirection control (in units of bits) p1 (output latch) p1fcfunction control (in units of bits) external read p1 access reset stop/reset drive disable
tmp19a43 tmp19a43 (rev2.0) 7-4 input/output ports fig. 7-3 port 1 (p10 through p17) port 1 register 7 6 5 4 3 2 1 0 p1 bit symbol p17 p16 p15 p14 p13 p12 p11 p10 (0xffff_f001) read/write r/w after reset input mode (output latch register is cleared to "0.") port 1 control register 7 6 5 4 3 2 1 0 p1cr bit symbol p17c p16c p15c p14c p13c p12c p11c p10c (0xffff_f004) read/write r/w after reset 0 0 0 0 0 0 0 0 function << see p1fc >> port 1 function register 7 6 5 4 3 2 1 0 p1fc bit symbol p17f p16f p15f p14f p13f p12f p11f p10f (0xffff_f005) read/write r/w after reset 0 0 0 0 0 0 0 0 function p1fc/p1cr = 00: input, 01: output, 10: d15 through 8 or ad15 through 8, 11: a15 through 8 port 1 pull-up control register 7 6 5 4 3 2 1 0 p1pe bit symbol pe17 pe16 pe15 pe14 pe13 pe12 pe11 pe10 (0xffff_f00d) read/write r/w after reset 0 0 0 0 0 0 0 0 function pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up function corresponding bit of p1fc corresponding bit of p1cr port to be used por1 input setting 0 0 port1 por1 output setting 0 1 port1 data bus (d15 through d8) input/output setting 1 0 separate bus mode (busmd="0") address bus (a15 through a8) output setting 1 1 port1 address data bus (ad15 through ad8) input/output setting 1 0 multiplexed bus mode (busmd="1") address bus (a15 through a8) output setting 1 1 port1 table 7-1
tmp19a43 tmp19a43 (rev2.0) 7-5 input/output ports 7.3 port 2 (p20 through p27) the port 2 is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register p2cr and the function register p2fc. a reset allows all bits of the output latch p2 to be set to ?1,? all bits of p2cr and p2fc to be cleared to ?0,? and the port 2 to be put in input mode. the port 2 also performs a 16-bit timer input function. this function is enabled by setting the corresponding bits of p2fc and p2fc2 to ?1? and the corresponding bit of p2cr to ?0.? a reset allows p2cr and p2fc to be cleared to ?0? and the port 2 to function as an input port. besides the general-purpose input/output port function, the port 2 performs another function: a0 through a7 function as one address bus and a16 through a23 function as the other address bus. to access external memory, registers p2cr and p2fc must be provisioned to allow the port 2 to function as an address bus. if the busmd pin (port p45) is set to ?l? level during a re set, the port 2 is put in separate mode (a16 to a23). if it is set to ?h? level during a reset, the port 2 is put in multiplexed mode (a0 through a7 or a16 through a23).
tmp19a43 tmp19a43 (rev2.0) 7-6 input/output ports fig. 7-3 port 2 (p20 through p27) internal data bus p2read 1 0 a16toa23 1 0 1 0 stop/reset drive disable external bus opening 1 0 a0toa7 port2 p20top27 (a16toa23) (a0toa7) (tb0in0,tb0in1) (tb1in0,tb1in1) (tb4in0,tb4in1) (tb5in0,tb5in1) tb0in0,tb0in1 tb1in0,tb1in1 tb4in0,tb4in1 tb5in0,tb5in1 p2pe (pull-up control) p2cr ( direction control ) p2 ( output latch ) p2fc2 ( function control ) reset p2fc ( function control )
tmp19a43 tmp19a43 (rev2.0) 7-7 input/output ports port 2 register 7 6 5 4 3 2 1 0 p2 bit symbol p27 p26 p25 p24 p23 p22 p21 p20 (0xffff_f012) read/write r/w after reset input mode (output latch register is set to ?1.?) port 2 control register 7 6 5 4 3 2 1 0 p2cr bit symbol p27c p26c p25c p24c p23c p22c p21c p20c (0xffff_f014) read/write r/w after reset 0 0 0 0 0 0 0 0 function <> port 2 function register 1 7 6 5 4 3 2 1 0 p2fc bit symbol p27f p26f p25f p24f p23f p22f p21f p20f (0xffff_f015) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0 : port 1 : function 0 : port 1 : function 0 : port 1 : function 0 : port 1 : function 0 : port 1 : function 0 : port 1 : function 0 : port 1 : function 0 : port 1 : function port 2 function register 2 7 6 5 4 3 2 1 0 p2fc2 bit symbol p27f2 p26f2 p25f 2 p24f2 p23f2 p22f2 p21f2 p20f2 (0xffff_f016) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: address 1: tb5in1 0: address 1: tb5in0 0: address 1: tb4in1 0: address 1: tb4in0 0: address 1: tb1in1 0: address 1: tb1in0 0: address 1: tb0in1 0: address 1: tb0in0 port 2 pull-up control register 7 6 5 4 3 2 1 0 p2pe bit symbol pe27 pe26 pe25 pe24 pe23 pe22 pe21 pe20 (0xffff_f01c) read/write r/w after reset 0 0 0 0 0 0 0 0 function pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up function corresponding bit of p2fc corresponding bit of p2fc2 corresponding bit of p2cr port to be used por2 input setting 0 * 0 port2 por2 output setting 0 * 1 port2 address bus (a7 through a0) output setting (*1) 1 0 0 port2 address bus (a23 through a16) output setting (*1) 1 0 1 port2 tmrb input setting 1 1 0 port2 table 7-2 (*1) the same address bus (a7 through a0/a23 through a16) output settings are used in both the separate bus mode and the multip lexed bus mode (busmd="0," "1").
tmp19a43 tmp19a43 (rev2.0) 7-8 input/output ports 7.4 port 3 (p30 through p37) the port 3 is a general-purpose, 8-bit input/output port (p30 and p31 are used exclusively for output). for this port, inputs and outputs can be specified in units of bits by using the control register p3cr and the function register p3fc. a reset allows the output latches p30 and 31 to be set to "1." besides the input/output port function, the port 3 performs other functions: p34 outputs a 16-bit timer, and p35, p36 and p37 perform the 32-bit capture and trigger input function. these functions are enabled by setting the corresponding bit of p3fc to "1." a reset allows p3cr and p3fc to be cleared to "0" and the port 3 to function as an input port. in addition to above functions, a function of inputting and outputting the control and status signals of cpu is provided. if the p30 pin is set to rd signal output mode ( = "1"), the rd strobe is output only when an external address area is accessed. li kewise, if the p31 pin is set to wr signal output mode ( = "1"), the wr strobe is output only when an external address area is accessed. fig. 7-4 port 3 (p30, p31) internal data bus p0read 1 0 1 0 stop drive disable external bus opening p30 ( rd ) p31 ( wr ) rd , wr p3pe (pull-up control) p3fc (function control) p3 ( output latch ) reset
tmp19a43 tmp19a43 (rev2.0) 7-9 input/output ports fig. 7-5 port 3 (p33) internal data bus p3read 1 0 stop/reset drive disable p33 ( wait/rdy ) wait/rd y p3pe (pull-up countrol) p3cr ( direction control ) p3fc ( function control ) p3 ( output latch ) reset 1 0
tmp19a43 tmp19a43 (rev2.0) 7-10 input/output ports internal data bus p3read 1 0 stop/read drive disable p34 busrq p3pe (pull-upcontrol) p3cr ( direction control ) p3fc ( function control ) p3 ( output latch ) reset ( busrq ) (tbeout) tbeout 0 1 fig. 7-6 port 3 (p34)
tmp19a43 tmp19a43 (rev2.0) 7-11 input/output ports internal data bus p3read 1 0 1 0 1 0 stop/reset drive disable external bus opening rese t p3pe (pull-up control) p3cr ( direction control ) p3fc ( function control ) busak p3 ( output latch ) reset p35 ( busak ,tc1in) tc1in fig. 7-7 port 3 (p35)
tmp19a43 tmp19a43 (rev2.0) 7-12 input/output ports internal data bus p read 1 0 stop drive disable p37 p3pe (pull-up control) p3cr direction control p3fc ( function control ) p3 ( output latch ) reset (ale) (tc3in) 1 0 1 0 ale tc3in fig. 7-8 port 3 (p37)
tmp19a43 tmp19a43 (rev2.0) 7-13 input/output ports port 3 register 7 6 5 4 3 2 1 0 p3 bit symbol p37 p36 p35 p34 p33 p32 p31 p30 (0xffff_f018) read/write r/w output mode after reset to be determined according to the bus mode input mode 1 1 port 3 control register 7 6 5 4 3 2 1 0 p3cr bit symbol p37c p36c p35c p34c p33c p32c ? ? (0xffff_f01a) read/write r/w after reset 0 0 0 0 0 0 0 function according to the bus mode 0: input 1: output port 3 function register 1 7 6 5 4 3 2 1 0 p3fc bit symbol p37f p36f p35f p34f p33f p32f p31f p30f (0xffff_f01b) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 0: port 0: port 0: port 0: port/ wait 0: port 0: port 0: port 1: ale/ tc3in 1: w/r 1: busak 1: busrq 1: port/ rdy 1: hwr / tc0in 1: wr 1: rd port 3 pull-up control register 7 6 5 4 3 2 1 0 p3pe bit symbol pe37 pe36 pe35 pe34 pe33 pe32 pe31 pe30 (0xffff_f01d) read/write r/w after reset 0 0 0 0 0 0 0 0 function pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up
tmp19a43 tmp19a43 (rev2.0) 7-14 input/output ports port to be used function corresponding bit of p3fc corresponding bit of p3cr busmd p30/31output setting 0 p30/p31 rd/wroutput setting 1 p32/p36input setting * 0 p32/p36output setting 0 1 tc0in/tc2ininput setting 1 0 p32/p36 hwr/ r/woutput setting 1 1 p33input setting * 0 p33output setting * 1 waitinput setting 0 0 p33 rdyinput setting 1 0 p34input setting * 0 p34output setting 0 1 busrqinput setting 1 0 p34 tbeoutoutput setting 1 1 p35input setting * 0 p35output setting 0 1 tc1in input setting 1 0 p35 busak output setting 1 1 p37input setting * 0 p37output setting 0 1 tc3in input setting 1 0 h p37 ale output setting 1 1 h table 7-3 (*1) in separate bus mode (busmd="0"), ale is not output. the port 3 functions as an input/output port based on the bit setting of the control register p3cr. after a reset, the port becomes an input port. if a reset is executed in multiplexed bus mode (busmd="1"), the port 3 becomes an output port at "l" level. (*2) /rd and /wr are output only when an external area is being accessed.
tmp19a43 tmp19a43 (rev2.0) 7-15 input/output ports 7.5 port 4 (p40 through p47) the port 4 is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register p4cr and the function register p4fc. besides the general-purpose input/output port function, the port 4 performs other functions: p40 through p43 output the chip select signal ( cs0 to cs3 ) and input the key-on wake-up, p44 functions as the scout output pin for outputting internal clocks, and p47 outputs a 16-bit timer. by making necessary settings during a reset, p45 functions as a busmd pin for setting external bus modes, and p46 as an endian setting pin. internal data bus p4read 1 0 1 0 1 0 stop/reset drive disable external bus opening p4pe (pull-up control) p4cr ( direction control ) p4fc ( function control ) p4 ( output latch ) reset system reset key ch24, ch25,ch27 pull-up p40 ( cs0 )key24 p41 ( cs1 )key25 p43 ( cs3 )key27 cs0 , cs1, cs3 key24 key25 key27 fig. 7-9 port 4 (p40 to p43) if the port 4 goes into stop mode when the key input is enabled, inputs are always accepted. to inhibit inputs, switch to po rt using the function register. ? port: inputs are accepted only during a read. ? key: inputs are always accepted.
tmp19a43 tmp19a43 (rev2.0) 7-16 input/output ports internal data bus p4read 1 0 1 0 1 0 stop/reset drive disable external bus opening p4pe (pull-up control) p4cr ( direction control ) p4fc ( function control ) p4 ( output latch ) reset system reset key ch26 pull-up p42 ( cs2 )key26 cs2 key26 fig. 7-10port 4 (p42)
tmp19a43 tmp19a43 (rev2.0) 7-17 input/output ports internal data bus p4read 1 0 1 0 stop/reset drive disable p4pe (pull-up control) p4cr ( direction control ) p4fc ( function control ) p4 ( output latch ) reset p44 (scout) scout fig. 7-11port 4 (p44)
tmp19a43 tmp19a43 (rev2.0) 7-18 input/output ports internal data bus p4 read 1 0 stop/reset drive disable p4pe (pull-up control) p4cr (direction control) p4 (output latch) reset system reset busmd,endian port4 p45,46 (busmd,endian) fig. 7-12 port 4 (p45,46)
tmp19a43 tmp19a43 (rev2.0) 7-19 input/output ports internal data bus p4read 1 0 1 0 stop/reset drive disable p4pe (pull-up control) p4cr ( direction control ) p4fc ( function control ) p4 ( output latch ) reset tbfout p47 (tbeout system reset fig. 7-13 port 4 (p47)
tmp19a43 tmp19a43 (rev2.0) 7-20 input/output ports port 4 register 7 6 5 4 3 2 1 0 p4 bit symbol p47 p46 p45 p44 p43 p42 p41 p40 (0xffff_f01e) read/write r/w after reset input mode (output latch register is set to "1.") port 4 control register 7 6 5 4 3 2 1 0 p4cr bit symbol p47c p46c p45c p44c p43c p42c p41c p40c (0xffff_f020) read/write r/w after reset 0 0 0 0 0 0 0 0 0: input 1: output port 4 function register 7 6 5 4 3 2 1 0 p4fc bit symbol p47f p46f p45f p44f p43f p42f p41f p40f (0xffff_f021) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 0: port 0: port /key27 0: port/ key26 0: port/ key25 0: port/ key24 1: tbfout write 0 write 0 1: scout 1: cs3 /key27 1: cs2 /key26 1: cs1 /key25 1: cs0 /key24 port 4 pull-up control register 7 6 5 4 3 2 1 0 p4pe bit symbol pe47 pe46 pe45 pe44 pe43 pe42 pe41 pe40 (0xffff_f025) read/write r/w after reset 0 0 0 0 0 0 0 0 function pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up
tmp19a43 tmp19a43 (rev2.0) 7-21 input/output ports port to be used function corresponding bit of p4fc corresponding bit of p4cr p40/p41/p43input setting 0 0 p40/p41/p43output setting 0 1 key24/25/27input setting * 0 p40/p41/p43 cs0/cs1/cs3output setting 1 1 p42input setting 0 0 p42output setting 0 1 key26input setting * 0 p42 cs2output setting 1 1 p44input setting * 0 p44output setting 0 1 p44 scout setting 1 1 p45/p46input setting - 0 p45/p46output setting - 1 p45/p46 busmd/endianinput setting - * p47input setting * 0 p47output setting 0 1 p47 tbeoutoutput setting 1 1 table 7-4
tmp19a43 tmp19a43 (rev2.0) 7-22 input/output ports 7.6 port 5 (p50 through p57) the port 5 is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register p5cr and the function register p5fc. a reset allows all bits of the output latch p5 to be set to "1," all bits of p5cr and p5fc to be cleared to "0," and the port 5 to be put in input mode. besides the input/output port function, the port 5 performs other functions: p50 through p53 input external interrupts, p54 through p57 output a 16-bit timer, and p56 and p57 input the key-on wake-up. these functions are enabled by setting the corresponding bit of p5fc to "1." a reset allows p5cr and p5fc to be cleared to "0" and the port 5 to function as an input port. the port 5 also functions as an address bus (a0 thro ugh a7). to access external memory, p5cr and p5fc must be provisioned to allow the port 5 to function as an address bus. this address bus function can be used only in separate bus mode. (to put the port 5 in separate bus mode, the busmd pin (port 45) must be set to "l" level during a reset.)
tmp19a43 tmp19a43 (rev2.0) 7-23 input/output ports internal data bus p5 read 1 0 1 0 1 0 stop/reset drive disable external bus opening p5pe (pull-up) p5cr (direction control) p5fc (function control) p5 (output latch) reset port5 p50top53 (a0toa3) (intctointf) a0to3 intctointf nf (40ns typ) fig. 7-14 port 5 (p50 to p53) if the port 5 goes into stop mode when the int input is enabled, inputs are always accepted. to inhibit inputs, switch to po rt using the function register. ? port: inputs are accepted only during a read. ? int: inputs are always accepted.
tmp19a43 tmp19a43 (rev2.0) 7-24 input/output ports internal data bus p5 read 1 0 1 0 1 0 stop/reset drive disable external bus opening p5pe (pull-up) p5cr (direction control) p5 ( output latch p5fc2 (function control) reset p5fc (function control) 1 0 tb0out, tb1out a4to5 port5 p54top55 (a4toa5) ( tb0out,tb1out) fig. 7-15 port 5 (p54 and p55)
tmp19a43 tmp19a43 (rev2.0) 7-25 input/output ports internal data bus p5 read 1 0 1 0 1 0 stop/reset drive disable external bus opening p5pe (pull-up control) p5cr (direction control) p5 (output latch) p5fc2 (function control) reset p5fc (function control) 1 0 nf (40ns typ) port5 p56top57(a6toa7, tb2out,tb3out key2 8, 2 9 ) a6,7 tb2out, tb3out key28, key29 key ch28,ch29 pull-up fig. 7-16 port 5 (p56 to p57) if the port 5 goes into stop mode when the key input is enabled, inputs are always accepted. to inhibit inputs, switch to po rt using the function register. ? port: inputs are accepted only during a read. ? key: inputs are always accepted.
tmp19a43 tmp19a43 (rev2.0) 7-26 input/output ports port 5 register 7 6 5 4 3 2 1 0 p5 bit symbol p57 p56 p55 p54 p53 p52 p51 p50 (0xffff_f028) read/write r/w after reset input mode (output latch register is set to "1.") port 5 control register 7 6 5 4 3 2 1 0 p5cr bit symbol p57c p56c p55c p54c p53c p52c p51c p50c (0xffff_f02c) read/write r/w after reset 0 0 0 0 0 0 0 0 function <> port 5 function register 1 7 6 5 4 3 2 1 0 p5fc bit symbol p57f p56f p55f p54f p53f p52f p51f p50f (0xffff_f02d) read/write r/w after reset 0 0 0 0 0 0 0 0 function p5fc/p5cr = 00: input, 01: output, 10: input, 11: a7 through 0 port 5 function register 2 7 6 5 4 3 2 1 0 p5fc2 bit symbol p57f2 p56f2 p55f2 p54f2 ? (0xffff_f03c) read/write r/w r after reset 0 0 0 0 0 function 0: address/ port 1: tb3out 0: address/ port 1: tb2out 0: address/ port 1: tb1out 0: address/ port 1tb0out "0" is read. note: if p5fc = "0" and p5fc2 = "1," tb3out through tb0out are selected. to use the port 5 in the port setting, set both p5fc and p5fc2 to "0." port 5 pull-up control register 7 6 5 4 3 2 1 0 p5pe bit symbol pe57 pe56 pe55 pe54 pe53 pe52 pe51 pe50 (0xffff_f026) read/write r/w after reset 0 0 0 0 0 0 0 0 function pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up
tmp19a43 tmp19a43 (rev2.0) 7-27 input/output ports port to be used function corresponding bit of p5fc2 corresponding bit of p5fc corresponding bit of p5cr p50top53input setting - * 0 p50top53output setting - 0 1 intctointfinput setting - 1 0 p50 to p53 a0toa3output setting - 1 1 p54/p55input setting * * 0 p54/p55output setting 0 0 1 tb0out/tb1outoutput setting 1 * 1 p54/p55 a4/a5output setting 0 1 1 p56/p57input setting * 0 0 p56/p57output setting 0 0 1 tb2out/tb3outoutput setting 1 * 1 a4/a5output setting 0 1 1 p56/p57 key28/key29input setting * 0 0 table 7-5
tmp19a43 tmp19a43 (rev2.0) 7-28 input/output ports 7.7 port 6 (p60 through p67) the port 6 is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register p6cr and the function register p6fc. a reset allows all bits of the output latch p6 to be set to ?1,? all bits of p6cr and p6fc to be cleared to ?0,? and the port 6 to be put in input mode. besides the input/output port function, the port 6 performs other functions: p60 and p63 output sio data, p61 and p64 input sio data, p62 and p65 input and output sio clk or input cts, p61 and p64 input external interrupts, and p66 and p67 output a 16-bit timer. the port 6 also functions as an address bus (a8 thr ough a15). to access external memory, p6cr and p6fc must be provisioned to allow the port 6 to function as an address bus. the address bus function can be used only in separate bus mode. (to put the port 6 in separate bus mode, the busmd pin (port 45) must be set to ?l? level during a reset.)
tmp19a43 tmp19a43 (rev2.0) 7-29 input/output ports a8,11 internal data bus p6read 1 0 1 0 1 0 stop/reset drive disable external bus opening p6pe (pull-up control) p6cr (direction control) p6 (output latch) p6fc2 (function control) reset p6fc (function control) 1 0 p6ode ( open drain ) port6 p60, p63(a8,a11) txd0,txd1 txd0,1 fig. 7-17 port 6 (p60, p63)
tmp19a43 tmp19a43 (rev2.0) 7-30 input/output ports internal data bus 1 0 stop/reset drive disable external bus opening p6pe (pull-up control) p6cr (direction control) p6 (output latch) p6fc2 (function control) reset p6fc (function control) p6 read 1 0 1 0 nf (40ns typ) port6 p61, p64(a9,a12) rxd0 rxd1 inta,intb rxd0,rxd1 inta,b a9,12 fig. 7-18 port 6 (p61, p64)
tmp19a43 tmp19a43 (rev2.0) 7-31 input/output ports internal data bus p6 read 1 0 1 0 1 0 stop/reset drive disable external bus opening p6pe (ull-up control) p6cr (direction control) p6 (output latch) p6fc2 (function control) reset p6fc (function control) 1 0 p6ode (open drain) cts0, cts1 sclk0, sclk1 a10,13 sclk0,1 p62 (sclk0/cts0,a10) p65 (sclk1/cts1,a13) fig. 7-19 port 6 (p62, p65)
tmp19a43 tmp19a43 (rev2.0) 7-32 input/output ports internal data bus 1 0 1 0 stop/reset drive disable external bus opening p6pe (pull-up control) p6cr (direction control) p6 (output latch) p6fc2 (function control) reset p6fc (function control) 1 0 tb5out, tb4out p6 read 1 0 port6 p66top67 (a14toa15, tb4out,tb5out) a14,a15 fig. 7-20 port 6 (p66, p67)
tmp19a43 tmp19a43 (rev2.0) 7-33 input/output ports port 6 register 7 6 5 4 3 2 1 0 p6 bit symbol p67 p66 p65 p64 p63 p62 p61 p60 (0xffff_f029) read/write r/w after reset input mode (output latch register is set to ?1.?) port 6 control register 7 6 5 4 3 2 1 0 p6cr bit symbol p67c p66c p65c p64c p63c p62c p61c p60c (0xffff_f02e) read/write w after reset 0 0 0 0 0 0 0 0 function << see p6fc >> port 6 function register 7 6 5 4 3 2 1 0 p6fc bit symbol p67f p66f p65f p64f p63f p62f p61f p60f (0xffff_f02f) read/write w after reset 0 0 0 0 0 0 0 0 function p6fc/p6cr = 00: input, 01: output, 10: input, 11: a15 through 8 port 6 function settings p6cr p6fc 0 1 0 input port p60, p63 separate bus mode (busmd=?l?) 1 output port address bus (a11, 8) /txd0, 1 0 input port multiplexed bus mode (busmd=?h?) 1 output port address bus (a11, 8) /txd0, 1 p6cr p6fc 0 1 0 input mode (inta, b) rxd0, 1/inta, b p61, p64 separate bus mode (busmd=?l?) 1 output port address bus (a12-9) 0 input port (inta, b) rxd0, 1/inta, b multiplexed bus mode (busmd=?h?) 1 output port address bus (a12-9) p6cr p6fc 0 1 p62, p65 0 input port sclk0, 1/cts0, 1 separate bus mode (busmd=?l?) 1 output port address bus (a13-10) /sclk0, 1 0 input port sclk0, 1/cts0, 1 multiplexed bus mode (busmd=?h?) 1 output port address bus (a13-10) /sclk0, 1
tmp19a43 tmp19a43 (rev2.0) 7-34 input/output ports p6cr p6fc 0 1 0 input port p66, p67 separate bus mode (busmd=?l?) 1 output port address bus (a15, 14) /tb4out, tb5out 0 input port multiplexed bus mode (busmd=?h?) 1 output port address bus (a15, 14) /tb4out, tb5out port 6 function register 2 7 6 5 4 3 2 1 0 p6fc2 bit symbol p67f2 p66f2 p65f 2 p64f2 p63f2 p62f2 p61f2 p60f2 (0xffff_f03d) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: a15 1: tb5out 0: a14 1: tb4out 0: a13 1: sclk1/ cts1 0: a12 1:rxd1 0: a11 1: txd1 0: a10 1: sclk0/ cts0 0: a9 1: rxd0 0: a8 1: txd0, note: if p6fc = ?0? and p6fc 2 = ?1,? port is selected. to use this function register as a functional pin, set both p6fc and p6fc2 to ?1.? (set 1, 4bit to p6fc2 = ?0.?) port 6 pull-up control register 7 6 5 4 3 2 1 0 p6pe bit symbol pe67 pe66 pe65 pe64 pe63 pe62 pe61 pe60 (0xffff_f027) read/write r/w after reset 0 0 0 0 0 0 0 0 function pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up port 6 open drain control register 7 6 5 4 3 2 1 0 p6ode bit symbol ? p65ode ? p63ode p62ode ? p60ode (0xffff_ f030) read/write r r/w r r/w r r/w after reset 0 0 0 0 0 0 0 function ?0? is read. 0: cmos 1: open drain ?0? is read. 0: cmos 1: open drain 0: cmos 1: open drain ?0? is read. 0: cmos 1: open drain
tmp19a43 tmp19a43 (rev2.0) 7-35 input/output ports port to be used function corresponding bit of p6fc2 corresponding bit of p6fc corresponding bit of p6cr p60/p63input setting * * 0 p60/p63output setting * 0 1 txd0/txd1output setting 1 1 1 p60/p63 a8/a11output setting 0 1 1 p61/p64input setting * 0 0 p61/p64output setting * 0 1 rxd0/rxd1input setting 1 1 0 inta/intbinput setting * 0 0 p61/p64 a9,a12output setting 0 1 1 p62/p65input setting * * 0 p62/p65output setting * 0 1 sclk0/sclk1output setting 1 * 1 cts0/cts1/sclk0/sclk1 input setting 1 1 0 p62/p65 a10/a13output setting 0 1 1 p66/p67input setting * * 0 p66/p67output setting * 0 1 tb4out/tb5outoutput setting 1 1 1 p66/p67 a15/a16output setting 0 1 1 table 7-6
tmp19a43 tmp19a43 (rev2.0) 7-36 input/output ports 7.8 port 7 (p70 through p77) the port 7 is an 8-bit, analog input port for the a/d converter. although p74 through p77 form part of the analog input port, they also perform another function of inputting the key-on wake-up. fig. 7-21 port 7 (p70 through p73) ? if the port 7 goes into stop mode when the port input is enabled, inputs are always accepted. to inhibit inputs, switch to ad using the function register. ? ad: inputs are accepted only during a read. inputs are inhibited in stop mode. ? port: inputs are always accepted. internal data bus p7read p7pe (pull-up control) p70top73 (ain0toain3 ) ain0toain3 p7 accsess
tmp19a43 tmp19a43 (rev2.0) 7-37 input/output ports fig. 7-22 port 7 (p74 through p77) ? if the port 7 goes into stop mode when the key/port input is enabled, inputs are always accepted. to inhibit inputs, switch to ad using the function register. ? ad: inputs are accepted only during a read. inputs are inhibited in stop mode. ? key/port: inputs are always accepted. internal data bus p7read p7pe (pull-up control) p7fc (function control) key00tokey03 key ch00toch03 pull-up nf (40ns typ) 1 0 p74top77 (ain4toain7 key00tokey03) ain4toain7
tmp19a43 tmp19a43 (rev2.0) 7-38 input/output ports port 7 register 7 6 5 4 3 2 1 0 p7 bit symbol p77 p76 p75 p74 p73 p72 p71 p70 (0xffff_f040) read/write r after reset input mode port 7 function register 7 6 5 4 3 2 1 0 p7fc bit symbol p77f p76f p75f p74f ? ? ? ? (0xffff_f048) read/write r/w r after reset 0 0 0 0 0 function 0: a/d 1: port /key03 0: a/d 1: port /key02 0: a/d 1: port /key01 0: a/d 1: port /key00 "0" is read. port 7 pull-up control register 7 6 5 4 3 2 1 0 p7pe bit symbol pe77 pe76 pe75 pe74 pe73 pe72 pe71 pe70 (0xffff_f04c) read/write r/w after reset 0 0 0 0 0 0 0 0 function pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up
tmp19a43 tmp19a43 (rev2.0) 7-39 input/output ports 7.8 port 8 (p80 through p87) the port 8 is an 8-bit, analog input port for the a/d converter. besides this analog input port function, p80 through p83 input the key-on wake-up, and p84 through p87 input external interrupts. fig. 7-23 port 8 (p80 through p83) if the port 8 goes into stop mode when the key/port input is enabled, inputs are always accepted. to inhibit inputs, switch to po rt using the function register. ? ad: inputs are accepted only during a read. inputs are inhibited in stop mode. ? key/port: inputs are always accepted. internal data bus p8 read p8pe (pull-up control) p8fc (function control) key04tokey08 key ch04toch07 pull-up nf (40ns typ) 1 0 p80top83 (ain8toain11 key04tokey08) ain8toain11
tmp19a43 tmp19a43 (rev2.0) 7-40 input/output ports fig. 7-24 port 8 (p84 through p87) ? if the port 8 goes into stop mode when the key/port/int input is enabled, inputs are always accepted. to inhibit inputs, switch to ad using the function register. ? ad: inputs are accepted only during a read. inputs are inhibited in stop mode. ? key/port/int: inputs are always accepted. internal data bus p8 read p8pe (pull-up control) p8fc (function control) int6toint9 nf (40ns typ) 1 p84top87 (ain12toain15 int6toint9) ain12toain15 0
tmp19a43 tmp19a43 (rev2.0) 7-41 input/output ports port 8 register 7 6 5 4 3 2 1 0 p8 bit symbol p87 p86 p85 p84 p83 p82 p81 p80 (0xffff_f041) read/write r after reset input mode port 8 function register 7 6 5 4 3 2 1 0 p8fc bit symbol p87f p86f p85f p84f p83f p82f p81f p80f (0xffff_f049) read/write rw after reset 0 0 0 0 0 0 0 0 function 0: a/d 1: port /int9 0: a/d 1: port / int8 0: a/d 1: port / int7 0: a/d 1: port / int6 0: a/d 1: port / key07 0: a/d 1: port / key06 0: a/d 1: port / key05 0: a/d 1: port / key04 port 8 pull-up control register 7 6 5 4 3 2 1 0 p8pe bit symbol pe87 pe86 pe85 pe84 pe83 pe82 pe81 pe80 (0xffff_f04d) read/write r/w after reset 0 0 0 0 0 0 0 0 function pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up
tmp19a43 tmp19a43 (rev2.0) 7-42 input/output ports 7.9 port 9 (p90 through p97) the port 9 is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register p9cr and the function register p9fc. a reset allows all bits of the output latch p9 to be set to "1," all bits of p9cr and p9fc to be cleared to "0," and the port 9 to be put in input mode. besides the input/output port function, the port 9 performs other functions: p93 outputs si0 data, p94 inputs si0 data, p95 inputs and outputs si0 clk or inputs cts, and p90, p91, p92, p96 and p97 output a 16-bit timer. fig. 7-25 port 9 (p90, p91, p92, p96 and p97) internal data bus p9 read 1 0 stop/reset drive disable p9pe (pull-up control) p9cr (direction control) p9fc (function control) p9 (output latch) reset 1 0 port 9 p90top92,p96,p97 (tb6outtotbaout) tb6outtotb aout
tmp19a43 tmp19a43 (rev2.0) 7-43 input/output ports fig. 7-26 port 9 (p93) internal data bus p9 read 1 0 stop/reset drive disable p9pe (pull-up control) p9cr (direction control) p9fc (function control) p9 (output latch) reset p9ode (open drain) 1 0 txd2
tmp19a43 tmp19a43 (rev2.0) 7-44 input/output ports fig. 7-27 port 9 (p94) internal data bus p9 read 1 0 stop/reset drive disable p9pe (pull-up control) p9cr (direction control) p9fc (function control) p9 (output latch) reset port9 (p94 rxd2) rxd2
tmp19a43 tmp19a43 (rev2.0) 7-45 input/output ports internal data bus pb read 1 0 stop/reset drive disable pbpe (pull-up control) pbcr (direction control) pbfc (function control) pb (output latch) reset pbode (open drain) 1 0 sclk2 cts2 sclk2 p95 (sclk2/cts2) fig. 7-28 port 9 (p95)
tmp19a43 tmp19a43 (rev2.0) 7-46 input/output ports fig. 7-29 port 9 (p95) function control (in units of bits) p9fc direction control (in units of bits) p9cr output latch p9 stop drive internal data bus p95 (sclk2/cts2) cts2 sclk2 0 selector 1 s pull-up control (in units of bits) p9pe reset selector p9 read s y 1 0
tmp19a43 tmp19a43 (rev2.0) 7-47 input/output ports port 9 register 7 6 5 4 3 2 1 0 p9 bit symbol p97 p96 p95 p94 p93 p92 p91 p90 (0xffff_f042) read/write r/w after reset input mode (output latch register is set to "1.") port 9 control register 7 6 5 4 3 2 1 0 p9cr bit symbol p97c p96c p95c p94c p93c p92c p91c p90c (0xffff_f046) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port 9 function register 7 6 5 4 3 2 1 0 p9fc bit symbol p97f p96f p95f p94f p93f p92f p91f p90f (0xffff_f04a) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 1: tbaout 0: port 1: tb9out 0: port 1: sclk2/ cts2 0: port 1: rxd2 0: port 1: txd2 0: port 1: tb8out 0: port 1: tb7out 0: port 1: tb6out port 9 pull-up control register 7 6 5 4 3 2 1 0 p9pe bit symbol pe97 pe96 pe95 pe94 pe93 pe92 pe91 pe90 (0xffff_f04e) read/write r/w after reset 0 0 0 0 0 0 0 0 function pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up port 9 open drain control register 7 6 5 4 3 2 1 0 p9ode bit symbol ? p95ode ? p93ode ? (0xffff_f031) read/write r r/w r r/w r after reset 0 0 0 0 0 function "0" is read. 0: cmos 1: open drain "0" is read. 0: cmos 1: open drain "0" is read.
tmp19a43 tmp19a43 (rev2.0) 7-48 input/output ports 7.10 port a (pa0 through pa7) the port a is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register pacr and the function register pafc. a reset allows all bits of the output latch pa to be set to "1," all bits of pacr and pafc to be cleared to "0," and the port a to be put in input mode. besides the input/output port function, the port a performs other functions: pa0 through pa5 input external interrupts and a 16-bit timer, and pa6 and pa7 perform a dial input function. fig. 7-30 port a (pa0 through pa5) if the port a goes into stop mode when the int input is enabled, inputs are always accepted. to inhibit inputs, switch to po rt using the function register. ? port: inputs are accepted only during a read. ? int: inputs are always accepted. internal data bus pa read 1 0 stop/reset drive disable pape (pull-up control) pacr (direction control) pafc (function control) pa (output latch) reset port a pa0topa5 (tb6in0totb8in1, int0toint5) tb6in0totb8in1 int0toint5 nf (40ns typ)
tmp19a43 tmp19a43 (rev2.0) 7-49 input/output ports fig. 7-31 port a (pa6, pa7) internal data bus pa read 1 0 stop/reset drive disable pape (pull-up control) pacr (direction control) pafc (function control) pa (output latch) reset tb2in0,tb2in1 port a pa6,pa7 (tb2in0,tb2in1)
tmp19a43 tmp19a43 (rev2.0) 7-50 input/output ports port a register 7 6 5 4 3 2 1 0 pa bit symbol pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 (0xffff_f043) read/write r/w after reset input mode (output latch register is set to "1.") port a control register 7 6 5 4 3 2 1 0 pacr bit symbol pa7c pa6c pa5c pa4c pa3c pa2c pa1c pa0c (0xffff_f047) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port a function register 7 6 5 4 3 2 1 0 pafc bit symbol pa7f pa6f pa5f pa4f pa3f pa2f pa1f pa0f (0xffff_f04b) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 1: /tb2in1 0: port 1: /tb2in0 0: port / int5 1: int5 /tb8in1 0: port / int4 1: int4 /tb8in0 0: port / int3 1: int3 /tb7in1 0: port / int2 1: int2 /tb7in0 0: port / int1 1: int1 /tb6in1 0: port / int0 1: int0 /tb6in0 port a pull-up control register 7 6 5 4 3 2 1 0 pape bit symbol pea7 pea6 pea5 pea4 pea3 pea2 pea1 pea0 (0xffff_f04f) read/write r/w after reset 0 0 0 0 0 0 0 0 function pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up
tmp19a43 tmp19a43 (rev2.0) 7-51 input/output ports 7.11 port b (pb0 to pb7) port b is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register pbcr and the function regi ster pbfc. a reset allows all bits of the output latch pb to be set to "1," all bits of pbcr and pbfc to be cl eared to "0," and the port b to be put in input mode. besides the input/output port function, the port b performs other functions: pb2 and pb5 output hsio data, pb3 and pb6 input hsio data, pb4 and pb7 input and output hsio hclk or input hcts, and pb0 and pb1 perform a 16-bit capture input function with a dial input function. fig. 7- 32 port b (pb0, pb1) internal data bus pb read 1 0 stop/reset drive disable pbpe (pull-up control) pbcr (direction control) pbfc (function control) pb (output latch) reset port b pb0,pb1,pb3,pb6 (tb3in0,tb3in1) (hrxd0,hrxd1) tb3in0,tb3in1 hrxd0,hrxd1
tmp19a43 tmp19a43 (rev2.0) 7-52 input/output ports fig. 7-33 port b (pb2, pb5) internal data bus pb read 1 0 stop/reset drive disable pbpe (pull-up control) pbcr (direction control) pbfc (function control) pb (output latch) reset port b pb2,pb5 (htxd0,htxd1) pbode (open drain) htxd0 htxd1 1 0
tmp19a43 tmp19a43 (rev2.0) 7-53 input/output ports fig. 7-344 port b (pb4, pb7) internal data bus pb read 1 0 stop/reset drive disable pbpe (pull-up control) pbcr (direction control) pbfc (function control) pb (output latch) reset pbode (open drain) 1 0 port b pb4,pb7 (hsclk0/hcts0, hsclk1/hcts1) h sc lk 0 / h c t s0 , hsclk1/hcts1 h sc lk 0 hsclk1
tmp19a43 tmp19a43 (rev2.0) 7-54 input/output ports port b register 7 6 5 4 3 2 1 0 pb bit symbol pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 (0xffff_f050) read/write r/w after reset input mode (output latch register is set to "1.") port b control register 7 6 5 4 3 2 1 0 pbcr bit symbol pb7c pb6c pb5c pb4c pb3c pb2c pb1c pb0c (0xffff_f054) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port b function register 7 6 5 4 3 2 1 0 pbfc bit symbol pb7f pb6f pb5f pb4f pb3f pb2f pb1f pb0f (0xffff_f058) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 1: hsclk1 /hcts1 0: port 1: hrxd1 0: port 1: htxd1 0: port 1: hsclk0 /hcts0 0: port 1: hrxd0 0: port 1: htxd0 0: port 1: tb3in1 0: port 1: tb3in0 port b pull-up control register 7 6 5 4 3 2 1 0 pbpe bit symbol peb7 peb6 peb5 peb4 peb3 peb2 peb1 peb0 (0xffff_f05c) read/write r/w after reset 0 0 0 0 0 0 0 0 function pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up port b open drain control register 7 6 5 4 3 2 1 0 pbode bit symbol pb7ode ? pb5ode pb4ode ? pb2ode ? (0xffff_f034) read/write r/w r r/w r r/w r after reset 0 0 0 0 0 0 0 function 0: cmos 1: open drai n "0" is read. 0: cmos 1: open drain 0: cmos 1: open drain "0" is read. 0: cmos 1: open drain "0" is read.
tmp19a43 tmp19a43 (rev2.0) 7-55 input/output ports 7.12 port c (pc0 to pc7) port c is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register pccr and the function regi ster pcfc. a reset allows all bits of the output latch pc to be set to "1," all bits of pccr and pcfc to be cl eared to "0," and the port c to be put in input mode. besides the input/output port function, the port c performs other functions: pc0 inputs external clock sources into a 32-bit time base timer and inputs the key-on wake-up, pc1 through pc4 perform the 32-bit compare output function, and pc5 through pc7 input and output sbi. fig. 7-35 port c (pc0) if the port c goes into stop mode when the key/tbtin input is enabled, inputs are always accepted. to inhibit inputs, switch to port using the function register. ? port: inputs are accepted only during a read. ? key/tbtin: inputs are always accepted. internal data bus pa read 1 0 stop/reset drive disable pcpe (pull-up control) pccr (direction control) pcfc (function control) pc (output latch) reset portc pc0 (tbtin,key30) tbtin key30 key ch30 pu-l up nf (40ns typ)
tmp19a43 tmp19a43 (rev2.0) 7-56 input/output ports fig. 7- 36 port c (pc1 through pc4) internal data bus pcread 1 0 stop/reset drive disable pcpe (pull-up control) pccr (direction control) pcfc (function control) pc (output latch) reset 1 0 port c pc1topc4 (tcout0totcout3) tcout0to tcout3
tmp19a43 tmp19a43 (rev2.0) 7-57 input/output ports fig. 7-37 port c (pc5-pc7) internal data bus pcread 1 0 stop/reset drive disable pcpe (pull-up control) pccr (direction control) pcfc (function control) pc (output latch) reset pcode (open drain) 1 0 port c pc5,pc6,pc7 (so/sda, si/scl, sck) sda, si/scl sck so/sda scl sck
tmp19a43 tmp19a43 (rev2.0) 7-58 input/output ports port c register 7 6 5 4 3 2 1 0 pc bit symbol pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (0xffff_f051) read/write r/w after reset input mode (output latch register is set to "1.") port c control register 7 6 5 4 3 2 1 0 pccr bit symbol pc7c pc6c pc5c pc4c pc3c pc2c pc1c pc0c (0xffff_f055) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port c function register 7 6 5 4 3 2 1 0 pcfc bit symbol pc7f pc6f pc5f pc4f pc3f pc2f pc1f pc0f (0xffff_f059) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 1: sck 0: port 1: si /scl 0: port 1: so /sda0 0: port 1: tcout3 0: port 1: tcout2 0: port 1: tcout1 0: port 1: tcout0 0: port /key30 1: tbtin /key30 port c pull-up control register 7 6 5 4 3 2 1 0 pcpe bit symbol pec7 pec6 pec5 pec4 pec3 pec2 pec1 pec0 (0xffff_f05d) read/write r/w after reset 0 0 0 0 0 0 0 0 function pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up port c open drain control register 7 6 5 4 3 2 1 0 pcode bit symbol pc7ode pc6ode pc5ode ? (0xffff_f035) read/write r/w r/w r/w r after reset 0 0 0 0 function 0: cmos 1: open drain 0: cmos 1: open drain 0: cmos 1: open drain "0" is read.
tmp19a43 tmp19a43 (rev2.0) 7-59 input/output ports 7.13 port d (pd0 to pd6) the port d is a general-purpose, 7-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register pdcr and the function register pdfc. a reset allows all bits of the output latch pd to be set to "1," all bits of pdcr and pdfc to be cleared to "0," and the port d to be put in input mode. besides the input port function, the port d performs other functions: pd0 outputs hsio data, pd1 inputs hsio data, pd2 inputs and outputs hsio hclk or inputs hcts, pd3, pd4 and pd5 output a 16-bit timer, and pd6 inputs the key-on wake-up and a/d triggers into the a/d converter. fig. 7-38 port d (pd0) internal data bus pd read 1 0 stop/reset drive disable pdpe (pull-up control) pdcr (direction control) pdfc (function control) pd (output latch) reset pdode (open drain) htxd2 1 0 port d pd0 (htxd2)
tmp19a43 tmp19a43 (rev2.0) 7-60 input/output ports fig. 7-39 port d (pd1) internal data bus pd read 1 0 stop/reset drive disable pdpe (pull-up control) pdcr (direction control) pdfc (function control) pd (output latch) reset port d pd1 (hrxd2)
tmp19a43 tmp19a43 (rev2.0) 7-61 input/output ports internal data bus pd read 1 0 stop/reset drive disable pdpe (pull-up control) pdcr (direction control) pdfc (function control) pd (output latch) reset pdode (open drain) 1 0 hcts2 hsclk2 hsclk2 port d pd2 (hsclk2/ hcts2 ) fig. 7-40 port d (pd2)
tmp19a43 tmp19a43 (rev2.0) 7-62 input/output ports fig. 7- 41 port d (pd3 through pd5) internal data bus pd read 1 0 stop/reset drive disable pdpe (pull-up control) pdcr (direction control) pdfc (function control) pd (output latch) reset 1 0 port d pd3topd5 (tboutb tboutc tboutd) tboutb tboutc tboutd
tmp19a43 tmp19a43 (rev2.0) 7-63 input/output ports fig. 7- 42 port d (pd6) if the port d goes into stop mode when the key/adtrg input is enabled, inputs are always accepted. to inhibit inputs, switch to po rt using the function register. ? port: inputs are accepted only during a read. ? key/adtrg: inputs are always accepted. internal data bus pd read 1 0 stop/reset drive disable pdpe (pull-up control) pdcr (direction control) pdfc (function control) pd (output latch) reset port d pd6 (adtrg,key31) adtrg key31 key ch31 pull-up nf (40ns typ)
tmp19a43 tmp19a43 (rev2.0) 7-64 input/output ports port d register 7 6 5 4 3 2 1 0 pd bit symbol pd6 pd5 pd4 pd3 pd2 pd1 pd0 (0xffff_f052) read/write r r/w after reset 0 input mode (output latch register is set to "1.") port d control register 7 6 5 4 3 2 1 0 pdcr bit symbol pd6c pd5c pd4c pd3c pd2c pd1c pd0c (0xffff_f056) read/write r r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port d function register 7 6 5 4 3 2 1 0 pdfc bit symbol ? pd6f pd5f pd4f pd3f pd2f pd1f pd0f (0xffff_f05a) read/write r r/w after reset 0 0 0 0 0 0 0 0 function "0" is read. 0: port /key31 1: adtrg /key31 0: port 1: tbdout 0: port 1: tbcout 0: port 1: tbbout 0: port 1: hsclk2/ hcts2 0: port 1: hrxd2 0: port 1: htxd2 port d pull-up control register 7 6 5 4 3 2 1 0 pdpe bit symbol ped6 ped5 ped4 ped3 ped2 ped1 ped0 (0xffff_f05e) read/write r r/w after reset 0 0 0 0 0 0 0 0 function a written value can be read. pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up port d open drain control register 7 6 5 4 3 2 1 0 pdode bit symbol ? pd2ode ? pd0ode (0xffff_f036) read/write r r/w r r/w after reset 0 0 0 0 function "0" is read. 0: cmos 1: open drain "0" is read. 0: cmos 1: open drain
tmp19a43 tmp19a43 (rev2.0) 7-65 input/output ports 7.14 port e (pe0 through pe7) the port e is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register pecr and the function register pefc. a reset allows all bits of the output latch pe to be set to "1," all bits of pecr and pefc to be cleared to "0," and the port e to be put in input mode. besides the input/output port function, the port e performs the key-on wake-up input function. fig. 7- 43 port e (pe0 through pe7) if the port e goes into stop mode when the key input is enabled, inputs are always accepted. to inhibit inputs, switch to po rt using the function register ? port: inputs are accepted only during a read. ? key: inputs are always accepted. internal data bus pe read 1 0 stop/reset drive disable pepe (pull-up control) pecr (direction control) pefc (function control) pe (output latch) reset port e pe0tope7 (key8tokey15) key8tokey15 key ch8tokey15 pull-up nf (40ns typ)
tmp19a43 tmp19a43 (rev2.0) 7-66 input/output ports port e register 7 6 5 4 3 2 1 0 pe bit symbol pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 (0xffff_f053) read/write r/w after reset input mode (output latch register is set to "1.") port e control register 7 6 5 4 3 2 1 0 pecr bit symbol pe7c pe6c pe5c pe4c pe3c pe2c pe1c pe0c (0xffff_f057) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port e function register 7 6 5 4 3 2 1 0 pefc bit symbol pe7f pe6f pe5f pe4f pe3f pe2f pe1f pe0f (0xffff_f05b) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port / key15 1: key15 0: port / key14 1: key14 0: port / key13 1: key13 0: port / key12 1: key12 0: port / key11 1: key11 0: port / key10 1: key10 0: port / key09 1: key09 0: port / key08 1: key08 port e pull-up control register 7 6 5 4 3 2 1 0 pepe bit symbol pee7 pee6 pee5 pee4 pee3 pee2 pee1 pee0 (0xffff_f05f) read/write r/w after reset 0 0 0 0 0 0 0 0 function pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up
tmp19a43 tmp19a43 (rev2.0) 7-67 input/output ports 7.15 port f (pf0 through pf7) the port f is a general-purpose, 8-bit input/output port. fo r this port, inputs and outputs can be specified in units of bits by using the control register pfcr and the function register pffc. a reset allows all bits of the output latch pf to be set to "1," all bits of pfcr and pffc to be cleared to "0," and the port f to be put in input mode. besides the input/output port function, the port f performs the key-on wake-up input function, pf0 through pf3 perform a 32-bit timer capture input function, and pf4 through pf7 perform a 32-bit timer compare output function. fig. 7-44 port f (pf0, pf2) if the port f goes into stop mode when the key/dreq input is enabled, inputs are always accepted. to inhibit inputs, switch to po rt using the function register. ? port: inputs are accepted only during a read. ? key/dreq: inputs are always accepted. internal data bus pf read 1 0 stop/reset drive disable pfpe (pull-up control) pfcr (direction control) pffc (function control) pf (output latch) reset port f pf0,pf2 ( dreq0 , dreq4 key16,key18) dreq0 , dreq4 key ch16,18 pull-up nf (40ns typ)
tmp19a43 tmp19a43 (rev2.0) 7-68 input/output ports fig. 7-45 port f (pf1, pf3,pf4-pf7) if the port f goes into stop mode when the key input is enabled, inputs are always accepted. to inhibit inputs, switch to po rt using the function register. ? port: inputs are accepted only during a read. ? key: inputs are always accepted. internal data bus pf read 1 0 stop/reset drive disable pfpe (pull-up control) pfcr (direction control) pffc (function control) pf (output latch) reset port f pf1,pf3 pf4topf7 (dack0,dack4, tcout4to7) (key17,key19 key20tokey23) key17,key19 key20tokey23 key17,key19 ch20tokey23 pull-up nf (40ns typ) 1 0 dack0,dack4, tcout4to7
tmp19a43 tmp19a43 (rev2.0) 7-69 input/output ports port f register 7 6 5 4 3 2 1 0 pf bit symbol pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 (0xffff_f060) read/write r/w after reset input mode (output latch register is set to "1.") port f control register 7 6 5 4 3 2 1 0 pfcr bit symbol pf7c pf6c pf5c pf4c pf3c pf2c pf1c pf0c (0xffff_f064) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port f function register 7 6 5 4 3 2 1 0 pffc bit symbol pf7f pf6f pf5f pf4f pf3f pf2f pf1f pf0f (0xffff_f068) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port / key23 1: tcout7 / key23 0: port / key22 1: tcout6 / key22 0: port /key21 1: tcout5 /key21 0: port /key20 1: tcout4 /key20 0: port /key19 1: dack4 /key19 0: port /key18 1: dreq4 /key18 0: port /key17 1: dack0 /key17 0: port /key16 1: dreq0 /key16 port f pull-up control register 7 6 5 4 3 2 1 0 pfpe bit symbol pef7 pef6 pef5 pef4 pef3 pef2 pef1 pef0 (0xffff_f06c) read/write r/w after reset 0 0 0 0 0 0 0 0 function pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up
tmp19a43 tmp19a43 (rev2.0) 7-70 input/output ports 7.16 port g (pg0 through pg7) the port g is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register pgcr and the function register pgfc. a reset allows all bits of the output latch pg to set to "1," all bits of pgcr and pgfc to be cleared to "0," and the port g to be put in input mode. besides the input/output port function, the port g outputs data tracing signals for debugging. the port g gets ready to output data tracing signals according the debug le vel, independent of the regi ster setting. if dsu-ice is to be used for debugging, the port g outputs the signal for ejtag. therefore, it is recommended not to use the port g as an input/output port. fig. 7-46 port g (pg0 through pg7) (note) the above system diagram does not show the debug function. internal data bus pg read 1 0 stop/reset drive disable pgpe (pull-up control) pgcr (direction control) pg (output latch) reset port g pg0topg7
tmp19a43 tmp19a43 (rev2.0) 7-71 input/output ports port g register 7 6 5 4 3 2 1 0 pg bit symbol pg7 pg6 pg5 pg4 pg3 pg2 pg1 pg0 (0xffff_f061) read/write r/w after reset input mode (output latch register is set to "1.") port g control register 7 6 5 4 3 2 1 0 pgcr bit symbol pg7c pg6c pg5c pg4c pg3c pg2c pg1c pg0c (0xffff_f065) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port g pull-up control register 7 6 5 4 3 2 1 0 pgpe bit symbol peg7 peg6 peg5 peg4 peg3 peg2 peg1 peg0 (0xffff_f06d) read/write r/w after reset 0 0 0 0 0 0 0 0 function pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up level 0 level 1 level 2 level 3 pgfc = 0 port pg port port port pgfc = 1 tpd tpd pgfc = 0 tpd ph port port tpc pgfc = 1 port tpc table 7-7 pin states of the ports g and h relative to debug levels * when ejtag is used, the pgfc setting is made using a tool.
tmp19a43 tmp19a43 (rev2.0) 7-72 input/output ports 7.17 port h (ph0 through ph7) the port h is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register phcr. a reset allo ws all bits of the output latch ph to be set to "1," all bits of phcr to be cleared to "0," an d the port h to be put in input mode. besides the port function, the port h outputs tpc/tpd of dsu, and is determined by the levels of pgfc and ejtag. if dsu-ice is used for debugging, the port h outputs the signal for ejtag. therefore, it is recommended not to use the port h as an input/output port. fig. 7-47 port h (ph0 through ph7) (note) the above system diagram does not show the debug function. internal data bus phread 1 0 stop/reset drive disable phpe (pull-up control) phcr (direction control) ph (output latch) reset port h ph0toph7
tmp19a43 tmp19a43 (rev2.0) 7-73 input/output ports port h register 7 6 5 4 3 2 1 0 ph bit symbol ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 (0xffff_f062) read/write r/w after reset input mode (output latch register is set to "1.") port h control register 7 6 5 4 3 2 1 0 phcr bit symbol ph7c ph6c ph5c ph4c ph3c ph2c ph1c ph0c (0xffff_f066) read/write w after reset 0 0 0 0 0 0 0 0 function <> port h pull-up control register 7 6 5 4 3 2 1 0 phpe bit symbol peh7 peh6 peh5 peh4 peh3 peh2 peh1 peh0 (0xffff_f06e) read/write r/w after reset 0 0 0 0 0 0 0 0 function pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up pull-up 0: off 1: pull-up
tmp19a43 8. external bus interface the tmp19a43 has a built-in external bu s interface func tion to c o nnec t to ex ternal me m o ry , i/os, e t c. this in terface con s i s ts o f an ex ternal b u s in terface circu it (ebif), a chi p selector (cs) a n d a wa it controller . the c h i p sel ect or a n d wai t c ont rol l e r desi g n at e m a ppi ng add r esses i n a 4- bl oc k a d dres s space an d al so c ont rol wait states and data bus wi dths (8- or 16-bit) in these and ot her external a d dress s p aces. the exte rnal bus interface circ uit (ebif) c ont rols the timing of e x ternal buse s base d on the chi p sele ctor and wai t co nt r o l l e r set t i ngs. t h e eb if al s o c ont rol s t h e dy nam i c bus sizing a n d the bus arbi tratio n with t h e ex tern al bus m a st er . z ext e r n al b u s m ode selectab le add r ess, d a ta sep a rato r bu s m o d e an d m u ltip lex m o d e z w a it fun c tio n this function c a n be e n able d for each bl ock. ? a wait of u p to 7 cl o c ks can be au to m a ticall y in serted . ? a wait can b e in serted v i a th e wait / rdy pi n. z data b u s wi dth ei t h er a n 8- o r 16 - b i t wi dt h ca n be set fo r eac h bl oc k. z recove ry cycle (rea d /write) if an e x ternal bus cycle is in progress, a dummy cyc l e of up t o 2 cl ock s can be i n sert e d a n d t h i s du m m y cycle can be s p ecified for eac h bloc k. z recove ry cycle (c hi p sel ect or ) whe n an e x ternal bus is selec t ed, a dummy cycle of up to 1 cl ock ca n be inserted a n d t h is dummy cycle can be s p eci fi ed f o r eac h bl oc k. z bu s arb itration fu n c tion tmp19a43 (rev2.0) 8-1 external bu s interface
tmp19a43 8.1 address and dat a pins (1 ) ad dr ess a n d d a t a pi n set t i ngs th e tmp1 9a43 can be set to eith er sep a rat e bu s o r m u lti p l ex ed bu s m o d e . settin g the busmd p i n (po r t p45 ) to t h e "l" lev e l (dvss) at a reset activates th e sep a rate b u s m o d e , an d settin g th e p i n t o t h e "h" lev e l ( d v cc3) activates th e m u lti p l ex ed bu s m o d e . po r t p i n s 0 , 1, 2, 5 an d 6, wh ich ar e to b e conn ected t o ext e r n al de vi ce s (m em ory ) , ar e use d as a d dr ess b u ses , dat a b u ses a n d ad d r ess/ dat a b u ses . t a bl e 8- 1 sho w s these. t able 8-1 bu s mode, ad dress and dat a pins s e p a r a t e m u l t ip le x bus m d = " l " bus m d = " h" p o rt 0 (p 00 t o p 07) d 0 -d 7 a d 0 -a d 7 p o rt 1 (p 10 t o p 17) d 8 -d 15 a d 8-a d 15/ a 8 -a 15 p o rt 2 (p 20 t o p 27) a 16-a 2 3 a 0-a 7 / a 16-a 2 3 p o rt 5 (p 50 t o p 57) a 0 -a 7 g e n e r a l -p urp o s e p o rt p o rt 6 (p 60 t o p 67) a 8 -a 15 g e ne ra l - p u rp os e p o rt p o rt 37 (p 37) g e ne ra l - p u rp os e p o rt a l e each port is put into i n put m ode af ter a reset. t o acce ss an e x ternal device , set the address a nd data bus fu nct i o ns by u s i ng t h e po rt c o nt r o l re gi st er ( p nc r ) an d t h e po rt f u nct i o n r e gi st er (p nfc ) . in t h e m u ltip le x m o d e , th e fou r typ e s of fun c tio ns can b e selected , as sh own in t a b l e 8 - 2 , b y settin g th e p o rt regi st ers ( p nc r an d p n fc ). t able 8-2 ad d r ess an d dat a pins in the multiplex mo de c d e f number of addr ess buses max.24 (-16 mb ) max.24 (-16 mb ) max.16 (-64 kb ) max.8 (-256 b) number of data buses 8 16 8 16 number of address/data m u ltiplexed bus es 8 1 6 0 0 port 0 ad0 to ad7 ad0 to ad7 ad0 to ad7 ad0 to ad7 port 1 a8 to a15 ad8 to ad15 a8 to a15 ad8 to ad15 port function port 2 a16 to a23 a16 to a23 a0 to a7 a0 to a7 t i mi ng dia g ra m a23-8 a23-8 a7-0 rd ale ad7-0 d7-0 a15 -0 rd ale ad15-0 d15 -0 a23-16 a23-16 a7-0 a15 -0 rd ale ad15-0 d15 -0 (note 1 ) a7-0 (note 1 ) a7-0 rd ale ad7-0 d7-0 a 15-0 a15-0 (note 1) eve n in cases of e and f , a d dress out puts are available a s the data bus pins a r e also used for a d dress bus es. (n ot e 2) port s 0 t o 2 a r e p u t i n t o i n put m odes aft e r a r e set , an d t h ey do n o t se rve as ad dres s or dat a b u s pi ns . (n ot e 3) port 0 a u t o m a t i cal l y beco m e s a dat a a nd a d d r ess/ dat a b u s pi n w h en an ext e r n al m e mory i s bei n g accessed. (n ot e 4) any of c to f can b e selected b y settin g th e p1 cr, p1 fc, p2 cr an d p2 fc reg i sters. tmp19a43 (rev2.0) 8-2 external bu s interface
tmp19a43 (2) address hol d whe n a n i n ternal a r ea is acc essed whe n an inte rnal a r ea is bei n g accesse d, t h e a d dress bus m a intains the addre ss ou tput of the pre v iously accessed e x ternal area and doesn' t change it. also, the data bus is i n a state of high im pedance . 8.2 dat a format internal registe r s a n d exte rnal bus interfaces of the tm p19a43 a r e c o nfigure d as de scribed below . (1 ) b i g-en di an m ode c w o rd acces s ? 16 - b i t b u s wi dt h internal registe r s external buses addr es s d31 a a x0 bb x 1 aabb ccdd cc x 2 d00 d d x 3 a 1=0 a 1=1 msb l sb 8- bi t b u s wi dt h internal registe r s external buses d half word acce ss addr es s d31 a a x0 bb x 1 cc x 2 d00 d d x 3 aa b b cc dd x0 x1 x2 x3 ? 16 - b i t b u s wi dt h internal registe r s external buses addr es s d31 aabb aa x 0 d00 b b x 1 msb l sb addr es s d31 ccdd cc x 2 d00 d d x 3 msb l sb tmp19a43 (rev2.0) 8-3 external bu s interface
tmp19a43 ? 8- bi t b u s wi dt h internal registe r s external buses internal registe r s external buses e byte access ad dre s s d3 1 aa x 0 d0 0 b b x 1 a ab b x0 x1 addr es s d31 cc x 2 d00 d d x 3 cc dd x2 x3 ? 16 - b i t b u s wi dt h internal registe r s external buses addr es s d31 aa d00 a a x 0 addr es s d31 bb d00 b b x 1 addr es s d31 cc d00 c c x 2 addr es s d31 dd d00 d d x 3 msb l sb msb l sb msb l sb msb l sb tmp19a43 (rev2.0) 8-4 external bu s interface
tmp19a43 8- bi t b u s wi dt h internal registe r s external buses addr es s d31 aa d00 a a x 0 addr es s d31 bb d00 b b x 1 addr es s d31 cc d00 c c x 2 addr es s d31 dd d00 d d x 3 tmp19a43 (rev2.0) 8-5 external bu s interface
tmp19a43 (2) little-en d i an m o d e c w o rd acces s ? 16 - b i t b u s wi dt h internal registe r s external buses addr es s d31 d d x 3 cc x 2 aabb ccdd bb x 1 d00 a a x 0 a 1=0 a 1=1 lsb m sb ? 8- bi t b u s wi dt h internal registe r s external buses d half word acce ss ad dr e s s d3 1 d d x 3 cc x 2 bb x 1 d0 0 a a x 0 a ab b c c d d x0 x 1 x2 x3 ? 16 - b i t b u s wi dt h internal registe r s external buses addr es s d31 aabb bb x 1 d00 a a x 0 lsb m sb ad dr e s s d3 1 cc dd dd x 3 d0 0 c c x 2 ls b m s b tmp19a43 (rev2.0) 8-6 external bu s interface
tmp19a43 ? 8- bi t b u s wi dt h internal registe r s external buses internal registe r s external buses e byte access ad dr e s s d3 1 bb x 1 d0 0 a a x 0 a ab b x0 x1 addr es s d31 dd x 3 d00 c c x 2 cc dd x2 x3 ? 16 - b i t b u s wi dt h internal registe r s external buses ad dr e s s d3 1 aa d0 0 a a x 0 ad dr e s s d3 1 bb d0 0 b b x 1 ad dr e s s d3 1 cc d0 0 c c x 2 ad dr e s s d3 1 dd d0 0 d d x 3 ls b m s b ls b m s b ls b m s b ls b m s b tmp19a43 (rev2.0) 8-7 external bu s interface
tmp19a43 ? 8- bi t b u s wi dt h internal registe r s external buses addr es s d31 aa d00 a a x 0 addr es s d31 bb d00 b b x 1 addr es s d31 cc d00 c c x 2 addr es s d31 dd d00 d d x 3 tmp19a43 (rev2.0) 8-8 external bu s interface
tmp19a43 8.3 external bus operations (sep arate bus mode) th is section describ e s v a rious bu s timin g valu es. th e ti min g d i ag ram sh own b e low assu m e s th at th e ad dres s bus es a r e a2 3 t h r o ug h a 0 a n d t h at t h e dat a b u ses a r e d 1 5 t h r o ug h d0 . (1 ) b a si c bu s ope r a t i on the e x ternal bus cycle of t h e tmp19a43 ba sically cons i s t s o f t h ree cl oc k pul ses a n d a w a i t can be i n se r t ed as m e nt i oned l a t e r . t h e basi c cl ock o f a n e x t e rnal b u s cycle is the sam e as the internal sys t e m clock. fig. 8-1 s h ows rea d bus tim in g a n d fi g. 8-2 shows write bus tim i ng. if i n ternal a r eas are accessed, a d dress bus es r e m a i n uncha n g ed as s h ow n i n t h e s e fi gu res. a d di t i onal l y , dat a bus es are i n a st at e of hi g h i m pedanc e and control signals s u ch as rd an d wr d o no t b e co m e activ e. csn address hol d a [23:0] no output of rd rd ts ys da t a output high ? z d [15:0] internal access external access fig. 8-1 read operatio n t i ming dia g ra m no output of wr external access internal access d [15:0] output high ? z da t a ts ys a [23:0] a ddress hol d csn wr fig. 8-2 w r ite operatio n t i ming dia g ra m tmp19a43 (rev2.0) 8-9 external bu s interface
tmp19a43 (2) w a it timin g a wait cycle can be inserted for each bl ock by usin g t h e c h ip selector (cs) and wait controller . th e fo llowing th ree typ e s of wait can b e i n serted : c a wait of u p to 7 cl o c ks can be au to m a ticall y in serted . d a wait can be inserted via the wait pi n (2+ 2 n, 3+2 n , 4+ 2 n , 5+2 n , 6+ 2 n , 7+2 n ) . n o t e : 2n i s t h e num ber of exte rnal waits that can be inserte d . e a wait ca n be inserted via the rdy pi n ( 2 + 2 n , 3+2 n , 4+ 2n , 5+2 n , 6+ 2n , 7+2 n ) . n o t e : 2n i s t h e num ber of exte rnal waits that can be inserte d . th e setting of t h e n u m b e r of waits to b e au t o m a t i cally in serted and the set tin g o f th e ex tern al wait inpu t can be m a de usi n g t h e chi p sel ect or an d wai t co nt r o l l e r re gi st e r s, b m nc s. fi g. 8 - 3 t h r o ug h fi g. 8 - 1 0 s h o w t h e t i m i ng di agram s i n w h i c h wai t s ha ve b een i n sert ed . a[ 2 3 : 0 ] d[ 1 5 : 0 ] rd ad dr e s s a d d r e s s da t a da t a 0 w a i t 1 w a i t ts y s fig. 8-3 read operatio n t i ming dia g ra m (0 w a it an d 1 w a it auto matically inse rted) a[ 2 3 : 0 ] d[ 1 5 : 0 ] rd ts y s ad dr e s s da t a 5 w a i t s fig. 8-4 read operatio n t i ming dia g ra m (5 w a it s a u tomatically inse rted ) tmp19a43 (rev2.0) 8-1 0 external bu s interface
tmp19a43 fig . 8 - 5 shows th e read op eratio n ti m i n g when 0 wait, wait s au to m a tical ly in serted, and waits au to m a ti call y in serted + ex tern al waits are in serted in th e sep a rate bu s m o d e . ts y s fsy s 0 w a it 2 w a it s au to maticall y in sert e d 2 wait s automatically inserted 2 w a it s au to maticall y in sert e d + 2n (n= 1 ) 2n_w ait 3 w a it s au to maticall y in sert e d + 2n (n= 1 ) 2n_w ait 2 w a it s au to maticall y in sert e d + 2n (n= 2 ) 2n_w ait a [23:0] d[15:0] / rd / rd /w ai t a [23:0] d[15:0] / rd a [23:0] d[15:0] a [23:0] d[15:0] / rd /w ai t /w ai t /w ai t a [23:0] d[15:0] / rd /w ai t 2 wait s automatically inserted 3 wait s automatically inserted 2 wait s automatically i n s e r t e d z --- ex ternal w a it sampling point exter nal w a it sampli ng p o i n t s t a ke plac e befo r e a c y cl e of w a it s automatic a l l y inserte d is finis hed a nd b e fore a 2n_ w a i t c y c l e is finish ed as sho w n a bov e. t he same a pp li es to combi natio ns of other numb e rs of w a it s. fig. 8-5 rea d operation t i ming dia g ra m tmp19a43 (rev2.0) 8-1 1 external bu s interface
tmp19a43 fig . 8 - 6 sh ows th e write o p e ration timin g wh en 0 wait, waits au to m a tical ly in serted, and waits au to m a tical ly i n serted + ex tern al waits are i n serted i n th e sep a rate bu s m o de. ts ys fs y s 0 w a it 2 w a it s a u tomat i call y inser ted 2 w a i t s aut o m at i c al l y i n s e rt ed 2 w a it s a u tomat i call y inser ted + 2n (n =1) 2 w a i t s aut o m at i c al l y i n s e rt ed 2n_ w a i t 3 w a it s a u tomat i call y inser ted + 2n (n =1) 3 w a i t s aut o m at i c al l y i n s e rt ed 2n_ w a i t 2 w a it s a u tomat i call y inser ted + 2n (n =2) 2 w a i t s aut o m at i c al l y i n s e rt ed 2n_ w a i t / w ait a[ 23:0 ] d [ 15:0 ] a[ 23:0 ] d [ 15:0] /w r / w ait / w ait / wr a[ 23:0 ] d [ 15:0 ] /w r /w r / w ait a[ 23:0 ] d [ 15:0] a [23:0] d [ 15:0] / wr / w ait z --- ex ternal w a it s a m p li ng p o in t e x ternal w a it s a mp lin g po int s t a ke pla c e b e fore a cy cle of w a it s auto m at ica lly inser t ed is f i ni she d a nd b e fore a 2n _w ait cy cl e i s fi ni shed as show n abov e. t he sam e ap plie s t o c o mb inat i ons of ot her n u mb ers of w a it s. fig. 8-6 w r it e operation t i ming dia g ra m tmp19a43 (rev2.0) 8-1 2 external bu s interface
tmp19a43 by settin g th e b i t 3 < p33 f > o f p o rt 3 fu n c t i o n reg i ster p3fc to "1 ," th e wait in pu t p i n ( p 33 ) can also serve as t h e rdy i nput pi n . the rdy inp u t is inp u t t o t h e ex tern al bu s in terf a ce circuit as the logical re vers e of the wait in pu t. th e num ber of wai t s i s spe c i f i e d b y t h e chi p sel e ct or a n d wai t cont rol l e r re gi st er , b m nc s. fig . 8- 7 show s th e rdy in pu ts and th e n u m b e r o f waits. ts ys fsy s 2 w a it s au to maticall y in sert e d 2 wait s automatically inserted 2 w a it s au to maticall y in sert e d + 2n (n= 1 ) 2 wait s automatically inserted 2n_w ait /rdy /rdy a [23:0] d[15:0] /rd /rd a [23:0] d[15:0] z --- ex ternal rdy sampling point exter nal r d y s a mpli ng p o i n t s t a ke plac e befo r e a c y cl e of w a it s automatic a l l y inserte d is finis hed a nd b e fore a 2n_ w a i t c y c l e is finish ed as sho w n a bov e. t he same appl ies to combi nat ions of oth e r n u mbers of w a it s. fig. 8-7 rdy input and w a it op eration t i min g diag ram tmp19a43 (rev2.0) 8-1 3 external bu s interface
tmp19a43 (3) t i m e th at it tak e s b e fore ale is asserted wh en th e ex tern al bu s o f th e tmp19 a 4 3 is u s ed as a m u ltip lex e d bu s, the ale wi d t h (assert ti m e ) can b e speci fi ed by us i ng t h e sy st em cont rol regi st er sy sc r 3 < a l e sel> i n the cg . in the cas e of a se parate bus m o d e , ale is n o t ou tpu t , bu t th e tim e fro m wh en an add r ess is estab lished t o t h e assertio n o f th e rd or wr si g n al i s di f f e r ent de pe ndi n g on t h e sy sc r 3 . during a reset , = "1" is set and the rd or wr sig n a l is asserted as a po in t of two system (internal) cl oc ks afte r a n address is esta blished. if < a le sel> is cleare d to " 0 ," t h e rd or wr sig n a l is asserted at a point of one sys t e m (internal) clock afte r an ad dress is estab lish e d . t h is assert setting c a nnot be established for each bl oc k in a n exte rnal area an d the sam e se tting is comm only use d in a n ext e rnal address space . a[23:0] d[15:0] rd addr es s addr es s data data ="0" ts y s ="1" fig. 8-8 syscr3< a lese l> set v a l ue and external bus operation tmp19a43 (rev2.0) 8-1 4 external bu s interface
tmp19a43 (4 ) r ecove ry t i m e if acce ss to ext e rnal a r eas occ u rs consec utively , a dummy c y cle can be ins e rt ed for recovery tim e . a dumm y c y cle can be inse rted in bo th a re ad and a write cycle. the du m m y cy cl e i n sert i on s e t t i ng c a n be m a de i n t h e c h i p sel ect or a n d wai t c o nt r o l l e r r e gi st ers , b m nc s ( w ri t e rec ove ry cy cl e) a nd (re a d rec ove ry cy cle). as for the num b er of d u m m y cy cl es, one or t w o sy s t em cl ocks (i nt ernal ) can be s p eci fi e d fo r eac h bl oc k. fi g. 8 - 9 s h o w s t h e t i m i ng of rec ove ry t i m e i n sert i o n. cs a[23:0] rd wr addr es s nex t addr es s ts y s no rec o v e r y c y cl e cs a[ 2 3 : 0 ] rd wr 2 re c o v e ry c y c l e s a d d r es s n ex t ad dre s s 1 re c o v e ry c y c l e fig. 8-9 t i mi n g of recovery t i me inserti on tmp19a43 (rev2.0) 8-1 5 external bu s interface
tmp19a43 (5 ) chip select or recove ry tim e if acce ss to ext e rnal a r eas occ u rs consec utively , a dummy c y cle can be ins e rt ed for recovery tim e . th e du mmy cycle in sertion setting can b e m a d e in th e ch ip selecto r and wait co n t ro ller reg i sters, bm nc s. as fo r t h e n u m b er of dum m y cy cl es, one sy st em clock (i nt e r nal ) can be sp eci fi ed f o r each bloc k. fi g. 8-10 s h ows the timing of re cove ry tim e in sertion. cs a[23:0] rd wr addr es s nex t addr es s ts y s n o re co v e ry cy cl e 1 re co v e ry cy cl e fig. 8-10 t i mi ng of re cove ry t i me inse rt ion tmp19a43 (rev2.0) 8-1 6 external bu s interface
tmp19a43 8.4 external bus operations (multiplexed bu s mode) th is section describ e s v a rious bu s timin g valu es. th e ti min g d i ag ram sh own b e low assu m e s th at th e ad dres s bus es a r e a2 3 t h r o ug h a 1 6 an d t h at t h e a d dr ess/ dat a b u ses are ad 1 5 t h r o ug h a d 0 . (1 ) b a si c bu s ope r a t i on the e x ternal bus cycle of t h e tmp19a43 ba sically cons i s t s o f t h ree cl oc k pul ses a n d a w a i t can be i n se r t ed as m e nt i oned l a t e r . t h e basi c cl ock o f a n e x t e rnal b u s cycle is the sam e as the internal sys t e m clock. fi g. 8- 1 1 s h o w s rea d b u s t i m i ng an d fi g. 8- 1 2 s h o w s wri t e b u s t i m ing . i f i n t e rna l areas are a c c e ssed, add r ess b u ses rem a i n unc han g ed an d t h e ale d o es not o u t p ut l a t c h pul se as s h o w n i n t h ese fi g u res . ad di t i onal l y , a d d r ess/ dat a bu ses a r e i n a st at e of hi g h i m pedance a n d c o nt rol si g n al s suc h as rd and wr do not becom e active. a [2 3 : 1 6 ] a d [ 1 5: 0] a le rd ex te r n a l a cce ss in te r n a l a cce s s out put hi ? z no out put o f a l e no out put o f rd hi gh er - o r d e r ad d r es s h o l d ad r da t a ts ys cs n fig. 8-1 1 re ad ope r ation t i ming di ag ram a [2 3 : 1 6 ] a d [ 1 5: 0] a le wr ex t e rnal area int e rnal area o u tp u t h i ? z no out put o f a l e no out p u t of wr h i gher-o r der ad dre s s h o ld ad r da t a ts ys cs n fig. 8-12 w r i t e operation t i ming di ag ram tmp19a43 (rev2.0) 8-1 7 external bu s interface
tmp19a43 (2) w a it t i m i n g a wait cycle can be inserted for each bl ock by usin g t h e c h ip selector (cs) and wait controller . th e fo llowing th ree typ e s of wait can b e i n serted : c a wait of u p to 7 cl o c ks can be au to m a ticall y in serted . d a wait can b e in serted v i a th e wait pi n ( 2 + 2 n , 3+ 2n , 4+2 n , 5+ 2 n , 6+ 2n , 7+2 n ). no te: 2 n is th e nu m b er of ex tern al waits th at can b e i n serted . e a wait can b e in serted v i a th e rdy pi n ( 2 + 2 n , 3+ 2n , 4+2 n , 5+ 2 n , 6+ 2n , 7+2 n ). no te: 2 n is th e nu m b er of ex tern al waits th at can b e i n serted . th e setting of t h e n u m b e r of waits to b e au t o m a t i cally in serted and the set tin g o f th e ex tern al wait inpu t can be m a de usi n g t h e chi p sel ect or an d wai t co nt r o l l e r re gi st e r s, b m nc s. tmp19a43 (rev2.0) 8-1 8 external bu s interface
tmp19a43 fig . 8 - 13 shows th e read o p e ration ti m i n g wh en 0 wait, waits au to m a tical ly i n serted , an d waits au to m a tical ly i n serted + ex tern al waits are i n serted i n th e mu ltip lex e d b u s m o d e . ts ys fsy s 0 w ait 2 w ait s auto ma ticall y inser ted 2 wait s automatically inserted 2 w ait s auto ma ticall y inser ted + 2n (n=1 ) 2n_w ait 3 w ait s auto ma ticall y inser ted + 2n (n=1 ) 2n_w ait 2 w ait s auto ma ticall y inser ted + 2n (n=2 ) 2n_w ait a d[15:0] a le /w ait /w ait /rd a [23:16] /rd a [23:16] a d[15:0] /rd /w ait a d[15:0] a le a [23:16] a d[15:0] a le /w ait /w ait /rd a le a [23:16] a [23:16] a d[15:0] a le /rd da t a 2 wait s automatically inserted 3 wait s automatically inserted 2 wait s automatically inserted low er - o r der addr ess h i g her - o r der addr ess da t a da t a low er - o r der addr ess h i g her - o r der addr ess da t a low er - o r der addr ess h i g her - o r der addr ess da t a low er - o r der addr ess h i g her - o r der addr ess low er - o r der addr ess h i g her - o r der addr ess z --- ex ternal w a it sampling point exter nal w a it sampli ng p o i n t s t a ke place b e f o re a c y cle of w a it s autom ati c all y inserte d is fini shed a nd b e fo re a 2n_ w a i t c y cl e is finish e d as sho w n a bove. t he same appl ies to combi nat ions of oth e r n u mbers of w a it s. fig. 8-13 rea d operation t i ming dia g ra m tmp19a43 (rev2.0) 8-1 9 external bu s interface
tmp19a43 fi g. 8- 14 sh o w s t h e wri t e ope rat i o n t i m i ng w h en 0 wait, waits au to m a tical ly in serted, and waits fig. 8-14 w r it e operation t i ming dia g ra m au to m a tical ly i n serted + ex tern al waits are i n serted i n th e mu ltip lex e d b u s m o d e . ts ys fsy s 0 w ait 2 w ait s auto ma ticall y inser ted 2 wait s automatically inserted 2 w ait s auto ma ticall y inser ted + 2n (n=1 ) 2 wait s automatically inserted 2n_w ait 3 w ait s auto ma ticall y inser ted + 2n (n=1 ) 2 wait s automatically inserted 2n_w ait 2 w ait s auto ma ticall y inser ted + 2n (n=2 ) 2 wait s automatically inserted 2n_w ait /w ait /wr a le a le a [23:16] /wr a [23:16] a d[15:0] a [23:16] a d[15:0] /wr /w ait a d[15:0] a le /w ait /w ait /wr a [23:16] a d[15:0] a le a [23:16] a d[15:0] a le /wr /w ait h i g her - o r der addr ess z --- ex ternal w a it sampling point exter nal w a it sampli ng p o int s t a ke place b e fore a c y c l e of w a it s autom ati c all y inserte d is fini shed a nd bef o r e a 2n_ w a i t c y cl e is finish e d as sho w n a bove. t he same appl ies to combi nat ions of oth e r n u mbers of w a it s. h i g her - o r der addr ess low e r - o r der addr ess da t a low e r - o r der addr ess da t a low er - o r der addr ess da t a low er - o r der addr ess da t a da t a low e r - o r der addr ess h i g her - o r der addr ess h i g her - o r der addr ess h i g her - o r der addr ess tmp19a43 (rev2.0) 8-2 0 external bu s interface
tmp19a43 (3 ) t i m e th at it tak e s b e fore eith er 1 cl o c k o r 2 clo c k s can b e selected as th e tim e th at it tak e s b e fo re ale is asserted. th e setting b it is l o cat ed i n t h e sy st em cl ock cont r o l re gi st er . t h e de fa ul t i s 2 cl ock s . th is assert settin g canno t b e established for each bloc k in an exte rnal a r e a and t h e sam e setting is co m m only used in an exte rnal a d dress space. ale is asserted a l e ( a lesel = 0) a d [ 1 5: 0] ( a l ese l = 1) a d [ 1 5: 0] 1 c l oc k ts ys 2 c l ock s fig. 8-15 t i m e that it t a kes before ale is asserte d fi g. 8 - 1 6 s h ow s t h e t i m i ng w h en t h e al e i s 1 cl ock o r 2 cl ock s . fig. 8-16 rea d operation t i ming dia g ra m (wh e n the ale is 1 clo c k or 2 clocks) w h en th e a l e is 1 clo ck o r 2 clo cks ts ys fsy s a [23:16] a d[15:0] a le /rd dat a higher-order addre ss low er-order addre s s dat a higher-order addre ss tmp19a43 (rev2.0) 8-2 1 external bu s interface
tmp19a43 (4) read a n d w r it e recovery t i me if acce ss to ext e rnal a r eas occ u rs consec utively , a dummy c y cle can be ins e rt ed for recovery tim e . a dumm y c y cle can be inse rted in bo th a re ad and a write cycle. the du m m y cy cl e i n sert i on s e t t i ng c a n be m a de i n t h e c h i p sel ect or a n d wai t c o nt r o l l e r r e gi st ers , b m nc s ( w ri t e rec ove ry cy cl e) a nd < b n r c v > (re a d rec ove ry cy cle). as for the num b er of d u m m y cy cl es, one or t w o sy s t em cl ocks (i nt ernal ) a n be s p eci fi e d fo r eac h bl oc k. fi g . 8- 1 7 s h ows t h e t i m i ng o f rec o very t i m e i n sert i o n. when rea d / w rite reco v e r y is i n serted ( a l e w i d t h:1 f s y s ) c ts ys fsy s dumm y c y cle dumm y c y cle normal c y cle 1 r e covery c y cle 2 r e covery c y cles /cs /rd,/w r a [23:16] a d[15:0] a le da t a hi g he r - o r der addr ess low e r - o r der addr ess da t a h i g her - o r der addr ess low er - o r der addr ess da t a h i g her - o r der addr ess low er - o r der addr ess fig. 8-17 t i mi ng of re cove ry t i me inse rt ion tmp19a43 (rev2.0) 8-2 2 external bu s interface
tmp19a43 (5) chip select or recove ry tim e if acce ss to ext e rnal a r eas occ u rs consec utively , a dummy c y cle can be ins e rt ed for recovery tim e . th e du mmy cycle in sertion setting can b e m a d e in th e ch ip selecto r and wait co n t ro ller reg i s t e r s , bm nc s. as fo r t h e n u m b er of dum m y cy cl es, one sy st em clock (i nt e r nal ) can be sp eci fi ed f o r each bloc k. fi g. 8-18 s h ows the timing of re cove ry tim e in sertion. fig. 8-18 t i mi ng of re cove ry t i me inse rt ion h en ch ip selecto r re co v e r y is in sert e d (a l e w i d t h : 1fsys) w ts ys f s y s d normal c y cl e chip s e lector r e cover y c y cle /rd,/wr /cs a [23:16] a u m m y cy cl e d[15:0] a le da t a h i g her - o r der a d d r ess low er addr ess - o r der da t a h i g her - o r der a d d l o w er - o r der addr ess r ess tmp19a43 (rev2.0) 8-2 3 external bu s interface
tmp19a43 8 . 5 the e x t e b u s arbitration tmp19a43 ca n be c o nnected to a n e x ternal bus m a st er . th e arb i t r atio n of bu s co n t ro l au thority with t h e r n a l bus m a ster is exe c ut ed b y u s i n g t h e two sign als, busrq and busak . t h e ex ter n a l bu s ma s t e r c a n i re con t ro l au t h ority fo r tmp19 a 43 extern al bu ses on ly , an d can n acq u o t a c q u i re con t ro l au tho r ity for in tern al bus es. (1) ly , and can not re c o ntrol aut h ority for internal buse s (g-b us). therefore, the exte rnal bus m a ster cannot access the tern al m e m o ries or t h e i n tern al i/ o . th e arb itration of b u s con t ro l au thority for ex tern al bu ses is ex ecu t ed al bu s in terface c a n d t h is is ind e p e u a n d t h e i n tern al dma c . the external bus a ster h d s th e ex t ro l auth ority , th e cpu an d t h e intern al e in ternal ro m, ram and reg i sters. on th e o t her h a nd , if th e cpu o r th e in tern al r ies t o acces s a n e x ternal m e m o ry whe n t h e e x ternal bus m a ster hol ds t h e e x ternal bus c o ntrol u t , th e cpu o r t h e in t e rn al d m a c has to w a it un til th e ex tern al bu s m a ster releases th e b u s. fo r t h is e a c c e s s i b l e r a nge of external bus m a ster t h e e x ternal bus m a ster can ac quir e con t ro l au t h ority fo r tmp1 9a4 3 ex tern al bu ses on a c q u i i n b y th e ex tern i r c u i t ( e b i f ) , n d en t of th e c p e v e n w h e n m a c m o l tern al b u s con d can access th dmac t a h o r i t y busrq r e a s o n , i f t h re m a ins active, th e tmp19a43 ca n loc k . (2) a c qu isitio n of b u s co n t ro l au th ority e ex tern al bu s m a s t e r m p 1 9 a 43 f o r b i n g th e busrq th r e q u e s t s t h e t u s co n t ro l au t h ority b y a s s e r t signal. the tmp19a43 sam p l e s t h e busrq signal at t h e brea k of e x ternal b u h eth e r or no t to g i ve th e bu s con t ro l au thority to s c y c l e s on the internal buses (g- bu s) and d e term in es w th e ex tern al bus m a ster . w h en it gi ves t h e bu s c ont rol a u t h ori t y t o t h e e x t e r n al bus m a st er , it assert s t h e busak sig n a l. a t th e sa m e ti me, i t m a kes add r e ss b u ses, dat a bus es an d b u s cont rol si gnal s ( rd and wr ) i n a st at e of hi g h i m peda nce. (th e in tern al pu ll-up is en ab l e d for th e w r/ , hwr and csx .) depe n d i n g o n t h e rel a t i o ns hi p bet w ee n t h e si ze o f dat a t o be l o ade d o r st ore d a n d t h e e x t e r n al m e m o ry b u s width, two or m o re bus cycle s can occur in response to a s i ngl e dat a t r a n sfer (b us si zing). in this cas e, the end of t h e last bus cycle is th e break of e x ternal bus cycles. if acc ess t o e x ternal a r eas occ u rs consec utively on th e tm p19a43, a dummy c y cle can be i n se rted. agai n, requests for buses a r e acce pte d at the brea k of e x ternal bus cycles on the i n ternal buse s (g-b us). duri ng a dumm y cycle, the next e x ternal bus cy cle is already starte d on the internal buses. therefore, eve n i f t h e busrq sign al is assert ed du ri n g a dummy cycle, th e bu s is no t rel eased un til th e n e x t ex tern al bu s cycle is co m p leted . keep asse rting the busrq signal unt il the bus c o nt rol aut h ority is released. fi g. 8 - 1 9 s h ow s t h e t i m i ng o f acqui ri n g bus c ont rol a u t h ori t y by t h e e x t e r n al bu s m a st er . tmp19a43 (rev2.0) 8-2 4 external bu s interface
tmp19a43 c d e i n t e rnal address e x t e rnal addres s t m e r n a l acc p 19a 43 ex t e ss t m p19a4 3 ex ter nal ac c e s s e x ter n a l bus m a ste r cyc le t m p 19a 43 e x t e r n a l ac c e s s ts ys bu sr q bu sa k t m p19a4 3 ex ter nal ac c e s s c busrq is at the " h " le vel. th e tmp19a 43 rec ognizes t h at the d busrq is at the "l" le vel, a n d releases t h e bus at t h e e n d of the bus cycle. w h en th e bu s is co m p leted , t h e tmp1 9a4 3 asserts busak . the external bus mast er reco gn izes th at th e e busak i s a t l e v e l, an d acqu i res th e bu s co n t ro l au tho r i t y t h e " l " t o s t a r t b u s op eratio n s . fig. 8-19 bu s control auth ority acqui s ition t i ming (3) s t h e bu release o f bu s co n t ro l au thority th e ex tern al bu s m a s t e r r e l e a s e s contro l au tho r ity w h en it b eco m e s unn ecessary . if t h e ex tern al b u s m a ster n o l o ng er n e ed s the bu s co n t ro l au tho r ity th at it h a s h e ld , it d e asserts th e busrq sig n a l and ret u rn s th e bu s contro l au tho r ity to th e tmp1 9a4 3 . fig . 8-20 sho w s th e tim in g of releasin g unn ecessary b u s con t r o u t h o r i l a t y . i n t e rnal address e x t e rnal addres s t m p 19a 43 ex ternal acc e ss t m p 19a 43 e x t e r n a l ac c e s s t m p 19a 43 e x t e r n a l ac c e s s e x ter nal bus m a ster cycle t m p 19a 43 e x t e r n a l ac c e s s cd e ts ys bu sr q bu sa k c the e x ternal bus m a ster ha s t h e bu s c ont r o l aut h ori t y . d the e x ternal bus m a ster deas serts the busrq , as it no longe r requi r es the bus control a u thority . e th e tmp19a 43 rec ognizes that the busrq is at the "h" level, and deasse rts the busak . fig. 8-20 t i mi ng of rele asi ng bus control authority tmp19a43 (rev2.0) 8-2 5 external bu s interface
tmp19a43 9. the chip selector and w a i t control l er the tm p1 9 a 4 3 ca n be c o n n e c t e d t o e x t e r n a l devi ces ( i / o devi ces , r o m and sr am ). 4-bloc k addres s s p aces (cs0 through c s 3) can be esta b lished i n t h e tm p19a43 a nd three param e ters ca n be specified for e ach 4-bloc k a d dress an d othe r address s p aces : data bus widt h, t h e num ber of waits a n d the num b er of dummy cycles. cs0 t h r o ug h cs3 (als o use d a s p40 t h rough p43) a r e the outp ut pins corres ponding to s p aces cs0 through cs3. these pins ge nerate chi p select or signals (f or r o m and sr am) to each s p ace when the cpu designates an a d dres s i n whic h spaces cs0 t h rough c s 3 are selected. for chi p selector signals t o be ge ne rated, howe ver , t h e p o r t 4 co nt r o l l e r re gi st er ( p 4c r ) an d t h e po rt 4 f u nct i o n re gi st er ( p 4 f c ) m u st be set a p p r op ri at el y . the s p eci fi cat i o n o f t h e s p ace s c s 0 t h r o ug h c s 3 i s t o be pe rf orm e d wi t h a com b i n at i on o f ba se a d d r esse s (b a n , n = 0 t o 3) a n d m a sk ad dresse s (m a n , n = 0 t o 3 ) u s i n g t h e base a nd m a sk add r ess set t i n g regi st ers (b m a 0 t h r o ug h bma3 ). mean wh ile, master en ab le, data b u s wid t h, th e n u m b e r of waits and the num b er of dummy cycles for eac h address space are s p ecified in the c h i p sel ect or an d wai t co nt r o l l e r re gi st e r s (b 0 1 c s , b 2 3c s, an d b e x c s). a bu s wait requ est p i n ( wait / r dy ) i s pr o v i d e d as an i n p u t pi n t o co nt r o l t h e st a t us of t h ese set t i ngs. 9.1 s p ecif y ing address s p aces spaces cs0 t h rough cs3 a r e speci fied using the base and m a sk addre ss setting re gisters (bm a 0 through bma3 ). in each bus cycle, a com p arison is m a de to see if each address on the bu s is located in th e space cs0 through cs3. if the re sult of a c o m p arison is a m a tch, it is c o nsidered that the designate d cs s p ace has bee n accessed and c h i p sel ect or si g n al s a r e o u t p ut fr om pi ns cs0 th ro ugh cs3 and the ope rations s p ecified by t h e c h ip sel ect or a n d w a i t cont rol l e r r e gi st ers (b 01c s a n d b 2 3c s ) are exec ute d . (refer to " 9 .2 the c h ip sele ctor and w a it con t ro ller . ") 9.1.1 base and mask addres s setting registers fig . 9-1 and fig . 9 - 2 show base and m a sk ad dress settin g reg i sters. fo r b a se add r esses (ba0 th rou g h ba3), a start a d dress in the s p ace c s 0 through cs3 is s p e c ified. in each bus cycle, the chip selector a n d wait co n t ro ller co m p are v a lues in th eir reg i sters with a d dresses and thos e addresses wi th address bits m a s k e d b y t h e m a s k a d d r e s s ( m a 0 t h r o u g h m a 3 ) a r e not c o m p ared. the size of a n a d dress s p ace is d e term in ed b y th e m a sk add r ess settin g. (1) base addres ses base address ban s p ecifies the hi ghe r - order 16 bits (a 31 through a16) of the start a d dres s. t h e l o we r - o r d e r 16 b its (a15 to a0 ) of th e st art addres s are always se t to "0." the r e f ore, the start a d dress be gins w ith 0 x00 00_ 00 00h an d in creases in 64 k ilo b y te u n its. fi g. 9 - 3 sh o w s t h e rel a t i ons hi p bet w ee n t h e st art ad dres s a n d t h e b a n val u e. (2) mask a d dresse s mask a d dress (man) s p ecifi es which a d dre ss bit val u e is t o be com p are d . t h e a d dress on the bus that co rresp ond s t o th e b i t fo r which "0 " is written on t h e add r ess m a sk man is t o b e in clud ed in ad dress com p arison t o determ ine if t h e address is i n the a r ea of t h e cs0 to cs3 s p aces. t h e bit for whic h " 1 " is written is no t i n clud ed in address co m p arison . cs0 t o cs3 s p aces ha ve dif f e r ent a d dress bi t s that ca n be maske d by ma0 to ma3. cs0 s p ace a n d cs1 s p ace: a29 through a14 cs2 s p ace a n d cs3 s p ace: a30 through a15 (no t e ) addre ss se ttings must b e made usin g ph y s ical a ddress es. tmp19a43 (rev2.0 ) 9-1 the chip sel e ctor and w a it controller
tmp19a43 base and m a sk add r ess setting reg i sters bma0 (0 xffff_e4 00) to bma3 (0x f fff_ e4 0c) 7 6 5 4 3 2 1 0 b m a 0 b i t sy m b o l m a 0 (0xff ff_e40 0 ) r e a d / w r i t e r / w a f t e r r e s e t 1 1 1 1 1 1 1 1 function cs0 space size setti ng 0: addre ss for comparison 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t sy m b o l m a 0 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 1 1 function make sure that you w r i te "0. " cs0 space size setting 0: address for comparison 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t sy m b o l b a 0 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 function a23 to a16 to be set as a start ad dress 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t sy m b o l b a 0 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 function a31 to a24 to be set as a start ad dress 7 6 5 4 3 2 1 0 b m a 1 b i t sy m b o l m a 1 (0xff ff_e40 4 ) r e a d / w r i t e r / w a f t e r r e s e t 1 1 1 1 1 1 1 1 function cs1 space size setti ng 0: addre ss for comparison 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t sy m b o l m a 1 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 1 1 function make sure that you w r i te "0. " cs1 space size setting 0: address for comparison 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t sy m b o l b a 1 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 function a23 to a16 to be set as a start ad dress 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t sy m b o l b a 1 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 function a31 to a24 to be set as a start ad dress (no t e ) make sur e th at y ou w r i t e "0" for bit s 1 0 throug h 15 for bm a0 a nd bm a1. the size of both the cs0 and cs1 s p aces c a n b e a minimum of 16 kb to a maximu m of 1 gb. the external addre s s sp ace of the tmp19a4 3 is 16 mb a nd so bit s 10 through 15 must be set to "0" as addres s e s a24 throu g h a29 ar e no t masked. fig. 9-1 ba se and mask ad dre ss setting regi sters (b ma0, bma1) tmp19a43 (rev2.0 ) 9-2 the chip sel e ctor and w a it controller
tmp19a43 7 6 5 4 3 2 1 0 b m a 2 b i t sy m b o l m a 2 (0xff ff_e40 8 ) r e a d / w r i t e r / w a f t e r r e s e t 1 1 1 1 1 1 1 1 function cs0 space size setti ng 0: addre ss for comparison 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t sy m b o l m a 2 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 1 1 function make sure that you w r ite "0. " 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t sy m b o l b a 2 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 function a23 to a16 to be set as a start ad dress 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t sy m b o l b a 2 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 function a31 to a24 to be set as a start ad dress 7 6 5 4 3 2 1 0 b m a 3 b i t sy m b o l m a 3 ( 0 x f f f f _ e 4 0 c ) r e a d / w r i t e r / w a f t e r r e s e t 1 1 1 1 1 1 1 1 function cs1 space size setti ng 0: addre ss for comparison 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t sy m b o l m a 3 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 1 1 function make sure that you w r ite "0. " 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t sy m b o l b a 3 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 function a23 to a16 to be set as a start ad dress 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t sy m b o l b a 3 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 function a31 to a24 to be set as a start ad dress (no t e ) make sur e th at y ou w r i t e "0" for bit s 9 through 1 5 for bma2 an d bma3. the size of both the cs2 and cs3 s p aces c a n b e a minimum of 32 kb to a maximu m of 2 gb. the ex ternal add r es s sp ace of the tmp19 a 4 3 is 16 m b a nd so bit s 9 throug h 15 must be set to "0" as addres s e s a24 throu g h a30 ar e no t masked. fig. 9-2 ba se and mask ad dre ss setting regi sters (b ma2, bma3) tmp19a43 (rev2.0 ) 9-3 the chip sel e ctor and w a it controller
tmp19a43 s t a r t addr es s b a s e a ddr es s v a lue ( b a n ) 0 x ffff_0000 0 x f fff_ ffff f fffh a d dr es s 0x 0 0 00_0000 64 k b 0 x 0 006_0000 00 06h 0 x 0 005_0000 00 05h 0 x 0 004_0000 00 04h 0 x 0 003_0000 00 03h 0 x 0 002_0000 0 002h 0 x 0 001_0000 00 01h 0 x 0 000_0000 00 00h fig. 9-3 s t art and base ad dre ss regi ste r v a lue s 9.1.2 how to defi ne s t art ad dresses and address s p aces ? t o specify a space of 64 kb star ting at 0xc000_0000 in the cs0 space, t h e base and m a s k address regi st ers m u st be pr o g ram m ed as sh o w n bel o w . 3 1 1 6 1 5 0 b a 0 m a 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 c 0 0 0 0 0 0 3 v a lue s to be set in the ba se a n d ma sk a ddre ss re gis t e r s (bma0) in the base a ddress (b a0), s p ecify "0xc 000" that corr esp o nds t o hi ghe r 1 6 bi t s o f a st art add r ess, w h i l e in the m a sk a d dress (ma0), s p ecify whether a c o m p arison of addresse s in th e sp ace a29 th rou gh a14 i s to b e m a d e o r n o t . a co m p ariso n of a3 1 and a3 0 will d e fi n itely b e m a d e an d to en su re a co m p ariso n of a2 9 t h r o ug h a 2 4 , set bi t s 1 5 t o 10 o f t h e m a sk a d dress (m a0 ) t o "0 ." th is settin g al lo w s a 3 1 thro ugh a16 to b e co m p ar ed w ith th e v a lu e sp ecif i ed as a star t ad dr ess. there f ore, a s p ace of 64 kb from 0xc000_0000 to 0xc000_ffff is de si gnated as a cs0 space and the cs0 sign al is asserted if th ere is a match with a n address on t h e bus . tmp19a43 (rev2.0 ) 9-4 the chip sel e ctor and w a it controller
tmp19a43 t o s p ecify a s p ace of 1 mb startin g at 0x1fd0_0000 i n the cs2 s p ac e, the base and m a sk a d dres s regi st ers m u st be pr o g ram m ed as sh o w n bel o w . 3 1 1 6 1 5 0 b a 2 m a 2 0 0 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 f d 0 0 0 1 f v a lues to b e se t in the base a nd mask ad dre ss registers (bma2) in t h e base ad d r ess (b a2 ), s p ecify "0 x1fd0" that corres ponds t o higher 16 b its o f a start ad dress, wh ile in the m a sk a d dress (ma2), s p ecify whether a c o m p arison of addresse s in th e sp ace a30 th rou gh a15 i s to b e m a d e or n o t . a co m p arison o f a31 will d e fi n itely b e m a d e an d to en su re a com p ariso n o f a3 0 th ro ugh a20 , set b its 15 t o 5 o f th e m a sk add r ess (m a2) t o "0 ." th is setting allo ws a31 throug h a2 0 to b e co m p ared w ith t h e v a lu e sp eci fied as a start ad dress. as a1 9 t h r o u g h a 0 a r e m a sked, a s p a ce of 1 m b f r o m 0x1f d0 _ 0 0 0 0 t o 0 x 1 f df _ff ff i s desi g n at ed a s a c s 2 space. after a reset, t h e cs0, cs1 a n d cs3 s p aces are disa ble d , while the whol e cs2 space (4 gb) is e n able d as an addre ss s p ace. tmp19a43 (rev2.0 ) 9-5 the chip sel e ctor and w a it controller
tmp19a43 t a ble 9-1 s hows the relationship betwee n cs space a n d space sizes. if two or m o re a d dress s p aces are specified sim u l t aneously , a space or spaces with a sm al ler space num b er will be give n priority in space selectio n . example: 0xc000 _000 0 as a st ar t a ddress o f th e cs0 sp ac e w i th a sp ac e size of 1 6 kb 0xc000 _000 0 as a st ar t a ddress o f th e cs1 sp ac e w i th a sp ac e size of 6 4 kb cs0 sp a c e cs1 s p a c e 0xc00 0_3f 0xc00 0_00 0xc00 0_fff f 0xc00 0_3f if a sp ace of 0xc 000_0000 to 0xc00 0_3f ff is accessed, the cs0 sp ace is selected. 0xc00 0_00 t able 9-1 cs s p ace and s p a c e size s size (by t es) cs sp ace 16 k 32 k 64 k 128 k 256 k 512 k 1 m 2 m 4 m 8 m 16 m cs0 { { { { { { { { { { { cs1 { { { { { { { { { { { c s 2 { { { { { { { { { { c s 3 { { { { { { { { { { tmp19a43 (rev2.0 ) 9-6 the chip sel e ctor and w a it controller
tmp19a43 9.2 the chip selector and w a it controller fig. 9-4 to fig. 9-6 s h ow t h e chip selector and wait controller re gisters. for each a ddress s p ace (s pa ces cs0 th ro ugh cs3 an d o t h e r add r ess sp aces) , each ch ip selecto r and w a it con t ro ller r e g i ster (b0 1 c s th rough b23 c s, b e xc s) ca n b e pr o g ram m ed t o set m a st er enabl e or di sa bl e, t o sel ect d a t a bus wi dt h, t o speci fy t h e num ber of waits and t o insert dummy cycles. if t w o or m o re addre ss s p ace s are spe c ified sim u ltaneously , a s p ace or s p aces with a smaller space num ber will be gi ve n pri o ri t y i n space sel e ct i on (o rde r of pri o ri t y : c s 0> c s 1>c s 2>c s 3>e x c s ) . b01cs (0x ffff_e480), b23cs (0x fff f_e484), be x c s ( 0 x ffff_e488) b 0 1 c s 7 6 5 4 3 2 1 0 (0xffff_e48 0 ) b i t sy m b o l b0o m b0bus b 0 w r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 0 0 0 1 0 1 function select the chip selector output w a vefo rm. 00: rom/ ram do not make an y other settings. this can be read as "0." select data bus w i dth. 0: 16 bit 1: 8 bit specify th e num ber of w a its. (automatic wait insertion) 0000: 0wait 0 001: 1wait 001 0: 2wait 0011: 3wait 0 100: 4wait 010 1: 5wait 0110: 6wait 0 111: 7wait (ext ernal wait input) 1010: (2 + 2xn) wait 1011: (3 + 2xn) wait 1100: (4 + 2xn) wait 1101: (5 + 2xn) wait 1110: (6 + 2xn) wait 1111: (7 + 2xn) wait 1000, 1001: res e rved 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t sy m b o l b0cscv b 0 w c v b 0 e b 0 r c v r e a d / w r i t e r r / w r / w r / w r r / w a f t e r r e s e t 0 0 0 0 0 0 0 f u n c t i o n t h i s c a n be read as "0." specify th e number of dumm y cy cles to be inserted. (cs0 r e covery time) 1: 1 c y cle 0: none specify th e num ber of dumm y c y cles to be inserted. (w rite, recovery ti me) 00: 2 c y cles 01: 1 c y cle 10: none 11: setting prohi bited enable or disable cs0. 0: disable 1: enable this can be read as "0. " specify th e num ber of dumm y c y cles to be inserted. (read, recovery time) 00: 2 c y cles 01: 1 c y cle 10: none 11: setting prohi bited 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t sy m b o l b1o m b1bus b 1 w r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 0 0 0 1 0 1 function select the chip selector output w a vefo rm. 00: rom/ ram do not make an y other settings. this can be read as "0." select data bus w i dth. 0: 16 bit 1: 8 bit specify th e num ber of w a its. (automatic wait insertion) 0000: 0wait 0 001: 1wait 001 0: 2wait 0011: 3wait 0 100: 4wait 010 1: 5wait 0110: 6wait 0 111: 7wait (ex t ernal w a it inp u t) 1010: (2 + 2xn) w a it 1011: (3 + 2 x n) wait 1100: (4 + 2xn) wait 1101: (5 + 2xn) wait 1110: (6 + 2xn) wait 1111: (7 + 2xn) wait 1000, 1001: res e rved 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t sy m b o l b1cscv b 1 w c v b 1 e b 1 r c v r e a d / w r i t e r r / w r / w r / w r r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 f u n c t i o n t h i s c a n be read as "0." specify th e number of dumm y cy cles to be inserted. (cs1 r e covery time) 1: 1 c y cle 0: none specify th e num ber of dumm y c y cles to be inserted. (w rite, recovery ti me) 00: 2 c y cles 01: 1 c y cle 10: none 11: setting prohi bited enable or disable cs1. 0: disable 1: enable this can be read as "0. " specify th e num ber of dumm y c y cles to be inserted. (read, recovery time) 00: 2 c y cles 01: 1 c y cle 10: none 11: setting prohi bited fig. 9-4 chip selecto r and w a it controll er re giste r s tmp19a43 (rev2.0 ) 9-7 the chip sel e ctor and w a it controller
tmp19a43 tmp19a43 (rev2.0) 9-8 the chip selector and wait controller b23cs 7 6 5 4 3 2 1 0 (0xffff_e484) bit symbol b2om b2bus b2w read/write r/w r/w after reset 0 0 0 0 1 0 1 function select the chip selector output waveform. 00: rom/ram do not make any other settings. this can be read as "0." select data bus width. 0: 16 bit 1: 8 bit specify the number of waits. (automatic wait insertion) 0000: 0wait 0001: 1wait 0010: 2wait 0011: 3wait 0100: 4wait 0101: 5wait 0110: 6wait 0111: 7wait (external wait input) 1010: (2 + 2xn) wait 1011: (3 + 2xn) wait 1100: (4 + 2xn) wait 1101: (5 + 2xn) wait 1110: (6 + 2xn) wait 1111: (7 + 2xn) wait 1000, 1001: reserved 15 14 13 12 11 10 9 8 bit symbol b2cscv b2wcv b2e b2m b2rcv read/write r r/w r/w r/w after reset 0 0 0 0 1 0 0 0 function this can be read as "0." specify the number of dummy cycles to be inserted. (cs2 recovery time) 1: 1 cycle 0: none specify the number of dummy cycles to be inserted. (write, recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting prohibited enable or disable cs2. 0: disable 1: enable select cs2 space. 0: 4 gb space 1: cs space specify the number of dummy cycles to be inserted. (read, recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting prohibited 23 22 21 20 19 18 17 16 bit symbol b3om b3bus b3w read/write r/w r r/w after reset 0 0 0 0 0 1 0 1 function select the chip select output waveform. 00: rom/ram do not make any other settings. this can be read as "0." select data bus width. 0: 16 bit 1: 8 bit specify the number of waits. (automatic wait insertion) 0000: 0wait 0001: 1wait 0010: 2wait 0011: 3wait 0100: 4wait 0101: 5wait 0110: 6wait 0111: 7wait (external wait input) 1010: (2 + 2xn) wait 1011: (3 + 2xn) wait 1100: (4 + 2xn) wait 1101: (5 + 2xn) wait 1110: (6 + 2xn) wait 1111: (7 + 2xn) wait 1000, 1001: reserved 31 30 29 28 27 26 25 24 bit symbol b3cscv b3wcv b3e b3rcv read/write r r/w r/w r/w r r/w after reset 0 0 0 0 0 0 0 0 function this can be read as "0." specify the number of dummy cycles to be inserted. (cs3 recovery time) 1: 1 cycle 0: none specify the number of dummy cycles to be inserted. (write, recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting prohibited enable or disable cs3. 0: disable 1: enable this can be read as "0." specify the number of dummy cycles to be inserted. (read, recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting prohibited fig. 9-5 chip selector and wait controller registers
tmp19a43 b e x c s 7 6 5 4 3 2 1 0 little (0x f fff_e 48c) bit sy mbol bexo m bexbus bexw big (0xf ff, f_e4 8e) read/write r/w r r/w a f t e r r e s e t 0 0 0 0 0 1 0 1 function select the chip selector output w a vefo rm. 00: rom/ ram do not make an y other settings. this can be read as "0." select data bus w i dth. 0: 16 bit 1: 8 bit specify th e num ber of w a its. (automatic wait insertion) 0000: 0wait 00 01: 1wait 0010 : 2wait 0011: 3wait 01 00: 4wait 0101 : 5wait 0110: 6wait 01 11: 7wait (exte r nal wait i nput) 1010: (2 + 2xn) w a it 1011: (3 + 2 x n) wait 1100: (4 + 2xn) wait 1101: (5 + 2xn) wait 1110: (6 + 2xn) wait 1111: (7 + 2xn) wait 1000, 1001: res e rved 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t sy m b o l becscv b e x w c v b e x r c v r e a d / w r i t e r r / w r / w r r / w a f t e r r e s e t 0 0 0 0 0 0 0 f u n c t i o n t h i s c a n be read as "0." specify th e number of dumm y cy cles to be inserted. 1: 1 c y cle 0: none specify th e num ber of dumm y c y cles to be inserted. (w rite, recovery ti me) 00: 2 c y cles 01: 1 c y cle 10: none 11: setting prohi bited this can be read as "0." specify th e num ber of dumm y c y cles to be inserted. (read, recovery time) 00: 2 c y cles 01: 1 c y cle 10: none 11: setting prohi bited fig. 9-6 chip selecto r and w a it controll er re giste r s a res e t o f th e tmp19 a 43 allo w s the port 4 co ntr o ller register (p4cr) a nd the por t 4 func tion regi ster (p4 f c) to be cleared to "0 ," and the cs sign al output is disabled. t o ou tput th e cs signal s , set the c orresp ondin g bit s to "1 " at th e p4f c and the p4cr in th at order . the cs r e c o v e r y time can be con f igured in an y other area s tha n th e cs se tting areas, bu t cs signals w i l l not be outp u t. tmp19a43 (rev2.0 ) 9-9 the chip sel e ctor and w a it controller
tmp19a43 10. dma controller (dmac) th e tm p19a43 h a s a bu ilt-in 8-ch ann e l dm a c o n t ro ller (dmac). 10.1 features th e d m a c of th e tmp1 9a43 has t h e following feature s : (1 ) dma with 8 ind e p e nd en t ch an n e ls (t w o i n t e r r upt f act ors, 0c h t h r o u g h 3ch: i n t d m a 0, 4c h t h r o u g h 7ch: i n t d m a 1) (2) t w o ty p e s o f req u e sts fo r bu s con t ro l au t h ority: w ith an d with ou t sno o p requ ests (3 ) t r an sfer requ ests: in tern al req u e sts (so f t w are in itiated ) /ex t ern a l requ ests (ex t ern a l in terrup ts, i n t e rr upt re que st s gi ve n by i n t e rnal peri ph era l i/ os, an d re q u est s gi ve n by t h e dr e q pi n ) r e quest s gi ven by t h e dr e q pi n (c h 0 , 4 ) : level m ode (m em ory me m o r y ) ed ge m ode (m em ory i/o , i/o t o m e m o ry) (4) t r ans f er m ode: dual address m ode (5) t r ans f er de vic e s: me m o ry space trans f er (6 ) devi ce si ze: 3 2 - b i t m e m o ry (8 or 1 6 bi t s ca n be s p eci fi ed usi n g t h e c s / w ai t c ont r o l l e r); i/ o of 8 , 1 6 or 32 b its (7) address c h a n ges: inc r ease, de crease, fi xe d, i rre gul a r i n c r ea se, i r reg u l a r de crease (8 ) c h an nel pri o ri t y : fi xed (i n as cendi ng o r der of cha n nel n u m bers) (9 ) en di an s w i t c h ove r fu nct i o n tmp19a43 (rev2.0 ) 10-1 dma control l er (dmac)
tmp19a43 10.2 configuration 10.2.1 internal connections of the tmp19a43 fig . 10 -1 sho w s th e i n tern al co nn ection s with th e dm ac i n th e tmp1 9a4 3 . dreq [4, 0 ] dack [4,0] dmac contro l request for bus co ntrol authori t y request to relea s e bus control autho rity notifi ca tion of bu s control authori t y ow nership notification to release bus control autho rit y dat a address tx19a processor core intdre q [7 : 0 ] * dack [7 : 0]* port function control interrup t c ontrol l e r (exter nal req u e s t) haveit * busreq * busrel * external interrupt request internal i/ o interrupt request busgnt * (no t e ) in fig. 10.1, signals indi c a ted by * are internal sig n als. fig. 10-1 dm ac con n e c tions in the tm p19a43 the dm ac h a s ei ght dm a chan nel s . eac h o f t h e s e cha nnel s ha ndl es t h e dat a t r a n s f e r re que st si g n a l (i ntdr eo n) fr om t h e i n t e r r u p t c ont rol l e r an d t h e ac kn owl e dgm ent si gnal ( dac kn ) gene rat e d i n response to intdr e on, where " n " i s a chan nel n u m b er fr om 0 t o 7. e x t e r n al pi ns ( d r e q 0 a n d dreq4 ) are i n tern ally wired to allow t h em t o fun c tion as pin s o f th e p o rt f . t o use t h em as p i ns o f th e po rt f , t h ey m u st be sel ect e d b y set t i ng t h e f u nct i o n co nt r o l regi st er pf fc t o a n a p p r op ri at e set t i ng. pin s , da ck0 an d da ck4 , h a nd le th e d a t a tr an sf er r e q u est an d acknow ledg e sign al o u t p u t sup p lied t h r o u g h e x t e r n al pi ns, dr e q 0 a n d dr e q 4. c h a n nel 0 i s gi ve n hi ghe r p r i o ri t y t h an c h annel 1, cha n n e l 1 hi g h er pri o ri t y t h an cha n ne l 2 an d c h a nne l 2 hi ghe r pri o ri t y t h an c h an n e l 3. s u bse que nt cha n nel s are gi ve n pri o ri t y i n t h e sam e m a nne r . the t x 19 a pr ocess o r c o re h a s a sn o o p f u n c t i on. usi n g t h e sn oo p fu nct i on , t h e tx 1 9 a pr ocess o r co r e ope ns t h e core' s data bus t o the dmac, t h us allo wing the dmac to access th e internal rom and ram lin k e d to th e co re. th e dm ac is cap ab le of d e term in in g wh eth e r o r n o t t o u s e th is sno o p fun c tion . fo r fu rthe r in fo rm ation on the sn o o p f u nction , re fer t o 10 .2 .3 "s no o p f u nction . " t w o typ e s o f b u s con t ro l au th ority (sreq an d greq) are av ailab l e to th e dmac an d wh ich typ e of cont rol ri g h t t o use depe n d s o n t h e use o r n o n u se o f t h e sn oo p f unct i o n. gr e q i s a req u est f o r bu s co n t ro l au thority if th e dmac do es no t u s e th e sno o p fu nctio n , wh ile sreq is a requ est for bu s con t ro l aut h ori t y i f t h e dm ac use s t h e s n oo p fu nct i on. sr e q i s g i ven hi g h e r pri o ri t y t h a n gr e q . tmp19a43 (rev2.0 ) 10-2 dma control l er (dmac)
tmp19a43 10.2.2 dmac internal blocks fi g. 1 0 - 2 s h ow s t h e i n t e rnal b l ocks o f t h e d m ac . channel 3 channel 2 des t i nat i on address regi s t er da r x s ourc e address regi st er sa rx b y t e c ount regi s t er bs rx channel c ont rol regi st er ccrx 31 0 channel 0 dm a c ont rol regi s t er dcr dat a hol di ng regi s t er dhr channel s t a t us regi st er cs rx dm a t r ans f e r c ont rol regi st er dt cr x reques t s e l e c t regi s t er rs r x 0 t h rough 7 channel 4 channel 5 channel 6 channel 7 channel 1 fig. 10-2 dm ac internal b l ocks 10.2.3 snoop function the t x 1 9 a p r oces so r co re has a sn o op f unct i o n. if t h e snoop funct i on is activated, the t x 19a pr ocess o r co re ope ns t h e c o re' s dat a bus t o t h e dm ac a n d s u sp en ds i t s ow n o p e r at i o n u n t i l t h e dm ac withdra w s a re que st for bus c ont rol aut h ority . if t h e snoop function is enabled, t h e dm ac ca n access the internal r a m and r o m and th e r efore designate t h e r a m or r o m a s a s o urce or destination. if the snoop function is not us ed, the dm ac cannot access the internal ram or rom. howe ver , t h e g- bus is ope ne d to the dmac. if t h e t x 19a process o r co re atte m p ts to access m e m o ry or the i/ o by wa y of t h e g-b u s a n d i f t h e dm a c d o es n o t ac c e pt a b u s c ont r o l rel ease req u e st , bus ope rat i ons ca n not be execute d a n d, as a re sult, t h e pipeline stalls. (no t e ) if the sno op func tion is not used, the tx19a p roce ssor cor e do es not op en the dat a bus to the dmac. if the dat a bu s is closed an d the inter n a l ram or ro m is designa ted as a dm ac source o r de stina t ion, an ackno w l e dg ment signal w i ll n o t be re turne d in res ponse to a dmac tr ans f er bus c y cle and, as a res u lt, the bus w i ll loc k . tmp19a43 (rev2.0 ) 10-3 dma control l er (dmac)
tmp19a43 10.3 registers the dm ac ha s fi ft y - one 3 2 - bi t re gi st ers. t a bl e 1 0 . 1 sh o w s t h e regi st er m a p of t h e dm a c . t able 10.1 dmac re giste r s a d d r e ss reg i ster s y m b o l reg i ster n a m e 0 x f f f f _ e 2 0 0 c c r 0 channel cont ro l register (ch . 0) 0 x f f f f _ e 2 0 4 c s r 0 channel st atus r e gister (ch . 0) 0xffff_e208 sar0 source addr ess r e gister (ch . 0) 0 x f f f f _ e 2 0 c d a r 0 destination addr ess register (ch . 0) 0xffff_e210 bcr0 b y te count regis t er ( c h. 0) 0xffff_e218 dtcr0 dma transfer control r e gister (ch. 0) 0 x f f f f _ e 2 2 0 c c r 1 channel cont ro l register (ch . 1) 0 x f f f f _ e 2 2 4 c s r 1 channel st atus r e gister (ch . 1) 0xffff_e228 sar1 source addr ess r e gister (ch . 1) 0 x f f f f _ e 2 2 c d a r 1 destination addr ess register (ch . 1) 0xffff_e230 bcr1 b y te count regis t er ( c h. 1) 0xffff_e238 dtcr1 dma transfer control r e gister (ch. 1) 0 x f f f f _ e 2 4 0 c c r 2 channel cont ro l register (ch . 2) 0 x f f f f _ e 2 4 4 c s r 2 channel st atus r e gister (ch . 2) 0xffff_e248 sar2 source addr ess r e gister (ch . 2) 0 x f f f f _ e 2 4 c d a r 2 destination addr ess register (ch . 2) 0xffff_e250 bcr2 b y te count regis t er ( c h. 2) 0xffff_e258 dtcr2 dma transfer control r e gister (ch. 2) 0 x f f f f _ e 2 6 0 c c r 3 channel cont ro l register (ch . 3) 0 x f f f f _ e 2 6 4 c s r 3 channel st atus r e gister (ch . 3) 0xffff_e268 sar3 source addr ess r e gister (ch . 3) 0 x f f f f _ e 2 6 c d a r 3 destination addr ess register (ch . 3) 0xffff_e270 bcr3 b y te count regis t er ( c h. 3) 0xffff_e278 dtcr3 dma transfer control r e gister (ch. 3) 0 x f f f f _ e 2 8 0 c c r 4 channel cont ro l register (ch . 4) 0 x f f f f _ e 2 8 4 c s r 4 channel st atus r e gister (ch . 4) 0xffff_e288 sar4 source addr ess r e gister (ch . 4) 0 x f f f f _ e 2 8 c d a r 4 destination addr ess register (ch . 4) 0xffff_e290 bcr4 b y te count regis t er ( c h. 4) 0xffff_e298 dtcr4 dma transfer control r e gister (ch. 4) 0xffff_e2a0 c c r 5 channel c ontro l register (ch . 5) 0xffff_e2a4 c s r 5 channel st atus r e gister (ch . 5) 0xffff_e2a8 sar5 source addr ess r e gister (ch . 5) 0xfff f_e2ac d a r 5 destination addr ess register (ch . 5) 0xffff_e2b0 bcr5 b y te count regis t er ( c h. 5) 0xffff_e2b8 dtcr5 dma transfer control r e gister (ch. 5) 0xffff_e2c0 ccr6 channel contro l register (ch . 6) 0xffff_e2c4 csr6 channel status r e gister (ch . 6) 0xffff_e2c8 sar6 source addr ess r e gister (ch . 6) 0 x f f f f _ e 2 c c d a r 6 destination a ddr ess register (ch . 6) 0xffff_e2d0 bcr6 b y te count regis t er ( c h. 6) 0xffff_e2d8 dtcr6 dma transfer control r e gister (ch. 6) tmp19a43 (rev2.0 ) 10-4 dma control l er (dmac)
tmp19a43 t able 10.2 dmac re giste r s (co n tinue d) 0xffff_e2e0 ccr7 channel contro l register (ch . 7) 0xffff_e2e4 csr7 channel status r e gister (ch . 7) 0xffff_e2e8 sar7 source addr ess r e gister (ch . 7) 0 x f f f f _ e 2 e c d a r 7 destination addr ess register (ch . 7) 0xffff_e2f0 bcr7 b y te count regis t er ( c h. 7) 0xffff_e2f8 dtcr7 dma transfer control r e gister (ch. 7) 0xffff_e300 dcr dma control r e gister (dmac) 0 x f f f f _ e 3 0 4 r s r request se lect r e gister (dmac) 0xffff_e30c dhr data ho lding reg i ster (dmac) tmp19a43 (rev2.0 ) 10-5 dma control l er (dmac)
tmp19a43 10.3.1 dma control register (dcr) 7 6 5 4 3 2 1 0 d c r bit s y m b o l r s t 7 r s t 6 r s t 5 r s t 4 r s t 3 r s t 2 r s t 1 r s t 0 (0xff ff_e30 0 h ) r e a d / w r i t e w a f t e r r e s e t 0 function see detailed description. 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t s y m b o l r e a d / w r i t e w a f t e r r e s e t 0 f u n c t i o n 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t s y m b o l r e a d / w r i t e w a f t e r r e s e t 0 f u n c t i o n 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t s y m b o l r s t a l l r e a d / w r i t e w a f t e r r e s e t 0 f u n c t i o n s ee det ail ed des cr ipt i o n . b i t m n e m onic fie l d na me de sc r i p t i o n 3 1 r s t a l l r e s e t a l l performs a software r e set of th e dmac. if th e r s tall bit is set to 1, the va lu es of all the in ter n al r e gisters of t h e dmac are r e set to the i r initi al valu es. al l tr ansfer r e quest s are canc e led and a ll eight chann e ls g o into an idl e s t a t e. 0: don't car e 1: ini tia liz es th e dmac 7 r s t 7 r e s e t 7 performs a software r e set of th e dmac channel 7. if th e rst7 bit is set to 1, in tern al r e gist ers of th e dmac chann e l 7 and a corr esponding bit of the channel 7 of th e rsr register are r e s e t to the i r initi al valu es . t h e tr ans f er r e que s t of th e channe l 7 is c a n cel ed and th e ch annel 7 go es into an idl e sta t e. 0: don't car e 1: ini tia liz es th e dmac channel 7 6 r s t 6 r e s e t 6 performs a software r e set of th e dmac channel 6. if th e rst6 bit is set to 1, in tern al r e gist ers of th e dmac chann e l 6 and a corr esponding bit of the channel 6 of th e rsr register are r e s e t to the i r initi al valu es . t h e tr ans f er r e que s t of th e channe l 6 is c a n cel ed and th e ch annel 6 go es into an idl e sta t e. 0: don't car e 1: ini tia liz es th e dmac channel 6 5 r s t 5 r e s e t 5 performs a software r e set of th e dmac channel 5. if th e rst5 bit is set to 1, in tern al r e gist ers of th e dmac chann e l 5 and a corr esponding bit of the channel 5 of th e rsr register are r e s e t to the i r initi al valu es . t h e tr ans f er r e que s t of th e channe l 5 is c a n cel ed and th e ch annel 5 go es into an idl e sta t e. 0: don't car e 1: ini tia liz es th e dmac channel 5 tmp19a43 (rev2.0 ) 10-6 dma control l er (dmac)
tmp19a43 b i t m n e m onic fie l d na me de sc r i p t i o n 4 r s t 4 r e s e t 4 performs a software r e set of th e dmac channel 4. if th e rst4 bit is set to 1, in tern al r e gist ers of th e dmac chann e l 4 and a corr esponding bit of the channel 4 of th e rsr register are r e s e t to the i r initi al valu es . t h e tr ans f er r e que s t of th e channe l 4 is c a n cel ed and th e ch annel 4 go es into an idl e sta t e. 0: don't car e 1: ini tia liz es th e dmac channel 4 3 r s t 3 r e s e t 3 performs a software r e set of th e dmac channel 3. if th e rst3 bit is set to 1, in tern al r e gist ers of th e dmac chann e l 3 and a corr esponding bit of the channel 3 of th e rsr register are r e set to the i r initi al valu es. th e tr ansfer r e ques t of the channe l 3 is c a n cel ed and th e ch annel 3 go es into an idl e sta t e. 0: don't car e 1: ini tia liz es th e dmac channel 3 2 r s t 2 r e s e t 2 performs a software r e set of th e dmac channel 2. if th e rst2 bit is set to 1, in tern al r e gist ers of th e dmac chann e l 2 and a corr esponding bit of the channel 2 of th e rsr register are r e set to the i r initi al valu es. th e tr ansfer r e ques t of the channe l 2 is c a n cel ed and th e ch annel 2 go es into an idl e sta t e. 0: don't car e 1: ini tia liz es th e dmac channel 2 1 r s t 1 r e s e t 1 performs a software r e set of th e dmac channel 1. if th e rst1 bit is set to 1, in tern al r e gist ers of th e dmac chann e l 1 and a corr esponding bit of the channel 1 of th e rsr register are r e s e t to the i r initi al valu es . t h e tr ans f er r e que s t of th e channe l 1 is c a n cel ed and th e ch annel 1 go es into an idl e sta t e. 0: don't car e 1: ini tia liz es th e dmac channel 1 0 r s t 0 r e s e t 0 performs a software r e set of th e dmac channel 0. if th e rst0 bit is set to 1, in tern al r e gist ers of th e dmac chann e l 0 and a corr esponding bit of the channel 0 of th e rsr register are r e set to the i r initi al valu es. th e tr ansfer r e ques t of the channe l 0 is c a n cel ed and th e ch annel 0 go es into an idl e sta t e. 0: don't car e 1: ini tia liz es th e dmac channel 0 fig. 10-3 dm a control re gister (dcr) (no t e 1 ) if a w r i t e to the dcr regi ster oc curs during a sof t w a r e re set ri ght af ter th e last round o f dma trans f er is c o mpleted, th e interrup t to stop dma transfer is no t canc eled al though the channel register is initializ ed. (no t e 2 ) an attemp t to execu te a w r i t e (sof t w a r e rese t) to the dcr regi ster b y dma trans f er mus t be strictly a v oided. tmp19a43 (rev2.0 ) 10-7 dma control l er (dmac)
tmp19a43 10.3.2 channel control registers (ccrn) 7 6 5 4 3 2 1 0 c c r n b i t s y m b o l s a c d i o d a c t r s i z d p s (0xff ff_e20 0 h ) r e a d / w r i t e r / w r / w r / w r / w r / w (0x f f ff_e 2 2 0 h ) a fter res e t 0 (0xff ff_e24 0 h ) f u n c t i o n s e e detailed description . alw a y s set this bit to ?0?. see detailed description (0xff ff_e26 0 h ) 1 5 1 4 1 3 1 2 1 1 1 0 9 8 (0xff ff_e28 0 h ) b i t s y m b o l e x r p o s e l e v s r e q r e l e n s i o s a c (0xff ff_e2a0 h ) r e a d / w r i t e r / w r / w r / w r / w r/ w r / w r / w r / w (0x f f ff_e 2 c 0 h ) a fter res e t 0 (0xff ff_e2e0 h ) f u n c t i o n alw a y s s e t this bit to "0." see detailed description. 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t s y m b o l n i e n a b l e n b i g r e a d / w r i t e r / w r / w r / w r / w r / w r / w r / w r / w a f t e r r e s e t 1 0 1 0 f u n c t i o n s e e d e t a i l e d description. alw a y s set this bi t to "0." s ee d e t a il ed des cr ipt i o n . alw a y s s e t t h i s b i t to " 0 ." 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t s y m b o l s t r r e a d / w r i t e w w a f t e r r e s e t 0 f u n c t i o n s ee det ail ed des cr ipt i o n . alw a y s s e t t h i s b i t to " 0 ." fig. 10-4 tmp19a43 (rev2.0 ) 10-8 dma control l er (dmac)
tmp19a43 b i t m n e m onic fie l d na me de sc r i p t i o n 31 str channel start start ( i nitial valu e:?) starts ch annel o p erat ion. if th is bit is set to 1 , th e ch anne l goes i n to a standb y mode and starts to tran sfer data in response to a tr ansfer requ est. only a write of 1 is valid to the str bit and a wr ite of 0 is ignored . a read alway s returns a 0. 1: star ts ch annel operation 24 ? (res erved) this is a r e s e rve d bi t . alwa ys se t this b it to "0 ." 2 3 n i e n norm al com p leti on interrup t en abl e norm al com p let i on int e rrupt en able (ini tia l v a lu e: 1) 1: norm al com p letion in terrupt e n able 0: norm al com p letion in terrupt d i sable 2 2 a b i e n abnormal com p letion int e r r upt enabl e abnormal completion interrupt enable (in itial v a lue: 1) 1: abnormal co mpletion interru pt en able 0: abnormal co mpletion interru pt disab l e 21 ? (reserved) this is a r e served bit. alth ough its in itial value is "1," alway s set this bit to "0 ." 20 ? (res erved) this is a r e s e rve d bi t . alwa ys se t this b it to "0 ." 19 ? (res erved) this is a r e s e rve d bi t . alwa ys se t this b it to "0 ." 18 ? (res erved) this is a r e s e rve d bi t . alwa ys se t this b it to "0 ." 17 big big-endian big endian ( i nitial v a lue: 1) 1: a ch annel op erates b y big- endian 0: a ch anne l op e r ates b y l ittl e-en dian 16 ? (res erved) this is a r e s e rve d bi t . alwa ys se t this b it to "0 ." 15 ? (res erved) this is a r e s e rve d bi t . alwa ys se t this b it to "0 ." 1 4 e x r extern al r e quest mode extern al r e ques t mode ( i nitial v a lue: 0) se l e ct s a t r a n sfer re que st m ode. ( only for 0 c h and 4ch) 1: ex ternal trans f er r e quest ( i nter r upt requ est or external dreqn request) 0: int e rnal tr ans f er requ es t (s oftw are init iat e d) 13 pose positive edge positive e dge ( i nitia l v a lue : 0) the effe ctiv e lev e l of th e tr ansfer request signa l i n tdreqn or dreqn is specifi ed. this f unction is va lid onl y if the tr ans f er requ es t is an e x terna l tr ans f er request ( i f the e x r bit is 1) . if it is an in terna l tra n sfer requ est (if the exr bi t is 0), th e pose v a lue is ignored . b e cause the intdreqn and dreqn signals are act ive at "l" l e v e l, m a ke sur e th a t this pose bit is set to "0." 1: setting p r ohibited 0: the f a lling edge of the intdreqn or dreqn signal or th e "l" level is effec tive . the dackn is act ive at "l" lev e l . 12 lev level mode level m ode (initial valu e: 0) s p ecifi es which is us ed to re cogn ize the ex tern al t r ans f er r e ques t , s i gnal lev e l or signal change. this setting is va lid onl y if a tr an sfer requ est is th e ex tern al transfer request ( i f th e exr bi t is 1). if th e inte rna l tr ansfer r e quest is spec ifi e d as a tr ans f er r e ques t (if th e exr bi t i s 0), th e v a lu e of the lev bit is ig nored. b e cause the intdreqn signal is a c tiv e a t "l" leve l, m a ke sure th at you se t the l e v bi t to "1." the sta t e o f act ive dreqn is det e rm ined b y t h e l e v b it se ttin g. 1: level mode the level of th e dreqn signal is recogn iz ed as a data trans f er r e q u es t. (the " l " l e vel is recogn iz ed if th e pose bi t is 0. 0: edge mode a change in th e dreqn s i gnal is recogn iz ed as a data trans f er r e q u es t. (a falling edge is recognized if the pose bit is 0.) 11 sreq snoop request snoop reque st ( i nitial valu e: 0) the use of the snoop function is specified b y asserting the bus con t rol r e quest mode. if the snoop function is used, the snoop fu nction of th e tx19a processor core is en abled and the dmac can use the data b u s of the tx19a processor core. if the snoop function is not us ed, the snoop fun c tion of th e tx19a processor cor e does not work . 1: use snoop fun c tion (sreq) 0: do not use sn oop function (g req) tmp19a43 (rev2.0 ) 10-9 dma control l er (dmac)
tmp19a43 b i t m n e m onic fie l d na me de sc r i p t i o n 1 0 r e l e n bus control re le as e reques t enab le rele ase requ est enab le (ini tia l v a lue : 0) acknowledgment of the bus con t rol r e lease r e qu est made b y th e tx19a processor core is spec ified . this fun c tion is valid onl y if gr eq is gen e ra ted . if sreq is generated , th e tx19a processor core ca nno t mak e a bus con t rol r e lease r e quest and, ther efore, this function can not be used. 1: the bus contro l release r e quest is ac knowledg ed if th e dmac has control of the bus. if the tx19a processor core issues a bus contro l r e lease r e quest, th e dmac relinquis h es contro l of th e bus to th e tx19a processor co re during a pause in bus operation . 0: the bus contro l release r e quest is not acknowled g ed. 9 s i o trans f er t y pe selec tion trans f er t y pe s e l ect ion: ( i nit i al v a lue : 0) 1 single transf er 0: continuous tr ansfer (da t a is tr ansferred succes sivel y un til bcr x becom e s "0") 8 : 7 sac source addr ess count source a ddress count (initial v a lue: 00) s p ecifi es the m a nner of chang e i n a s our ce addre s s . 1x: address fix e d 01: address decr ease 00: addres s in cr eas e 6 - (reserved) this is a r e served bit . alwa ys se t this b it to ? 0 ? . 5 : 4 dac destination addr ess count destination add r ess count (in itial v a lue: 00) s p ecifi es the m a nner of chang e i n a d e s tin ation a ddres s . 1x: address fix e d 01: address decr ease 00: addres s in cr eas e fig. 10-5 cha nnel control r egi sters (ccrn) (2 of 3) tmp19a43 (rev2.0 ) 10-10 dma control l er (dmac)
tmp19a43 b i t m n e m onic fie l d na me de sc r i p t i o n 3 : 2 trsiz transfer unit transfer size (in itia l v a lue : 00) specifies the am ount of d a ta to b e tr ansf erred in r e sponse to on e tr ansfer r e quest. 11: 8 b its (1 b y te) 10: 16 b its (2 b y tes) 0x: 32 b its (4 b y tes) *m ake s u re to s e t th e s a m e s i ze a s the d e vi ce p o rt s i ze (dp s ) . 1 : 0 dps device port size device port si ze (ini tia l v a lue : 0 0 ) specifies the bus width of an i/o device d e signated as a source or destination device. 11: 8 b its (1 b y te) 10: 16 b its (2 b y tes) 0x: 32 b its (4 b y tes) *m ake s u re to s e t th e s a m e s i ze a s the trans f er uni t (trs i z ) fig. 10-6 cha nnel control r egi sters (ccrn) (3 of 3) (no t e 1 ) the ccrn re gister se ttin g must be c o mpleted be fore the dm ac is pu t into a st andby mode. (no t e 2 ) when a cce s s ing the inte rnal i/o or transferring d a t a b y dma in respon se to the dreq pin reques t , make sure that y o u set the transfer unit and the dev i ce port size to the same si ze. (no t e 3 ) in execu ting memor y -to-memor y dat a trans f e r , a v a lue set in dps become s in v a lid. tmp19a43 (rev2.0 ) 10-1 1 dma control l er (dmac)
tmp19a43 10.3.3 request select register (rsr) 7 6 5 4 3 2 1 0 r s r bit s y m b o l r e q s 4 r e q s 0 (0xff ff_e30 4 h ) r e a d / w r i t e r / w r / w a f t e r r e s e t 0 function alw a y s set this bi t to "0." see detailed description. alw a y s set this bi t to "0." see detailed description. 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t s y m b o l r e a d / w r i t e a f t e r r e s e t 0 f u n c t i o n 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t s y m b o l r e a d / w r i t e a f t e r r e s e t 0 f u n c t i o n 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t s y m b o l r e a d / w r i t e a f t e r r e s e t 0 f u n c t i o n fig. 10-7 b i t m n e m onic fie l d na me de sc r i p t i o n 4 reqs4 request se lec t ( c h.4) request se lec t ( i nitia l v a lue : 0) selec t s a source of the ex terna l tr ansfer r e quest f o r the dma channel 4. 1: requ est made b y dreq4 0: requ est m a de b y th e interrup t controll er ( i ntc ) 0 reqs0 request se lec t ( c h.0) request se lec t ( i nitia l v a lue : 0) selec t s a source of the ex terna l tr ansfer r e quest f o r the dma channel 0. 1: requ est made b y dreq0 0: requ est m a de b y th e interrup t controll er ( i ntc ) (no t e ) make sur e th at y ou w r i t e "0" to bit s 1 throug h 3 an d 5 throug h 7 of the rsr registe r . fig.10-8 dma control regi ster (rs r ) tmp19a43 (rev2.0 ) 10-12 dma control l er (dmac)
tmp19a43 tmp19a43 (rev2.0) 10-13 dma controller (dmac) 10.3.4 channel status registers (csrn) 7 6 5 4 3 2 1 0 csrn bit symbol (0xffff_e204h) read/write r/w (0xffff_e224h) after reset 0 (0xffff_e244h) function always set this bit to "0." (0xffff_e264h) 15 14 13 12 11 10 9 8 (0xffff_e284h) bit symbol (0xffff_e2a4h) read/write (0xffff_e2c4h) after reset 0 (0xffff_e2e4h) function 23 22 21 20 19 18 17 16 bit symbol nc abc bes bed conf read/write r/w r/w r/w r r r after reset 0 function see detailed description. always set this bit to "0." see detailed description. 31 30 29 28 27 26 25 24 bit symbol act read/write r after reset 0 function see detailed description . fig. 10-9 channel status registers (csrn)
tmp19a43 b i t m n e m onic fie l d na me de sc r i p t i o n 31 act channel activ e channel activ e (initial valu e: 0) indicates whether the ch annel is in a standb y mod e : 1: in a standb y mode 0: not in a stand b y mode 23 nc norm al com p leti on norm al com p let i on (in iti al v a lu e : 0) indicates normal completion of cha nnel oper a tion . if an interrupt at norm a l com p l e tion is pe rm itte d b y th e ccr re gister, th e dmac requests an in terrupt when the nc bit becomes 1. this set ting can be c l e a red b y wr iting 0 to th e nc bit . if a requ est for an int e rrupt a t norm a l com p le tion was pr eviou s l y issued, the request is c a nc el ed if th e nc b it becom e s 0. if an at tem p t is m a de to set the str bit to 1 when the nc bi t is 1, an erro r oc curs . to s t ar t th e n e xt trans f er, th e nc bit m u s t be cleared to 0 . a write of 1 will b e ignor ed. 1: chann e l op er ation has b een completed normally . 0: chann e l op er ation has not been completed nor mally . 22 abc abnormal completion a bnormal completion (in itial value: 0) indicates abnor mal completion of chann e l oper a tion. if an interrup t a t abno rm al com p let i on is perm it ted b y t h e ccr regis t er , the dm ac reques t s an i n terrupt when th e abc bi t becom e s 1. this set ting can be c l e a red b y wr iting 0 to th e ab c bit . if a request for an in terrupt at abnormal completion w a s previously is s u ed, th e r e que s t is c a nc eled if t h e abc bi t b eco m e s 0. additional l y , if t h e abc bi t is cl e a red to 0 , ea ch o f the bes, bed and conf b its ar e cleared to 0 . if an at tem p t is m a de to set the str bit to 1 when the abc bi t is 1 , an erro r oc curs . to s t ar t th e n e xt trans f er, th e ab c bit m u s t be cleared to 0 . a write of 1 will b e ignor ed. 1: chann e l op er ation has b een completed abnor mally . 0: chann e l op er ation has not been completed abn o rmally . 21 ? (res erved) this is a r e s e rve d bi t . alwa ys se t this b it to "0 ." 20 bes source bus error source bu s erro r (initial v a lue: 0 ) 1: a bus error h a s occurr ed when the s ourc e was a cces s e d. 0: a bus error h a s not occurred w h en th e source w a s accessed. 19 bed destination bus error destination bus error (in iti al val u e: 0) 1: a bus error h a s occurr ed when the d e s tina tion was ac ces s e d. 0: a bus error h a s not occurred w h en th e d e stination was acc es s e d. 1 8 c o n f configuration er r o r confi guration er ror (ini tia l v a lue : 0) 1: a conf iguration error has o c curred. 0: a conf iguration error has not occurred . 2 : 0 ? (res erved) thes e thre e bi ts are r e s e rved bi ts . alwa y s s e t the m to "0." fig. 10-1 0 ch annel s t atu s regi sters (csrn) tmp19a43 (rev2.0 ) 10-14 dma control l er (dmac)
tmp19a43 10.3.5 source add r ess registers (sarn) 7 6 5 4 3 2 1 0 s a r n b i t s y m b o l s a d d r 7 saddr6 saddr 5 s a d d r 4 s a d d r 3 s a d d r 2 s a d d r 1 saddr0 (0xff ff_e20 8 h ) r e a d / w r i t e r / w (0xff ff_e22 8 h ) a f t e r r e s e t i n d e t e r m i n a t e (0xff ff_e24 8 h ) function see detailed description. (0xff ff_e26 8 h ) 1 5 1 4 1 3 1 2 1 1 1 0 9 8 (0xff ff_e28 8 h ) b i t s y m b o l s a d d r 1 5 saddr 14 saddr13 saddr12 saddr11 s a d d r 1 0 s a d d r 9 saddr8 (0xff ff_e2a8 h ) r e a d / w r i t e r / w (0xff ff_e2c 8 h ) a f t e r r e s e t i n d e t e r m i n a t e (0xff ff_e2e8 h ) function see detailed description. 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t s y m b o l s a d d r 2 3 saddr22 saddr21 saddr20 saddr19 s a d d r 1 8 s a d d r 1 7 saddr16 r e a d / w r i t e r / w a f t e r r e s e t i n d e t e r m i n a t e function see detailed description. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t s y m b o l s a d d r 3 1 saddr30 saddr29 saddr28 saddr27 s a d d r 2 6 s a d d r 2 5 saddr24 r e a d / w r i t e r / w a f t e r r e s e t i n d e t e r m i n a t e function see detailed description. fig. 10-1 1 b i t m n e m onic fie l d na me de sc r i p t i o n 31 : 0 saddr source addr ess source address (i niti al valu e: ? ) s p ecifi es the ad dres s of th e s our ce from whi c h d a ta is trans f erred us ing a ph ys i c a l ad dre s s . this addres s changes accord ing to th e sac and trsiz s e ttings of ccrn and th e sacm setting o f dtcrn. fig. 10-1 2 source add r e ss regi ster (sarn) tmp19a43 (rev2.0 ) 10-15 dma control l er (dmac)
tmp19a43 10.3.6 destination address register (darn) 7 6 5 4 3 2 1 0 d a r n b i t s y m b o l d a d d r 7 daddr6 d addr 5 d a d d r 4 d a d d r 3 d a d d r 2 d a d d r 1 daddr0 (0xff ff_e20 c h ) r e a d / w r i t e r / w (0xff ff_e22 c h ) a f t e r r e s e t i n d e t e r m i n a t e (0xff ff_e24 c h ) function see detailed description. (0xff ff_e26 c h ) 1 5 1 4 1 3 1 2 1 1 1 0 9 8 (0xff ff_e28 c h ) b i t s y m b o l d a d d r 1 5 daddr 14 daddr13 daddr12 daddr11 d a d d r 1 0 d a d d r 9 daddr8 (0xff ff_e2ac h ) r e a d / w r i t e r / w (0xff ff_e2c c h ) a f t e r r e s e t i n d e t e r m i n a t e (0xff ff_e2ec h) function see detailed description. 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t s y m b o l d a d d r 2 3 daddr22 daddr21 daddr20 daddr19 d a d d r 1 8 d a d d r 1 7 daddr16 r e a d / w r i t e r / w a f t e r r e s e t i n d e t e r m i n a t e function see detailed description. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t s y m b o l d a d d r 3 1 daddr30 daddr29 daddr28 daddr27 d a d d r 2 6 d a d d r 2 5 daddr24 r e a d / w r i t e r / w a f t e r r e s e t i n d e t e r m i n a t e function see detailed description. fig. 10-1 3 b i t m n e m onic fie l d na me de sc r i p t i o n 31 : 0 daddr destination addr ess destination add r ess (init i al va lu e: ? ) specifi es the ad dress of th e dest i n ation to whi c h data is trans f erred us ing a ph ys i c a l ad dre s s . this addres s changes accord ing to th e dac and trs i z settings of ccr n and the dacm setting of dtcrn. fig. 10-1 4 de stination ad dress re giste r (da r n) tmp19a43 (rev2.0 ) 10-16 dma control l er (dmac)
tmp19a43 10.3.7 by te count registers (bcrn) 7 6 5 4 3 2 1 0 b c r n b i t s y m b o l b c 7 b c 6 b c 5 b c 4 b c 3 b c 2 b c 1 b c 0 (0xff ff_e21 0 h ) r e a d / w r i t e r / w (0x f f ff_e 2 3 0 h ) a fter res e t 0 (0xff ff_e25 0 h ) function see detailed description. (0xff ff_e27 0 h ) 1 5 1 4 1 3 1 2 1 1 1 0 9 8 (0xff ff_e29 0 h ) b i t s y m b o l b c 1 5 b c 1 4 b c 1 3 b c 1 2 b c 1 1 b c 1 0 b c 9 b c 8 (0xff ff_e2b0 h ) r e a d / w r i t e r / w (0x f f ff_e 2 d 0 h ) a fter res e t 0 (0xff ff_e2 f0h ) function see detailed description. 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t s y m b o l b c 2 3 b c 2 2 b c 2 1 b c 2 0 b c 1 9 b c 1 8 b c 1 7 b c 1 6 r e a d / w r i t e r / w a f t e r r e s e t 0 function see detailed description. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t s y m b o l r e a d / w r i t e a f t e r r e s e t 0 f u n c t i o n fig. 10-1 5 b i t m n e m onic fie l d na me de sc r i p t i o n 23 : 0 bc b y te count b y te coun t (in itial v a lue: 0) specifies the nu mber of b y tes of data to be tr ansferred. th e address decreases b y the num ber of pieces of data trans f erred (a value specified b y trsiz of c crn). fig. 10-1 6 byte count regi ster (b crn) tmp19a43 (rev2.0 ) 10-17 dma control l er (dmac)
tmp19a43 10.3.8 dma t r ansfer control register (dtcrn) 7 6 5 4 3 2 1 0 d t c r n b i t s y m b o l d a c m s a c m (0xff ff_e21 8 h ) r e a d / w r i t e r / w r / w (0x f f ff_e 2 3 8 h ) a fter res e t 0 (0xff ff_e25 8 h ) function see detailed description. see detailed description. (0xff ff_e27 8 h ) 1 5 1 4 1 3 1 2 1 1 1 0 9 8 ( 0 xffff_e29 8 h ) b i t sy m b o l (0xff ff_e2b8 h ) r e a d / w r i t e (0x f f ff_e 2 d 8 h ) a fter res e t 0 (0x f f ff_e2 f8h ) f u n c t i o n 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t s y m b o l r e a d / w r i t e a f t e r r e s e t 0 f u n c t i o n 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t s y m b o l r e a d / w r i t e a f t e r r e s e t 0 f u n c t i o n fig. 10-1 7 b i t m n e m onic fie l d na me de sc r i p t i o n 5 : 3 dacm destination addr ess count mode destination add r ess count mod e specifies the co unt mode of the destination addr ess. 000: counting b e gins from bit 0 001: counting b e gins from bit 4 010: counting b e gins from bit 8 011: counting b e gins from bit 1 2 100: counting b e gins from bit 1 6 101: setting pro h ibited 110: setting pro h ibited 111: setting pro h ibited 2 : 0 sacm source addr ess count mode source address count mode s p ecifi es the co unt m ode of the s ource add r es s . 000: counting b e gins from bit 0 001: counting b e gins from bit 4 010: counting b e gins from bit 8 011: counting b e gins from bit 1 2 100: counting b e gins from bit 1 6 101: setting pro h ibited 110: setting pro h ibited 111: setting pro h ibited fig. 10-1 8 dma t r an sfe r control re gister (dtcrn ) tmp19a43 (rev2.0 ) 10-18 dma control l er (dmac)
tmp19a43 10.3.9 dat a holding register (dhr) 7 6 5 4 3 2 1 0 d h r b i t s y m b o l dot 7 dot 6 dot 5 dot 4 d o t 3 dot 2 dot 1 dot 0 (0xff ff_e30 c h ) r e a d / w r i t e r / w a f t e r r e s e t 0 function see detailed description. 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t s y m b o l dot 1 5 dot 1 4 d ot 13 dot 1 2 dot 1 1 dot 1 0 dot 9 dot 8 r e a d / w r i t e r / w a f t e r r e s e t 0 function see detailed description. 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t s y m b o l dot 2 3 dot 2 2 dot 2 1 dot 2 0 d o t 1 9 dot 1 8 dot 1 7 dot 1 6 r e a d / w r i t e r / w a f t e r r e s e t 0 function see detailed description. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t s y m b o l dot 3 1 dot 3 0 dot 2 9 d ot 2 8 d o t 2 7 dot 2 6 dot 2 5 dot 2 4 r e a d / w r i t e r / w a f t e r r e s e t 0 function see detailed description. fig. 10-1 9 b i t m n e m onic fie l d na me de sc r i p t i o n 31 : 0 dot data on tr ansfer data on tr ansfer (ini tia l v a lue : 0) data that is r ead from the s ourc e i n a du al- a ddres s data trans f er m ode fig. 10-2 0 da t a holdi ng re gister (dhr) tmp19a43 (rev2.0 ) 10-19 dma control l er (dmac)
tmp19a43 10.4 functions th e dmac is a 32 -b it dm a co n t ro ller cap ab le of tran sferrin g d a ta in a sy ste m u s in g th e tx1 9 a pro cesso r core at hi g h s p ee ds wi t h o u t ro ut i n g dat a vi a t h e c o re . 10.4.1 overview (1 ) so urce an d des t i n at i on the dm ac h a ndl es dat a t r a n sfe r s f r o m mem o ry t o m e m o ry and bet w een m e m o ry and a n i/ o devi ce. a de vi ce fr om whi c h dat a i s t r ans f er red i s cal l e d a sou r ce devi ce and a de vi ce t o whi c h dat a is tran sferred i s called a d e sti n atio n d e v i ce. bo th m e m o ry and i/ o device s can be designated as a sou r ce o r dest i n at i o n de vi ce. the dm ac su pp o r t s dat a t r a n sfe r s fr om m e m o ry t o i/ o de vi ces, fr o m i/ o de vi ces t o m e m o ry , and f r o m m e m o ry t o m e m o ry , but n o t bet w een i/ o de vi ces. the dif f ere n ce s bet w een m e m o ry and i/o de vi ces a r e i n the way they are access e d. when accessing an i/ o de vice, t h e dmac asse rts a dack n signal. because there is only one line per channel t h at ca rries a dackn si gnal, the num b er of i/o devices accessi ble during data trans f er is l i m i t e d t o one . there f ore, dat a can not be t r an sfer red bet w ee n i/ o de vi ces. an i n terrup t facto r can b e attach ed t o a tran sfer requ est to b e sen t to t h e dmac. if an in terrup t fact or i s ge ne r a t e d, t h e i n t e r r upt c o nt rol l e r (i ntc ) i s s u es a re quest t o t h e dm ac (t h e tx 19a p r o cesso r co re is no t no tified of th e in terrup t re qu est. fo r d e tails, see descrip tion on interrup t s.). the re quest iss u ed by the intc is cleared by th e d a c k n si gnal . the r ef ore , a re qu est m a de t o t h e dmac is clea red afte r c o m p letion of ea ch data tran s f er (t ra nsfe r of t h e am ou nt of dat a s p eci fi ed by t r siz) if a sing le tran sfer is d e sign ated to sel ect a t r a n s f er t y pe (si o b i t). on t h e ot he r ha nd , d u ring a con tin uou s tran sfer , th e dac kn sig n a l is a s s e rted only when the num b er of bytes tran sferred (v alu e set i n th e bcrn reg i ster) b eco m e s "0 ." th erefore, one tr ansfer request allo ws dat a t o be t r an s f er red succe ssi vel y wi t h out a pau s e. fo r ex am p l e, if d a ta is tran sferre d b e tween a in tern al i/ o an d th e in tern al (ex t ern a l) m e m o ry o f t h e tmp19 a 43 , a requ est m a d e b y th e in tern al i/o to th e dmac is cleared after co m p letio n o f each dat a t r ans f e r a nd t h e t r a n sfe r ope rat i o n i s al way s p u t i n a s t and b y m ode f o r t h e ne xt t r a n sfer req u est if th e nu m b er o f b y tes tran sferred (v alu e set in th e bcrn reg i ster) do es n o t beco m e "0 ." th erefore, th e dm a t r an sfer op eration co n tinu e s un til th e v a lu e of th e bcrn reg i ster b e co m e s "0 ." (2) bu s co n t ro l arb itratio n (bu s arb itration ) in res p onse t o a t r ans f er re q u e st m a de i n si de the dm ac, the dm ac req u es ts th e tx19a p r o cessor core t o a r bi t r a t e bu s c ont r o l au thor ity . w h en a r e spon se sign al is r e tu rn ed fro m th e cor e , th e dmac acqu ires bu s con t ro l au tho r ity and e x ecutes a data trans f er bus cycle. in ac q u i r i n g bu s co nt rol fo r t h e dm ac , use or n o n u se of t h e dat a b u s of t h e tx 19 a pr oc essor co re can b e sp ecif i ed ; sp ecif i cally eith er sn oop m o d e or no n- snoo p m o d e can b e sp ecif i ed fo r each ch ann e l b y usin g b it 1 1 (sreq ) of th e ccrn reg i ster . there a r e case s in which the tx19a proce ssor c o re re quests the releas e of bus control authority . whet her or no t t o res p on d t o t h i s re q u est c a n be s p eci fi e d f o r eac h c h a nnel by usi n g t h e bi t 10 (relen ) o f the ccrn reg i ster . ho wev e r , th is fun c tio n can on ly b e used i n no n-sno op m o d e (gr e q) . i n s n o o p m ode (s r e q) , t h e tx 19 a pr ocess o r core ca nn ot r e que st t h e rel e ase of bu s cont rol a n d, t h eref ore , t h i s f u nct i o n can n o t be use d . whe n t h ere are no m o re tra n sfer re quests , t h e dm ac releases control of the bus . whe n the r e a r e no m o re transfer re quests, t h e dmac releas es the bus c ont rol. (no t e 1 ) do not brin g the tx19 a to a halt w h e n the dm ac is in operati on. (no t e 2 ) t o put the t x 19a into idle (doze) m ode w h en th e snoop fun c tion is bein g used, y ou must first s t op th e dma c . tmp19a43 (rev2.0 ) 10-20 dma control l er (dmac)
tmp19a43 (3) t r ans f er re que s t m odes t w o t r a n sfe r r e que st m odes are use d f o r t h e dm ac : an internal t r ans f er re quest m ode a n d a n external tra n sfer re quest m o de. in the i n ternal transfer re que s t m o d e , a tran sfer requ est is g e n e rated i n sid e th e dm ac . settin g a start b it (s t r b it o f t h e ch ann e l co n t ro l reg i st er ccrn ) in t h e in tern al reg i ster of th e dm ac to "1 " g e n e r a te s a tr an s f er r e qu e s t, an d th e dm ac starts to tran sfer d a ta. in t h e e x ternal trans f er re que st m ode, a f ter a start b it is set to "1 ," a transfer req u e st is g e n e rated w h en a tr an s f er r e q u e s t s i gn al in t d re qn o u t p u t b y th e in t c is in pu t, o r w h en a tr ans f e r re qu e s t sig n a l dreqn ou tpu t b y an ex tern al d e v i ce is in pu t. for t h e dm ac, two m o d e s are p r ov id ed : th e lev e l m o d e in wh ich a tran sfer requ est is g e n e rate d wh en th e "l" lev e l of th e intdreqn sign al is det ect ed an d a m ode i n whi c h a t r ansfe r re q u est i s ge nerat e d w h e n t h e fa l l i ng ed ge o r " l " l e vel of the dre q n si gnal is detected. (4 ) ad dr ess m ode for t h e dm a c o f t h e tm p 1 9 a 43 , o n l y o n e a d dres s m ode i s pr ovi de d : a dual a d d r e ss m ode. a si ngl e a d dress m ode i s n o t av ai l a bl e. i n th e du al ad dr ess m o d e , bo th sing le an d co n tinuo us tr an sf er s are av ailab l e. so ur ce and destination device addresses a r e output by the dm ac. t o a ccess an i/o device, the dm ac asserts th e dackn si g n a l. in th e dual ad dress m o d e , two bu s ope r ations , a rea d and a write, a r e execute d. data that is re ad from a source device for t r ans f er i s fi rst put i n t o t h e da t a hol di n g re gi st er ( dhr ) in sid e t h e dmac an d th en written to a d e stin atio n d e v i ce. (5 ) c h an nel ope rat i on the dm ac h a s ei g h t c h a n n e l s (c han n el s 0 t h r o ug h 7 ) . a c h a n nel i s act i v at ed a n d put i n t o a stan db y m o d e b y settin g a start (s t r) b it in t h e ch an n e l con t ro l reg i ster (ccrn ) t o "1 ." if a t r a n sfe r re que st i s ge ne r a t e d w h e n a c h an nel i s i n a st and b y m ode, t h e dm ac a c qui res bu s co n t ro l au t h ority an d tran sfers d a ta . if th ere is n o tran sfer requ es t, th e dmac releases b u s co n t ro l aut h ori t y a n d g o es i n t o a st an dby m ode. if d a t a t r ans f er has bee n com p l e t e d, a c h a nnel i s put i n an id le state. data tran sfer is com p le ted eith er n o rm ally or abnorm ally (e.g . occu rre nce o f err o rs ). a n i n t e rr upt si g n al can be ge nerat e d up o n c o m p let i on of dat a t r ansfe r . fig. 10-21 s h ows the state tra n s itio n s of ch an n e l op eration . bus control auth o rit y not acquired wa i t st a r t idle bus control auth o rit y not acquired bus control auth o rit y acquired t r ansfer completed bus control auth o rit y acquired t r ansfer fig. 10-2 1 ch annel o peration s t ate t r a n s ition tmp19a43 (rev2.0 ) 10-21 dma control l er (dmac)
tmp19a43 (6 ) c o m b i n at i ons of t r an sfe r m odes the dmac ca n tra n s f er data by com b ining each tra n s f er m ode as follows: t r an sfer req u est ed g e /le v e l a d d r e ss mo d e t r an sfer d e v i ces internal ? continuous extern al "l" lev e l (intdreqn) single "l" lev e l (dreqn) continuous extern al falling edge (dreqn) dual single (7) address c h a n ges ad dr ess c h a n g e s are br oadl y cl assi fi ed i n t o t h ree t y pes: increases, decrea ses a n d fi xed. the type of address cha n ge can be s p ecifi ed for each s o urce a n d destina tion a d dress by usi n g sac a n d dac in th e ccrn reg i ster . fo r a m e m o ry d e v i ce, an in crease, d e crease or fi x e d can b e sp ecified . if a sing le tran sfer is selected as a so urce o r d e stin ation d e v i ce, sac o r dac in th e ccrn reg i ster m u st b e set to "fi x ed ". if a d dress i n crease or dec r ea se is selected, the bi t p o si t i on f o r c o unt i n g ca n be speci fi ed usi n g sacm or dacm in th e dtcrn reg i ster . t o sp eci fy th e bit p o s itio n fo r co un ting a source address, sacm m u st b e used, wh ile dacm m u st b e used t o sp ecify th e b it p o s ition for a d e stin ation add r ess . any o f t h e bi t s 0, 4 , 8, 1 2 a n d 16 c a n be s p eci fi e d as t h e bi t p o si t i on fo r a d dres s co u n t i n g . if 0 is selected, a n a d dres s norm ally increases or decreas es. b y sel ect i ng bi t s 4, 8, 1 2 or 16 , i t i s pos sible to inc r ease or decreas e an a d dres s irregula r ly . exam pl es of a d d r ess cha n ges are s h ow n bel o w . exam ple 1: m o notonic incre a se for a s o urc e de vi ce a n d irregular i n crea s e for a de stination de vice sac: address incr ease dac: address incr ease t r si z: t r ansfer unit 32 bits sour ce addr ess: 0xa000 _10 00 destination addr ess: 0xb00 0_0 000 sacm : 000 countin g to begin fr o m bit 0 of the addr ess counter dacm : 001 countin g to begin fr o m bit 4 of the addr ess counter source destination 1st 0xa000 _10 00 0xb00 0_0 000 2nd 0xa000 _10 04 0xb00 0_0 010 3r d 0xa000 _10 08 0xb00 0_0 020 4th 0xa000 _10 0c 0xb00 0_0 030 ? ? tmp19a43 (rev2.0 ) 10-22 dma control l er (dmac)
tmp19a43 example 2 : irr eg ular d ecr ease fo r a sour ce d e vice and monotonic d ecrease for a des tination d e vice sac: address decr ease dac: address dec r ease t r si z: t r ansfer unit 16 bits sour ce addr ess: i n itial value 0xa000 _10 00 destination addr ess: 0xb00 0_0 000 sacm : 010 counting to begin fr o m bit 8 of the addr ess cou n ter dacm : 000 counting to begin fr o m bit 0 of the addr ess cou n ter source destination 1st 0xa000 _10 00 0xb00 0_0 000 2nd 0x9fff_ff00 0xafff_fffe 3rd 0x9fff_fe00 0xafff_fffc 4th 0x9fff_fd00 0xafff_fff a ? ? 10.4.2 t r ansfer re quest fo r th e dmac to t r an sfer data, a tran sfer req u e st m u st be i ssue d t o t h e dm ac . t h ere are t w o t y pes of trans f er reques t: an in ternal trans f er re que st and an exte rnal tr ansfer request. eithe r of these tra n s f e r requests ca n be selected a n d s p ecified for ea ch c h annel. wh ich e v e r is selected , th e dmac acqu ires bu s con t ro l au thority an d starts to transfer d a ta if the t r ans f er re ques t i s ge nerat e d a f t e r t h e st art of cha nnel o p erat i on. ? ? in tern al tran sfer requ est if t h e s t r b it o f ccr is set to "1 " wh en t h e ex r b it o f ccrn is "0 ," a t r an sfer requ est is g e n e rated i mmed i ately . th is tran sfer requ est is called a n inte rnal t r ans f er re quest. th e i n ternal tran sfer requ est is v a lid un til th e ch an n e l o p eratio n is co m p leted . th erefo r e, d a ta can b e tr an sf err e d co n tinuo usly if eith er o f two ev en ts shown belo w do es no t o ccur: * a t r an sition t o a ch an n e l of h i gh er priority * a shi f t o f bus co nt r o l aut h o r i t y t o anot her b u s m a st er of hi ghe r pri o ri t y in the case of t h e inte rnal t r ansfer re que st, da ta can only be t r ans f erre d from me m o ry to me m o ry . external tra n sfer re quest if th e ex r b it o f ccrn is "1 ," setting th e s t r b it of cc r to "1 " allows a ch ann e l to go in t o a st and b y m ode. the intc or an ext e rnal de vi ce t h e n ge ne rat e s t h e i n t d r e q n or dr eq n si g n al for t h is ch ann e l to no tify th e dmac of a tran sfer req u e st , and a tran sfer requ est is g e n e rated . th is trans f er re ques t is called an extern al transfer re quest. t h e external tra n sfer re quest is use d fo r a si ngl e a n d a c o nt i n u o u s t r a n s f er . the tmp19a43 recognizes the tr an sfer requ est signal b y d e tectin g t h e "l" lev e l of th e intdreqn si g n a l or b y d e tectin g th e falling ed g e or "l" lev e l of t h e dreqn sign al. th e un it o f d a ta to b e tran sferred in respon se to one tra n s f er request is s p ecified i n t h e t r siz field o f ccrn , and 3 2 , 1 6 or 8 b its can b e selected . t r ans f er re q u e s t s usi n g i n td r e qn an d dr eq n are de scri bed i n det a i l o n t h e ne xt pa ge . tmp19a43 (rev2.0 ) 10-23 dma control l er (dmac)
tmp19a43 c a tran sfer req u est m a d e b y the in terrup t co n t ro ller (intc ) a tran sfer requ est m a d e b y th e in terru p t con t ro ller is cleared u s i n g th e dac kn sign al . th is dac kn signal is asserted only if a bus cycle fo r a singl e trans f er or the num b er of bytes (v al u e set in the bcrn reg i st er) t r an sferred at c o n tinuo us t r an sfer b e co mes "0 ." th erefo r e, at the si ngle tra n sfer , the am ount of data s p e c ifie d by t r si z is trans f erre d only once because i n td req n is clear ed up on co m p letio n of on e d a ta tr an sf er fro m o n e tr an sfer re quest. on the other hand, at the continuous tran sfer , it can be transferred su ccessi vely in response to a tran sfer req u e st b ecau s e intd reqn is no t cleared un til th e nu m b er o f b y tes tran sferred (v al u e set in the bcrn reg i ster) b e co m e s "0 ." th is dac kn sig n a l is asserted o n l y if a bu s cycle fo r a si ng le tran sfer o r th e nu m b er o f b y tes (v al u e set in the bcrn reg i st er) t r an sferred at c o n tinuo us t r an sfer b e co mes "0 ." th erefo r e, at the si ngle tra n sfer , the am ount of data s p e c ifie d by t r si z is trans f erre d only once because i n td req n is clear ed up on co m p letio n of on e d a ta tr an sf er fro m o n e tr an sfer re quest. on the other hand, at the continuous tran sfer , it can be transferred su ccessi vely in response to a tran sfer req u e st b ecau s e intd reqn is no t cleared un til th e nu m b er o f b y tes tran sferred (v al u e set in the bcrn reg i ster) b e co m e s "0 ." note that if t h e dm ac ac k n o wle d g e s an in terrup t set in intdreqn an d if th is in terrup t is cleared b y th e intc b e fore dma tran sfer b e g i n s , th ere i s a po ssib ility th at dm a t r an sfer m i ght be e x ec u t ed o n ce a f t e r t h e i n t e rr upt i s cl eared, de pe n d i n g on t h e t i m i ng. d a tra n s f er re quest m a de by an external devic e ex tern al p i n s (dreq0 an d dreq4) are in t e rn ally wired t o allow th em t o fun c tio n as pin s of t h e p o r t f . t h ese pi ns ca n b e sel ect ed by set t i ng t h e f u n c t i on c ont rol r e gi st er p ffc t o a n appropriate setting. in t h e e dge m ode , t h e dr e q n si g n al m u st be negat e d a n d t h e n asse rt ed f o r eac h t r ansfe r request to crea te an ef fective edge. in the l e vel m ode, howeve r , s u ccess i ve tra n sfe r re que sts can b e reco gn i zed b y m a in tai n ing an ef fecti v e lev e l. at the co n tinuo us tran sfer , on ly the "l " lev e l m o d e can b e u s ed . at t h e sing le transfer , o n l y th e fallin g edg e m o d e can b e u s ed . ? le vel m ode in t h e l e vel m ode, t h e dm ac det ect s t h e "l " l e vel of t h e dr eq n si g n al up o n t h e ri si ng o f t h e in tern al system clo c k . if it d e tects th e "l" lev e l of t h e dreqn si g n a l wh en a ch an n e l is in a st and b y m ode, i t g o es i n t o t r a n sfe r m ode an d st arts to transfer d a ta. t o use th e dreqn sig n a l at an activ e lev e l, th e po se b it (b it 13 ) o f th e ccrn reg i ster m u st b e set to "0 ." th e dack n sig n a l is acti v e at th e "l" lev e l, as in th e case of th e dreqn sign al. if an e x ternal circuit asse rts t h e dre q n signal , t h e dreqn si g n a l m u st b e m a in tain ed at th e "l" lev e l u n til th e dackn sig n a l is asserted . if th e dreqn si g n a l is deasserted b e fore th e dac kn sig n al is asserte d , a trans f er re quest m a y not be re cognized. if th e dreqn sig n a l is no t at th e "l" lev e l, t h e dm ac j udg es th at t h ere i s n o tran sfer req u e st, and st a r t s a t r ansfe r o p e r at i o n f o r ot he r ch annel s or rel e a s es b u s co nt r o l aut h o r i t y and goes i n t o a st an dby m ode. th e un it o f a tran sfer requ est i s sp eci fied i n t h e t r siz fiel d () o f t h e ccrn reg i ster . tmp19a43 (rev2.0 ) 10-24 dma control l er (dmac)
tmp19a43 dr eq n a [ 31: 1] da ck n t r a n sf er da t a fig. 10-2 2 t r ansfe r re que st t i ming (le v el mode) tmp19a43 (rev2.0 ) 10-25 dma control l er (dmac)
tmp19a43 tmp19a43 (rev2.0) 10-26 dma controller (dmac) ? edge mode in the edge mode, the dmac detects the falling edge of the dreqn signal. if it detects the falling edge of the dreqn signal upon the rising of the internal system clock (the case in which the "l" level is detected upon the rising of the system clock although it was not detected upon the rising of the previous system clock) when a channel is in a standby mode, it judges that there is a transfer re quest, goes into transfer mode, and starts a transfer operation. to detect the falling edge of the dreqn signal, the pose bit (bit 13) of the ccrn register must be set to "0," and the lev bit (bit 12) must also be set to "0." the dackn signal is active at the "l" level. if the falling edge of the dreqn signal is det ected after the dackn signal is asserted, the next data is transferred without a pause. if there is no falling edge of the dreqn signal after the dackn signal is asserted, the dmac judges that there is no transfer reque st, and starts a transfer operation for other channels or goes into a standby mode after releasing bus control authority. the unit of a transfer request is specified in the trsiz field () of the ccrn register. dreqn a [31:1] dackn transfer data transfer data fig. 10-23 transfer request timing (edge mode) start factor is dma interrupt. instruction of the trans mission demand cannot be done by the instruction. there is a possibility that the dma start factor remains after the dma forwarding ends last time. in dma interrupt, transmission the dummy. ccrx = setting; sarx = (ram address) darx = (ram address) bcrx = 0x01; dtcrx = 0x00; ccrx = (channel start) dma demand transmission dummy
tmp19a43 address mode in th e add r ess m o d e , wh et h e r th e dmac execu tes d a ta tran sfers b y o u t pu ttin g ad dresses to b o t h source and dest i n at i o n devi ces o r i t d o es by o u t p ut t i ng a d dres s e s t o ei t h e r a sou r ce de vi ce or a de st i n at i o n device is s p eci fied. the former is called the dual a d dr ess m ode , a nd t h e l a t t e r i s cal l e d t h e si ngl e a d dress m ode. fo r tm p1 9a 4 3 , o n l y t h e dual a d dres s m ode i s avai l a bl e. in the dual address m ode, t h e dmac firs t perform s a read of the s ource device by storing t h e dat a out put by t h e sou r ce devi ce i n o n e o f i t s r e gi st ers ( d hr ). it t h e n e x ec ut es a w r i t e o n t h e dest i n at i on d e v i ce b y writin g th e sto r ed data to th e d e v i ce, th ereb y co mp letin g t h e d a t a tran sfer . destination device dmac dat a c address d d c source device address bus dat a bus fig. 10-2 4 basic con c e p t of dat a t r an sfer in the du al addre s s mod e the uni t o f dat a t o be t r a n sfe r red by t h e dm ac i s t h e am ount of dat a ( 3 2 , 1 6 o r 8 bi t s ) speci fi ed i n t h e t r siz fiel d o f t h e ccrn. on e u n it o f d a ta is tran sfer red each ti m e a tran sfer req u e st is ackn o wledg e d . in th e d u a l address m o d e , t h e u n it of d a ta is read fro m th e so urce d e v i ce, p u t in to t h e dhr and written to th e d e stin ati o n d e v i ce. access t o m e m o ry takes pl ace when the specified unit of data is tra n sferred. if acc ess to externa l me m o ry takes place, 16-bit a ccess ta kes pla ce twice if the unit of data is set t o 32 bits and if the bus wid t h set in t h e cs wait co n t ro ller is 16 b its. lik e wise, if th e u n it o f d a ta is set to 32 b its and if t h e b u s width set in the cs wait c o ntroller is 8 bits, 8-bit access ta kes place four tim e s. if dat a i s t o be t r an sfe rre d fr o m m e m o ry t o an i/ o de vi ce or f r om an i/ o de vi ce t o m e m o ry , t h e uni t of dat a t o be t r a n sfer red m u st b e s p eci fi ed a n d, at t h e s a m e t i m e , t h e bus wi dt h of a n i/ o de vi ce (de v i c e p o rt size) m u st b e sp ecified i n th e dps field o f th e ccrn (32 , 16 o r 8 b its). tmp19a43 (rev2.0 ) 10-27 dma control l er (dmac)
tmp19a43 if t h e u n it o f data to b e tran sferred is equ a l to a d e vice port size, a read or write is e x ec uted once for a n i/ o de vi ce. if a de vi ce po r t si ze i s sm aller t h a n t h e uni t of dat a t o be t r ans f er re d, t h e dm ac pe rf orm s a rea d or write for a n i/ o device m o re than once. for exam ple, if the un it of d a ta to b e tran sferred is 32 b its and if dat a i s t r ans f er red fr om an i/ o de vi ce w h os e devi ce po rt si ze i s 8 bi t s t o m e m o ry , 8 bi t s of dat a are rea d fro m an i/o dev i ce fou r consecu tiv e tim es and st o r ed i n th e dhr. th is 32 -b it data is th en written to me m o ry all at o n c e (t wice if t h e d a ta is written to ex tern al me m o ry an d if th e bu s wi d t h i s 16 b its). an addre ss c h ange occ u rs by the am ount de fine d as t h e unit of data to be trans f erred. t h e bcrn value al so cha n ges b y t h e sam e am ount . a de vi ce p o rt si ze m u st n o t be l a r g er t h a n t h e u n i t of dat a t o b e t r ans f er red . t h e rel a t i o ns hi ps bet w ee n u n i t s o f dat a t o b e t r a n sfe r r e d a nd de vi ce po rt si zes a r e summ arized in t a ble 10.1. t able 10.1 unit s of dat a to be t r an sfe r red an d devi ce port sizes (dual ad dress mode ) t r s i z d p s bus ope r a t ion s pe rforme d on i/o dev i ce 0x (32 bits) 0x (32 bits) once 0x (32 bits) 10 (16 bits) twice 0x (32 bits) 11 (8 bits) 4 times 10 (16 bits) 0x (32 bi t s ) s e t t i n g p r o h i b i t e d 10 (16 bits) 10 (16 bits) once 10 (16 bits) 11 (8 bits) twice 11 (8 bits) 0x (32 bi t s ) s e t t i n g p r o h i b i t e d 11 (8 bits) 10 (16 bi t s ) s e t t i n g p r o h i b i t e d 11 (8 bits) 11 (8 bits) once tmp19a43 (rev2.0 ) 10-28 dma control l er (dmac)
tmp19a43 10.4.3 channel operation a ch ann e l is activ ated if th e s t r b it o f th e c crn o f a ch ann e l is set t o "1." if a ch an nel is activ ated , an activ atio n ch eck is con d u c ted an d if no erro r is d e tected , th e ch an n e l is pu t in to a stand b y m o d e . if a t r an sfe r re que st i s ge nera t e d whe n a cha nnel i s i n a st a n d b y m ode, t h e dm ac ac q u i res bu s c o nt r o l au tho r ity and starts to tran sfer d a ta. ch ann e l op eratio n is co m p let e d eit h er normally o r a bno rm ally (forced termin atio n o r o c cu rren ce o f an error). either norm al com p le tion or a b norm al com p letion is indicated to t h e csrn. s t art of ch ann e l o p e ration a ch an n e l is activ ated if t h e s t r b it o f th e cc rn is set t o "1 ." whe n a c h a n nel is activated, a c o nf i g urat i o n e r r o r c h eck i s co n duct e d a n d i f no er ro r i s det ect ed , t h e cha nnel i s put i n t o a st an dby m ode. if a n er ro r is dete cted, the c h annel is deactivat ed and this st at e of c o m p l e t i on i s c onsi d ered t o be a b n o rm al com p letion. when a channel goes int o a sta n dby m o d e , th e act b it of th e csr n o f th at ch annel b eco m e s "1 ." if a channel is programm ed to start op eration in respo n se to an in tern al transfe r re quest, a transfe r requ est is g e nerated imm e d i ately an d th e dmac acqu ires bu s co n t ro l au tho r ity and starts to tr an sf er d a ta. i f a ch ann e l is p r og r a mm ed to star t o p e r a tio n in r e sponse to an ex tern al tr an sf er requ est, th e dmac acq u i res bu s con t ro l au tho r ity afte r intdr e qn or dre q n is as serted, a nd starts to tran sfer d a ta. co m p letio n of ch ann e l o p e ratio n a ch an n e l com p le tes o p er at io n eith er normall y o r abnor m a l l y an d eit h er on e of t h ese states is indicated to t h e csrn. if an attem p t is m a d e to set t h e s t r b it o f the ccrn reg i ster t o "1 " wh en th e nc or abc b it o f th e csrn reg i ster is "1 ," ch ann e l op eratio n do es n o t start and th e com p le tio n of op eration is considere d t o be abnorm al com p le tion. norm al co m p letion c h an nel o p er a t i on i s co nsi d e r ed t o ha ve be en com p l e t e d no rm al ly i n t h e case sh ow n bel o w . f o r chan nel op erat i on t o be c o nsi d ere d t o have been co m p leted n o rm all y , th e tran sfer of a un it of d a ta (val ue specifie d in the t r siz field of ccrn) m u st be com p leted successful ly . ? ? whe n t h e c ont ent s of b c r n becom e 0 a n d dat a t r a n sfe r i s com p l e t e d abnorm al completion cases of ab normal co m p letio n o f dm ac operatio n are as fo llo ws: co m p letio n due to a con f i g uratio n erro r a con f i g u r ation error o c cu rs if th ere is a mi stak e in th e dm a tran sfer setting . becau s e a con f i g urat i o n err o r occ u rs b e fo re dat a t r a n sfer be gi ns, va l u es speci fi ed i n sar n , da r n an d bcrn rem a in th e sam e as wh en th ey were in itially sp ecified . if ch an n e l op eratio n is co m p leted abno rm ally d u e to a con f i g u r ation erro r , t h e ab c b it o f th e csrn is set t o "1 ," alo n g with the co nf b it. cau s es of a con f i g uratio n error are as fo llows: ? both si o a n d di o were set t o " 1 ." ? th e s t r b it of ccrn was set to "1 " wh en the nc b it or abc b it of csr n was "1 ." ? a v a lu e th at is n o t an i n teg e r m u l tip le o f t h e u n it o f d a ta was set fo r bcrn. ? a v a lu e th at is n o t an i n teg e r m u l tip le o f t h e u n it o f d a ta was set fo r sarn o r darn. tmp19a43 (rev2.0 ) 10-29 dma control l er (dmac)
tmp19a43 ? a pr oh ib ited co m b in atio n of a d e v i ce po r t size and a un it of d a ta to b e t r an sf er r e d w a s set. ? th e s t r b it of ccrn was set to "1 " wh en the bcrn v a lu e was "0 ." co m p letio n due to a bu s erro r if t h e dm ac ope rat i o n has been c o m p l e t e d a b no rm al ly due t o a b u s e r r o r , t h e a b c bi t o f csrn is set t o "1 " an d th e bes or bed b it of csrn is set t o "1 ." ? a bus e r ror wa s detected duri ng data t r ans f e r . ? (no t e ) if the dm ac opera tion ha s been comp leted abn o r m ally due to a bus erro r , bcr, sar a nd dar v a lues canno t be g u aran teed. if a bus error persist s , re fer to 21. "list of fun ctio nal regis t ers" w h ich appea r later in this documen t. 10.4.4 order of priority of channels conce r ni ng the eight c h an nel s of the dmac, the sm aller the cha n nel num ber assigne d to each c h a nne l, t h e hi g h er t h e pri o ri t y . i f a t r ansfe r re que st i s ge ne rated to ch ann e ls 0 and 1 sim u ltan e o u s ly , a tran sfer req u est fo r c h annel 0 i s pr ocesse d wi t h hi g h er p r iority and t h e t r ansfer op er atio n is p e rf or m e d accordingly . whe n t h e tra n sfer re quest for cha n nel 0 is cleared, the tra n sfe r ope ration for c h a nnel 1 is p e rform e d if th e tran sfer re qu est still ex ists (an i n tern al tran sfer req u e st is retain ed if i t is n o t cleared . th e i n terrup t co n t ro ller retain s an ex tern al tran sfer requ est if th e activ e state fo r an i n terrup t requ est assig n e d to dma req u e sts i n t h e in terrup t con t ro ller is set to edg e mo d e . ho wev e r , th e in terru p t co n t ro ller do es no t retain an ex tern al transfer requ est if th e activ e state is set to lev e l m o de. if th e active state for a n int e rr upt re q u est assigne d to d m a re que sts i n th e in terrup t co n t ro ller is set to lev e l m o d e , it is n ecessary to co n tinu e assert in g t h e in terrup t requ est signal). if a t r ans f er re que st i s ge nera t e d whe n d a t a i s bei n g t r a n s f erre d t h r o ug h chan nel 1, a c h an nel t r ansi t i on occurs at c h annel 0, that is, data t r an sfe r t h ro u gh c h a nnel 1 i s t e m porari l y suspe n ded a nd dat a t r a n s f e r th ro ugh ch annel 0 is started. wh en t h e t r a n sfe r re quest f o r cha n nel 0 i s cleare d , data transfe r through channel 1 resumes. ch ann e l tran si tio n s o c cu r upo n th e co m p letio n o f d a ta tran sfers (wh e n th e writin g of all d a ta in t h e dhr has bee n com p l e t e d). int e r r upt s up o n c o m p l e t i on o f a cha n ne l ope rat i o n, t h e dm ac can gene rat e i n t e rr upt re quest s ( i n tdm a n : dma t r an sfer co m p letio n interrup t ) t o th e tx1 9 a pr oce ssor co re wi t h t w o t y pes o f i n t e rr upt s av ailab l e: a n o rm al co m p letio n in terru p t and an ab norm a l c o m p letio n in terrup t. in tdm a 0: 0c h t h r o u g h 3ch i n tdm a 1: 4ch t h r o ug h 7c h ? ? norm al co m p letio n in terrup t if a ch ann e l op eration is com p le ted n o rm a lly , th e nc b it of csrn is set to "1." if a no rm al co m p letio n in t e rru p t is au thorized fo r th e nien b it of t h e ccrn , th e dmac requ ests th e tx19a proces sor core t o au th orize an in terru p t . abno rm al co mp letio n i n terrup t if a ch an n e l op eration is com p le ted abno rmall y , th e abc b it o f csr n is set t o "1 ." if an ab norm a l co mp letio n in terrup t is au tho r ized for t h e abien b it o f t h e ccrn , th e dmac requests t h e t x 19a process o r c o re t o a u thorize an inte rrupt. (no t e ) the dm a tr a n sfer c o mpletion inter r u p t comes in t w o ty pes: intdma0 for 0ch thr ough 3ch and int d ma1 for 4ch thr ough 7ch. tmp19a43 (rev2.0 ) 10-30 dma control l er (dmac)
tmp19a43 10.5 t i ming diagrams dm ac o p erat i ons are sy nc hr on o u s t o t h e ri s i ng e d ges of t h e i n t e r n al sy st em cl ock. 10.5.1 dual addre s s mode ? ? c ont i n u ous t r a n sfe r fi g. 1 0 - 2 5 sh o w s a n exam pl e o f t h e t i m i ng w ith wh ich 1 6 -b it d a ta is tran sferred from o n e ex tern al m e mo ry (16-b it wid t h ) to ano t her (16 - b it wi d t h). data is actu a lly transferred su ccessi v e ly un til bcrn b e co m e s "0 ." a [23 : 0] cs0 rd wr / hwr ts ys dat a dat a wr i t e read d [15 : 0] cs1 fig. 10-2 5 du al addre s s m ode (m emo r y-to-me m ory ) me m o ry-to-i/ o device t r ans f er fi g. 1 0 - 2 6 s h o w s a n e x am pl e o f t h e t i m i ng wi t h whi c h dat a i s t r a n sfe rre d fr om m e m o ry t o an i/ o de vi ce i f t h e uni t of dat a t o be t r a n sfe rre d i s set t o 1 6 bits an d if the dev i ce port size is set to 8 b its. read wr i t e dat a dat a ts ys dat a wr i t e a [23 : 0] cs0 cs1 rd wr d [15 : 0] fig. 10-2 6 du al addre s s m ode (m emo r y-to-i/o devi ce) tmp19a43 (rev2.0 ) 10-31 dma control l er (dmac)
tmp19a43 ? i/o de vice-to-me m ory transfer fi g. 1 0 - 2 7 sh o w s a n exam pl e o f t h e t i m i ng wi t h w h i c h dat a i s t r a n s f er red f r om an i/ o d e vi ce to m e m o ry if t h e un it of d a ta to b e tran sferred is set t o 16 bits and if th e dev i ce p o rt size is set to 8 b its. a [23 : 0] cs0 rd wr / hwr dat a ts ys dat a dat a d [15 : 0] cs1 r e a d r e a d wr i t e fig. 10-2 7 du al addre s s m ode (i/o device-to - me mory) tmp19a43 (rev2.0 ) 10-32 dma control l er (dmac)
tmp19a43 10.5.2 dreqn-initiated t r ansfer mode ? ? data tran sfer fro m in tern al r a m t o ex tern al m e m o ry (m u l tip lex e d b u s , 5-wait i n sertion , lev e l m ode) fig . 10- 28 show s t w o tim in g cycles in w h i c h 16 -b it d a ta is tran sferred twice fro m in tern al ram to ex ternal m e m o ry (16-b it wid t h). d r e q n dackn inte r nal sy stem cl o ck a le a [23 : 16] a d [ 1 5: 0] rd wr hw r csn da t a a dd a dd a dd da t a (7+ ) c l o c k 5 w a it s r / w fig. 10-2 8 le vel mode (fro m internal ra m to external memory) data tran sfer fro m ex tern al me m o ry to in t e rn al ram (m u ltip lex e d bu s, 5-wait in sertion , lev e l m ode) fi g. 1 0 - 2 9 sh o w s t w o t i m i ng cy cl es i n w h i c h 1 6 -b it d a ta is transferred t w ice fro m ex tern al m e m o ry (1 6- bi t wi dt h ) t o i n t e rnal r a m . inte r nal sy stem cl o ck dreq dackn a le a [23 : 16] a d [ 15 :0 ] rd w r hw r csn da t a a dd a dd a dd da t a (7+ ) c l o c k 5 w a it s r / w fig. 10-2 9 le vel mode (fro m external memory to internal ram ) tmp19a43 (rev2.0 ) 10-33 dma control l er (dmac)
tmp19a43 ? ? data tran sfer fro m in tern al ram to ex tern al m e m o ry (separate bu s, 5 - wait in sertio n , l e v e l m ode) fig . 10- 30 show s t w o tim in g cycles in w h i c h 16 -b it d a ta is tran sferred twice fro m in tern al ram to ex ternal m e m o ry (16-b it wid t h). dat a add dat a (7 + ) clo c k inter n al sy stem clock dre qn da ck n a [23: 0] d [15: 0] rd wr hw r cs n r/ w 5 w a i t s fig. 10-3 0 le vel mode (int ernal ram to external me mory) data tran sfer fro m ex tern al me m o ry to in te rn al ram (sep arate b u s , 5-wait in sertio n, lev e l m ode) fi g. 1 0 - 3 1 sh o w s t w o t i m i ng cy cl es i n w h i c h 1 6 -b it d a ta is transferred t w ice fro m ex tern al m e m o ry (1 6- bi d wi dt h ) t o i n t e rnal r a m . internal s y ste m clock dreq d a c k n a [23 : 0] a [15 : 0] rd w r hw r csn r / w dat a add dat a (7+ ) c l o c k 5 w a it s fig. 10-3 1 le vel mode (fro m external memory to internal ram ) tmp19a43 (rev2.0 ) 10-34 dma control l er (dmac)
tmp19a43 ? ? data tran sfer fro m in tern al ra m to ex tern al m e m o ry ( m u ltip lex e d bu s, 5-wait in sertio n, ed g e m ode) fig . 10 -3 2 shows o n e ti m i n g cycle in wh ich 1 6 -b it d a ta is tran sferred on ce fro m in tern al ram to ex tern al m e m o ry (1 6-b it wid t h ) . internal s y stem c l ock dreqn dackn a le a [23:16] a d [15:0] rd wr hwr csn r/w a dd a dd dat a (7+ ) c l oc k 5 wait s fig. 10-3 2 edge mode (fro m internal ra m to external memory) data tran sfer fro m ex tern al me m o ry to in tern al ram (mu ltip lex e d bu s, 5 - wait in sertion , ed g e m ode) fi g. 10 - 33 s h ows o n e t i m i ng cy cl e i n w h i c h 1 6 - b i t dat a i s t r ansfe rre d once fr om ext e rnal m e m o ry (1 6- bi t wi dt h ) t o i n t e rnal r a m . internal s y stem clock dreqn dackn a le a [23:16] a d [15:0] rd wr hw r csn r/w a dd a dd dat a (7+ ) clock 5 w a it s fig. 10-3 3 edge mode (fro m external memory to internal ram ) tmp19a43 (rev2.0 ) 10-35 dma control l er (dmac)
tmp19a43 ? ? data transfer fro m in tern al ra m to e x ternal m e m o ry (separat e bu s, 5-wait in sertion, edg e m ode) fig . 10 -3 4 shows o n e ti m i n g cycle in wh ich 1 6 -b it d a ta is tran sferred on ce fro m in tern al ram to ex tern al m e m o ry (1 6-b it wid t h ) . internal s y stem clock dreqn dackn a [23:0] d [15:0] rd wr hw r csn r/w add data (7+ ) clock 5 w a it s fig. 10-3 4 edge mode (fro m internal ra m to external memory) data transfer fro m ex tern al me m o ry to in tern al r a m (s eparate bus, 5-wait in sertion, edg e m ode) fi g. 10 - 35 s h ows o n e t i m i ng cy cl e i n w h i c h 1 6 - b i t dat a i s t r ansfe rre d once fr om ext e rnal m e m o ry (1 6- bi t wi dt h ) t o i n t e rnal r a m . internal s y stem clock dreqn dackn a [23:0] d [15:0] rd wr hw r csn r/w a dd dat a ( 7+ ) clock 5 w a it s fig. 10-3 5 edge mode (fro m external memory to internal ram ) tmp19a43 (rev2.0 ) 10-36 dma control l er (dmac)
tmp19a43 10.6 case of dat a t r ansfer the settings de scribe d below relate to a ca se in whic h se rial data receive d (scnbu f) is transfe rre d t o the internal r a m by dm a t r ans f er . dma (c h.0) is use d to transfe r data. t h e dma0 is activated by a receive inte rrupt ge ne rated by sio1. c h an nel used: 0 ? ? ? ? ? ? ? so urce ad dre s s : sc 1b u f dest i n at i o n: (p hy si cal ad dress ) 0xf fff _ 9 8 0 0 num b er of by t e s t r an sfe rre d: 25 6 by t e s data leng th 8 bits: uar t serial cha n nel: ch 1 t r an sf er r a te: 96 00 bp s imc5 ll x111, x1 00 /* assigned to dm c0 activation facto r * / intclr 0x05 0 /* i v r [8:0] , intrx1 inter r upt factor * / sc1mod0 0x29 /* uart m ode, 8-bit length, baud r a te gener a tor * / sc1cr 0x00 br1 cr 0x 1f / * @ f c = 4 0 m h z */ dcr 0x80 00_ 000 0 /* dm a r e set * / imcfh l x000, x0 00 /* disable inter r upt * / intclr 0x0f8 /* i v r [8:0] value * / imcfh l x000, x1 00 /* level = 4 (any given value) */ dtcr0 0x00 00_ 000 0 /* dacm = 000 * / /* sacm = 000 * / sar0 0xffff_f208 /* physical address of sc1buf */ dar0 0xffff_980 0 /* phy sical address of destina tion to which data is trans f erred */ bcr0 0x00 00_ 00ff /* 256 ( n u m ber of by tes tr ansfer r e d ) / ccr0 0x80c 0_5b 0f /* dm a ch. 0 setting */ (contents) 3 1 2 7 23 19 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 5 1 1 7 3 0 1 0 1 1 x 1 1 x 0 0 0 1 1 1 1 s t art fac t or is dma interrupt . ins t ruc t ion of the trans mi ssion d e man d can not be do ne by the inst ructio n. there is a possibility t h at the dma start fact or remains after the d m a forwarding ends last time. in dma interrupt, transmission the dummy . tmp19a43 (rev2.0 ) 10-37 dma control l er (dmac)
tmp19a43 11. 16-bit t i mer/event counters (tmrbs) each of t h e s i xteen c h annel s (tmrb0 t h rough tmrf) h a s a m u lti-fun c tio n a l, 16 -b i t ti m e r/ev en t co un ter . tmrbs op erat e in th e fo llowi ng f o ur o p erat i o n m odes: ? 1 6 -b it in terv al ti m e r m o d e ? 16 - b i t eve n t co unt e r m ode ? 16 - b i t p r o g ram m abl e sq uare - w ave out put ( ppg ) m ode (si m ult a neou s ou t put i n uni t s o f f o u r c h a nnel s can be pr o g ram m ed) ? t w o - p h ase p u l s e i n put c o unt e r m ode ( q uad/ n o m a l - speed, t m r b 2 , tm r b 3, tm r b 6 a n d tm r b 7 onl y ) ? t i m e r syn c hr on ou s m o d e th e u s e of th e cap ture fun c tion allows tmr b s to o p e rate i n three o t h e r m o d e s: ? fre que ncy m e asurem ent m ode ? pulse widt h measurem ent m ode ? t i m e dif f ere n c e m easure m ent m ode each ch ann e l co nsists o f a 16 -b it up -co u n t er , two 16 -b it tim e r registers (o ne of whic h is do u b le-b u f fe red ) , tw o 16-bit capt u re registers , t w o com p arators , a capt u re i n pu t con t ro l, a ti mer flip -flop and its ass o ciated c o ntrol ci rcui t . t i m e r ope rat i o n m o d e s an d t h e t i m er fl i p -fl op are c ont rol l e d by a 13 - b y t e regi st e r . each ch ann e l (tmrb0 thro ug h tmrbf) fu n c tion s ind e pen d e n tly an d wh ile th e ch ann e ls op erate in th e sam e way , the r e are dif f e r e n ces in their s p ecifications as s h ow n i n t a b l e 1 1 -1 an d th e t w o- ph ase pu lse co un t f u n c tion . there f ore, t h e o p er at i onal d e scri pt i o ns he r e are f o r tm r b 0 onl y a n d f o r t h e t w o- p h a s e p u l s e co u n t f unct i on (tmrb2 , tm rb3 , tmrb6 an d tmrb7) on ly . tmp19a43 (rev2.0) 11 - 1 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 t able 1 1 -1 dif f eren ce s in the s pecificatio ns of tmrb module s cha nne l sp ecificatio n t m r b 0 t m r b 1 t m r b 2 t m r b 3 ex t e rn al clo c k/ cap tu re tr i gge r i n p u t pi n s t b 0in 0 ( s h a re d w i t h p20) t b 0in 1 ( s h a re d w i t h p21) t b 1in 0 ( s h a re d w i t h p22) t b 1in 1 ( s h a re d w i t h p23) t b 2in 0 ( s h a re d w i t h pa 6) t b 2in 1 ( s h a re d w i t h pa 7) t b 3in 0 ( s h a re d w i t h pb0) t b 3in 1 ( s h a re d w i t h pb1) ex t e rn al pi n s t i m e r flip-f lo p ou tp u t p i n t b 0o u t (shar e d w i t h p5 4) t b 1o u t (shar e d w i t h p5 5) t b 2o u t (shar e d w i t h p5 6) t b 3o u t (shar e d w i t h p5 7) internal si g n al s tim e r for capture trigger s D tb0 o u t t b 0 o u t t b 0 o u t tim e r run register tb0run (0xffff _f 140) tb1run (0x ffff _f 1 5 0 ) t b 2 r u n (0xffff _f 16 0 ) t b 3 r u n (0xffff _f 1 7 0 ) tim e r contr o l r e giste r tb0cr ( 0xf f f f _ f 1 4 1 ) t b 1 c r ( 0xf fff_ f 1 5 1 ) t b 2 c r ( 0xf fff_f161) t b 3 c r ( 0xf f f f _ f 1 7 1 ) tim e r m ode registe r tb0mod (0xffff _f142) tb1mod (0x ffff _ f 1 5 2 ) t b 2 m o d (0xffff _ f 1 6 2 ) t b 3 m o d (0xffff _ f 1 7 2 ) t i m e r flip-f lo p c o n t r o l register tb0ffcr ( 0 xffff _f143) tb1ffcr ( 0 xffff _f153) tb2ffcr ( 0 xffff _f163) tb3ffcr ( 0 xffff _f173) tim e r status re gi ster t b 0 s t (0xffff _f 1 4 4 ) tb1s t (0xffff _f 154) tb2st (0xffff _f 1 6 4 ) t b 3 s t (0xffff _f 1 7 4 ) tim e r uc preset re giste r tb0 u cl tb0 u ch tb1 u cl tb1 u ch tb2 u cl tb2 u ch tb3 u cl tb3 u ch tim e r register t b 0rg 0 l ( 0xff ff_ f14 8 ) tb0rg0h ( 0xf fff_f149) t b 0rg 1 l ( 0xff ff_ f14a ) tb0rg1h ( 0xf fff_f14b) t b 1rg 0 l ( 0xff ff_ f15 8 ) tb1rg0h ( 0xf fff_f159) t b 1rg 1 l ( 0xff ff_ f15a ) tb1rg1h ( 0xf fff_f15b) t b 2rg 0 l ( 0xff ff_ f16 8 ) tb2rg0h ( 0xf fff_f169) t b 2rg 1 l ( 0xff ff_ f16a ) tb2rg1h ( 0xf fff_f16b) t b 3rg 0 l ( 0xff ff_ f17 8 ) tb3rg0h ( 0xf fff_f179) t b 3rg 1 l ( 0xff ff_ f17a ) tb3rg1h ( 0xf fff_f17b) register nam e s (ad d re sse s) cap t ur e re gi st er tb0cp 0 l (0xffff _f14c) tb0cp 0 h (0xffff _f14d) tb0cp 1 l (0xffff _f14e) tb0cp 1 h (0xffff _f14f) tb1cp 0 l (0xffff _f15c) tb1cp 0 h (0xffff _f15d) tb1cp 1 l (0xffff _f15e) tb1cp 1 h (0xffff _f15f) tb2cp 0 l (0xffff _f16c) tb2cp 0 h (0xffff _f16d) tb2cp 1 l (0xffff _f16e) tb2cp 1 h (0xffff _f16f) tb3cp 0 l (0xffff _f17c) tb3cp 0 h (0xffff _f17d) tb3cp 1 l (0xffff _f17e) tb3cp 1 h (0xffff _f17f) cha nne l sp ecificatio n tmrb4 t m r b 5 t m r b 6 t m r b 7 ex t e rn al clo c k/ cap tu re tr i gge r i n p u t pi n s t b 4in 0 ( s h a re d w i t h p24) t b 4in 1 ( s h a re d w i t h p25) t b 5in 0 ( s h a re d w i t h p26) t b 5in 1 ( s h a re d w i t h p27) t b 6in 0 ( s h a re d w i t h pa 0) t b 6in 1 ( s h a re d w i t h pa 1) t b 7in 0 ( s h a re d w i t h pa 2) t b 7in 1 ( s h a re d w i t h pa 3) ex t e rn al pi n s t i m e r flip-f lo p ou tp u t p i n t b 4o u t (shar e d w i t h p6 6) t b 5o u t (shar e d w i t h p6 7) t b 6o u t (shar e d w i t h p9 0) t b 7o u t (shar e d w i t h p9 1) internal si g n al s tim e r for capture trigger s t b 0 o u t t b 0 o u t t b 0 o u t t b 0 o u t tim e r run register tb4run (0xffff _f 180) tb5run (0x ffff _f 1 9 0 ) t b 6 r u n (0xffff _f 1a 0 ) t b 7 r u n (0xffff _f 1b 0 ) tim e r contr o l r e giste r tb4cr ( 0xf f f f _ f 1 8 1 ) t b 5 c r ( 0xf fff_ f 1 9 1 ) t b 6 c r ( 0xf fff_f1a1 ) t b 7 c r ( 0xf f f f _ f 1 b 1 ) tim e r m ode registe r tb4mod (0xffff _f182) tb5mod (0x ffff _f192) tb6mod (0xffff _f1a2) tb7mod (0xffff _f1b 2) t i m e r flip-f lo p c o n t r o l register tb4ffcr ( 0 xffff _f183) tb5ffcr ( 0 xffff _f193) tb6ffcr ( 0 xffff _f1a3) tb7ffcr ( 0 xffff _f1b 3) tim e r status re gi ster t b 4 s t (0xffff _f 1 8 4 ) tb5s t (0xffff _f 194) tb6st (0xffff _f 1 a 4 ) t b 7 s t (0xffff _f 1 b 4 ) tim e r uc preset re giste r tb4 u cl tb4 u ch tb5 u cl tb5 u ch tb6 u cl tb6 u ch tb7 u cl tb7 u ch tim e r register t b 4rg 0 l ( 0xff ff_ f18 8 ) tb4rg0h ( 0xf fff_f189) t b 4rg 1 l ( 0xff ff_ f18a ) tb4rg1h ( 0xf fff_f18b) t b 5rg 0 l ( 0xff ff_ f19 8 ) tb5rg0h ( 0xf fff_f199) t b 5rg 1 l ( 0xff ff_ f19a ) tb5rg1h ( 0xf fff_f19b) t b 6rg 0 l ( 0xff ff_ f1a 8 ) tb6rg0h ( 0xf fff_f1a9) t b 6rg 1 l ( 0xff ff_ f1a a ) tb6rg1h ( 0xf fff_f1ab) t b 7rg 0 l ( 0xff ff_ f1b 8 ) tb7rg0h ( 0xf fff_f1b 9 ) t b 7rg 1 l ( 0xff ff_ f1ba ) tb7rg1h ( 0xf fff_f1bb) register nam e s (ad d re sse s) cap t ur e re gi st er tb4cp 0 l (0xffff _f18c) tb4cp 0 h (0xffff _f18d) tb4cp 1 l (0xffff _f18e) tb4cp 1 h (0xffff _f18f) tb5cp 0 l (0xffff _f19c) tb5cp 0 h (0xffff _f19d) tb5cp 1 l (0xffff _f19e) tb5cp 1 h (0xffff _f19f) tb6cp 0 l (0xffff _f1ac) tb6cp 0 h (0xffff _f1ad) tb6cp 1 l (0xffff _f1ae) tb6cp 1 h (0xffff _f1af) tb7cp 0 l (0xffff _f1bc) tb7cp 0 h (0xffff _f1bd) tb7cp 1 l (0xffff _f1be) tb7cp 1 h (0xffff _f1bf) tmp19a43 (rev2.0) 11 - 2 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 cha nne l sp ecificatio n tmrb8 t m r b 9 t m r b a t m r b b ex t e rn al clo c k/ cap tu re tr i gge r i n p u t pi n s t b 8in 0 ( s h a re d w i t h pa 4) t b 8in 1 ( s h a re d w i t h pa 5x) ex t e rn al pi n s ti m e r fl i p -fl o p o u t put pi n tb8 out (s h a red w i th p92 ) tb9 out (s h a red w i th p96 ) tbaout (s h a red w i t h p97 ) tbbout (s h a red with pd3 ) internal si g n al s tim e r for capture trigger s D tb8 o u t t b 8 o u t t b 8 o u t tim e r run register tb8run (0xffff _f 1c 0) tb9run (0x ffff _f 1d0) tbarun (0xffff _f1e0) tbbrun (0xfff f_f1f 0 ) tim e r contr o l r e giste r tb8cr ( 0xf f f f _ f 1 c 1 ) t b 9 c r ( 0xf f f f _ f 1 d 1 ) tbacr (0xf fff _ f 1 e 1 ) t b b c r (0xffff _f 1 f 1 ) tim e r m ode registe r tb8mod (0xffff _f1c 2) tb9mod (0x ffff _f1d2) tbamod (0xffff _f1e2) tbbmod (0xff ff_f1f 2 ) t i m e r flip-f lo p c o n t r o l register tb8ffcr ( 0 xffff _f1c 3) tb9ffcr ( 0 xffff _f1d3) tbaffcr (0xffff _f1e3) tbbffcr (0xfff f_f1f 3 ) tim e r status re gi ster tb8st (0xffff _f 1c4) tb9st (0xffff _f 1d 4) tbast (0xffff _f 1e4) tbbst (0xf fff_f1f4) tim e r uc preset re giste r tb8 u cl tb8 u ch tb9 u cl tb9 u ch tbaucl tbauch tbbucl tbbuch tim e r register t b 8rg 0 l ( 0xff ff_ f1c 8 ) tb8rg0h ( 0xf fff_f1c 9 ) t b 8rg 1 l ( 0xff ff_ f1ca ) tb8rg1h ( 0xf fff_f1cb) t b 9rg 0 l ( 0xff ff_ f1d 8 ) tb9rg0h ( 0xf fff_f1d9) t b 9rg 1 l ( 0xff ff_ f1d a ) tb9rg1h ( 0xf fff_f1db) t b a r g 0 l (0xf fff _f1e 8) t b a r g 0 h (0xf fff _f1e 9) t b a r g 1 l (0xf fff _f1e a ) t b a r g 1 h (0xf fff _f1e b ) tbbrg0l (0xffff _f1f 8) tbbrg0h (0xffff _f1f9) tbbrg1l (0xffff _f1fa) tbbrg1h (0xffff _f1fb) register nam e s (ad d re sse s) cap t ur e re gi st er tb8cp 0 l (0xffff _f1cc) tb8cp 0 h (0xffff _f1cd) tb8cp 1 l (0xffff _f1ce) tb8cp 1 h (0xffff _f1cf) tb9cp 0 l (0xffff _f1dc) tb9cp 0 h (0xffff _f1dd) tb9cp 1 l (0xffff _f1de) tb9cp 1 h (0xffff _f1df) tbacp0l (0xffff _f1ec) tbacp0h (0xffff _f1ed) tbacp1l (0xffff _f1ee) tbacp1h (0xffff _f1ef) tbbcp0l (0xff ff_f1fc) tbbcp0h (0xff ff_f1fd) tbbcp1l (0xff ff_f1fe) tbbcp1h (0xff ff_f1ff) cha nne l sp ecificatio n tmrbc t m r b d t m r b e t m r b f ex t e rn al clo c k/ cap tu re tr i gge r i n p u t pi n s ? ? ? ? ex t e rn al pi n s ti m e r fl i p -fl o p o u t put pi n tbcout (s h a red with pd4 ) tbdout (s h a red w i t h pd 5 ) tbeout (s h a red w i th p32 ) tbfout (s h a red with p47 ) internal si g n al s ti m e r fo r cap tu re t r igg e rs tb8 out tb8 out tb8 out tb8 out tim e r run register tbcrun (0xfff f_ f 2 0 0 ) t b d r u n (0xffff _f21 0 ) t b e r u n (0xffff _f220) t b f r u n (0xfff f _ f 2 3 0 ) tim e r contr o l r e giste r tbccr (0xffff _f 2 0 1 ) t b d c r (0xf fff _f2 1 1 ) t b e c r (0xf fff _f221) t b f c r (0xffff _f 2 3 1 ) tim e r m ode registe r tbcmod (0xff ff_f202) tbdmod (0x ffff _ f 2 1 2 ) t b e m o d (0xffff _f22 2 ) t b f m o d (0xfff f _ f 2 3 2 ) t i m e r flip-f lo p c o n t r o l register tbcffcr (0xfff f_f203) tbdffcr (0xffff _ f 2 1 3 ) t b e f f c r (0xffff _ f 2 2 3 ) t b f f f c r (0xffff _ f 2 3 3 ) tim e r status re gi ster tbcst (0xf fff_f204) tbdst (0xffff _f 214) tbest (0xffff _f 224) tbfst (0xff ff_f 2 34) tim e r uc preset re giste r tbcucl tbcuch tbducl tbduch tbeucl tbeuch tbfucl tbfuch tim e r register tbcrg0l (0xffff _f208) tbcrg0h (0xffff _f209) tbcrg1l (0xffff _f20a) tbcrg1h (0xffff _f20b) t b d r g 0 l (0xf fff _f2 1 8 ) tbdrg0 h (0 x f fff_ f 219 ) tbdrg1 l (0 x f fff_ f 21 a) tbdrg1 h (0 x f fff_ f 21 b) tberg0l (0xf fff_f228) t b e r g 0 h (0xf fff _f2 2 9 ) tberg1l (0xf fff_f22a) t b e r g 1 h (0xf fff _f2 2 b) tbfrg0l (0xffff _f238) tbfrg0h (0xffff _f239) tbfrg1l (0xffff _f23a) tbfrg1h (0xffff _f23b) register nam e s (ad d re sse s) cap t ur e re gi st er tbccp0l (0xff ff_f20c) tbccp0h (0xff ff_f20d) tbccp1l (0xff ff_f20e) tbccp1h (0xff ff_f20f) tbdcp0l (0xffff _f21c) tbdcp0h (0xffff _f21d) tbdcp1l (0xffff _f21e) tbdcp1h (0xffff _f21f) tbecp0l (0xffff _f22c) tbecp0h (0xffff _f22d) tbecp1l (0xffff _f22e) tbecp1h (0xffff _f22f) tbfcp0l (0xfff f_f23c) tbfcp0h (0xfff f_f23d) tbfcp1l (0xfff f_f23e) tbfcp1h (0xfff f_f23f) tmp19a43 (rev2.0) 11 - 3 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 11.1 block diagram of e ach chann e l i n t e rnal dat a bus i n t e rnal dat a bus run/ c l ear matc h det ecti o n 16-bi t c o m parat or (cp 0 ) 16-bi t t i m e r regi s t er t b 0rg0h/ l 16-bi t c o m parat or (cp 1 ) regi s t er bu f f e r 0 16-bi t t i m e r regi s t er t b 0rg1h/ l ma t c h det ec t i on count cl o c k tb0 m o d < t b0 c l k1 : 0 > t b 0run se le c t o r tb0 m od pr e s ca l e r cl o c k : t0 tbou t tb0 i n 0 tb0 i n 1 t1 t4 t1 6 t b 0run tb0 m o d < t b0 c l e> capt ure regi s t er 0 t b 0cp 0 h/ l tb0mod capt ure regi s t er 1 t b 0cp 1 h/ l 8 4 2 t4 t16 t b 0run i n t e rnal dat a bus i n t e rnal dat a bus ti m e r flip - f lo p c ont rol tb0 f f0 ti m e r flip - f lo p tb0 o u t tmr b 0 i n t e rrupt in ttb0 t i me r flip - f lo p out put o v e r flo w in te r r u p t o u t p ut capt ure c ont rol 16-bi t up-c ount er (uc0) 16-bi t t i m e r s t a t us regi s t er tb0 s t re g i s t e r 0 i n t e rru p t o u t p ut re g i s t e r 1 i n t e rru p t o u t p ut t1 16 32 fig. 1 1 -1 tm rb0 block di agra m (same for chan nel s 1, 4, 5 and 8 throug h f) tmp19a43 (rev2.0) 11 - 4 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 in te r n a l d a t a b u s in te r n a l d a t a b u s run/ c l ear matc h d e t e c t i o n 16-bi t c o m paraot r (cp 0 ) 16-bi t t i m e r regi s t er t b 2rg0h/ l 16-bi t c o m parat or (cp 1 ) regi s t er bu f f e r 0 16-bi t t i m e r regi s t er t b 2rg1h/ l m a t c h det e c t i on count cl o c k tb2 m o d < t b2 c l k1 : 0 > t b 2run se le c t o r tb2mod pr e s ca l e r cl o c k : t0 tbou t tb2 i n 0 tb2 i n 1 t1 t2 t16 t b 2run tb2 m od < t b2 c l e> capt ure regi s t er 0 tb2c p0h / l tb2 m od capt ure regi s t er 1 t b 2cp 1 h/ l 16 8 4 2 t1 t 16 t b 2run in te r n a l d a t a b u s in te r n a l d a t a b u s ti m e r flip - f lo p c ont rol tb2 ff0 ti m e r flip - f lo p tb2ou t tmr b 2 i n t e rrupt in ttb2 t i me r flip - f lo p out p ut o v e r flo w in te r r u p t o u tp u t capt ure c o nt rol 16-bi t up-and-down c o unt e r (uc0 ) 16-bi t t i m e r s t a t us regi s t er tb2 s t r e g i ste r 0 in te r r u p t o u tp u t r e g i ste r 1 in te r r u p t o u tp u t up-and-down co n t r o l t b 2run tmp19a43 11.2 description of operations for each circuit 11.2.1 prescaler there is a 4-bit prescaler for acqui ring the tm rb0 source clock. t h e prescale r input clock t0 is fpe r i p h/ 2, f p eri ph/ 4, fpe r i p h/ 8 or f p eri ph/ 16 s e l ect ed by s y sc r 0 i n t h e c g . the peri phe ral clock, fperiph, is either fgea r , a clock selected b y syscr 1 in th e cg , o r fc, wh ich is a clo c k bef o re i t i s di vi ded by t h e cl oc k gear . th e op eration o r th e stop page of a prescaler is set wit h tb0 r un wh ere writin g "1 " st arts co un ting and writing "0 " clears an d stop s co un ting . t a b l e 1 1 -2 shows p r escaler o u t p u t clo c k reso lu tion s . tmp19a43 (rev2.0) 11 - 6 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 t able 1 1 -2 prescale r outp ut clock resolution s @ = 40mhz pres cale r o u t p u t clo ck reso lu tion s relea se pe riphe ra l c l oc k clo ck g ear v a l u e select p r es cal er clo ck t1 t4 t1 6 00(fperiph/16) fc/2 5 (0.8 s ) f c /2 7 (3.2 s ) f c /2 9 (12.8 s) 01(fperiph/8) fc/2 4 (0.4 s ) f c /2 6 (1.6 s ) f c /2 8 (6.4 s) 10(fperiph/4) fc/2 3 (0.2 s ) f c /2 5 (0.8 s ) f c /2 7 (3.2 s) 000 (fc) 11(fperiph/2) fc/2 2 (0.1 s ) f c /2 4 (0.4 s ) f c /2 6 (1.6 s) 00(fperiph/16) fc/2 6 (1.6 s ) f c /2 8 (6.4 s ) f c /2 10 (25.6 s) 01(fperiph/8) fc/2 5 (0.8 s ) f c /2 7 (3.2 s ) f c /2 9 (12.8 s) 10(fperiph/4) fc/2 4 (0.4 s ) f c /2 6 (1.6 s ) f c /2 8 (6.4 s) 100(fc/2) 11(fperiph/2) fc/2 3 (0.2 s ) f c /2 5 (0.8 s ) f c /2 7 (3.2 s) 00(fperiph/16) fc/2 7 (3.2 s ) f c /2 9 (12.8 s ) f c /2 11 (51.2 s) 01(fperiph/8) fc/2 6 (1.6 s ) f c /2 8 (6.4 s ) f c /2 10 (25.6 s) 10(fperiph/4) fc/2 5 (0.8 s ) f c /2 7 (3.2 s ) f c /2 9 (12.8 s) 110(fc/4) 11(fperiph/2) fc/2 4 (0.4 s ) f c /2 6 (1.6 s ) f c /2 8 (6.4 s) 00(fperiph/16) fc/2 8 (6.4 s ) f c /2 10 (25.6 s ) f c /2 12 (102.4 s) 01(fperiph/8) fc/2 7 (3.2 s ) f c /2 9 (12.8 s ) f c /2 11 (51.2 s) 10(fperiph/4) fc/2 6 (1.6 s ) f c /2 8 (6.4 s ) f c /2 10 (25.6 s) 0 (fgear) 111(fc/8) 11(fperiph/2) fc/2 5 (0.8 s ) f c /2 7 (3.2 s ) f c /2 9 (12.8 s) 00(fperiph/16) fc/2 5 (0.8 s ) f c /2 7 (3.2 s ) f c /2 9 (12.8 s) 01(fperiph/8) fc/2 4 (0.4 s ) f c /2 6 (1.6 s ) f c /2 8 (6.4 s) 10(fperiph/4) fc/2 3 (0.2 s ) f c /2 5 (0.8 s ) f c /2 7 (3.2 s) 000 (fc) 11(fperiph/2) fc/2 2 (0.1 s ) f c /2 4 (0.4 s ) f c /2 6 (1.6 s) 00(fperiph/16) fc/2 5 (0.8 s ) f c /2 7 (3.2 s ) f c /2 9 (12.8 s) 01(fperiph/8) fc/2 4 (0.4 s ) f c /2 6 (1.6 s ) f c /2 8 (6.4 s) 10(fperiph/4) fc/2 3 (0.2 s ) f c /2 5 (0.8 s ) f c /2 7 (3.2 s) 100(fc/2) 11(fperiph/2) ? fc/2 4 (0.4 s ) f c /2 6 (1.6 s) 00(fperiph/16) fc/2 5 (0.8 s ) f c /2 7 (3.2 s ) f c /2 9 (12.8 s) 01(fperiph/8) fc/2 4 (0.4 s ) f c /2 6 (1.6 s ) f c /2 8 (6.4 s) 10(fperiph/4) ? fc/2 5 (0.8 s ) f c /2 7 (3.2 s) 110(fc/4) 11(fperiph/2) ? fc/2 4 (0.4 s ) f c /2 6 (1.6 s) 00(fperiph/16) fc/2 5 (0.8 s ) f c /2 7 (3.2 s ) f c /2 9 (12.8 s) 01(fperiph/8) ? fc/2 6 (1.6 s ) f c /2 8 (6.4 s) 10(fperiph/4) ? fc/2 5 (0.8 s ) f c /2 7 (3.2 s) 1 (fc) 111(fc/8) 11(fperiph/2) ? ? fc/2 6 (1.6 s) (no t e 1 ) the pres cale r outpu t cloc k tn must be selected s o that tn< fs y s /2 is satisfied (so that t n is slo w e r than fs y s /2 ). (no t e 2 ) do not c h an ge the cloc k gear w h ile th e timer is operating. (no t e 3 ) " ? " de notes a setting pr ohibited. tmp19a43 (rev2.0) 11 - 7 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 11.2.2 up-counter (uc0) and up-counter capture registers (tb0ucl, tb0uch) th is is th e 16 -b it b i n a ry co un ter t h at co un ts u p in respon se to th e inpu t clo c k sp ecified by tb0 m od . uc0 i n put cloc k ca n be selected from either three types - t1, t4 and t1 6 - o f presca l e r o u t p ut cl oc k or t h e e x t e r n al cl oc k of t h e tb 0 i n 0 p i n. f o r u c 0 , star t, stop and clear are s p ecified by tb0 r un an d i f uc0 m a tch e s th e tb0 r g1h/l tim er reg i ster , it is cleared to "0 " if t h e settin g is "clear en ab le." clear en ab le/d isa b l e is speci fied by tb0mod. if t h e setting is "clear d i sab l e," th e co un ter op erates as a free-ru nn ing cou n ter . the c u r r e n t co unt val u e o f t h e uc 0 ca n be c a pt u r ed by rea d i n g t h e tb 0 u c l an d tb 0 u c h re gi st ers . note make sur e th at readin g is performe d in the orde r of lo w - ord er b i t s follo w e d b y high-ord er b i t s . if uc0 o v e rfl o w occu rs, the i n ttb 01 o v er f l ow i n terr u p t is ge nerate d. tm r b 2 , tm r b 3, tm r b 6 a n d tm r b 7 ha ve t h e t w o - p h a s e p u l s e i n p u t cou n t fu nct i o n. t h e t w o- pha s e pul se c o unt m ode i s act i v at ed by tb 2r u n . t h i s co u n t e r ser v es a s t h e up -an d - d o w n co un ter , and is in itialized to 0x 7fff . if a cou n t er ov erflow o ccurs, t h e in i tial v a lu e 0x 000 0 is relo ad ed. if a c o unter underflow oc curs , the initial val u e 0xffff c o unt is c ontin ue d.. whe n the t w o-phase puls e co un t m o d e is n o t active, t h e co un ter coun ts u p on ly . 11.2.3 t i mer registers (tb0 rg0h/l, tb0rg1h/l) th ese are 1 6 -bit reg i sters for sp ecifying co un ter v a lu es and two reg i sters are bu ilt in to each ch ann e l. if a val u e set on t h i s t i m e r regi s t er m a t c hes t h at on a uc 0 u p -c o unt er , t h e m a t c h det ect i on si g n al o f t h e com p arator be com e s active. t o write d a ta to t h e tb 0 r g0h/l and tb0 r g1 h/l tim er re gisters, either a 2- by t e dat a t r a n s f er in stru ction o r a 1 - b y te d a ta tran sfer in stru ction writte n twice in th e ord e r of lo w-ord e r 8 b i ts fo llowed b y hi g h - o r d e r 8 bi t s can be use d . tb 0r g 0 of t h i s t i m er regi st er i s pai r ed wi t h regi st er bu f f e r 0 - a do u b l e - b u f fe re d c o n f i g urat i o n. tb 0r g 0 us es tb 0r u n t o c ont rol t h e e n a b l i ng/ di sabl i n g of do u b l e bu f f e r i n g so t h at i f = "0," do u b l e bu f f e r i n g i s di sabl ed a n d i f = "1 ," it is en ab led . if do ub l e bu f f e r i n g i s e n abl e d, dat a i s t r ans f er re d f r o m regi st er bu f f er 0 t o t h e tb 0r g 0 t i m er regi st er whe n t h ere i s a m a t c h bet w een uc 0 a n d tb 0r g1 . the val u es of tb 0r g 0 h/ l a n d tb 0r g 1 h/ l becom e u n d e fi ne d a f t e r a r e set so t o use a 1 6 - b i t t i m er , i t is necess a ry t o write data to t h em before hand. a reset initi alizes tb0run to "0" a n d set s d oub le buf f e r i n g to "d isab le." t o u s e do uble b u f f er ing , write d a ta to th e ti m e r reg i ster , set to "1 " and t h en write t h e fo llowing d a ta to t h e reg i ster b u f f ers. tb 0r g 0 a n d t h e regi st er b u f f ers are a ssi g n e d t o t h e sam e ad dres s: 0 x f fff _f 14 8/ 0 x f fff _f 14 9. i f = "0," t h e sam e value is written to tb0r g0 and each re gister buf fe r; if = "1 ," th e v a l u e is only written to each reg i ster b u f f er . t o wr ite an in itial v a lu e t o th e tim er register , th erefore, th e reg i ster bu f f ers m u st b e set to "d isab le." note ) please re write neither t b xrg1 nor t b xrg0 a do uble b u f f er un u s ed wh ile th e timer is work ing . no te) wh en a d oub le buf fer i s u s ed , d a ta is n o t up d a ted wh ile rewriting tbx r eg0 . tmp19a43 (rev2.0) 11 - 8 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 cap t u r e reg i st ers (tb0 cp0h/l, tb0 c p1h/l) these are 16 -b i t regi st ers fo r l a t c hi ng val u es f r om t h e u c 0 up - c oun ter . t o r e ad d a ta f r om th e cap ture reg i ster , u s e eith er a 2 - o r 1 - b y te d a ta tran sfer instru ct io n . please read it in o r d e r o f t h e title in sub o r di nat e p o s i t i on 11.2.4 capture th is is a circu i t th at co n t ro ls th e ti m i n g o f l a tch i n g v a lu es fro m th e uc0 u p -coun ter in t o th e tb 0 c p0 and tb 0c p 1 capt u re re gi st ers. t h e t i m i ng wi t h w h i c h t o l a t c h dat a i s speci fi ed by tb 0m o d . soft ware ca n al so be use d t o im port val u es f r om t h e uc 0 up -c ou nt er i n t o t h e ca pt u r e re gi st er; specifically , uc0 val u es are taken int o the tb0c p0 ca pture re gister each tim e "0" is written to tb0 m od . t o u s e th is cap ab ilit y , th e p r escaler m u st b e ru nn i n g (tb 0 run = "1"). in t h e two - ph ase pu lse coun t m o d e (fo r t h e tmrb2 , tmr b 3 , tmrb6 an d tmrb7 o n ly), th e co un ter val u e i s capt u r e d by u s i n g s o f t ware. (no t e 1 ) althou gh a r ead of lo w - o rder 8 bit s in the cap ture registe r sus p ends the capture ope r a tion, it is resumed b y su cces siv e l y r eading high-order 8 bit s . (no t e 2 ) if the timer s t op s af ter a r ead of lo w - o rder 8 bit s , the cap ture o p eratio n rem a ins suspe nded e v en af ter the timer rest art s . please en sure th at the timer is not stopp ed af te r a read of lo w - o r d e r 8 bit s . 11.2.5 comp arato r s (cp0, cp1) these a r e 16-bit co m p arators for detecting a match by com p ari ng set val u es of t h e uc 0 up -c ou nt er wi t h set val u es o f t h e tb 0r g0 an d tb 0r g1 t i m e r re gi st ers . i f a m a t c h i s det ect ed, i n ttb 0 i s gene rat e d . 11.2.6 t i mer flip-flop (tb0ff0) th e tim er flip -flop (tb0 ff0) is rev e rsed b y a m a tc h si gna l fr om t h e co m p arat or and a latch signal t o th e cap ture reg i sters. it can b e en ab led or d i sab l ed to rev e rse b y setting th e tb 0 ffc r. th e v a lu e o f tb0 f f0 b eco m e s un d e fin e d after a reset. th e flip-fl o p can be rev e rsed by writin g "00 " to tb 0ffc r < tb 0ff 0 c 1 : 0 >. i t can be set t o "1" by w r i t i ng " 0 1 , " a n d ca n be cl ea red t o "0" by w r i t i n g "10." the val u e o f tb 0ff 0 ca n b e o u t p ut t o t h e t i m e r out put pi n, tb 0 o ut (sha re d wi t h p 5 4 ) . t o e n abl e t i m e r out p u t , t h e po rt 5 rel a t e d regi st ers p 5 c r an d p 5 fc m u st be pr og ram m e d be fo reha n d . tmp19a43 (rev2.0) 11 - 9 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 tmp19a43(rev2.0) 11-10 16-bit timer/event counters (tmrbs) 11.3 register description tmrbn run register (n=0, 1, 4, 5, 8 through f) 7 6 5 4 3 2 1 0 bit symbol tbnrde i2tbn tbnprun tbnrun read/write r/w r/w r/w r/w r/w r/w r r/w after reset 0 0 0 0 0 0 0 0 function double buffering 0: disable 1: enable write "0." write "0." write "0." in the idle mode 0: stop 1: operate timer run/stop control 0: stop & clear 1: count * the first bit can be read as "0." : controls the tmrb0 count operation. : controls the tmrb0 prescaler operation. : controls the operation in the idle mode. : controls enabling/disabling of double buffering. (note 1) the value read from bit 1 of tbnrun is "0." (note 2) do not set bits 7 to 3 (counter operating conditions) and bits 2 to 0 (count start) simultaneously tmrbm run register (m=2, 3, 6, 7) 7 6 5 4 3 2 1 0 bit symbol tbmrde udmck tbmudce i2tbm tbmprun tbmrun read/write r/w r/w r/w r/w r/w r/w r r/w after reset 0 0 0 0 0 0 0 0 function double buffering 0: disable 1: enable write "0." sampling clock 0: fs 1: t0/4 enable/ disable two-phase counter 0: disable 1: enable idle 0: stop 1: operate timer run/stop control 0: stop & clear 1: count * the first bit can be read as "0." : controls the tmrb0 count operation. : controls the tmrb0 prescaler operation. : controls the operation in the idle mode. : controls enabling/disabling of the two-phase pulse input count operation. enable: the counter counts up and counts down. disable: this is the normal timer mode and the counter counts up only. : selects the two-phase pulse input sampling clock. : controls enabling/disabling of double buffering. (note 1) the value read from bit 1 of tbmrun is "0." (note 2) do not set bits 7 to 3 (counter operating conditions) and bits 2 to 0 (count start) simultaneously. fig. 11-3 tmrb-related registers tbnrun (0xffff_f1x0) tbnrun (0xffff_f1x0)
tmp19a43 tmrbn con t rol register (n=2, 3, 6, 7) 7 6 5 4 3 2 1 0 bit sy mbol tbnen tbns yc udnnf udncn t r e a d / w r i t e r / w r / w r r r / w r / w r / w r a f t e r r e s e t 0 0 0 0 0 0 0 0 function tmrbn operation 0: disable 1: enable write "0." this can be read as "0." this can be read as "0." sy nchr oni z a ti on m o d e sw itch- ov er 0: in di v i dual o per ati on 1: sy nchr on ous o per ati o n digit a l noise filter 0: no use 1: use mode sw itch-ov e r 0: normal 1: quad ruple this can be read as "0." tbncr (0x f f ff_ f1x 1 ) tmrbn con t rol register (n=0, 1, 4, 5, 8 throug h f) 7 6 5 4 3 2 1 0 b i t sy m b o l t b n e n tbns y c r e a d / w r i t e r / w r / w r r r / w r r r a f t e r r e s e t 0 0 0 0 0 0 0 0 function tmrbn operation 0: disable 1: enable write "0." this can be read as "0." this can be read as "0." sy nchr oni z a ti on m o d e sw itch- ov er 0: in di v i dual o per ati on 1: sy nchr on ous o per ati o n this can be read as "0." this can be read as "0." this can be read as "0." tbncr (0x f f ff_ f1x 1 ) : s pecifie s the tmrb ope rat i on. when the oper atio n is disabled, no clo ck is su ppl ied to th e other regi sters in the tm rb module. t h is ca n redu ce po we r di ssip ation. (th i s disable s readi ng from and writing to the other regi st ers.) t o use the t m rb, enable the tmrb operation (set to "1") before prog rammi ng each regi ster in the tmrb module. if the tmr b operation is e x ecuted a nd then di sable d , setti ngs will be maint a i n e d in each regi ster . tmrbn mod e registe r (n =0 th rough f ) 7 6 5 4 3 2 1 0 bit sy mbol tbncp0 tbncpm1 t bncpm0 tbncle tbnclk1 tbnclk0 r e a d / w r i t e r w r / w a f t e r r e s e t 0 0 1 0 0 0 0 0 function this can be read as "00." capture control b y softw a r e 0: cap t ure by so f t w a re 1: don' t c a re capture timing 00: di sable 01: tbn i n0 tbnin1 10: tbn i n0 tbnin0 11: tb3 o ut tb3 o ut up-counte r control 0: clear/dis able 1: clear/enable selects sour ce cl ock 00: tb0in0 pin input 01: t1 10: t4 11: t16 tbnmo d (0x f f ff_ f1x 2 ) : s e lect s t h e tmrb n t i me r cou n t clo ck. : clea rs a nd control s the t m rbn up -cou nter . "0": disable s cl ea ring of the up -co unte r . "1": clea rs u p -co unter if there i s a match wit h timer regi st er 1 (tbn rg 1). : s pecifie s t m rbn capture timing. "00": capture disa ble "01": t a kes cou n t values into ca pture regi ster 0 (tbncp0 ) upon the ri sin g of tbnin0 pin input. t a kes cou n t values into ca pture regi ster 1 (tbncp1 ) upon the ri sin g of tbnin1 pin input. "10": t a kes cou n t values into ca pture regi ster 0 (tbncp0 ) upon the ri sin g of tbnin0 pin input. t a kes cou n t values into ca pture regi ster 1 (tbncp1 ) upon the falli ng of tbnin0 pin input. tmp19a43 (rev2.0) 11 - 1 1 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 "1 1": t a kes cou n t values into capture regi ster 0 (tbn cp 0) upo n the rising of 16 -bi t timer match output (tb 3 o u t) and i n to captu r e regi st er 1 (tbn cp 1) u pon th e falling of tbx o ut (tm r b 1 throug h tmrb7). : captu r e s co u n t values by sof t wa re and t a ke s them int o captu r e regi ster 0 (tbncp0). (no t e ) the v a lue re ad from bit 5 of tbnm od is "1." fig. 1 1 -4 tm rb-related registe r tmrbn flip-flop control r e gister (n =0 throug h f) 7 6 5 4 3 2 1 0 bit sy mbol tbnc1t 1 t bnc0t 1 tbne1t1 t bne0t1 tbnff 0 c 1 tbnff 0 c 0 r e a d / w r i t e r r / w r / w a f t e r r e s e t 1 1 0 0 0 0 1 1 tbnff 0 reverse trigger 0: disable trigger 1: enable trigger function this is alw a y s re ad as "11." w hen the up-coun ter v a lue is take n in to tbncp1 w hen the up-coun ter v a lue is take n in to tbncp0 w hen the up-coun ter mat c he s tbnrg1 w hen the up-coun ter mat c he s tbnrg0 tbnff 0 control 00: invert 01: set 10: clear 11: don't care * this is alw a y s as "11." tbnff cr (0x f f ff_ f1x 3 ) : co ntrol s the timer flip-fl op. "00": reverse s the value of tbnff0 (reverse by usin g sof t wa re ). "01": set s tbnff0 to "1." "10": clears tbnff0 to "0." "1 1": don't c a re : reverse s th e timer flip-flop whe n the up-cou n ter matche s the timer regi ster 0, 1 (tbnr g 0,1 ) . : reverse s the timer flip-flo p whe n the u p -counte r val ue is t a ke n into the ca ptu r e re giste r 0,1 (tbn cp0,1). fig. 1 1 -5 tm rb-related registe r tmp19a43 (rev2.0) 11 - 1 2 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 tmrbn st a t u s registe r (n =0, 1, 4, 5, 8 throug h f) 7 6 5 4 3 2 1 0 bit sy mbol i n ttbofn i n t t b n 1 i n t t b n 0 r e a d / w r i t e r r after reset 0 0 0 0 function this can be read as "0." 0: in terrup t n o t g enera t ed 1: in terrup t g enera t ed 0: in terrup t n o t g enera t ed 1: in terrup t g enera t ed 0: in terrup t n o t g enera t ed 1: in terrup t g enera t ed tbnst (0x f f ff_ f1x 4 ) : in terrup t g e n e rated if t h ere is a m a tch with timer reg i ster 0 (tbn rg0 ) : in terrup t g e n e rated if t h ere is a m a tch with timer reg i ster 1 (tbn rg1 ) : in ter r up t g e n e r a ted if an up- co un ter ov erf l ow o ccur s (no t e ) if an y interru pt is gener a ted, the flag that cor r esp o nds to th e interrup t is se t to tbnst a nd the gen e ra tion of interr u p t is notified to intc . th e flag is clea red b y reading the t b ns t registe r . tmrbm st atus register (m=2, 3, 6, 7) c when t b m r u n = 0: normal time r mode 7 6 5 4 3 2 1 0 bit sy mbol i n ttbofm i n t t b m 1 i n t t b m 0 r e a d / w r i t e r r after reset 0 0 0 0 function this can be read as "0." 0: in terrup t n o t g enera t ed 1: in terrup t g enera t ed 0: in terrup t n o t g enera t ed 1: in terrup t g enera t ed 0: in terrup t n o t g enera t ed 1: in terrup t g enera t ed tbnst (0x f f ff_ f1x 4 ) : int e r r upt ge ner a t e d i f t h ere i s a m a tch with timer reg i ster 0 (tb m rg0 ) : int e r r upt ge ner a t e d i f t h ere i s a m a tch with timer reg i ster 1 (tb m rg1 ) : int e r r upt ge n e rat e d i f a n up - c ou nt er o v er fl o w occu rs (no t e ) if an y interru pt is gener a ted, the flag th at cor r esp o nds to th e interrup t is se t to tbmst a nd the gen e ra tion of interr u p t is notified to intc . th e flag is clea red b y reading the t b mst registe r . d when t b m r u n = 1: t w o - pha se p u lse input c ount mode 7 6 5 4 3 2 1 0 bit sy mbol i n t t b u d m i n ttbudfm i n t t b o u f m r e a d / w r i t e r r after reset 0 0 0 0 0 function this can be read as "0." up-and- dow n count 0: n o t g enera t ed 1: genera t ed underflow 0: n o t g enera t ed 1: genera t ed ov erflow 0: n o t g enera t ed 1: genera t ed this can be read as "0." tbnst (0x f f ff_ f1x 4 ) inttbudf2: an up-and-down counter und erflo w occurs. inttbouf2: an up-and-down counter ov erflow occurs. inttbud2: an up- or down-co unt occurs. : i n ter r up t gen e r a ted if an u p - a n d - dow n co un ter ov erf l ow o ccur s : i n ter r up t gen e r a ted if an u p - a n d - dow n co un ter und erf l o w o c cur s : int e r r upt ge nerat e d i f an u p - o r do w n -c o unt occ u rs (no t e ) if an y interru pt is gener a ted, the flag th at cor r esp o nds to th e interrup t is se t to tbmst a nd the gen e ra tion of interr u p t is notified to intc . th e flag is clea red b y reading the t b mst registe r . fig. 1 1 -6 tm rb-related registe r tmp19a43 (rev2.0) 11 - 1 3 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 tbn r g0 h/l and tbn r g 1 h/l timer re gisters tbnrg0 h/l ti me r re gis t e r s (n=0 thro ugh f) 7 6 5 4 3 2 1 0 bit sy mbol t b n r g 0 l 7 t b n r g 0 l 6 tbnrg0l5 tbnrg0l4 tbnrg0l3 tbnrg0l2 t b n r g 0 l 1 t b n r g 0 l 0 r e a d / w r i t e w after reset undefined function timer count valu e, data of lo w-order 8 bits tbnr g0l (0x f f ff_ f1x 8 ) 7 6 5 4 3 2 1 0 bit sy mbol t b n r g 0 h 7 t b n r g 0 h 6 tbnrg0h5 tbnrg0h4 tbnrg0h3 tbnrg0h2 t b n r g 0 h 1 t b n r g 0 h 0 r e a d / w r i t e w after reset undefined function timer count valu e, d ata of high -o rder 8 bits tbnr g0h (0x f f ff_ f1x 9 ) (no t e ) t o w r ite d a t a to the timer registe r s, us e either a 2 - b y te dat a tra n sfer instruc tion o r a 1-b y te dat a tran sfe r instruc tion w r i tte n t w i ce in the ord er of lo w - ord er 8 bit s follo w e d b y high-order 8 bit s . tbn r g1 h/l timer registe r s (n =0 thr o u gh f) 7 6 5 4 3 2 1 0 bit sy mbol t b n r g 1 l 7 t b n r g 1 l 6 tbnrg1l5 tbnrg1l4 tbnrg1l3 tbnrg1l2 t b n r g 1 l 1 t b n r g 1 l 0 r e a d / w r i t e w after reset undefined function timer count valu e, data of lo w-order 8 bits tbnr g1l (0x f f ff_ f1xa ) 7 6 5 4 3 2 1 0 bit sy mbol t b n r g 1 h 7 t b n r g 1 h 6 tbnrg1h5 tbnrg1h4 tbnrg1h3 tbnrg1h2 t b n r g 1 h 1 t b n r g 1 h 0 r e a d / w r i t e w after reset undefined function timer count valu e, d ata of high -o rder 8 bits tbnr g1h (0x f f ff_ f1xb ) (no t e ) t o w r ite d a t a to the timer registe r s, us e either a 2 - b y te dat a tra n sfer instruc tion o r a 1-b y te dat a tran sfe r instruc tion w r i tte n t w i ce in the ord er of lo w - ord er 8 bit s follo w e d b y high-order 8 bit s . tmp19a43 (rev2.0) 11 - 1 4 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 tbn c p0h/l and tbn c p1 h/l cap ture registe r s tbn c p0h/l capture regi ster s (n =0 th rough f) 7 6 5 4 3 2 1 0 bit sy mbol t b n c p 0 l 7 t b n c p 0 l 6 tbncp0l5 tbncp0l4 tbncp0l3 tbncp0l2 t b n c p 0 l 1 t b n c p 0 l 0 r e a d / w r i t e r after reset undefined function timer capture va lue, data of lo w - order 8 bits tbncp0l (0x f f ff_ f1x c ) 7 6 5 4 3 2 1 0 bit sy mbol t b n c p 0 h 7 t b n c p 0 h 6 tbncp0h5 tbncp0h4 tbncp0h3 tbncp0h2 t b n c p 0 h 1 t b n c p 0 h 0 r e a d / w r i t e r after reset undefined function timer capture va lue, data of high-order 8 bits tbncp0h (0x f f ff_ f1x d ) (no t e ) t o read d a t a from the c a p t ure re gister s, use a 1-by te dat a tran s f er instruc tion w r i t ten t w i c e in the order of lo w - or der 8 bit s follo w e d b y high- order 8 bit s . don' t use a 2-b y te dat a transfer instr u ction. tbn c p1h/l capture regi ster s (n =0 th rough f) 7 6 5 4 3 2 1 0 bit sy mbol t b n c p 1 l 7 t b n c p 1 l 6 tbncp1l5 tbncp1l4 tbncp1l3 tbncp1l2 t b n c p 1 l 1 t b n c p 1 l 0 r e a d / w r i t e r after reset undefined function timer capture va lue, data of lo w - order 8 bits tbncp1l (0x f f ff_ f1xe ) 7 6 5 4 3 2 1 0 bit sy mbol t b n c p 1 h 7 t b n c p 1 h 6 tbncp1h5 tbncp1h4 tbncp1h3 tbncp1h2 t b n c p 1 h 1 t b n c p 1 h 0 r e a d / w r i t e r after reset undefined function timer capture va lue, data of high-order 8 bits tbncp1h (0x f f ff_ f1x f ) (no t e ) t o read d a t a from the c a p t ure re gister s, use a 1-by te dat a tran s f er instruc tion w r i t ten t w i c e in the order of lo w - or der 8 bit s follo w e d b y high- order 8 bit s . don' t use a 2-b y te dat a transfer instr u ction. tmp19a43 (rev2.0) 11 - 1 5 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 11.4 description of operations for each mode 11.4.1 16-bit interval t i mer mode gene rat i n g i n t e rr upt s at pe ri o d i c cy cl es t o g e n e rate the inttb0 in terru p t , sp ecify a ti m e in terv al in th e tb0 r g1 ti m e r reg i ster . 7 6 5 4 3 2 1 0 t b 0 c r 1 0 x x x x x x starts th e tmr b 0 module. t b 0run 0 0 0 0 ? 0 x 0 stops tmrb0. imc8 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 enabl e s inttb 0 , and sets it to l e vel 4. 0 1 1 0 0 1 0 0 (setting of int t b 0 onl y is show n here . th is is a 32-bit register and requ ires settings of o t her interrup t s as well .) 0 1 1 0 0 0 0 0 t b 0ffcr 1 1 0 0 0 0 1 1 disables th e trig ger. tb 0 m o d 0 0 1 0 0 1 * * designates the p r escaler ou tput clock as th e inpu t clo c k, t b 0rg 1l * * * * * * * * and spec ifi e s the tim e inte rval . t b 0 r g 1 h * * * * * * * * (16 bits) t b 0run 0 0 0 0 ? 1 x 1 starts tmrb0. x; don't car e ? ; no chan g e 11.4.2 16-bit event counter mode b y usi n g a n i n p u t cl oc k as an e x t e r n al cl o c k ( t b 0 in 0 pi n i n p u t ) , i t i s pos si bl e t o m a ke i t t h e e v e n t counter . the up -c ou nt e r co u n t s u p on t h e ri si n g e dge of tb 0 i n 0 pi n i n put . b y capt u ri n g a val u e usi n g s o ft war e an d read ing t h e cap tured v a lue, it is po ssi b l e to read th e cou n t v a lu e. 7 6 5 4 3 2 1 0 t b 0cr 1 0 x x x x x x starts th e tmr b 0 module. t b 0run 0 0 0 0 ? 0 x 0 stops tmrb0. p2cr ? ? ? ? ? ? ? 0 p2fc ? ? ? ? ? ? ? 1 sets p20 to the input mode. p2fc2 ? ? ? ? ? ? ? 0 imc8 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 enabl e s inttb 0 , and sets it to l e vel 4. 0 1 1 0 0 1 0 0 (setting of int t b 0 onl y is show n here . th is is a 32-bit register and requ ires settings of o t her interrup t s as well .) 0 1 1 0 0 0 0 0 t b 0ffcr 1 1 0 0 0 0 1 1 disables th e trig ger. tb 0 m o d 0 0 1 0 0 1 0 0 designates the tb0in0 pin i npu t as the input clock. t b 0run 0 0 0 0 ? 1 x 1 starts tmrb0. tb 0 m o d x x 0 0 0 1 0 0 captures a v a lue using softwar e . t b 0rg 1l * * * * * * * * specifi es the t i m e in terva l . t b 0 r g 1 h * * * * * * * * (16 bits) x; don't car e ? ; no chan g e t o be use d a s the ev ent counte r , put the presc aler in a "run" st ate ( t b0run < t b 0 prun > = "1"). tmp19a43 (rev2.0) 11 - 1 6 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 11.4.3 16-bit ppg (programm a ble square w a ve) ou tput mode sq uare waves wi t h a n y fr eq uency an d a n y d u t y (p ro g r a m m a bl e squa r e wa ves ) c a n be o u t p ut . t h e out put p u l s e ca n be ei t h e r l o w - act i v e or hi gh -act i v e. pro g r am m a bl e sq uare wa ves can be out pu t fr om t h e tb 0o ut pi n by t r i gge ri n g t h e t i m e r fl i p -fl o p (tb0ff) t o rev e rse wh en the set v a lu e of th e up -cou n t er m a tch e s th e set v a lu es o f the ti m e r reg i sters (tb0 r g 0h/l an d tb 0 r g1h/l). no te th at th e set val u es o f tb 0r g0 h/ l an d t b 0r g 1 h/ l m u st satisfy th e fo ll o w i n g requ iremen t: (set val u e of t b 0r g 0 h/ l ) < (set val u e of t b 0r g 1 h/ l ) m a t c h w i t h t b 0rg0h/ l (i nt t b 0 i n t e rrupt ) m a t c h w i t h t b 0rg1h/ l (i nt t b 1 i n t e rrupt ) tb 0out p i n fig. 1 1 -7 example of outp ut of program mable squ a re w a ve (ppg ) in th is m o d e , by en ab lin g th e d oub le b u f f erin g of tb0 r g0 h/ l, t h e val u e of re gi st er b u f f er 0 i s shi f t e d in to tb 0 r g0h/l wh en t h e set v a lu e of the up -co u n t er match e s th e set v a lu e o f tb 0 r g1 h/l. this facilitates h a ndlin g o f sm all d u ties. q 1 q 2 q 2 q 3 t r i gger t o s h i f t t o t b 0rg1 up-c ount er = q 1 up-c ount er = q 2 m a tch w i th t b 0 r g 0 m a tch w i th t b 0 r g 1 tb0 r g0 (c o m pare val ue) regi s t er bu f f e r w r i t e t b 0rg0 fig. 1 1 -8 re g i ster buf f er o peratio n note: double bu ffe r ing is a v aila ble for tb0r g0 only . pa y attention to change s to tb0 r g1. tmp19a43 (rev2.0) 11 - 1 7 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 the bl oc k di ag ram of t h i s m ode i s s h ow n be l o w . se le c t o r se le c t o r t b 0run matc h tb0 r g0 16-bi t c o m parat or regi s t er bu f f e r 0 16-bi t up-c ount er uc0 f/f (t b 0 f f 0 ) 16-bi t c o m parat or i n t e rnal dat a bus tb0 r g1 tb0 r g0 - w r tb 0 i n 0 t1 t4 t1 6 t b 0out ( p p g out pu t ) t b 0run cl ear fig. 1 1 -9 block dia g ra m of 16-bit ppg m ode each regi st e r i n t h e 1 6 - bi t p p g out put m ode m u st be p r o g r am m e d as l i s t e d bel o w . 7 6 5 4 3 2 1 0 t b 0cr 1 0 x x x x x x starts th e tmr b 0 module. t b 0run 0 0 0 0 ? 0 x 0 disables th e tb 0rg0 double bu ffering and stops tmrb0. t b 0rg 0l * * * * * * * * specifies a duty . (16 bits) tb 0 r g 0 h * * * * * * * * t b 0rg 1l * * * * * * * * spe c i fie s a cy cl e. (16 bi t s ) tb 0 r g 1 h * * * * * * * * t b 0run 1 0 0 0 ? 0 x 0 enables the tb0 r g0 double buf f e ring. (changes th e du ty /cy c le wh en th e inttb0 interru pt is generated) t b 0ffcr x x 0 0 1 1 1 0 specifi es to trig ger tb0ff0 to r e verse wh en a m a tch with tb0rg0 or tb0rg1 is d e tected , and sets th e initi al valu e of t b 0ff0 to "0." tb 0 m o d 0 0 1 0 0 1 * * (** = 01, 10, 1 1 ) designates the p r escaler ou tput clock as th e inpu t clo c k, and dis a b l es the captur e fun c tion . p5cr ? ? ? 1 ? ? ? ? p5fc ? ? ? 1 ? ? ? ? assigns p54 to tb0out. p5fc2 ? ? ? 0 ? ? ? ? t b 0run 1 0 0 0 ? 1 x 1 starts tmrb0. x; don't car e ? ; no c h an ge tmp19a43 (rev2.0) 11 - 1 8 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 11.4.4 t i mer sy nc hronization mode the t i m ers can be st art e d sy n c hr o n o u sl y by usi n g t h e t i m er sy nc hr oni zat i o n m ode. the sy nch r oni zat i on m ode ca n be use d f o r p p g o u t p ut , fo r exam pl e, fo r a ppl i cat i o n t o d r i v i n g a m o t o r . tbn cr is u s ed to tu rn t h e syn c hron izatio n m o d e on /of f . =" 0": ope r ates the tim e rs at the timing s p ecifie d for eac h c h annel. =" 1": e n abl e s t h e sy nc hr on o u s o u t p ut . th ere are fou r b l o c k s , tmrb0 thro ugh tmrb3 , tmrb 4 t h ro ugh tmrb7 , tmrb 8 th ro ugh tmr b b an d tmrbc th rou g h tmrb f . if is set to "1 ," t h e ti m e rs will n o t star t at th e ti min g sp ecified fo r each chan n e l b y settin g tb m r un to "1 ,1", b u t th e tim e r s i n each b l o c k will start in syn c hron izatio n with tmrb0, tmrb4 , tmr b 8 o r tmrbc. not e : ? for the ch an nels to be o u tpu t s y nchronously , set tbmrun to "1,1" to enabl e simult aneo us st ar t befo re st arting t m rb0, tmrb4, tmrb8 or t m rbc. ? set tbn c r to "0" unless the s y nchronous outp u t mode is sele c ted. when the s y nchrono us o u tpu t mode is selected, o t her ch annel s w i ll not st a r t until tmrb0, 4 , 8 and c st art. n o te) mas tert mrb 0,t mrb 4,t mrb 8,t mrb c wri te tbn syc0 7 6 5 4 3 2 1 0 bit sy mbol t b n e n tbnsy c read/write r / w r / w r r r/w r r r after reset 0 0 0 0 0 0 0 0 function tmrbn operation 0: disable 1: enable write "0." this can be read as "0." this can be read as "0." write?0? this can be read as "0." this can be read as "0." this can be read as "0." tbncr (0x f f ff_ f1x 1 ) slavew rit e t bns yc 1 7 6 5 4 3 2 1 0 bit sy mbol tbnen tbnsy c r e a d / w r i t e r / w r / w r r r/w r r r a f t e r r e s e t 0 0 0 0 0 0 0 0 function tmrbn operation 0: disable 1: enable write "0." this can be read as "0." this can be read as "0." write "1" this can be read as "0." this can be read as "0." this can be read as "0." tbncr (0x f f ff_ f1x 1 ) tmp19a43 (rev2.0) 11 - 1 9 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 applications using the capture function the ca pt u r e fu nct i o n can b e u s ed t o devel o p m a ny appl i cat i ons , i n cl u d i n g t hose desc ri be d bel o w: c one - s hot p u l s e o u t p ut t r i g ge r e d by an ext e rn al pul se d fre que ncy m e asurem ent e pulse widt h measurem ent f t i m e dif f ere n c e m easure m ent c one - s hot p u l s e o u t p ut t r i g ge r e d by an ext e rn al pul se one - s hot p u l s e o u t p ut t r i g ge r e d by an ext e rn al pul se i s car ri ed out a s f o l l o ws: th e 16 -b it u p -co u n t er (uc 6 ) is m a d e to coun t u p b y p u tting it i n a free-run n i n g state u s i n g th e p r escaler out put cl oc k. an e x t e r n al p u l se i s i nput t h r o u g h t h e tb 6i n0 pi n . a t r i g ger i s gene rat e d at t h e ri si n g of th e ex tern al p u lse b y u s i n g the cap t u re fun c tio n and th e v a l u e o f th e u p -cou n t er is tak e n i n to th e cap t u re registers (tb 6 cp0h/l ). the intc m u s t be pr ogram m ed s o that a n interrupt i n t 0 is g e n e rated at the rising of an ex tern al trigg e r p u l se. th is i n terrup t is u s ed to set th e ti m e r reg i sters (tb 6 rg0 h /l) to th e su m o f th e tb6 c p0 v a lu e (c) a n d t h e d e lay tim e (d), (c + d ) , and set th e tim er reg i sters (tb 6 rg1 h /l) t o th e su m o f the tb 6r g 0 h/ l v a l u es a n d t h e p u l s e wi dt h ( p ) of o n e- sh ot pul se, (c + d + p) . in add ition , t h e ti m e r flip -flop con t ro l reg i sters (t b6ffcr ) m u st b e set to "1 1 . " th is en ab les t r ig g e ring th e ti mer flip -flop (tb6 ff 0 ) t o re verse w h e n u c 6 m a t c hes tb 6r g 0 h/ l an d tb 6r g 1 h/ l. thi s t r i gge r i s di sabl e d by t h e in ttb6 in terru p t after a on e-sh o t pu lse is ou tpu t . sym bol s (c ), ( d ) a n d ( p ) use d i n t h e t e xt c o r r esp o nd t o sy m bol s c, d an d p i n fi g. 1 1 - 1 0 o n e - sh ot p u l s e ou t p u t (w ith delay)." t i m e r out pu t t b 6out pi n c + d + p c + d c di s abl e revers e w hen dat a i s t a k en i n t o c a p 6 e nabl e revers e (p) (d) pu lse w i d t h del a y t i m e e nabl e revers e in ttb6 generat i on t a k i ng da t a i n t o t h e c apt ure regi s t er (ca p 6 ) i n t 0 generat i on count c l o c k (i nt ernal c l ock ) p u t t he c ount er i n a f r ee-runn i ng st at e t b 6i n0 p i n i nput (e x t ernal t r i gger pul s e ) m a t c h w i t h t b 6rg0h/ l m a t c h w i t h t b 6rg1h/ l i n t t b 6 generat i on fig. 1 1 -10 on e-shot pulse output (with delay) tmp19a43 (rev2.0) 11 - 2 0 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 programming exam ple : out put a 2 - m s o n e-s h ot p u l s e t r i gge re d by an e x t e rn al p u l s e fr om t h e tb 6i n0 pi n wi t h a 3 - m s del a y * clock co nditi on s y stem clock : high speed (f c) high-speed clock gear : 1x (f c) p r es caler c l ock : fper iph/4 (fperi ph fs y s ) main pr ogram ming puts to a free-ru nning state 7 6 5 4 3 2 1 0 uses t1 for co unting. tb 6 m o d x x 1 0 1 0 0 1 takes d a ta in to tb6cp0 at the rising of tb6in0 input t b 6ffcr x x 0 0 0 0 1 0 clears tb6f f 0 t o zero disables tb6ff0 to r e verse p9cr ? ? ? ? ? ? ? 1 p9fc ? ? ? ? ? ? ? 1 assigns p90 pin to tb6out imc0 x x 0 0 0 0 0 0 x x 1 1 0 1 0 0 enables int0 an d disables inttb6 x x 0 0 0 0 0 0 imc9 x x x x 0 1 0 1 0 0 0 0 0 0 0 0 thes e are 32-bit regis t ers a nd mu st be all processed. x x 1 1 0 0 0 0 x x 1 1 0 0 0 0 x x 1 1 0 0 0 0 t b 6run ? 0 x 0 ? 1 x 1 starts tmrb6 int 0 programming tb 6 r g 0 t b 0cp0 + 3 ms/ t1 tb 6 r g 1 tb 0 r g 0 + 2 ms/ t1 t b 6ffcr x x ? ? 1 1 ? ? enabl e s tb2ff0 to r e verse when ther e is a m a tch with tb2rg0, 1 imc9 x x 1 1 0 0 0 0 x x 1 1 0 0 0 0 x x 1 1 0 0 0 0 enabl e s inttb 6 x x 1 1 0 1 0 0 int t b 6 progra mming t b 6ffcr x x ? ? 0 0 ? ? disables tb6ff0 to r e verse whe n ther e is a m a tc h with tb6rg0, 1 imc9 x x 1 1 0 0 0 0 x x 1 1 0 0 0 0 x x 1 1 0 0 0 0 x x 1 1 0 0 0 0 disables inttb6 x; don't car e ? ;n o chan ge if a del a y i s n o t re qui red , t b 6ff 0 i s reve r s ed whe n dat a i s t a ken i n t o t b 6c p0 , a nd t b 6r g 1 i s set t o t h e s u m of t h e tb 6c p o val u e (c) a n d t h e o n e-s h ot p u l s e wi dt h (p ), (c + p) , by gene rat i n g t h e i n t 0 i n t e rr upt . tb 6ff 0 i s ena b l e d t o re ve rse w h en uc 6 m a t c hes wi t h tb 6r g 1 , an d i s di sa bl ed b y gene rat i n g t h e int t b 6 i n t e rr upt . tmp19a43 (rev2.0) 11 - 2 1 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 c + p c e nabl e revers e (p) p u l s e wi dt h t a ki n g d a ta i n to th e c a p t u r e r e g i s t e r t b 6 c p 0 i n t 0 g ener at i o n count c l o c k (p res c a l e r out put cl ock ) tb 6i n0 i nput (e x t ernal t r i gger pul s e ) m a tch w i th t b 6 r g 1 ti m e r out pu t tb 6out pi n tak i ng da t a i n t o t he c apt ure regi s t er t b 6cp 1 i n ttb 6 generat i on e nabl e revers e w hen dat a i s t a k en i n t o tb 6c p 0 di s abl e revers e w hen dat a i s t a k e n i n t o tb6c p1 fig. 1 1 -1 1 o n e-shot pulse output t r i gge red by an external pul s e (without dela y) d fre que ncy m e asurem ent b y usi n g t h e c a pt u r e f u nct i o n , t h e fre q u ency o f a n e x t e rnal cl ock ca n be m easure d . t o m easu r e freq u e n c y , ano t h e r 1 6 -b it ti mer (tmrb0) i s u s ed i n co mb in ation with th e 1 6 -b it even t co un ter m o d e (tmrb0 r e v e rses tb0ffcr t o s p ecify the measurem ent time). the tb 3in0 pin input is sele cted as t h e t m rb3 c o u n t c l ock t o per f o r m t h e co u n t o p erat i o n usi n g an ex tern al inp u t clo c k . tb 3 m od is set to "1 1 . " th is settin g allo ws a cou n t v a l u e o f the 1 6 -b it uc0 up-coun ter to b e tak e n i n to t h e cap ture reg i ster (tb 0 cp0 ) up on t h e rising o f a ti m e r flip - fl o p (tb 3 ffc r ) of t h e 16 - b i t t i m e r (tm r b 3 ), a n d a n u c 0 c o unt e r val u e t o be t a ke n i n t o t h e capt u r e reg i ster (tb 0 c p 1 ) upo n th e fallin g of tb 3 ff of th e 16 -b it timer (tmrb3). a f r e que ncy i s t h en o b t a i n ed f r om t h e di f f e r e n ce bet w een tb 0c p 0 an d tb 0c p 1 ba sed o n t h e measu r em en t, b y g e n e ratin g th e inttb3 16-b it tim er in terrup t . co u n t c2 c1 c2 c1 c2 c1 c o u n t c l o c k ( t b 3 in 0 p i n in pu t ) tb 0 o u t ta k i ng da ta i n to tb 3 c p 0 ta k i ng da ta i n to tb 3 c p 1 in t t b 0 fig. 1 1 -12 freque ncy mea s ureme n t for exam pl e, i f t h e set wi dt h o f tb 3ff l e vel "1" of the 16 -b it ti m e r is 0 . 5 s and if th e d i f f eren ce bet w ee n tb 0c p0 a n d tb 0c p 1 i s 1 0 0 , t h e f r e que ncy i s 1 0 0 / 0. 5 s = 200 h z . tmp19a43 (rev2.0) 11 - 2 2 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 e pulse widt h measurem ent b y usi ng t h e capt u re f unct i o n , t h e "h" l e vel wi dt h of a n e x ternal pulse ca n be m easured. specifically , an ex tern al p u l se i s inpu t thr oug h th e tb0in 0 p i n and t h e up - c o u n t er (u c 6 ) is m a d e to count up b y pu ttin g it in a free - runni ng state usi n g the pre s caler output cloc k. a tri gge r is gene rated at each rising a n d fallin g ed g e o f th e ex tern al pu lse b y using th e cap t u re fu n c t i on an d t h e v a l u e o f t h e up - c ou nt er i s t a ke n into t h e capt u re registe r s (t b0cp0, tb0c p1). th e intc m u st be program m ed so t h at int0 i s g e n e rated at the fallin g edg e o f an ex tern al p u l se inp u t t h ro ugh th e tb6in0 p i n . th e "h" lev e l pu lse wid t h can b e calcu lated b y m u ltip lyin g th e d i f f eren ce b e t w een tb6 c p0 and tb6cp1 by the clock cycle of a n internal cl ock. for exam ple, if the dif f ere n c e betwee n tb 6cp0 an d tb 6cp1 is 100 a n d the cycle of the pre s caler out put cl oc k i s 0. 5 s, th e "h" lev e l pu lse wi d t h is 100 0.5 s = 50 s. c a ut i on m u st be exe r ci sed whe n m easuri ng p u l s e wi dt hs excee di n g t h e uc 2 m a xim u m count t i m e whi c h i s de pen d ant up o n t h e sou r ce cl oc k u s ed. t h e m easurem ent of s u c h p u l s e wi dt hs m u st be m a de usi n g s o ft ware . c2 c1 c2 c1 c2 c1 p r esc a l e r out pu t c l ock tb 6i n0 p i n i nput (e x t ernal pul s e ) tak i ng da t a i n t o t b 6cp 0 in t0 tak i ng da t a i n t o t b 6cp 1 fig. 1 1 -13 pu lse wi d t h me asu r em ent the "l" level width of an e x ternal pulse ca n also be m eas ure d . in s u c h cases, the dif f e r ence betwee n c2 g e n e rated th e first tim e a n d c1 g e n e rated t h e secon d ti m e is in itial l y o b t ai n e d b y p e rform i n g th e seco nd st age o f i n t 0 i n t e r r u pt p r oce ssi n g a s sh ow n i n "fi g . 1 1 -14 t i m e dif f e r e n ce me asurem ent," and th is d i f f eren ce is m u lt ip lied by th e cy cl e o f t h e prescal e r ou t put cl oc k t o o b t a i n t h e "l" l e vel wi dt h. tmp19a43 (rev2.0) 11 - 2 3 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 f t i m e dif f ere n c e measurem ent b y usi n g t h e c a pt u r e fu nct i o n, t h e t i m e di f f ere n ce be twee n two eve n ts c a n be m easure d . specifically , th e up -cou n t er (uc 6 ) is m a d e to coun t up b y p u ttin g it in a free-ru nn ing st ate u s ing th e prescaler o u t p u t cl ock. t h e val u e o f uc 6 i s t a ken i n t o t h e c a pt u r e re gi st er (tb 6 c p 0 ) at t h e ri si n g e dge of t h e tb 6 i n 0 pi n i n p u t pul se . t h e in tc m u st be pr og ram m e d t o gene rat e i n t0 i n t e r r u p t at t h i s t i m e. the val u e of u c 6 i s t a ke n i n t o t h e ca pt u r e r e gi st er tb 6c p 1 at t h e ri si ng edge o f t h e tb 6i n1 pi n i n put p u l se. th e intc m u st b e pro g ramm ed to gen e rate int1 in terrup t at th is ti m e . th e tim e d i f f eren ce can b e calcu l ated b y mu ltip lyin g t h e d i f f eren ce b e tween tb6 c p1 and tb 6 c p0 b y the cloc k cycle of a n internal clock. ti m e d i ffe r e n c e c2 c1 t b 6i n0 p i n i nput t b 6i n1 p i n i nput in t0 t a k i ng da t a i n t o t b 6cp 0 in t1 t ak i ng da t a i n t o t b 6cp 1 p r esc a l e r out pu t c l ock fig. 1 1 -14 t i me dif f ere n ce measureme n t tmp19a43 (rev2.0) 11 - 2 4 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 11.5 t w o-phas e pulse input count mode (tmrb2, tmrb3, tmrb6, tmrb7) (o perat i o ns ar e com m on t o t m r b 2 , 3, 6 a n d 7. t h i s sect i o n de scri be s t m r b 2 o n l y .) in th is m o d e , t h e co un ter is in crem en ted o r d e crem en ted b y on e d e p e ndin g on th e state tran sition o f th e two - pha se cl oc k t h at i s i nput t h r o ug h tb 2i n 0 a nd tb 2 i n 1 a n d ha s p h ase di f f ere n ce. a n i n t e rru p t i s o u t p ut w h en a cou n t e r o v e rfl ow o r u nde rfl ow oc cu rs i n t h e u p -a nd - d o w n c o unt er m o d e , a n d w h e n t h e c o unt i n g o p erat i o n i s execut e d. i n t e r r u p t i s out put i n t h e u p s an d d o w n s c o unt e r m ode by t h e co unt o p erat i o n. th ere are two co un ting o p e ratio n m o d e s, whic h are switched b y th e reg i ster settin g. 1) n o rm al ope rat i o n m ode ( u p/ d o w n at t h e f o u r t h co u n t ) 2) q u a d r upl e m ode (u p/ d o w n at eac h c o unt ) 0 2 2 3 3 1 1 0 0 1 1 3 3 2 2 0 tb2cr t b 2 c r < ud 2 c nt > up upint down downn t set 1 0 set clr clr 2 0 0 1 0 2 0 1 0 2 up down + - se t ( lead cl ear ) internal bus uc 0 digit a l n o i se f ilte r (-delete 8 clocks) tmp19a43 ? n o rm al ope r a t i on c o u n t m ode 0 0 2 1 3 1 0 0 1 1 1 1 0 0 1 up 0 1 3 2 0 1 1 0 0 1 1 0 0 1 1 down tb2in0 tb2in1 p i n s t a t e c o un t c o nd itio n u p d o w n tb2in0, tb2in1 0 2 0 1 s et t b 2in0, t b 2in 1 1 0 2 0 interrup t g e n e rated t b 2in0, t b 2in 1 1 0 2 0 clr note: chan ges fro m 0 to 3 and from 3 to 0 a r e conside r e d as irregula r st ate s and are not c oun ted. up and do w n st ate s e ttin gs are clear e d . ? mu ltip licatio n - b y -4 o p e ratio n coun t m o d e up down d coun t do w n at ea ch e dge 1 1 0 0 1 1 0 1 2 3 0 1 1 0 0 0 0 1 3 2 1 0 1 1 0 0 1 1 1 0 tb2in0 tb2in1 c coun t up at eac h edge p i n s t a t e c o un t c o nd itio n u p d o w n 0 2 0 1 2 3 1 3 3 1 3 2 tb2in0, tb2in1 1 0 2 0 tmp19a43 (rev2.0) 11 - 2 6 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 tmrb 2r un regist er ( t b2ru n) 7 6 5 4 3 2 1 0 bit symbol tb2rde u d 2 c k tb2udce i 2 t b 2 tb2prun tb2run r e a d / w r i t e r / w r / w r / w r / w r / w r / w r r / w after reset 0 0 0 0 0 0 0 0 f u n c t i o n d o u b l e buffering 0: disable 1: enable write "0." select sampling clock 0: fs 1: t 0/4 enable/ disable tw o - phase counter 0: disable 1: enable idle 0: stop 1: ope r ate timer run/sto p control 0: stop & clear 1: run (count u p ) tb2run (0xff ff_ f160) fig. 1 1 -16 t w o-ph ase pulse input cou n t mode setting regi ster for t h e sam p l i ng cl oc k, t h e fi ft h bi t of t h e tb 2 r un re gi st er i s set t o " 1 ." << reco v e ry fr o m the sleep mode >> 1) for t m rb 2 a nd t m rb 3 th e t w o- ph ase cou n t er co un ts up o r do wn d e p e nd ing on th e sleep r e lease in pu t state. 2) reco ver y b y u s i n g i n t 0 t h r o u g h i n t 3 f o r t m rb 6 an d t m rb 7 th e cou n t er v a lu e do es no t ch ang e un til th e req u i rem e n t s are satisfied. t o read t h e cou n t er v a lu e aft e r th e sleep m o d e is released, it m u st b e ex ecu t ed wh en an in terrup t is g e n e rated d u e to co un ting u p or do w n . c op eration m o de reg i ster setting d e term in es wh et h e r th e extern al i n pu t si gn als fro m th e tb2 i n0 an d tb2 i n1 inpu t p i n s are inpu t to t h e no rm al 1 6 - b it ti m e r (cap ture in pu t) o r th e up -and -d own cou n t er . in t h e up -an d - do w n c o u n t e r m ode, capt u re i s execut e d by t h e s o ft wa re onl y . c a pt u r e at t h e ext e r n al cl oc k t i m i ng doe s no t wo r k . ? ? ? in t h e up -a nd -d ow n c o unt e r m ode, t h e c o m p arat or i s di sabl e d a n d i t does n o t e x ecut e co m p ariso n wi th ti m e r reg i sters. the i n put cl oc k sam p l i ng i s execut e d by fs ( 3 2 k h z/ 1 6 k hz) or t h e hi g h -s pee d cl oc k (sy s t e m cl ock ) . th e m a xi m u m i nput fre que ncy i s 4 khz f o r fs an d t0/ 4 for t h e h i gh -spee d cl oc k. << rec over y fr om the st op mode >> r ecov e ry by us in g in t0 th r o ug h in t3 for tmr b 6 a nd tmr b 7 th e t w o-p h a se coun ter en ters th e st op m o d e wh ile it m a intains t h e previous state. t h e r efore , whe n the relations hip be tween t h e i n put state use d for releasin g t h e st op m o d e and th e m a in tain ed state satisfi es th e r e q u i r e m e n t s f o r coun ting u p or d o wn , t h e co un te r val u e is inc r em ented or decrem e n ted by one (+ 1 o r -1) after th e st op m o d e is released . if it is n ecessa ry to keep a c o nstant state after the st op m ode is released, t h e t w o-phase c o unter m u st b e in i tialized to "0x7 fff" after the st op m o d e is released (b y settin g tb 7 r un to "0 " and turn ing it b a ck to "1 "). this functio n is unava ila ble fo r t m rb 2 and t m rb 3. << how to pr ogr am the up -and -d own c o u n ter >> set t h e tb 2m od re gi st er < t b 2 c l k 0 , tb 2c lk 1> t o "0 0" ( p rescal er o ff). t h en , pr og ram t h e fo ur t h b it o f th e tb 2run reg i ster t o d e term in e whethe r t o operate the counter as the up-a nd- do w n c o u n t e r or as t h e co n v e n t i onal u p -c o u n t e r fo r e x t e r n al cl ock i n put . tb 2u dc e (e nabl e t h e up -a nd - d o w n c o u n t e r) = "0 ": no rm al 1 6 -b it ti m e r o p eratio n = " 1 ": u p -a n d - d o w n c o u n t e r ope rat i o n tmp19a43 (rev2.0) 11 - 2 7 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 d int e r r upt ? i n th e no rma l or slow m o d e th e inttb2 i n terrup t is en ab led u s ing th e in terr u p t con t ro ller (intc). th e inttb2 i n terrup t is gene rat e d by c o u n t i n g u p or do w n . r e a d i n g t h e st at u s re gi st er tb 2s t du ri n g i n t e r r u p t ha ndl i n g allows sim u ltaneous c h ec k for occurre n ces o f an ov erf l ow an d an un d e rf lo w . i f tb2st< intt bouf 2> is "1," it i ndicates that an overflow has o c cu rr ed . if < i n t t b u d f 2 > is "1," it indicates that a n unde rflow has occ u rred. t h is register is cleared a f ter it is read. t h e co un ter b e co mes 0x0 000 w h en an ov erf l ow o ccur s , and it b eco m e s 0 x ffff wh en an un d e r f l o w occurs. afte r t h at, the counte r c ont i n ues t h e cou n t i n g ope ra t i on. 7 6 5 4 3 2 1 0 bit symbol i n ttbud2 i n ttbudf2 i n t t b o u f 2 r e a d / w r i t e r r r after reset 0 0 0 0 0 function this can be read as "0." up-and- dow n count 0: n o t o c curred 1: occurre d underflow 0: n o t o c curred 1: occurre d ov erflow 0: n o t o c curred 1: occurre d this can be read as "0." tb2st (0xff ff_ f164) fig. 1 1 -17 tm rb2 s t atus registe r note: the st a t us is cleared af te r the regis t er is read. ? in the slee p m ode th e two - ph ase in pu t pu lse in pu t coun ter o p e rates. th e inttb 2 in terru p t is g e n e rated b y th e count-up or count -down input, and t h e system recove rs from the s leep m ode. reading the status regi st er tb 2s t du ri n g i n t e rr upt han d l i n g al l o ws si m u lt aneo us c h eck fo r occ u r r e n ces of a n ove rfl ow an d an u n d er fl o w . if tb 2st< i n ttb o u f 2 > is "1 ," it ind i cates th at an ov erflow h a s occurre d. if < i nt tbudf2> is " 1 ," it i ndi cates that a n u nde rfl ow has o ccur r ed . t h i s regi st er i s cleared after it is rea d . th e co un ter b eco m e s 0 x00 00 when an o v e r f l ow o c cu r s , it an d b eco m e s 0 x ffff wh en an u n d e rflow occu rs. after t h at, th e co un ter co n tinu e s th e co un ting o p e ratio n. ? in t h e st o p m ode ( r ec over y by usi n g i n t 0 thr o u g h i n t 3 f o r t m rb 6 and t m rb 7 ) th e two - p h a se inp u t pu lse in pu t cou n t er i s stopp ed. after th e release inp u t and th e elap se o f warm -up t i m e, t h e m ode ch ange s t o t h e nor m a l m ode an d t h e co unt i n g ope rat i on rest art s . whe n t h e rel a t i ons hi p bet w een t h e i n p u t st at e used for releasing the st op m ode and the main tain ed st ate satisfies th e requ irem en ts for co un ting u p or down , t h e co un ter v a l u e is increm ented or dec r em ented by one (+ 1 or -1) afte r the st op m ode is released. tmp19a43 (rev2.0) 11 - 2 8 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 e u p - a n d - dow n co un ter wh en the two-ph ase inpu t co un t m o d e is selected (tb 2 run = "1 ") , t h e up- coun ter b eco m e s th e up -and -d own co un ter and it i s in itialized to 0 x 7 f ff . if a co un ter o v e rflo w o ccurs, t h e cou n ter retu rns to 0 x 0 0 0 0 . if a cou n ter un de rflo w occu rs, t h e co u n ter ret u rns t o 0 x ff ff . a f ter th at, the co un ter con tinu e s th e co un ti n g op eration . th erefo r e, t h e state can be c h ecked by rea d i ng t h e counte r val u e a n d t h e s t at us fl ag tb 2 s t aft e r a n i n t e rr upt i s ge ner a t e d. up-count input u p -a nd- dow n c o u n te r v a lue 0x3f ff 0x4000 0x4001 sampling clock up-and -do w n int e rrupt (no t e 1 ) the up (do w n) coun t inp u t must be s e t to the "h" le v e l for the st ates be for e and af ter a n inpu t. (no t e 2 ) readin g of c ounte r v a lue must be exe cute d during inttb2 inte rrupt ha ndling tmrb2 con t rol register tb2cr (0xff ff_ f162) 7 6 5 4 3 2 1 0 bit s y m b o l t b 2 e n tb2s y c u d 2 n f ud2cn t r e a d / w r i t e r / w r / w r r r / w r / w r / w r a f t e r r e s e t 0 0 0 0 0 0 0 0 function tmrb2 operation 0: disable 1: enable write "0." this can be read as "0. " this can be read as "0. " sy nchroniza tion mode sw itch- ov er 0: indiv i dual o pera t ion 1: sy nchron ous o pera t ion digital noise filter 0: no use 1: use mode sw itch- ov er 0: normal 1: quadruple this can be read as "0. " ? m ode swi t c h- o v er bi t 0: n o rm al m ode 1: q u a d r u pl e m ode ud 2 n f c ont r o l s n o i s e rem oval . if th is is set to "1 (use)," th e tmrb2 , tm rb3 , tmrb6 an d tmrb7 pin inpu ts are re m o v e d wh en they are s h orte r tha n 8 system clocks. pay cl ose at t e nt i on t o t h e i n put si gnal fre q u ency beca use an er r o r of o n e sy st em cl ock occu rs du e t o syn c hron ization with in tern al sig n a ls. tmp19a43 (rev2.0) 11 - 2 9 16-bit t i m e r/ event counte rs (tmrb s )
tmp19a43 12. 32-bit input capt ure (tmrc) tmrc con s ists of on e ch ann e l with a 32-b it ti m e b a se tim e r (tbt), f o u r c h a nnels ( t ccap 0 th r o ug h tccap3) eac h with a 32-bit input capt u re register , a n d eight c h annels (tccmp0 through tccmp7) each with a 32-bit c o m p are re gister . fi g. 1 2 - 1 s h ow s t h e tm r c bl ock di a g ram . 12.1 tmrc block diagram 4 8 1 6 32 64 128 256 512 tbtin (pc0) prescal e r out put t2 through t256 tc0in (p32 ) noise remov a l circuit overflo w interrup t (int tbt) clear & count control circuit 32-bit input captu re (tccap0 ) capture 0 interru pt (intcap0 ) noise remov a l circuit edge detection capt ure regis t e r s 0 thro ug h 3 (tcc a p 0 t h rou gh t c c a p 3 ) prescaler input clock ( t0) t16 t32 t64 t 1 28 run & clear 32-bit comp arat o r 32-bit register buf fer 0 32-bit comp are register 0 (tccmp 0 ) comp are match interrupt 0 (intc m p0) (intcap a ) t 2 56 32-bit time base ti mer (tb t ) com p are re gisters 0 thr oug h 7 (tccmp 0 thr o u gh t ccmp7) comp are match t r igge r (cmp0t rg ) comp are match output ( t co ut 0 ) t2 t4 t8 fig. 12-1 t i m e r c blo ck di agra m tmp19a43 (rev2.0) 12-1 32-bit input capture (tm r c)
tmp19a43 12.2 description for operations of e ach circuit 12.2.1 prescaler the pre s caler i s provide d t o a c qui re the tm rc source cl oc k. the prescale r input cloc k t0 is fp eriph / 2, fpe r i p h/ 4, fpe r i ph/ 8 or f p eri ph/ 16 sel ect ed by sy sc r 0 < p r c k 1: 0> i n t h e c g . t2 t h r o ug h t256 gene rat e d by di vi di ng t0 are a v ailable a s tmrc pres caler input clocks a n d ca n be selected with tbtcr. fpe r iph is either "fgear" which is a cloc k s e lected b y syscr1 in th e cg, or "fc" wh ich is a cl ock be fo re i t i s di vi ded by t h e cl oc k gea r . th e op er ation o r stopp ag e o f th e prescaler is set with tbt r un whe r e wr iting " 1 " sta r ts co un ting an d writing "0 " cl ears and st o p s co un ting . t a b l e 12 -1 shows th e prescaler ou tpu t clock reso l u tio ns. tmp19a43 (rev2.0) 12-2 32-bit input capture (tm r c)
tmp19a43 t able 12-1 prescale r outp ut clock resolution s @fc = 40 .0m h z select pe riphe ra l clo ck clo ck g ear va l u e select p r es cal er clock pres cale r o u t p u t clo ck reso lu tion t2 t4 t8 t1 6 0 ( f g e a r ) 0 0 0 ( f c ) 00(fperiph/16) fc/2 6 (1.60 s ) f c /2 7 (3.20 s ) f c /2 8 (6.40 s ) f c /2 9 (12.8 s) 0 1 ( f p e r i p h / 8 ) fc/2 5 (0.80 s ) f c /2 6 (1.60 s ) f c /2 7 (3.20 s ) f c /2 8 (6.40 s) 1 0 ( f p e r i p h / 4 ) fc/2 4 (0.40 s ) f c /2 5 (0.80 s ) f c /2 6 (1.60 s ) f c /2 7 (3.20 s) 11(fperiph/2) fc/2 3 (0.20 s ) f c /2 4 (0.40 s ) f c /2 5 (0.80 s ) f c /2 6 (1.60 s) 1 0 0 ( f c / 2 ) 00(fperiph/16) fc/2 7 (3.20 s ) f c /2 8 (6.40 s ) f c /2 9 (12.8 s ) f c /2 10 (25.3 s) 0 1 ( f p e r i p h / 8 ) fc/2 6 (1.60s) fc/2 7 (3.20 s ) f c /2 8 (6.40 s ) f c /2 9 (12.6 s) 1 0 ( f p e r i p h / 4 ) fc/2 5 (0.80 s ) f c /2 6 (1.60 s ) f c /2 7 (3.20 s ) f c /2 8 (6.32 s) 11(fperiph/2) fc/2 4 (0.40 s ) f c /2 5 (0.80 s ) f c /2 6 (1.60 s ) f c /2 7 (3.20 s) 1 1 0 ( f c / 4 ) 00(fperiph/16) fc/2 8 (6.40 s ) f c /2 9 (12.8 s ) f c /2 10 (25.6 s ) f c /2 11 (51.2 s) 0 1 ( f p e r i p h / 8 ) fc/2 7 (3.20 s ) f c /2 8 (6.40 s ) f c /2 9 (12.8 s ) f c /2 10 (25.6 s) 1 0 ( f p e r i p h / 4 ) fc/2 6 (1.60 s ) f c /2 7 (3.20 s ) f c /2 8 (6.40 s ) f c /2 9 (12.8 s) 11(fperiph/2) fc/2 5 (0.80 s ) f c /2 6 (1.60 s ) f c /2 7 (3.20 s ) f c /2 8 (6.40 s) 1 1 1 ( f c / 8 ) 00(fperiph/16) fc/2 9 (12.8 s ) f c /2 10 (25.6 s ) f c /2 11 (51.2 s ) f c /2 12 (102.4 s) 0 1 ( f p e r i p h / 8 ) fc/2 8 (6.40 s ) f c /2 9 (12.8 s ) f c /2 10 (25.6 s ) f c /2 11 (51.2 s) 10(fperiph/4) fc/2 7 (3.20 s ) f c /2 8 (6.40 s ) f c /2 9 (12.8 s ) f c /2 10 (25.6 s) 11(fperiph/2) fc/2 6 (1.60 s ) f c /2 7 (3.20 s ) f c /2 8 (6.40 s ) f c /2 9 (12.8 s) 1 ( f c ) 0 0 0 ( f c ) 00(fperiph/16) fc/2 6 (1.60 s ) f c /2 7 (3.20 s ) f c /2 8 (6.40 s ) f c /2 9 (12.8 s) 0 1 ( f p e r i p h / 8 ) fc/2 5 (0.80 s ) f c /2 6 (1.60 s ) f c /2 7 (3.20 s ) f c /2 8 (6.40 s) 1 0 ( f p e r i p h / 4 ) fc/2 4 (0.40 s ) f c /2 5 (0.80 s ) f c /2 6 (1.60 s ) f c /2 7 (3.20 s) 11(fperiph/2) fc/2 3 (0.20 s ) f c /2 4 (0.40 s ) f c /2 5 (0.80 s ) f c /2 6 (1.60 s) 1 0 0 ( f c / 2 ) 00(fperiph/16) fc/2 6 (1.60 s ) f c /2 7 (3.20 s ) f c /2 8 (6.40 s ) f c /2 9 (12.8 s) 0 1 ( f p e r i p h / 8 ) fc/2 5 (0.80 s ) f c /2 6 (1.60 s ) f c /2 7 (3.20 s ) f c /2 8 (6.40 s) 1 0 ( f p e r i p h / 4 ) fc/2 4 (0.40 s ) f c /2 5 (0.80 s ) f c /2 6 (1.60 s ) f c /2 7 (3.20 s) 11(fperiph/2) fc/2 3 (0.20 s ) f c /2 4 (0.40 s ) f c /2 5 (0.80 s ) f c /2 6 (1.60 s) 1 1 0 ( f c / 4 ) 00(fperiph/16) fc/2 6 (1.60 s ) f c /2 7 (3.20 s ) f c /2 8 (6.40 s ) f c /2 9 (12.8 s) 0 1 ( f p e r i p h / 8 ) fc/2 5 (0.80 s ) f c /2 6 (1.60 s ) f c /2 7 (3.20 s ) f c /2 8 (6.40 s) 1 0 ( f p e r i p h / 4 ) fc/2 4 (0.40 s ) f c /2 5 (0.80 s ) f c /2 6 (1.60 s ) f c /2 7 (3.20 s) 11(fperiph/2) fc/2 3 (0.20 s ) f c /2 4 (0.40 s ) f c /2 5 (0.80 s ) f c /2 6 (1.60 s) 1 1 1 ( f c / 8 ) 00(fperiph/16) fc/2 6 (1.60 s ) f c /2 7 (3.20 s ) f c /2 8 (6.40 s ) f c /2 9 (12.8 s) 01(fperiph/8) fc/2 5 (0.80 s ) f c /2 6 (1.60 s ) f c /2 7 (3.20 s ) f c /2 8 (6.40 s) 10(fperiph/4) fc/2 4 (0.40 s ) f c /2 5 (0.80 s ) f c /2 6 (1.60 s ) f c /2 7 (3.20 s) 11(fperiph/2) fc/2 3 (0.20 s ) f c /2 4 (0.40 s ) f c /2 5 (0.80 s ) f c /2 6 (1.60 s) tmp19a43 (rev2.0) 12-3 32-bit input capture (tm r c)
tmp19a43 @fc = 40mhz select pe riphe ra l clo ck clo ck g ear va l u e select p r es cal er clock pres cale r o u t p u t clo ck reso lu tion t3 2 t6 4 t 1 28 t 2 56 0 ( f g e a r ) 0 0 0 ( f c ) 00(fperiph/16) fc/2 10 (25.6 s ) f c /2 11 (51.2 s ) f c /2 12 (102.4 s ) f c /2 13 (204.8 s) 0 1 ( f p e r i p h / 8 ) fc/2 9 (12.8 s ) f c /2 10 (25.6 s ) f c /2 11 (51.2 s ) f c /2 12 (102.4 s) 1 0 ( f p e r i p h / 4 ) fc/2 8 (6.40 s ) f c /2 9 (12.8 s ) f c /2 10 (25.6 s ) f c /2 11 (51.2 s) 11(fperiph/2) fc/2 7 (3.20 s ) f c /2 8 (6.40 s ) f c /2 9 (12.8 s ) f c /2 10 (25.6 s) 1 0 0 ( f c / 2 ) 00(fperiph/16) fc/2 11 (51.2 s ) f c /2 12 (102.4 s ) f c /2 13 (204.8 s ) f c /2 14 (409.6 s) 0 1 ( f p e r i p h / 8 ) fc/2 10 (25.6 s ) f c /2 11 (51.2 s ) f c /2 12 (102.4 s ) f c /2 13 (204.8 s) 1 0 ( f p e r i p h / 4 ) fc/2 9 (12.8 s ) f c /2 10 (25.6 s ) f c /2 11 (51.2 s ) f c /2 12 (102.4 s) 11(fperiph/2) fc/2 8 (6.40 s ) f c /2 9 (12.8 s ) f c /2 10 (25.6 s ) f c /2 11 (51.2 s) 1 1 0 ( f c / 4 ) 00(fperiph/16) fc/2 12 (102.4 s ) f c /2 13 (204.8 s ) f c /2 14 (409.6 s ) f c /2 15 (819.2 s) 0 1 ( f p e r i p h / 8 ) fc/2 11 (51.2 s ) f c /2 12 (102.4 s ) f c /2 13 (204.8 s ) f c /2 14 (409.6 s) 1 0 ( f p e r i p h / 4 ) fc/2 10 (25.6 s ) f c /2 11 (51.2 s ) f c /2 12 (102.4 s ) f c /2 13 (204.8 s) 11(fperiph/2) fc/2 9 (12.8 s ) f c /2 10 (25.6 s ) f c /2 11 (51.2 s ) f c /2 12 (102.4 s) 1 1 1 ( f c / 8 ) 00(fperiph/16) fc/2 13 (204.8 s ) f c /2 14 (409.6 s ) f c /2 15 (819.2 s ) f c /2 16 (1638.4 s) 0 1 ( f p e r i p h / 8 ) fc/2 12 (102.4 s ) f c /2 13 (204.8 s ) f c /2 14 (409.6 s ) f c /2 15 (819.2 s) 10(fperiph/4) fc/2 11 (51.2 s ) f c /2 12 (102.4 s ) f c /2 13 (204.8 s) fc/2 14 (409.6s) 11(fperiph/2) fc/2 10 (25.6 s ) f c /2 11 (51.2 s ) f c /2 12 (102.4 s ) f c /2 13 (204.8 s) 1 ( f c ) 0 0 0 ( f c ) 00(fperiph/16) fc/2 10 (25.6 s ) f c /2 11 (51.2 s ) f c /2 12 (102.4 s ) f c /2 13 (204.8 s) 0 1 ( f p e r i p h / 8 ) fc/2 9 (12.8 s ) f c /2 10 (25.6 s ) f c /2 11 (51.2 s ) f c /2 12 (102.4 s) 1 0 ( f p e r i p h / 4 ) fc/2 8 (6.40 s ) f c /2 9 (12.8 s ) f c /2 10 (25.6 s ) f c /2 11 (51.2 s) 11(fperiph/2) fc/2 7 (3.20 s ) f c /2 8 (6.40 s ) f c /2 9 (12.8 s ) f c /2 10 (25.6 s) 1 0 0 ( f c / 2 ) 00(fperiph/16) fc/2 10 (25.6 s ) f c /2 11 (51.2 s ) f c /2 12 (102.4 s ) f c /2 13 (204.8 s) 0 1 ( f p e r i p h / 8 ) fc/2 9 (12.8 s ) f c /2 10 (25.6 s ) f c /2 11 (51.2 s ) f c /2 12 (102.4 s) 1 0 ( f p e r i p h / 4 ) fc/2 8 (6.40 s ) f c /2 9 (12.8 s ) f c /2 10 (25.6 s ) f c /2 11 (51.2 s) 11(fperiph/2) fc/2 7 (3.20 s ) f c /2 8 (6.40 s ) f c /2 9 (12.8 s ) f c /2 10 (25.6 s) 1 1 0 ( f c / 4 ) 00(fperiph/16) fc/2 10 (25.6 s ) f c /2 11 (51.2 s ) f c /2 12 (102.4 s ) f c /2 13 (204.8 s) 0 1 ( f p e r i p h / 8 ) fc/2 9 (12.8 s ) f c /2 10 (25.6 s ) f c /2 11 (51.2 s ) f c /2 12 (102.4 s) 1 0 ( f p e r i p h / 4 ) fc/2 8 (6.40 s ) f c /2 9 (12.8 s ) f c /2 10 (25.6 s ) f c /2 11 (51.2 s) 11(fperiph/2) fc/2 7 (3.20 s ) f c /2 8 (6.40 s ) f c /2 9 (12.8 s ) f c /2 10 (25.6 s) 1 1 1 ( f c / 8 ) 00(fperiph/16) fc/2 10 (25.6 s ) f c /2 11 (51.2 s ) f c /2 8 (6.40 s ) f c /2 9 (12.8 s) 01(fperiph/8) fc/2 9 (12.8 s ) f c /2 10 (25.6 s ) f c /2 7 (3.20 s ) f c /2 8 (6.40 s) 10(fperiph/4) fc/2 8 (6.40 s ) f c /2 9 (12.8 s ) f c /2 6 (1.60 s ) f c /2 7 (3.20 s) 11(fperiph/2) fc/2 7 (3.20 s ) f c /2 8 (6.40 s ) f c /2 5 (0.80 s ) f c /2 6 (1.60 s) (no t e 1 ) do not c h an ge the cloc k gear w h ile th e timer is operating. (no t e 2 ) "-" deno tes "setting pro hibited." tmp19a43 (rev2.0) 12-4 32-bit input capture (tm r c)
tmp19a43 12.2.2 noise rem o val circuit the noi se rem oval ci r c ui t re m oves noi ses f r om an ext e rn al cl ock s o urc e i n p u t ( t b t i n ) a n d a ca pt u r e t r i gge r i n p u t ( t cni n ) o f t h e t i m e base t i m e r (tb t ). it ca n al so o u t p ut i n p u t si g n al s w i t hout rem ovi n g noi ses f r om t h em . 12.2.3 32-bit t i me base t i mer (tbt) thi s i s a 3 2 - bi t bi na ry c o unt er t h at c o u n t s up up o n t h e ri si ng of an i n p u t cl o c k s p eci f i ed by t h e tb t co n t ro l reg i ster tbtcr of th e ti m e b a se ti m e r . based on th e tbtcr settin g, an i n pu t clo c k is selected fro m ex tern al clo c k s sup p lie d t h r o u g h t h e t b tin pi n a n d ei ght p r escal er out put cl ocks t2, t4, t8, t16, t32, t64, t128 , and t256. "c ou nt ," "st o p " or "cl ear" o f t h e up -c ou nt er can be selected with tbtrun. whe n a res e t i s perform e d, the up-c ounter is in a cleared state and th e timer is in an idle state. as cou n ting starts, th e up -c ou nt er ope rat e s i n a free - ru n n i n g c o ndi t i on. as i t reac hes an o v er fl o w st at e, t h e o v e rfl o w i n t e r r u p t int t b t i s ge nerat e d; su bse que nt l y , t h e c o unt val u e i s cl eared t o 0 a nd t h e u p -c o unt e r rest art s a c o u n t - u p op er atio n. th is coun ter can p e rfo r m a read cap t u re operatio n. wh en it is p e rform in g a read cap t u re o p e ration , it is pos sible to rea d a c o unter val u e by accessing the tbt rea d capture re giste r (tbtr d cap) in units of 32 b its. howe ver , a c o unte r value ca nnot be rea d (c a p tured) if the register is acce s s ed i n units of 8 or 16 bits. 12.2.4 edge detection circuit by p e rfo r m i n g sam p lin g , th is circu it d e tects th e inpu t edg e of an ex tern al cap ture i n pu t (t cn in). it can b e set to "rising edg e ," "falling edg e ," "bo t h ed g e s" o r "no t cap ture" b y p r o v i si o n i n g th e cap ture con t ro l regi st er c a p n c r < c p neg 1 : 0 >. fi g. 1 3 . 2 sh ows capt u re i n put s , o u t put s (ca p t u re fact or o u t p ut s) p r od u c ed b y the edg e d e tection circu it, an d sp ecific d e tectio n circu it setting s . t c nin input captur e factor (risin g ed ge s e tting) (fallin g ed ge s e tting) (both-ed ge set t ing) (not capture s e tting) fig. 12-2 cap t ure input s an d captu r e fa ctor o u tput s (o utput s prod uce d by the edge detectio n circuit) tmp19a43 (rev2.0) 12-5 32-bit input capture (tm r c)
tmp19a43 12.2.5 32-bit capture register thi s i s a 3 2 - b i t re gi st er fo r c a pt u r i n g c o unt val u es o f t h e t i m e base t i m er by usi n g cap t u re fact o r s as t r i gge rs. if a ca pt u r e o p erat i o n i s pe rf orm e d, t h e ca pt u r e i n t e rr upt i n tc a p n i s ge nerat e d . f o ur i n t e rr upt req u est s i n tc ap 0 t h ro u gh i n tc a p 3 a r e gr o upe d i n t o o n e set o f i n t e r r u p t re que st s whi c h are t h e n n o tified to th e in terru p t con t ro ller . wh ich on e of in terru p t requ ests intcap0 th rou gh intc ap3 m u st be p r ocesse d can be i d ent i f i e d by rea d i n g t h e st at us r e gi st er tc g 0 st d u ri ng i n t e rr upt pr ocessi ng . add itio n a lly , i t is po ssib l e t o m a sk unn ecessary in terrup t s b y settin g th e in terru p t m a sk reg i ster tcg0im to an approp riate b it settin g . wh ile a read o f th e cap ture reg i ster is ong o i n g , coun t v a lues cannot be ca pt ure d e v e n if t h ere are trigge rs . data is read in th e ord e r o f lower to hi ghe r bits by usi n g a w o r d t r a n s f er i n st r u ct i o n. if a hal f - w o r d tran sfer in stru ctio n is u s ed, d a ta is read twice. if a b y te d a ta tran sfer in stru ctio n is u s ed, d a ta is read fou r ti m e s. 12.2.6 32-bit comp are register th is is a 3 2 -b it reg i ster fo r sp ecifying a com p are v a lu e. tmrc h a s eig h t b u ilt-in com p are reg i sters, t c c m p 0 th ro u g h t c c m p 7 . if v a lu e s s e t in th e s e c o m p are registe r s m a tch the value of t h e tim e base tim e r tbt , t h e m a tch detection signal of a com p arat or be com e s act i v e. "c om pare ena b l e " or "com pare disable" ca n be specifie d with the com p are c o ntrol re gister c m pctl. t o set tc c m pn t o a speci f i c val u e , dat a m u st be t r a n sf erre d t o tc c m pn i n t h e o r der of lo wer to higher bits by u s in g a wo rd transfer in st ru ction . if a hal f-word tran sfer in stru ction is u s ed, d a ta i s trans f erred twi ce to tccmpn. if a byte d a ta tran sfer in stru ctio n is u s ed, d a ta is tran sferred fo ur tim es to tccmpn . each com p are register has a double-b uf fer st ruct ure, t h at is, tccmpn fo rm s a pair with a re gister buf fe r "n." " e na bl e" or "di s a b l e " of t h e d o u b l e bu f f ers i s c ont r o l l e d by t h e com p are co nt r o l re gi st er c m pc t l . if is set t o " 0 , " t h e d o ubl e b u f f ers are di sa bl ed. i f i s set t o "1," t h ey are e n able d. if the double buf f e r s a r e enabled, d a ta tran sfer fro m th e reg i ster bu f f e r "n" t o the c o m p are re gister tccmpn take s place when the value of tb t m a tches that of tccmpn. because tcc m pn is i ndete rminate whe n a reset is pe rformed, it is nece ssary to prepa r e and write data in adv a n ce. a reset in itializes cmpctl to "0 " an d d i sab l es th e do ub le b u f f ers. t o u s e t h e d oub le bu f f ers, data m u st b e written to th e co m p are reg i ster , m u st b e set to "1 ," and t h en th e fo llowing data m u st b e wri tten to the reg i ster buf fer . tccmpn an d th e r e g i ster buf f e r ar e assigned to th e sam e address . if < c mprden> is "0," the same v a lu e is written t o tccmpn and each reg i ster b u f f er . if is "1," d a ta is written to each reg i ster bu f f er o n l y . th erefo r e, to write an in itial v a lu e to t h e co m p are reg i ster , it is n e cessary to set the d oub le buf fers to "d isab le." tmp19a43 (rev2.0) 12-6 32-bit input capture (tm r c)
tmp19a43 12.3 register description t m rc cont r o l re g i s t er 7 6 5 4 3 2 1 0 b i t sy m b o l tc e n i 2 tb t r ead/ w r it e r / w r af te r r e s e t 0 0 0 f unc t i on t m rc o per ati on 0: d i s a b l e 1 : e n abl e id le 0: s t op 1: r un ? 0 ? is r ead . t ccr (0 x fff f_ f4 0 0 ) : c ont r o l s t h e o p erat i o n i n i d le m ode : specifies e n abl i ng/disa bling of t h e tmrc opera tion . if set to "d isab le," a clo c k is no t sup p lied to ot he r regi st er s o f t h e tm r c m odul e a n d, t h e r ef ore , a re d u ct i o n i n po we r c o nsum pt i o n i s pos si bl e (a rea d o f o r a wri t e t o ot her regi st ers c a n n o t be execut e d) . t o use tm r c , t h e tm r c o p e ration m u st b e set to "en a b l e" ("1 " ) before m a k i n g in d i v i d u a l reg i ster settin gs of tmrc m odules. if t m rc is ope rat e d a n d the n set to " d is able," indi vidual re gis t er settings are retained. tb tr u n r e g i s t e r 7 6 5 4 3 2 1 0 bi t s y m b o l tb t c a p tbtpr u n t b trun re ad / w r i t e r r/ w afte r r e s e t 0 0 0 0 0 fu ncti o n "0" i s r e ad . e n s u r e th i s i s set to "0." tb t cou n te r so ftw a r e c a pt u r e 0: don ? t ca r e 1: s o ftw a r e c a ptu r e ti m e r r un /s to p con t r o l 0: s t op & c l ea r 1: cou n t tb t r u n ( 0 x fff f_ f4 01 ) : c ont r o l s t h e t b t co unt o p er at i on : controls t h e t b t prescaler operation : if th is is set to "1 ," th e cou n t v a lu e o f t h e time b a se ti m e r (tbt) is tak e n in to th e cap t ure reg i ster tbtcap n. fig. 12-3 tmrc-r e lated r egisters tmp19a43 (rev2.0) 12-7 32-bit input capture (tm r c)
tmp19a43 t b t co n t r o l re gis t er 7 6 5 4 3 2 1 0 b i t sy m b o l tbt n f t b tc l k 3 t btc l k2 tbtc l k 1 tbt c l k 0 re ad/w r i t e r/w a f t e r re s e t 0 0 0 0 0 0 0 0 funct i on tb ti n i n pu t no i s e re m o v a l 0 : 2/ fs y s or mo r e 1 : 6/ fs y s or mo r e e n s u re t h is is s e t t o " 0 ." tb t so ur ce clock 0 000: t 2 000 1 : t4 00 1 0 : t8 0 011: t 1 6 010 0: t32 01 0 1 : t6 4 0 110: t 1 28 011 1: t256 1 111: t b ti n p i n inp u t tbtc r (0 x f f f f _ f402) : thi s i s an i n pu t cl ock f o r tb t . c l ocks f r o m "0 00 0" t o " 0 1 1 1 " a r e a v ai l a b l e as prescal er out put c l o c k s . a c l o c k " 1111 " i s i nput th ro ugh th e tbti n p i n . : c ont r o l s t h e n o i s e rem oval f o r t h e tb t i n pi n i n p u t . if t h is is set t o "0 " (rem o v a l disab l ed ), an y inp u t of m o re th an 2 / fsys (50ns@fpe r iph=fc=40mhz ) i s accepte d as a sour ce cloc k for tbt , at whi c heve r le vel the tb tin pi n i s , "h" or " l ." if t h is is set t o "1 " (rem o v a l en ab led ) , an y inp u t of less t h an 6 / fsys (1 5 0ns @f pe ri p h =fc= 4 0 m h z ) i s rega r d ed as noi se an d rem oved , at whi c he ver l e vel t h e t b tin pi n i s , "h" o r " l ." t h e ran g e of rem oval ch a nge s depe n d i n g on t h e sel ect ed cl oc k gea r a n d a syste m clock used. t b t captu r e re gis t er ( t bt cap) 7 6 5 4 3 2 1 0 bi t s y m bol ca p 07 ca p 06 ca p 05 ca p 04 ca p 03 ca p 02 ca p 01 ca p 0 0 read/ w r i t e r afte r r e se t f unc t i on capt ure dat a 7 6 5 4 3 2 1 0 bi t s y m bol ca p 15 ca p 14 ca p 13 ca p 12 ca p 11 ca p 10 ca p 09 ca p 0 8 read/ w r i t e r afte r r e se t f unc t i on capt ure dat a 7 6 5 4 3 2 1 0 bi t s y m bol ca p 23 ca p 22 ca p 21 ca p 20 ca p 19 ca p 18 ca p 17 ca p 1 6 read/ w r i t e r afte r r e se t f unc t i on capt ure dat a 7 6 5 4 3 2 1 0 bi t s y m bol ca p 31 ca p 30 ca p 29 ca p 28 ca p 27 ca p 26 ca p 25 ca p 2 4 read/ w r i t e r afte r r e se t f unc t i on capt ure dat a tbtc a p 0 (0 x ffff_f404) tbtc a p 1 (0 x ffff_f405) tbtc a p 2 (0 x ffff_f406) tbtc a p 3 (0 x ffff_f407) fig. 12-4 tmrc-r e lated r egisters tmp19a43 ( r e v2.0) 12-8 32-bit input capture (tm r c)
tmp19a43 t b t re ad ca pt u r e r e g i st er (t b t rd ca p ) 7 6 5 4 3 2 1 0 bi t s y m bol r d c a p 0 7 r d c a p 0 6 rdc a p 0 5 rdc a p 04 rdc a p 03 rd ca p02 rd ca p01 rd ca p00 re ad/ w r i t e r a f ter re s e t funct i on c apture d a t a 7 6 5 4 3 2 1 0 bi t s y m bol r d c a p 1 5 r d c a p 1 4 rdc a p 1 3 rdc a p 12 rdc a p 11 rd ca p10 rd ca p09 rd ca p08 re ad/ w r i t e r a f t e r r e s e t funct i on c apture d a t a 7 6 5 4 3 2 1 0 bi t s y m bol r d c a p 2 3 r d c a p 2 2 rdc a p 2 1 rdc a p 20 rdc a p 19 rd ca p18 rd ca p17 rd ca p16 re ad/ w r i t e r a f ter re s e t funct i on c apture d a t a 7 6 5 4 3 2 1 0 bi t s y m bol r d c a p 3 1 r d c a p 3 0 rdc a p 2 9 rdc a p 28 rdc a p 27 rd ca p26 rd ca p25 rd ca p24 re ad/ w r i t e r a f t e r r e s e t funct i on c apture d a t a tb t r dca p l l ( 0 x f f ff_ f4 0 8 ) tb t r dc ap l h ( 0 x f f f f _f 40 9) tbtr d c a p h l ( 0 x fff f_ f 4 0 a ) tbtr d c a p h h ( 0 x fff f_ f 4 0 b ) fig. 12-5 tmrc-r e lated r egisters tmp19a43 ( r e v2.0) 12-9 32-bit input capture (tm r c)
tmp19a43 t m rc ca ptu r e 0 c o nt r o l r e gis t er 7 6 5 4 3 2 1 0 bi t s y m bol t c 0nf c p 0e g1 cp 0e g 0 re ad/w r i t e r / w r r / w a f t e r r e s e t 0 0 0 0 f unc t i on tc 0 i n i n pu t no i s e re m o va l 0:2/ f s y s or mo r e 1:6/ f s y s or mo r e "0 " i s r e a d . s e le c t e f f e ctiv e e d g e o f t c 0 i n i n p u t 00 n o t c apt u r e 01 r i si ng e d ge 10 fa lli ng e d g e 11 b o th ed ge s cap 0 c r ( 0 x f f f f _f 4 10) : sel ect s t h e ef f ect i v e edge o f an i n put t o t h e t r i gge r i n put pi n tc 0i n o f t h e capt u re 0 r e gi st er (tccap0). if th is is set t o "0 0," the ca pture operation is disa bled. : c ont r o l s t h e n o i s e rem oval f o r t h e tc 0i n p i n i n put . if t h is is set t o "0 " (rem o v a l disab l ed ), an y inp u t of m o re th an 2 / fsys (50ns@fpe r iph=fc=40mhz ) i s accepte d as a trigge r i n put for tccap0, at whiche ver level the tc 0i n pi n i s , "h" or " l ." if t h is is set t o "1 " (rem o v a l en ab led ) , an y inp u t of less t h an 6 / fsys (1 5 0ns @f pe ri p h =fc= 4 0 m h z ) i s rega r d ed as noi se an d rem oved , at whi c he ver l e vel t h e t c 0i n pi n i s , "h" o r " l ." t h e ran g e of rem oval ch a nge s depe n d i n g on t h e sel ect ed cl oc k gea r a n d a syste m clock used. fig. 12-6 tmrc-r e lated r egisters tmp19a43 ( r e v2.0) 12-10 32-bit input capture (tm r c)
tmp19a43 t m rc captur e 0 re gis t er ( t ccap0) 7 6 5 4 3 2 1 bi t s y m bol ca p 007 ca p 006 ca p 005 ca p 004 ca p 003 ca p 002 ca p 001 ca p 000 read/ w r i t e r afte r r e se t f unc t i on capt ure 0 dat a 7 6 5 4 3 2 1 bi t s y m bol ca p 015 ca p 014 ca p 013 ca p 012 ca p 011 ca p 010 ca p 009 ca p 008 read/ w r i t e r afte r r e se t f unc t i on capt ure 0 dat a 7 6 5 4 3 2 1 bi t s y m bol ca p 023 ca p 022 ca p 021 ca p 020 ca p 019 ca p 018 ca p 017 ca p 016 read/ w r i t e r afte r r e se t f unc t i on capt ure 0 dat a 7 6 5 4 3 2 1 bi t s y m bol ca p 031 ca p 030 ca p 029 ca p 028 ca p 027 ca p 026 ca p 025 ca p 024 read/ w r i t e r afte r r e se t f unc t i on capt ure 0 dat a t cca p 0ll (0 x ffff_f414) t cca p 0lh (0 x ffff_f415) t cca p 0 hl (0 x ffff_f416) t cca p 0 hh (0 x ffff_f417) (no t e 1 ) af ter a res e t, the v a lue of tccap0 is u ndefine d. (no t e 2 ) dat a is no t c a ptur ed duri ng a read of the ca ptur e r e giste r . t m r c g 0 i n t e rrupt m a s k r egi s t er 7 6 5 4 3 2 1 0 bi t s y m bol tci m 3 tci m 2 tci m 1 tci m 0 read/ w r i t e r r/ w a fter r e s e t 0 0 0 0 0 f unc ti on "0" i s r ead. ma s k 1 : i n tcap3 ma s k 1 : i n tcap2 ma s k 1 : i n tcap1 ma s k 1 : i n tcap0 tcg0 i m ( 0 x ffff_ f4 0 c ) t m r c g 0 s t at us r e g i s t er 7 6 5 4 3 2 1 0 bi t s y m bol in t c ap 3 in t c ap 2 in t c ap 1 in t c ap 0 rea d / w r i t e r a f ter r e s e t 0 0 0 0 0 f unc ti on "0" i s r ead. 0: in terr upt not gene r a ted 1: in terr upt gene r a ted 0: in terr upt not gene r a ted 1: in terr upt gene r a ted 0: in terr upt not gene r a ted 1: in terr upt gene r a ted 0: in te r r upt not gen er ated 1: in te r r upt gen er ated tcg 0 s t ( 0 x f fff_ f40 d ) (no t e 1 ) if tcg0st is read, bit s 0, 1, 2 and 3 ar e cleared. fig. 12-7 tmrc-r e lated r egisters tmp19a43 ( r e v2.0) 12-1 1 32-bit input capture (tm r c)
tmp19a43 t m rc capt ur e 1 co ntro l r egi s t er 7 6 5 4 3 2 1 0 bi t s y m b ol t c 1 n f c p 1e g 1 c p 1e g 0 r ead /w ri te r / w r r/w a f t e r r e s e t 0 0 0 0 fu n c tio n tc1 i n i n p u t no ise re m o v a l 0:2/ fs y s or mo r e 1:6/ fs y s or mo r e " 0 " i s r ead. s e l e c t e f fe c t i v e ed ge o f tc 1i n i n pu t 00: n o t c a p t ur e 01: ri si ng ed ge 10: f a l l i ng ed ge 11: b o th e d ges cap 1 c r (0 x f f f f _ f418) : sel ect s t h e e f fe ct i v e ed ge of a n i n p u t t o t h e t r i g ger i n p u t pi n tc 1i n of t h e capt u re 1 regi s t er (tccap1). if th is is set t o "0 0," the ca pture operation is disa bled. : c ont r o l s t h e n o i s e rem oval f o r t h e tc 1 n f pi n i n p u t . if t h is is set t o "0 " (rem o v a l disab l ed ), an y inp u t of m o re th an 2 / fsys (50ns@fpe r iph=fc=40mhz ) i s accepte d as a trig ger i n put for tccap1, at whiche ver level tc 1i n pi n i s , "h" or " l ." if t h is is set t o "1 " (rem o v a l en ab led ) , an y inp u t of less t h an 6 / fsys (1 5 0ns @f pe ri p h =fc= 4 0 m h z ) i s rega r d ed as noi se an d rem oved , at whi c he ver l e vel t h e t c 1i n pi n i s , "h" o r " l ." t h e ra nge of rem oval ch a nge s depe n d i n g on t h e sel ect ed cl oc k gea r a n d a syste m clock used. t m rc captur e 1 re gis t er ( t ccap1) 7 6 5 4 3 2 1 0 bi t s y m bol ca p 107 ca p 106 ca p 105 ca p 104 ca p 103 ca p 102 ca p 101 ca p 100 read/ w r i t e r afte r r e se t f unc t i on capt ure 1 dat a 7 6 5 4 3 2 1 0 bi t s y m bol ca p 115 ca p 114 ca p 113 ca p 112 ca p 111 ca p 110 ca p 109 ca p 108 read/ w r i t e r afte r r e se t f unc t i on capt ure 1 dat a 7 6 5 4 3 2 1 0 bi t s y m bol ca p 123 ca p 122 ca p 121 ca p 120 ca p 119 ca p 118 ca p 117 ca p 116 read/ w r i t e r afte r r e se t f unc t i on capt ure 1 dat a 7 6 5 4 3 2 1 0 bi t s y m bol ca p 131 ca p 130 ca p 129 ca p 128 ca p 127 ca p 126 ca p 125 ca p 124 read/ w r i t e r afte r r e se t f unc t i on capt ure 1 dat a t cca p 1ll ( 0 x ffff_ f4 1 c ) t cca p 1lh ( 0 x ffff_ f4 1 d ) t cca p 1 hl ( 0 x ffff_ f4 1 e ) t cca p 1 hh ( 0 x ffff_ f4 1 f ) (no t e 1 ) af ter a res e t, the v a lue of tccap1 is u ndefine d. (no t e 2 ) dat a is no t c a ptur ed duri ng a read of the ca ptur e r e giste r . fig. 12-8 tmrc-r e lated r egisters tmp19a43 ( r e v2.0) 12-12 32-bit input capture (tm r c)
tmp19a43 t m rc captur e 2 co ntr o l r egis t er 7 6 5 4 3 2 1 0 bi t s y m bol tc2nf cp 2e g1 cp 2e g0 read/w r i t e r/w r r/w a f t e r res e t 0 0 0 0 func t i on tc 2 i n i n pu t no i s e rem o v a l 0: d i s abl e 1: e n abl e " 0 " i s read. s e l e c t e f fe c t i v e ed ge o f tc 2i n i n pu t 00: n o t c a p t ur e 01: r i si ng ed ge 10: fal l i ng ed ge 11: b o th ed ges ca p 2 cr (0 x ffff_f420) : selects the e f fective edge of an input to the trigg e r inpu t p i n tc 2 i n of th e cap t u re 2 reg i ster (tccap2). if th is is set t o "0 0," the ca pture operation is disa bled. : c ont r o l s t h e n o i s e rem oval f o r t h e tc 2i n p i n i n put . if th is is set to "0 " (rem o v a l disab l ed ), an y i n pu t of m o re th an 2 / fsys (50n s@fp eriph = fc=4 0 m hz ) is accepted as a trigger i n put for tcc a p2, a t wh ic heve r le vel the tc2in pin is , "h" or " l ." if t h i s i s set t o "1" (rem oval e n abl e d) , a n y i n put o f l e ss t h a n 6/ fsy s ( 1 50 n s @f peri ph= fc= 40m hz) i s regar d e d as noi se a nd rem oved , at w h i c he ver l e vel t h e t c 2i n pi n i s , " h " o r "l." t h e ran g e o f rem oval cha n g e s de pe ndi ng o n t h e sel ect ed c l ock gea r a n d a sy st em cl ock use d . t m rc captur e 2 re gis t er ( t ccap2) 7 6 5 4 3 2 1 0 bi t s y m bol ca p 207 ca p 206 ca p 205 ca p 204 ca p 203 ca p 202 ca p 201 ca p 200 read/ w r i t e r afte r r e se t f unc t i on capt ure 2 dat a 7 6 5 4 3 2 1 0 bi t s y m bol ca p 215 ca p 214 ca p 213 ca p 212 ca p 211 ca p 210 ca p 209 ca p 208 read/ w r i t e r afte r r e se t f unc t i on capt ure 2 dat a 7 6 5 4 3 2 1 0 bi t s y m bol ca p 223 ca p 222 ca p 221 ca p 220 ca p 219 ca p 218 ca p 217 ca p 216 read/ w r i t e r afte r r e se t f unc t i on capt ure 2 dat a 7 6 5 4 3 2 1 0 bi t s y m bol ca p 231 ca p 230 ca p 229 ca p 228 ca p 227 ca p 226 ca p 225 ca p 224 read/ w r i t e r afte r r e se t f unc t i on capt ure 2 dat a t cca p 2ll (0 x ffff_f424) t cca p 2lh (0 x ffff_f425) t cca p 2 hl (0 x ffff_f426) t cca p 2 hh (0 x ffff_f427) (no t e 1 ) af ter a res e t, the v a lue of tccap2 is u ndefine d. (no t e 2 ) dat a is no t c a ptur ed duri ng a read of the ca ptur e r e giste r . fig. 12-9 tmrc-r e lated r egisters tmp19a43 ( r e v2.0) 12-13 32-bit input capture (tm r c)
tmp19a43 t m rc capture 3 co ntr o l r egi s t er 7 6 5 4 3 2 1 0 b i t s y m b ol t c 3 n f c p 3e g 1 c p 3e g 0 rea d / w ri te r / w r r/ w a f t e r r e set 0 0 0 0 fu nct i on tc 3 i n in p u t n o i s e re m o v a l 0: d i s a bl e 1: e n a b l e "0" i s r e a d . s e l e c t e f f e c t i v e ed ge o f t c 3 i n i n pu t 00 : n o t c a p t ur e 01 : r i si ng ed g e 1 0 : fa ll i n g ed ge 11 : b o th e d g e s ca p3cr (0 x f f f f_f 4 28 ) : selects the e f fective edge of an input to the trigg e r inpu t p i n tc 3 i n of th e cap t u re 3 reg i ster (tccap3). if th is is set t o "0 0," the ca pture operation is disa bled. : c ont r o l s t h e n o i s e rem oval f o r t h e tc 3i n p i n i n put . if th is is set to "0 " (rem o v a l disab l ed ), an y i n pu t of m o re th an 2 / fsys (50n s@fp eriph = fc=4 0 m hz ) is accepted as a trigger i n put for tcc a p3, a t wh ic heve r le vel the tc3in pin is , "h" or " l ." if t h i s i s set t o "1" (rem oval e n abl e d) , a n y i n put o f l e ss t h a n 6/ fsy s ( 1 50 n s @f peri ph= fc= 40m hz) i s regar d e d as noi se a nd rem oved , at w h i c he ver l e vel t h e t c 3i n pi n i s , " h " o r "l." t h e ran g e o f rem oval cha n g e s de pe ndi ng o n t h e sel ect ed c l ock gea r a n d a sy st em cl ock use d . (no t e ) v a lues rea d from bit s 2 through 6 o f cap3 c r are all "0." t m r c c apture 3 r e gis t er ( t c c ap3) 7 6 5 4 3 2 1 0 bit s y m bol ca p 3 07 ca p 306 c a p 305 ca p 304 ca p 303 c a p 302 ca p 301 ca p 300 read/ w r i t e r a f ter res e t f unc t i on capt ur e 3 data 7 6 5 4 3 2 1 0 bit s y m bol ca p 3 15 ca p 314 c a p 313 ca p 312 ca p 311 c a p 310 ca p 309 ca p 308 read/ w r i t e r a f ter res e t f unc t i on capt ur e 3 data 7 6 5 4 3 2 1 0 bit s y m bol ca p 3 23 ca p 322 c a p 321 ca p 320 ca p 319 c a p 318 ca p 317 ca p 316 read/ w r i t e r a f ter res e t f unc t i on capt ur e 3 data 7 6 5 4 3 2 1 0 bit s y m bol ca p 3 31 ca p 330 c a p 329 ca p 328 ca p 327 c a p 326 ca p 325 ca p 324 read/ w r i t e r a f ter res e t f unc t i on capt ur e 3 data t c ca p 3ll ( 0 x ffff_ f4 2 c ) t c ca p 3lh ( 0 x ffff_ f4 2 d ) tcc ap3 h l ( 0 x ffff_ f4 2 e ) tcc ap3 h h ( 0 x ffff_ f4 2 f ) (no t e 1 ) af ter a res e t, the v a lue of tccap3 is u ndefine d. (no t e 2 ) dat a is no t c a ptur ed duri ng a read of the ca ptur e r e giste r . fig. 12-1 0 tmrc-rel a ted registers tmp19a43 ( r e v2.0) 12-14 32-bit input capture (tm r c)
tmp19a43 t m r c c o m p ar e c ont r o l r egi st er (c m p c t l) 7 6 5 4 3 2 1 0 bi t s y m bol t c f f e n 0 t c f f c 01 t c f f c 0 0 cm p r d e 0 cmpe n0 r ead/ w r i t e r r / w r / w r r / w a f ter r e s e t 0 0 1 1 0 0 0 f unc ti on "0 " i s r ead. t c ff0 re v e r s a l 0: d i s a b l e 1: e n a b l e tcf f 0 c o n t r o l 00 : r e ve r s a l 01 : s e t 10 : c l e a r 11 : d o n? t ca r e ?0 ? is re a d . d oub l e b u f f er s 0 0: d i s a b l e 1: e n a b l e c o m pare 0 en a b l e 0: d i s a bl e 1: e n abl e 7 6 5 4 3 2 1 0 bi t s y m bol t c f f e n 1 t c f f c 11 t c f f c 1 0 cm p r d e 1 cmpe n1 r ead/ w r i t e r r / w r / w r r / w a f ter r e s e t 0 0 1 1 0 0 0 f unc ti on "0 " i s r ead. t c ff1 re v e r s a l 0: d i s a b l e 1: e n a b l e tcf f 1 c o n t r o l 00 : r e ve r s a l 01 : s e t 10 : c l e a r 11 : d o n? t ca r e ?0 ? is re a d . d oub l e b u f f er s 1 0: d i s a b l e 1: e n a b l e c o m pare 1 en a b l e 0: d i s a bl e 1: e n abl e 7 6 5 4 3 2 1 0 bi t s y m bol t c f f e n 2 t c f f c 21 t c f f c 2 0 cm p r d e 2 cmpe n2 r ead/ w r i t e r r / w r / w r r / w a f ter r e s e t 0 0 1 1 0 0 0 f unc ti on "0 " i s r ead. t c ff2 re v e r s a l 0: d i s a b l e 1: e n a b l e tcf f 2 c o n t r o l 00 : r e ve r s a l 01 : s e t 10 : c l e a r 11 : d o n? t ca r e ?0 ? is re a d . d oub l e b u f f er s 2 0: d i s a b l e 1: e n a b l e c o m pare 2 en a b l e 0: d i s abl e 1: e n abl e 7 6 5 4 3 2 1 0 bi t s y m bol t c f f e n 3 t c f f c 31 t c f f c 3 0 cm p r d e 3 cmpe n3 r ead/ w r i t e r r / w r / w r r / w a f ter r e s e t 0 0 1 1 0 0 0 f unc ti on "0 " i s r ead. t c ff3 re v e r s a l 0: d i s a b l e 1: e n a b l e tcf f 3 c o n t r o l 00 : r e ve r s a l 01 : s e t 10 : c l e a r 11 : d o n? t ca r e ?0 ? is re a d . d oub l e b u f f er s 3 0: d i s a b l e 1: e n a b l e c o m pare 3 en a b l e 0: d i s a bl e 1: e n abl e c m p c t l0 ( 0 x f f f f _ f 470) c m p c t l1 ( 0 x f f f f _ f 471) c m p c t l2 ( 0 x f f f f _ f 472) c m p c t l3 ( 0 x f f f f _ f 473) fig. 12- 1 1 tmrc-rel a ted registers tmp19a43 ( r e v2.0) 12-15 32-bit input capture (tm r c)
tmp19a43 t m r c c o m p a r e c o n t r o l r e gi s t er ( c m p c t l) 7 6 5 4 3 2 1 0 bi t sy m bol tcff en4 t cff c 41 tcffc40 c m p rde4 cm p e n4 r e a d / w r i te r r / w r/ w r r/ w a fter r e s e t 0 0 1 1 0 0 0 func tion "0" i s r ead . t c ff4 re v e rs a l 0: d i s a b l e 1: e n abl e tcf f 4 c o n t r o l 00: r e ve r s al 01: s e t 10: c l e a r 11: d on? t ca r e ? 0 ? is r ead. d o ubl e buf f e r s 4 0: d i s a ble 1: e n ab le c o m par e 4 ena ble 0: d i s able 1: e n a b le 7 6 5 4 3 2 1 0 bi t sy m bol tcff en5 t cff c 51 tcffc50 c m p rde5 cm p e n5 r e a d / w r i te r r / w r/ w r r/ w a fter r e s e t 0 0 1 1 0 0 0 func tion "0" i s r ead . t c ff5 re v e rs a l 0: d i s a b l e 1: e n abl e tcf f 5 c o n t r o l 00: r e ve r s al 01: s e t 10: c l e a r 11: d on? t ca r e ? 0 ? is r ead. d o ubl e buf f e r s 5 0: d i s a ble 1: e n ab le c o m par e 5 ena ble 0: d i s able 1: e n a b le 7 6 5 4 3 2 1 0 bi t sy m bol tcff en6 t cff c 61 tcffc60 c m p rde6 cm p e n6 r e a d / w r i te r r / w r/ w r r/ w a fter r e s e t 0 0 1 1 0 0 0 func tion "0" i s r ead . t c ff6 re v e rs a l 0: d i s a b l e 1: e n abl e tcf f 6 c o n t r o l 00: r e ve r s al 01: s e t 10: c l e a r 11: d on? t ca r e ? 0 ? is r ead. d o ubl e buf f e r s 6 0: d i s a ble 1: e n ab le c o m par e 6 ena ble 0: d i s able 1: e n a b le 7 6 5 4 3 2 1 0 bi t sy m bol tcff en7 t cff c 71 tcffc70 c m p rde7 cm p e n7 r e a d / w r i te r r / w r/ w r r/ w a fter r e s e t 0 0 1 1 0 0 0 func tion "0" i s r ead . t c ff7 re v e rs a l 0: d i s a b l e 1: e n abl e tcf f 7 c o n t r o l 00: r e ve r s al 01: s e t 10: c l e a r 11: d on? t ca r e ? 0 ? is r ead. d o ubl e buf f e r s 7 0: d i s a ble 1: e n ab le c o m par e 7 ena ble 0: d i s able 1: e n a b le cmp c tl4 ( 0 x fff f_f474) cmp c tl5 ( 0 x fff f_f475) cmp c tl6 ( 0 x fff f_f476) cmp c tl7 ( 0 x fff f_f477) : c ont r o l s e n a b l i ng/ di sabl i n g of t h e c o m p are m a t c h det ect i o n. : c ont r o l s e n a b l i ng/ di sabl i n g of d o u b l e bu f f e r s o f t h e com p ar e re gi st er . : co n t ro ls f/f of th e co m p are match o u t pu t. : c ont r o l s e n a b l i ng/ di sabl i n g of f/ f r e ve rsal of t h e c o m p are m a t c h out p u t . fig. 12-1 2 tmrc-rel a ted registers tmp19a43 ( r e v2.0) 12-16 32-bit input capture (tm r c)
tmp19a43 t m rc com p are r e gister 0 (t ccm p0 ) 7 6 5 4 3 2 1 0 b i t s y m b ol cm p 0 07 c m p 006 cm p 0 0 5 cm p 0 04 cm p003 cm p 0 0 2 cm p 0 01 cm p000 re ad/ w r i t e r/ w a fter r e set 0 0 0 0 0 0 0 0 funct i on com p a r e r e g i st e r 0 da t a 7 6 5 4 3 2 1 0 b i t s y m b ol cm p 0 15 c m p 014 cm p 0 1 3 cm p 0 12 cm p011 cm p 0 1 0 cm p 0 09 cm p008 re ad/ w r i t e r/ w a fter r e set 0 0 0 0 0 0 0 0 funct i on com p a r e r e g i st e r 0 da t a 7 6 5 4 3 2 1 0 b i t s y m b ol cm p 0 23 c m p 022 cm p 0 2 1 cm p 0 20 cm p019 cm p 0 1 8 cm p 0 17 cm p016 re ad/ w r i t e r/ w a fter r e set 0 0 0 0 0 0 0 0 funct i on com p a r e r e g i st e r 0 da t a 7 6 5 4 3 2 1 0 b i t s y m b ol cm p 0 31 c m p 030 cm p 0 2 9 cm p 0 28 cm p027 cm p 0 2 6 cm p 0 25 cm p024 re ad/ w r i t e r/ w a fter r e set 0 0 0 0 0 0 0 0 funct i on com p a r e r e g i st e r 0 da t a t ccm p 0 ll (0 x f ff f _ f440 ) t ccm p 0 lh (0 x f ff f _ f441 ) t ccm p 0 hl (0 x f ff f _ f442 ) t ccm p 0 hh (0 x f ff f _ f443 ) t m r c c o m p ar e r egis t er 1 ( t cc m p 1) 7 6 5 4 3 2 1 0 bi t s y m bol cm p 1 0 7 c m p 106 cmp 105 cm p 104 cmp 103 cmp 102 c m p 101 cmp 100 read/ w r i t e r/ w a f ter res e t 0 0 0 0 0 0 0 0 f unc t i on com par e r egi s t er 1 dat a 7 6 5 4 3 2 1 0 bi t s y m bol cm p 1 1 5 c m p 114 cmp 113 cm p 112 cmp 111 cmp 110 c m p 109 cmp 108 read/ w r i t e r/ w a f ter res e t 0 0 0 0 0 0 0 0 f unc t i on com par e r egi s t er 1 dat a 7 6 5 4 3 2 1 0 bi t s y m bol cm p 1 2 3 c m p 122 cmp 121 cm p 120 cmp 119 cmp 118 c m p 117 cmp 116 read/ w r i t e r/ w a f ter res e t 0 0 0 0 0 0 0 0 f unc t i on com par e r egi s t er 1 dat a 7 6 5 4 3 2 1 0 bi t s y m bol cm p 1 3 1 c m p 130 cmp 129 cm p 128 cmp 127 cmp 126 c m p 125 cmp 124 read/ w r i t e r/ w a f ter res e t 0 0 0 0 0 0 0 0 f unc t i on com par e r egi s t er 1 dat a t c cm p 1ll (0 x ffff_f444) t c cm p 1lh (0 x ffff_f445) tcc m p1 hl (0 x ffff_f446) tcc m p1 hh (0 x ffff_f447) fig. 12-1 3 tmrc-rel a ted registers tmp19a43 ( r e v2.0) 12-17 32-bit input capture (tm r c)
tmp19a43 t m rc com p ar e regis t er 2 ( t ccmp2) 7 6 5 4 3 2 1 0 bi t s y m bol cm p 207 cm p 206 cm p 205 cm p 204 cm p 203 cm p 202 cm p 201 cm p 200 read/ w r i t e r/ w a f t e r res e t 0 0 0 0 0 0 0 0 f unc t i on com pare regi s t er 2 dat a 7 6 5 4 3 2 1 0 bi t s y m bol cm p 215 cm p 214 cm p 213 cm p 212 cm p 211 cm p 210 cm p 209 cm p 208 read/ w r i t e r/ w a f t e r res e t 0 0 0 0 0 0 0 0 f unc t i on com pare regi s t er 2 dat a 7 6 5 4 3 2 1 0 bi t s y m bol cm p 223 cm p 222 cm p 221 cm p 220 cm p 219 cm p 218 cm p 217 cm p 216 read/ w r i t e r/ w a f t e r res e t 0 0 0 0 0 0 0 0 f unc t i on com pare regi s t er 2 dat a 7 6 5 4 3 2 1 0 bi t s y m bol cm p 231 cm p 230 cm p 229 cm p 228 cm p 227 cm p 226 cm p 225 cm p 224 read/ w r i t e r/ w a f t e r res e t 0 0 0 0 0 0 0 0 f unc t i on com pare regi s t er 2 dat a t ccm p 2ll (0 x ffff_f448) t ccm p 2lh (0 x ffff_f449) t ccm p 2 hl ( 0 x ffff_ f4 4 a ) t ccm p 2 hh ( 0 x ffff_ f4 4 b ) t m rc co m p are reg i st er 3 (t ccmp 3 ) 7 6 5 4 3 2 1 0 b i t s y m b o l cmp 307 c m p 3 06 cmp 305 cmp 304 c m p 3 03 c m p 302 cmp 301 c m p 3 00 re ad / w r i te r/ w a f te r res e t 0 0 0 0 0 0 0 0 f u nc t i on com p are r e gi s t er 3 dat a 7 6 5 4 3 2 1 0 b i t s y m b o l cmp 315 c m p 3 14 cmp 313 cmp 312 c m p 3 11 c m p 310 cmp 309 c m p 3 08 re ad / w r i te r/ w a f te r res e t 0 0 0 0 0 0 0 0 f u nc t i on com p are r e gi s t er 3 dat a 7 6 5 4 3 2 1 0 b i t s y m b o l cmp 323 c m p 3 22 cmp 321 cmp 320 c m p 3 19 c m p 318 cmp 317 c m p 3 16 re ad / w r i te r/ w a f te r res e t 0 0 0 0 0 0 0 0 f u nc t i on com p are r e gi s t er 3 dat a 7 6 5 4 3 2 1 0 b i t s y m b o l cmp 331 c m p 3 30 cmp 329 cmp 328 c m p 3 27 c m p 326 cmp 325 c m p 3 24 re ad / w r i te r/ w a f te r res e t 0 0 0 0 0 0 0 0 f u nc t i on com p are r e gi s t er 3 dat a t c cmp 3ll ( f fff _ f 44 c) t c cmp 3lh ( 0 x fff f_ f 4 4 d ) t c cmp 3 hl ( 0 x fff f_ f 4 4 e ) t c cmp 3 hh ( 0 x fff f_ f 4 4 f ) fig. 12-1 4 tmrc-rel a ted registers tmp19a43 ( r e v2.0) 12-18 32-bit input capture (tm r c)
tmp19a43 t m rc com p ar e regis t er 4 ( t ccmp4) 7 6 5 4 3 2 1 0 bi t s y m bol cm p 407 cm p 406 cm p 405 cm p 404 cm p 403 cm p 402 cm p 401 cm p 400 read/ w r i t e r/ w a f t e r res e t 0 0 0 0 0 0 0 0 f unc t i on com pare regi s t er 4 dat a 7 6 5 4 3 2 1 0 bi t s y m bol cm p 415 cm p 414 cm p 413 cm p 412 cm p 411 cm p 410 cm p 409 cm p 408 read/ w r i t e r/ w a f t e r res e t 0 0 0 0 0 0 0 0 f unc t i on com pare regi s t er 4 dat a 7 6 5 4 3 2 1 0 bi t s y m bol cm p 423 cm p 422 cm p 421 cm p 420 cm p 419 cm p 418 cm p 417 cm p 416 read/ w r i t e r/ w a f t e r res e t 0 0 0 0 0 0 0 0 f unc t i on com pare regi s t er 4 dat a 7 6 5 4 3 2 1 0 bi t s y m bol cm p 431 cm p 430 cm p 429 cm p 428 cm p 427 cm p 426 cm p 425 cm p 424 read/ w r i t e r/ w a f t e r res e t 0 0 0 0 0 0 0 0 f unc t i on com pare regi s t er 4 dat a t ccm p 4ll (0 x ffff_f450) t ccm p 4lh (0 x ffff_f451) t ccm p 4 hl (0 x ffff_f452) t ccm p 4 hh (0 x ffff_f453) t m rc com p ar e regis t er 5 ( t ccmp5) 7 6 5 4 3 2 1 0 bi t s y m bol cm p 507 cm p 506 cm p 505 cm p 504 cm p 503 cm p 502 cm p 501 cm p 500 read/ w r i t e r/ w a f t e r res e t 0 0 0 0 0 0 0 0 f unc t i on com pare regi s t er 5 dat a 7 6 5 4 3 2 1 0 bi t s y m bol cm p 515 cm p 514 cm p 513 cm p 512 cm p 511 cm p 510 cm p 509 cm p 508 read/ w r i t e r/ w a f t e r res e t 0 0 0 0 0 0 0 0 f unc t i on com pare regi s t er 5 dat a 7 6 5 4 3 2 1 0 bi t s y m bol cm p 523 cm p 522 cm p 521 cm p 520 cm p 519 cm p 518 cm p 517 cm p 516 read/ w r i t e r/ w a f t e r res e t 0 0 0 0 0 0 0 0 f unc t i on com pare regi s t er 5 dat a 7 6 5 4 3 2 1 0 bi t s y m bol cm p 531 cm p 530 cm p 529 cm p 528 cm p 527 cm p 526 cm p 525 cm p 524 read/ w r i t e r/ w a f t e r res e t 0 0 0 0 0 0 0 0 f unc t i on com pare regi s t er 5 dat a t ccm p 5ll (0 x ffff_f454) t ccm p 5lh (0 x ffff_f455) t ccm p 5 hl (0 x ffff_f456) t ccm p 5 hh (0 x ffff_f457) fig. 12-1 5 tmrc-rel a ted registers tmp19a43 ( r e v2.0) 12-19 32-bit input capture (tm r c)
tmp19a43 t m rc com p ar e regis t er 6 ( t ccmp6) 7 6 5 4 3 2 1 0 bi t s y m bol cm p 607 cm p 606 cm p 605 cm p 604 cm p 603 cm p 602 cm p 601 cm p 600 read/ w r i t e r/ w a f t e r res e t 0 0 0 0 0 0 0 0 f unc t i on com pare regi s t er 6 dat a 7 6 5 4 3 2 1 0 bi t s y m bol cm p 615 cm p 614 cm p 613 cm p 612 cm p 611 cm p 610 cm p 609 cm p 608 read/ w r i t e r/ w a f t e r res e t 0 0 0 0 0 0 0 0 f unc t i on com pare regi s t er 6 dat a 7 6 5 4 3 2 1 0 bi t s y m bol cm p 623 cm p 622 cm p 621 cm p 620 cm p 619 cm p 618 cm p 617 cm p 616 read/ w r i t e r/ w a f t e r res e t 0 0 0 0 0 0 0 0 f unc t i on com pare regi s t er 6 dat a 7 6 5 4 3 2 1 0 bi t s y m bol cm p 631 cm p 630 cm p 629 cm p 628 cm p 627 cm p 626 cm p 625 cm p 624 read/ w r i t e r/ w a f t e r res e t 0 0 0 0 0 0 0 0 f unc t i on com pare regi s t er 6 dat a t ccm p 6ll (0 x ffff_f458) t ccm p 6lh (0 x ffff_f459) t ccm p 6 hl ( 0 x ffff_ f4 5 a ) t ccm p 6 hh ( 0 x ffff_ f4 5 b ) t m rc com p ar e regis t er 7 ( t ccmp7) 7 6 5 4 3 2 1 0 bi t s y m bol cm p 707 cm p 706 cm p 705 cm p 704 cm p 703 cm p 702 cm p 701 cm p 700 read/ w r i t e r/ w a f t e r res e t 0 0 0 0 0 0 0 0 f unc t i on com pare regi s t er 7 dat a 7 6 5 4 3 2 1 0 bi t s y m bol cm p 715 cm p 714 cm p 713 cm p 712 cm p 711 cm p 710 cm p 709 cm p 708 read/ w r i t e r/ w a f t e r res e t 0 0 0 0 0 0 0 0 f unc t i on com pare regi s t er 7 dat a 7 6 5 4 3 2 1 0 bi t s y m bol cm p 723 cm p 722 cm p 721 cm p 720 cm p 719 cm p 718 cm p 717 cm p 716 read/ w r i t e r/ w a f t e r res e t 0 0 0 0 0 0 0 0 f unc t i on com pare regi s t er 7 dat a 7 6 5 4 3 2 1 0 bi t s y m bol cm p 731 cm p 730 cm p 729 cm p 728 cm p 727 cm p 726 cm p 725 cm p 724 read/ w r i t e r/ w a f t e r res e t 0 0 0 0 0 0 0 0 f unc t i on com pare regi s t er 7 dat a t ccm p 7ll ( 0 x ffff_ f4 5 c ) t ccm p 7lh ( 0 x ffff_ f4 5 d ) t ccm p 7 hl ( 0 x ffff_ f4 5 e ) t ccm p 7 hh ( 0 x ffff_ f4 5 f ) fig. 12-1 6 t m rc-r elated regi ster s tmp19a43 ( r e v2.0) 12-20 32-bit input capture (tm r c)
tmp19a43 13. serial channel (sio) 13.1 features this de vice has three se rial i/o c h annels: sio0 t o si o2. eac h c h a n nel operates in either t h e uart m ode (asy nc hr o n o u s com m uni cat i on) o r t h e i/ o i n t e rface m ode (sy n ch ro n o u s com m uni cat i on) w h i c h i s se l ect ed by the user. i/o i n terface mode mode 0: this is t h e m ode to se nd and receive i/o dat a and ass o ciate d syn c hron ization si g n a ls (sclk) t o ex tend i/o. m ode 1: tx/ r x dat a l e ngt h: 7 bi t s asy n c h r o no us (u ar t) m ode: m ode 2: tx/ r x dat a l e ngt h: 8 bi t s m ode 3: tx/ r x dat a l e ngt h: 9 bi t s in t h e a b ove m odes 1 a n d 2 , pa ri t y bi t s ca n be a dde d. t h e m ode 3 has a wa ke up f u n c t i on i n w h i c h t h e m a st er co n t ro ller can start up slav e co n t ro llers v i a th e serial lin k (m u lti-co n t ro l l er system ). fi g . 13-2 sh ows th e b l o c k di ag ram of s i o0 . each cha n nel c onsists of a pre s caler , a serial clock ge ne ra tio n circu it, a receiv e b u f f er and its con t ro l circu it, and a sen d b u f f er a n d i t s co nt r o l c i rcui t . eac h c h annel f unct i o ns i nde pe nde nt l y . as the sios 0 to 2 o p e rate in th e sam e way , onl y s i o 0 i s d e scri be d here . bi t 0 1 2 3 45 6 sta r t s to p bi t 0 1 2 3 45 6 sta r t s to p pari t y bi t 0 1 2 3 45 6 bi t 0 1 2 3 45 6 sta r t s to p s t art s t op pari t y 77 7 bi t 0 1 2 3 45 6 sta r t 8 7 s t op bi t 0 1 2 3 45 6 s t art s t op (w ak e-up) bi t 8 7 i f b i t 8 =1, repres ent s address (s e l ec t c ode). i f b i t 8 =0, repres ent s da t a . z m ode 0 (i / o i n t e rf ac e m ode)/ m s b f i rst t r ansm i ss i on di re c t i on z m ode 1 (7-bi t u a rt m ode) z m ode 2 (8-bi t u a rt m ode) z m ode 3 (9-bi t u a rt m ode) w i t hout pari t y w i t h pari t y w i t hout pari t y w i t h pari t y 0 bi t 7 6 5 4 32 1 z m ode 0 (i / o i n t e rf ac e m ode)/ l s b f i r s t t r ansm i ss i on di re c t i on 7 bi t 0 1 2 3 45 6 fig. 13-1 dat a form at tmp19a43 (rev2.0) 13-1 serial chann el (sio)
tmp19a43 tmp19a43(rev2.0) 13-2 serial channel (sio) 13.2 block diagram (channel 0) fig. 13-2 sio0 block diagram sc0mod0 uart mode prescaler tb0out (from tmrb0) 16 32 64 8 4 2 t1 t4 t16 t0 br0cr br0add selector selector selector divider t1 t4 t16 t64 br0cr f sys /2 i/o interface mode 2 selector i/o interface mode sc0cr sc0mod0 receive counter ( 16 only with uart) serial channel interrupt control transmit counter ( 16 only with uart ) transmit control receive control receive buffer 1 (shift register) rb8 receive buffer 2 (sc0buf) error flag sc0mod0 tb8 send buffer 2 (sc0buf) interrupt request (intrx0) internal data bus sc0cr txd0 (shares p60) 0 cts (shares p62) internal data bus interrupt request (inttx0) sc0mod0 rxd0 (shares p61) sc0cr txdclk sc0mod0 parity control internal data bus serial clock generation circuit sclk0 input (shares p62) sclk0 output (shares p62) baud rate generator rxdclk send buffer 1 (shift register) sioclk br0cr fifo control fifo control 128 t64
tmp19a43 13.3 operation of each circuit (channel 0) 13.3.1 prescaler the device i n c l udes a 7-bit prescaler to ge ne rate neces sary clocks t o dri v e sio0. t h e input cloc k t0 to the prescaler i s selected by sys c r of c g t o p r o v i d e t h e fre que ncy o f e i t h er f p eri ph/ 2, fpe r i p h/ 4, f p eri ph/ 8, o r f p e r i p h/ 1 6 . the cl ock frequency fperi p h is eith er t h e cl ock "fgear ," to be selected by syscr1 of cg , or t h e cl oc k " f c" bef o re i t i s di vi ded by t h e cl oc k gear . the prescaler becom e s active only wh en t h e ba ud rate generat o r is selected for ge ne rating the se ri al t r ans f er cl ock . t a bl e 1 3 - 1 l i s t s t h e pre s cal er out put cl oc k re sol u t i o n. tmp19a43 (rev2.0) 13-3 serial chann el (sio)
tmp19a43 t able 13-1 cl ock re sol u tio n to the baud rate gen e ra tor @ = 40m hz pres cale r o u tp u t clo ck reso lu tion clear periph eral clock clock gear v alu e prescaler clock selecti on t1 t4 t1 6 t6 4 00(fperiph/16) fc/2 5 (0.8 s) fc/2 7 (3.2 s ) f c /2 9 (12.8 s ) f c /2 11 (51.2 s) 0 1 ( f p e r i p h / 8 ) f c / 2 4 (0.4 us) fc/2 6 (1.6 s ) f c /2 8 (6.4 s ) f c /2 10 (25.6 s) 1 0 ( f p e r i p h / 4 ) f c / 2 3 (0.2us) fc/2 5 (0.8us) fc/2 7 (3.2us) fc/2 9 (12.8 s) 000 (fc) 1 1 ( f p e r i p h / 2 ) f c / 2 2 (0.1us) fc/2 4 (0.4us) fc/2 6 (1.6 s ) f c /2 8 (6.4 s) 00(fperiph/16) fc/2 6 (1.6 s) fc/2 8 (6.4 s ) f c /2 10 (25.6 s ) f c /2 12 (102 s) 0 1 ( f p e r i p h / 8 ) f c / 2 5 (0.8us) fc/2 7 (3. 2 us) fc/2 9 (12.8 s ) f c /2 11 (51.2 s) 1 0 ( f p e r i p h / 4 ) f c / 2 4 (0.4us) fc/2 6 (1. 6 m s ) fc/2 8 (6. 4 s) fc/2 10 (25.6 s) 100(fc/2) 1 1 ( f p e r i p h / 2 ) f c / 2 3 (0.2 us) fc/2 5 ( 0 .8 u s ) fc/2 7 (3.2 us) fc/2 9 (12.8 s) 00(fperiph/16) fc/2 7 (3.2 us) fc/2 9 (12.8 s ) f c /2 11 (51.2 s ) f c /2 13 (204 s) 01(fperiph/8) fc/2 6 (1. 6 s) fc/2 8 (6.4 s ) f c /2 10 (25.6 s ) f c /2 12 (102 s) 1 0 ( f p e r i p h / 4 ) f c / 2 5 (0.8 us) fc/2 7 (3.2 us) fc/2 9 (12.8 s ) f c /2 11 (51.2 s) 110(fc/4) 1 1 ( f p e r i p h / 2 ) f c / 2 4 (0.4 us) fc/2 6 (1.6 s) fc/2 8 (6. 4 s) fc/2 10 (25.6 s) 00(fperiph/16) fc/2 8 (6.4 s) fc/2 10 (25.6 s ) f c /2 12 (102 s) fc/2 14 (410us) 01(fperiph/8) fc/2 7 (3.2 us) fc/2 9 (12.8 s ) f c /2 11 (51.2 s ) f c /2 13 (204 s) 10(fperiph/4) fc/2 6 (1. 6 s) fc/2 8 (6.4 s ) f c /2 10 (25.6 s ) f c /2 12 (102 s) 111(fc/8) 1 1 ( f p e r i p h / 2 ) f c / 2 5 (0.8 us) fc/2 7 (3.2 us) fc/2 9 (12.8 s ) f c /2 11 (51.2 s) 00(fperiph/16) f c / 2 5 (0.8 us) fc/2 7 (3.2 us) fc/2 9 (12.8 s ) f c /2 11 (51.2 s) 0 1 ( f p e r i p h / 8 ) f c / 2 4 (0.4 us) fc/2 6 (1.6 s ) f c /2 8 (6.4 s ) f c /2 10 (25.6 s) 10(fperiph/4) fc/2 3 (0.2 us) fc/2 5 (0.8 us) fc/2 7 (3.2 us) fc/2 9 (12.8 s) 0 (fgear) 000 (fc) 1 1 ( f p e r i p h / 2 ) f c / 2 2 (0.1 us) fc/2 4 ( 0 .4 u s ) fc/2 6 (1.6 us) fc/2 8 (6.4 s) 00(fperiph/16) f c / 2 5 (0.8 us) fc/2 7 (3.2 us) fc/2 9 (12.8 s ) f c /2 11 (51.2 s) 0 1 ( f p e r i p h / 8 ) f c / 2 4 (0.4 us) fc/2 6 (1.6 s ) f c /2 8 (6.4 s ) f c /2 10 (25.6 s) 1 0 ( f p e r i p h / 4 ) f c / 2 3 (0.2 us) fc/2 5 (0.8 us) fc/2 7 (3.2 us) fc/2 9 (12.8 s) 100(fc/2) 1 1 (fperiph/2) ? fc/2 4 (0.4 us) fc/2 6 (1.6 us) fc/2 8 (6.4 s) 00(fperiph/16) f c / 2 5 (0.8 us) fc/2 7 (3.2 us) fc/2 9 (12.8 s ) f c /2 11 (51.2 s) 01(fperiph/8) ? fc/2 6 (1.6 s ) f c /2 8 (6.4 s ) f c /2 10 (25.6 s) 10(fperiph/4) ? fc/2 5 (0.8 us) fc/2 7 (3.2 us) fc/2 9 (12.8 s) 110(fc/4) 1 1 (fperiph/2) ? ? fc/2 6 (1.6 us) fc/2 8 (6.4 s) 00(fperiph/16) f c / 2 5 (0.8 us) fc/2 7 (3.2 us) fc/2 9 (12.8 s ) f c /2 11 (51.2 s) 0 1 ( f p e r i p h / 8 ) f c / 2 4 (0.4 us) fc/2 6 (1.6 s ) f c /2 8 (6.4 s ) f c /2 10 (25.6 s) 10(fperiph/4) ? fc/2 5 (0.8 us) fc/2 7 (3.2 us) fc/2 9 (12.8 s) 1 (fc) 111(fc/8) 1 1 (fperiph/2) ? ? fc/2 6 (1.6 us) fc/2 8 (6.4 s) (no t e 1 ) the presc aler outpu t clock tn mu st be selec ted so that the relations hip " tn < fs y s /2" is satis fied (s o tha t tn is sl o w er than fsy s /2). (no t e 2 ) do not c h an ge the cloc k gear w h ile sio is operatin g . (no t e 3 ) the horizont al lines in the abov e t a ble indicate th at th e settin g is prohibited. the se rial interface ba ud rate gene rato r uses four differe n t c l ocks , i.e., t1, t4, t16 an d t64, s u p p l i e d f r om the prescaler output cloc k. 13.3.2 baud rate generator the ba ud rate gene rator ge ne rates tra n sm it and recei ve cl ocks to determine the serial c h annel tra n s f er rate. the ba u d rat e gene rat o r uses ei t h er t h e t1, t4, t16 or t64 cl ock s u ppl i e d fr om t h e 7 - bi t p r escal e r . th is inpu t clo c k selection is mad e b y setting th e b a ud rate settin g reg i ster , br0 cr
. th e b a u d rate g e n e rator con t ain s b u ilt-in d i v i d e rs for d i v i d e b y 1 , (n + m / 1 6 ) , and 16 wh ere n is a tmp19a43 (rev2.0) 13-4 serial chann el (sio)
tmp19a43 num ber from 2 t o 15 a n d m is a num b er from 0 t o 15. the divisi on i s pe rform e d according t o t h e settin g s of the b a ud rate co n t ro l reg i st ers br0 cr an d br0add t o d e term in e th e resu lting tran sfer rate. ? uar t m o de: 1 ) if br 0 cr = 0, th e setting o f br0 add is ign o red an d th e co un ter is d i v i d e d b y n wh ere n is th e v a l u e set t o br0 cr . (n = 1 t o 1 6 ). 2 ) if br 0 cr = 1, the n + ( 1 6 - k)/ 1 6 di vi si on fu nct i o n i s e n a b l e d a n d t h e di vi si o n i s m a de by u s i n g t h e v a l u es n (set i n br0cr ) an d k (set i n br 0 add ) . (n = 2 to 15 , k = 1 to 15 ) note for the n v a lues of 1 and 16, the abov e n+(1 6-k)/16 div i sion function is inhibited. so, be sure to set br 0cr< br 0ad d e > t o "0." ? i/o i n terface m ode: the n + (16 - k)/16 di vision function ca nnot be use d in the i/o interface m ode. be sure t o di vi de by n, b y set t i ng b r 0 c r t o " 0 ." ? b a ud rat e cal c u l a t i on t o use t h e bau d rat e ge nerat o r: 1) uar t m ode bau d rate = ratio divide by the divided frequency clock input generator rated baud /16 the hi g h est ba ud rat e o u t o f t h e bau d rat e ge nerat o r i s 6 2 5 kb ps w h en t1 i s 1 0 m h z . the fsy s / 2 fre que ncy , w h i c h i s i ndepe n d en t of t h e b a u d rat e gene rat o r , can be used as t h e serial clo c k . in th is case, th e hig h e st b a u d rat e w ill b e 1 . 25 mb p s wh en fsys is 40 mh z. tmp19a43 (rev2.0) 13-5 serial chann el (sio)
tmp19a43 2) i/ o i n t e rface m ode baud rate = ratio divide by the divided frequency clock input generator rated baud /2 th e h i gh est b a u d rate w ill b e g e n e rated wh en t1 i s 1 0 m h z. if d o ubl e bu f f e r i n g i s us ed, t h e d i v i d e ratio can b e set to "1 " an d t h e resu ltin g o u t p u t b a ud rate w ill b e 5 mbp s . (if dou b l e b u f f ering is not u s ed , t h e h i ghest b a u d rate will b e 2 . 5 m b p s app l yin g t h e div i d e ratio o f "2 .") ? exam pl e bau d rat e set t i ng: 1) di vi si o n by a n i n t e ger ( d i v i d e by n ) : selecting fc = 39. 3 21 m h z for fpe r iph, setting t0 t o fpe r i p h/ 1 6 , u s i ng t h e bau d rat e gene rat o r i n pu t cl ock t1, set t i ng t h e di vi de rat i o n (b r0cr) = 4 , an d set t i ng br0 cr = "0 ," th e resu lting b a ud rate in th e ua rt mo d e is calcu lated as fo llow s : * cl oc ki n g c o n d i t i ons sy st em cl ock : hi g h -s pee d (fc ) hi g h s p ee d cl o c k gear : x 1 (fc ) prescaler cloc k : f periph / 16 (f periph = f sy s ) baud rate = 4 fc/32 / 16 = 39 .3 21 (b p s ) 10 6 / 32 / 4 / 1 6 192 00 (bps) (no t e ) the div i de b y (n + (16-k)/16) func tion is inhibited and thus br0add is ignored. 2) for di vi de by n + (1 6 - k ) / 1 6 (o nl y f o r u a r t m ode): selectin g fc = 1 9 .2 m h z fo r fp eriph , setting t0 to fp eriph / 16 , u s ing th e b a ud rate g e nerato r in pu t clo c k t2 , settin g th e d i v i d e ratio n (br0cr) = 7 , settin g k (br0 add ) = 3 , and selecting br0 cr = 1, t h e resu lting b a u d rate is calcu lated as fo llo w s : * cl oc ki n g c o n d i t i ons sy st em cl ock : hi g h -s pee d (fc ) hi g h -s pee d cl o c k gear : x 1 (fc ) prescaler cloc k : f periph /4 (f periph = f sy s ) baud rate = 16 3) (16 7 fc/32 ? + /16 = 19.2 10 6 / 6 4 / (7 + 16 13 ) / 16 = 48 00 (b p s ) tmp19a43 (rev2.0) 13-6 serial chann el (sio)
tmp19a43 also, an exte rnal cloc k input m a y be us ed as t h e se ri al cl ock. t h e res u l t i ng ba u d rat e calcu latio n is sh own b e low : ? bau d rate calcu latio n fo r an ex tern al clo c k i n pu t: 1) uart m ode baud rat e = e x t e r n al cl oc k i n p u t / 16 in t h i s , t h e peri od o f t h e e x t e r n al cl oc k i n p u t m u st be eq ual t o o r great e r t h an 4/ fsy s . if fsys = 40 m h z, t h e h i gh est b a u d rate w ill b e 4 0 / 4 / 16 = 62 5 (kb p s ). 2) i/ o i n t e rface m ode baud rate = e x ternal cloc k i n put w h en do ub le bu fferi n g is used , it is n ecessa ry to satisfy th e fo llow i ng relatio n s h i p : ext e r n al cl oc k i n p u t pe ri o d > 12/ fsy s there f ore, w h en fsy s = 40 mhz, t h e bau d rat e m u st be set t o a rat e l o wer t h an 40 / 12 = 3. 3 (mbps) . w h en do ub le bu fferi n g is no t u s ed , it is n ecessary to satisfy th e fo llow i ng relatio n s h i p : ext e r n al cl oc k i n p u t pe ri o d > 16/ fsy s there f ore, w h en fsy s = 40 mhz, t h e bau d rat e m u st be set t o a rat e l o wer t h an 40 / 16 = 2. 5 (mbps) . exam pl e bau d rat e s f o r t h e u a rt m ode a r e sh ow n i n ta bl e 1 3 - 2 a n d t a b l e 13 - 3 . tmp19a43 (rev2.0) 13-7 serial chann el (sio)
tmp19a43 table 13 -2 selectio n of uart baud rate (u se th e b a u d rate g e n e rator w ith br0 cr = 0) unit ( kbps) fc [mhz] inpu t c l oc k di v i de ra tio n (set to br0c r ) t1 (fc/4) t4 (fc/16) t1 6 (fc/64) t6 4 (fc/256) 1 9 . 6 6 0 8 1 307.200 76.800 1 9 . 2 0 0 4.800 2 1 5 3 . 6 0 0 38.400 9 . 6 0 0 2.400 4 7 6 . 8 0 0 19.200 4 . 8 0 0 1.200 8 3 8 . 4 0 0 9.600 2 . 4 0 0 0.600 0 1 9 . 2 0 0 4.800 1 . 2 0 0 0.300 2 4 . 5 7 6 5 76.800 19.200 4 . 8 0 0 1.200 a 3 8 . 4 0 0 9.600 2 . 4 0 0 0.600 2 9 . 4 9 1 2 1 460.800 115.200 2 8 . 8 0 0 7.200 2 2 3 0 . 4 0 0 57.600 1 4 . 4 0 0 3.600 3 1 5 3 . 6 0 0 38.400 9 . 6 0 0 2.400 4 1 1 5 . 2 0 0 28.800 7 . 2 0 0 1.800 6 7 6 . 8 0 0 19.200 4 . 8 0 0 1.200 c 3 8 . 4 0 0 9.600 2 . 4 0 0 0.600 (no t e ) this t a ble sho w s th e ca se w h ere th e s y stem clock is set to fc, the cloc k gear is set to fc/1, and th e presc aler clock is set to f perip h /2. t able 13-3 selectio n of uar t baud ra te (the tmrb0 t i m e r out put (i n t ernal tb 0o u t ) i s use d wi t h t h e t i m er i nput cl ock set t o t0. ) fc tb0 r eg 29.49 12 mhz 24.57 6 mhz 24 mhz 19.66 08 mhz 16 mhz 12.28 8 mhz 1 h 2 3 0 . 4 1 9 2 1 8 7 . 5 1 5 3 . 6 1 2 5 9 6 2 h 1 1 5 . 2 9 6 9 3 . 7 5 7 6 . 8 6 2 . 5 4 8 3 h 7 6 . 8 6 4 6 2 . 5 5 1 . 2 4 1 . 6 7 3 2 4 h 5 7 . 6 4 8 4 6 . 8 8 3 8 . 4 3 1 . 2 5 2 4 5 h 4 6 . 0 8 3 8 . 4 3 7 . 5 3 0 . 7 2 2 5 1 9 . 2 6 h 3 8 . 4 3 2 3 1 . 2 5 2 5 . 6 2 0 . 8 3 1 6 8 h 2 8 . 8 2 4 2 3 . 4 4 1 9 . 2 1 5 . 6 3 1 2 a h 2 3 . 0 4 1 9 . 2 1 8 . 7 5 1 5 . 3 6 1 2 . 5 9 . 6 1 0 h 1 4 . 4 1 2 1 1 . 7 2 9 . 6 7 . 8 1 6 1 4 h 1 1 . 5 2 9 . 6 9 . 3 8 7 . 6 8 6 . 2 5 4 . 8 unit ( kbps) bau d rate calcu latio n t o u s e t h e tmrb0 ti mer: t r ans f er rate = 16 2 tb0reg 0 : prck1 syscr0 by selected frequency clock > < ( whe n i n p u t clo c k to t h e tim e r tmrb0 is t0 ) (no t e 1 ) in the i/o interfa ce mode , the tm rb0 timer outp u t signal ca n not be u sed internally a s the tr ans f er clock. (no t e 2 ) this t a ble sho w s th e ca se w h ere th e s y stem clock is set to fc, the cloc k gear is set to fc/1, and th e presc aler clock is set to f perip h /4. tmp19a43 (rev2.0) 13-8 serial chann el (sio)
tmp19a43 13.3.3 serial cloc k generatio n circuit thi s ci rc ui t ge nerat e s basi c t r ansm i t and rec e i v e cl oc ks. ? i/o i n terface m ode: in t h e scl k o u t p ut m ode wi t h t h e sc0cr seri al c ont rol re gi st er set t o "0 ," t h e out put of t h e pre v i o us l y m e nt i oned b a ud rat e ge nera t o r i s di vi ded b y 2 t o ge ne rat e t h e basi c cl oc k. in t h e sclk i n pu t m o d e w ith sc0 cr set to "1," risin g and fallin g edg e s are detected according t o the sc0cr setti ng t o generate the basic clock. ? asy n c h r o no us (u ar t) m ode: according t o t h e settings of t h e serial c o ntro l m ode re gister sc0m od0 , either t h e cl ock f r o m t h e bau d rat e regi st er , t h e sy st em cl ock (f sys /2) , t h e i n t e r n al out put si g n al of t h e tmrb0 tim er , or the e x ternal clock (sclko pin) is selected to ge nerate the basic clock, siocl k . 13.3.4 receive counter the recei ve c o unte r is a 4-bit bi nary counter us e d i n the a s ynchronous (uar t) m ode and is up-c ounted by sioclk. sixt een sioclk c l ock pulses a r e used i n receiving a single da ta bit whi l e t h e dat a sy m bol i s sa m p l e d at t h e s e vent h, ei g h t h , an d ni nt h p u l s es. fr om t h ese t h re e sam p les, m a jority logic is app lied to decide the receive d data. 13.3.5 receive control unit ? i/o i n terface m ode: in t h e scl k out put m ode wi t h sc 0cr set t o " 0 ," t h e rx d0 pi n i s sam p l e d on t h e ri si ng ed ge o f t h e s h i f t cl oc k o u t p ut t o t h e sc lk 0 pi n. in the sclk i n put m ode wit h sc0cr < i oc> set to "1," the se rial recei ve data r x d0 pi n is sam p led on t h e rising or fallin g edg e of sclk i n pu t d e p e nd ing on the sc0 c r settin g . ? asy n c h r o no us (u ar t) m ode: the receive cont rol unit has a st art bit detection circuit, whic h is used to initiate receive o p e ration w h en a no rm al start b it is d e tected. 13.3.6 receive buffer the recei ve buf f er is of a dual st ruct ure t o preve n t ove r run errors. the first receive buf f e r (a s h ift register) stores the receive d data b it-by-bit. w h e n a c o mplete set of bi ts have bee n s t ore d , they a r e m oved to t h e second recei ve buf f e r (sc 0 buf). at t h e sam e time, the receive buf f e r full flag (sc0m o d2 " rbfll") is set to " 1 " to indicate that vali d data is st or ed in the second recei ve buf f er . howe ver , i f the receive fifo is set ena b led, the recei ve da ta is m oved t o the receive fifo and t h is fla g is imm e diate l y cleared. if the receive fifo has bee n disabled (sc o fcnf = 0 a nd < f dpx1 :0> = 0 1), the intrx0 interrupt is generated at the sa me tim e . if the r eceive fifo has bee n e n abl e d (scnfcnf = 1 an d = 01), an i n terru p t w ill b e gen e ra ted acco r d i ng to th e sc0 r fc settin g . tmp19a43 (rev2.0) 13-9 serial chann el (sio)
tmp19a43 the cpu will read t h e data from e ither the second receive buf f er (sc0 b u f) or from the receive fifo (the address is the sam e as t h at of the rece ive buf f e r ). if the receive fifo ha s not be en e n a b led, t h e receive buf f er full flag is clea red to " 0 " by the read operation. the ne xt data received can be store d in the fi rst receive buf f er e v e n if the cpu has not read the pre v ious data from the sec o nd recei ve buf f e r (sc 0 buf) or the receive fifo. if sclk is s e t to ge nerate clock output in the i/o i n terface m ode, the doub le buf f er c o ntrol bit sc0mod2 < w buf> ca n be programm e d t o e n a b le or disa ble the operation of t h e second recei ve buf f e r (sc o buf). by disabli n g t h e second rece ive buf f er (i.e ., the d ouble buf f e r function) and als o disa bling the recei ve fifo (scofcnf = 0 a n d = 0 1 ) , han d s h aki n g wi t h t h e ot he r si de o f comm unication ca n be e n abl e d a n d t h e sclk output st op s each tim e one fram e of data is tra n s f erred. in this setting, t h e cpu rea d s data from the first receive buf f er . by the rea d ope r ation of cpu, t h e sclk out put res u m e s. if t h e sec o nd receive buf f e r (i.e., double buf fe ring) is e n a b led but the re ceive fifo is not e n a b led, t h e sclk out put is stoppe d whe n the first receive data is m oved from the first receive buf f er to the sec o n d receive buf fer and the ne xt data is stored i n t h e first buf f er f illing bot h buf f ers with vali d data. w h en t h e second receive buf f e r is rea d , the data of t h e first recei ve buf f e r is m ove d to the second recei ve buf fe r and t h e sclk out put is res u med upon ge neration of th e receive i n terrupt intrx. the r efore, no buf f e r overrun error will be cause d in the i/o int e rface sclk out put m ode regardless of t h e setting of the d oub le buf fer co n t ro l b it sc0mo d 2 . if the sec o nd receive buf f e r (double buf f ering) is enabled and the receive fifo i s also ena b le d (scnfcnf < c nfg> = 1 a n d = 01/ 1 1 ), t h e sclk output wi ll be stoppe d when t h e recei ve fifo is full (according to t h e setting of scofncf ) an d bot h the first and second receive buf f e r s contain valid data. also i n this case, if sc ofc n f < r xtxc nt> has bee n set to " 1 ," t h e receive co n t ro l b it rxe w ill b e au tomatical ly clear ed u pon su sp en sion o f t h e sclk o u t p u t . if it is set to "0 , " au to m a tic clear in g w ill no t be p e rform e d . (no t e ) in this m ode, the sc0 c r f l ag is insignificant a n d the opera ti on is undefin e d. there fore, before s w i t chi ng from the sclk output mode to an othe r mode, the sc0 cr re gister must be read to initializ e this flag. in ot her o p e r at i n g m odes, t h e o p erat i o n o f t h e sec o nd rece i v e bu f f e r i s al way s val i d , t h u s i m provi ng t h e perform a nce of continuous data tr ansfe r . if the recei ve fifo is not e n a b led, an overrun error occurs whe n t h e data in the second re ceive buf fe r ( s c0buf ) has not bee n read be fore the first re ceive buf fe r is full with the next recei ve dat a . if an overrun error occurs, data in t h e fi rst receive buf f er will be l o st while data i n t h e sec o nd rece ive buf f e r a n d the c ont e n ts of sc0cr rem a in intac t . if t h e receive fifo is enabled, t h e fifo must be read before t h e fifo i s full and th e second receive buf f er is written by the next dat a through t h e first buf f er . otherwise, an overrun error will be ge nerated and t h e receive fifo overrun error fl ag will be set. even in th is case, the data already in t h e receive fifo rem a ins in tact. th e p a rity b it to b e add e d in th e 8 - b it ua r t m o d e as w e ll as th e m o st sign ifican t b it in th e 9 - b it ua r t m o d e w ill b e st o r ed i n sc0 cr . tmp19a43 (rev2.0) 13-10 serial chann el (sio)
tmp19a43 in t h e 9 - bi t u a r t m ode, t h e sl ave c ont r o l l er ca n be o p er at ed i n t h e wak e -u p m ode by set t i ng t h e wa k e - u p fun c tio n sc0 m od 0 to "1." in th is case, th e i n terrup t in trx0 w ill b e g e nerated on ly wh en sc0cr is set to " 1 ." 13.3.7 receive fifo buffer in addition to the d ouble buf f er function already descri bed, data m a y be stor ed using t h e receive fifo b u f f er . by settin g of t h e sc0fcnf reg i ster and of th e sc0 m od1 reg i ster , th e 4 - byte receive buf f er can be enable d. als o , in the uar t m ode or i/o interface m ode, data m a y be stored u p to a p r ed efi n ed fill lev e l. w h en th e receiv e fifo b u f f er is t o b e u s ed , b e sure t o en ab le th e dou b l e bu f f e r fu nct i o n . if data with pa rity bit is to be receive d in t h e uar t m ode, parity chec k m u st be performed each tim e a data fram e is received. 13.3.8 receive fifo operatio n c i/ o i n t e rface m ode wi t h scl k out put : the following exam ple descri bes t h e case a 4-byte da ta st rea m is receive d in the half duplex m ode: sc0 r fc<7 : 6 >=0 1 : clears receiv e fifo an d se ts th e co nd itio n of i n terrup t g e n e ration . sc0 r fc<1 : 0 >=0 0 : sets th e in terrup t to b e gen e rated at fill lev e l 4 . sc0fc n f <1: 0 >=101 1 1 : aut o m a tically inhibits con tinued reception after r eachi n g the fill level. the num b er of bytes to be us ed i n t h e recei ve fifo is t h e sam e as the in terru p t g e n e ratio n fill lev e l. in th is con d iti o n , 4 - b y te d a ta recep tion may b e i n itiated b y settin g t h e h a lf d u p l ex tran sm issio n m ode and writing " 1 " to the r x e bit. after receiving 4 bytes, the r x e bi t is autom a tica lly cleared and the receive operation is stoppe d (sclk i s stoppe d). 1 by t e 2 by t e 3 by t e 4 by t e 1 by t e 1 by t e 1 by t e 1 by t e 2 by t e 2 by t e 2 by t e 2 by t e 1 by t e 3 by t e 3 by t e 3 by t e 4 by t e 4 by t e receive buf fe r 1 receive buf fe r 2 rx fi fo rbfll receive interrupt rxe fig. 13-3 re ceive fifo op eration tmp19a43 (rev2.0) 13-1 1 serial chann el (sio)
tmp19a43 d i/o i n terface mo d e w ith sclk inpu t: the following exam ple descri bes t h e case a 4-byte data st rea m is receive d: sc0rfc <7:6> = 10: clears recei ve fifo and sets the cond ition of interr upt generation sc0 r fc <1 :0> = 00 : sets the in terrup t to be g e n e rated at fill lev e l 4 . sc0fc n f <1: 0 > = 10101: aut o m a tically allows con tinued reception after reac hing t h e fill level. the num b er of bytes t o be us ed i n t h e recei ve fifo is t h e m a ximu m allowable number . in t h is co nd itio n, 4 - b y te d a t a recep tio n can b e in itiated alo n g w ith th e in pu t clo c k by settin g th e h a lf dup lex tran sm issio n m o de an d w r iting "1 " to th e rx e b it. w h en th e 4 - b y te d a ta recep tio n is com p leted, the receive fifo i n terrupt will be generated. not e t h at pre p arat i on fo r t h e next dat a rece p t i on can be m a nage d i n t h i s s e t t i ng, i . e. , t h e next 4- by t e d a ta can be receiv ed b e fore data is fu lly read fro m th e fifo . receive buf fe r 1 rx fi fo receive buf fe r 2 1 by t e 2 by t e 3 by t e 4 by t e 1 by t e 1 by t e 1 by t e 1 by t e 2 by t e 2 by t e 2 by t e 2 by t e 1 by t e 3 by t e 3 by t e 3 by t e 4 by t e 4 by t e rxe receive interrupt rbfll fig. 13-4 re ceive fifo o p eratio n tmp19a43 (rev2.0) 13-12 serial chann el (sio)
tmp19a43 13.3.9 t r ansmit counter the t r a n sm it cou n t e r i s a 4 - b i t bi na ry c o unt er use d i n t h e asy n ch ro n o u s com m uni cat i on ( uar t ) m ode. it is c o unted by sioclk a s in t h e ca se of the receive counter a nd ge nerates a t r ansm it clock (txd clk ) on ev ery 16 th clock p u l se. 2 1 1 5 1 6 14 13 12 9 1 0 11 7 8 6 5 4 1 2 3 16 15 txdclk sio c l k fig. 13-5 t r a n smit clo c k gene ration 13.3.10 t r ansmit control unit ? i/o i n terface m ode: in the sclk output m ode with sc 0cr set to "0," each bit of dat a in the send buf f er is out put t o t h e t x d 0 pi n o n t h e ri si n g e dge o f t h e shi f t cl oc k out put fr om the scl k 0 pi n. in the sclk i n put m ode with sc 0cr < i oc> set to "1," each bit of dat a in t h e se nd buf f er is out put t o t h e t x d 0 pi n o n t h e ri si ng or fal l i ng e d ge o f t h e i n p u t sclk si gnal acc or di n g t o t h e sc0 cr setting . ? asy n c h r o no us (u ar t) m ode: w h en t h e cpu w r ites d a ta to th e send bu f f er , d a ta tran sm is sio n is i n itiated o n t h e risi n g edg e of t h e ne xt tx dclk an d t h e t r ansm i t shi f t cl ock (t xd sft ) i s al s o gene ra t e d. tmp19a43 (rev2.0) 13-13 serial chann el (sio)
tmp19a43 ? h a nd sh ak e functio n the cts pin ena b l e s fram e by fram e data transm ission so that ove r run errors ca n be pre v e n t e d. t h i s f unct i o n ca n be e n abl e d or d i sabl ed by sc 0 m od 0 . whe n t h e cts0 p i n is set to t h e "h " lev e l , th e cu rren t d a ta t r an sm issio n can b e co m p leted b u t th e n e x t data tran sm issi o n is su sp en ded un til th e cts0 pin ret u rn s to th e "l" lev e l . h o w e v e r in t h is case, th e in ttx0 in terrup t is g e n e rated, the n e x t tran sm it d a ta is requ est e d to th e cpu , d a ta i s written to t h e send bu f f er , an d it w a its u n t i l it is read y t o t r an sm it d a ta. a lth oug h no rts p i n i s p r o v i d e d , a ha nds ha ke cont rol fu nct i o n ca n be ea si l y im pl em ent e d by assi g n i n g a po rt f o r t h e rts fun c tio n. by settin g t h e p o rt to "h " lev e l u pon co m p letio n o f data recepti on (in the recei ve in terrupt routine), the tra n sm it si de ca n be re que sted to s u s p end d a ta tran sm issi o n . cts txd transmit side receive side rxd rts (a n y po rt) fig. 13-6 han d sh ake fun c tion 3 2 1 16 15 start bit bit 0 c d 13 14 transmission i s suspended during this per iod data w r ite timing to send buffer o r shift reg i ster cts 14 1 5 1 6 1 2 3 sioclk txdclk txd (no t e ) c if t h e cts signal is set to "h" during tr ansmission, the next d a t a tran smission is suspe nded a f ter th e curr e n t tra n smiss i on is completed. d dat a tra n smission st a r t s on the firs t falling edge of th e txdclk cloc k af ter cts is set to "l." fig. 13-7 cts (cl ear to send ) signal t i min g tmp19a43 (rev2.0) 13-14 serial chann el (sio)
tmp19a43 13.3.11 t r ansmit buffer th e send buffer (sc0 buf) is in a du al st ru ct u r e. th e do ub le b u ffering fun c tio n m a y b e en ab led o r di sabl e d by set t i ng t h e d o u b l e bu ffe r c ont rol bi t < w bu f> i n seri al m ode c ont rol re gi st er 2 ( s c0mo d 2 ) . if dou b l e b u ffering is en ab led, d a ta written t o send buffer 2 (sco bu f) is m o v e d t o send buffer 1 (sh i ft register ). if t h e t r a n sm i t fif o has be en di sa bl ed (s cofc n f = 0 or 1 an d = 01), the int t x i n t e r r u pt i s ge nerat e d at t h e sam e t i m e an d t h e sen d bu ffe r em pt y fl ag < t bemp> of sc 0mo d 2 is set t o "1 ." th is flag ind i cat es th at sen d buffer 2 i s n o w e m pty an d t h at t h e ne xt t r a n s m i t dat a ca n b e w r itten . w h en th e n e x t d a ta is w r itten to send b u ffer 2 , th e flag is cleared t o "0 ." if t h e tran sm it fifo h a s b e en en ab led (scnfcn f = 1 and < f dpx1:0> = 10/11), any data i n t h e t r a n sm it fi fo i s m ove d t o t h e se nd b u f f e r 2 a nd < t bemp> flag is immediately clea red to " 0 ." the cpu w r ites d a t a to send b u ffer 2 o r t o th e tran sm it fifo . if the t r ansm it fifo is disa bled in the i/o interface sc lk input m ode and i f no data is set in send bu ffe r 2 be fo r e t h e ne xt fra m e cl ock i n p u t , whi c h occ u r s up o n com p l e t i on o f dat a t r ansm i ssi on fr o m send bu ffer 1 , an und er-run erro r o c cu rs and a seri al cont ro l regi st er ( s c0 cr) p a rity/u nd er-run flag is set. if t h e tran sm it fifo is en ab led in t h e i/o i n terf ace scl k i n p u t m ode, w h en dat a t r a n sm i ssi on fr om sen d b u f f er 1 i s com p l e t e d, t h e se nd b u f f er 2 dat a i s m o v e d t o se n d b u f fer 1 a nd a n y dat a i n t r a n sm it fif o is m ove d to se nd buffe r 2 at the sam e tim e . if t h e t r ansm i t fif o i s di sa bl ed i n t h e i/ o i n t e rface scl k o u t p ut m ode, whe n dat a i n s e nd bu ffe r 2 i s m oved t o se n d b u f f er 1 a n d t h e dat a t r an sm i ssi on i s c o m p l e t e d, t h e scl k out put st ops . s o , no u n d er - ru n e r r o r s ca n be gene rat e d . if t h e tran sm it fifo is en ab l e d in th e i/ o i n terface sclk ou tpu t m o d e , th e sclk ou tp u t stop s up on co m p letio n of d a ta tran sm issi o n fro m send bu ffer 1 if th ere is no v a lid d a ta in th e tran sm it fifo . note) in the i/o interface sclk outp ut mode, the sc0cr < peer> flag is insignifican t. in this case, the operati on is undefined. therefo re, to s w i t ch from the sclk o u tpu t mode to ano t her mode, sc0cr must b e r ead in adv a nce to initializ e the flag. if d oub le bu ffering is d i sab l ed , th e cpu w r ites d a ta o n ly to sen d b u ffer 1 and th e t r an sm it in terrup t int t x i s ge ne rat e d u p o n c o m p l e t i on o f dat a t r ansm i ssi on. if h a nd sh ak ing w ith t h e o t her sid e is n e cessary, set th e d oub le bu ffer co n t ro l b it to "0" (di s a b l e ) t o di sabl e se nd b u f f e r 2; any set t i n g f o r t h e t r a n sm it fif o s h oul d not be pe rf orm e d. tmp19a43 (rev2.0) 13-15 serial chann el (sio)
tmp19a43 13.3.12 transmit fifo buffer in add itio n to th e do ub le b u f f er fun c tion alread y d e scri b e d, d a ta m a y b e sto r ed u s ing t h e tran sm it fifo b u f f er . by settin g of t h e sc0fcnf reg i ster and of th e sc0 m od1 reg i ster , th e 4 - byte send buf f er ca n be e n abl e d. in the uar t m ode or i/o interface m ode , up t o 4 bytes of data m a y be store d . if data is to b e tran sm it ted w i th a p a rity b it i n t h e u a r t m ode , pa ri t y che c k m u st be pe r f o r m e d o n t h e receive si de ea ch tim e a data fram e is received. 13.3.13 t r ansmit fifo operation c i/ o i n t e rface m ode wi t h scl k out put ( n o r m a l m ode): the following exam ple descri bes t h e case a 4 - b y te d a ta st rea m is tran sm it ted : sc0 t fc <7 : 6 > = 01 : clears tran sm it fifo an d sets th e con d ition o f in terrup t g e n e ration sc0 t fc <1 : 0 > = 00 : sets the in terrup t to be g e n e rated at fill lev e l 0 . sc0fc n f <1: 0 > = 0101 1: inhib its continued transm ission af ter reachi n g the fill level. in th is con d itio n, d a ta tran smissio n can be in itiate d b y settin g th e tran sfer m o d e t o h a lf dup lex , w r iting 4 b y tes o f d a ta to the tran sm it fifo , an d settin g th e bit to "1 ." w h en th e last tran sm it d a ta is m o v e d t o th e sen d bu f f er , th e tran sm i t fifo in terru p t is g e n e rat e d . w h en t r ansm i ssi on o f t h e l a st dat a i s com p l e t e d, t h e cl ock i s st o ppe d an d t h e t r ansm i ssi on se que nce i s termin ated . data 6 data 6 data 5 data 6 data 4 data 5 data 6 data 3 data 4 data 5 data 2 data 3 data 4 data 5 data 1 data 2 data 3 data 4 data 5 data 6 tx f i fo send bu f f er 2 send bu f f er 1 tbem p int t x0 txe fig. 13-8 t r a n smit fifo o p eratio n tmp19a43 (rev2.0) 13-16 serial chann el (sio)
tmp19a43 d i/o i n terface mo d e w ith sclk inpu t (no r mal m o d e ): the following exam ple descri bes t h e case a 4 - b y te d a ta st rea m is tran sm it ted : sc0 t fc <1 : 0 > = 01 : clears th e tran sm it fifo and sets t h e con d ition o f in terrup t g e n e ratio n . sc0 t fc <7 : 2 > = 000 000 : sets th e in terru p t to b e g e n e rated at fill lev e l 0 . sc0fc n f <4: 0 > = 01001: allows continued transm ission afte r reachi n g the fill level. in th is co nd itio n, d a ta tran smissio n can be in itiated alon g w ith th e in pu t clo c k b y settin g t h e tran sfer m o d e to h a lf du p l ex , writin g 4 b y tes of d a ta t o t h e tr ansm i t fifo, an d settin g the b it to "1 ." w h en th e last transmit d a ta is mo v e d to th e sen d bu f f er , th e t r an sm it fifo in terrup t is gene rat e d . data 6 data 6 data 5 data 6 data 4 data 5 data 6 data 3 data 4 data 5 data 2 data 3 data 4 data 5 data 1 data 2 data 3 data 4 data 5 data 6 tx f i fo send bu f f er 2 send bu f f er 1 tbem p int t x0 txe fig. 13-9 t r a n smit fifo o p eratio n tmp19a43 (rev2.0) 13-17 serial chann el (sio)
tmp19a43 13.3.14 parity control circuit if th e p a rity ad d ition b it o f th e serial con t ro l re g i st er sc0 cr is set to "1 ," d a ta is sen t w ith the p a rity b it. n o te th at th e p a rity b it m a y b e used on ly in th e 7 - o r 8-b it uart m o d e . th e b it of sc0cr sel ect s ei t h er e v e n or od d pa ri t y . u pon d a ta tran sm issio n , th e p a rity co n t ro l circu it au to matically g e n e rates th e p a rity w ith th e d a ta w r itten t o th e sen d buffer (sc0 bu f). af ter d a ta tran sm issi o n is co m p lete, th e p a rity b it w ill b e st o r ed i n sc0bu f bi t 7 i n t h e 7- bi t u a rt m ode and i n b i t 7 i n t h e seri al m ode cont rol regi st er sc0 m od i n t h e 8 - b it u a r t m o d e . th e and setting s m u st b e co m p let e d b e fore d a ta is w r itten t o th e sen d buffer. upon data rec e ption, t h e parity b it for the receive d data i s aut o m a tically gene rated while the data i s shifted t o rece ive buffer 1 a nd m ove d to receive buffer 2 (sc 0 buf). in th e 7-bit uart m ode, the p a rity g e n e rated is co m p ared w ith th e p a rity sto r ed in sc0 b u f , wh ile in th e 8 - b i t u a r t m o d e , it is co m p ared w ith th e b it 7 of th e sc0 cr re gister. if the r e is any di ffere n ce, a parity erro r occurs a n d the flag of th e sc0 cr reg i ster is set. in the i/o interface m ode, the sc 0cr flag func tions as a n unde r -run error flag, not as a pa rity flag. 13.3.15 error flag three error flags are prov ided to increase t h e relia bility of received data. 1. ove r r u n e r r o r : bi t 4 of t h e se ri al cont rol regi st e r sc0cr in bot h uar t and i/ o interface m odes, thi s bit is set to "1" when a n e r ror is ge ne rated by com p leting the reception of t h e ne xt fram e receive data before t h e rec e ive buf f er ha s bee n read. if th e receiv e fifo is en ab led , t h e receiv ed d a ta is au to m a tical ly mo v e d t o th e receiv e fifo and no overrun error wi ll be generated until the recei ve fi fo is full (or until the usable b y tes are fu lly o c cu p i ed ). this flag is set to "0 " wh en it is read. in t h e i/o in terface sclk out put m ode, no o v e r r u n er r o r i s ge ne rat e d a n d t h e r ef or e, t h i s fl ag i s i n o p erat i v e an d t h e ope rat i o n i s un defi ned . 2. pari t y err o r/ un der - r u n er r o r < p err>: bi t 3 of t h e sc0cr regi st er in th e ua r t m o d e , th is b it is set to "1 " wh en a p a rity error is g e n e rated . a p a rity erro r is gene rat e d whe n t h e pa ri t y g e nerat e d fr om t h e receiv ed d a ta is d i f f eren t fro m th e parity receive d. this flag is set to " 0 " when it is rea d . in t h e i/o interface m ode, this bit indicates a n unde r -run e r ror . whe n th e double buf fe r control b it o f th e serial mo d e con t ro l reg i ster sc0 m od 2 is set to "1" in th e sclk in pu t m o d e , if no d a ta is set to th e tran sm it d o uble b u f f e r be f o r e t h e ne xt dat a t r ans f er cl ock aft e r co m p letin g the transm issio n fro m th e tran sm it sh ift reg i ster , t h is erro r flag is set to "1 " i ndi cat i n g a n u nde r - r u n e r r o r . if t h e t r an sm it fif o is en ab led , an y d a ta conten t in th e transmit fifo w ill b e m o v e d to th e b u f f er . w h en th e tran sm it fifo and t h e dou b l e bu f f er are bo th e m pty , an under -run error wi ll be gene rated. b ecause no unde r - run e r rors can be gene ra ted in t h e sclk o u t p ut m ode, t h i s fl ag i s i n ope rat i v e an d t h e o p e r at i on i s u nde fi ned . i f se nd b u f fe r 2 is d i sab l ed , t h e un d e r - run flag w ill n o t b e set. th is flag is set to "0 " w h en it is read . tmp19a43 (rev2.0) 13-18 serial chann el (sio)
tmp19a43 3. fram i ng er ro r : bi t 2 o f t h e sc0cr regi st er in th e u a r t m o d e , th is b it i s set t o "1 " when a fram i n g erro r is g e n e rat e d . th is flag is set t o "0 " w h en it is read . a fram in g error is g e n e rated if t h e corresp ond ing st o p b it is d e term in ed t o b e "0 " b y sam p lin g th e b it at aroun d th e cen t er . reg a rd less of th e (stop b it len g t h ) set t i ng of t h e s e ri al m ode c o n t rol regi st er 2, sc0mo d 2 , t h e st o p bi t st at u s i s det e rm i n ed by only 1 bit on the receive side . ope r a t ion mo de error fla g func tio n oerr overrun error flag p e r r p a r i t y e r r o r f l ag uart ferr framing error f l ag oerr overrun error flag underrun error f l ag (wbuf = 1) perr fixed to 0 (wb u f = 0) i/o interface (sclk input) ferr fixed to 0 o e r r o p e r a t i o n undef i n e d p e r r o p e r a t i o n undef i n e d i/o interface (sclk output) ferr fixed to 0 tmp19a43 (rev2.0) 13-19 serial chann el (sio)
tmp19a43 13.3.16 direction of dat a t r ansfer in the i/o i n terface m ode, t h e direction of data tran s f er ca n be s w itche d betwee n "msb first" a n d "lsb first" b y th e d a ta tran sfer d i rectio n setting b i t of th e sc0 m od 2 serial m o d e con t ro l reg i st er 2. d on' t swi t c h t h e di rect i o n whe n dat a i s b e i ng t r ans f er re d. 13.3.17 s t op bit length in t h e u a r t m o d e tran sm is sio n , th e st o p bit len g t h can be set to eith er 1 o r 2 b its b y b it 4 of t h e sc 0mo d 2 re gi st er . 13.3.18 s t atus flag if th e dou b l e bu f f er fun c tio n is en ab led (sc0 mod 2 = "1 "), t h e b it 6 flag o f th e sc0mod2 register indicates the co ndition of receive buf f er full. w h en one fram e of data has been receive d and transfe rre d fr om buf f e r 1 to buf f er 2, t h is bit is set to "1" to s h ow that buf f e r 2 is full (data is store d in buf f er 2). whe n the recei ve buf fer is rea d by c p u/dm ac, it is cleared to " 0 ." if < w b u f> is set to "0 ," th is b it is in sign ifican t an d mu st no t b e u s ed as a statu s fl ag . w h en d oub le bu f f eri n g i s enable d (sc0mod2 < w buf> = "1" ) , th e b it 7 flag of th e sc 0mod2 re gister indicates tha t sen d bu f f er 2 i s em pt y . w h e n dat a i s m ove d f r om sen d b u f f er 2 t o se nd b u f f er 1 (shi ft r e gi st er) , t h i s bi t is set to "1 " in d i cating th at sen d bu f f er 2 is no w em p t y . w h en d a ta is set to th e sen d bu f f er b y cpu/dm ac, t h e bit is cleare d t o " 0 ." if < w buf> is se t to "0," t h is b it is in sign ifican t an d m u st no t b e use d as a status flag. 13.3.19 configurations of send/receive buffers = 0 = 1 transmit buff e r single double uart receive bu ffer double double transmit buff e r single double i/o interface (sclk input) receive bu ffer double double transmit buff e r single double i/o interface (sclk output) receive bu ffer single double 13.3.20 softw are re set soft ware reset is hsc 0 mod2 ?10? ?01 ? sc0 m od0 rxe sc0mod1 sc0m od2 tbemp , rbfll , txr u n sc0cr oerr per r fer r and i n ternal circu it is in it ialized . othe r states are m a intained. tmp19a43 (rev2.0) 13-20 serial chann el (sio)
tmp19a43 13.3.21 signal gen e ration t i ming c uar t mo de: receive side mode 9 - bit 8 - bit w i t h pa rity 8 - bit, 7 - bit , a n d 7 - bit w i t h pa rity interrupt gen e ration tim ing around the cen ter of the 1st stop bit around the cen ter of the 1st stop bit around the cen ter of the 1st stop bit framing error timing around the cen ter of the stop b it around the cen ter of the stop bit around the cen ter of the stop b i t parity error g e neration tim ing ? around the cen ter of the last (p arit y) bi t around the cen ter of the last (parity ) bit overrun error generation tim ing around the cen ter of the stop b it around the cen ter of the stop bit around the cen ter of the stop b i t t r an sm it sid e mode 9 - bit 8 - bit w i t h pa rity 8 - bit, 7 - bit , a n d 7 - bit w i t h pa rity interrupt gen e ration tim ing ( = 0) just be fore the stop bit is sent just before the stop bit is se nt just be fore the stop bit is se nt interrupt gen e ration tim ing ( = 1) im m e diatel y aft e r data is moved to send buffer 1 ( j u s t before start bit tra n smission) im m e diatel y aft e r dat a is moved to send b u ffer 1 (just befor e start bit tra n smission) immediately after data is moved to send buffer 1 ( j u s t before star t b i t tra n smission) d i/o i n terface m ode: receive side sclk output mode im m e diatel y aft e r the ris i ng edg e of the l a s t s c lk interrupt gen e ration tim ing (wbuf = 0) sclk input mo de im m e diatel y aft e r the ris i ng or f a lling edge of th e last sclk (for rising or f a lling edge m ode , r e s p ect ivel y) sclk output mode im m e diatel y aft e r the ris i ng edg e of the l a s t s c lk (jus t aft e r d a ta trans f er to r e c e iv e buffe r 2) or jus t af ter re ceiv e bu ffer 2 is r ead interrupt gen e ration tim ing (wbuf = 1) sclk input mo de im m e diatel y aft e r the ris i ng edg e or fal ling edge o f the l a s t s c lk depending on th e rising or f a llin g edge tr iggerin g mode, respect ivel y (rig h t af ter dat a is moved to receiv e buffer 2) overrun error generation timin g sclk input mo de im m e diatel y aft e r the ris i ng or f a lling edge of th e last sclk (for rising or f a lling edge m ode , r e s p ect ivel y) t r an sm it sid e sclk output mode im m e diatel y aft e r the ris i ng edg e of the l a s t s c lk interrupt gen e ration tim ing (wbuf = 0) sclk input mo de im m e diatel y aft e r the ris i ng or f a lling edge of th e last sclk (for rising or f a lling edge m ode , r e s p ect ivel y) sclk output mode im m e diatel y aft e r the ris i ng edg e of the l a s t s c lk or jus t af ter data is moved to send buff e r 1 interrupt gen e ration tim ing (wbuf = 1) sclk input mo de im m e diatel y aft e r the ris i ng or f a lling edge of th e last sclk (for the r i sing or falling edge mode, r e sp ect ivel y) or j u s t aft e r d a ta is moved to send b u ffer 1 under-run error generation timin g sclk input mo de im m e diatel y aft e r the fa lling or r i sing edge of the next sclk (fo r the r i sing or falling edge tr iggering mode, r e spectively ) note 1) do no t modif y an y control regist er w h en dat a is being sen t o r receiv e d (in a st ate re ad y to send or receiv e ). note 2) do not stop the receiv e operation (b y setting sc0mo d 0 = "0") w h e n dat a is being receiv e d. note 3) do no t s t op the tran smit oper a tion (b y setting sc0mo d 1 = " 0 " ) w h e n dat a is being trans m itted. tmp19a43 (rev2.0) 13-21 serial chann el (sio)
tmp19a43 13.4 register description (only for channel 0) 7 6 5 4 3 2 1 0 bit sy mbol tb8 ctse rxe wu sm1 sm0 sc1 sc0 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 f u n c t i o n s e n d d a t a bit 8 handsha ke function control 0: di sable s c t s 1: e nable s c t s receive control 0: di sable s rece ption 1: e nable s rece ption wake-up function 0: disable 1: enable serial transfer m ode 00: i/o inte rface mode 01: 7-bit length uart mo de 10: 8-bit length uart mo de 11: 9-bit length uart mo de serial transfer clock (for ua rt) 00: timer tb0out 01: baud rat e generat or 10: internal f sy s /2 clock 11: exte rnal clock (sclk0 input ) sc0mod 0 (0xff ff_ f262) no te) in th e i/o in terface m o d e , th e serial co n t ro l reg i ster (sc0cr) is u s ed fo r clo ck li wakeup functio n 9-bit uart other mode 0 interrupt when rece ived 1 i nterrupt at rb8 =1 don' t care handshake fun c tion ( cts pin) en able 0 disable ( t ransmission is alway s allowed) 1 e nable note) with set to "0," se t each mod e registe r (sc0mod0, sc0 m od1 and sc0mo d 2 ) . then se t to "1." fig. 13-1 0 serial mo de control regi ster 0 (fo r sio0, sc0mod0) tmp19a43 (rev2.0) 13-22 serial chann el (sio)
tmp19a43 7 6 5 4 3 2 1 0 bit sy mbol i2s0 fdpx1 fdpx0 txe sint2 sint1 sint0 ? r e a d / w r i t e r / w r / w r / w r / w r / w r / w r / w r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 f u n c t i o n i d l e 0: stop 1: start transfer mode s e tting 00: tra n sfer proh ibited 01: half duplex (rx) 10: half duplex (tx) 11: full duplex transmit control 0: disable 1: enable interval time of continuous transmission 000: none 100: 8sclk 001: 1sclk 1 01:16sclk 010: 2sclk 1 10: 32sclk 011: 4sclk 1 11: 64sclk wr it e " 0 . " sc0mod 1 (0xff ff_ f265) fig. 13-1 1 s e rial mo de control regi ster 1 (fo r sio0, sc0mod1) : specifies the i n terval tim e of co nt i n uo us t r a n sm i ssi on whe n d o u b l e b u f f e r i n g or f i f o i s ena b l e d in the i/ o inte rface m ode. this pa ram e ter is inva lid for t h e uar t m o de or when an external cl ock i s use d . : th is b it en ables tran sm issi o n and is v a lid for all t h e trans f er m odes. if disabl ed while transm ission i s in progress , tra n sm issio n is inh i b ited o n ly after the c u rrent fram e of data is co m p leted for t r an sm issio n . : configures t h e tr ansfe r m ode in the i/o i n terface m ode. als o confi g ures the fifo if it is enable d. in th e ua r t m o d e , it is u s ed o n l y to sp ecify th e fifo con f i g uratio n. : specifies t h e idle m ode ope r ation. tmp19a43 (rev2.0) 13-23 serial chann el (sio)
tmp19a43 7 6 5 4 3 2 1 0 bit sy mbol tbemp rbfll txrun sblen drch g w buf swrst1 swrst0 r e a d / w r i t e r r / w a f t e r r e s e t 1 0 0 0 0 0 0 0 function send buffer empt y flag 0: full 1: empty receive buffer full flag 0: empty 1: full in transmissi on flag 0: stop 1: start stop bit 0: 1-bit 1: 2-bit setting transfer direction 0: lsb first 1: msb first w - buffer 0: disable 1: enable soft reset overwrite "01" o n "10" to reset sc0mod 2 (0xff ff_ f266) : ove r writing " 01" i n place of " 10" ge nerates a softwa re reset. whe n this soft ware reset is execute d, t h e m ode register param e ters sc0mo d 0 , sc0m od 1, sc 0 m od 2 , < rbfll>, and , contro l re gi ster param e ters sc0cr , , an d , an d th eir i n ternal circu its are in itialized . < w buf>: this pa ram e ter ena b les or dis a bles t h e se nd /receive buf f e r s to se nd (i n both sclk out put/input m odes) and re ceive (in sclk outp ut m ode) data in the i/o interface m ode and to tra n s m it data in th e ua r t . in all o t h e r m o d e s, dou b l e bu f f eri n g is en ab led reg a rdless of th e settin g . : specifies the direction of da ta tra n sfe r i n t h e i/o interface m ode . in t h e uar t m ode, it is fixe d to lsb first. : this is a status flag to s h ow th at d a ta t r ansmissio n is in p r og ress. w h en th is b it is set t o "1 ," it ind i cates t h at d a ta tran sm issi o n o p eration is in p r og ress. if it is "0 ," th e b it 7 is set to "1 " to ind i cate th at th e tran sm issio n h a s b een fu lly co m p le ted and the sam e is set to "0" t o i ndicat e that t h e send buf f e r contains s o m e data wai t i ng f o r t h e next t r ansm i ssion . : this is a flag to s h ow that the receive d ouble buf f e r s are full. when a receive operation is com p leted and receive d data is m oved from the receive shift re gister t o the receive double b u f f ers, th is b it ch an g e s to "1 " wh ile read ing th is b it ch ang e s it to "0 ." if do ub le b u f f ering is d i sab l ed, th is flag is in sig n i fican t . : this flag s h ows that the se nd do u b l e b u f fe rs are em pt y . w h en dat a i n t h e s e nd d o ubl e b u f f ers i s m o v e d to th e sen d sh ift reg i st er an d th e doub le b u f f ers are e m p t y , th is b it is set to "1 ." w r itin g d a ta ag ai n t o the do ub le b u f f ers sets th is b it to "0 ." if do ub le b u f f ering is d i sab l ed, th is flag is in sig n i fican t . : this s p ecifies the length of s t op bit tra n sm ission in the ua r t m ode. on t h e receive s i de, t h e d ecision is m a d e u s ing on ly a sing le b it reg a rd less of th e settin g. (no t e ) while dat a transmis sion is in pro gress, a n y sof t w a re r e set o p era t io n must b e execu ted t w i ce in succe s s ion. fig. 13-1 2 s e rial mo de control regi ster tmp19a43 (rev2.0) 13-24 serial chann el (sio)
tmp19a43 7 6 5 4 3 2 1 0 bit sy mbol rb8 even pe o e rr perr ferr sclks io c read/write r r/w r (cleared to "0" w h en rea d ) r/w a f t e r r e s e t 0 0 0 0 0 0 0 0 0: normal ope rati on 1: e rro r function receive data bit 8 par i ty 0: odd 1: even add parit y 0: disable 1: enable ov erru n p a ri t y / under-run framing 0: sclk0 1: sclk0 0: b aud rate g enera t or 1: scl k 0 p i n in put sc0cr (0xff ff_ f261) i/o int e rfa ce inp u t c l ock sele ctio n framing error f l ag parity error/und er-run error flag overrun error flag edge selection f o r sclk0 input operation add/check ev en parit y clear ed to "0" when re ad 0 data send /receiv e at r i sing edges of sclk0 1 data send /re ceiv e a t f a ll ing edges of sclk0 0 b aud rate generator 1 s clk0 pin inpu t 0 o dd parity 1 e ven p a rity (no t e ) an y error flag is cleared w h e n re ad. fig. 13-1 3 s e rial control regi ster (for sio0, sc0cr) tmp19a43 (rev2.0) 13-25 serial chann el (sio)
tmp19a43 7 6 5 4 3 2 1 0 bit symbol ? br0adde br0ck1 b r0ck0 b r 0 s 3 b r 0 s 2 b r 0 s 1 br0s0 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 function wr it e " 0 . " n+(16-k)/16 div i der function 0: disable 1: enable 00: t1 01: t4 10: t16 11: t64 divide ratio "n" br0cr (0xff ff_ f263) select inpu t clock to the baud rate gen e rator 00 internal clock t1 01 internal clock t4 10 internal clock t16 11 internal clock t64 7 6 5 4 3 2 1 0 bit symbol br0k3 br0k2 br0k1 br0k0 r e a d / w r i t e r r / w after reset 0 0 0 0 0 function alw a y s reads "0. " specify k fo r the "n + (16 - k)/16 " division setting d i vid e r a tio of the baud r a te gen e rator br0add (0xff ff_ f264) br0cr = 1 br0cr = 0 br0cr br0add 0000 (n = 16) 0001 (n = 1) 0010 (n = 2) 1111 (n = 15) 0001 ( n = 1) ( o nly ua rt) 1111 (n = 15) 0000 (n = 16) 0 0 0 0 d i s a b l e d i s a b l e 0001 (k = 1) 1111 (k = 15) disable n + 16 k) (16 ? divis i on divide b y n ~ ~ ~ ~ (no t e 1 ) in the uart m ode, the div i sion ratio "1" of the baud rate g e nera tor can be specified only w h e n the "n + (16 - k)/16" div i sion function is not used. in the i/o interfa ce mode , the div i sion ratio "1" of the baud rate ge nerator can be specified only w h en double buffe ring is used. (no t e 2 ) t o us e the " n + (1 6 - k)/16" div i sion func tion, be sure to s e t br0 cr to " 1 " af te r setting the k v a lue (k = 1 to 15) to br0add . ho w e v e r , don't use the "n + (16 - k)/16" div i sion function w h e n br0 c r is set to either "000 0" or "0001" (n = 16 o r 1). (no t e 3 ) the "n + (1 6 - k)/16" d i v i sion function can o n ly be used in the uart mode. in the i/o interface m ode, th e "n + (16 - k)/ 16" div i sion func tion m u st b e disabled (prohib i ted) b y set ting b r 0 cr t o "0." fig. 13-1 4 baud rate ge nerato r c ontrol (for sio0, br0cr, br0 a dd) tmp19a43 (rev2.0) 13-26 serial chann el (sio)
tmp19a43 7 6 5 4 3 2 1 0 bit symbol tb7/rb7 tb6/rb6 t b5/rb5 tb 4/rb4 t b3/rb3 t b 2 / r b 2 t b 1 / r b 1 tb0/rb0 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 function tb7 to tb0: se n d buffer + fif o rb7 to rb0: r e ceive buffer + fif o sc0buf (0xff ff_ f260) fig. 13-1 5 note: hsc0 buf w orks as a s e nd buffer for wr ope rati on and as a receiv e buffer for rd op eration. fig. 13-1 6 fi fo co nfigura t ion regi ster 7 6 5 4 3 2 1 0 bit symbol reserved reserved reser v e d r f s t t f i e r f i e rxtxcn t cnf g r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 function be sure to w r ite "000." by t e s used in rx fif o 0: max i mum 1: s a me a s fill lev e l o f r x f i f o tx interrupt for tx fif o 0: disable 1: enable rx interrupt for rx fif o 0: disable 1: enable automatic disable of rxe/txe 0: none 1: auto disable fif o enable 0: disable 1: enable sc0fcn f (0x f f ff_ f26c ) : if en ab led , t h e sco m od 1 settin g au to m a ticall y co nfigu r es fifo as fo llo ws: = 01 ( h alf duple x rx) -- -- 4- byte rx f i f o = 10 ( h al f d upl e x t x ) - - - - 4- by t e tx fif o = 1 1 ( f ul l du pl ex ) - - - - 2- byte rx fi fo + 2- byte t x fi fo : 0 t h e fu nct i o n t o aut o m a t i c al ly di sabl e r x e/ txe bi t s i s di s a bl ed. 1 : if en ab led , t h e sco m od1 is u s ed t o set as fo llo ws: = 0 1 (h alf du p l ex rx) ------ w h en th e rx fifo is filled u p t o th e sp ecified nu m b er o f v a lid b y tes, rx e is au to matically set to "0 " t o i n h i b i t furthe r rece pti o n. = 1 0 (h alf du p l ex tx ) -- -- -- w h en th e tx fifo is em p t y , tx e is au t o matical ly se t to "0 " to i n h i b it furth e r tran smissio n . = 1 1 (fu ll d u p l ex) ---- ------- w h en e ith er of th e abov e tw o con d ition s is satisfied , tx e/rx e are au to m a tical ly set to "0 " to inhib it furth e r tran sm issio n an d recep tion . : whe n rx fifo is enable d, receive interrupts are ena b led or disabled by this param e ter . : w h en tx fifo is enab led , tran sm it in terr u p t s are enabl e d or di sa bl ed by t h i s pa ram e t e r . : whe n rx fifo is enable d, t h e num ber of r x fi fo by t e s t o be use d i s sel ect e d . 0: the m a xim u m num ber of by t e s of t h e fi f o co n f i g ure d 4 by t e s whe n = 01 (h al f du pl ex rx ) a n d 2 by t e s f o r < f dp x 1 : 0 > = 1 1 (ful l d upl e x ) 1 : sam e as th e fill lev e l fo r recei v e in terru p t g e n e ration sp ecified b y sc0 r fc . (no t e 1 ) rega rding t x fifo, the maximum number of b y tes being con f igured is al w a y s av ailable. the av ailable number of b y tes is the b y tes already w r i t ten to the tx fifo. tmp19a43 (rev2.0) 13-27 serial chann el (sio)
tmp19a43 fig. 13-1 7 receive fifo control re gister 7 6 5 4 3 2 1 0 bit symbol rfcs rfis ril1 ril0 r e a d / w r i t e w r / w r r / w after reset 0 0 0 0 0 function clear rx fif o 1: clear alw a y s reads "0." select interrupt generation condition alw a y s reads "0. " fifo fill level to generate rx inte rrupts 00: 4 b y t e s (2 b y t e s if full duplex) 01: 1b y t e 10: 2b y t e 11: 3b y t e note: ril1 is ign o red w h en f d px1:0 = 11 (full duplex) sc0rfc (0xff ff_ f268) 0 : a n in terrup t is g e n e rated wh en th e sp ecified fill lev e l is reach e d. 1 : a n i n terrup t is g e n e rated wh en th e sp ecified fill lev e l is re ach e d or if t h e sp ecified fill level h a s b een ex ceed ed at th e ti m e d a ta is read . t r a n smit fif o config urati o n re giste r 7 6 5 4 3 2 1 0 bit symbol tfcs tfis til1 til0 r e a d / w r i t e w r / w r r / w after reset 0 0 0 0 0 function clear tx fif o 1: clear alw a y s reads "0." select interrupt generation condition alw a y s reads "0. " fifo fill level to generate tx inte rrupts 00: empt y 01: 1b y t e 10: 2b y t e 11: 3b y t e note: til 1 is ignored w h en f d px1:0 = 11 (full duplex). 0 : a n in terrup t is g e n e rated wh en th e sp ecified fill lev e l is reach e d. 1 : a n in terru p t is g e n e rated w h en t h e sp ecified fill lev e l is re ach e d o r if t h e l e v e l is l o w e r th an th e sp ecifi ed fill lev e l at th e ti m e n e w data is w r itten. fig. 13-1 8 re ceive fifo s t atus regi ster 7 6 5 4 3 2 1 0 bit symbol ror rlvl2 rlvl1 rlvl0 r e a d / w r i t e r r r after reset 0 0 0 0 0 function rx fif o ov erru n 1: gene rated alw a y s reads "0. " status of rx fifo fill level 000: empt y 001: 1b y t e 010: 2b y t e 011: 3b y t e 100: 4b y t e (no t e ) the bit is cleared to "0" w h en receiv e dat a is read from the sc0buf registe r . sc0rst (0x f f ff_ f26a) sc0tf c (0xff ff_ f269) tmp19a43 (rev2.0) 13-28 serial chann el (sio)
tmp19a43 fig. 13-1 9 t r ansmit fifo s t atus regist er 7 6 5 4 3 2 1 0 bit symbol tur tlvl2 tlvl1 tlvl0 r e a d / w r i t e r r r after reset 1 0 0 0 0 function tx fif o under run 1: gene rated cleared b y writing to fif o alw a y s reads "0. " status of tx fi fo fill level 000: empt y 001: 1b y t e 010: 2b y t e 011: 3b y t e 100: 4b y t e sc0tst (0x f f ff_ f26b) (no t e ) the bit is cleared to "0" w h en tran smit dat a is w r itten to the sc0 buf registe r . sio enable re gister 7 6 5 4 3 2 1 0 bit symbol sioe r e a d / w r i t e r r / w after reset 0 0 function alw a y s reads "0. " sio operation 0: disable 1: enable sc0en (0xff ff_ f267) < s ioe>: it specifies sio operation. when sio ope ration is disable d, the clock w ill not be supplied to the sio module exce pt for th e regis t er p a rt and thus po w e r dissip ation can be red u ced (o ther r e gister s can not be ac ce ssed for rea d / w r i te oper a tion). wh e n sio is to be used, be sur e to enable sio b y setting "1" to this register be fore se tting an y other registers of th e sio module. if sio is enabled onc e and then disabled, an y register setti ng is maint a ined. tmp19a43 (rev2.0) 13-29 serial chann el (sio)
tmp19a43 13.5 operation in each mode 13.5.1 mode 0 (i/o interface mode) mo d e 0 co n s i s ts o f two m o d e s, i.e., th e "sclk o u t p u t " m o d e to o u t pu t syn c h r o nous clo c k and the "sclk input" m ode to acce pt sync hronous clock from an external source. the follow i ng op erational descri ptions a r e for the case use of fi fo is disab l ed . fo r d e tails o f fifo op eration , refer to th e p r ev iou s sections desc ribing recei ve/transm it fifo functions . c sen d i n g dat a sclk o u t p ut m ode in t h e sc lk out put m ode, i f sc0m od 2< wbuf > i s set t o " 0 " a n d t h e se nd do u b l e bu f f e r s are di sabl e d , 8 bi t s of dat a are o u t put fr om t h e txd 0 pi n a nd t h e sy nc hr o n o u s cl ock i s out p u t fr om t h e sclk0 p i n each tim e th e cpu w r ites d a ta t o t h e send bu f f er . w h en all d a ta is ou tpu t , the in ttx 0 in terru p t is g e nerated . if sc 0mo d 2 < w bu f> i s se t t o "1" an d t h e sen d d o ubl e bu f f e r s a r e ena b l e d, dat a i s m ove d fr o m send b u f f er 2 t o send bu f f er 1 wh en t h e cpu writes d a ta to send b u f f er 2 w h ile d a ta t r ansmissio n is hal t e d or whe n dat a t r a n sm issi on f r om sen d b u f f er 1 (s hi ft re gi st er) i s com p l e t e d. when dat a i s m oved fr om send b u f f er 2 t o s e nd b u f f er 1, t h e se nd b u f f er em pt y fl ag sc0mo d 2 < t be mp> i s set t o "1 ," an d t h e in ttx 0 i n t e r r u p t i s ge ne rat e d. if sen d bu f f er 2 has no d a t a t o be m o v e d t o sen d bu f f e r 1, t h e i n tt x0 i n t e r r u p t i s not ge nera t e d an d t h e sc lk 0 out put st o p s. tr ansm i t da t a wr i t e t i m i n g s c lk 0 ou t put bi t 0 bi t 6 b i t 7 bi t 1 tx d 0 ( i n ttx 0 i n t e r r upt r eques t ) bi t 0 t x run < w bu f> = " 0 " (i f d o u b l e bu f f eri n g i s di sa bl ed) t r ansm i t da t a w r it e t i m i ng s c lk 0 ou t put bit 0 bit 6 b it 7 bit 1 tx d 0 ( i n t t x 0 i n t e rr up t r e q uest ) bit 0 t b run tbem p = "1" (if do ub le b u f f ering is en ab l e d ) (if th ere is d a ta in bu f f er 2) tmp19a43 (rev2.0) 13-30 serial chann el (sio)
tmp19a43 t r ansm i t da t a w r it e t i m i ng s c lk 0 ou t put bit 0 bit 6 b it 7 bit 1 tx d 0 ( i n t t x 0 i n t e rr up t r e q uest ) t b run tbem p < w bu f> = " 1 " (i f d o u b l e bu f f eri n g i s ena b l e d) (i f t h ere i s no dat a i n bu f f er 2) fig. 13-2 0 s end op eratio n in the i/o in terface m ode (sclk0 outp ut mode) sclk i n p u t m ode in th e sclk i n pu t m o d e , if sc0 m od2 i s s e t t o " 0 " a n d t h e sen d d o ubl e bu f f e r s are d i sab l ed , 8 - b it d a ta th at h a s been w r itten in th e send bu f f er is ou tpu t fro m th e tx d0 p i n wh en t h e sclk0 inpu t b eco m e s activ e. w h en all 8 b its are sen t , th e in ttx0 i n terrup t is g e n e rated . th e n e x t send d a ta m u st b e w r itten b e fo re th e ti min g po in t "a" as sh own in fig . 13 -21 . if sc 0mo d 2 < w bu f> i s se t t o "1" an d t h e sen d d o ubl e bu f f e r s a r e ena b l e d, dat a i s m ove d fr o m sen d bu f f e r 2 t o se nd bu f f e r 1 w h e n t h e cpu wri t e s d a t a t o se n d bu f f e r 2 bef o re t h e sclk 0 becom e s act i v e or w h e n dat a t r ansm i ssi on f r om send b u f f e r 1 (s hi ft re gi st er) i s c o m p l e t e d. as dat a is m o v e d fro m send buf fer 2 to send b u f f er 1 , the se nd buf fer em pty flag sc0mod2 is set to "1 " and t h e inttx0 in t e rru p t is g e n e rated . if th e sclk0 inpu t b e co m e s activ e wh ile no d a ta i s i n sen d b u f f er 2, al t h o u gh t h e i n t e r n al bi t cou n t e r i s st ar t e d, an u nde r - r un e r r o r occ u r s and 8 - bi t dum m y dat a (f fh) i s se nt . s c lk 0 i nput ( < scl ks>=0 (< s c lk s > = 0 , ri si ng edg e m ode) s c lk 0 i nput ( < scl ks>=1 , fal l i ng edge m ode) bit 0 bit 1 tx d 0 (in t t x 0 i n t e rru pt re quest) bit 5 b it 6 bit 7 t r ansm i t data w r i t e t i m i ng bit 0 bit 1 a < w bu f> = " 0 " (i f d o u b l e bu f f eri n g i s di sa bl ed) tmp19a43 (rev2.0) 13-31 serial chann el (sio)
tmp19a43 s c lk 0 i nput ( < scl ks>=0 , ri s i n g edge m ode) s c lk 0 i nput ( < scl ks>=1 f al l i ng edge m ode) bit 0 bit 1 tx d 0 (in t t x 0 i n t e rru pt re quest) bit 5 b it 6 bit 7 t r ansm i t data w r i t e t i m i ng bit 0 bit 1 a t b run tbem p = "1" (if do ub le b u f f ering is en ab l e d ) (if th ere is d a ta in bu f f er 2) s c lk 0 i nput ( < scl ks>=0 ri s i n g edge m ode) s c lk 0 i nput ( < scl ks>=1 f al l i ng edge m ode) bi t 0 bi t 1 tx d 0 (in t t x 0 i n t e rru pt re quest) bi t 5 b i t 6 bi t 7 t r ansm i t data w r i t e t i m i ng 1 a t b run tbem p p e r r (functi ons to det ect und er- r un e rro rs) < w bu f> = " 1 " (i f d o u b l e bu f f eri n g i s ena b l e d) (i f t h ere i s no dat a i n bu f f er 2) fig. 13-2 1 s end op eratio n in the i/o in terface m o de (sclk0 inp u t mode) tmp19a43 (rev2.0) 13-32 serial chann el (sio)
tmp19a43 d receiving data sclk o u t p ut m ode in t h e sclk output m ode, if sc0mod2 < w buf> = " 0 " and recei ve double buf f e r ing is disable d , a sync hronous clock pulse is out put from the sclk0 pin and the next data is s h ifted i n to recei ve buf f e r 1 each tim e the cpu reads receive d data. whe n a ll the 8 bits are receive d, the intr x0 in terru p t is g e nerated . the first sclk output ca n be started by set ting t h e receive ena b le bit sc0mod0 to " 1 ." if the receive double buf f ering is enable d with sc0mod2 < w buf> set to "1," the first frame receive d is m oved to receive buf f e r 2 a n d re ceive buf f e r 1 can receive the ne xt fram e successively . as data is m o ved from receive buf fe r 1 to re ceive buf f e r 2, the recei ve buf fe r full flag sc0mod2 is set to "1 " an d th e in trx0 in t e rru p t is g e n e rated . while data is in recei ve buf fer 2, if cpu/dmac ca nnot read data from receive buf f er 2 i n tim e before com p leting reception of t h e ne xt 8 bits, the intr x0 interrupt i s not ge ne rated a n d the sclk0 cloc k stops . in this st ate, re a d ing da ta from receive buf f er 2 allows data i n receive buf f er 1 to m o v e to receiv e bu f f er 2 an d thu s th e intrx 0 in terrupt is g e n e rated an d d a ta recep tio n resu m e s. r e cei v e data w r i t e t i m i ng s c lk 0 ou t put bi t 0 bi t 6 b i t 7 bi t 1 rx d 0 (i nt rx 0 i n t e rrupt reques t ) bi t 0 < w bu f> = " 0 " (i f d o u b l e bu f f eri n g i s di sa bl ed) re ce iv e d a t a r e ad t i mi ng s c lk 0 ou t put bit 0 bit 6 b it 7 bit 1 rx d 0 (in t r x 0 i n ter r upt reques t) bit 0 bit 7 rb f u ll < w bu f> = " 1 " (i f d o u b l e bu f f eri n g i s ena b l e d) (i f dat a i s r ead fr om buf fe r 2) tmp19a43 (rev2.0) 13-33 serial chann el (sio)
tmp19a43 re ce iv e d a t a r e ad t i mi ng s c lk 0 ou t put bit 0 bit 6 b it 7 bit 1 rx d 0 (in t r x 0 i n ter r upt reques t) bit 7 rb f u ll < w bu f> = " 1 " (i f d o u b l e bu f f eri n g i s ena b l e d) (i f dat a ca n not be rea d f r o m buf fe r 2) fig. 13-2 2 receive o pera t ion in the i/o interface mo de (sclk0 o u tput mode ) sclk i n p u t m ode in the sclk i n put m ode, since receive double buf fe ring i s always e n a b led, t h e receive d fram e can be m oved to re ceive buf fe r 2 and recei ve buf f e r 1 ca n re ceive the ne xt fra me successivel y . the intrx re ceive interrupt is ge nerated ea ch tim e received data is m ove d to recei ved buf f er 2. s c lk 0 i npu t ( < sc l ks> = 0 ri s i ng edge m ode) s c lk 0 i npu t ( < sc l ks> = 1 f a l l i ng edge m ode) bi t 0 bi t 1 rx d 0 ( i n t r x 0 i n te rru pt re que st) bi t 5 b i t 6 bi t 7 rec e i v e dat a read t i m i ng bi t 0 rb full if dat a i s read f r om bu f f e r 2 s c lk 0 i npu t ( < sc l ks> = 0 ri s i ng edge m ode) s c lk 0 i npu t ( < sc l ks> = 1 f al l i ng edge m ode) bi t 0 bi t 1 rx d 0 ( i n t r x 0 i n te rru pt re que st) bi t 5 b i t 6 bi t 7 rec e i v e dat a read t i m i ng bi t 0 rb full oe rr if dat a ca nn ot be read f r om b u f f er 2 fig. 13-2 3 re ceive op erati on in the i/o interface mod e (sclk0 inp u t mode) (no t e ) t o receiv e d a t a , sc0mo d must al w a y s be set to "1 " (receiv e e n able) rega r d less of the scl k in put or ou tpu t mode. tmp19a43 (rev2.0) 13-34 serial chann el (sio)
tmp19a43 e send a n d recei ve (full-duplex) th e fu ll-d u p l ex m o d e is en ab led b y settin g b it 6 o f t h e serial m o d e con t ro l reg i ster 1 (sc0m o d1) t o " 1 ." sclk o u t p ut m ode in t h e sclk out put m ode, i f sc0m od2 < w buf> is s e t to "0" a nd bot h the se nd and receive d oub le bu f f ers are d i sab l ed , sclk is ou tp u t wh en t h e cpu w r ites d a ta to t h e sen d bu f f er . subseque ntly , 8 bits of data are shi f ted int o recei ve buf f e r 1 a n d the intrx0 receive interrupt is g e n e rated. co ncu r ren tly , 8 b its of d a ta w r itten to th e send bu f f er are ou tput fro m th e txd 0 p i n , t h e in ttx0 send in terru p t is g e n e rated wh en t r an sm issio n of all d a ta b its has b een co m p l e ted . th en , t h e scl k o u t put st op s. in t h i s , t h e ne xt r o u n d of dat a t r ansm i ssi on an d rece pt i o n st a r t s w h e n t h e d a ta is read from th e receiv e b u f f er and th e n e x t send d a ta is w r itten to t h e send bu f f er by th e cpu . the orde r of reading t h e rec e ive buf f e r and writi ng to the se nd buf fe r can be freely determ ined. d a ta tran sm iss i o n is resu m e d o n l y w h en bo th co nd itio ns are satisfied . if sc0m o d 2 < w bu f> = "1 " an d d o ubl e b u f f eri n g i s e n a b l e d f o r bot h t r ansm i ssi on a n d rece pt i o n , sclk is ou tpu t wh en th e cpu w r ites d a ta to th e sen d bu f f e r . s ubse q uent l y , 8 bi t s of dat a a r e sh ifted in to receiv e buf fer 1 , m o v e d to receiv e buf fer 2 , an d th e in trx 0 in terrup t is g e n e rated . while 8 bits of data is receive d, 8 bits of t r a n sm it data is output from the txd0 pin. when all data b its are sen t ou t, t h e in ttx0 i n terrup t is g e ne rat e d a n d t h e next dat a i s m oved f r o m t h e se nd bu f f e r 2 t o s e n d b u f fe r 1. i f s e nd b u f f er 2 h a s n o dat a t o b e m oved t o se nd b u f f er 1 (s c0mo d2 = 1) or whe n rece ive buf f er 2 is fu ll (sc 0 mod2 = 1), the sclk cloc k is sto p p e d . w h en b o t h cond itio n s are satisfied, i.e., r ecei v e data is read and sen d d a ta is written , th e sclk o u t p ut i s res u m e d an d t h e ne xt ro u n d of dat a t r a n sm issi on i s st art e d. rec e ive dat a read t i m i ng s c lk 0 ou t put bit 0 bit 6 b it 7 bit 1 tx d 0 (i nt t x 0 int e rrupt reques t ) bit 0 t r ansm i t da t a w r i te ti m i n g (i nt rx 0 int e rrupt reques t ) bit 5 bit 1 bit 0 bit 6 b it 7 bit 1 rx d 0 bit 0 bit 5 bit 1 < w bu f> = " 0 " (i f d o u b l e bu f f eri n g i s di sa bl ed) tmp19a43 (rev2.0) 13-35 serial chann el (sio)
tmp19a43 rec e ive dat a read t i m i ng s c lk 0 ou t put bit 0 bit 6 b it 7 bit 1 tx d 0 ( i n t t x 0 i n t e rr up t r e q uest ) bit 0 t r ansm i t da t a w r i te ti m i n g ( i n t r x 0 i n te rru pt re que st) bit 5 bit 1 bit 0 bit 6 b it 7 bit 1 rx d 0 bit 0 bit 5 bit 1 = "1" (if do ub le b u f f ering is en ab l e d ) rec e ive dat a read t i m i ng s c lk 0 ou t p u t bit 0 bit 6 b it 7 bit 1 tx d 0 ( i n t t x 0 i n t e rr up t r e q uest ) t r ansm i t da t a w r i te ti m i n g ( i n t r x 0 i n te rru pt re que st) bit 5 bit 0 bit 6 b it 7 bit 1 rx d 0 bit 5 = "1" (if do ub le b u f f ering is en ab l e d ) fig. 13-2 4 s end/receive operation in the i/o in terface mod e (sclk0 output mode ) sclk i n p u t m ode in t h e sclk i n pu t m o d e w i t h sc0 m od 2 set to "0 " and th e send d oub le b u f f ers are d i sab l ed (d ouble b u f f ering is alw a ys en ab led fo r t h e recei v e sid e ), 8 - b it d a ta written in th e send buf f e r is out put from the txd0 pin and 8 bits of data is shifted int o t h e recei ve buf f e r whe n the sclk i n pu t b eco m e s activ e. th e in ttx 0 in terrup t i s g e n e rated up on co m p letio n o f d a ta tran sm issio n an d t h e in trx0 i n terrup t is gen e rated at th e in stan t t h e receiv ed d a ta is m o v e d fro m receiv e b u f f er 1 to recei v e bu f f er 2 . n o te t h at tran sm it d a ta m u st b e written in to th e send bu f f e r b e fo re t h e sclk inpu t fo r t h e n e x t fram e (d ata m u st b e w r itten b e fo re th e po in t a in fig . 1 3 -2 5). as double buf f ering is e n a b led for data rece ption, data m u st be rea d before c o m p leting reception of t h e ne xt fram e dat a . if sc0m o d 2 < w bu f> = "1 " an d d o ubl e b u f f eri n g i s e n a b l e d f o r bot h t r ansm i ssi on a n d rece pt i o n , th e i n terrup t in trx0 is g e nerated at t h e ti min g se nd bu f f er 2 d a ta is m o v e d to send buf fer 1 afte r com p leting data tra n sm ission from se nd buf f er 1. at the s a m e tim e , the 8 bits of data received is shifted t o buf f er 1, m ove d to receive buf fe r 2, and the intrx0 i n terrupt is generate d. upon t h e sclk i n put f o r t h e next f r a m e, t r ansm i ssion f r o m send bu f f e r 1 (i n w h i c h dat a ha s been m oved from send buf f er 2) is started while receive data is shi f ted into receive buf f e r 1 sim u ltaneously . if data in recei ve buf f er 2 has not bee n rea d whe n the last bit of t h e fram e is receive d, an overrun tmp19a43 (rev2.0) 13-36 serial chann el (sio)
tmp19a43 erro r o c cu rs. si m i larly , if th ere is no d a ta w r itten to sen d bu f f er 2 wh en sclk for th e n e x t fram e is i n p u t , a n un de r - r u n er ro r occ u rs. rec e ive dat a read t i m i ng s c lk 0 inpu t bit 0 bit 6 b it 7 bit 1 tx d 0 ( i n t t x 0 i n t e rr up t r e q uest ) bit 0 t r ansm i t da t a w r i te ti m i n g ( i n t r x 0 i n te rru pt re que st) bit 5 bit 1 bit 0 bit 6 b it 7 bit 1 rx d 0 bit 0 bit 5 bit 1 a < w bu f> = " 0 " (i f d o u b l e bu f f eri n g i s di sa bl ed) rec e i v e dat a read t i m i ng s c lk 0 i npu t b i t 0 b it 6 b it 7 bi t 1 tx d 0 ( i n t t x 0 i n t e rr up t r e q uest ) bi t 0 transm i t da t a w r i te ti m i n g ( i n t r x 0 i n te rru pt re que st) bi t 5 bi t 1 b i t 0 b it 6 b it 7 bi t 1 rx d 0 bi t 0 bi t 5 bi t 1 < w buf> = " 1 " (if double buf f ering is ena b l e d) (no errors ) tmp19a43 (rev2.0) 13-37 serial chann el (sio)
tmp19a43 rec e i v e dat a read t i m i ng s c lk 0 i npu t b i t 0 b it 6 b it 7 bi t 1 tx d 0 ( i n t t x 0 i n t e rr up t r e q uest ) bi t 0 transm i t da t a w r i te ti m i n g ( i n t r x 0 i n te rru pt re que st) bi t 5 bi t 1 b i t 0 b it 6 b it 7 bi t 1 rx d 0 bi t 0 bi t 5 bi t 1 p e rr (under-run error) < w bu f> = " 1 " (i f d o u b l e bu f f eri n g i s ena b l e d) (e rr or ge ne rat i o n ) fig. 13-2 5 s end/receive operation in the i/o in terface mod e (sclk0 input mo de) tmp19a43 (rev2.0) 13-38 serial chann el (sio)
tmp19a43 13.5.2 mode 1 (7-bit uart mo de) the 7 - bi t uar t m ode ca n be sel ect ed by set t i ng t h e se ri al m ode co nt rol r e gi st er (sc 0 mod ) to "01." in t h is m o d e , p a rity b its can b e add e d to t h e tran sm it d a ta stream; th e serial m o d e co n t ro l reg i ster (sc0 cr ) co n t ro ls t h e parity en ab le/d i s ab le settin g. w h en is set to "1 " (en a b l e), eith er ev en or od d pari t y m a y be sel ect ed usi ng t h e sc 0cr bi t . the l e n g t h of t h e st op bi t can be s p eci fi e d usi n g sc 0mo d 2< sble n>. ex am p l e: th e con t ro l reg i ster setting s for tran sm itt in g in th e fo llow i ng d a ta format are listed in th e fo llow i ng tab l e. t r ansm i ss i o n di rect i on (t ransm i ss i o n ra t e of 2400bp s , @ f c =24 . 576m hz) s t art bi t 0 1 2 3 5 4 6 even pa r i t y s t op * clocking con d iti ons sy ste m clock : high- speed ( f c) high- speed clock gear : x 1 ( f c) prescale r clock : f peri ph /4 (f peri ph = f sy s ) 7 6 5 4 3 2 1 0 p6cr ? ? ? ? ? ? ? 1 p6fc ? ? ? ? ? ? ? 1 designates p60 as the txd0 pin. p6fc2 ? ? ? ? ? ? ? 1 sc0mod x 0 ? x 0 1 0 1 sets the 7-bit u a r t m ode. sc0cr x 1 1 x x x 0 0 adds even parity . br0cr 0 0 1 0 1 0 1 0 sets the data r a te to 2400 b p s. imc4 ? 1 1 x 0 1 0 0 enables the intt x0 interrupt a nd s e ts to level 4 by th e <31:24> bits of the 32 bit r e gister . sc0buf * * * * * * * * sets the data to be sent. note: x: don't car e - : no change tmp19a43 (rev2.0) 13-39 serial chann el (sio)
tmp19a43 13.5.3 mode 2 (8-bit uart mo de) the 8- bi t u a r t m ode can be sel ect ed by set t i ng sc 0mo d 0 t o "10 . " i n t h i s m ode , pa ri t y bi t s can be a d ded and pa ri t y enabl e / d i s abl e i s cont rol l e d usi n g sc0cr

. if < p e> = "1" (e nabl e d ) , either e v en or odd pa rity can be selected usi n g sc0cr . ex am p l e: th e con t ro l reg i ster setting s fo r receiv i n g data in th e fo llo win g fo rm at are as fo llo ws: t r ansm i ss i o n di rect i on (t ransm i ss i on ra t e of 9600bp s , @ f c =24 . 576m hz) s t art bi t 0 1 2 3 5 4 6 odd pa r i t y s t op 7 * clocking con d iti ons sy ste m clock : high- speed ( f c) high- speed clock gear : x 1 ( f c) prescale r clock : f peri p h/4 ( f peri ph = f sy s ) main ro u tin e settin g s 7 6 5 4 3 2 1 0 p6cr ? ? ? ? ? ? 0 ? p6fc ? ? ? ? ? ? 1 ? designates p62 as the rxd0 pin. p6fc2 ? ? ? ? ? ? 1 ? sc0mod ? 0 0 x 1 0 0 1 selects the 8-bit u a r t m ode. sc0cr x 0 1 x x x 0 0 sets odd par ity . br0cr 0 0 0 1 0 1 0 1 sets the data r a te to 9600 b p s. imc4 ? 1 1 x 0 1 0 0 enables the intr x0 interrupt a nd sets to level 4 by th e <23:16> bits of the 32 bit r e gister . sc0mod ? ? 1 x ? ? ? ? enables reception of data. an exam ple interrupt routine process intclr x 1 0 0 1 0 0 0 clear s the interr upt r e quest. 0x0000_ 0048 reg. s c0c r and 0x1 c if r e g. is not " 0 " then er r o r pr ocessing set sc0buf to re g. reads received dat a . i n ter r upt pr ocessing is co m p leted note: x: don't car e - : no change interrup t process complete perf o r m s e rro r ch e c k intclr= 0x48 interrup t process st art no ye s sc0buf da t a re ad sc0cr=0 x 1c ? e rror processing tmp19a43 (rev2.0) 13-40 serial chann el (sio)
tmp19a43 13.5.4 mode 3 (9-bit uart) the 9 - bi t u a r t m ode ca n be sel ect ed by set t i ng sc0m od 0 < s m1: 0 > t o "1 1 . " i n t h i s m ode , pa ri t y bi t s m u st be di sabl ed (sc0cr < p e> = " 0 "). th e m o st significan t b it (9 t h b it) is w r itten to b it 7 o f th e serial m o d e co n t ro l reg i ster 0 (sc0 mo d0) fo r t r an sm it d a ta and it is stored in b it 7 of t h e se rial cont rol regis t er sc0cr upon receiv i ng d a ta. w h en w r iting or read ing d a ta to /fro m th e bu f f ers, th e m o st sig n i fican t b it m u st b e w r itten o r read first b e fore writin g o r read i n g t o /fro m sc 0 b uf . th e stop b it leng th can b e sp ecifie d usi n g sc 0mo d 2 . w a keu p f unct i on in t h e 9- bi t u a r t m ode, sl a v e c o nt r o l l e rs can be o p e r at ed i n t h e wa ke- u p m ode by se t t i ng t h e wake - u p fun c tion con t ro l b it sc0 m od 0 to "1 ." in th is case, th e in terrup t in trx0 w ill b e g e n e rated o n l y whe n sc0cr is set t o " 1 ." r xd rxd t x d t xd rxd r x d t x d slave 3 slave 2 slave 1 master txd (no t e ) the txd pin of the slav e controller must be se t to the open drain outpu t mode usin g the ode regis t er . fig. 13-2 6 s e rial lin k s to use w a ke -u p function tmp19a43 (rev2.0) 13-41 serial chann el (sio)
tmp19a43 prot oc ol c select th e 9 - b it ua r t m o d e fo r the m a ster and slave controllers. d set sc0m od < w u> to " 1 " for the sla v e c o ntro llers to m a ke them ready to recei ve data. e th e m a ster con t ro ller is to sen d a sing le frame o f d a ta th at in clud es th e sl ave c o ntroller select code (8 b its). in t h is, th e m o st sig n i fican t b it (b it 8) m u st b e set t o "1 ." s l ave c o n t roller s e lect c ode s t art bit 0 1 2 3 5 4 6 s t op 7 8 "1 " f every sla v e c ont roller recei ves the above data fram e; if the c o de re ceived m a tches with t h e co n t ro ller's own select co d e , i t clears th e w u b it to "0 ." g th e m a ster con t ro ller transmits d a ta to th e d e si g n at ed sl ave c ont r o l l e r (t he c ont rol l e r of w h i c h sc0 m od b it is cleared t o "0 "). in th is, th e m o st sig n i fican t b it (bit 8 ) mu st b e set t o "0." dat a "0 " s t art bit 0 1 2 3 5 4 6 s t op 7 bit 8 h the slave c o ntrollers with t h e < w u> bit set t o " 1 " ignore the recei ve data beca use the m o st sig n i fican t b it (b it 8) is set to "0 " a nd th us n o in terrup t (intrx0 ) is g e n e rated . a l so , th e slav e con t ro ller w ith the b i t set to "0 " can tran sm it d a ta to the m a ster con t ro ller to inform that the data has bee n success f ully re ceived. ex am p l e settin g : u s ing th e in tern al clo c k f sys /2 as the t r ans f er cl ock, two slave c ontrollers are serially lin k e d as fo llo ws: master slave 1 slave 2 select code 00000001 r x d t x d r xd txd r x d select code 00001010 txd tmp19a43 (rev2.0) 13-42 serial chann el (sio)
tmp19a43 3) master con t ro ller settin g main routine p6cr ? ? ? ? ? ? 0 1 p6fc ? ? ? ? ? ? 1 1 designates p60/p61 as the t xd0/rxd0 pins, r e spectively . p6fc2 ? ? ? ? ? ? 1 1 imcc4 ? 1 1 ? 0 1 0 1 e n ables the i n t r x0 inter r upt and sets to level 5 by the <23:16> bits of the 32 bit r e gister . imcc4 ? 1 1 ? 0 1 0 0 e n ables the i n t t x0 inter r upt and sets to level 4 by the <31:24> bits of the 32 bit r e gister . sc0mod 0 1 0 1 0 1 1 1 0 sets the 9-bit u a r t m ode and f sys /2 transf er clock. sc0buf 0 0 0 0 0 0 0 1 sets the select code of slave 1. interrup t routine (int tx0) intclr x 1 0 0 1 1 0 0 clear s the interr upt r e quest. (i nt t x 0) sc0mod 0 0 ? ? ? ? ? ? ? sets tb8 to "0. " sc0buf * * * * * * * * sets the data to be sent. interrup t processing is completed. 4) slav e co n t ro ller settin g main routine p6cr ? ? ? ? ? ? 0 1 p6fc ? ? ? ? ? ? 1 1 designates p60 as t xd ( open dr ain output) and p61 as rxd. p6fc2 ? ? ? ? ? ? 1 1 p6o d e ? ? ? ? ? ? 1 ? imc4 ? ? 1 1 0 1 1 0 en ab les in ttx0 a n d intrx0 . imc4 ? ? 1 1 0 1 0 1 sc0mod 0 0 0 1 1 1 1 1 0 sets the 9-bit u a r t m ode and f sys /2 transf er clock and sets to "1 ." interrup t routine (intrx0 ) intclr 0 1 0 0 1 0 0 0 clears the interrupt request. reg. sc0buf if reg. = select code, then sc0mod 0 ? ? ? 0 ? ? ? ? clears < w u> to " 0 ." tmp19a43 (rev2.0) 13-43 serial chann el (sio)
tmp19a43 14. serial channel (hsio) thi s devi ce ha s t h ree hi g h -s peed seri al i/ o c h an nel s : hsio0 to hsio2 . each ch annel o p e rates i n eith er th e uar t m ode ( a sy nch r o n o u s com m uni cat i on) or t h e i/ o i n t e rface m ode (sy n c h r o no us c o m m uni cat i on) w h i c h i s selected by t h e use r . i/o i n terface mode mode 0: this is t h e m ode to se nd and receive i/o dat a and ass o ciate d syn c hron ization si g n a ls (hsc lk) to ex tend i/o. m ode 1: tx/ r x dat a l e ngt h: 7 bi t s asy n c h r o no us (u ar t) m ode: m ode 2: tx/ r x dat a l e ngt h: 8 bi t s m ode 3: tx/ r x dat a l e ngt h: 9 bi t s in t h e a b ove m odes 1 a n d 2 , pa ri t y bi t s ca n be a dde d. t h e m ode 3 has a wa ke up f u n c t i on i n w h i c h t h e m a st er co n t ro ller can start up slav e co n t ro llers v i a th e serial lin k (m u lti-co n t ro l l er system ). fi g . 14-2 sh ows th e b l o c k di ag ram of h s io 0. each cha n nel c onsists of a pre s caler , a serial clock ge ne ra tio n circu it, a receiv e b u f f er and its con t ro l circu it, and a sen d b u f f er a n d i t s co nt r o l c i rcui t . eac h c h annel f unct i o ns i nde pe nde nt l y . as the hsios 0 to 2 op erate in th e sam e way , on ly hsio0 is d e scrib e d h e re. bi t 0 1 2 3 45 6 sta r t s to p bi t 0 1 2 3 45 6 sta r t s to p pari t y bi t 0 1 2 3 45 6 bi t 0 1 2 3 45 6 sta r t s to p s t art s t op pari t y 77 7 bi t 0 1 2 3 45 6 sta r t 8 7 s t op bi t 0 1 2 3 45 6 s t art s t op (w ak e-up) bi t 8 7 i f b i t 8 =1, repres ent s address (s e l ec t c ode). i f b i t 8 =0, repres ent s da t a . z m ode 0 (i / o i n t e rf ac e m ode)/ m s b f i rst t r ansm i ss i on di re c t i o n z m ode 1 (7-bi t u a rt m ode) z m ode 2 (8-bi t u a rt m ode) z m ode 3 (9-bi t u a rt m ode) w i t hout pari t y w i t h pari t y w i t hout pari t y w i t h pari t y 0 bi t 7 6 5 4 32 1 z m ode 0 (i / o i n t e rf ac e m ode)/ l s b f i r s t t r ansm i ss i on di re c t i o n 7 bi t 0 1 2 3 45 6 fig. 14-1 dat a form at tmp19a43 (rev2.0) 14-1 serial chann el (hsio )
tmp19a43 hsc0mod0 uart mode tb8o ut (from tmrb0) hbr0cr hbr0add selector selector divider hbr0cr i/o interface mo d e 2 selector i/o interface mo d e hsc0cr hsc0mod0 receive counter ( 16 onl y w i th uart) serial channel interrupt cont rol transmit counter ( 16 onl y w i th uart ) transmit control receive control receiv e buffer 1 ( s hift regi ster) rb8 recei v e buffer 2 (hs c 0buf) error fl ag hsc0mod0 tb8 send bu ffer 2 (hsc 0buf) interrup t requ est hintrx0 internal data b u s hsc0cr htxd0 (shares pb2) hcts0 (shares pb4) internal data b u s interrup t requ est hinttx 0 hsc0mod0 hrxd0 (shares pb3) hsc0cr htxdclk hsc0mod0 parit y control internal data b u s fif o control hsioclk rxdclk hsclk0 input (shares pb4) send buffer 1 (sh i ft register) baud rate generato r serial clock gene ration circuit fif o control f sy s hsclk0 output ( shares pb4 ) fig. 14-2 hsio0 block dia g ram note: the baud ra te genera tor canno t be se t for "div ide b y 1." tmp19a43 (rev2.0) 14-2 serial chann el (hsio )
tmp19a43 14.1 operation of each circuit (hsio channel 0) 14.1.1 baud rate generator the ba ud rate gene rator ge ne rates tra n sm it and recei ve cl ocks to determine the serial c h annel tra n s f er rate. the ba ud rat e gene rat o r uses t h e sy s/ 2 cl ock . th e b a u d rate g e n e rator con t ain s b u ilt-in d i v i d e rs for d i v i d e b y 1 , (n + m / 1 6 ) , and 64 wh ere n is a num ber from 2 t o 63 a n d m is a num b er from 0 t o 15. the divisi on i s pe rform e d according t o t h e set t i ngs o f t h e ba u d rat e c ont rol re gi st er s hbr0 cr an d hbr0add t o d e term in e th e resu lting tran sfer rate. uar t m o de: 1 ) if hbr0 cr = 0 , the set t i ng of hb r 0 ad d < b r 0 k 3 : 0 > i s i g n o r ed a nd t h e cou n t e r i s di vi ded by n whe r e n i s th e v a l u e set t o hbr0 cr . (n = 1 t o 6 4 ). 2 ) if hbr0 cr = 1 , the n + ( 1 6 - k)/ 1 6 di vi si on fu nct i o n i s e n a b l e d a n d t h e di vi si o n i s m a de by u s i n g t h e v a l u es n (set in hbr 0 cr ) and k (set in hbr0add). (n = 2 t o 63 , k = 1 to 15 ) note for the n v a lues of 1 and 16, the abov e n+(1 6-k)/16 div i sion function is inhibited. so, be sure to set hbr 0cr < br 0a dd e> t o "0." i/o i n terface m ode: the n + (16 - k)/16 di vision function ca nnot be use d in the i/o interface m ode. be sure t o di vi de by n, b y set t i ng hb r 0 c r t o " 0 ." b a ud rat e cal c u l a t i on t o use t h e bau d rat e ge nerat o r: 1) uar t m ode bau d rate = ratio divide by the divided frequency fsys /16 th e h i gh est b a u d r a te ou t of t h e b a ud r a te g e n e r a t o r is 2.5 mb p s wh en fsys is 40 mh z. tmp19a43 (rev2.0) 14-3 serial chann el (hsio )
tmp19a43 2) i/ o i n t e rface m ode bau d rate = ratio divide by the divided frequency fsys /2 th e h i gh est b a u d rate will b e g e n e rated wh en fsys is 40 mhz. if d oub le b u f f ering is u s ed , th e d i v i d e ratio can b e set to "2 " and th e resu ltin g ou tpu t b a ud rate will b e 1 0 mbp s . (if do ub le b u f f ering is not u s ed , t h e h i ghest b a u d rate will b e 5 m b p s ap p l ying th e d i vid e ratio of "2 .") exam pl e bau d rat e set t i ng: 1) di vi si o n by a n i n t e ger ( d i v i d e by n ) : using t h e b a ud rate gen e rat o r inp u t clo c k sys, settin g th e d i v i d e ratio n (hbr0 cr
) = 4 , an d setting hbr0 cr = "0 ," t h e resu ltin g b a u d rate in th e uart m o d e is calcu lated as fo llows: * c l oc ki n g c o n d i t i ons sy st em cl ock : hi g h -s pee d (fc ) hi g h s p ee d cl o c k gear : x 1 (fc ) bau d rate = 4 fsys / 16 = 40 10 6 / 4 / 16 = 62 5 k (bp s ) (no t e ) the div i de b y (n + (16-k)/16) func tion is inhibited and thus hbr0 a dd is ignored. 2) for di vi de by n + (1 6 - k ) / 1 6 (o nl y f o r u a r t m ode): using t h e b a ud rate g e n e rat o r fsys, setting t h e d i v i d e ratio n (hbr0cr) = 4, set t i ng k ( h b r 0 a dd ) = 14 , an d sel ect i n g hb r 0 c r < b r 3 a d d e > = 1, t h e resu lting b a ud rate is calcu lat e d as fo llo ws: * c l oc ki n g c o n d i t i ons sy st em cl ock : hi g h -s pee d (fc ) hi g h -s pee d cl o c k gear : x 1 (fc ) bau d rate = 16 14) (16 4 fsys ? + /16 = 40 10 6 / (4 + 16 2 ) / 1 6 = 6 0 . 6 k (b ps) tmp19a43 (rev2.0) 14-4 serial chann el (hsio )
tmp19a43 also , an ex ternal clo c k i n pu t may b e u s ed as th e serial clock . th e resu ltin g b a ud rate calcu l atio n is sho w n bel o w: bau d rate calcu latio n fo r an ex tern al clo c k i n pu t: 1) uar t m ode b a ud r a t e = e x t e r n al cl oc k i n p u t / 16 in t h i s , t h e peri od o f t h e e x t e r n al cl oc k i n p u t m u st be eq ual t o o r great e r t h an 2/ fsy s . if fsys = 40 m h z, t h e h i gh est b a u d rate will b e 4 0 / 4 / 16 = 62 5 (kb p s ). 2) i/ o i n t e rface m ode b a ud r a t e = e x t e r n al cl oc k i n p u t w h en do ub le bu ff er i n g is used , it is n ecessa ry to satisfy th e fo llowing relatio n s h i p : ext e r n al cl oc k i n p u t pe ri o d > 6/ fsy s there f ore, w h en fsy s = 40 m h z, t h e bau d rat e m u st be set t o a rat e l o wer t h an 40 / 12 = 3. 3 (m b p s) . wh en do ub le bu fferi n g is no t u s ed , it is n ecessary to satisfy th e fo llowing relatio n s h i p : ext e r n al cl oc k i n p u t pe ri o d > 8/ fsy s there f ore, w h en fsy s = 40 m h z, t h e bau d rat e m u st be set t o a rat e l o wer t h an 40 / 16 = 2. 5 (m b p s) . tmp19a43 (rev2.0) 14-5 serial chann el (hsio )
tmp19a43 14.1.2 high-speed serial cloc k generatio n circuit thi s ci rc ui t ge nerat e s basi c t r ansm i t and rec e i v e cl oc ks. i/o i n terface m ode: in th e hsclk ou tpu t m o d e with the hsc0cr se rial co n t ro l reg i ster set to "0," th e ou t p u t of t h e pre v i o us l y m e nt i oned b a ud rat e ge nera t o r i s di vi ded b y 2 t o ge ne rat e t h e basi c cl oc k. in th e hsclk in pu t m o d e with hsc0 cr set to "1," rising and fallin g edg e s are d e tected according t o the hsc 0 cr settin g to gene rate the basic cl ock. asy n c h r o no us (u ar t) m ode: according to t h e settings of the serial control m o d e reg i ster hsc 0 mod0 , eith er th e clock from the ba ud rate re gi ster , t h e system clock (f sys ), th e in tern al ou tpu t si g n a l o f th e tmrb8 t i m e r , or t h e e x t e rnal cl oc k ( h sc lk o pi n ) i s se lected to ge nerate t h e basi c clock, hsioclk. 14.1.3 receive counter the receive c o unte r is a 4-bit bina ry counte r use d in t h e asy n chronous (uar t) m ode a n d is up-counted by hsiocl k. sixtee n hsio clk cl ock pulses are used i n receivi ng a single data bit while the data sym bol i s sam p l e d at t h e se v e nt h, ei g h t h , a n d ni nt h pu lses. fro m th ese t h ree sam p les, maj o rity log i c is applied to deci de the recei ved data. 14.1.4 receive control unit i/o i n terface m ode: in t h e hscl k out p u t m ode with hsc0cr se t t o "0 ," th e hr xd0 p i n is samp led on th e ri si ng ed ge o f t h e s h i f t cl oc k o u t p ut t o t h e hs c l k0 pi n. in th e hsclk inp u t m o d e with hsc0 cr set t o "1," th e serial receiv e d a ta hr xd0 p i n is sam p l e d on t h e ri si n g o r fal l i ng e d ge of hsc l k i n p u t de pe ndi ng o n t h e hsc 0 c r settin g . asy n c h r o no us (u ar t) m ode: the recei ve control unit ha s a start bit detection ci rc uit, which is use d to initiate receive ope ration wh en a norm a l start b it is d e tected . 14.1.5 receive buffer the recei ve buf f er is of a dual st ruct ure t o preve n t ove r run errors. t h e first receive buf f e r (a s h ift register) stores the receive d data b it-by-bit. w h e n a c o mplete set of bi ts have bee n s t ore d , they a r e m oved to t h e second recei ve buf f e r (hsc0buf). at t h e sam e tim e , the receive buf f e r full flag (hsc 0mod2 "rbfll") is s e t to " 1 " to indicate that va li d data is st ore d i n t h e second receive buf f e r . howe ver , i f the receive fifo is set ena b led, the recei ve da ta is m oved t o the receive fifo and t h is fla g is imm e diate l y cleared. if t h e receive fifo has be en disable d (hsc ofcnf = 0 and = 01), t h e hintrx0 inte rrupt is ge nera ted at t h e same tim e . if the receive fifo has been e n able d (hscnfcnf = 1 and scom od1< fdpx1:0> = 01), an i n terrupt will be gene rated according to the hsc0 r f c setting . tmp19a43 (rev2.0) 14-6 serial chann el (hsio )
tmp19a43 the cpu will read t h e data from e ither the second receive buf f e r (h sc 0b uf) or from the receive fifo (the address is the sam e as t h at of the rece ive buf f e r ). if the receive fifo ha s not be en e n a b led, t h e receive buf f er full flag is clea red to " 0 " by the read operation. the ne xt data received can be store d in the fi rst receive buf f er e v e n if the cpu has not read the pre v ious data from the sec o nd recei ve buf f e r (hsc0b uf) or t h e rece ive fifo. if hscl k is set to gene rate clock output in th e i/o interface m ode, the double buf fe r c ontrol bit hsc0m o d2 < w buf> can be programmed to e n a b le or disa ble the operation of t h e second receive bu f f e r (h sc o b uf) . by disabli n g t h e second rece ive buf f er (i.e ., the d ouble buf f e r function) and als o disa bling the recei ve fif o ( h sc o f c n f = 0 or 1 and < f d p x 1 : 0 > = 1 0 ) , han d sh aki ng wi t h t h e ot he r si d e of com m uni cat i on c a n be e n a b l e d an d t h e h s c l k o u t p ut st ops eac h t i m e one fram e o f d a t a i s t r a n s f er r e d. in t h is setting, the cpu rea d s data from the first recei ve buf f e r . by the read operati on of cpu, the hsc l k out put res u m e s. if t h e sec o nd receive buf f e r (i.e., double buf fe ring) is e n a b led but the re ceive fifo is not e n a b led, t h e hscl k output is stoppe d when t h e first receive data is m oved from the first recei ve buf f e r to the second recei ve buf f er a n d the ne xt data is st ore d i n t h e first buf f er filling bot h buf f ers with valid data. when t h e second receive bu f f er is read, t h e data of t h e first receive buf f er is m oved to the second receive buf f e r and t h e hscl k output is re sum e d upon generation of t h e r eceive inte rrupt hintrx. there f ore, no buf f e r ove rrun error will be ca use d in the i/o interface hsc l k out put m ode re gardless of th e settin g of t h e d oub le buf fer co n t ro l b it hsc0 mod2 . if the sec o nd receive buf f e r (doub le buf f ering) is enabled and th e receive fifo i s also ena b le d (hsc nfc n f = 1 an d = 01 / 1 1) , t h e hsclk outp u t will b e st o p p e d wh en the receive fifo i s full (acc ordi ng to the setting of hscofncf ) a n d bot h t h e first and sec o nd receive buf f ers contain valid data. als o in t h is cas e , if hscofcnf ha s bee n set t o " 1 ," the recei ve c ontrol bit rxe will be aut o m a ti cally cleared up on suspe n sion of the hsclk out put . if it i s set to "0 ," au tomatic clearin g will n o t b e p e rfo r m e d . (no t e ) in this m ode, the hsc0 cr < o er r > flag is insignifican t an d the opera tion is undefin e d. therefor e , befor e s w i t ching from the hs clk output mo de to anoth e r mod e , the hs c0 cr re giste r must be read to initializ e this flag. in ot her o p e r at i n g m odes, t h e o p erat i o n o f t h e sec o nd rece i v e bu f f e r i s al way s val i d , t h u s i m provi ng t h e perform a nce of continuous data tr ansfe r . if the recei ve fi fo is not e n a b led, an overrun error occurs whe n t h e data in the sec o nd receive buf fe r (hsc0b uf) ha s not bee n read before the firs t receive buf f e r is full with t h e ne xt receive data. if an ove rrun e r ror occurs, data i n t h e first recei ve buf f er will be lost wh ile d a ta i n th e second receiv e bu f f er and th e co n t en ts o f hsc 0 cr rem a i n in tact. if the receive fifo i s ena b le d, the fifo m u st be read befo re the fifo is full a n d the sec o nd receive buf f er is written b y th e n e x t d a ta t h ro ug h th e first bu f f er . ot h e rwise, an ov errun erro r will b e g e nerated and th e receive fifo ove rrun error flag will be set. eve n in this case, the data already in the receive fifo rem a in s in tact. th e p a rity b it to b e add e d in th e 8 - b it uar t m o d e as well as th e m o st sign ifican t b it in th e 9 - b it uar t m o d e will b e st o r ed i n hsc0cr . tmp19a43 (rev2.0) 14-7 serial chann el (hsio )
tmp19a43 in t h e 9 - bi t u a r t m ode, t h e sl ave c ont r o l l er ca n be o p er at ed i n t h e wak e -u p m ode by set t i ng t h e wa k e - u p fun c tion hsc0 mod0 t o "1 ." in th is case, the in terru p t hintrx0 will b e g e n e rated o n ly wh en hsc 0 c r is set to "1." 14.1.6 receive fifo buffer in addition to the d ouble buf f er function already de scri bed, da ta m a y be store d using t h e receive fifo bu f f e r . b y set t i ng of t h e hsc 0 f c nf r e gi st er a n d of t h e hsc 0 m o d 1 re gi st e r , th e 4 - b y te receiv e b u f f er can b e en ab led. al so , in th e uar t m o d e or i/o in terface m o d e , d a ta m a y b e store d up t o a pre d efi n ed fill level. whe n the receive fifo buf fe r is to be used, be sure to e n a b le the d oub le buf f e r fu n c tion . 14.1.7 receive fifo operatio n c i/o i n terface mo d e with hsc l k ou tpu t: the following exam ple descri bes t h e case a 4-byte da ta st rea m is receive d in the half duplex m ode: hsc0r f c<7: 6>=01: clears receive fifo a n d se ts the condition of inte rrupt ge neration. hsc0 r f c<1 : 0 >=00 : sets the in terrup t to be g e n e rated at fill lev e l 4 . hsc0fcnf < 1 :0>= 101 1 1 : aut o m a t i cally inhibits c o ntinued rece ption a f ter reachi n g the fill level. th e nu m b er of b y tes t o b e u s ed i n th e receiv e fifo is th e sam e as th e in terru p t g e n e ratio n fill lev e l. in th is con d iti o n , 4 - b y te d a ta recep tion may b e i n itiated b y settin g t h e h a lf d u p l ex tran sm issio n m ode and writing " 1 " to the r x e bit. after receiving 4 bytes, the r x e bi t is autom a tica lly cleared and the receive operation is stoppe d (hsc l k is st oppe d). 1 by te 2 by t e 3 by t e 4 by t e 1 by t e 1 by t e 1 by t e 1 by t e 2 by t e 2 by t e 2 by t e 2 by t e 1 by t e 3 by t e 3 by t e 3 by t e 4 by t e 4 by t e receive buf fe r 1 receive buf fe r 2 rx fi fo rbfll receive interrupt rxe fig. 14-3 re ceive fifo op eration tmp19a43 (rev2.0) 14-8 serial chann el (hsio )
tmp19a43 d i/o i n terface mo d e with hsc l k i n pu t: the following exam ple descri bes t h e case a 4-byte data st rea m is receive d: hsc0r f c <7: 6 > = 10: clears receive fifo and sets t h e c o ndition of interrupt gene ration hsc0 r f c <1 : 0 > = 00 : sets t h e in terru p t t o b e g e n e rated at fill lev e l 4. hsc0fcnf < 1 :0> = 10101: aut o m a t i cally allows c o ntinued reception a f ter r eac hing t h e fill level. the num ber of bytes to be us ed in t h e recei ve fifo is the m a xim u m allowable number . in t h is co nd itio n, 4 - b y te d a t a recep tio n can b e in itiated alo n g with th e in pu t clo c k by settin g th e h a lf dup lex tran sm issio n m o de an d writing "1 " to th e r x e b it. wh en th e 4 - b y te d a ta recep tio n is com p leted, the receive fifo i n terrupt will be ge nerate d. not e t h at pre p arat i on fo r t h e next dat a rece p t i on can be m a nage d i n t h i s s e t t i ng, i . e. , t h e next 4- by t e d a ta can be receiv ed b e fore data is fu lly read fro m th e fifo. receive buf fe r 1 rx fi fo receive buf fe r 2 1 by t e 2 by t e 3 by t e 4 by t e 1 by t e 1 by t e 1 by t e 1 by t e 2 by t e 2 by t e 2 by t e 2 by t e 1 by t e 3 by t e 3 by t e 3 by t e 4 by t e 4 by t e rxe receive interrupt rbfll fig. 14-4 re ceive fifo op eration tmp19a43 (rev2.0) 14-9 serial chann el (hsio )
tmp19a43 14.1.8 t r ansmit counter the t r a n sm it cou n t e r i s a 4 - b i t bi na ry c o unt er use d i n t h e asy n ch ro n o u s com m uni cat i on ( uar t ) m ode. it is c o unte d by hsiocl k as i n t h e cas e of t h e recei ve c o unte r a n d ge nerates a transm it clock ( t xd clk ) on ev er y 16 th clock p u l se. 2 1 15 14 13 12 9 1 0 11 6 7 8 5 4 1 2 1 6 3 16 15 txdclk sio c lk fig. 14-5 t r a n smit clo c k gene ration 14.1.9 t r ansmit control unit i/o i n terface m ode: in th e hsclk ou tpu t m o d e with hsc 0 cr set to "0 ," each b it o f d a ta in th e send b u f f er is out put t o t h e h t xd 0 pi n on t h e ri si ng ed ge of t h e s h i f t cl o c k out put fr om t h e hsc l k0 pi n. in t h e hsclk input m ode with hs c 0 cr set to " 1 ," each bit of data in the se nd buf fe r is out put t o t h e h t xd 0 pi n o n t h e ri si ng o r fal l i ng e dge o f t h e i n p u t h s c l k si g n al acc or di n g t o t h e hsc0 cr settin g . asy n c h r o no us (u ar t) m ode: whe n t h e c p u w r i t e s dat a t o t h e se n d b u f f e r , t h e se n d i n g of dat a be gi n s on t h e ri si ng edge o f t h e next ht x d c l k a n d a se n d s h i f t cl oc k (h t x d sft ) i s gen e rat e d. tmp19a43 (rev2.0) 14-10 serial chann el (hsio )
tmp19a43 h a nd sh ak e functio n the h cts pi n e n ab l e s f r am e by f r a m e dat a t r a n s m i ssi on s o that ove r run e r rors can be p r eve n t e d. thi s fu nct i o n ca n b e ena b l e d o r di sabl ed by hsc 0 m o d0 . w h en th e h cts0 p i n is set t o t h e "h" lev e l, t h e cu rren t d a ta tran sm issio n can b e co m p leted bu t th e n e x t d a ta tran smissio n is su spen d e d un til th e h cts0 p i n r e t u r n s to th e " l " l e v e l . ho w e v e r in th i s c a s e , th e hinttx0 in terru p t is g e n e rated , t h e n e x t tran sm it d a t a is req u e sted to th e c p u, d a ta is written to th e sen d bu f f er , and it waits un til it is read y t o tran sm it d a ta. a lth oug h no h rts pi n i s pr o v i d ed , a han d s h ake c ont r o l fu nct i o n can be easi l y im pl em ent e d b y assi gni ng a po rt f o r t h e h rts fun c tio n. by set tin g t h e po rt to "h" lev e l up on co m p letio n of d a ta reception (in the recei ve interrupt routine ) , the transm it side can be requeste d to sus p e nd data transm ission. htxd h cts transmit side receive side hrxd h rts ( a ny p o r t) fig. 14-6 han d sh ake fun c tion 3 2 1 1 6 1 5 14 3 2 1 16 15 start bit bit 0 c d 13 transmission i s suspended during this per iod htxd data w r ite timing to send buffer o r shift reg i ster h cts hsioclk htxdclk htxd (no t e ) c if the h cts signal is set to "h" during transmission , the ne xt d a t a transmis sion is suspe nded a f ter th e curr e n t tra n smiss i on is completed. d dat a tr ansmi ssion st art s on th e firs t falling edge of the htxdclk cloc k a f ter h cts is set to "l." fig. 14-7 h cts (clear to send ) signal t i min g tmp19a43 (rev2.0) 14-1 1 serial chann el (hsio )
tmp19a43 14.1.10 t r ansmit buffer th e send buf fer ( h sc0 b u f ) is in a du al str u ctur e. th e do ub le bu ff er i n g f u n c tion m a y b e en ab led or di sabl e d by s e t t i ng t h e d o ubl e bu ffe r c ont rol bi t < w b u f > i n s e ri al m ode cont rol re gi st er 2 (hsc 0 m od2 ). if do ub le bu ffering is en ab l e d , d a ta written to sen d bu ffer 2 (hsc ob uf) is m o v e d to sen d bu ffe r 1 ( s hift register ). if t h e t r ansm i t fif o ha s bee n di sa bl ed (h sc ofc n f = 0 or 1 an d = 01 ), t h e hinttx in terrup t is g e n e rated at th e same ti me and the send buffer em pty flag of h s c0 m o d 2 i s set t o "1 ." this f l ag ind i cates th at send buff e r 2 is no w em p t y an d th at t h e n e x t tr an smi t dat a can b e w r i t t e n. whe n t h e next dat a i s wri t t e n t o se n d bu ffe r 2, t h e fl a g i s c l eared t o " 0 ." if th e tran sm it fifo h a s b e en enab led (hsc nfcn f = 1 and = 10/1 1 ) , an y data in th e tran sm it fifo is m o v e d to t h e se nd buffer 2 a n d flag i s imm e diately cleared to "0." th e cpu writes d a ta t o sen d b u ffer 2 o r to t h e tran sm it fifo. if the t r ansm it fifo is disa bled in the i/o interface hsc l k input m ode and i f no data is set in send bu ffe r 2 be fo r e t h e ne xt fra m e cl ock i n p u t , whi c h occ u r s up o n com p l e t i on o f dat a t r ansm i ssi on fr o m sen d b u f f er 1 , an u nde r- r u n e r r o r occu rs an d a se ri al c ont r o l regi st er (hs c 0c r ) < p er r > pa ri t y / u n d e r - ru n flag is set. if th e tran sm it fifo is en ab l e d i n th e i/ o i n terf ace hsc l k i n p u t m ode, w h e n dat a t r a n sm i ssi on f r om sen d b u f f er 1 i s com p l e t e d, t h e se nd b u f f er 2 dat a i s m o v e d t o se n d b u f fer 1 a nd a n y dat a i n t r a n sm it fifo is m o v e d to send b u ffer 2 at th e sam e ti me. if th e tran sm it fifo is d i sab l ed in th e i/ o in terface hsc l k o u t p ut m ode , whe n dat a i n sen d b u f f er 2 i s m oved t o sen d b u f f er 1 a n d t h e dat a t r a n sm i ssi on i s c o m p l e t e d, t h e h s c l k out p u t st o p s . s o , n o un de r- ru n e r r o r s ca n be gene rat e d . if t h e t r an sm it fif o i s ena b l e d i n t h e i/ o i n t e rface h s c l k o u t p ut m ode, t h e hsc l k o u t put st o p s u p on co m p letio n of d a ta tran sm issi o n fro m send bu ffer 1 if th ere is no v a lid d a ta in th e tran sm it fifo. note) in the i/o interface hsclk outp u t mode, the hsc0 cr flag is insignifican t. in this case, the operati on is undefined. therefo re, to s w i t ch from the hsclk o u tpu t mode to another m ode, hsc0 cr must be read in ad v a nce to initializ e the flag. if d oub le bu ffering is d i sab l ed , th e cpu writes d a ta o n ly to sen d b u ffer 1 and th e t r an sm it in terrup t hinttx0 is gen e rated u pon co m p letio n of d a ta tran sm issi o n . if h a n d s h a k i ng with th e o t her sid e is n e cessary , set th e do ub le buf fer con t ro l b it to "0" (di s a b l e ) t o di sabl e se nd b u f f e r 2 s o th e tran smit fifo is not co nfigu r ed . tmp19a43 (rev2.0) 14-12 serial chann el (hsio )
tmp19a43 14.1.11 transmit fifo buffer in add itio n to th e do ub le b u f f er fun c tion alread y d e scri b e d, d a ta m a y b e sto r ed u s ing t h e tran sm it fifo b u f f er . by settin g o f th e hsc 0 fcnf reg i ster an d of th e hsc0mod1 reg i ster , t h e 4 - by t e se n d b u f fe r can b e enabl e d. in t h e u a r t m o d e or i/ o i n t e rfa ce m ode, u p t o 4 by t e s of dat a m a y be st ore d . 14.1.12 t r ansmit fifo operation c i/o i n terface mo d e with hsc l k ou tpu t (n ormal m o d e ): the following exam ple descri bes t h e case a 4 - b y te d a ta st rea m is tran sm it ted : hsc0tfc <7 : 6 > = 01 : clears transm i t fifo an d sets th e co nd itio n of i n terrup t g e n e ratio n hsc0tfc <1 : 0 > = 00 : sets t h e in terru p t t o b e g e n e rated at fill lev e l 0. h s c0fcnf <1 :0 > = 0101 1 : i n h i b its co n t i n u e d tr an sm issi o n af ter r each i n g th e f ill lev e l. in th is con d itio n, d a ta tran smissio n can be in itiate d b y settin g th e tran sfer m o d e t o h a lf dup lex , writing 4 b y tes o f d a ta to the tran sm it fifo, an d settin g th e bit to "1 ." wh en th e last tran sm it d a ta is m o v e d t o th e sen d bu f f er , th e tran sm i t fifo in terru p t is g e n e rat e d . wh en t r ansm i ssi on o f t h e l a st dat a i s com p l e t e d, t h e cl ock i s st o ppe d an d t h e t r ansm i ssi on se que nce i s termin ated . send bu f f er 1 tx f i fo send bu f f er 2 dat a 1 tbem p int t x0 dat a 2 dat a 3 dat a 4 dat a 2 dat a 3 dat a 4 dat a 5 dat a 5 dat a 6 dat a 6 dat a 4 dat a 5 dat a 6 dat a 3 dat a 4 dat a 5 dat a 5 txe dat a 6 dat a 6 fig. 14-8 t r a n smit fifo o p eratio n tmp19a43 (rev2.0) 14-13 serial chann el (hsio )
tmp19a43 d i/o i n terface mo d e with hsc l k i n pu t (no r mal m o d e ): the following exam ple descri bes t h e case a 4 - b y te d a ta st rea m is tran sm it ted : hsc0tfc <1 : 0 > = 01 : clears th e tran sm it fifo an d sets t h e co nd ition o f in terrup t g e n e ratio n. hsc0tfc <7 : 2 > = 00 000 0 : sets th e i n terrup t to b e g e n e rated at fill lev e l 0 . hsc0fcnf < 4 :0> = 01001: allo ws c ontinued tra n sm ission a f ter reachi n g the fill level. in th is co nd itio n, d a ta tran smissio n can be in itiated alon g with th e in pu t clo c k b y settin g t h e tran sfer m o d e to h a lf du p l ex , writin g 4 b y tes of d a ta t o t h e tr ansm i t fifo, an d settin g the b it to "1 ." when th e last transmit d a ta is mo v e d to th e sen d bu f f er , th e t r an sm it fifo in terrup t is gene rat e d . send bu f f er 1 tx f i fo send bu f f er 2 dat a 1 tbem p int t x0 dat a 2 dat a 3 dat a 4 dat a 2 dat a 3 dat a 4 dat a 5 dat a 5 dat a 6 dat a 6 dat a 4 dat a 5 dat a 6 dat a 3 dat a 4 dat a 5 dat a 5 txe dat a 6 dat a 6 fig. 14-9 t r a n smit fifo o p eratio n tmp19a43 (rev2.0) 14-14 serial chann el (hsio )
tmp19a43 14.1.13 parity con t rol circuit if th e p a rity add itio n b it of th e serial co n t ro l re g i ster hsc0 cr is set to "1 ," d a ta is sen t with the p a rity b it. no te th at th e p a rity b it m a y b e used on ly in th e 7 - o r 8-b it uart m o d e . th e b it of hsc0 cr selects eith er ev en or o d d p a rity. upon d a ta tran sm issio n , th e p a rity co n t ro l circu it au to matically g e n e rates th e p a rity with th e d a ta written to th e sen d bu ffer (hsc0 b uf). after d a ta tran sm iss i o n is co m p le t e , th e p a rity b it will b e stored i n hsc 0 b u f bi t 7 i n t h e 7- bi t u a r t m ode an d i n bi t 7 i n t h e se r i al m ode cont r o l reg i ster hsc 0 mod in th e 8-b it uart m o d e . th e an d settin gs m u st b e co m p lete d b e fo re d a ta is written t o th e sen d buffer. upon data rec e ption, t h e parity b it for the receive d data i s aut o m a tically gene rated while the data i s shifted t o rece ive buffer 1 a nd m ove d to receive buffer 2 (hsc 0buf). in the 7-bit uart m ode, the p a rity g e n e rated is co m p ared with th e p a rit y st o r ed in hsc0 buf , wh ile in t h e 8-b it uart m o d e , it is co m p ared with t h e b it 7 o f t h e hs c0 cr register. if there is a n y di ffe rence , a pa ri ty er ro r o c cu rs and th e f l ag o f th e hsc0 cr reg i ster is set. in t h e i/o i n terface m ode, the hsc 0 cr flag functions as a n unde r-run e r ror fla g , not as a p a rity flag. 14.1.14 error flag three error fla g s a r e provide d to in c r ease t h e reliability of receive d data. 1. ove r r u n e r r o r : b i t 4 of t h e se ri al cont rol regi st e r hsc 0 c r in bot h u a r t a n d i/ o i n t e rface m odes, t h i s bi t is set to "1 " wh en an erro r is gen e rated b y com p leting the recepti on of the next fram e receive da ta be fore the receive buf f er has be en rea d . if the receive fifo is e n a b led, the recei ve d data is a u tom a tically m oved to the recei ve fifo and no ove rrun error will be ge nera ted until the receive fi fo is full (or until the usable bytes are fully o ccup i ed). th i s flag is set to "0 " wh en it is rea d . i n t h e i/ o i n t e rface hsc l k out pu t m ode, n o ove rr u n e r r o r i s ge nerat e d a n d t h e r ef o r e, t h i s fl ag is inoperative and t h e operation is undefine d. 2. pari t y err o r/ un der - r u n er r o r < p er r > : b i t 3 of t h e hsc 0 c r regi st er in th e uar t m o d e , th is b it i s set to "1 " when a p a r i t y er ro r i s ge nerat e d. a pa ri t y err o r i s ge ne rat e d whe n t h e parity gene rated from the receive d data is di f f e r ent from the parity received. this fla g is set to "0 " wh en it is read. in the i/o i n terface m ode, t h is bit indicates an unde r -run e r ror . whe n t h e do uble buf f er cont rol bit < w b u f> o f t h e se ri al m ode co nt r o l re gi st er h s c 0 m o d 2 i s set t o " 1 " i n t h e hsc l k i n put m ode, if n o d a ta is set to th e tran smit d oub le bu f f er b e f o re t h e ne xt dat a t r ans f er cl o c k after co m p letin g th e tran sm issio n fro m th e t r ansmit sh ift reg i ster , th is erro r fl ag is set to "1 " ind i catin g an u n d e r -ru n erro r . if th e tran sm it fifo is en ab led , an y data co n t en t in th e tran sm it fi fo will b e m o v e d t o th e b u f f er . wh en t h e tran sm it fifo and th e dou b l e bu f f er are bo th em p t y , an u n d e r -ru n error will b e gene rat e d . b e c a use n o un de r - ru n e r r o r s ca n be gen e rat e d i n t h e hsc l k out put m ode , t h i s fl a g i s i n o p erat i v e a n d t h e ope rat i o n i s un defi ned . i f sen d bu f f e r 2 i s di sabl ed , t h e un de r - ru n fl ag will n o t b e set. th is flag is set to "0 " wh en it is read . tmp19a43 (rev2.0) 14-15 serial chann el (hsio )
tmp19a43 3. fram i ng er ro r : b i t 2 o f t h e h s c 0 c r regi st er in t h e uar t m o d e , th is b it is set to "1 " wh en a fram i n g erro r is g e n e rated . th is flag i s set to "0 " wh en it is read. a fram i n g erro r is g e n e rated if t h e c o rres p on di n g st o p bi t i s det e rm i n ed t o be " 0 " b y sam p lin g the b i t at aroun d th e cen t er . reg a rd le ss of the (st o p b it leng th) settin g of th e serial m o de con t ro l reg i ster 2, hsc0 m o d2 , t h e st o p b it statu s is d e termin ed b y on ly 1 b it on the recei ve si de. ope r a t ion mo de error fla g func tio n oerr overrun error flag p e r r p a r i t y e r r o r f l ag uart ferr framing error f l ag oerr overrun error flag underrun error f l ag (wbuf = 1) perr fixed to 0 (wb u f = 0) i/o interface (hsclk input) ferr fixed to 0 o e r r o p e r a t i o n undef i n e d p e r r o p e r a t i o n undef i n e d i/o interface (hsclk output) ferr fixed to 0 tmp19a43 (rev2.0) 14-16 serial chann el (hsio )
tmp19a43 14.1.15 direction of dat a t r ansfer in the i/o i n terface m ode, t h e direction of data tran s f er ca n be s w itche d betwee n "msb first" a n d "lsb first" b y t h e data tran sfer d i rectio n settin g b it o f th e hsc 0 mod2 serial m o d e con t ro l reg i ster 2. don't switch th e d i rectio n wh en data is b e ing t r an sferred . 14.1.16 s t op bit length in t h e uar t m o d e tran sm is sio n , th e st o p bit len g t h can be set to eith er 1 o r 2 b its b y b it 4 of the hsc0m o d2 re gister . 14.1.17 s t atus flag if th e d oub le bu f f er fun c tion i s en ab led (hsc0 m od 2 = "1 " ) , th e b it 6 f l ag o f the hsc0m o d2 register indicates the c o ndition of receive buf f er full. wh en one fram e of data has be en receive d and transfe rre d fr om buf f e r 1 to buf f er 2, t h is bit is set to "1" to s h ow that buf f e r 2 is full (data is store d in buf f er 2). whe n the recei ve buf fer is rea d by c p u/dm ac, it is cleared to " 0 ." if < w b u f> is set to "0 ," th is b it is in sign ifican t an d mu st no t b e u s ed as a statu s fl ag . wh en d oub le bu f f eri n g i s enable d (hsc 0mod2 < w b u f> = " 1 "), the bit 7 flag of t h e hsc 0 mod2 register indicates t h at sen d b u f f e r 2 i s em pt y . whe n dat a i s m oved f r om send b u f fe r 2 t o sen d bu f f e r 1 ( s hi ft regi st er ), t h i s b it is set to "1" in d i cating that sen d bu f f er 2 is now emp t y . wh en d a t a is set to th e send bu f f er by cpu/dm ac, t h e bit is cleare d t o " 0 ." if < w buf> is se t to "0," t h is b it is in sign ifican t an d m u st no t b e use d as a status flag. 14.1.18 configurations of send/receive buffers w buf = 0 w buf = 1 transmit buff e r s ingle double uart receive bu ffer d ouble double transmit buff e r s ingle double i/o interface (hsclk input) receive bu ffer d ouble double transmit buff e r s ingle double i/o interface (hsclk output) receive bu ffer s ingle double 14.1.19 softw are re set soft ware reset is hsc 0 m o d 2 ?10? ?01 ? hsc0m o d0 rxe hsc0 mod1 hsc0mo d2 tbe m p , rbfll , tx ru n hsc0 cr oe rr pe rr fe rr an d in tern al circu it is initialized . othe r states are m a intained. tmp19a43 (rev2.0) 14-17 serial chann el (hsio )
tmp19a43 14.1.20 signal gen e ration t i ming c uar t m o de: receive side mode 9 - b i t 8 - b i t w i t h parity 8-b i t, 7-b i t, and 7-b i t w i th pa r i ty interrupt gen e ration tim ing around the cen ter of the 1st stop b i t around the cen ter of the 1st stop bit around the cen ter of the 1st stop bit framing error timing around the cen ter of the stop bit around the cen ter of the stop bit around the cen ter of the stop b i t parity error g e neration tim ing ? around the cen ter of the last (p arit y) bi t around the cen ter of the last (parity ) bit overrun error generation tim ing around the cen ter of the stop bit around the cen ter of the stop bit around the cen ter of the stop b i t t r an sm it sid e mode 9 - b i t 8 - b i t w i t h parity 8-b i t, 7-b i t, and 7-b i t w i th pa r i ty interrupt gen e ration tim ing ( = 0) just before the stop bit is sent just before the stop bit is se nt just be fore the stop bit is se nt interrupt gen e ration tim ing ( = 1) im m e diatel y aft e r dat a is moved to send buffer 1 (just b e f o re start b it transm ission) im m e diatel y aft e r dat a is moved to send b u ffer 1 (just befor e start bit tra n smission) immediately after data is moved to send buff e r 1 (just befor e start bit tra n smission) d i/o i n terface m ode: receive side hsclk output mode immediately after th e rising edg e of the last hsclk interrupt gen e ration tim ing (wbuf = 0) hsclk input mode immediately after the rising or f a lling edge of th e last hsclk (for rising o r f a lling edg e mode, r e spectively ) hsclk output mode immediately aft e r the rising edg e of the l a st hscl k (just af ter data trans f er to r ece ive buffer 2) or jus t aft e r r ece i v e buffe r 2 is read interrupt gen e ration tim ing (wbuf = 1) hsclk input mode immediately after the rising edg e or falling edge o f the last hsclk depending on th e r i sing or falling edge tr iggering m ode, respe c tiv e l y (righ t after da ta is moved to receiv e buff e r 2) overrun error generation timin g hsclk input mode immediately after the rising or f a lling edge of th e last hsclk (for rising o r f a lling edg e mode, r e spectively ) t r an sm it sid e hsclk output mode immediately after th e rising edg e of the last hsclk interrupt gen e ration tim ing (wbuf = 0) hsclk input mode immediately after the rising or f a lling edge of th e last hsclk (for rising o r f a lling edg e mode, r e spectively ) hsclk output mode immediately after the rising edg e of the last hsclk or just after data is moved to send buff e r 1 interrupt gen e ration tim ing (wbuf = 1) hsclk input mode immediately after the rising or f a lling edge of th e last hsclk (for the rising or falling edge m ode, r e spec tive l y) or just af ter data is moved to send buff e r 1 under-run error generation timin g hsclk input m ode im m e diatel y aft e r the fa lling or r i sing edge of the next hsclk (for the rising or falling edge tr ig gering mode , r e s p ect ivel y) note 1) do no t modif y an y contr o l register w h en dat a is being sen t o r receiv ed (in a st ate re ad y to send or receiv e ). note 2) do not sto p the receiv e ope ration (b y setting hsc0mo d0 ="0" ) w h e n dat a is being receiv e d. note 3) do not sto p the transmi t opera tion (b y setting hsc0mo d1 ="0" ) w h e n dat a is being trans m itted. tmp19a43 (rev2.0) 14-18 serial chann el (hsio )
tmp19a43 14.2 register description (only for channel 0) 7 6 5 4 3 2 1 0 bit symbol tb8 ctse rxe wu sm1 sm0 sc1 sc0 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 f u n c t i o n s e n d d a t a bit 8 handsha ke function control 0: di sable s c t s 1: e nable s c t s receive control 0: di sable s rece ption 1: e nable s rece ption wake-up function 0: disable 1: enable serial transfer m ode 00: i/o inte rface mode 01: 7-bit length uart mo de 10: 8-bit length uart mo de 11: 9-bit length uart mo de serial transfer clock (for ua rt) 00: timer tb0out 01: baud rat e generat or 10: internal f sy s clock 11: exte rnal clock (hsclk0 inp ut) hsc0mod0 (0x f f ff_e80e ) (0x f f ff_e80 d ) l i tt le big wakeup functio n 9-bit uart other mode 0 interrupt when rece ived 1 i nterrupt at rb8 =1 don?t care h a nd sh ak e functio n ( cts pi n) e n a b l e no te) in th e i/o in terface m o d e , th e serial control regist er (hsc0cr) is u sed fo r clo ck selectio n . 0 disable ( t ransmission is alway s allowed) 1 e nable note) with set to "0," se t each mod e re giste r (hs c 0mo d 0, hs c0mo d1 a n d hsc0 mo d2). then se t to "1." ? the regis t er s must be b y te acc ess ed in setting th em. fig. 14-1 0 serial mod e co ntrol re giste r 0 (for hsio0 , hsc0mo d0 ) tmp19a43 (rev2.0) 14-19 serial chann el (hsio )
tmp19a43 7 6 5 4 3 2 1 0 bit symbol i2s0 fdpx1 fdpx0 txe sint2 sint1 sint0 ? r e a d / w r i t e r / w r / w r / w r / w r / w r / w r / w r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 f u n c t i o n i d l e 0: stop 1: start transfer mode s etting 00: tra n sfer proh ibited 01: half duplex (rx) 10: half duplex (tx) 11: full duplex transmit control 0: disable 1: enable interval time of continuous transmission 000: none 1 00: 8sclk 001: 1sclk 1 01:16sclk 010: 2sclk 1 10: 32sclk 011: 4sclk 1 11: 64sclk write "0." hsc0mod1 (0x f f ff_e80 5 ) (0x f f ff_e80 6 ) l i tt le big fig. 14-1 1 se rial mod e co ntrol re giste r 1 (for hsio0 , hsc0mo d1 ) : sp ecifies th e in terv al tim e o f co n tinuou s t r an sm issio n wh en d oub le b u f f ering o r /an d fifo is en ab led in th e i/o i n terface mo d e . th is p a rameter is in v a li d for th e ua r t m o d e . : th is b it en ables tran sm issi o n and is v a lid for all t h e trans f er m odes. if disabl ed while transm ission i s in progress , tra n sm issio n is inh i b ited o n ly after the c u rrent fram e of data is co m p leted for t r an sm issio n . : configures t h e tr ansfe r m ode in the i/o i n terface m ode. als o confi g ures the fifo if it is enable d. in th e ua r t m o d e , it is u s ed o n l y to sp ecify th e fifo con f i g uratio n. : specifies t h e idle m ode ope r ation. ? the regis t er s must be b y te acc ess ed in setting th em. tmp19a43 (rev2.0) 14-20 serial chann el (hsio )
tmp19a43 7 6 5 4 3 2 1 0 bit symbol tbemp rbfll txrun sblen drch g w buf swrst1 swrst0 r e a d / w r i t e r / w a f t e r r e s e t 1 0 0 0 0 0 0 0 function send buffer empt y flag 0: full 1: empt y receive buffer full flag 0: empt y 1: full in transmiss ion flag 0: stop 1: start stop bit 0: 1-bit 1: 2-bit setting transfer direction 0: l sb f i r s t 1: m sb f i r s t w-buffer 0: disable 1: enable soft reset overwrite "01" o n "10" to reset hsc0mod2 (0x f f ff_e80 6 ) (0x f f ff_e80 5 ) l i tt le big : ove r writing " 01" i n place of " 10" ge nerates a softwa re reset. whe n this soft ware reset is execute d, t h e m ode regis t er pa ram e ter s hsc 0 mod0 , hsc0m o d1< t xe>, hsc0m o d2 , < rbfll>, a nd , cont rol re gister param e ters hsc0cr , , and , and th ei r in tern al circu its are i n itialized . < w buf>: this pa ram e te r ena b les or disables t h e s e nd/ receive buf f ers t o se nd (i n both hsclk o u t p u t/inp u t m o d e s) and receiv e (in h s c l k ou tpu t m o d e ) d a ta i n th e i/o in terface m o d e an d to tran sm it d a ta in th e ua r t . in all o t h e r mo d e s, do ub le bu f f eri n g is en ab led reg a rd less of t h e settin g. : specifies the direction of da ta tra n sfe r i n t h e i/o interface m ode . in t h e uar t m ode, it is fixe d to lsb first. : this is a status flag to s h ow th at d a ta t r ansmissio n is in p r og ress. w h en th is b it is set t o "1 ," it ind i cates t h at d a ta tran sm issi o n o p eration is in p r og ress. if it is "0 ," th e b it 7 is set to "1 " to ind i cate th at th e tran sm issio n h a s b een fu lly co m p le ted and the sam e is set to "0" t o i ndicat e that t h e send buf f e r contains s o m e data wai t i ng f o r t h e next t r ansm i ssion . : this is a flag to s h ow that the receive d ouble buf f e r s are full. when a receive operation is com p leted and receive d data is m oved from the receive shift re gister t o the receive double b u f f ers, th is b it ch an g e s to "1 " wh ile read ing th is b it ch ang e s it to "0 ." if do ub le b u f f ering is d i sab l ed, th is flag is in sig n i fican t . : this flag s h ows that the se nd do u b l e b u f fe rs are em pt y . w h en dat a i n t h e s e nd d o ubl e b u f f ers i s m o v e d to th e sen d sh ift reg i st er an d th e doub le b u f f ers are e m p t y , th is b it is set to "1 ." w r itin g d a ta ag ai n t o the do ub le b u f f ers sets th is b it to "0 ." if do ub le b u f f ering is d i sab l ed, th is flag is in sig n i fican t . : this s p ecifies the length of s t op bit tra n sm ission in the ua r t m ode. on t h e receive s i de, t h e d ecision is m a d e u s ing on ly a sing le b it reg a rd less of th e settin g. (no t e ) while dat a transmis sion is in pro gress, a n y sof t w a re r e set o p era t io n must b e execu ted t w i ce in succe s s ion. ? the regis t er s must be b y te acc ess ed in setting th em. fig. 14-1 2 serial mod e co ntrol re giste r tmp19a43 (rev2.0) 14-21 serial chann el (hsio )
tmp19a43 7 6 5 4 3 2 1 0 bit sy mbol rb8 even pe o e rr perr ferr sclks io c read/write r r/w r (cleared to "0" w h en rea d ) r/w a f t e r r e s e t 0 0 0 0 0 0 0 0 1: erro r f u n c t i o n r e c e i v e data bit 8 parit y 0: odd 1: even add parit y 0: disable 1: enable ov erru n p a r i t y / under-run framing 0: hsclk0 1: hsclk0 0: b aud rate g enera t or 1: hsclk0 p i n in put hsc0cr (0x f f ff_e80 d ) (0x f f ff_e80e ) l i tt le big i/o int e rfa ce inp u t c l ock sele ctio n framing error f l ag parity error/und er-run error flag overrun error flag edge se le ction f o r hsclk0 inp u t oper a tion add/check ev en parit y clear ed to "0" when re ad 0 data send /receiv e at r i sing edges of hsclk0 1 data send /re ceiv e a t f a ll ing edges of hsclk0 0 b aud rate generator 1 h sclk0 pin in put 0 o dd parity 1 e ven p a rity (no t e ) an y error flag is cleared w h e n re ad. ? the regis t er s must be b y te acc ess ed in setting th em. fig. 14-1 3 serial co ntrol r egiste r (for hsio0, hsc0 cr) tmp19a43 (rev2.0) 14-22 serial chann el (hsio )
tmp19a43 7 6 5 4 3 2 1 0 bit symbol ? hbr0adde hbr0s5 hbr0s4 hbr0s3 h b r 0 s 2 h b r 0 s 1 hbr0s0 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 function write "0." n+(16-k)/16 div i der function 0: disable 1: enable divide ratio "n" hbr0cr (0x f f ff_e80 f ) (0x f f ff_e80 c ) l i tt le big ? the regis t er s must be b y te acc ess ed in setting th em. 7 6 5 4 3 2 1 0 bit symbol hbr0k3 hbr0k2 hbr0k1 hbr0k0 r e a d / w r i t e r r / w after reset 0 0 0 0 0 function alw a y s reads "0. " specify k fo r the "n + (16 - k)/16 " division hbr0add (0x f f ff_e80 4 ) (0x f f ff_e80 7 ) l i tt le big setting d i vid e r a tio of the baud r a te gen e rator hbr0cr = 1 hbr0cr = 0 hbr0cr hbr0dd 000000(n = 64) 0001(n = 1) 000010(n = 2) 111111(n = 63) 0000 01( n = 1) ( o nly ua rt) 111111 (n = 63) 000000 (n = 64) 0 0 0 0 d i s a b l e d i s a b l e 0001(k = 1) 1111(k = 15) disable n + 16 k) (16 ? divis i on divide b y n ~ ~ ~ ~ fig. 14-1 4 baud rate g e n e rato r co nt rol (for hsio0, hbr0 cr, hb r0add) (no t e 1 ) in the uart m ode, the div i sion ratio "1" of the baud rate g e nera tor can be specified only w h e n the "n + (1 6 - k)/16 " div i sion function is no t used. in the i/o interfac e mode, "div ide b y 1" must not be speci fied as a div i sor for the bau d rate ge nera to r . (no t e 2 ) t o use the " n + (16 - k)/ 16" div i sion function, be sure to se t hbr0 cr to "1" af ter se tting the k v a lue (k = 1 to 15) to hb r0 add . ho w e v e r , don't us e th e "n + (16 - k)/16" div i sion function w h en hbr0 cr is set to eithe r "0000 00" or "0000 0 1" (n = 64 or 1). (no t e 3 ) the "n + (1 6 - k)/16" d i v i sion function can o n ly be used in the uart mode. in the i/o interface m ode, th e "n + (16 - k)/ 16" div i sion func tion m u st b e disabled (prohib i ted) b y sett i ng hb r0cr t o "0." tmp19a43 (rev2.0) 14-23 serial chann el (hsio )
tmp19a43 7 6 5 4 3 2 1 0 t b 7 t b 6 tb5 t b4 tb3 t b2 tb1 t b0 ( s e n d buffer fif o ) hsc0buf (0x f f ff_e80 0 ) (0xff ff_e80 3 ) 7 6 5 4 3 2 1 0 r b 7 r b 6 rb5 r b4 rb3 r b2 rb1 r b0 ( r e c e i v e buffer fif o ) l i tt le big note: hsc0 buf w orks as a s e nd buffer for wr ope rati on and as a receiv e buffer for rd op eration. fig. 14-1 5 fifo co nfigura t ion regi ster 7 6 5 4 3 2 1 0 bit symbol reserved reserved rese rved r f s t t f i e r f i e rxtxcn t cnf g r e a d / w r i t e r / w after reset 0 0 function be sure to w r ite "000." by tes u s ed in r x f i fo 0: max i mum 1: s a me a s fill lev e l o f r x f i f o t x inte rrup t f o r t x fi fo 0: disable 1: enable r x inte rrup t f o r r x fi fo 0: disable 1: enable autom a tic disable o f rx e/ t x e 0: none 1: a u to d i sable fi fo enable 0: di sable 1: e nable hsc0fc nf (0x f f ff_e80 c ) (0x f f ff_e80 f ) l i tt le big : if en ab led , t h e h s co mod 1 settin g au t o m a tica l ly co nfigu r es fifo as fo ll o w s: = 01 ( h alf duple x rx) -- -- 4- byte rx f i f o = 10 ( h al f d upl e x t x ) - - - - 4- by t e tx fif o = 1 1 ( f ul l du pl ex ) - - - - 2- byte rx fi fo + 2- byte t x fi fo : 0 t h e fu nct i o n t o aut o m a t i c al ly di sabl e r x e/ txe bi t s i s di s a bl ed. 1: if e n able d, t h e hscom o d1 is use d t o set as follows: = 0 1 (h alf du p l ex rx) ------ w h en th e rx fifo is filled u p t o th e sp ecified nu m b er o f v a lid b y tes, rx e is au to matically set to "0 " t o i n h i b i t furthe r rece pti o n. = 1 0 (h alf du p l ex tx ) -- -- -- w h en th e tx fifo is em p t y , tx e is au t o matical ly se t to "0 " to i n h i b it furth e r tran smissio n . = 1 1 (fu ll d u p l ex) ---- ------- w h en e ith er of th e abov e tw o con d ition s is satisfied , tx e/rx e are au to m a tical ly set to "0 " to inhib it furth e r tran sm issio n an d recep tion . : whe n rx fifo is enable d, receive interrupts are ena b led or disabled by this param e ter . : w h en tx fifo is enab led , tran sm it in terr u p t s are enabl e d or di sa bl ed by t h i s pa ram e t e r . : whe n rx fifo is enable d, t h e num ber of r x fi fo by t e s t o be use d i s sel ect e d . 0: the m a xim u m num ber of by t e s of t h e fi f o co n f i g ure d 4 by t e s whe n = 01 (h al f du pl ex rx ) a n d 2 by t e s f o r < f dp x 1 : 0 > = 1 1 (ful l d upl e x ) 1 : sam e as th e fill lev e l fo r recei v e in terru p t g e n e ration sp ecified b y sc0 r fc . (no t e 1 ) rega rding t x fifo, the maximum number of b y tes being con f igured is al w a y s av ailable. the av ailable number of b y tes is the b y tes already w r i t ten to the tx fifo. ? the regis t er s must be b y te acc ess ed in setting th em. tmp19a43 (rev2.0) 14-24 serial chann el (hsio )
tmp19a43 fig. 14-1 6 re ceive fifo control regi ster 7 6 5 4 3 2 1 0 bit symbol rfcs rfis ? ? ? ? r i l 1 r i l 0 read/write r a f t e r r e s e t 0 0 0 0 0 0 0 0 function clear rx fif o 1: clear alw a y s reads "0." select interrupt generation condition alw a y s reads "0. " fifo fill level to generate rx inte rrupts 01: 1b y t e 10: 2b y t e 11: 3b y t e note: ril1 is ign o red w h en f d px1:0 = 11 (full duplex) hsc0rf c (0x f f ff_e80 8 ) (0x f f ff_e80b ) l i tt le big 0: an interrupt is generated w h en the specified fill lev e l is reached. 1: an interru pt is generate d w h e n the specifie d fill le v e l is reached or if the specified fill le v e l has been ex ceed ed at th e time dat a is rea d . fig. 14-1 7 t r ansmit fifo config uratio n regi ster 7 6 5 4 3 2 1 0 bit symbol tfcs tfis ? ? ? ? t i l 1 t i l 0 read/write r a f t e r r e s e t 0 0 0 0 0 0 0 0 function clear tx fif o 1: clear alw a y s reads "0." select interrupt generation condition alw a y s reads "0. " fifo fill level to generate tx inte rrupts 00: empt y 01: 1b y t e 10: 2b y t e 11: 3b y t e note: til 1 is ignored w h en f d px1:0 = 11 (full duplex). 0: an interrupt is generated w h en the specified fill lev e l is reached. 1: an interru pt is generated w h en the specified fill le v e l is reached or if the le v e l is low e r than th e specified fill le v e l at the time ne w dat a is w r itten. hsc0t f c (0x f f ff_e80 9 ) (0x f f ff_e80a ) l i tt le big ? the regis t er s must be b y te acc ess ed in setting th em. tmp19a43 (rev2.0) 14-25 serial chann el (hsio )
tmp19a43 fig. 14-1 8 re ceive fifo s t atus regi ster 7 6 5 4 3 2 1 0 b i t s y m b o l r o r r l v l 2 r l v l 1 r l v l 0 r e a d / w r i t e r r after reset 0 0 0 0 0 0 0 0 function rx fif o ov erru n 1: gene rated cleared w h en rea d alw a y s reads "0. " status of rx fifo fill level 000: empt y 001: 1b y te 010: 2b y te 011: 3b y t e 100: 4b y te hsc0rst (0x f f ff_e80a ) (0x f f ff_e80 9 ) l i tt le big fig. 14-1 9 t r ansmit fifo s t atus regist er 7 6 5 4 3 2 0 b i t s y m b o l t u r t l v l 2 t l v l 1 t l v l 0 r e a d / w r i t e r r after reset 1 0 0 0 0 0 0 0 function tx fif o under run 1: gene rated cleared b y writing to fif o alw a y s reads "0. " status of tx fi fo fill level 000: empt y 001: 1b y te 010: 2b y te 011: 3b y t e 100: 4b y te hsc0tst (0x f f ff_e80b ) (0x f f ff_e80 8 ) l i tt le big fig. 14-2 0 hsio enable registe r 7 6 5 4 3 2 1 0 bit symbol ? ? ? ? ? ? ? sio e r e a d / w r i t e r r / w after reset 0 0 0 0 0 0 0 0 function alw a y s reads "0. " hsio operation 0: disable 1: enable hsc0en (0x f f ff_e80 7 ) (0x f f ff_e80 4 ) l i tt le big : it specifie s hsio opera tion. when hsio operatio n is disabled, the clock w i ll not b e supplied to the hsio mo dule exc ept for the regis t er p a r t and thus p o w e r dissip a tio n can be red u ced (o ther r e gister s can not be ac ce ssed for rea d / w r i te oper a tion). wh e n hsio is to be used, be sure to e n able hsio b y setting "1 " to this re gister be for e setting an y other r e gisters of the hsio modul e. if hsio is enabled on c e and th en disabled, an y register se tting is main t a ined. ? the regis t er s must be b y te acc ess ed in setting th em. tmp19a43 (rev2.0) 14-26 serial chann el (hsio )
tmp19a43 14.3 operation in each mode 14.3.1 mode 0 (i/o interface mode) mode 0 c onsi s t s o f t w o m odes, i . e. , t h e " h sclk o u t p ut " m ode t o o u t p ut sy nc h r o n o u s cl oc k a n d t h e "hsclk input" m ode to acce pt sync hronous clock from an external s o urc e . the followi ng ope r ational descri ptions a r e for the case use of fi fo is disab l ed . fo r d e tails o f fifo op eration , refer to th e p r ev iou s sections desc ribing recei ve/transm it fifo functions . c sen d i n g dat a hscl k out put m ode in t h e hscl k out put m ode, i f hsc 0 mo d 2 < w bu f> i s set t o "0" an d t h e send d o u b l e bu f f e r s are di sabl e d , 8 bi t s of dat a are o u t put fr om t h e hxd 0 pi n a n d t h e sy nc hr o n o u s cl ock i s o u t p ut fr om t h e hsclk0 pin each tim e the cpu writes data to th e se nd buf f e r . when all data is out put, the hi ntt x 0 i n t e rr upt i s ge nerat e d. if h s c0 mod2 is set to "1 " an d th e sen d do u b l e bu f f e r s a r e e n abl e d, dat a i s m oved fr o m send b u f f er 2 t o send bu f f er 1 wh en t h e cpu writes d a ta to send b u f f er 2 w h ile d a ta t r ansmissio n is hal t e d or whe n dat a t r a n sm issi on f r om sen d b u f f er 1 (s hi ft re gi st er) i s com p l e t e d. when dat a i s m oved f r om send b u f f e r 2 t o sen d b u f fe r 1, t h e se nd b u f f er em pt y fl ag h s c0mo d 2 i s set t o "1 ," an d t h e h i ntt x 0 i n t e rr u p t i s ge nerat e d. if se n d bu f f e r 2 ha s n o dat a t o be m oved t o sen d bu f f e r 1, t h e hi ntt x 0 i n t e rr u p t i s not gene rat e d an d t h e hscl k0 o u t p ut st o p s. t r a n s m i t d a ta wr i t e t i m i n g h s c l k 0 o u tp u t bi t 0 bi t 6 b i t 7 bi t 1 ht x d 0 ( h in t t x 0 in t e r r u p t bi t 0 ht xrun < w bu f> = " 0 " (i f d o u b l e bu f f eri n g i s di sa bl ed) tmp19a43 (rev2.0) 14-27 serial chann el (hsio )
tmp19a43 transm i t da t a w r i t e t i m i ng hc lk 0 out put bi t 0 bi t 6 b i t 7 bi t 1 ht x d (h i n t t x0 i n t e r r up t r e q ues t ) bi t 0 t b run tbem p = "1" (if do ub le b u f f ering is en ab l e d ) (if th ere is d a ta in bu f f er 2) transm i t da t a w r i t e t i m i ng s c lk 0 ou t put bi t 0 bi t 6 b i t 7 bi t 1 ht x d 0 ( h i n t t x 0 i n t e r r up t r e q uest ) t b run tbem p < w bu f> = " 1 " (i f d o u b l e bu f f eri n g i s ena b l e d) (i f t h ere i s no dat a i n bu f f er 2) fig. 14-2 1 send ope r ation in the i/o inte rface m ode (hsclk 0 out put mode ) hscl k i n p u t m ode in th e h s clk inp u t m o d e , i f hsc0 mo d2 is set to "0 " and the sen d d oub le b u f f ers ar e d i sab l ed , 8 - b it d a ta th at h a s been written in th e send b u f f er is o u t pu t fro m th e h t x d 0 p i n wh en th e h s clk 0 inp u t b e co m e s activ e. w h en all 8 b its ar e sen t , th e h i n t tx0 i n terrup t is g e nerated . th e n e x t send d a ta m u st b e w r itten b e fo re th e ti min g po in t "a ." if h s c0 mod2 is set to "1 " an d th e sen d do u b l e bu f f e r s a r e e n abl e d, dat a i s m oved fr o m send buf fer 2 to send bu f f er 1 w h en t h e cpu w r ites d a ta to sen d bu f f er 2 b e fore t h e h s clk0 becom e s act i v e or w h e n dat a t r ansm i ssi on f r om send b u f f e r 1 (s hi ft re gi st er) i s c o m p l e t e d. as dat a i s m oved f r o m sen d bu f f er 2 t o se nd b u f f er 1, t h e se n d bu f f er em pt y fl ag hsc0m o d2 < t bemp> is set to "1 " and th e h i n t tx0 in terrup t is gen e rated . if the h s clk 0 i n pu t b e co m e s act iv e wh ile no dat a i s i n s e nd b u f fe r 2, a l t hou g h t h e i n t e rnal bi t co u n t e r i s st a r t e d, a n un de r - r u n er ro r occu rs an d 8-b it du mmy d a ta (ffh ) is sen t . tmp19a43 (rev2.0) 14-28 serial chann el (hsio )
tmp19a43 hs clk 0 i npu t ( < sc l k s> = 0 ri s i ng ed ge m ode) hs clk 0 i npu t ( < sc l k s> = 1 f al l i ng e dge m ode) bi t 0 bi t 1 ht x d 0 (hi n ttx 0 i n t e rrupt requ es t ) bi t 5 b i t 6 bi t 7 transm i t da t a w r i t e t i m i ng bi t 0 bi t 1 a < w bu f> = " 0 " (i f d o u b l e bu f f eri n g i s di sa bl ed) hs clk 0 inpu t ( < sc l k s> = 0 ris i ng ed ge m ode) hs clk 0 inpu t ( < sc l k s> = 1 f alling e dge m ode) bit 0 bit 1 ht x d 0 (hi n t t x 0 int e rrupt reques t ) bit 5 b i t 6 bit 7 t r ansm i t da t a w r it e t i m i ng bit 0 bit 1 a t b run tb em p = "1" (if do ub le b u f f ering is en ab l e d ) (if th ere is d a ta in bu f f er 2) hs clk 0 inpu t ( < sc l k s> = 0 ris i ng ed ge m ode) hs clk 0 inpu t ( < sc l k s> = 1 f alling e dge m ode) bit 0 bit 1 ht x d 0 (hnt t x 0 int e rrupt reques t ) bit 5 b i t 6 bit 7 t r ansm i t da t a w r it e t i m i ng 1 a tbru n tbe m p p e r r (functi ons to det ect und er- r un e rro rs) < w bu f> = " 1 " (i f d o u b l e bu f f eri n g i s ena b l e d) (i f t h ere i s no dat a i n bu f f er 2) fig. 14-2 2 send ope r ation in the i/o inte rface m ode (hsclk 0 inpu t mode) tmp19a43 (rev2.0) 14-29 serial chann el (hsio )
tmp19a43 d receiving data hscl k out put m ode in the hsclk output m ode, if hsc0m o d2 < w b u f> = " 0 " a n d receive double buf f eri n g is di sabl e d , a sy n c hr o n o u s cl oc k p u l s e i s o u t p ut fr om t h e hsclk 0 pi n an d t h e ne xt dat a i s shi f t e d into receive buf fe r 1 eac h time the cpu rea d s recei ve d data. when all t h e 8 bits a r e rec e ived, t h e hi ntrx 0 i n t e rr upt i s ge nerat e d. the fi rst h s c l k out put ca n be st art e d by set t i ng t h e rec e i v e ena b l e bi t hsc 0 mo d0 to "1 ." if t h e receiv e dou b l e bu f f eri n g is en ab led w ith h s c0 mod 2 set to "1 ," t h e first fram e receive d is m oved to recei ve buf f e r 2 and recei ve buf fe r 1 can recei ve t h e next fram e successi vely . as data is m o ved from receive buf f e r 1 to re ceive buf f er 2, the receive buf f er full flag h s c0 mod 2 is set to "1 " and t h e hin t rx0 interrup t is g e n e rated . while data is in recei ve buf fer 2, if cpu/dmac ca nnot read data from receive buf f er 2 i n tim e before com p leting reception of t h e ne xt 8 bits, the hintrx0 i n terrupt is not ge nerate d a n d the hsclk0 cl oc k stops. in this state, reading data from receive buf f er 2 allows data in rec e ive buf f er 1 to m ove to receive buf f er 2 a n d thus t h e hi ntr x 0 int e rrupt is ge ne rated and data reception resum e s. rec e ive dat a w r it e t i m i ng h s clk 0 out pu t bi t 0 bit 6 b it 7 bit 1 hr x d 0 ( h in trx 0 in te r r u p t r e qu e s t) bit 0 < w bu f> = " 0 " (i f d o u b l e bu f f eri n g i s di sa bl ed) rec e i v e dat a read t i m i ng hs cl k 0 out pu t bi t 0 bi t 6 b i t 7 bi t 1 hr x d 0 (h i n t r x0 i n te rr upt re qu es t) bi t 0 rb f u ll bi t 7 < w bu f> = " 1 " (i f d o u b l e bu f f eri n g i s ena b l e d) (i f dat a i s r ead fr om buf fe r 2) tmp19a43 (rev2.0) 14-30 serial chann el (hsio )
tmp19a43 rec e i v e dat a read t i m i ng hs c l k 0 out pu t bi t 0 bi t 6 b i t 7 bi t 1 hr x d 0 (h i n t r x0 i n te rr upt re qu es t) rb f u ll bi t 7 < w bu f> = " 1 " (i f d o u b l e bu f f eri n g i s ena b l e d) (i f dat a ca n not be rea d f r o m buf fe r 2) fig. 14-2 3 re ceive op erati on in the i/o interface mod e (hs c lk0 o u tput mode ) hscl k i n p u t m ode in t h e hsclk input m ode, s i nce r ecei ve double buf f e r ing is always e n abled, the rece ived fram e can be m oved t o receive buf f e r 2 a n d receive bu f f er 1 can re ceive the ne xt fram e successively . the hintrx0 receive interrupt is gene rated each tim e received data is m o ved t o receive d buf f e r 2. hs clk 0 i npu t ( < sc l ks> = 0 ri s i ng edge m ode) hs clk 0 i npu t ( < sc l ks> = 1 f al l i ng edge m ode) bi t 0 bi t 1 hr x d 0 (hntr x 0 i n t e rrupt reques t ) bi t 5 b i t 6 bi t 7 rec e i v e dat a read t i m i ng bi t 0 rb full if dat a i s read f r om bu f f e r 2 hs clk 0 i npu t ( < sc l ks> = 0 ri s i ng edge m ode) hs clk 0 i npu t ( < sc l ks> = 1 f al l i ng edge m ode) bi t 0 bi t 1 hr x d 0 (hi n t r x 0 i n t e rrupt reques t ) bi t 5 b i t 6 bi t 7 rec e i v e dat a read t i m i ng bi t 0 rb full oe rr if dat a ca nn ot be read f r om b u f f er 2 fig. 14-2 4 re ceive op erati on in the i/o interface mod e (hs c lk0 input mode ) (no t e ) t o rec e iv e d a t a , hs c0m o d must al w a y s be set to "1 " (receiv e enable) re gardl ess o f the hs cl k input or ou tp ut mode. tmp19a43 (rev2.0) 14-31 serial chann el (hsio )
tmp19a43 e send a n d recei ve (full-duplex) th e fu ll-d u p l ex m o d e is en ab led b y settin g b it 6 o f t h e serial m o d e con t ro l reg i ster 1 (h sc0 m od1 ) to "1 ." hscl k out put m ode in t h e hsclk output m ode, if hsc 0 mod2 < w b u f> is set to "0" a n d bot h the send and recei ve d oub le bu f f ers are d i sab l ed , h s clk is ou tpu t wh en the cpu w r ites d a ta to t h e sen d bu f f er . subseque ntly , 8 bits of data a r e s h ifted int o recei ve buf f er 1 a n d the hintrx0 recei ve interrupt is g e n e rated. co ncu r ren tly , 8 b its of d a ta w r itten t o th e sen d b u f f er are ou tpu t fro m th e htx d 0 p i n , th e hin t tx 0 send in terru p t is g e n e rated wh en tran sm issi o n of all d a ta b its h a s b een co m p leted . the n , t h e hs clk o u t p ut st ops . i n t h i s , t h e ne xt ro u n d o f dat a t r a n sm i s si on an d rece p t i on st a r t s w h en t h e d a ta i s read fro m th e receiv e bu f f er an d t h e n e x t sen d d a ta is w r itten to t h e sen d b u f f er b y th e cpu. th e o r d e r of readin g t h e recei ve bu f f er and w r iting to t h e send buf fer can b e freely d e term in ed . data tran sm issio n is resu m e d on ly wh en bo th co nd itio ns are satisfied . if hsc0 mo d2 = "1 " an d dou b l e buf fering is en ab led fo r bo th tran smissio n an d reception, hsclk is out put whe n the cpu writes data t o t h e send buf f er . subse q uently , 8 bits of data a r e s h ifte d i n to recei ve buf f e r 1, m o ved t o receive buf f e r 2, a n d t h e hintr x 0 interrupt is gene rated. while 8 bits of da ta is receive d, 8 b its of tra n s m it data is out put from the htxd0 pin. w h en all d a ta b its are sen t ou t, th e hin t tx 0 in t e r r u p t i s ge nerat e d a n d t h e next dat a i s m oved fr om t h e send bu f f e r 2 t o se n d b u f fe r 1 . i f s e nd b u f f er 2 h a s n o dat a t o b e m oved t o se nd b u f f er 1 (hsc 0mod2 = 1) or whe n recei ve buf fe r 2 is full (hsc0m od2 = 1), the hsclk cl ock is stoppe d . when bot h c o nditions a r e satis fied, i.e., receive data is rea d and send d a ta is w r itten , th e h s clk ou tpu t is resu m e d an d th e n e x t roun d of d a ta tran sm issio n is started . rec e i v e dat a read t i m i ng hs c l k 0 out pu t bi t 0 bi t 6 b i t 7 bi t 1 ht x d 0 ( h in t t x 0 in te r r u p t r e qu e s t) bi t 0 transm i t da t a w r i te ti m i n g ( h in t r x 0 in te r r u p t r e qu e s t) bi t 5 bi t 1 bi t 0 bi t 6 b i t 7 bi t 1 hr x d 0 bi t 0 bi t 5 bi t 1 < w bu f> = " 0 " (i f d o u b l e bu f f eri n g i s di sa bl ed) tmp19a43 (rev2.0) 14-32 serial chann el (hsio )
tmp19a43 rec e i v e dat a read t i m i ng hs clk 0 out pu t bi t 0 bi t 6 b i t 7 bi t 1 ht x d 0 (hi n t t x 0 i n t e rrupt reques t ) bi t 0 transm i t da t a w r i te ti m i n g (hi n t r x 0 i n t e rrupt reques t ) bi t 5 bi t 1 bi t 0 bi t 6 b i t 7 bi t 1 hr x d 0 bi t 0 bi t 5 bi t 1 = "1" (if do ub le b u f f ering is en ab l e d ) rec e i v e dat a read t i m i ng hs clk 0 out pu t bi t 0 bi t 6 b i t 7 bi t 1 ht x d 0 (hi n t t x 0 i n t e rrupt reques t ) transm i t da t a w r i te ti m i n g (hi n t r x 0 i n t e rrupt reques t ) bi t 5 bi t 0 bi t 6 b i t 7 bi t 1 hr x d 0 bi t 5 = "1" (if do ub le b u f f ering is en ab l e d ) fig. 14-2 5 send/re ceive o peratio n in the i/o interface mode (hsclk0 output mode ) hscl k i n p u t m ode in t h e h s clk in pu t m o d e with h s c0 mod2 set to "0 " and the send d oub le b u f f ers are d i sab l ed (d ouble b u f f ering is alw a ys en ab led fo r t h e recei v e sid e ), 8 - b it d a ta written in th e send buf f e r is output from the htxd0 pi n a nd 8 bits of data is shifted i n to the receive buf f e r whe n the hscl k i n p u t bec o m e s act ive. the h i nt tx 0 i n t e rr upt i s ge ne rat e d up o n c o m p l e t i on o f dat a transm ission and t h e hintr x 0 i n terrupt is gene ra ted at the instant the receive d data is m oved fro m receiv e bu f f er 1 t o receiv e bu f f er 2. n o te t h at transmit d a ta m u st b e w r itten in t o th e send b u f f er b e fore t h e h s clk inp u t fo r t h e n e x t fram e (d ata m u st b e written b e fo re th e p o i n t a). a s double buf f eri n g is ena b led for da ta rece ption, data m u st be r ead be fore com p leting reception of t h e ne xt fram e dat a . if hsc0 mo d2 = "1 " an d dou b l e buf fering is en ab led fo r bo th tran smissio n an d reception, t h e interrupt hintrx0 is gene rated at the timing se nd buf f e r 2 data is m o ved t o send bu f f e r 1 a f t e r c o m p l e t i ng dat a t r ansm i ssi on f r om send b u f fe r 1. at t h e sam e t i m e , t h e 8 bi t s of dat a receive d is s h ifted to buf f er 1, m oved to rec e i ve buf f e r 2, a n d the hintr x 0 inte rrupt is ge ne rated. up o n t h e hs clk i n put fo r t h e ne xt f r am e, t r ansm i ssi on fr om send b u f fe r 1 (i n whi c h dat a has been m ove d f r om sen d b u f f er 2) i s st art e d w h i l e rec e i v e dat a i s shi f t e d i n t o re cei v e b u f fe r 1 sim u l t a neousl y . if dat a i n re cei ve b u f f er 2 has not been read when t h e last bit of t h e fram e is receiv e d , an ov errun error occu rs. similarly , if t h ere is n o d a ta w r itten t o send bu f f er 2 wh en hscl k f o r t h e ne xt f r am e i s i n p u t , a n u nde r - r u n er ro r occ u rs . tmp19a43 (rev2.0) 14-33 serial chann el (hsio )
tmp19a43 rec e i v e dat a read t i m i ng hs clk 0 i nou t bi t 0 bi t 6 b i t 7 bi t 1 ht x d 0 ( h in ttx 0 i n t e rrupt reques t ) bi t 0 t r ansm i t da t a w r i te ti m i n g (hi n t r x 0 i n t e rrupt reques t ) bi t 5 bi t 1 bi t 0 bi t 6 b i t 7 bi t 1 hr x d 0 bi t 0 bi t 5 bi t 1 < w bu f> = " 0 " (i f d o u b l e bu f f eri n g i s di sa bl ed) rec e i v e dat a read t i m i ng hs clk 0 i npu t bi t 0 bi t 6 b i t 7 bi t 1 ht x d 0 ( h in ttx 0 i n t e rrupt reques t ) bi t 0 transm i t da t a w r i te ti m i n g (hi n t r x 0 i n t e rrupt reques t ) bi t 5 bi t 1 bi t 0 bi t 6 b i t 7 bi t 1 hr x d 0 bi t 0 bi t 5 bi t 1 < w buf> = " 1 " (if double buf f ering is ena b l e d) (no errors ) tmp19a43 (rev2.0) 14-34 serial chann el (hsio )
tmp19a43 rec e i v e dat a read t i m i ng hs clk 0 i npu t bi t 0 bi t 6 b i t 7 bi t 1 ht x d 0 ( h in ttx 0 i n t e rrupt reques t ) bi t 0 t r ansm i t da t a w r i te ti m i n g (hi n t r x 0 i n t e rrupt reques t ) bi t 5 bi t 1 bi t 0 bi t 6 b i t 7 bi t 1 hr x d 0 bi t 0 bi t 5 bi t 1 p e rr (under-run error) < w bu f> = " 1 " (i f d o u b l e bu f f eri n g i s ena b l e d) (e rr or ge ne rat i o n ) fig. 14-2 6 send/re ceive o peratio n in t he i/o interface mode (hsclk0 input mo de) tmp19a43 (rev2.0) 14-35 serial chann el (hsio )
tmp19a43 14.3.2 mode 1 (7-bit uart mo de) the 7- bi t ua r t m ode ca n be sel ect ed by set t i ng t h e se r i al m ode co nt r o l re gi st er ( h s c 0mo d ) t o " 0 1." in t h is m o d e , p a rity b its can b e add e d to t h e tran sm it d a ta stream; th e serial m o d e co n t ro l reg i ster (h sc0 cr ) co n t ro ls t h e p a rity en able/d isab le se ttin g. w h en is set to "1 " (en a b l e), either even o r o d d pa ri t y m a y be sel ect ed usi n g t h e hsc 0 cr bi t . t h e l e ngt h o f t h e st op bi t can be specified using hsc 0 mod2< s blen> . 14.3.3 mode 2 (8-bit uart mo de) the 8 - bi t u a r t m ode ca n be sel ect ed by set t i ng hsc 0 mod 0 t o "1 0." in t h i s m ode, pari t y bi t s can be a d d e d an d pa ri t y enabl e / d i s a b l e i s cont rol l e d usi ng hsc 0 cr . i f = "1" (e nabl e d ), either e v en or odd pa rity can be selected usi n g hsc0cr < e ven>. 14.3.4 mode 3 (9-bit uart) the 9 - bi t ua r t m ode can be sel ect ed by set t i ng hsc 0 mod 0 < s m1: 0 > t o " 1 1 . " in t h i s m ode, pari t y bi t s m u st be di sabl ed ( h sc 0 cr = " 0 "). th e m o st significan t b it (9 t h b it) is w r itten to b it 7 o f th e serial m o d e co n t ro l reg i ster 0 (h sc0 m od0 ) for tran sm it d a ta an d it is st o r ed in b it 7 of th e serial co n t ro l reg i ster h s c0 cr u pon receiv i ng d a ta. w h en writin g or read i n g d a ta to / f ro m th e buf fers, th e m o st sig n i fican t b it m u st b e w r itten or read first b e fore writin g or read i n g to / fro m h s c0 buf . th e sto p b it leng th can b e sp ecified usi n g hsc 0 mod 2 < s blen >. w a keu p f unct i on in t h e 9- bi t u a r t m ode, sl a v e c o nt r o l l e rs can be o p e r at ed i n t h e wa ke- u p m ode by se t t i ng t h e wake - u p fun c tion co n t ro l b it h s c0 mo d0 to "1 ." in th is case, th e i n terrupt h i n t rx0 will b e g e n e rated only whe n hsc0cr is set to " 1 ." htxd hrxd h t x d h r x d hrxd htxd hrxd slave 3 slave 2 slave 1 master htxd (no t e ) the htx d pin of the slav e contr o ller must be se t to the op en drain outpu t mode using the ode regis t er . fig. 14-2 7 serial lin ks to use w a ke-up functio n tmp19a43 (rev2.0) 14-36 serial chann el (hsio )
tmp19a43 prot oc ol c select th e 9 - b it ua r t m o d e fo r the m a ster and slave controllers. d set hsc 0 mod < w u> to " 1 " for t h e sla v e cont ro llers to make them ready to receive data. e th e m a ster con t ro ller is to sen d a sing le frame o f d a ta th at in clud es th e sl ave c o ntroller select code (8 b its). in t h is, th e m o st sig n i fican t b it (b it 8) m u st b e set t o "1 ." s l ave c o n t rol l er s e l e ct c ode s t ar t bi t 0 1 2 3 5 4 6 s t op 7 8 "1 " f every sla v e c ont roller recei ves the above data fram e; if the c o de re ceived m a tches with t h e co n t ro ller's own select co d e , i t clears th e w u b it to "0 ." g th e m a ster con t ro ller transmits d a ta to th e d e si g n at ed sl ave c ont r o l l e r (t he c ont rol l e r of w h i c h h s c0 mod b it is cleared to "0 "). in th is, th e m o st sig n i fican t b it (b it 8) m u st b e set to "0." data "0 " s t ar t bi t 0 1 2 3 5 4 6 s t op 7 bi t 8 h the slave c o ntrollers with t h e < w u> bit set t o " 1 " ignore the recei ve data beca use the m o st sig n i fican t b it (b it 8) is set to "0 " a nd th us n o in terrup t (h in trx 0 ) is g e n e rated . a l so , th e slav e con t ro ller w ith the b i t set to "0 " can tran sm it d a ta to the m a ster con t ro ller to inform that the data has bee n success f ully re ceived. exam ple setting: using t h e inte rnal cl ock f sys as the t r ans f er cloc k, two slave c ontrolle rs a r e serially lin k e d as fo llo ws: hrxd htxd h t x d h r x d slave 1 master slave 2 hrxd htxd select code 00001010 select code 00000001 tmp19a43 (rev2.0) 14-37 serial chann el (hsio )
tmp19a43 tmp19a43(rev2.0) 15-1 serial bus interface (sbi) 15. serial bus interface (sbi) the tmp19a43 contains a serial bus interface (sbi) channel, which has the following two operating modes: ? i 2 c bus mode (with multi-master capability) ? clock-synchronous 8-bit sio mode in the i 2 c bus mode, the sbi is connected to external devi ces via pc5 (sda) and pc7 (scl). in the clock- synchronous 8-bit sio mode, the sbi is connected to external devices via pc7 (sck), pc5 (so) and pc6 (si). the following table shows the programming required to put the sbi in each operating mode. pcode pccr pcfc i2c bus mode 11 x11 011 clock-synchronous 8-bit sio mode xx 101 (clock output) 001 (clock input) 111 x: don't care 15.1 configuration the configuration is shown in fig. 15.1. fig. 15.1 sbi block diagram i 2 c bus clock synchroni- zation + control noise canceller shift register sbicr2/ sbisr sbidbr ints0 interrupt request fsys/4 sbi control register 2/ sbi status register i 2 c bus address register sbi data buffer register sbi control registers 0 and 1 sbi baud rate register 0 sda so si scl sck pc7 pc5 pc6 (sck) (so/sda) (si/scl) sio clock control frequency divider transfer control circuit sbicr0,1 sbibr0 i2car noise canceller i 2 c bus data control sio data control input/ output control
tmp19a43 tmp19a43(rev2.0) 15-2 serial bus interface (sbi) 15.2 control the following registers control the serial bus interface and provide its status information for monitoring. ? serial bus interface control register 0 (sbicr0) ? serial bus interface control register 1 (sbicr1) ? serial bus interface control register 2 (sbicr2) ? serial bus interface buffer register (sbidbr) ? i 2 c bus address register (i2car) ? serial bus interface status register (sbisr) ? serial bus interface baud rate register 0 (sbibr0) the functions of these registers vary, depending on the mode in which the sbi is operating. for a detailed description of the registers, refer to "3.12.4 control in the i 2 c bus mode" and "3.12.7 control in the clock- synchronous 8-bit sio mode." 15.3 i 2 c bus mode data formats fig. 15.1 shows the data formats used in the i 2 c bus mode. fig. 15.2 i 2 c bus mode data formats note: s: start condition w / r : direction bit ack: acknowledge bit p: stop condition r / w r / w s (a) addressing format (b) addressing format (wi th repeated start condition) (c) free data format (master-tr ansmitter to slave-receiver) slave address data p s s sp p 8 bits 1 to 8 bits 1 once repeated 1 to 8 bits a c k slave address data data once once a c k a c k 8 bits 1 to 8 bits 8 bits 1 to 8 bits 11 1 1 1 1 8bits 1 to 8 bits 1 to 8 bits data data data data a c k 1 1 1 slave address repeated once repeated repeated r / w a c k a c k a c k a c k a c k a c k
tmp19a43 tmp19a43(rev2.0) 15-3 serial bus interface (sbi) 15.4 control registers in the i 2 c bus mode the following registers control the se rial bus interface (sbi) in the i 2 c bus mode and provide its status information for monitoring. serial bus interface control register 0 7 6 5 4 3 2 1 0 bit symbol sbien read/write r/w r after reset 0 0 function sbi operation 0: disable 1: enable this can be read as "0." : to use the sbi, enable the sbi operat ion ("1") before setting each register in the sbi module. fig. 15.3 i 2 c bus mode register sbicr0 (0xffff_f257)
tmp19a43 tmp19a43(rev2.0) 15-4 serial bus interface (sbi) serial bus interface control register 1 7 6 5 4 3 2 1 0 bit symbol bc2 bc1 bc0 ack sck2 sck1 sck0/ swrmon read/write r/w r/w r r/w r/w after reset 0 0 0 0 1 0 0 1 function select the number of bits per transfer (note 1) acknow- ledgment clock 0: not generate 1: generate this can be read as "1." select internal scl output clock frequency (note 2) and reset monitor on writing : select internal scl output clock frequency 000 001 010 011 100 101 110 111 n=5 n=6 n=7 n=8 n=9 n=10 n=11 196 khz 149 khz 101 khz 61 khz 34 khz 18 khz 9 khz reserved system clock : fsys (=40 mhz) clock gear : fc/1 frequency = [hz] on reading : softwa re reset status monitor 0 software reset operation is in progress. 1 software reset operation is not in progress. select the number of bits per transfer when = 0 when = 1 number of clock cycles data length number of clock cycles data length 000 001 010 011 100 101 110 111 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 9 2 3 4 5 6 7 8 8 1 2 3 4 5 6 7 (note 1) clear to "000" before switchi ng the operation mode to the clock-synchronous 8-bit sio mode. (note 2) for details on the scl line clock frequency, refer to "3.12.5 (3) serial clock." (note 3) after a reset, the bit is read as "1." however, if the sio mode is selected at the sbicr2 register, the initial value of the bit is "0." fig. 15.4 i 2 c bus mode register fsys/2 2 n + 70 sbicr1 (0xffff_f250)
tmp19a43 tmp19a43(rev2.0) 15-5 serial bus interface (sbi) serial bus interface control register 2 7 6 5 4 3 2 1 0 bit symbol mst trx bb pin sbim1 sbim0 swrst1 swrst0 read/write w w (note 1) w (note 1) after reset 0 0 0 1 0 0 0 0 function select master/slave 0: slave 1: master select transmit/ receive 0: receive 1: transmit start/stop condition generation 0: stop condition generated 1: start condition generated clear ints0 interrupt request 0: ? 1: clear interrupt request select serial bus interface operating mode (note 2) 00: port mode 01: sio mode 10: i 2 c bus mode 11: (reserved) software reset generation write "10" followed by "01" to generate a reset. select serial bus interface operating mode (note 2) 00 port mode (serial bus in terface output disabled) 01 clock-synchronous 8-bit sio mode 10 i 2 c bus mode 11 (reserved) (note 1) reading this register causes it to function as the sbisr register. (note 2) ensure that the bus is free before switching the operating mode to the port mode. ensure that the port is at the "h" level before switch ing the operating mode from the port mode to the i 2 c bus or clock-synchronous 8-bit sio mode. (note 3) ensure that serial transfer is completed before switching the mode. fig. 15.5 i 2 c bus mode register table 15.1 base clock resolution @fsys = 40 mhz clock gear value base clock resolution 00 (fc) fsys/2 2 (0.1 s) 01 (fc/2) fsys/2 3 (0.2 s) 10 (fc/4) fsys/2 4 (0.4 s) 11 (fc/8) fsys/2 5 (0.8 s) sbicr2 (0xffff_f253)
tmp19a43 tmp19a43(rev2.0) 15-6 serial bus interface (sbi) serial bus interface status register 7 6 5 4 3 2 1 0 bit symbol mst trx bb pin al aas ad0 lrb read/write r after reset 0 0 0 1 0 0 0 0 function master/ slave selection monitor 0: slave 1: master transmit/ receive selection monitor 0: receive 1: transmit i 2 c bus state monitor 0: free 1: busy ints0 interrupt request monitor 0: interrupt request generated 1: interrupt request cleared arbitration lost detection 0: ? 1: detected slave address match detection 0: ? 1: detected general call detection 0: ? 1: detected last received bit monitor 0: "0" 1: "1" last received bit monitor 0 the last bit received was "0." 1 the last bit received was "1." addressed as slave 0 ? 1 addressed as slave or general call detected arbitration lost 0 ? 1 arbitration was lost to another master (note) writing to this register causes it to function as sbicr2. fig. 15.6 i 2 c bus mode register sbisr (0xffff_f253)
tmp19a43 tmp19a43(rev2.0) 15-7 serial bus interface (sbi) serial bus interface baud rate register 0 7 6 5 4 3 2 1 0 bit symbol i2sbi0 read/write r r/w r r/w after reset 1 0 1 0 function this can be read as "1." idle 0: stop 1: operate this can be read as "1." make sure that you write "0." (note) operation in the idle mode 0 stop 1operate (note) this is read as "1" in the sio mode. serial bus interface data buffer register 7 6 5 4 3 2 1 0 bit symbol db7 db6 db5 db4 db3 db2 db1 db0 read/write r (receive)/w (transmit) after reset 0 (note) transmit data must be wri tten to this register, with bit 7 being the most-significant bit (msb). i 2 c bus address register 7 6 5 4 3 2 1 0 bit symbol sa6 sa5 sa4 sa3 sa2 sa1 sa0 als read/write r/w after reset 0 0 0 0 0 0 0 0 function set the slave address when the sbi acts as a slave device. specify address recognition mode specify address recognition mode 0 recognizes the slave address. 1 does not recogniz e slave address. fig. 15.7i 2 c bus mode register sbibr0 (0xffff_f254) i2car (0xffff_f252) sbidbr (0xffff_f251) ( note ) please set the bit of i2c bus address register i2car to "0" about 0< als >, except when you use the free data format. it operates as a free data format when setting it to ?1", it fixes to the transmission at the master, and the direction of forwarding is fixed to the reception at the slave.
tmp19a43 tmp19a43(rev2.0) 15-8 serial bus interface (sbi) control in the i 2 c bus mode 15.4.1 setting the acknowledgement mode setting sbicr1 to "1" selects the acknowledg e mode. when operating as a master, the sbi adds one clock for acknowledgment signals. as a tr ansmitter, the sbi releases the sda pin during this clock cycle to receive acknowledgment signals from the receiver. as a receiver, the sbi pulls the sda pin to the "l" level during this clock cycle and generates acknowledgment signals. setting to "0" selects the non-acknowledgmen t mode. when operating as a master, the sbi does not generate clock for acknowledgement signals. 15.4.2 setting the number of bits per transfer sbicr1 specifies the numb er of bits of the next data to be transmitted or received. under the start condition, is set to "000," causing a slave address and the direction bit to be transferred in a packet of eight bits. at other times, keeps a previously programmed value. 15.4.3 serial clock c clock source sbicr1 specifies the maximum frequency of the serial clock to be output from the scl pin in the master mode. fig. 15.8 clock source the highest speeds in the standard and high-speed modes are specified to 100khz and 400khz respectively in the communications standards. note that the internal scl clock frequency is determined by the fsys used and the calculation formula shown above. t high t low 1/fscl t low = 2 n-1 /(fsys/2) + 58/(fsys/2) t high = 2 n-1 /(fsys/2) + 12/(fsys/2) fscl = 1/(t low + t high ) sbi0cr1 n 000 001 010 011 100 101 110 5 6 7 8 9 10 11 = fsys/2 2 n + 70
tmp19a43 tmp19a43(rev2.0) 15-9 serial bus interface (sbi) d clock synchronization the i 2 c bus is driven by using the wired-and connection due to its pin structure. the first master that pulls its clock line to the "l" level overrides other masters producing the "h" level on their clock lines. this must be detected and responded by the masters producing the "h" level. clock synchronization assures correct data transfer on a bus that has two or more masters. for example, the clock synchron ization procedure for a bus with two masters is shown below. fig. 15.9 example of clock synchronization at point a, master a pulls its internal scl output to the "l" level, bringing the scl bus line to the "l" level. master b detects this transition, resets its "h" level peri od counter, and pulls its internal scl output level to the "l" level. master a completes counting of its "l" level period at point b, and brings its internal scl output to the "h" level. however, master b still keeps the scl bus line at the "l" level, and master a stops counting of its "h" level period counting. after mast er a detects that master b brings its internal scl output to the "h" level and brings the scl bus line to the "h" level at point c, it starts counting of its "h" level period. this way, the clock on the bus is determined by th e master with the shortest "h" level period and the master with the longest "l" level period among those connected to the bus. 15.4.4 slave addressing and address recognition mode when the sbi is configured to operate as a slav e device, the slave address and must be set at i2car. setting to "0" selects the address recognition mode. 15.4.5 configuring the sbi as a master or a slave setting sbicr2 to "1" configures the sbi to operate as a master device. setting to "0" configures the sbi as a slave de vice. is cleared to "0" by the hardware when the stop condition has been detected on the bus or when arbitration has been lost. internal scl output (master a) internal scl output (master b) scl line reset high-level period counting wait for high-level period counting start high-level period counting a b c
tmp19a43 tmp19a43(rev2.0) 15-10 serial bus interface (sbi) 15.4.6 configuring the sbi as a transmitter or a receiver setting sbicr2 to "1" configures the sbi as a transmitter. setting to "0" configures the sbi as a receiver. in the slave mode, the sbi receives the direction bit ( w r/ ) from the master device on the following occasions: ? when data is transmitted in the addressing format ? when the received slave address matc hes the value specified at i2ccr ? when a general-call address is received; i.e. , the eight bits followi ng the start condition are all zeros if the value of the direction bit ( w r/ ) is "1," is set to "1" by the hardware. if the bit is "0," is set to "0." as a master device, the sbi receives acknowledgement from a slave device. if the direction bit of "1" is transmitted, is set to "0" by the hardware. if the direction bit is "0," changes to "1." if the sbi does not receive acknowledgement , retains the previous value. is cleared to "0" by the hardware when the stop condition has been detected on the bus or when arbitration has been lost. 15.4.7 generating start and stop conditions when sbisr is "0," writing "1" to sbicr2 causes the sbi to generate the start condition on the bus and output 8-bit data. must be set to "1" in advance. fig. 15.10 generating the start condition and a slave address when is "1," writing "1" to and "0" to causes the sbi to start a sequence for generating the stop condition on the bus. the contents of should not be altered until the stop condition appears on the bus. fig. 15.11 generating the stop condition sbisr can be read to check the bus state. is set to "1" when the start condition is detected on the bus (the bus is busy), and set to "0" when the stop condition is detected (the bus is free). scl line start condition a6 slave address and direction bit a cknowledgment signal 1 sda line 234567 8 9 a5 a4 a3 a2 a1 a0 r/w stop condition scl line sda line
tmp19a43 tmp19a43(rev2.0) 15-11 serial bus interface (sbi) 15.4.8 interrupt service request and release when a serial bus interface interrup t request (ints0) is generated, sb icr2 is cleared to "0." while is "0," the sbi pulls the scl line to the "l" level. after transmission or reception of one data word, is cleared to "0." it is set to "1" when data is written to or read from sbidbr. it takes a period of t low for the scl line to be released after is set to "1." in the address recognition mode ( = "0"), is cleared to "0" when the received slave address matches the value specified at i2car or when a general-call ad dress is received; i.e., the eight bits following the start condition are all zeros. when the program writes "1" to sbicr2, it is set to "1." however, writing "0" does clear this bit to "0." 15.4.9 serial bus interface operating modes sbicr2 selects an operating mode of the serial bus interface. must be set to "10" to configure the sbi for the i 2 c bus mode. make sure that the bus is free before switching the operating mode to the port mode. 15.4.10 lost-arbitration detection monitor the i 2 c bus has the multi-master capability (there are tw o or more masters on a bus), and requires the bus arbitration procedure to en sure correct data transfer. a master that attempts to generate the start condition while the bus is busy loses bus arbitration, with no start condition occurring on th e sda and scl lines. the i 2 c-bus arbitration takes place on the sda line. the arbitration procedure for two masters on a bus is shown below. up until point a, master a and master b output the same data. at point a, master a outputs the "l" level and master b outputs the "h" level. then master a pulls the sda bus line to the "l" level because the line has the wired-and connection. when the scl line goes high at point b, the slave de vice reads the sda line data, i.e., data transmitted by master a. at this time, data transm itted by master b becomes invalid. in other words, master b loses arbitration. master b releases its sd a pin, so that it does not affect the data transfer initiated by another master. if two or more masters have transmitted exactly the same first data word, the arbitration procedure continues with the second data word. fig. 15.12 lost arbitration loses arbitration and sets the internal sda output to "1." scl line internal sda output (master a) internal sda output (master b) sda line ab
tmp19a43 tmp19a43(rev2.0) 15-12 serial bus interface (sbi) a master compares the sda bus line level and the in ternal sda output level at the rising of the scl line. if there is a difference between these two va lues, the master loses arbitration and sets sbi0sr to "1." when is set to "1," sbisr are clear ed to "0," causing the sbi to operate as a slave receiver. is cleared to "0" when data is wr itten to or read from sbidbr or data is written to sbicr2. fig. 15.13 example of master b losing arbitration (d7a = d7b, d6a = d6b) 15.4.11 slave address match detection monitor when the sbi operates as a slave device in the address recognition mode (i2ccr = "0"), sbisr is set to "1" on receiving the general- call address or the slave address that matches the value specified at i2ccr. when is "1," is set to "1" when the first data word has been received. is cleared to "0" when data is written to or read from sbidbr. 15.4.12 general-call detection monitor when the sbi operates as a slave device, sbisr is set to "1" when it receives the general-call address; i.e., the eight bits followi ng the start condition are all zeros. is cleared to "0" when the start or stop condition is detected on the bus. 15.4.13 last received bit monitor sbisr is set to the sda line value that wa s read at the rising of the scl line. in the acknowledgment mode, reading sbisr immediately after generation of the ints0 interrupt request causes ack signal to be read. clock output stops here 1 internal sda output is held high because master b has lost arbitraiton. a ccess to sbidbr or sbicr2 internal scl output internal sda output internal sda output internal scloutput master a master b 23456789 1 2 34 d7a d6b d5a d4a d3a d2a d1a d0a d7a' d6a' d5a' d4a' 1 234 d7b d6a
tmp19a43 tmp19a43(rev2.0) 15-13 serial bus interface (sbi) 15.4.14 software reset if the serial bus interface circuit locks up due to exte rnal noise, it can be initialized by using a software reset. writing "10" followed by "01" to sbicr2 generates a reset signal that initializes the serial bus interface circuit. after a reset, all control registers and status flags are initialized to their reset values. when the serial bus interface is initia lized, is automatically cleared to "0." (note) a software reset causes the sbi operating mode to switch from the i 2 c mode to the port mode. 15.4.15 serial bus interface data buffer register (sbidbr) reading or writing sbidbr initiates r eading received data or writing transmitted data. when the sbi is acting as a master, setting a slave address and a di rection bit to this register generates the start condition. 15.4.16 i 2 c bus address register (i2car) when the sbi is configured as a slave device, the i2car bit is used to specify a slave address. if i2c0ar is set to "0," the sbi recognizes a slave address transmitted by the master device and receives data in the addressing format. if is set to "1," the sbi does not recognize a slave address and receives data in the free data format. 15.4.17 idle setting register (sbibr0) the sbibr0 register determines if the sbi ope rates or not when it enters the idle mode. this register must be programmed before executing an instruction to switch to the standby mode.
tmp19a43 tmp19a43(rev2.0) 15-14 serial bus interface (sbi) 15.5 data transfer procedure in the i 2 c bus mode 15.5.1 device initialization first, program sbicr1 by writing "0" to bits 7 to 5 and bit 3 in sbicr1. next, program i2car by specifying a slave address at and an address recognition mode at . ( must be set to"0" when using the addressing format.) next, program sbicr2 to initially configure the sbi in the slave receiver mode by writing "0" to , "1" to , "10" to and "0" to bits 1 and 0. 7 6 5 4 3 2 1 0 sbicr1 0 0 0 x 0 x x x specifies ack and scl clock. i2car x x x x x x x x specifies a slave address and an address recognition mode. sbicr2 0 0 0 1 1 0 0 0 configures the sbi as a slave receiver. (note) x: don't care 15.5.2 generating the start condition and a slave address c master mode in the master mode, the following steps are required to generate the start condition and a slave address. first, ensure that the bus is free ( = "0"). then, write "1" to sbicr1 to select the acknowledgment mode. write to sbidbr a slave ad dress and a direction bit to be transmitted. when = "0," writing "1111" to sbicr2 generates the start condition on the bus. following the start condition, the sbi generates nine clocks from the scl pin. the sbi outputs the slave address and the direction bit specified at sb idbr with the first eight clocks, and releases the sda line in the ninth clock to receive an acknowledgment signal from the slave device. the ints0 interrupt request is generated on the falling of the ninth clock, and is cleared to "0." in the master mode, the sbi holds the scl line at the "l" level while is "0." changes its value according to the transmitted direction bit at ge neration of the ints0 interrupt request, provided that an acknowledgment signal has been returned from the slave device. settings in main routine 7 6 5 4 3 2 1 0 reg. sbisr reg. reg. e 0x20 if reg. 0x00 ensures that the bus is free. then sbicr1 x x x 1 0 x x x selects the acknow ledgement mode. sbidr1 x x x x x x x x specifies the desired slav e address and direction. sbicr2 1 1 1 1 1 0 0 0 generates the start condition. example of ints0 interrupt routine intclr 0x78 clears the interrupt request. processing end of interrupt
tmp19a43 tmp19a43(rev2.0) 15-15 serial bus interface (sbi) d slave mode in the slave mode, the sbi receives the start condition and a slave address. after receiving the start condition from the master device, the sbi receives a slave address and a direction bit from the master devi ce during the first eight clocks on the scl line. if the received address matches its slave address specified at i2car or is equal to the general-call address, the sbi pulls the sda line to the "l" level during the ninth clock and outputs an acknowledgment signal. the ints0 interrupt request is generated on the falling of the ninth clock, and is cleared to "0." in the slave mode, the sbi holds the scl line at the "l" level while is "0." (note) the user can only use a dma transfer: ? when there is only one master and only one slave and ? continuous transmission or reception is possible. fig. 15.14 generation of the star t condition and a slave address 15.5.3 transferring a data word at the end of a data word transfer, the ints0 interrupt is generated to test to determine whether the sbi is in the master or slave mode. c master mode ( = "1") test to determine whether the sbi is configured as a transmitter or a receiver. transmitter mode ( = "1") test . if is "1," that means the recei ver requires no further data. the master then generates the stop condition as described later to stop transmission. if is "0," that means the receiver requires furt her data. if the next data to be transmitted has eight bits, the data is written into sbidbr. if the data has different length, and are programmed and the transmit data is written into sbidbr. writing the data makes to"1," causing the scl pin to generate a serial clock for transfer of a next data word, and the sda pin to transfer the data word. after the transf er is completed, the ints0 interrupt request is generated, is set to "0," and the scl pin is pulled to the "l" level. to transmit more data words, test again and repeat the above procedure. scl start condition a6 slave address + direction bit a cknowledgement from slave 1 sda 2 34567 8 9 a5 a4 a3 a2 a1 a0 w r/ ints0 interrupt request ack master to slave slave to master
tmp19a43 tmp19a43(rev2.0) 15-16 serial bus interface (sbi) ints0 interrupt if mst = 0 then go to the slave-mode processing if trx = 0 then go to the receiver-mode processing if lrb = 0 then go to processing for generating the stop condition sbicr1 x x x x 0 x x x specifies the number of bits to be transmitted and specify whethe r ack is required. sbidbr x x x x x x x x writes the transmit data. end of interrupt processing (note) x: don't care fig. 15.15 = "000" and = "1" (transmitter mode) receiver mode ( = "0") if the next data to be transmitted has eight bits, the transmit data is written into sbidbr. if the data has different length, and are programmed and the received data is read from sbidbr to release the scl line. (the data read immediately after transmission of a slave address is undefined.) on reading the data, is set to "1," and the serial clock is output to the scl pin to transfer the next data word. in the last bit, when the acknowledgment signal becomes the "l" level, "0" is output to the sda pin. after that, the ints0 interrupt request is generate d, and is cleared to "0," pulling the scl pin to the "l" level. each time the received data is read from sbidbr, one-word transfer clock and an acknowledgement signal are output. fig. 15.16 = "000" and = "1" (receiver mode) scl pin write to sbi0dbr d7 a cknowledgment signal from receiver 1 sda pin 2 345678 9 d6 d5 d4 d3 d2 d1 ints0 interrupt request ack master to slave slave to master d0 scl d7 a cknowledgment signal to transmitter 1 sda 2 345678 9 d6 d5 d4 d3 d2 d1 ints interrupt request ack master to slave slave to maste r d0 read the received data next d7
tmp19a43 tmp19a43(rev2.0) 15-17 serial bus interface (sbi) to terminate the data transmission from the transmitter, must be set to "0" immediately before reading the second to last data word. this disables generation of an acknowledgment clock for the last data word. when the transfer is comple ted, an interrupt request is generated. after the interrupt processing, must be set to "001" and the data must be read so that a clock is generated for 1-bit transfer. at this time, the master receiver holds the sda bus line at the "h" level, which signals the end of transfer to the transmitter as an acknowledgment signal. in the interrupt processing for terminating the reception of 1-bit data, the stop condition is generated to terminate the data transfer. fig. 15.17 terminating data transmission in the master receiver mode example: when receiving n data words ints0 interrupt (after data transmission) 7 6 5 4 3 2 1 0 sbicr1 x x x x 0 x x x sets the number of bits of da ta to be received and specify whether ack is required. reg. sbi0cbr reads dummy data. end of interrupt ints0 interrupt (first to (n-2)th data reception) 7 6 5 4 3 2 1 0 reg. sbidbr reads the first to (n-2)th data words. end of interrupt ints0 interrupt ( (n-1)th data reception) 7 6 5 4 3 2 1 0 sbi0cr1 x x x 0 0 x x x disables generation of acknowledgement clock. reg. sbidbr reads the (n-1)th data word. end of interrupt ints0 interrupt (nth data reception) 7 6 5 4 3 2 1 0 sbi0cr1 0 0 1 0 0 x x x generates a clock for 1-bit transfer. reg. sbidbr reads the nth data word. end of interrupt ints0 interrupt (after completing data reception) processing to generate the stop condition terminates the data transmission. end of interrupt (note) x: don't care scl d7 a cknowledgment signal to transmitter 1 sda 2 345678 1 d6 d5 d4 d3 d2 d1 ints0 interrupt request master to slave slave to master d0 read out the received data after clearing to "0." 9 read out the received data after setting to "001."
tmp19a43 tmp19a43(rev2.0) 15-18 serial bus interface (sbi) d slave mode ( = "0") in the slave mode, the sbi generates the ints0 in terrupt request on four occasions: 1) when the sbi has received any slave address from the mast er, 2) when the sbi has received a general-call address, 3) when the received slave address matche s its own address, and 4) when a data transfer has been completed in response to a general-call. also, if the sbi loses arbitration in the master mode, it switches to the slave mode. upon the completion of data word transfer in which arbitration is lost, the ints0 inte rrupt request is generated, is cleared to "0," and the scl pin is pulled to the "l" level. when data is wr itten to or read from sbidbr or when is set to "1," the scl pin is released after a period of t low . in the slave mode, the normal slave mode processing or the processing as a re sult of lost arbitration is carried out. sbisr , , and are tested to determine the processing required. table 15.1 shows the slave mode states and required processing. example: when the received slave a ddress matches the sbi's own address an d the direction bit is "1" in the slave receiver mode ints0 interrupt if trx = 0 then go to other processing if al = 1 then go to other processing if aas = 0 then go to other processing sbicr1 x x x 1 0 x x x sets the number of bits to be transmitted. sbidbr x x x x 0 x x x sets the transmit data. (note) x: don't care
tmp19a43 tmp19a43(rev2.0) 15-19 serial bus interface (sbi) table 15.1 processing in slave mode state processing 1 1 0 arbitration was lost while the slave address was being transmitted, and the sbi received a slave address with the direction bit "1" transmitted by another master. 1 0 in the slave receiver mode, the sbi received a slave address with the direction bit "1" transmitted by the master. set the number of bits in a data word to and write the transmit data into sbi0dbr. 1 0 0 0 in the slave transmitter mode, the sbi has completed a transmission of one data word. test lrb. if it has been set to "1," that means the receiver does not require further data. set to 1 and reset to 0 to release the bus. if has been reset to "0," that means the receiver requires further data. set the number of bits in the data word to and write the transmit data to the sbidbr. 1 1/0 arbitration was lost while a slave address was being transmitted, and the sbi received either a slave address with the direction bit "0" or a general-call address transmitted by another master. 1 0 0 arbitration was lost while a slave address or a data word was being transmitted, and the transfer terminated. 1 1/0 in the slave receiver mode, the sbi received either a slave address with the direction bit "0" or a general-call address transmitted by the master. read the sbidbr (a dummy read) to set to 1, or write "1" to . 0 0 0 1/0 in the slave receiver mode, the sbi has completed a reception of a data word. set the number of bits in the data word to and read the received data from sbidbr.
tmp19a43 tmp19a43(rev2.0) 15-20 serial bus interface (sbi) 15.5.4 generating the stop condition when sbisr is "1," writing "1" to sbicr2 and "0" to causes the sbi to start a sequence for generating the stop condition on the bus. do not alter the contents of until the stop condition appears on the bus. if another device is holding down the scl bus line, the sbi waits until the scl line is released. after that, the sda pin goes high, causing the stop condition to be generated. 7 6 5 4 3 2 1 0 sbicr2 1 1 0 1 1 0 0 0 generates the stop condition. fig. 15.18 generating the stop condition scl pin sda pin (read) stop condition "1" "1" "0" "1"
tmp19a43 tmp19a43(rev2.0) 15-21 serial bus interface (sbi) 15.5.5 repeated start procedure repeated start is used when a master device change s the data transfer direction without terminating the transfer to a slave device. the procedure of generatin g a repeated start in the master mode is described below. first, set sbicr2 to "0" and write "1" to to release the bus. at this time, the sda pin is held at the "h" level and the scl pin is released. because no stop condition is generated on the bus, other devices think that the bus is busy. then, test sbisr and wait until it becomes "0" to ensure that the scl pin is released. next, test and wait until it becomes "1" to ensure that no other device is pulling the scl bus line to the "l" level. once the bus is determined to be free this way, use the steps described above in (2) to generate the start condition. to satisfy the setup time of repeated start, at least 4.7- s wait period (in the standard mode) must be created by the software after the bus is determined to be free. 7 6 5 4 3 2 1 0 sbicr2 0 0 0 1 1 0 0 0 releases the bus. if sbisr 0 checks that the scl pin is released. then if sbisr 1 checks that no other device is pulling the scl pin to the "l" level. then 4.7 s wait sbicr1 x x x 1 0 x x x selects the acknowledgment mode. sbidbr x x x x x x x x sets the desired slave address and direction. sbicr2 1 1 1 1 1 0 0 0 generates the start condition. (note) x: don't care (note) do not write to "0" when it is "0." (repeated start cannot be done.) fig. 15.19 timing chart of generating a repeated start "0" "0" "0" "1" "1" "1" "1" "1" scl (bus) scl pin sda pin 4.7 s (min.) start condition 9
tmp19a43 tmp19a43(rev2.0) 15-22 serial bus interface (sbi) 15.6 control in the clock-sy nchronous 8-bit sio mode the following registers control the serial bus interface in the clock-synchronous 8-bit sio mode and provide its status information for monitoring. serial bus interface control register 0 7 6 5 4 3 2 1 0 bit symbol sbien read/write r/w r after reset 0 0 function sbi operation 0: disable 1: enable this can be read as "0." : to use the sbi, enable the sbi operation ("1") before setting each register of sbi module. serial bus interface control register 1 7 6 5 4 3 2 1 0 bit symbol sios sioinh siom1 siom0 sck2 sck1 sck0 read/write w r w r/w after reset 0 0 0 0 1 0 0 1 function start transfer 0: stop 1: start abort transfer 0: continue 1: abort select transfer mode 00: transmit mode 01: (reserved) 10: transmit/receive mode 11: receive mode this can be read as "1." select serial clock frequency on writing : select serial clock frequency 000 001 010 011 100 101 110 111 n = 3 n = 4 n = 5 n = 6 n = 7 n = 8 n = 9 ? 1.25 625 313 156 78 39 20 mhz khz khz khz khz khz khz system clock : fsys (=40 mhz) clock gear : fc/1 frequency = [hz] (note) set to "0" and to "1" before programming the transfer mode and the serial clock. serial bus interface data buffer register 7 6 5 4 3 2 1 0 bit symbol db7 db6 db5 db4 db3 db2 db1 db0 read/write r (receive)/w (transmit) after reset undefined fig. 15.20 sio mode registers external cloc k sbicr1 (0xffff_f250) fs y s/4 2 n sbidbr (0xffff_f251) sbicr0 (0xffff_f257)
tmp19a43 tmp19a43(rev2.0) 15-23 serial bus interface (sbi) serial bus interface control register 2 7 6 5 4 3 2 1 0 bit symbol sbim1 sbim0 read/write r w r after reset 1 0 0 1 function this can be read as "1." select serial bus interface operating mode 00: port mode 01: clock-synchronous 8-bit sio mode 10: i 2 c bus mode 11: (reserved) this can be read as "1." serial bus interface register 7 6 5 4 3 2 1 0 bit symbol siof sef read/write r r r after reset 1 0 0 1 function this can be read as "1." serial transfer status monitor 0: terminated 1: in progress shift operation status monitor 0: terminated 1: in progress this can be read as "1." serial bus interface baud rate register 0 7 6 5 4 3 2 1 0 bit symbol i2sbi read/write r r/w r w after reset 1 0 1 0 function this can be read as "1." idle 0: stop 1: operate this can be read as "1." make sure that you write "0." fig. 15.11 sio mode registers sbicr2 (0xffff_f253) sbisr (0xffff_f253) sbibr0 (0xffff_f254)
tmp19a43 tmp19a43(rev2.0) 15-24 serial bus interface (sbi) 15.6.1 serial clock c clock source internal or external clocks can be selected by programming sbicr1 . internal clocks in the internal clock mode, one of the seven frequencies can be selected as a serial clock, which is output to the outside through the sck pin. at the beginning of a transfer, the sck pin output becomes the "h" level. if the program cannot keep up with this serial clock rate in writing the transmit data or reading the received data, the sbi automatically enters a wait pe riod. during this period, the serial clock is stopped automatically and the next shift operation is suspended until the processing is completed. fig. 15.22 automatic wait external clock ( = "111") the sbi uses an external clock supplied from the outside to the sck pin as a serial clock. for proper shift operations, the serial clock at the "h" and "l" levels must have the pulse widths as shown below. fig. 15.23 maximum transfer frequency of external clock input sck pin output so pin output write the transmit data 3 1 7 2 8 1 2 6 7 8 1 2 3 c 0 a b c a utomatic wait a 0 a 1 a 2 a 5 a 6 a 7 b 0 b 5 b 6 b 7 c 1 c 2 b 1 b 4 t sck h t sckl , t sckh > 8/fsys sck pin t sck l
tmp19a43 tmp19a43(rev2.0) 15-25 serial bus interface (sbi) d shift edge leading-edge shift is used in transmission. trailing-edge shift is used in reception. leading-edge shift data is shifted at the leading edge of the serial clock (or the falling edge of the sck pin input/output). trailing-edge shift data is shifted at the trailing edge of the serial clock (or the rising edge of the sck pin input/output). fig. 15.24 shift edge bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 76543210 * 7654321 ** 765432 *** 76543 **** 7654 ***** 765 ****** 76 ****** 7 so pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 6543210 * 543210 ** 0 ******* 10 ****** 210 ***** 3210 **** 43210 *** ******** 76543210 sck pin shift register sck pin si pin shift register (a) leading-edge shift (b) trailing-edge shift (note) *: don't care
tmp19a43 tmp19a43(rev2.0) 15-26 serial bus interface (sbi) 15.6.2 transfer modes the transmit mode, the receive mode or the transm it/receive mode can be selected by programming sbicr1 . c 8-bit transmit mode set the control register to the transmit mode and write the transmit data to sbidbr. after writing the transmit data, writing "1" to sbicr1 starts the transmission. the transmit data is moved from sbidbr to a shift register and output to the so pin, with the least- significant bit (lsb) first, in synchronization with the serial clock. once the transmit data is transferred to the shift register, sbidbr becomes empty, and the ints0 (buffer-empty) interrupt is generated, requesting the next transmit data. in the internal clock mode, the serial clock will be stopped and automatically enter the wait state, if next data is not loaded after the 8-bit data has be en fully transmitted. the wait state will be cleared when sbidbr is loaded with the next transmit data. in the external clock mode, sbidbr must be loaded with data before the next data shift operation is started. therefore, the data transfer rate varies depending on the maximum latency between when the interrupt request is generated and when sbidbr is loaded with data in the interrupt service program. at the beginning of transmission, the same value as in the last bit of the previously transmitted data is output in a period from setting sbisr to "1" to the falling edge of sck. transmission can be terminated by clearing to "0" or setting to "1" in the ints0 interrupt service program. if is cleared, remaining data is output before transmission ends. the program checks sbi0sr to determine whether transmission has come to an end. is cleared to "0" at th e end of transmission. if is set to "1," the transmission is aborted immediately and is cleared to "0." in the external clock mode, must be set to "0" before the next transmit data shift operation is started. otherwise, operation will stop after dummy data is transmitted. 7 6 5 4 3 2 1 0 sbicr1 0 1 0 0 0 x x x selects the transmit mode. sbidbr x x x x x x x x writes the transmit data. sbicr1 1 0 0 0 0 x x x starts transmission. ints0 interrupt sbidbr x x x x x x x x writes the transmit data.
tmp19a43 tmp19a43(rev2.0) 15-27 serial bus interface (sbi) fig. 15.25 transmit mode example: example of programming (mips16) to terminate transmission by (external clock) addiu r3, r0, 0x04 stest1 : lb r2, (sbisr) ; if sbisr = 1 then loop and r2, r3 bnez r2, stest1 addiu r3, r0, 0x20 stest2 : lb r2, (pa) ; if sck = 0 then loop and r2, r3 beqz r2, stest2 addiu r3, r0, 0y00000111 stb r3, (sbicr1) ; 0 sbidbr ints0 interrupt request sck pin (output) so pin b a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 * is cleared a write the transmit data (a) internal clock sbidbr ints0 interrupt request sck pin (input) so pin b a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 * is cleared a write the transmit data (b) external clock
tmp19a43 tmp19a43(rev2.0) 15-28 serial bus interface (sbi) fig. 15.26 transmit data retention time at the end of transmission d 8-bit receive mode set the control register to the receive mode. then writing "1" to sb icr1 enables reception. data is taken into the shift register fro m the si pin, with the l east-significan t bit (lsb) first, in synchronization with the serial clock. once the shift register is loaded with the 8-bit data, it transfers the received data to sbidbr and the ints0 (buffer-full) interrupt request is generated to request reading the received da ta. the interrupt service progra m then reads the received data from sbidbr. in the internal clock mode, the serial clock will be stopped and automatically be in the wait state until the received data is read from sbidbr. in the external clock mode, shift operations are exec uted in synchronization with the external clock. the maximum data transfer rate varies, depending on the maximum latency between generating the interrupt request and read ing the received data. reception can be terminated by clearing to "0" or setting to "1" in the ints0 interrupt service program. if is cleared , reception continues until all the bits of received data are written to sbidbr. the program checks sbisr to determine whether reception has come to an end. is cleared to "0" at the end of reception. after confirming the completion of the reception, last received data is read. if is set to "1," the reception is aborted immediately and is cleared to "0 ." (the received data b ecomes invalid, and there is no need to read it out.) (note) the contents of sbidbr will not be retained after the transfer mode is changed. the ongoing reception must be completed by clearing to "0" and the last received data must be read before the transfer mode is changed. 7 6 5 4 3 2 1 0 sbicr1 0 1 1 1 0 x x x selects the receive mode. sbicr1 1 0 1 1 0 0 0 0 starts reception. ints0 interrupt reg. sbidbr reads the received data. bit 7 sck pin siof so pin bit 6 t sodh = min. 3.5/f sys /2 [s]
tmp19a43 tmp19a43(rev2.0) 15-29 serial bus interface (sbi) fig. 15.27 receive mode (example: internal clock) e 8-bit transmit/receive mode set the control register to the transfer/receive mode. then writin g the transmit data to sbidbr and setting sbicr1 to "1" enables transmission and receptio n. the transmit data is output through the so pin at the falling of the serial cloc k, and the received data is taken in through the si pin at the rising of the serial clock, with the least- significant bit (lsb) first. once the shift register is loaded with the 8-b it data, it transfers the received data to sbidbr and the ints0 interrupt request is generated. the interrupt service prog ram reads the received data from the data buffer register and writes the next transmit data. because sbidbr is shared between transmit and receive operations, the received data must be re ad before the next transmit data is written. in the internal clock operation, the serial clock will be automatically in the wait state until the received data is read and the next transmit data is written. in the external clock mode, shift operations are exec uted in synchronization with the external serial clock. therefore, the received data must be read and the next transmit data must be written before the next shift operation is started. the maximum da ta transfer rate for the external clock operation varies depending on the maximum latency between generating the interrupt request and reading the received data and writing the transmit data. at the beginning of transmission, the same value as in the last bit of the previously transmitted data is output in a period from setting to "1" to the falling edge of sck. transmission and reception can be terminated by clearing to "0" or setting sbicr1 to "1" in the ints0 interrupt service program. if is cleared, transmission and reception continue until the received data is fully transferred to sbidbr . the program checks sbisr to determine whether transmission and reception have come to an end. is cleared to "0" at the end of tran smission and reception. if is set, the transmission and reception are aborted immediately and is cleared to "0." (note) the contents of sbidbr will not be retained after the transfer mode is changed. the ongoing transmission and reception must be completed by clearing to "0" and the last received data must be read before the transfer mode is changed. sbidbr ints0 interrupt request sck pin (output) si pin b is cleared a a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 read the received data read the received data
tmp19a43 tmp19a43(rev2.0) 15-30 serial bus interface (sbi) fig. 15.28 transmit/receive mode (example: internal clock) fig. 15.6.2 transmit data retention time at the end of transmission/reception (in the transmit/receive mode) 7 6 5 4 3 2 1 0 sbicr1 0 1 1 0 0 x x x selects the transmit mode. sbidbr x x x x x x x x writes the transmit data. sbicr1 1 0 1 0 0 x x x starts reception/transmission. ints0 interrupt reg. sbiodbr reads the received data. sbidbr x x x x x x x x writes the transmit data. sbidbr ints0 interrupt request sck pin (output) so pin si pin is cleared c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 write the transmit data (a) read the received data (d) a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 * d b c a read the received data (c) write the transmit data (b) bit 7 of the last word transmitted sck pin siof so pin bit 6 t sodh = min. 4/f sys /2 [s]
tmp19a43 16. analog/digit al converter a 10 -b it, sequen tial-con v e rsi o n an alog /d ig it al con v e rter (a/d conv erter) is b u ilt in t o the tmp1 9a4 3 . th is a/d co nv er ter is equ i pp ed w ith 16 an alog i n pu t ch ann e ls. fi g. 1 6 - 1 s h ow s t h e bl oc k di a g ram of t h i s a/ d c o n v e r t e r . th ese 16 an alog inpu t ch ann e ls ( p i n s an 0 thr oug h an1 5) ar e also used as in pu t por ts. (no t e ) if it is necessar y to reduce a po w e r curren t b y operating the tmp19 a 43 in idle, sleep , slow or st op mode and if either c ase sho w n b e low i s ap plica b le, y ou mu st first s t op th e a/d conv erter and the n execu te the instru ction to put the tmp 19a43 into st andby mo de: 1) the tmp19a43 must be put into id le mode w h en admod1< i2ad> is "0." 2) the tmp19 a 43 must be p u t into sleep , slow or st op mode. interrup t request intad an15 (p87) an7 (p77) an0 (p70) comparato r vrefh vrefl internal data bus multip lexer sample hold a d m o d 1 scan repeat interrupt bus y end star t + ? internal data bus internal data bus channel select control circuit adtrg (pd6 ) a/d convers i on result regis t er adreg08l -7f l adreg08 h -7 fh d/a converter admo d 0 admo d2 admo d3 high-priorit y ad conversion contro l interval end ad conversion result regis t er adregs p comp a r at or t op-priority ad co n v ersion comple tion inte rrup t ad monito r fun c tio n in t e rrup t ad mo nitor function control busy ad st art control admo d4 tb0/ct r g ads hp adce adscn vref comp ariso n regi ster normal a/d conversion control cir c uit fig. 16-1 a/d converte r block dia g ra m tmp19a43(rev2.0) 16-1 analog/digit a l converter
tmp19a43 tmp19a43(rev2.0) 16-2 analog/digital converter note) please set the following be fore the analog to digital con version begins to guarantee the conversion accuracy. 0xffff_f319 0x58 7 6 5 4 3 2 1 0 bit symbol read/write r/w r/w r/w r/w r/w r r/w r/w after reset 0 0 1 1 1 0 0 0 function write 0 write 1 write 0 write 1 write 1 write 0 write 0 write 0 16.1 control register the a/d converter is controlled by a/d mode control registers (admod0, admod1, admod2, admod3 and admod4). results of a/d conversion are stored in 16 upper and lower a/d conversion result registers adreg08h/l through adreg7fh/l. results of top-pr iority conversion are st ored in adregsph/l. fig. 16-2 shows the registers related to the a/d converter. a/d mode control register 0 7 6 5 4 3 2 1 0 bit symbol eocfn adbfn itm1 itm0 repeat scan ads read/write r r r/w after reset 0 0 0 0 0 0 0 0 function normal a/d conversion completion flag 0: before or during conversion 1: completion normal a/d conversion busy flag 0: conversion stop 1: during conversion "0" is read. specify interrupt in fixed channel repeat conversion mode specify interrupt in fixed channel repeat conversion mode specify repeat mode 0: single conversion mode 1: repeat conversion mode specify scan mode 0: fixed channel mode 1: channel scan mode start a/d conversion 0: don't care 1: start conversion "0" is always read. specify a/d conversion interrupt in fixed channel repeat conversion mode fixed channel repeat conversion mode = "0," = "1" 00 generate interrupt once every single conversion 01 generate interrupt once every 4 conversions 10 generate interrupt once every 8 conversions 11 setting prohibited a dmod0 (0xffff_f314) fig. 16-2 registers related to the a/d converter adcbas (0xffff_f319)
tmp19a43 a/ d m o d e co n t r o l re g i s t e r 1 7 6 5 4 3 2 1 0 bi t sy mbol vr efo n i 2 ad ad sc n ? a dch3 a dch2 a dch1 a dch0 r ead/ w r i t e r / w af t e r r e s e t 0 0 0 0 0 0 0 0 func t i on vref appl i c at i on cont r o l 0: o ff 1: o n id l e 0: s t op 1 : a c ti v a te s peci f y oper at i o n m ode f o r channe l scanni ng 0: 4ch scan 1: 8ch scan w r i t e " 0 . " s e l e ct a n a l og i n p u t chan ne l sel e ct anal og i nput c hannel < s ca n> < a dch3 . 2 , 1, 0 > 0 fi x ed c hanne l 1 c hannel sc an ( a ds cn= 0 ) 1 c hannel sc an ( a ds cn= 1 ) 0000 an 0 an 0 an 0 0001 an 1 an 0 t o an 1 an 0 t o an 1 0010 an 2 an 0 t o an 2 an 0 t o an 2 0011 an 3 an 0 t o an 3 an 0 t o an 3 0100 an 4 an 4 an 0 t o an 4 0101 an 5 an 4 t o an 5 an 0 t o an 5 0110 an 6 an 4 t o an 6 an 0 t o an 6 0111 an 7 an 4 t o an 7 an 0 t o an 7 1000 an 8 an 8 an 8 1001 an 9 an 8 t o an 9 an 8 t o an 9 1010 an 1 0 an 8 t o an 10 an 8 t o an 10 1011 an 1 1 an 8 t o an 11 an 8 t o an 11 1100 an 1 2 an 12 an 8 t o an 12 1101 an 1 3 an 12 t o an 13 an 8 t o an 13 1110 an 1 4 an 12 t o an 14 an 8 t o an 14 1111 an 1 5 an 12 t o an 15 an 8 t o an 15 a dm od1 ( 0 x ffff_ f315) (no t e 1 ) before st ar ting ad conv ersion, w r ite "1" to the bit, w a it for 3 s during w h ich time the internal re ference v o lt age should st abiliz e, and then w r i t e "1" to the adm od 0< a d s> bit. (no t e 2 ) t o go into st andb y mode upon completion of ad c onv ersion, s e t to "0." fig. 16-3 reg i sters rel a t ed to the a/d co nverter tmp19a43(rev2.0) 16-3 analog/digit a l converter
tmp19a43 a/ d m o d e co n t r o l re g i s t e r 2 7 6 5 4 3 2 1 0 bi t sy mbol eo c f h p ad bfh p h p ad c e ? h pad c h3 hp a dch2 hp a dch1 hp a dch0 r ead/ w r i t e r r r / w af t e r r e s e t 0 0 0 0 0 0 0 0 func t i on top- p r i o ri t y ad conver s i on com p l e t i on f l ag 0: b e f o r e or duri ng conver s i on 1: u pon com p l e t i on top- p r i o ri t y a d conver s i on busy f l a g 0: d u ri ng conver s i on hal t s 1: d u ri ng conver s i on a c ti v a te t op- pri o ri t y conver s i on 0: d on' t care 1: s t ar t conver s i on. "0 " i s a l w a y s r ead. w r i t e " 0 . " s e l e ct a n a l og i n p u t chan ne l w hen act i vat i ng t op- pri o ri t y conver s i on < h p a dch4 , 3 . 2 , 1, 0 > anal og i nput c hannel w hen e x ec ut i ng t op- pr i o ri t y c onver s i on 0000 an 0 0001 an 1 0010 an 2 0011 an 3 0100 an 4 0101 an 5 0110 an 6 0111 an 7 1000 an 8 1001 an 9 1010 an 1 0 1011 an 1 1 1100 an 1 2 1101 an 1 3 1110 an 1 4 1111 an 1 5 a dm od2 ( 0 x ffff_ f316) tmp19a43(rev2.0) 16-4 analog/digit a l converter
tmp19a43 a/ d m o d e co n t r o l re g i s t e r 3 7 6 5 4 3 2 1 0 bi t sy mbol ad o b i c r e g s 3 r eg s2 r e g s 1 re g 0 ad o b sv r ead/ w r i t e r / w r r / w af t e r r e s e t 0 0 0 0 0 0 0 0 func t i on wr ite "0 ." " 0 " i s r ead. m a k e a d m o n i to r fu n c tio n i n te rru p t s e tti n g 0: sm al l e r t han com p ar i s on r e g i 1: lar g er t h an com p ar i s on r e g i b i t f o r se l e ct i n g t he a d conv er s i on r e su l t st orage r e g i t h a t i s to b e c o m p a r e d w i th th e c o m p a r i s o n r e g i i f th e a d m o ni t o r f unct i on i s enab l ed a d m oni t o r fu n c tio n 0: d i sa bl e 1: e n ab l e ad c onver s i o n r e s u l t st o r age r egi t o be c o m p ared 0000 ad r e g 08 0001 ad r e g 19 0010 ad r e g 2 a 0011 ad r e g 3 b 0100 ad r e g 4 c 0101 ad r e g 5 d 0110 ad r e g 6 e 0111 ad r e g 7 f 1 x x x ad r e g s p a dm od3 ( 0 x ffff _f317) a / d m o de c o n t r o l r e gi st e r 4 7 6 5 4 3 2 1 0 bi t s y m b o l ha d h s h a dh t g a dhs a d ht g a drs t 1 a d rs t 0 r ead/w r i t e r / w r w w af t e r res e t 0 0 0 0 0 ? ? func t i on h w sou r ce f o r a c t i vat i ng t o p- pri o ri t y a/ d c onver s i on 0 : e x t e r nal tr g 1: t b 9 t rg h w fo r ac t i vat i n g to p - p r i o r i ty a/ d co nver s i on 0: d i sa ble 1: e nab l e h w s o u r c e fo r act i v a t i ng nor m a l a / d c o nv e r s i on 0: e x t e r n a l tr g 1: t b 1tr g h w fo r act i va t i ng nor m a l a / d conve r s i on 0: d i s a bl e 1: e n ab l e ? 0 ? i s r ead. o v e r w r i t i n g 1 0 w i t h 01 a l l o w s a d c to b e s o ftw a r e re s e t . a dmod 4 ( 0 x fff f_f 318) (no t e 1 ) if ad conv ersion is executed w i th th e match trig gers and of a 16-bi t timer set to "1" b y usin g a source for triggeri ng h/w , a/ d conv ersion c a n be activ a t ed at specifie d interv als b y pe rforming thr ee step s sho w n b e lo w w h en the timer is idle: c select a sou r ce for trigg e ring hw : , d enable h/w activ ation of ad co nv ersion: , e s t art the tim e r . (no t e 2 ) do not mak e a top-p r iorit y ad co n v ersion setting and a normal ad c onv ersion s e ttin g simult aneou s ly . tmp19a43(rev2.0) 16-5 analog/digit a l converter
tmp19a43 lo w e r a / d c o n v e r s i on res u l t reg i s t er 0 8 7 6 5 4 3 2 1 0 b i t s y m b o l a d r0 1 a d r0 0 o v r 0 a dr0 rf r e a d / w r i t e r r r r a f t e r r e s e t 0 1 0 0 f u n c t i on st or e l o w e r 2 bi t s o f a / d c o nver s i on r e s u l t "1 " is r e a d . o v er r u n f l ag 0 : n o t g e n e r a te 1 : g e ner at e a / d con v er s i on r e s u l t s t o r a ge f l a g 1: p r es enc e of co n v er s i o n r e s u l t u p pe r a / d c o n v er s i o n re s u l t re g i s t e r 08 7 6 5 4 3 2 1 0 bi t symbol ad r 0 9 ad r 08 ad r 0 7 ad r 0 6 ad r 0 5 ad r 0 4 ad r 03 ad r 0 2 re a d / w r i t e r af t e r r e s e t 0 f u n c t i on st o r e up pe r 8 bi t s o f a/ d c o n v e r s i on r e s u l t lo w e r a / d c o n v e r s i on res u l t reg i s t er 1 9 7 6 5 4 3 2 1 0 bi t symbol ad r 1 1 ad r 10 o v r 1 ad r 1 r f re a d / w r i t e r r r r af t e r r e s e t 0 1 0 0 f u n c t i on st o r e l o w e r 2 b i t s o f a / d co n v e r si o n re s u l t " 1 " i s r e ad. o v er r u n f l a g 0 : n o t g e n e r a te 1 : g e ner at e a / d c onv er s i on r e su l t st o r ag e f l a g 1 : p r ese n ce of co nv er s i o n r e su l t u p pe r a / d c o n v er s i o n re s u l t re g i s t e r 19 7 6 5 4 3 2 1 0 bi t symbol ad r 1 9 ad r 18 ad r 1 7 ad r 1 6 ad r 1 5 ad r 1 4 ad r 13 ad r 1 2 re a d / w r i t e r af t e r r e s e t 0 f u n c t i on st o r e up pe r 8 bi t s o f a/ d c o n v e r s i on r e s u l t 9 8 765 432 10 c o nver t e d c h an n e l x val u e 7 65 4 3 21 0 7 65 4 3 2 1 0 a dr e g 0 8 h ( 0 x f ff f_ f3 01 ) a dr e g 1 9 h ( 0 x f ff f_ f3 03 ) a dr e g x h a d r e g x l ? v a l u es r e a d f r om b i t s 5 t h r o u gh 2 a r e a l w a y s " 1 . " ? b it 0 is t h e a / d c o n v e r s i o n r e s u l t s t o r a g e f l a g < a d r x r f > . t h i s b it i s s e t t o " 1 " a f te r a n a / d c o n v e r te d v a l u e i s s t o r e d . a re a d o f a l o w e r re g i s t e r ( a d r e g x l ) w i l l se t th is b i t to " 0 ." ? b i t 1 i s th e o v e r r u n f l a g < o v r x > . t h is b i t is s e t to " 1 " if a c o n v e r s i o n r e s u l t is o v e r w r itt e n b e f o r e b o th c o n v e r s i o n r e s u l t st o r a g e re g i s t e r s ( a d r e g x h a n d a d r e g x l ) are re a d . a r e ad o f a flag w i ll c l e a r t h i s b i t t o " 0 . " ? w h en r e a d i n g c o n v er s i on r e s u l t s t or age r e gi s t er s , f i r s t r e a d upp e r r e gi s t er s a n d t h en l o w e r r e gi s t er s . a d r eg 08 l ( 0 xff ff_ f3 00 ) a d r eg 19 l ( 0 xff ff_ f3 02 ) fig. 16 -4 reg i sters rel a ted to the a/d co nverter tmp19a43(rev2.0) 16-6 analog/digit a l converter
tmp19a43 l o w e r a / d c o nv e r s i o n re s u l t re g i s t e r 2a 7 6 5 4 3 2 1 0 bit s y m b ol adr2 1 a d r2 0 ovr2 adr2 rf re ad / w r i te r r r r a fter re set 0 1 0 0 fu nc t i on s t ore l o w e r 2 bi t s o f a / d c onvers i on re s u l t "1" i s r e a d . o v er ru n f l ag 0: n o t gen e r a t e 1: gen e r a te a / d con v er s i on r e s u l t s t o r a ge f l a g 1: pres enc e of co n v er s i o n res u l t u p p e r a / d c o nv e r s i o n re s u l t re g i s t e r 2a 7 6 5 4 3 2 1 0 b i t s y m b o l a d r 29 a d r 2 8 a d r2 7 a d r 26 a d r 2 5 a d r2 4 a d r 23 a d r 2 2 re ad / w r i te r a fter re set 0 fu nc t i on s t ore u ppe r 8 bi t s o f a / d c o nve r s i on res u l t l o w e r a / d c o nv e r s i o n re s u l t re g i s t e r 3b 7 6 5 4 3 2 1 0 bit s y m b ol adr3 1 a d r3 0 ov r 3 a d r3 rf re ad / w r i te r r r r a fter re set 0 1 0 0 fu nc t i on s t ore l o w e r 2 bi t s o f a / d c onvers i on re s u l t "1" i s r e a d . o v er r u n f l ag 0 : no t ge ne r a te 1 : ge ner ate a/d c onv ers i on r e su l t sto r ag e f l a g 1 : p r ese n ce of c o nv ers i o n r e su l t u p p e r a / d c o nv e r s i o n re s u l t re g i s t e r 3b 7 6 5 4 3 2 1 0 b i t s y m b o l a d r 39 a d r 3 8 a d r3 7 a d r 36 a d r 3 5 a d r3 4 a d r 33 a d r 3 2 re ad / w r i te r a fter r e set 0 fu nc t i on s t ore u ppe r 8 bi t s o f a / d c o nve r s i on res u l t 9 8 7 6 5 4 3 2 1 0 c o n v e r t e d c han ne l x va l u e 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 a dr e g 2a h ( 0 x f ff f_f 3 05) a dr e g 3b h ( 0 x f ff f_f307) a d r egx h adr e g x l ? v a lu es rea d from b i t s 5 th rou g h 2 a r e a l w a y s "1 . " ? bi t 0 is the a / d c o nv e r sio n r e s u l t s t o r ag e fl ag < a d r x r f > . i t is s e t to " 1 " afte r an a / d c o nv e r t e d v a l u e i s sto r e d . a re ad o f a l o w e r r e g i s t e r (a dreg x l ) w i l l s e t th is b i t to " 0 ." ? bi t 1 is t h e o v e r r u n f l ag . i t is s e t to "1" i f a co nv e r sio n r e sul t is o v e rw ritte n b e f o r e bo t h c o nv e r sio n r e sul t s t o r ag e r e g i s t e r s ( a d r egx h , a dr eg xl ) ar e r e ad. a re ad o f a fl ag w i l l c l e a r th i s bit to " 0 ." ? w h e n rea d in g c o n v e r si on resu lt st o r ag e re g i st ers, fi rs t rea d u p p e r re g i st ers a n d t h en rea d l o w e r re gi st ers. a dr e g 2a l ( 0 x f ff f_f304) a dr e g 3b l ( 0 x f ff f_f306) fig. 16-5 reg i sters rel a ted to the a/d co nverter (1 of 2) tmp19a43(rev2.0) 16-7 analog/digit a l converter
tmp19a43 lo w e r a/d co n v ers i on r e sul t r e g i s t er 4c 7 6 5 4 3 2 1 0 b i t s y m b o l ad r 4 1 ad r 4 0 o v r 4 ad r 4 r f re ad /w r i t e r r r r aft e r r e s e t 0 1 0 0 f unc t i o n s t o r e low e r 2 b i t s o f a/ d c o nv e r sion re sult "1" i s r e a d . ove r r un f l a g 0: not g ene rate 1: g ene r a te a/d conv ers i on r e su l t st o r ag e f l a g 1: p r e s en c e o f c o nv e r s i o n r e s u lt upp e r a/d co n v ers i on r e sul t r e g i s t er 4c 7 6 5 4 3 2 1 0 b i t s y m b o l ad r 4 9 ad r 4 8 a d r 4 7 ad r 4 6 ad r 4 5 a d r 4 4 ad r 4 3 ad r 4 2 re ad /w r i t e r aft e r r e s e t 0 f unc t i o n s t or e u p p e r 8 b i t s o f a / d c o nvers i on re s u l t lo w e r a/d co n v ers i on r e sul t r e g i s t er 5d 7 6 5 4 3 2 1 0 b i t s y m b o l ad r 5 1 ad r 5 0 o v r 5 ad r 5 r f r e a d / w ri te r r r r aft e r r e s e t 0 1 0 0 f unc t i o n s t o r e low e r 2 b i t s o f a/ d c o nv e r sion re sult "1" i s r e a d . o v er r u n f l ag 0 : no t ge ne r a te 1 : ge ner ate a/d conv ers i on r e su l t st o r ag e f l a g 1: p r e s en c e o f c o nv e r s i o n r e s u lt upp e r a/d co n v ers i on r e sul t r e g i s t er 5d 7 6 5 4 3 2 1 0 b i t s y m b o l ad r 5 9 ad r 5 8 a d r 5 7 ad r 5 6 ad r 5 5 a d r 5 4 ad r 5 3 ad r 5 2 re ad /w r i t e r aft e r r e s e t 0 f unc t i o n s t or e u p p e r 8 b i t s o f a / d c o nvers i on re s u l t 9 8 7 6 5 4 3 2 1 0 c o n v e r t e d c han ne l x va l u e 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 a dr e g 4c h ( 0 x f ff f_ f 3 09 ) a dr e g 5 d h ( 0 x f ff f_f3 0b) a d r egx h adr e g x l ? v a l u e s re ad f r o m bi ts 5 t h r o ug h 2 ar e al w a y s " 1 ." ? b i t 0 is the a / d c o n v e r s i o n r e s u l t s t o r a g e f l ag < a drx r f > . i t is s e t to " 1 " afte r an a / d c o nv e r t e d v a l u e is sto r e d . a re ad o f a l o w e r r e g i ste r ( a dr eg xl ) w i ll se t t h is bit to " 0 ." ? b i t 1 is the o v e r r u n f l ag . i t is s e t to " 1 " if a c o nv e r sio n r e sul t is o v e r w r itte n b e f o r e bo t h c o n v e r s i o n r e s u l t s t o r a g e r e g i ste r s ( a d r egx h an d a d r e g x l ) a r e re ad . a r e a d of a f l a g w i l l cle a r t h is b it to "0 ." ? w h en rea d in g c o n v ersi on r e su lt s t orage re gi st ers, fi rs t rea d upp e r re gi st ers a n d t h en r e a d low e r re gi st e r s . a dr e g 4c l ( 0 x f ff f_f3 08 ) a dr e g 5d l ( 0 x f ff f_f3 0a) tmp19a43(rev2.0) 16-8 analog/digit a l converter
tmp19a43 l o w e r a / d c o nv e r s i o n re s u l t re g i s t e r 6e 7 6 5 4 3 2 1 0 b i t sy m b o l a d r6 1 a d r6 0 ov r6 adr 6 r f re ad /w r i t e r r r r aft e r r e s e t 0 1 0 0 f unc t i o n s t o r e low e r 2 b i t s o f a/ d c o nv e r sion re sult "1" i s r e a d . ove r r un f l a g 0: not g ene rate 1: g ene r a te a / d con v ers i on r e s u l t s t o r a ge f l a g 1: pres enc e of co n v ers i o n res u l t u p p e r a / d c o nv e r s i o n re s u l t re g i s t e r 6e 7 6 5 4 3 2 1 0 b i t s y m b o l ad r 6 9 ad r 6 8 a d r 6 7 ad r 6 6 ad r 6 5 a d r 6 4 ad r 6 3 ad r 6 2 re ad /w r i t e r aft e r r e s e t 0 f unc t i o n s t or e u p p e r 8 b i t s o f a / d c o nvers i on re s u l t lo w e r a/d co n v e r s i on r e sul t r e g i s t er 7f 7 6 5 4 3 2 1 0 b i t sy m b o l a d r7 1 a d r7 0 ov r 7 adr7 rf re ad /w r i t e r r r r a f t e r res e t 0 1 0 0 f unc t i o n s t o r e low e r 2 b i t s o f a/ d c o nv e r sion re sult "1" i s r e a d . ove r r unf la g 0: not g ene rate 1: g ene r a te a/d conv ers i on r e su l t st o r ag e f l a g 1: p r e s en c e o f c o nv e r s i o n r e s u lt u p p e r a / d c o nv e r s i o n re s u l t re g i s t e r 7 f 7 6 5 4 3 2 1 0 b i t s y m b o l ad r 7 9 ad r 7 8 a d r 7 7 ad r 7 6 ad r 7 5 a d r 7 4 ad r 7 3 ad r 7 2 re ad /w r i t e r aft e r r e s e t 0 f unc t i o n s t or e u p p e r 8 b i t s o f a / d c o nvers i on re s u l t 9 8 7 6 5 4 3 2 1 0 c o n v e r t e d c han ne l x va l u e 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 a dr e g 6e h ( 0 x f ff f_ f 3 0d ) a dr e g 7f h ( 0 x f ff f_f3 0f) a d r egx h adr e g x l ? v a lu es rea d from b i t s 5 th rou g h 2 a r e a l w a y s "1 . " ? b i t 0 i s t h e a / d c o n v er s i on r e s u lt s t o r a g e f l a g < a d r xr f > . i t i s s e t t o " 1 " i f an a / d c o n v er t e d va lu e i s s t or ed . a r e a d of a l o w er r e g i s t e r ( a dreg x l ) w i l l s e t th is b it t o "0." ? bi t 1 is the o v e r r u n f l a g . i t is se t to " 1 " if a co nv e r s i o n r e sul t is o v e r w r itte n b e f o r e bo t h c o nv e r sio n r e s u l t s t o r ag e r e g i st e r s ( a d r egx h an d a d r e g x l ) a r e re ad . a r e a d of a f l ag w i l l c l e a r th is bit t o "0 ." ? w h e n read in g co n v e r si on resu lt st o r ag e reg i st ers, fi rs t rea d upp e r re gi st ers a n d t h en rea d low e r re gi st ers. a dr e g 6e l ( 0 x f ff f_f3 0c ) a dr e g 7f l ( 0 x f ff f_f3 0e) tmp19a43(rev2.0) 16-9 analog/digit a l converter
tmp19a43 lo w e r a/d co n v ers i on r e sul t r e g i s t er s p 7 6 5 4 3 2 1 0 b i t sy m b o l adr s p1 a d rsp 0 o v r s p a d rsp r f re ad /w r i t e r r r r aft e r r e s e t 0 1 0 0 f unc t i o n s t o r e low e r 2 b i t s o f a/ d c o nv e r sion re sult "1" i s r e a d . ove r r un f l a g 0: not g ene rate 1: g ene r a te a / d con v ers i on r e s u l t s t o r a ge f l a g 1: pres enc e of co n v ers i o n res u l t u p p e r a / d c o nv e r s i o n re s u l t re g i s t e r s p 7 6 5 4 3 2 1 0 b i t s y m b o l a d r s p 9 ad r s p8 ad r s p 7 a d r sp6 ad r s p5 a d r s p 4 a d r sp3 ad r s p2 re ad /w r i t e r aft e r r e s e t 0 f unc t i o n s t or e u p p e r 8 b i t s o f a / d c o nvers i on re s u l t 9 8 7 6 5 4 3 2 1 0 c o n v e r t e d c han ne l x va l u e 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 a dr e g sp h ( 0 x f ff f_ f 3 1 1 ) a d r egx h adr e g x l ? v a l u e s re ad f r o m bi ts 5 t h r o ug h 2 ar e al w a y s " 1 ." ? b i t 0 is the a / d c o n v e r s i o n r e s u l t s t o r a g e f l ag < a drx r f > . i t is s e t to " 1 " a f t e r an a / d c o n v e r te d v a l u e is sto r e d . a r e ad o f a l o w e r r e g i ste r ( a dr eg xl ) w i ll se t t h is bit to " 0 ." ? b i t 1 is t h e o v e r run fl ag . i t is s e t to " 1 " if a c o nv e r sio n r e s u l t is o v e r w r itt e n be fo r e bo th c o n v e r s i o n r e s u l t s t o r a g e r e g i ste r s ( a d r egx h an d a d r e g x l ) a r e re ad . a r e a d of a f l a g w i l l cle a r t h is b it to " 0 ." ? w h en rea d in g c o n v ersi on r e su lt s t orage re gi st ers, fi rs t rea d upp e r re gi st ers a n d t h en r e a d low e r re gi st e r s . a dr e g sp l ( 0 x f ff f_f3 10 ) tmp19a43(rev2.0) 16-10 analog/digit a l converter
tmp19a43 lo w e r a/d co n v ers i on r e sul t c o m p ari s o n re g i ste r 7 6 5 4 3 2 1 0 bi t s y m b ol a d r 2 1 a d r2 0 re ad /w ri t e r / w r af te r r e s e t 0 0 fu nction s t or e l o w e r 2 bi t s o f a/ d c o nv er sion re s u lt c o m p ari s on " 0 " i s r ead . u p p e r a / d c o nv e r s i o n re s u l t co mp a r i s o n r e gi s t e r 7 6 5 4 3 2 1 0 bi t s y m b ol a d r 2 9 a d r2 8 a d r 27 a d r 2 6 a d r2 5 a d r 2 4 a d r 2 3 a d r2 2 re ad /w ri t e r / w af te r r e s e t 0 fu nction s t o r e up pe r 8 bit s o f a/d con v e r s i o n r e sult c o m p ar ison a dc omre g h ( 0 x f ff f_ f 3 13 ) a dc omr e g l ( 0 x f ff f_f3 12 ) (no t e ) t o se t or ch ange a v a lue in this register , th e ad monitor fu ncti on must be disabled (admod3 < ado b sv>="0"). tmp19a43(rev2.0) 16-1 1 analog/digit a l converter
tmp19a43 16.2 conversio n clock z t h e conversion tim e is calcula t e d by t h e 46 co n v ersi on cl ock. a/d c o n v e r s i o n cl o c k s e tti ng re gi s t er 7 6 5 4 3 2 1 0 b i t s y m b o l ts h3 t s h2 t s h 1 t s h0 a d c l k 2 a dcl k 1 a dcl k 0 r e a d / w r i t e r / w r / w r / w r / w r r / w r / w r / w af ter re s e t 1 0 0 0 0 0 0 0 fun c t i o n s e le c t t h e a / d s a m p le h o ld t i m e 10 00 : 8 c o n v er s i o n c l oc k 1 0 0 1 : 8 2 c o nv er s i o n c l oc k 10 10 : 8 3 c o nv er s i on c l ock 1 011 : 8 4 c o nver s i o n c l ock 00 11 : 8 8 c o nv er s i on c l ock 11 00 : 8 16 con v er s i o n c l ock 11 01 : 8 6 4 c o nv er s i o n c l oc k "0 " i s re ad . s e lec t th e a / d p r es c a l e r ou t p u t 0 00: f c 00 1 : fc /2 01 0 : fc /4 01 1 : fc /8 10 0 : fc /1 6 1 11: reser v e d a dc lk (0 x f fff_f31 c) ad dcl k 2: 0 1 2 4 8 16 fc adclk exam ple: if fs y s = fc = 4 0 m h z f c p r e s c a l a r tconv. (conv ersion time) 1 1 . 1 5 u s 1 / 2 2 . 3 u s 40 mhz 1 / 4 4 . 6 u s v a riab le s/ h time conversion clock s/h time tconv. (conv ersion time) conversion clk* 8*1 (0.2 us) 1.15 us conversion clk* 8*2 (0.4 us) 1.35 us conversion clk* 8*3 (0.6 us) 1.55 us conversion clk* 8*4 (0.8 us) 1.75 us conversion clk* 8*8 (1.6 us) 2.55 us conversion clk* 8*16 (3.2 us) 4.15 us 40 mhz conversion clk* 8*64 (12.8 us) 13.75 us "please do not change the analog to digi t a l conversion clock setting in the analog to digit a l translation. " tmp19a43(rev2.0) 16-12 analog/digit a l converter
tmp19a43 description of operations 16.2.1 analog reference v o lt age th e "h" lev e l o f th e an alog referen ce vo ltage sh all b e ap p l i e d to th e vrefh p i n, an d the "l" lev e l sh all b e ap p lied to t h e vrefl p i n. by writing "0 " to th e admod1 b it, a swi t ch ed-on state o f vref h- vre f l ca n be t u r n ed int o a s w i t ched-of f state. t o sta r t ad c o nve r sion, m a ke s u re that y o u first write "1 " to th e b it, wait fo r 3 s du ri n g wh ich tim e th e in tern al referen ce vo ltag e sh ou l d stab ilize, and t h en wri t e "1 " to th e admod0 b it. 16.2.2 selecting the analog input channel how t h e a n alog input cha n ne l is selected is dif f e r e n t de pe n d i n g on a/ d c o nve rt er o p erat i o n m ode u s ed . (1 ) no rm al ad c o nve rsi o n m ode if t h e a n al o g i n put c h a nnel i s use d i n a fi xed st at e (a dm o d 0< sc a n > = "0 " ) : one cha n nel i s sel ect ed f r o m anal o g i n p u t pi ns ai n 0 t h r o u g h ai n1 5 by s e t t i ng adm od 1< a d c h 3 t o 0> t o an a p pr o p ri at e set t i ng. if t h e a n al o g i n put c h a nnel i s use d in a sca n state (admod0< scan> = "1 " ) : on e scan m o d e is selected fro m 1 6 scan m o d e s b y settin g admod1 and a d scn t o ap pr op r i ate settings. ( 2 ) t o p- pr ior ity ad co nv er sion m o d e one cha n nel i s sel ect ed fr om anal o g i n p u t pi ns ai n 0 t h ro ug h ai n 1 5 by set t i ng adm od 2< hp adc h3 to 0> to an ap p r o p ria t e setting. after a reset, admod0 is i n itialized to "0 " an d adm od1 < adch3 : 0 > is i n itialized t o "0 000 ." th is in itializatio n wo rk s as a trigger to select a fix e d ch ann e l in pu t th rou g h t h e an0 p i n. th e pi ns t h at are no t use d as a n al o g i n p u t cha n ne l s can be use d as o r di nary i n p u t p o r t s . if top - priority ad con v e rsion is activ ated d u ring nor m a l a d con v e r s i o n, no r m al ad conv er si o n is d i scon tinu e d, t o p-p r iority ad con v e rsion is ex ecu ted and co m p leted , and th en no rm al ad co nv ersion i s resum e d. exam ple: a case in which repeat-s can co nv er sion is ong o i n g at ch annels ai n0 t h ro ug h a i n 3 w ith adm od 0 set t o " 1 1" an d adm od 1< a d c h 3: 0> set t o 00 1 1 , an d t o p- pri o rity a d c o nve rsio n has b een activate d a t ai n 1 5 with adm od 2< hp adc h3: 0 >= 1 1 1 1: t op-prior i ty ad has been activ ated ch0 ch1 c h 2 ch15 c h 2 c h 3 c h 0 conversion ch tmp19a43(rev2.0) 16-13 analog/digit a l converter
tmp19a43 16.2.3 s t arting a/d conversion t w o t y pes of a/ d c o nve rsi o n a r e s u pp ort e d: n o r m a l ad co nve rsi o n an d t o p - p r i o ri t y ad co n v ersi o n . norm al ad co nv ersion is so ft ware activ ated b y settin g admod0 t o "1 ." t o p-p r iority ad co nv ersion is so ft ware activ at ed b y settin g adm od2 < hp adce> to "1 ." 4 o p e ration m o d e s are m a d e avai l a bl e t o no rm al ad con v e rsi o n. in pe rf o r m i ng no rm al ad c o nve rsi o n , o n e of t h ese o p erat i o n m odes m u st b e select ed b y setting adm od0 < 2 : 1> to an ap p r o p riate settin g . fo r t o p-priority ad con v e rsion, onl y o n e o p era t i on m ode can be used: fi x e d c h a nnel si n g l e co nve rsi o n m ode. n o rm al a d c o nve rsi o n can be activate d usi n g the hw acti v ation s o urce selected by adm od 4 < ad hs> , a n d to p- pri o rity a d conve r sion ca n be activate d using t h e hw a c tiva t i on s o u r c e sel ect ed by adm od 4< h a d h s> . i f t h i s b it is "0," n o rmal an d top- prio r ity ad con v er sion s ar e acti v ated i n r e sponse to t h e inpu t o f a f a lling e d g e th ro ugh t h e adtrg p i n . if t h is b it is "1 ," no rm al ad con v e rsion is activ ated in respo n s e to tb 1 t rg g e n e rated b y t h e 16 -b it tim e r 1 , and top - p r io rity ad conversi on is activated in res ponse t o tb9tr g g e n e rated b y t h e 1 6 -b it tim er 9 . software activ atio n is st ill v a lid ev en after h/ w acti v atio n h a s b e en au tho r ized . (no t e ) when an external trigger is used for the hw star t s o ur ce of a to p prio ri t y a n a l og to di gi t a l tra n sl ati o n, an e x t ernal tri gger cann ot usu a l l y be set a s an al o g t o d i gi tal t r anslat io n hw sta r t . whe n no rm al a/d c o n v e r sio n starts, t h e a/ d co n v ersi on b u sy fl ag (a d m od 0) sh o w i n g t h a t a/d co nv ersion is un d e r way is set to "1 ." wh en top - priority a/d con v e rsion starts, th e a/ d conv ersi on bu sy f l ag (admo d 2 < ad bfh p >) sh ow ing th at a / d co nv er si o n is under w a y is set to "1 ." i f no r m al a/d conv ersi on is in terrup ted b y top - p r i o ri ty a/d co nv ersio n , t h e v a l u e of th e busy flag for no rm al a/d co nv ersion b e fore th e st art o f t o p-priority a/d co nv ersio n is retai n ed. th e v a lu e o f th e con v e rsion com p l e t i on fl a g e o c f n fo r no rm al a/ d c o nve rsi o n be fo r e t h e st art of t o p- pri o ri t y a/ d con v e r si o n ca n also be retai n e d . (no t e ) normal a/ d conv ersion must not b e activ a ted w h en top - priori t y a/d conv ersion is under w a y . if activ ated w h e n to p-p r iorit y a/d conv ersion is under w a y , the top - priori t y a/d con v ersion completion flag c a nnot be s e t, and the flag for p r ev ious normal a/ d con v ersion cannot be clea r e d. t o reactivate norm al a/d conve r sion, a s o ft ware reset ( adm od 4< a d r s t 1 : 0 > ) m u st be pe rf orm e d before sta r ting a/d conversi on. the hw a c tivation m e thod m u st not be used t o reacti v ate norm al a/d co nv er sion . i f a d m od 2 < h p ad ce> is set to "1 " du rin g no r m al a / d conv er si on , o ngo ing a / d co nv er sion is d i scon tinu e d an d top - prio rity a/d co nv ersio n starts; sp eci fically , a/d con v e rsion (fix ed ch ann e l sing le conve r sion) is execute d for a channe l d e signated b y adm o d2 <3 :0 >. after th e resu lt of th is top - prio rit y a/ d c o nve rsi o n i s st ore d i n t h e st ora g e regi st er adr e g sp , n o r m a l a/ d con v e r si o n i s re sum e d. if h w act i v at i o n of t o p- pri o r i t y a/ d c o nve r s i o n i s a u t h o r i zed d u ri ng no r m al a/ d c o nv ersi o n , o n goi n g a/ d c o n v e r si o n i s di sc ont i n u e d w h e n re qui rem e nt s for ac t i v at i on u s i n g a reso ur ce are m e t , and t o p- pri o ri t y a/ d con v e r si o n (fi xed ch an nel si ngl e c o nve r s i o n ) st art s f o r a c h an nel desi gnat e d b y adm od2 < 3 : 0>. after th e resu lt o f th is t o p-priority a/ d c o nv er s i on is s t o r ed in th e sto r ag e r e g i s t er adre g sp , n o r m a l a/d co nv ersio n is res u m e d. tmp19a43(rev2.0) 16-14 analog/digit a l converter
tmp19a43 16.2.4 a/d conversion modes and a/d conversion completion interrupt s for a/ d c o n v e r si o n , t h e f o l l o wi n g f o ur o p er at i on m odes a r e su pp o r t e d. f o r n o rm al a/ d co nve rsi o n, a n o p e ration m o de can b e select ed b y settin g adm od0 < 2 : 1> to an app r op riate settin g . fo r t o p-p r iority a/d co nv ersion , th e fix e d chan n e l si n g l e con v e rsion m o d e is au to m a tica l ly selected , irresp ectiv e o f t h e adm od 0< 2: 1 > set t i ng. fi xed cha n nel si ngl e c o nve rsi o n m ode c h an nel sca n s i ngl e c o n v e r si o n m ode fi xed cha n nel repeat c o nve rsi o n m ode channel sca n repeat conversi on m ode (1 ) no rm al a/d c o n v e r sio n an op eratio n m o d e is selected with adm od0 < repea t , scan >. as a / d conv er sio n star ts, adm od0 < adbfn> is set to "1 ." wh en sp eci fied a/d con v e rsion is co m p leted , th e a/ d co nv ersion com p le tio n i n terrup t (int ad) is ge nerat e d, a n d adm o d 0< eoc f > s h o w i n g t h e com p letion of a/ d c o nve rsion is set to "1." if ="0," < adbfn> ret u rns to " 0 " co n c urren tly with th e settin g o f eoc f . if is set to "1 ," rem a in s at "1 " and a/ d c o nve rsi o n c ont i n ues . c fi xed cha n nel si ngl e c o nve rsi o n m ode i f ad m o d0 is set to "00 , " a / d conv er sion is p e rfo rmed in th e f i xed ch ann e l si ngl e c o nve rsi o n m ode. i n th is m o d e , a / d conv er si on is p e rf or m e d on ce fo r o n e ch ann e l selected . af ter a / d co nv er sion is co m p leted , admod0 < eocf> is set to "1 ," adm od0 < adbf> is cleared to "0," an d the in terrup t requ est int a d is g e n e rated. is cl eared to "0 " upo n read . d c h an nel sca n s i ngl e c o n v e r si o n m ode i f ad mod0 is set to "0 1," a / d c o n v e rsi o n i s per f o r m e d i n t h e c h an nel scan si ngl e c o nve rsi o n m ode. in t h i s m ode, a/ d c o nve rsi o n i s per f o r m e d o n ce for eac h scan c h a n nel selected. after a/d scan co nv ersion is co m p leted , admod0 is se t to "1," admod0 is cleared t o "0 ," an d th e i n terrup t requ est int a d is g e n e rate d. < e ocf> is cleared t o " 0 " upon read. e fi xed cha n nel repeat c o nve rsi o n m ode if a d m o d 0 < r epea t , sc a n > i s set t o "1 0," a/ d c o n v er si on i s pe rf orm e d i n fi xe d c h a nnel re peat co nv er sion m o d e . in t h i s m ode, a/ d c o n v er s i on i s pe rf o r m e d repeat e d l y for o n e cha nnel sel ect ed . aft e r a/ d co nv ersion is co m p leted , admod is se t t o "1." admod0 is no t cleared t o "0 ." it rem a in s at "1 ." th e ti min g with wh i c h th e in terru p t requ est int ad is g e n e rat e d can b e selected b y settin g admod0 t o an app r o p riate settin g . is set with th e sa me ti min g as th is i n terrup t int a d is g e n e rated. is cleared to " 0 " upon read. w ith set to "00," an interrupt re que st is ge nerated each tim e one a/ d c o nversi on is co m p leted . in t h is case, th e co nv ersion results ar e always store d in the st ora g e regi st er adr e g 08 . after th e con v ersion resu lt is sto r ed , eocf ch ang e s to "1 ." w i t h < i tm1: 0> set to " 0 1," an inte rrupt re que st is ge nera ted each tim e four a/ d c o nversion are co m p leted . in th is case, the con v e rsion resu lts are seq u e n tially sto r ed in storag e reg i sters adre g 08 th r o u g h adre g 3b. afte r th e c o n v e r sio n res u lts are st ore d i n adre g 3b, is set to "1," an d th e stor ag e of sub s eq u e n t co nv er sion results starts fro m adreg08 . is tmp19a43(rev2.0) 16-15 analog/digit a l converter
tmp19a43 cleared t o " 0 " upon read. w ith set to "10 , " an in terrup t req u e st i s ge ne ra t e d eac h t i m e ei ght a/ d c o n v ersi on s a r e co m p leted . in th is case, t h e co nv ersion resu lts are seq u e n tially sto r ed in storage reg i sters a d r eg0 8 th ro ugh ad reg7 f . af ter th e co nv er sion r e sults ar e sto r ed in ad reg 7 f , is set t o " 1 ," a n d t h e st o r age o f s ubs eq ue nt co n v ersi on res u l t s st art s f r om ad r e g0 8. is cleared to " 0 " upon read. f channel sca n repeat conversi on m ode if a d m o d0 is set to "1 1 , " a/d c onversi on is perform ed in t h e c h annel sca n repeat c o nve rsi o n m ode. in t h i s m ode, a/ d c o nve rsi o n i s per f o r m e d repeat e d l y f o r a scan c h a nne l sel ect ed. ea ch t i m e one a/d sca n c o n v ersi on is co m p leted, a d m od 0 is set to "1 ," and th e i n t e rru p t req u e st int ad is g e nerated . adm od0 is no t clear e d t o " 0 . " i t r e m a i n s a t " 1 . " < e o c f > i s cleared t o " 0 " upon read. t o st op t h e a/ d c o n v e r si o n o p erat i o n i n t h e repeat c o nv ersi on m ode (m odes des c ri be d i n e and f ab ov e), write "0 " to adm od0 . wh en on go ing a/ d conv ersi o n is com p le ted , th e repeat c o nve rsi o n m ode t e rm inat es, a n d ad m o d 0 < adb f> i s set t o "0 . " b e fo re s w i t c hi ng f r om one m ode t o st an d b y m ode (s uc h st a n d b y m odes as i d le , st op , et c.) , check t h at a/ d co nve rsi o n i s not bei n g e x ec ut ed. i f a/ d c o nve rsi o n i s u n d er way , y o u m u st st op it o r wait u n til it is co m p leted . (2 ) t o p- pr ior ity a / d co nv er sion t o p- pr ior ity a/d co nv er sion is p e r f o r m e d on ly i n f i x e d chann e l sing le co nv ersion m o d e . th e adm od 0 set t i ng has no rel e va nce t o t h e t o p- p r i o ri t y a/ d c o n v e r si o n o p e ration s or prep aratio ns. as ac tiv atio n requ irem en ts are met, a/ d c o nv ersi o n i s pe rf o r m e d onl y once fo r a c h an nel desi gn at ed by a d m od 2. a f t e r t h e a/ d c o nve rsi o n i s co m p leted , t h e t o p-p r iori ty a/d con v e rsion com p le tio n in t e rru p t is g e n e rated, adm od 2 is se t to " 1 ," a n d < adbf h p> re turns to "0." the e o cfhp fla g is cleare d u pon r ead. tmp19a43(rev2.0) 16-16 analog/digit a l converter
tmp19a43 relatio n ship s betwee n a/d conversio n mode s, in terrupt gene ratio n t i ming s an d flag ope r at ions ad m o d 0 con v ers i on mode inte rrupt ge ne ra tion timing eocf setting timing (see no te) a dbf (after the interrupt is ge ne ra te d) i t m 1 : 0 r e p e at s c an fixed ch annel single conversion after conv ersion is com p leted after conv ersion is com p leted 0 ? 0 0 each tim e one conversion is co mpleted after one conv er sion is com p leted 1 0 0 each tim e four conversions ar e com p leted after four conv ersions are com p let e d 1 0 1 fixed ch annel repeat conversion each tim e eigh t conversions ar e com p leted after eight conv ersions are com p let e d 1 1 0 1 0 channel s can s i n g le conversion after scan conv ersion is com p leted after scan conv ersion is com p leted 0 ? 0 1 channel s can re peat conversion each tim e one s c an conversion is co mpleted after one scan conversion is co mpleted 1 ? 1 1 (no t e ) eocf is clea red upon re a d . tmp19a43(rev2.0) 16-17 analog/digit a l converter
tmp19a43 16.2.5 high-priority conve rsion mode by in ter r u p ting o ngo ing n o rmal a / d conver s ion , t o p- pr i o r ity a / d conv er si o n can b e p e rfo r m ed . t o p - pri o rity a/d c o nve r sion can be s o ftwa re ac tivated b y settin g admod2 to "1 " or it can be activated using the hw res ource by setting adm od4< 7:6> to an ap propriate setti ng. i f t o p- pri o ri t y a / d conv er si on h a s b een acti v ated dur ing no r m al a / d conv er si o n , on go i n g n o r m al a / d con v e r s ion i s i n t e rr upt e d , an d si ngl e co n v er si on i s per f o r m e d fo r a c h an n e l desi g n at e d b y adm o d 2< 3 : 0>. t h e res u l t of si ngl e c o n v e rsi o n i s st ore d i n adr e g sp , and t h e t o p-p r io rity a/ d conv ersi o n i n terrup t is g e n e rated. after top - p r i o rity a/d conv ersio n is co m p leted , no rm al a/d co nv ersion i s resu m e d ; th e statu s o f n o rm al a / d co nv ersion imm e d i atel y befo r e b e ing in terru p t ed is m a in tain ed . t o p-priority a/d con v e rsion activ ated wh ile to p-p r iority a/ d co nv ersion i s un der way is ig no red . for exam ple, if cha n nel repeat conversi on is activated for ch an nel s a n 0 t h r o ug h an 8 a n d i f i s set t o " 1 " du ri n g a n 3 c o n v ersi on , an 3 con v e r si o n i s sus p en de d, a n d c o n v e r si o n i s per f o r m e d f o r a c h a nnel de si gnat e d by < h p a dc 3: 0> . aft e r t h e re su l t of co n v ersi on i s st ore d i n adr e g sp , ch annel re peat co nve rsi o n i s res u m e d, st art i n g fr om an 3. 16.2.6 a/d monito r function i f ad mod3 is set to "1 ," th e a / d m o n ito r fun c tio n is en ab led. if t h e v a lu e o f t h e conve r sion res u lt stora g e re gister s p ecifie d by re gs< 3 :0> bec o m e s lar g e r or sm aller ("lar g er" or "s m a ller" to be designated by adob ic) t h an t h e val u e of a c o m p ari s on regi st er , t h e a/ d m oni t o r fu nct i o n i n t e rr upt i s ge nerat e d. t h i s c o m p ari s on o p e r atio n is p e rfo r m e d each tim e a result is stored in a co rr esp ond ing co nv er sion r e su lt stor ag e r e g i ster , an d th e interrup t is g e n e rated if th e co nd itio n s are m e t . because st ora g e re gisters assi gne d t o perform the a/ d m onitor functi on are usually not read by s o ftwa re, ove rr u n fl a g < ovr n> i s al w a y s set and t h e con v e r si o n re sul t st ora g e fl ag i s al so set . t o use t h e a/ d m oni t o r f u nct i o n , t h ere f o r e, a fl a g of a co r r esp o ndi ng c o nve rsi o n res u l t st o r age re gi st er m u st not be us ed. 16.2.7 s t oring and reading a/d conversion result s a/ d c o nve rsi o n resul t s a r e st ore d i n up pe r and l o wer a/ d co nve rsi o n re sul t re gi st ers f o r n o rm al a/ d co nv er sion ( a d r eg08 h / l th rou g h ad rg7 f h / l) . in fi xe d c h a nnel repeat c o n v e r si o n m ode, a/ d c o n v ersi on res u l t s are se que nt i a l l y st ored i n adre g 08h/l through adr e g7fh/l . if < i tm1: 0> is s o set as to gene rate the inte rrupt each tim e on e a / d co nv er sion is co m p leted, conv er si o n r e su lts ar e st o r ed on ly in adreg08h/l. if is so set as to generate the in terrupt each ti m e four a/d conversions are com p le ted, conversion results are sequ en tially sto r ed i n adreg08h/l thro ug h adreg3 b h/l. t a bl e 1 6 . 1 sh o w s a n al o g i n p u t chan nel s a n d rel a t e d a/ d co nve rsi o n res u l t re gi st ers. tmp19a43(rev2.0) 16-18 analog/digit a l converter
tmp19a43 t able 16-1 an alog input ch annel s an d rela ted a/d conversion re sult re giste r s a / d co n v e r sio n resu lt reg i ster a n a l og inp u t c h a nne l (port a ) con v ers i on mode s othe r th an sh o w n to the right f i xed ch an n e l rep eat c o n v ers i on mode (e v e ry one co n v e r sio n ) f i xed ch an n e l rep eat c o n v ers i on mode (e v e ry four co n v e r sio n s ) f i xed ch an n e l rep eat co n v e r sio n mo d e (e v e ry e i ght co n v e r sio n s) a n 0 a d r e g 0 8 h / l a n 1 a d r e g 1 9 h / l a n 2 a d r e g 2 a h / l a n 3 a d r e g 3 b h / l a n 4 a d r e g 4 c h / l a n 5 a d r e g 5 d h / l a n 6 a d r e g 6 e h / l a n 7 a d r e g 7 f h / l a n 8 a d r e g 0 8 h / l a n 9 a d r e g 1 9 h / l a n 1 0 a d r e g 2 a h / l a n 1 1 a d r e g 3 b h / l a n 1 2 a d r e g 4 c h / l a n 1 3 a d r e g 5 d h / l a n 1 4 a d r e g 6 e h / l a n 1 5 a d r e g 7 f h / l adreg08 h /l fixed a dre g08h / l a dre g3b h / l a dr e g 0 8 h/ l a dr e g 7 f h / l 16.2.8 dat a polling t o p r o cess a/d con v e rsion resu lts with ou t u s ing i n terrup t s , adm od0 < eocf> m u st b e po lled . if t h is flag is set, conversi on re sults are stored in a sp eci fied a/ d conversi on re sult re gister . after c o nfirm i ng th at th is flag i s set, read t h at conv ersi o n resu lt st orage re gister . in rea d i n g the re gister , m a ke sure t h a t yo u first read up p e r b its and th en lower b its to d e t ect a n o v e rr un . if ovr n i s " 0 " a n d a d r n r f i s "1" i n l o we r bi t s , a c o rrect c o n v e r si o n resul t has be en obt ai ne d. tmp19a43(rev2.0) 16-19 analog/digit a l converter
tmp19a43 17. digit a l/analog converter th is section d e scrib e s th e d/ a con v e rter t h at is bu ilt in to t h e tmp19 a 43. 17.1 features ? a h i gh -reso l u tio n, 8 - b it d/ a co nv erter is bu ilt in to each o f two ch ann e ls o f th e tm 1 9 a4 3. ? each ch an n e l i s prov id ed with a bu f f er am p l ifier . ? each c h an nel c a n be i ndi vi d u a l l y put i n t o st and b y m ode b y m a ki ng an a p p r op ri at e cont rol re gi st er settin g . 17.2 operation (about the operat ion of the d/a converter) basic settings: ? set t h e c ont rol regi st er d a c c nt n t o < 1 : 1 >. ? a ssign an ou tpu t cod e t o the ou tpu t r e g i ster da re gn s o that an output vo ltage s p ecifi ed for that c ode ap pea r s at t h e out p u t p i n d a n . ? set da ccntn to "0 ," and th e ou t p u t p i n dan goes in t o pow e r d o wn m o d e . (th e electr i c pot e n t i a l of t h e pi n bec o m e s equal t o t h at o f t h e da vr e f p o we r s u ppl y . ) ? b y set t i ng d a c c n tn t o " 0 ," i r e f ca n be c u t a n d a c o n s um pt i o n cu rre nt ca n be red u ce d. da vre f da g nd da vcc + ? refonn da 0, 1 1 00p f ( m ax .) da g nd cvref ope n (note)please open the te rm in al cvref . fig. 17.2.1 d/ a converte r block diag ra m tmp19a43(rev2.0) 17-1 digit a l/analog converte r
tmp19a43 d a cc nt0 regis t er 7 6 5 4 3 2 1 0 daccn t 0 b i t sy mb o l r e f o n 0 o p 0 (0xff ff_ f 3 3 0 ) r e a d / w r i t e r / w r / w after reset 0 0 0 function "0" is read. 0: ref off 1: ref on 0: po w e r do w n 1: output output re gist er da reg0 7 6 5 4 3 2 1 0 d a r e g 0 b i t sy mb o l d a c 7 d a c 6 da c 5 d a c 4 d a c 3 d a c 2 d a c 1 d a c 0 (0xff ff_ f 3 3 1 ) r e a d / w r i t e r / w after reset 0 function d a cc nt1 regis t er 7 6 5 4 3 2 1 0 daccn t 1 b i t sy mb o l r e f o n 1 o p 1 (0xff ff_ f 3 3 8 ) r e a d / w r i t e r / w r / w after reset 0 0 0 function "0" is read. 0: ref off 1: ref on 0: po w e r do w n 1: output output re gist er da reg1 7 6 5 4 3 2 1 0 d a r e g 1 b i t sy mb o l d a c 7 d a c 6 da c 5 d a c 4 d a c 3 d a c 2 d a c 1 d a c 0 (0xff ff_ f 3 3 9 ) r e a d / w r i t e r / w after reset 0 function ? when setting refonn to "0," opn must also be set to "0." ? af ter "0" of refo nn is chang e d "1," w a it for 1 0 s ec(open the termina l cvref) msec durin g w h i c h time c i rcuitr y st abilizes. ? all v o lt ages in the rang e from dag nd throu gh da vcc (da v ref) ca nn ot be ou tpu t . a corre ct range of output v o lt ages must be v e rified b y ch ecking the e l ectrical cha r acteristic s w h i c h are later des c rib e d. ? (note 3)1 0 0 s(ty p.) is neces sar y b y the time th e v o lt age outp u t to dan af ter outpu t co de is set is stead y . tmp19a43(rev2.0) 17-2 digit a l/analog converte r
tmp19a43 18. w a tchdog t i mer (runaway detection t i mer) th e tm p19a43 h a s a bu ilt-in watchdo g timer for d e tectin g ru n a ways. th e w a tch dog ti m e r (w dt) is f o r d e tectin g m a lf u n c tion s (r un aw ays) of th e cpu cau s ed b y no ises o r o t h e r di st ur ba nces a nd rem e dy i ng t h em t o ret u rn t h e c p u t o n o rm al operat i o n. if t h e t i m e r det ect s a r u n a way , i t gene rat e s a n o n -m askabl e i n t e rr upt t o not i f y t h e c p u. by co nn ecting th e o u t p u t o f th e watchd og ti m e r to a reset p i n (in s i d e th e ch ip ), it is po ssib l e t o fo rce t h e watchd og tim e r to reset itself. 18.1 configuration fi g. 1 8 . 1 s h ow s t h e bl oc k di a g ram of t h e wa t c hd og t i m e r . internal reset wdmo d wdmo d reset watchdog timer contr ol register wdcr q r s binary counte r (22 stages) 2 22 internal reset w d m cr> o d tmp19a43 tmp19a43(rev2.0) 18-2 watchdog timer (runaway detection timer) 18.2 watchdog timer interrupt the watchdog timer consists of the binary counters th at are arranged in 22 stages and work using the f sys/2 system clock as an input clock. the outputs produced by these binary counters are 2 16 , 2 18 , 2 20 and 2 22 . by selecting one of these outputs with wdmod , a watchdog timer interrupt can be generated when an overflow occurs, as shown in fig. 18.. because the watchdog timer interrupt is a non-maskable interrupt f actor, nmiflg at the intc performs a task of identifying it. fig. 18.2 normal mode when an overflow occurs, resetting the chip itself is an opti on to choose. if the chip is reset, a reset is effected for a 32-state time, as shown in fig. 18.. if this reset is effected, the clock f sys that the clock gear generates by dividing the clock f c of the high-speed oscillator by 8 is used as an input clock f sys/2 . fig. 18.3 reset mode 0 wdt interrupt wdt clear write of a clear code wdt counter n overflow overflow wdt counter n wdt interrupt 32-state (12.8 s @ f c = 40 mhz, f sys = 5 mhz, f sys/2 = 2.5 mhz) internal reset
tmp19a43 18.3 control registers th e watchdo g ti m e r (w dt) i s con t ro lled b y two con t ro l reg i sters wdm o d an d wdcr. 18.3.1 w a tchdog t i mer mod e register (wdmod) c sp ecif y ing t h e d e tectio n ti m e o f th e w a tchdog tim er th is is a 2 - b it reg i ster for sp ecifying t h e watc hd og ti m e r in terru p t ti me fo r run a way d e tection . wh en a reset is ef fected, t h is reg i st er is i n itialized to wdmod = "00 . " fig. 18 .1 sh ows th e d e tectio n tim e o f the watchdo g timer . d en ab lin g / d i sablin g th e watchd og tim er whe n reset, wdmod < w dte> is i n itiali zed to "1 " and th e watch dog t i m e r is en ab led. t o d i sab l e th e watchd og tim e r , th is b it m u st b e set to "0 " an d, at th e same ti me, th e disab l e cod e (b1h) m u st b e written to t h e wdcr reg i ster . th is du al settin g is in ten d e d to m i n i m i ze th e p r ob ab ility th at th e watchd og t i m e r m a y in ad v e rten tly b e d i sab l ed if a ru n a way o c curs. t o c h ange t h e status of t h e watchdog tim er from "d isab le" t o "en a b l e," set th e b it to "1 ." e w a tchdo g tim e r o u t reset co nn ectio n thi s i s a re gi st er fo r speci fy i n g whet her or not t o reset th e watch dog timer itself after a run a way is d e tected . as a reset in itializes th is settin g to wdm o d = "0," a reset in itiated th e o u t p u t o f th e w a tchdog tim er is n o t per f o r m e d . 18.3.2 w a tchdog t i mer control register (wdcr) th is is a reg i st er for d i sab ling the watchd og tim er fun c tion an d co n t ro llin g th e clearing fu n c tion of t h e bi na ry co u n t e r . ? di sabl i n g c o nt rol by writin g th e d i sab l e cod e (b1 h ) to th is wdcr reg i ster after setting wdm o d t o "0 ," t h e wat c hd o g t i m e r can be di s a bl ed. wdmo d 0 ? ? ? ? ? ? ? clears w d te to "0." wdcr 1 0 1 1 0 0 0 1 w r ites the disab l e cod e (b1h) . ? en ab lin g con t ro l set wdmod < w dte> to " 1 ." ? w a tchdo g tim e r clearing con t ro l w r iting t h e cl ear code (4eh) to the wdc r register clears th e b i n a ry co un ter and al lo ws it to resu m e co un ting . wdcr 0 1 0 0 1 1 1 0 w r i t e s t h e cl ea r c ode (4e h ) (no t e ) w r iting the d i sable code (bih) cl ears the binar y co unte r . tmp19a43(rev2.0) 18-3 w a tchdo g t i mer (run a w a y d e tection t i mer)
tmp19a43 tmp19a43(rev2.0) 18-4 watchdog timer (runaway detection timer) 7 6 5 4 3 2 1 0 bit symbol wdte wdtp1 wdtp0 i2wdt rescr ? read/write r/w r/w r r/w r/w after reset 1 0 0 0 0 0 0 function wdt control 1: enable selects wdt detection time 00: 2 16 /f sys 01: 2 18 /f sys 10: 2 20 /f sys 11: 2 22 /f sys "0" is read. idle 0: stop 1: start 1: internally connect wdt output to reset pin write "0." 0 generates nmi interrupt 1 connects wdt out to reset detection time of watchdog timer wdmod syscr1 clock gear value 00 01 10 11 000 (fc) 1.6 ms 6.5 ms 26.2 ms 105 ms 100 (fc/2) 3.3 ms 13.1 ms 52.4 ms 210 ms 110 (fc/4) 6.5 ms 26.2 ms 105 ms 419 ms 111 (fc/8) 13.1 ms 52.4 ms 209 ms 839 ms 0 disable 1 enable fig. 18.4 watchdog timer mode register 7 6 5 4 3 2 1 0 bit symbol ? read/write w after reset ? function b1h : wdt disable code 4eh : wdt clear code b1h disable code 4eh clear code others ? fig. 18.5 watchdog timer control register disable & clear of wdt wdcr (0xffff_f091) wdmod (0xffff_f090) detection time of watchdo g time r @ fc = 40 mhz enable/disable control of the watchdog timer watchdog timer out control
tmp19a43 18.4 operation description th e w a tch dog tim er g e n e r a tes th e i n twd t in terr up t af ter a lap s e o f th e d e tectio n tim e sp ecified b y t h e wdm od < w dtp 1 , 0> re gi st er . b e f o re ge nerat i n g t h e i n t w d in terrup t, th e b i n a ry co un ter for th e watchd og t i m e r m u st be cl eared t o " 0 " usi n g s o ft ware (i nst r uct i on) . i f t h e cpu m a lf un ctio n s (r uns aw ay) du e t o no ise o r ot he r di st ur ba n ces an d can n o t exec ut e t h e i n st ruct i o n t o cl e a r t h e bi na ry c o u n t e r , t h e bi n a ry co u n t e r o v e rfl o w s an d th e intwd i n terrup t is g e n e rated. th e cpu is ab le t o rec o g n i ze t h e occ u rre nce o f a m a l f unct i o n (r u n away ) b y id en tifyin g th e intwd in terru p t and t o resto r e th e fau lty con d ition to no rm al b y u s ing a m a l f un ction (ru n a way) co un term easu r e prog ram . add itio n a lly , it is p o s sib l e t o reso lv e th e p r ob lem o f a m a lfun ctio n (r una way ) o f t h e c p u by c o n n ect i n g t h e wat c hd o g t i m er ou t pi n t o reset pi ns of pe ri p h era l devi ces . th e w a tchdo g ti m e r b e g i ns op er ation im m e diately after a reset is cleared. in st op m o de, th e watchd og tim er is reset an d i n an id l e state. wh en th e bu s is o p e n ( busak = "l"), it co n tinu e s co untin g . in idle m o d e , its op eratio n d e p e nd s o n th e wdm o d settin g . before p u tting i t in idle m o d e , wdmod m u st be set to an app r o p riate settin g, as requ ired . exam ples: c t o clear t h e bi nary c o unter 7 6 5 4 3 2 1 0 wdcr 0 1 0 0 1 1 1 0 w r i t e s t h e cl ea r c ode (4e h ) d t o set th e d e tectio n tim e o f the watchdo g timer to 2 18 /f sys 7 6 5 4 3 2 1 0 wdmo d 1 0 1 ? ? ? ? ? e t o d i sab l e the watchd og tim e r 7 6 5 4 3 2 1 0 wdmo d 0 ? ? ? ? ? ? ? clears wdte to "0" wdcr 1 0 1 1 0 0 0 1 w r ites the disab l e cod e (b1h) note: if the w a tchdog timer is operated w h en the high-frequency oscillator is idle, the s y stem reset operatio n initiated b y the w a tch d o g timer becomes erratic due to the unst a ble oscillation of the hi gh-frequenc y oscill ator . the refore, do not operate the w a tchdog ti mer w h en the high-frequenc y oscillator is idle. tmp19a43(rev2.0) 18-5 w a tchdo g t i mer (run a w a y d e tection t i mer)
tmp19a43 19. clock t i mer 19.1 features tm p1 9a 4 3 ca n be use d i n t h ese o p erat i o n m odes. th is cl o c k timer u s ing a l o w clo c k fr equ e n c y o f 3 2 .768 kh z can g e n e r a t e in terr up ts at ti m e in ter v als o f 0.125 s, 0. 25 0s, 0. 5 0 0 s and 1. 0 00s s o t h at t h e tm p 1 9 a 4 3 i s abl e t o use t h e cl oc k f unct i o n whe n ope rat i n g i n l o w- po we r - di ssi pat i o n ope rat i o n m odes. th is clo c k ti mer can b e op erated in all o p e ratio n m o d e s of lo w-freq u e n c y o s cillatio n . the in terru p t g e nerated b y t h i s cl oc k al l o ws t h e tm p 1 9a 4 3 t o rec o v e r f r o m st and b y m ode (e xc ept st op m ode) an d ret u rn t o n o rm al ope rat i o n m ode. t o use t h e c l ock t i m er i n t e rr upt (i ntr t c ) , th e imcgd reg i ster in t h e cg m u st be set to an appropriate setting. fi g. 1 9 - 1 s h ow s t h e bl oc k di a g ram of t h e cl o c k t i m er . 15-stage binary c ounter selector rtcc r rtcc r 2 15 run /clear 2 14 2 13 2 12 /clear rtcre g 32-bit cumulative register interrup t requ est intrt c fs (32.768 khz) fig. 19-1 blo ck diag ram o f the clock t i mer note:a built-in register i s initialized by res et with the termi nal reset. on the other hand, when re setting it by wdt an d dsu, it is not initialized. tmp19a43(rev2.0) 19-1 clock t i mer
tmp19a43 register th e cl o c k ti m e r is co n t ro lled b y th e cl o c k timer con t ro l reg i ster (r tccr). fi g. 1 9 - 2 s h ow s t h e cl ock t i m e r c ont r o l regi s t er . (fs = 32.768 khz) 7 6 5 4 3 2 1 0 bit sy mb ol r t c r c l r rtcsel1 rtcsel0 rtcr un r e a d / w r i t e r / w r / w r w r / w r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 f u n c t i o n w r i t e "0." write "0." "0" is read. clear cum u la tiv e register 0: c l e a r 1: don' t c a re interrup t gene ration cy cle 00: 2 15 /fs (1.000 s) 01: 2 14 /fs (0.500 s) 10: 2 13 /fs (0.250 s) 11: 2 12 /fs (0.125 s) binary coun ter 0: s t op & clear 1: coun t 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t sy mb o l r e a d / w r i t e r a f t e r r e s e t 0 0 0 0 0 0 0 0 f u n c t i o n 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t sy mb o l r e a d / w r i t e r a f t e r r e s e t 0 0 0 0 0 0 0 0 f u n c t i o n 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t sy mb o l r e a d / w r i t e r a f t e r r e s e t 0 0 0 0 0 0 0 0 f u n c t i o n r t ccr (0x f f ff_e70 4 ) (0x f f ff_e70 7 ) l i tt le big fig. 19-2 clo ck t i mer con t rol regi ste r (no t e 1 ) t o acc ess th is registe r , 32-bit a cces s is required. ( n ot e 2) v a lues read f rom r t c cr< rtcr clr> are al w a y s " 1 ." (note 3) before changing the rtccr setting, make sure that r t ccr is "0" and t h at the rtc interrupt is disabled. (no t e 4) a b u ilt-in register is initializ ed b y reset w i th the ter m inal reset . when r ese tti ng it b y wdt and ds u, it is not initializ ed. tmp19a43(rev2.0) 19-2 clock t i mer
tmp19a43 th e clo c k tim e r is p r ov id ed with a clo c k co un t cu m u lativ e reg i ster for co un ting th e n u m b er o f ti m e s in terru p t s are gene rated. clo ck cou n t cumul a tiv e r egiste r 7 6 5 4 3 2 1 0 bit sy mb o l r u i 7 r u i 6 r u i 5 r u i 4 r u i 3 r u i 2 r u i 1 r u i 0 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 function accumulate count value 1 5 1 4 1 3 1 2 1 1 1 0 9 8 bit sy mb o l r u i 1 5 r u i 1 4 r u i 1 3 r u i 1 2 r u i 1 1 r u i 1 0 r u i 9 r u i 8 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 function accumulate count value 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 bit sy mb o l r u i 2 3 r u i 2 2 r u i 2 1 r u i 2 0 r u i 1 9 r u i 1 8 r u i 1 7 r u i 1 6 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 function accumulate count value 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 bit sy mb o l r u i 3 1 r u i 3 0 r u i 2 9 r u i 2 8 r u i 2 7 r u i 2 6 r u i 2 5 r u i 2 4 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 function accumulate count value r t cre g (0x f f ff_e70 8 ) fig. 19-3 clo ck cou n t cu mulative regi ster (no t e 1 ) a w r ite to thi s cumulativ e register cle a rs the p r es caler . (no t e 2 ) interrup t s must be disa bled during a r ead. (no t e 3 ) t o acc ess th is registe r , 32-bit a cces s is required. tmp19a43(rev2.0) 19-3 clock t i mer
tmp19a43 exam pl e of t h e cl ock t i m er i n terr upt set t i ng: in itializatio n 7 6 5 4 3 2 1 0 imcd 0 0 0 1 0 0 0 0 disables th e inte rrupt intr tc sets the bit <15 : 8> of a 32-b i t register r t ccr 0 0 0 0 x x x 0 s t ops the r t c timer count sets the bit <7 :0 > of a 32-b i t register imcgd 0 0 1 0 0 0 0 1 sets the bit <15 : 8> of a 32-b i t register eicrc g 0 0 0 0 1 1 0 1 clears the interr upt requ est for the cg blo c k set th e bit <7:0> of a 32-bit r e gis t er intclr 1 1 1 1 0 0 0 0 clears the interr upt requ est for the intc b l ock sets the bit <8 :0 > of a 32-b i t register r t ccr 0 0 0 0 1 x x 1 s t arts the timer count sets the bit <7 :0 > of a 32-b i t register imcd 0 0 0 1 0 x x x sets the int e rrup t l e vel set th e bit <15:8 > of a 32-b i t register intr tc interrupt 7 6 5 4 3 2 1 0 eicrc g 0 0 0 0 1 1 0 1 clears the interr upt requ est for the cg blo c k sets the bit <7 :0 > of a 32-b i t register intclr 1 1 1 1 0 0 0 0 clears the interr upt requ est for the intc b l ock sets the bit <8 :0 > of a 32-b i t register processing interrup t ion finished (no t e 1 ) x means "do n 't ca re." (no t e 2 ) t o disable in terrup t s , imce must be fir s t se t and th en imcg d. tmp19a43(rev2.0) 19-4 clock t i mer
tmp19a43 20. key - on w akeup circuit 20.1 outline ? the tm p1 9 a 4 3 has 3 2 key i n p u t s , ke y 0 0 t o k e y 3 1, w h i c h ca n be use d f o r rel easi n g t h e s t o p m o d e or for ex tern al in terrup ts. no te th at in te rr up t pr o c essin g is ex ec u t ed with o n e in terrup t fact or fo r t h e 3 2 i n put s. (t hi s i s pr og ram m ed i n t h e c g bl o c k. ) each key i n p u t can be co nfi g u r ed t o be u s ed o r n o t , by p r og ram m i ng ( k wu ps tn)< ke y n en >. ? the act i v e st at e o f eac h i n p u t can be co nfi g ure d t o t h e ri si ng ed ge, t h e fa l l i ng e dge , bot h e dge s, t h e hi gh l e vel or t h e l o w l e ve l , by pr o g ram m i ng ( k wu ps tn)< ke y n >. ? an in terrup t requ est is cleared b y p r ogrammi n g th e k e y in terrup t requ est clear reg i ster kwupclr in th e in terru p t pro cessing . ? the key i n put pi ns ha ve p u l l -u p fu nct i o ns, w h i c h ca n be swi t c hed bet w een st at i c pu l l - up a n d dy nam i c pul l - u p by p r o g ram m i ng t h e (k w u pst n ) bi t . t h i s p r og ram m i ng i s neede d f o r each of 32 i n puts. fs lev el/edge kupin dy namic pull- up s t atic pul l -up dpup 1 1 1 1 1 rd clr rd clr iph iph iph iph fs ke y e n int kwupint pke y high/low lev el 20.2 key - on w akeup operation the tm p 1 9a 43 has 3 2 key i n p u t pi ns, ke y0 0 t o key 3 1. pr o g ram t h e im c g d3< k wu pen > re gi st er i n t h e cg to d e term i n e wh et h e r to u s e t h e k e y inp u t s fo r releasi n g th e st op m o d e o r fo r no rm al in terrup t s. settin g t o "1 " cau s es all th e k e y in pu ts, key00 to key 3 1, to b e used f o r inte rr upts fo r rele asing t h e st o p m ode. pro g r am kwu pstn< ke y n e n > t o e n abl e o r di sa bl e i n t e rr upt i n p u t s f o r e ach key i n p u t pi n. al so , program kw upstn< ke yn2: keyn0> to de fine the active state of each key inpu t pin t o be use d . det ection of key i n p u t s i s c a rri ed out i n t h e k w u p bl ock , a n d t h e det ect io n resu lts are n o tified t o th e imcgd3 reg i ster in th e c g as t h e act i v e hi g h l e vel . t h ere f o r e, pr og ram im c g d3< e m c gd 0 : 1> t o " 01" t o det e rm i n e t h e det ect i o n lev e l to th e h i gh lev e l. th e resu lts o f d e tectio n i n th e cg are also n o tified to th e in terrupt co n t ro ller intc as th e activ e h i gh level. th erefore, p r og ram th e intc to "01 " t o de fi ne t h e c o rres p o n d i n g i n t e rr upt as t h e hi gh l e vel . settin g imcgd3 to 0 (d efau l t ) configu r es a ll th e inp u t p i n s , key0 0 to key3 1 to the no rm al in ter r u p t s. in t h is case, you do n? t h a v e to mak e setting s at th e cg , bu t j u st sp ecif y t h e in tc d e tectio n lev e l t o th e h i gh lev e l. prog ram kwupstn in th e sam e way to en abl e or di sa bl e eac h key i n p u t a n d defi ne t h ei r act i v e states. w r itin g "10 1 0 " t o kwupclr du ring in terrup t pro c essin g clears al l th e k e y i n terru p t req u e sts. (note) if t w o or more ke y input s are generated, all the ke y input request s w ill be cleared by clearing interrup t req u est s. tmp19a43(rev2.0)20-1 key-on w a k eup circuit
tmp19a43 20.3 pull-up function each k e y inp u t h a s the pu ll-up fun c tion and can b e pro g rammed b y settin g th e reg i ster in th e p o rt. wh en a static p u ll-up is set, can it no t d e p e nd o n kwupstn < keyn en > an d th e pu ll-up b e u s ed . 20.3.1 cautions on use of key input s w i th pull-up enabled a) wh en y o u m a k e th e first sett in g after turn in g t h e p o wer on (ex a m p le: p o rt e0 with in terrup ts at bot h e dge s) 1 ) mak e a setting o f th e po rt. pefc = "1 " th e fun c tion is set to t h e k e y . pepe = "1" pull-up on c o ntrol 2) set k w u pst 0 8 t o " 0 " f o r t h e key i n put t o be use d . 3) set k w ups t 08< ke y 0 8 2 : k ey 08 0> t o " 1 0 0 " t o de fi ne t h e act i v e st at e of t h e key i n p u t t o be use d . 4) set k w u pst 0 8 t o " 1 " f o r t h e key i n put t o be use d . 5 ) w a it un til th e p u ll-up o p e ratio n is co m p lete d . 6 ) set kwupclr to "1 010 " to clear in terrup t requ ests. 7 ) program th e cg an d th e intc b y settin g imcgd3 to "01 " an d imcgd3< k wupe n> t o "1." (r efer t o c h a p t e r 6 , "i nt er ru p t set t i ngs" fo r t h e det a i l s of se t t i ng m e t hods. ) b) t o c h ange t h e active state of a k e y inpu t durin g op er ation 1) set k w u pst 0 8 t o " 0 " f o r t h e key i n put t o be use d . 2 ) d i sab l e k e y in t e r r u p t s b y settin g i m c4 to "000" at th e i n tc . 3) set k w u pst 0 8 t o " 1 " f o r t h e key i n put t o be use d . 4) c h an ge t h e act i v e st at e by set t i ng k w u p s t 08< ke y 0 8 2 : k ey 08 0> t o " 0 0 0 " f o r t h e key i n p u t to b e ch ang e d. (ex a m p le: lo lev e l in terrup t) 5 ) clear in terrup t requ ests b y set tin g kwupclr to "1 010 ." 6 ) en ab le th e k e y in terrup t at th e intc. set im c4 to a d e sired l e v e l "xxx ." c) t o en ab le a k e y in pu t during o p e ration 1 ) d i sab l e k e y in t e r r u p t s b y settin g i m c4 to "000" at th e i n tc . 2 ) set kwupstn t o "0 " for t h e k e y in pu t to b e used . 3) defi ne t h e act i v e st at e of t h e key i n put t o be use d at t h e c o r r esp o ndi ng k w u pst n. 4 ) set kwupstn t o "1 " for t h e k e y in pu t to b e used . 5 ) w a it un til th e p u ll-up o p e ratio n is co m p lete d . 6 ) clear in terrup t requ ests b y set tin g kwupclr. 7) ena b l e key i n t e rr upt s at t h e i n tc . (s et im c 4 t o a desi re d l e vel . ) tmp19a43(rev2.0)20-2 key-on w a k eup circuit
tmp19a43 20.3.2 cautions on use of key input s w i th pull-up disabled a) wh en y o u m a k e th e first settin g after turn i n g th e power on 1 ) set pepe t o "0 " to select th e pu ll-up off con t ro l. 2 ) set kwupstn t o "0 " for t h e k e y in pu t to b e used . 3) set k w ups t 08< ke y 0 8 2 : k ey 08 0> t o " 0 0 0 " t o de fi ne t h e act i v e st at e of t h e key i n p u t t o be use d . 4 ) set kwupstn t o "1 " for t h e k e y in pu t to b e used . 5 ) set kwupclr to "1 010 " to clear in terrup t requ ests. 6 ) program th e c g and th e intc. (refer to ch ap ter 6 , "interrup t settin gs" for th e details o f set t i ng m e t hod s.) b) t o c h ange t h e active state of a k e y inpu t durin g op er ation 1 ) d i sab l e k e y in t e r r u p t s b y settin g i m c4 to "000" at th e i n tc . 2 ) set kwupstn t o "0 " for t h e k e y in pu t to b e used . 3) c h an ge t h e act i v e st at e by s e t t i ng k w up st n fo r t h e key i n put t o be c h a n g e d. 4 ) set kwupstn t o "1 " for t h e k e y in pu t to b e used . 5 ) clear in terrup t requ ests b y set tin g kwupclr. 6) ena b l e key i n t e rr upt s at t h e i n tc . (s et im c 4 t o a desi re d l e vel . ) c) t o en ab le a k e y in pu t during o p e ration 1 ) d i sab l e k e y in t e r r u p t s b y settin g i m c4 to "000" at th e i n tc . 2 ) set kwupstn t o "0 " for t h e k e y in pu t to b e used . 3) defi ne t h e act i v e st at e by set t i ng k w u pst n f o r t h e key i n p u t t o be use d . 4 ) set kwupstn t o "1 " for t h e k e y in pu t to b e used . 5 ) clear in terrup t requ ests b y set tin g kwupclr. 6) ena b l e key i n t e rr upt s at t h e i n tc . (s et im c 4 t o a desi re d l e vel . ) tmp19a43(rev2.0)20-3 key-on w a k eup circuit
tmp19a43 key-on w a ke up co ntrol 7 6 5 4 3 2 1 0 k w u p c n t bit sy mb o l t 2 s 1 t 2 s 0 t 1 s 1 t 1 s 0 (0xff ff_ f 3 8 4 ) r e a d / w r i t e r / w r r / w r a f t e r r e s e t 0 0 0 0 0 0 0 f u n c t i o n m a k e s u r e that y ou write "0." this c a n be read a s "0 ." d y namic pull-up cy cle 00: 256/fs 10: 1024/fs 01: 512/fs 11: 2048/fs d y namic pull-up duration 00: 2/fs 10: 8/fs 01: 4/fs 11: 16/fs this can be read as "0." dy nam i c pul l - up o p e r at i o n i s exec ut ed as s h ow n bel o w . t1 t2 pul l - up i s e x e c ut ed onl y i n t h e t1 pe ri o d det e rm i n ed by . pul l - up i s n o t exec ut ed i n t h e rem a i n i ng pe ri od . 00: 2/ fs ( 6 2. 5 s @fs = 32 khz) 01: 4/ fs ( 1 25 s @fs = 32 khz) 10: 8/ fs ( 2 50 s @fs = 32 khz) 1 1 : 16 /fs (5 00 s @fs = 32 khz) dyn a m i c p u ll-u p op eratio n is rep eated i n the t2 cycle determined by < t 2s1:0> . 00: 2 56/ fs (8 m s @ f s = 3 2 kh z) 01: 5 12/ fs (1 6 m s @fs = 3 2 k h z) 1 0 : 10 24 /f s (32 m s @f s = 3 2 kh z) 1 1 : 204 8 / fs (64 m s @f s = 3 2 kh z) fs must b e operated w h il e d y namic p u ll-up is use d . tmp19a43(rev2.0)20-4 key-on w a k eup circuit
tmp19a43 20.4 key input de tection t i ming 1 ) wh en t h e static pu ll-up is selected b y settin g pn pe to 1 and kwupstn < dpen > to 0 : the act i v e st at e of eac h key i n p u t can be d e fi ne d t o t h e h i gh or l o w l e v e l or t o t h e ri s i ng a nd/ or fal l i ng e d ges b y set t i ng k w upst n< ke yn 2: 0>. t h e act i v e st at es o f ke y i n p u t s a r e c o nt i n u o u sl y detected. 2) whe n t h e dy na m i c pul l - u p i s sel ect ed by set t i ng pn pe t o 1 a n d k w upst n< dpe n > t o 1: detection of the active state of each key input (inte r rupt de tection) is ca rrie d out only at the edge one -cl o c k be fo re fs at t h e en d of t h e t 1 pe ri o d . t h ere f or e, a key i n p u t not sh o r t e r t h a n t h e t 2 peri od i s nee d ed. in t h i s cas e, do not de fi n e t h e active state to t h e high or l o w level . there is a del a y u p t o t h e t 2 peri od b e fo re key i n p u t det ect i o n . t h e fi g u re bel o w s h ow s a n e x am pl e of d e fi n i ng th e activ e state to th e fallin g edg e . pull- up( t 1 ) (t2) h or high -z t2 period o r long er is required (l period) interrup t detectio n timing h or high -z o r l ke y input ke y input detecti on internal sampling results tmp19a43(rev2.0)20-5 key-on w a k eup circuit
tmp19a43 the ext e rnal s t at e of p o rt va l u e ca n be m oni t o re d d u r i n g dy nam i c pul l - up op erat i o n b y re fer r i n g t o t h e pke y n

re gister . sam p lin g is execu ted i n t h e dynamic pull-up cycle. 7 6 5 4 3 2 1 0 pke y 0 b i t sy mb o l pke y 0 7 pke y 0 6 pke y 0 5 pke y 0 4 pke y 0 3 pke y 0 2 pke y 0 1 pke y 0 0 (0xff ff_ f 3 8 0 ) r e a d / w r i t e r a f t e r r e s e t 0 0 0 0 0 0 0 0 f u n c t i o n p o r t s t a t e 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" 7 6 5 4 3 2 1 0 pke y 1 b i t sy mb o l pke y 1 5 pke y 1 4 pke y 1 3 pke y 1 2 pke y 1 1 pke y 1 0 pke y 0 9 pke y 0 8 (0xff ff_ f 3 8 1 ) r e a d / w r i t e r a f t e r r e s e t 0 0 0 0 0 0 0 0 f u n c t i o n p o r t s t a t e 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" 7 6 5 4 3 2 1 0 pke y 2 b i t sy mb o l pke y 2 3 pke y 2 2 pke y 2 1 pke y 2 0 pke y 1 9 pke y 1 8 pke y 1 7 pke y 1 6 (0xff ff_ f 3 8 2 ) r e a d / w r i t e r a f t e r r e s e t 0 0 0 0 0 0 0 0 f u n c t i o n p o r t s t a t e 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" 7 6 5 4 3 2 1 0 pke y 3 b i t sy mb o l pke y 3 1 pke y 3 0 pke y 2 9 pke y 2 8 pke y 2 7 pke y 2 6 pke y 2 5 pke y 2 4 (0xff ff_ f 3 8 3 ) r e a d / w r i t e r a f t e r r e s e t 0 0 0 0 0 0 0 0 f u n c t i o n p o r t s t a t e 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" port state 0: "lo" 1: "hi" tmp19a43(rev2.0)20-6 key-on w a k eup circuit
tmp19a43 7 6 5 4 3 2 1 0 k w u p s t 0 0 b i t s y m b o l d p e 0 0 ke y 002 ke y 001 ke y 000 ke y 00en (0xff ff_ f 3 6 0 ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 0 0 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 00 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 0 1 b i t s y m b o l d p e 0 1 ke y 012 ke y 011 ke y 010 ke y 01en (0xff ff_ f 3 6 1 ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 0 1 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 01 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 0 2 b i t s y m b o l d p e 0 2 ke y 022 ke y 021 ke y 020 ke y 02en (0xff ff_ f 3 6 2 ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 0 2 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 02 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 0 3 b i t s y m b o l d p e 0 3 ke y 032 ke y 031 ke y 030 ke y 03en (0xff ff_ f 3 6 3 ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 0 3 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 03 interrupt input 0: disable 1: enable tmp19a43(rev2.0)20-7 key-on w a k eup circuit
tmp19a43 7 6 5 4 3 2 1 0 k w u p s t 0 4 b i t s y m b o l d p e 0 4 ke y 042 ke y 041 ke y 040 ke y 04en (0xff ff_ f 3 6 4 ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 0 4 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 04 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 0 5 b i t s y m b o l d p e 0 5 ke y 052 ke y 051 ke y 050 ke y 05en (0xff ff_ f 3 6 5 ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 0 5 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 05 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 0 6 b i t s y m b o l d p e 0 6 ke y 062 ke y 061 ke y 060 ke y 06en (0xff ff_ f 3 6 6 ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 0 6 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 06 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 0 7 b i t s y m b o l d p e 0 7 ke y 072 ke y 071 ke y 070 ke y 07en (0xff ff_ f 3 6 7 ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 0 7 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 07 interrupt input 0: disable 1: enable tmp19a43(rev2.0)20-8 key-on w a k eup circuit
tmp19a43 7 6 5 4 3 2 1 0 k w u p s t 0 8 b i t s y m b o l d p e 0 8 ke y 082 ke y 081 ke y 080 ke y 08en (0xff ff_ f 3 6 8 ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 0 8 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 08 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 0 9 b i t s y m b o l d p e 0 9 ke y 092 ke y 091 ke y 090 ke y 09en (0xff ff_ f 3 6 9 ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 0 9 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 09 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 1 0 b i t s y m b o l d p e 1 0 ke y 102 ke y 101 ke y 100 ke y 10en (0xff ff_ f 3 6 a ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 1 0 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 10 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 1 1 b i t s y m b o l d p e 1 1 ke y 112 ke y 111 ke y 110 ke y 11en (0xff ff_ f 3 6 b ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 1 1 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 11 interrupt input 0: disable 1: enable tmp19a43(rev2.0)20-9 key-on w a k eup circuit
tmp19a43 7 6 5 4 3 2 1 0 k w u p s t 1 2 b i t s y m b o l d p e 1 2 ke y 122 ke y 121 ke y 120 ke y 12en (0xff ff_ f36c ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 1 2 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 12 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 1 3 b i t s y m b o l d p e 1 3 ke y 132 ke y 131 ke y 130 ke y 13en (0xff ff_ f36d ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 1 3 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 13 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 1 4 b i t s y m b o l d p e 1 4 ke y 142 ke y 141 ke y 140 ke y 14en (0xff ff_ f 3 6 e ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 1 4 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 14 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 1 5 b i t s y m b o l d p e 1 5 ke y 152 ke y 151 ke y 150 ke y 15en (0xff ff_ f36f ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 1 5 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 15 interrupt input 0: disable 1: enable tmp19a43(rev2.0)20-10 key-on w a k eup circuit
tmp19a43 7 6 5 4 3 2 1 0 k w u p s t 1 6 b i t s y m b o l d p e 1 6 ke y 162 ke y 161 ke y 160 ke y 16en (0xff ff_ f 3 7 0 ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 1 6 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 16 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 1 7 b i t s y m b o l d p e 1 7 ke y 172 ke y 171 ke y 170 ke y 17en (0xff ff_ f 3 7 1 ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 1 7 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 17 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 1 8 b i t s y m b o l d p e 1 8 ke y 182 ke y 181 ke y 180 ke y 18en (0xff ff_ f 3 7 2 ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 1 8 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 18 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 1 9 b i t s y m b o l d p e 1 9 ke y 192 ke y 191 ke y 190 ke y 19en (0xff ff_ f 3 7 3 ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 1 9 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 19 interrupt input 0: disable 1: enable tmp19a43(rev2.0)20-1 1 key-on w a k eup circuit
tmp19a43 7 6 5 4 3 2 1 0 k w u p s t 2 0 b i t s y m b o l d p e 2 0 ke y 202 ke y 201 ke y 200 ke y 20en (0xff ff_ f 3 7 4 ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 2 0 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 20 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 2 1 b i t s y m b o l d p e 2 1 ke y 212 ke y 211 ke y 210 ke y 21en (0xff ff_ f 3 7 5 ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 2 1 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 21 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 2 2 b i t s y m b o l d p e 2 2 ke y 221 ke y 221 ke y 220 ke y 22en (0xff ff_ f 3 7 6 ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 2 2 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 22 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 2 3 b i t s y m b o l d p e 2 3 ke y 232 ke y 231 ke y 230 ke y 23en (0xff ff_ f 3 7 7 ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 2 3 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 23 interrupt input 0: disable 1: enable tmp19a43(rev2.0)20-12 key-on w a k eup circuit
tmp19a43 7 6 5 4 3 2 1 0 k w u p s t 2 4 b i t s y m b o l d p e 2 4 ke y 242 ke y 241 ke y 240 ke y 24en (0xff ff_ f 3 7 8 ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 2 4 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 24 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 2 5 b i t s y m b o l d p e 2 5 ke y 252 ke y 251 ke y 250 ke y 25en (0xff ff_ f 3 7 9 ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 2 5 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 25 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 2 6 b i t s y m b o l d p e 2 6 ke y 262 ke y 261 ke y 260 ke y 26en ( 0 x fff f_f37a ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 2 6 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 26 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 2 7 b i t s y m b o l d p e 2 7 ke y 272 ke y 271 ke y 270 ke y 27en ( 0 x fff f_f37b ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 2 7 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 27 interrupt input 0: disable 1: enable tmp19a43(rev2.0)20-13 key-on w a k eup circuit
tmp19a43 7 6 5 4 3 2 1 0 k w u p s t 2 8 b i t s y m b o l d p e 2 8 ke y 282 ke y 281 ke y 280 ke y 28en (0xff ff_ f37c ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 2 8 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 28 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 2 9 b i t s y m b o l d p e 2 9 ke y 292 ke y 291 ke y 290 ke y 29en (0xff ff_ f37d ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 2 9 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 29 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 3 0 b i t s y m b o l d p e 3 0 ke y 302 ke y 301 ke y 300 ke y 30en (0xff ff_ f 3 7 e ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 3 0 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 30 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 k w u p s t 3 1 b i t s y m b o l d p e 3 1 ke y 312 ke y 311 ke y 310 ke y 31en (0xff ff_ f37f ) r e a d / w r i t e r / w r r / w a f t e r r e s e t 0 0 1 0 0 0 f u n c t i o n p u l l - u p 0:static 1:d y n a m ic define the ke y 3 1 active state 000: "l" level 001: "h" level 010: falling edge 011: rising edge 100: both edges this can be read as "0." ke y 31 interrupt input 0: disable 1: enable tmp19a43(rev2.0)20-14 key-on w a k eup circuit
tmp19a43 20.5 detection of key inp u t inte rrupt s and clearance of request s wh en keyn en is set to 1 an d an activ e si g n a l is inpu t to keyn , t h e keyintn ch an n e l th at co rresp ond s to kwupintn is set to "1 ," i n dicatin g th at an in terrup t is ge nerate d. the k w up in tn is the rea d -o nly register . reading this re gister clears the corre spo n d i ng b it th at has been set t o "1 " an d th e i n terrupt requ est. (a clear by kwupclr is al so possible. if th e activ e st ate is set to th e h i gh o r low l e v e l, th e co rresp ond ing b it of th e kwup in tn r e g i ster re m a in s "1 " after it is read, u n l ess th e ex tern al i n pu t is with drawn . 7 6 5 4 3 2 1 0 k w u p i n t 0 b i t s y m b o l ke y i n t 7 ke y i n t 6 k e y in t5 ke y i n t 4 k e y in t3 ke y i n t 2 ke y i n t 1 ke y i n t 0 (0xff ff_ f 3 8 8 ) r e a d / w r i t e r a f t e r r e s e t 0 0 0 0 0 0 0 0 f u n c t i o n :interru p t 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated 7 6 5 4 3 2 1 0 k w u p i n t 1 b i t s y m b o l ke y i n t 1 5 ke y i n t 14 ke y i n t 13 ke y i n t 12 ke y i n t 11 ke y i n t 1 0 ke y i n t 9 ke y i n t 8 (0xff ff_ f 3 8 9 ) r e a d / w r i t e r a f t e r r e s e t 0 0 0 0 0 0 0 0 f u n c t i o n :interru p t 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated 7 6 5 4 3 2 1 0 k w u p i n t 2 b i t s y m b o l ke y i n t 2 3 ke y i n t 22 ke y i n t 21 ke y i n t 20 ke y i n t 19 ke y i n t 1 8 ke y i n t 1 7 ke y i n t 16 (0xff ff_ f 3 8 a ) r e a d / w r i t e r a f t e r r e s e t 0 0 0 0 0 0 0 0 f u n c t i o n :interru p t 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated 7 6 5 4 3 2 1 0 k w u p i n t 3 b i t s y m b o l ke y i n t 3 1 ke y i n t 30 ke y i n t 29 ke y i n t 28 ke y i n t 27 ke y i n t 2 6 ke y i n t 2 5 ke y i n t 24 (0xff ff_ f 3 8 b ) r e a d / w r i t e r a f t e r r e s e t 0 0 0 0 0 0 0 0 f u n c t i o n :interru p t 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated :interru pt 0::not gener ated 1:gener ated 7 6 5 4 3 2 1 0 k w u p c l r b i t s y m b o l ke y c l r 3 k e y cl r 2 ke y c l r 1 ke y c l r 0 (0xff ff_ f 3 8 5 ) r e a d / w r i t e r w a f t e r r e s e t 0 function this can be read as "0." wr iting "1010" clears all the ke y f a ctors. this can be read as "0." tmp19a43(rev2.0)20-15 key-on w a k eup circuit
tmp19a43 21. rom cor r ection function th is ch ap ter describ e s th e r o m correctio n fu n c tion bu ilt in to th e tmp19 a 43 . 21.1 features using t h is func tion, ei ght piec es of one -word data or four pi eces of eight-word data ca n be re placed. ? ? ? ? if an add r ess (lo w er 5 o r 2 b i t s are "do n ? t care" b its) written t o th e ad dress reg i ster m a tc h e s an add r ess gene rat e d by t h e pc or dm ac , r o m dat a i s re pl ace d b y dat a ge nerat e d by t h e r o m co rrect i o n d a ta regi st er w h i c h i s est a bl i s he d i n a r a m a r ea assi gne d t o t h e ab ove ad d r ess regi st er . rom correction is au to m a tica lly au th orized b y writin g an ad dress t o each ad dress reg i ster . if r o m c o r r ec t i o n can n o t be execut e d usi n g ei g h t - wo r d dat a due t o a pr o g r am m odi fi cat i o n or fo r ot her reasons , it is possible to place a "jum p-to-ram" instru ct ion in a data register in a r a m a r ea and to correct rom data in that r a m area. 21.2 description of operations by setting in the address regi ster addre g n a physical ad dress (incl udi ng a projection area) of t h e r o m area t o be co rrect e d , r o m dat a ca n be repl ace d by dat a ge ne rat e d by a dat a regi st er i n a r a m area as si gne d t o addregn. th e r o m correctio n fu n c tion i s au to m a tica lly en ab led wh en an add r ess is set in addr egn, and it cann o t b e di s a bl ed. a f t e r a reset , t h e r o m co rrect i o n f u nct i on i s di sabl e d . t h e r ef ore , t o e x e c ut e r o m correction wit h the initializa tion afte r a reset is cleared, it is necessa ry to set an address in addr eg . as a n ad dress is set in addreg , t h e rom correctio n fu n c tion is en ab led for th is reg i ster . if th e cpu h a s th e bu s au tho r ity , rom d a ta is rep l aced wh en th e v a lu e g e n e rated by the pc m a tches that of the addre ss re gi ster . if the dmac has t h e bus a u thorit y , rom data is re placed when a source or destination a d dress ge nerat e d by the d m a c m a tch e s th e v a lu e o f th e add r ess r e g i ster . fo r ex am p l e, if an add r ess is set in addreg 0 an d addreg3, t h e r o m co rrectio n fu n c tion is en ab led fo r th is area; match d e tection is p e rform e d on t h ese registers , a n d data replacem ent is execu te d if there is a m a tc h. data re place ment is not e x e c uted for addreg1, a d d r eg 2, an d add reg4 th rou g h ad dreg 7. a ltho u g h th e b it <31:5 > ex ists in a d dress re gisters, m a tch d e tectio n is per f o r m e d o n a < 20 :5 > f o r reason s of ci r c u itry sim p lificatio n . in tern al pro cessing is th at d a ta replacem ent is execute d whe n the calc u lation of a logi cal product is com p leted by m u ltiplying the romcs sig n a l sho w i n g a rom area by th e resu lt of a m a tch d e tectio n op er atio n per f o r m e d b y r o m cor r ectio n cir c u itr y . if ei ght -w or d dat a i s r e pl ac ed, a n a d dres s f o r r o m c o rrect i o n ca n b e est a bl i s he d onl y on an ei ght -w or d bounda ry , and data is re placed in units of 32 bytes. if on ly part of 32-by t e data m u st be replace d wit h di f f e r ent data, the a d dre sses that do not need to be re placed m u st be overwritten with the sam e data as t h e one existing pri o r t o data re placem ent. addre g n re gisters a n d ram areas as signed to them are as follows: reg i s t e r a d d r e s s r a m are a nu mb e r o f w o rd s ad dre g 0 0xfff f_e 540 0xfff f_df 60 - 0xfff f_df 7c 8 ad dre g 1 0xfff f_e 544 0xfff f_df 80 - 0xfff f_df 9c 8 ad dre g 2 0xfff f_e 548 0xfff f_df a0 - 0xf fff _dfbc 8 ad dre g 3 0xfff f_e 54c 0xfff f_dfc 0 - 0xf fff _dfdc 8 ad dre g 4 0xfff f_e 550 0xfff f _dfe 0 1 ad dre g 5 0xfff f_e 554 0xfff f _dfe 4 1 ad dre g 6 0xfff f_e 558 0xfff f _dfe 8 1 ad dre g 7 0xfff f_e 55c 0xfff f_dfe c 1 ad dre g 8 0xfff f_e 560 0xfff f_df f 0 1 ad dre g 9 0xfff f_e 564 0xfff f_df f 4 1 ad dre ga 0xfff f_e 568 0xfff f_df f 8 1 ad dre g b 0xfff f_e 56c 0xfff f_df f c 1 note: t o use the rom corre cti on func tion, the rom mu st be unpr otecte d. tmp19a43(rev2.0)21-1 rom corre ction funct i on
tmp19a43 address registe r addregn comparison circuit selector operand address instruction address rom selector operand data instruction data tx19a processo r bus interface circuit write detection & hold circuit of addregn authorize comparison ram conver- sion cir c uit internal bus fig. 21-1 ro m cor r e c tion sy stem diag r a m tmp19a43(rev2.0)21-2 rom corre ction funct i on
tmp19a43 21.3 registers (1) address regist ers 7 6 5 4 3 2 1 0 a d d r e g 0 b i t s y m b o l a d d 0 7 add06 a dd05 (0xff ff_e54 0 ) r e a d / w r i t e r / w r a f t e r r e s e t 0 0 0 1 1 1 1 1 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t s y m b o l a d d 0 1 5 add014 add013 add012 add011 a d d 0 1 0 a d d 0 9 add08 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t s y m b o l a d d 0 2 3 add022 add021 add020 add019 a d d 0 1 8 a d d 0 1 7 add016 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t s y m b o l a d d 0 3 1 add030 add029 add028 add027 a d d 0 2 6 a d d 0 2 5 add024 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 a d d r e g 1 b i t s y m b o l a d d 1 7 add16 a dd15 (0xff ff_e54 4 ) r e a d / w r i t e r / w r a f t e r r e s e t 0 0 0 1 1 1 1 1 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t s y m b o l a d d 1 1 5 add114 add113 add112 add111 a d d 1 1 0 a d d 1 9 add18 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t s y m b o l a d d 1 2 3 add122 add121 add120 add119 a d d 1 1 8 a d d 1 1 7 add116 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t s y m b o l a d d 1 3 1 add130 add129 add128 add127 a d d 1 2 6 a d d 1 2 5 add124 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 a d d r e g 2 b i t s y m b o l a d d 2 7 add26 a dd25 (0xff ff_e54 8 ) r e a d / w r i t e r / w r a f t e r r e s e t 0 0 0 1 1 1 1 1 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t s y m b o l a d d 2 1 5 add214 add213 add212 add211 a d d 2 1 0 a d d 2 9 add28 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t s y m b o l a d d 2 2 3 add222 add221 add220 add219 a d d 2 1 8 a d d 2 1 7 add216 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t s y m b o l a d d 2 3 1 add230 add229 add228 add227 a d d 2 2 6 a d d 2 2 5 add224 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 tmp19a43(rev2.0)21-3 rom corre ction funct i on
tmp19a43 7 6 5 4 3 2 1 0 a d d r e g 3 b i t s y m b o l a d d 3 7 add36 a dd35 (0xff ff_e54 c ) r e a d / w r i t e r / w r a f t e r r e s e t 0 0 0 1 1 1 1 1 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t s y m b o l a d d 3 1 5 add314 add313 add312 add311 a d d 3 1 0 a d d 3 9 add38 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t s y m b o l a d d 3 2 3 add322 add321 add320 add319 a d d 3 1 8 a d d 3 1 7 add316 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t s y m b o l a d d 3 3 1 add330 add329 add328 add327 a d d 3 2 6 a d d 3 2 5 add324 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 a d d r e g 4 b i t s y m b o l a d d 4 7 add46 a dd45 a dd44 a dd43 a d d 4 2 (0xff ff_e55 0 ) r e a d / w r i t e r / w r a f t e r r e s e t 0 0 0 0 0 0 1 1 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t s y m b o l a d d 4 1 5 add414 add413 add412 add411 a d d 4 1 0 a d d 4 9 add48 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t s y m b o l a d d 4 2 3 add422 add421 add420 add419 a d d 4 1 8 a d d 4 1 7 a d d 4 1 6 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t s y m b o l a d d 4 3 1 add430 add429 add428 add427 a d d 4 2 6 a d d 4 2 5 a d d 4 2 4 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 a d d r e g 5 b i t s y m b o l a d d 5 7 add56 a dd55 a dd54 a dd53 a d d 5 2 (0xff ff_e55 4 ) r e a d / w r i t e r / w r a f t e r r e s e t 0 0 0 0 0 0 1 1 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t s y m b o l a d d 5 1 5 add514 add513 add512 add511 a d d 5 1 0 a d d 5 9 add58 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t s y m b o l a d d 5 2 3 add522 add521 add520 add519 a d d 5 1 8 a d d 5 1 7 add516 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t s y m b o l a d d 5 3 1 add530 add529 add528 add527 a d d 5 2 6 a d d 5 2 5 add524 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 tmp19a43(rev2.0)21-4 rom corre ction funct i on
tmp19a43 7 6 5 4 3 2 1 0 a d d r e g 6 b i t s y m b o l a d d 6 7 add66 a dd65 a dd64 a dd63 a d d 6 2 (0xff ff_e55 8 ) r e a d / w r i t e r / w r a f t e r r e s e t 0 0 0 0 0 0 1 1 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t s y m b o l a d d 6 1 5 add614 add613 add612 add611 a d d 6 1 0 a d d 6 9 add68 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t s y m b o l a d d 6 2 3 add622 add621 add620 add619 a d d 6 1 8 a d d 6 1 7 a d d 6 1 6 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t s y m b o l a d d 6 3 1 add630 add629 add628 add627 a d d 6 2 6 a d d 6 2 5 a d d 6 2 4 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 a d d r e g 7 b i t s y m b o l a d d 7 7 add76 a dd75 a dd74 a dd73 a d d 7 2 (0xff ff_e55 c ) r e a d / w r i t e r / w r a f t e r r e s e t 0 0 0 0 0 0 1 1 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t s y m b o l a d d 7 1 5 add714 add713 add712 add711 a d d 7 1 0 a d d 7 9 add78 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t s y m b o l a d d 7 2 3 add722 add721 add720 add719 a d d 7 1 8 a d d 7 1 7 add716 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t s y m b o l a d d 7 3 1 add730 add729 add728 add727 a d d 7 2 6 a d d 7 2 5 add724 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 a d d r e g 8 b i t s y m b o l a d d 8 7 add86 a dd85 a dd84 a dd83 a d d 8 2 (0xff ff_e56 0 ) r e a d / w r i t e r / w r a f t e r r e s e t 0 0 0 0 0 0 1 1 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t s y m b o l a d d 8 1 5 add814 add813 add812 add811 a d d 8 1 0 a d d 8 9 add88 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t s y m b o l a d d 8 2 3 add822 add821 add820 add819 a d d 8 1 8 a d d 8 1 7 add816 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t s y m b o l a d d 8 3 1 add830 add829 add828 add827 a d d 8 2 6 a d d 8 2 5 add824 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 tmp19a43(rev2.0)21-5 rom corre ction funct i on
tmp19a43 7 6 5 4 3 2 1 0 a d d r e g 9 b i t s y m b o l a d d 9 7 add96 a dd95 a dd94 a dd93 a d d 9 2 (0xff ff_e56 4 ) r e a d / w r i t e r / w r a f t e r r e s e t 0 0 0 0 0 0 1 1 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t s y m b o l a d d 9 1 5 add914 add913 add912 add911 a d d 9 1 0 a d d 9 9 add98 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t s y m b o l a d d 9 2 3 add922 add921 add920 add919 a d d 9 1 8 a d d 9 1 7 add916 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t s y m b o l a d d 9 3 1 add930 add929 add928 add927 a d d 9 2 6 a d d 9 2 5 add924 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 a d d r e g a b i t s y m b o l a d d a 7 adda6 a dda5 a dda4 a dda3 a d d a 2 (0xff ff_e56 8 ) r e a d / w r i t e r / w r a f t e r r e s e t 0 0 0 0 0 0 1 1 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t s y m b o l a d d a 1 5 adda14 adda13 adda12 adda11 a d d a 1 0 a d d a 9 adda8 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t s y m b o l a d d a 2 3 adda22 adda21 adda20 adda19 a d d a 1 8 a d d a 1 7 a d d a 1 6 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t s y m b o l a d d a 3 1 adda30 adda29 adda28 adda27 a d d a 2 6 a d d a 2 5 a d d a 2 4 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 a d d r e g b b i t s y m b o l a d d b 7 addb6 a ddb5 a ddb4 a ddb3 a d d b 2 (0xff ff_e56 c ) r e a d / w r i t e r / w r a f t e r r e s e t 0 0 0 0 0 0 1 1 1 5 1 4 1 3 1 2 1 1 1 0 9 8 b i t s y m b o l a d d b 1 5 addb14 addb13 addb12 addb11 a d d b 1 0 a d d b 9 addb8 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 b i t s y m b o l a d d b 2 3 addb22 addb21 addb20 addb19 a d d b 1 8 a d d b 1 7 addb16 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 b i t s y m b o l a d d b 3 1 addb30 addb29 addb28 addb27 a d d b 2 6 a d d b 2 5 addb24 r e a d / w r i t e r / w a f t e r r e s e t 0 0 0 0 0 0 0 0 (no t e 1 ) dat a c a nno t be tran sfe rre d b y dma to the add r ess registe r . ho w e v e r , dat a can be trans f er red b y dma to th e ram a r ea w h e r e d a t a for replacem ent is placed . the rom correc t ion fu nction su pp ort s dat a r e p l acement for both cp u a nd dm a acc ess. (no t e 2 ) w r iting ba ck the initial v a lue "0x00" al lo w s d a t a a t the res e t ad dress to be r e placed. tmp19a43(rev2.0)21-6 rom corre ction funct i on
tmp19a43 22. t a ble of s p ecial function registers special function registers are a llocated to an 8k-byte a d dres s space from ffffe 000h to ffff ffff h. [1] port re gisters [ 2 ] w a tchdo g tim e r [3 ] 1 6 -b it ti m e r [4] i 2 cbus/serial channel [5] uar t/se rial channel [6 ] 1 0 -b it a/d conv erter [7] 8- bit d/ a c o n v e rter [8] key - on wa ke- up [9 ] 3 2 -b it in pu t cap t ure [1 0] 32 - b i t com p are [1 1] int e r r upt c o nt r o l l e r [1 2] dm a co nt r o l l e r [13 ] ch ip select/wait co n t ro ller [1 4] flas h c o ntr o l [1 5] rom co rrectio n [1 6] c l ock t i m er [1 7] uar t/ hi g h -s p eed se rial cha n nel [1 8] c l ock ge nerat o r (no t e) 0 x ffff_f000 to 0x ffff _ ffff are a little-en d i an area. 0x fff f_e 0 00 t o 0 x f fff _ef ff ar e a bi -e nd i a n area . (note) for continuous 8-b it long re gisters, 16- or 32-bit access is possible. the us e of 16- or 32-bit access requires that a n e v e n -num ber a d dress be a ccessed and that a n e v e n -num ber a d dress does not contain undefi n ed areas . tmp19a43(rev2.0)22-1 t a ble of s p e c ial funct io n registers
tmp19a43 big-endian [1] p o r t re gisters a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff0 0 0 h p 0 fff ff0 1 0 h fff ff0 20h p 4 c r fff ff0 3 0 h p 6 o d e 1 h p 1 1 h 1h p 4 f c 1 h p 9 o d e 2 h p 0 c r 2 h p 2 2h 2 h 3 h 3 h 3h 3 h 4 h p 1 c r 4 h p 2 c r 4h 4 h p b o d e 5 h p 1 f c 5 h p 2 f c 5h p 4 p e 5 h p c o d e 6 h 6 h p 2 f c 2 6h p 5 p e 6 h p d o d e 7 h 7 h 7h p 6 p e 7 h 8 h 8 h p 3 8h p 5 8 h 9 h 9 h 9h p 6 9 h a h a h p 3 c r ah a h b h b h p 3 f c bh b h c h p 0 p e c h p 2 p e ch p 5 c r c h p 5 f c 2 d h p 1 p e d h p 3 p e dh p 5 f c d h p 6 f c 2 e h e h p 4 eh p 6 c r e h r e s e r v e d f h f h fh p 6 f c f h r e s e rv e d a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff0 4 0 h p 7 fff ff0 5 0 h p b fff ff0 60h p f fff ff0 7 0 h 1 h p 8 1 h p c 1h p g 1 h 2 h p 9 2 h p d 2h p h 2 h 3 h p a 3 h p e 3h 3 h 4h ? 4 h p b c r 4h p f c r 4 h 5h ? 5 h p c c r 5h p g c r 5 h 6 h p 9 c r 6 h p d c r 6h p h c r 6 h 7 h p a c r 7 h p e c r 7h 7 h 8 h p 7 f c 8 h p b f c 8h p f f c 8 h 9 h p 8 f c 9 h p c f c 9h p g f c 9 h a h p 9 f c a h p d f c ah ? a h b h p a f c b h p e f c bh ? b h c h p 7 p e c h p b p e ch p f p e c h d h p 8 p e d h p c p e dh pg p e d h e h p 9 p e e h p d p e eh p h p e e h fh pape fh pepe fh fh a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff0 c 0 h fff ff0 d 0 h fff ff0e0 h fff ff0 f 0 h 1 h 1 h 1h 1 h 2 h 2 h 2h 2 h 3 h 3 h 3h 3 h 4 h 4 h 4h 4 h 5 h 5 h 5h 5 h 6 h 6 h 6h 6 h 7 h 7 h 7h 7 h 8h 8 h 8h 8 h 9h 9 h 9h 9 h ah a h ah a h b h b h bh b h c h c h ch c h d h d h dh d h e h e h eh e h f h f h fh f h tmp19a43(rev2.0)22-2 t a ble of s p e c ial funct io n registers
tmp19a43 big-endian [2] wd t a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff0 8 0 h fff ff0 9 0 h w d m o d fff ff0a0 h fff ff0b0 h 1 h 1 h w d c r 1h 1 h 2 h 2 h 2h 2 h 3 h 3 h 3h 3 h 4 h 4 h 4h 4 h 5 h 5 h 5h 5 h 6 h 6 h 6h 6 h 7 h 7 h 7h 7 h 8 h 8 h 8h 8 h 9 h 9 h 9h 9 h a h a h ah a h b h b h bh b h c h c h ch c h d h d h dh d h e h e h eh e h f h f h fh f h [3 ] 1 6 -b it ti m e r a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff1 40h tb0run fff ff1 50h tb1run fff ff1 60h tb2run fff ff1 7 0 h t b 3 r u n 1 h t b 0 c r 1 h t b 1 c r 1h tb2cr 1 h t b 3 c r 2 h t b 0 m o d 2 h t b 1 m o d 2h tb2mod 2 h t b 3 m o d 3 h t b 0 f f c r 3 h tb1ff c r 3h tb2ff cr 3 h t b 3 f f c r 4 h t b 0 s t 4 h t b 1 s t 4h tb2st 4 h t b 3 s t 5 h 5 h 5h 5 h 6 h t b 0 u c l 6 h t b 1 u c l 6h tb2ucl 6 h t b 3 u c l 7 h t b 0 u c h 7 h t b 1 u c h 7h tb2uch 7 h t b 3 u c h 8 h t b 0 r g 0 l 8 h tb1r g 0 l 8h tb2r g0l 8 h t b 3 r g 0 l 9 h t b 0 r g 0 h 9 h tb1r g 0 h 9h tb2r g0h 9 h t b 3 r g 0 h a h t b 0 r g 1 l a h tb1r g 1 l ah tb2r g1l a h t b 3 r g 1 l b h t b 0 r g 1 h b h tb1rg 1 h bh tb2rg 1 h b h t b 3 r g 1 h c h t b 0 c p 0 l c h t b 1 c p 0 l ch tb2cp0l c h t b 3 c p 0 l d h t b 0 c p 0 h d h t b 1 c p 0 h dh tb2cp0h d h t b 3 c p 0 h e h t b 0 c p 1 l e h t b 1 c p 1 l eh tb2cp1l e h t b 3 c p 1 l f h t b 0 c p 1 h f h t b 1 c p 1 h fh tb2cp1h f h t b 3 c p 1 h a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff1 8 0 h t b 4 r u n fff ff1 9 0 h t b 5 r u n fff ff1a0 h t b 6 r u n fff ff1b0 h t b 7 r u n 1 h t b 4 c r 1 h t b 5 c r 1h t b 6 c r 1 h t b 7 c r 2 h t b 4 m o d 2 h t b 5 m o d 2h t b 6 m o d 2 h t b 7 m o d 3 h t b 4 f f c r 3 h t b 5 f f c r 3h tb6ff c r 3 h t b 7 f f c r 4 h t b 4 s t 4 h t b 5 s t 4h t b 6 s t 4 h t b 7 s t 5 h 5 h 5h 5 h 6 h t b 4 u c l 6 h t b 5 u c l 6h t b 6 u c l 6 h t b 7 u c l 7 h t b 4 u c h 7 h t b 5 u c h 7h t b 6 u c h 7 h t b 7 u c h 8 h t b 4 r g 0 l 8 h t b 5 r g 0 l 8h tb6r g 0 l 8 h t b 7 r g 0 l 9 h t b 4 r g 0 h 9 h t b 5 r g 0 h 9h tb6r g 0 h 9 h t b 7 r g 0 h a h t b 4 r g 1 l a h t b 5 r g 1 l ah tb6r g 1 l a h t b 7 r g 1 l b h t b 4 r g 1 h b h t b 5r g 1 h bh tb6r g 1 h b h t b 7 r g 1 h c h t b 4 c p 0 l c h t b 5 c p 0 l ch t b 6 c p 0 l c h t b 7 c p 0 l d h t b 4 c p 0 h d h t b 5 c p 0 h dh t b 6 c p 0 h d h t b 7 c p 0 h e h t b 4 c p 1 l e h t b 5 c p 1 l eh t b 6 c p 1 l e h t b 7 c p 1 l f h t b 4 c p 1 h f h t b 5 c p 1 h fh t b 6 c p 1 h f h t b 7 c p 1 h tmp19a43(rev2.0)22-3 t a ble of s p e c ial funct io n registers
tmp19a43 big-endian a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff1 c 0 h t b 8 r u n fff ff1 d 0 h t b 9 r u n fff ff1e0 h t b a r u n fff ff1 f 0 h t b b r u n 1 h t b 8 c r 1 h t b 9 c r 1h t b a c r 1 h t b b c r 2 h t b 8 m o d 2 h t b 9 m o d 2h t b a m o d 2 h t b b m o d 3 h t b 8 f f c r 3 h tb9ff c r 3h tbaffc r 3 h t b b f f c r 4 h t b 8 s t 4 h t b 9 s t 4h t b a s t 4 h t b b s t 5 h 5 h 5h 5 h 6 h t b 8 u c l 6 h t b 9 u c l 6h t b a u c l 6 h t b b u c l 7 h t b 8 u c h 7 h t b 9 u c h 7h t b a u c h 7 h t b b u c h 8 h t b 8 r g 0 l 8 h tb9r g 0 l 8h tbarg0 l 8 h t b b r g 0 l 9 h t b 8 r g 0 h 9 h tb9r g 0 h 9h tbarg0 h 9 h t b b r g 0 h a h t b 8 r g 1 l a h tb9r g 1 l ah tbarg1 l a h t b b r g 1 l b h t b 8 r g 1 h b h tb9rg 1 h bh tbarg 1 h b h t b b r g 1 h c h t b 8 c p 0 l c h t b 9 c p 0 l ch t b a c p 0 l c h t b b c p 0 l d h t b 8 c p 0 h d h t b 9 c p 0 h dh t b a c p 0 h d h t b b c p 0 h e h t b 8 c p 1 l e h t b 9 c p 1 l eh t b a c p 1 l e h t b b c p 1 l f h t b 8 c p 1 h f h t b 9 c p 1 h fh t b a c p 1 h f h t b b c p 1 h a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff2 0 0 h t b c r u n fff ff2 1 0 h tbdru n fff ff2 20h t b e r u n fff ff2 3 0 h t b f r u n 1 h t b c c r 1 h t b d c r 1h t b e c r 1 h t b f c r 2 h t b c m o d 2 h t b d m o d 2h t b e m o d 2 h t b f m o d 3 h t b c f f c r 3 h tbdf f c r 3h tbeffc r 3 h t b f f f c r 4 h t b c s t 4 h t b d s t 4h t b e s t 4 h t b f s t 5 h 5 h 5h 5 h 6 h t b c u c l 6 h t b d u c l 6h t b e u c l 6 h t b f u c l 7 h t b c u c h 7 h tbduc h 7h t b e u c h 7 h t b f u c h 8 h t b c r g 0 l 8 h tbdr g 0 l 8h tberg0 l 8 h t b f r g 0 l 9 h t b c r g 0 h 9 h tbdr g 0 h 9h tberg0 h 9 h t b f r g 0 h a h t b c r g 1 l a h tbdrg 1 l ah tberg 1 l a h t b f r g 1 l b h t b c r g 1 h b h tbdr g 1 h bh tberg1 h b h t b f r g 1 h c h t b c c p 0 l c h t b d c p 0 l ch t b e c p 0 l c h t b f c p 0 l d h t b c c p 0 h d h t b d c p 0 h dh t b e c p 0 h d h t b f c p 0 h e h t b c c p 1 l e h t b d c p 1 l eh t b e c p 1 l e h t b f c p 1 l f h t b c c p 1 h f h t b d c p 1 h fh t b e c p 1 h f h t b f c p 1 h tmp19a43(rev2.0)22-4 t a ble of s p e c ial funct io n registers
tmp19a43 big-endian [4] i2c/s i o [5] uar t/s i o a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff2 5 0 h s b i c r 1 fff ff2 6 0 h s c 0 b u f fff ff2 70h s c 1 b u f fff ff2 8 0 h s c 2 b u f 1 h s b i d b r 1 h s c 0 c r 1h s c 1 c r 1 h s c 2 c r 2 h i 2 c a r 2 h sc0mod 0 2h sc1mod 0 2 h s c 2 m o d 0 3 h s b i c r 2 / s r 3 h b r 0 c r 3h b r 1 c r 3 h b r 2 c r 4 h s b i b r 0 4 h b r 0 a d d 4h b r 1 a d d 4 h b r 2 a d d 5 h 5 h sc0mod 1 5h sc1mod 1 5 h s c 2 m o d 1 6 h 6 h sc0mod 2 6h sc1mod 2 6 h s c 2 m o d 2 7 h s b i c r 0 7 h s c 0 e n 7h s c 1 e n 7 h s c 2 e n 8 h 8 h s c 0 r f c 8h s c 1 r f c 8 h s c 2 r f c 9 h 9 h sc0tf c 9h sc1tf c 9 h s c 2 t f c a h a h s c 0 r s t ah s c 1 r s t a h s c 2 r s t b h b h s c 0 t s t bh s c 1 t s t b h s c 2 t s t c h c h sc0fcn f ch sc1fcn f c h s c 2 f c n f d h d h dh d h e h e h eh e h f h f h fh f h a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff2 9 0 h fff ff2a0 h fff ff2b0 h fff ff2 c 0 h 1 h 1 h 1h 1 h 2 h 2 h 2h 2 h 3 h 3 h 3h 3 h 4 h 4 h 4h 4 h 5 h 5 h 5h 5 h 6 h 6 h 6h 6 h 7 h 7 h 7h 7 h 8 h 8 h 8h 8 h 9 h 9 h 9h 9 h a h a h ah a h b h b h bh b h c h c h ch c h d h d h dh d h e h e h eh e h f h f h fh f h [ 6 ] 1 0 -b it ad c [ 7 ] 8 - b it da c a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a d r reg i ster na me fff ff3 0 0 h a d r e g 0 8 l fff ff3 1 0 h adregspl fff ff3 30h daccn t 0 fff ff3 4 0 h 1 h a d r e g 0 8 h 1 h adregsph 1h d a r e g 0 1 h 2 h a d r e g 1 9 l 2 h a dcomre g l 2 h 2 h 3 h a d r e g 1 9 h 3 h a dcomre g h 3 h 3 h 4 h a d r e g 2 a l 4 h a d m o d 0 4h 4 h 5 h a d r e g 2 a h 5 h a d m o d 1 5h 5 h 6 h a d r e g 3 b l 6 h a d m o d 2 6h 6 h 7 h a d r e g 3 b h 7 h a d m o d 3 7h r e s e r v e d 7 h 8 h a d r e g 4 c l 8 h a d m o d 4 8h daccn t 1 8 h 9 h a d r e g 4 c h 9 h a d c b a s 9h dareg 1 9 h a h a d r e g 5 d l a h reserved a h a h b h a d r e g 5 d h b h reserved b h b h c h a d r e g 6 e l c h a d c l k ch c h d h a d r e g 6 e h d h dh d h e h a d r e g 7 f l e h eh e h f h a d r e g 7 f h f h fh res e rv e d f h tmp19a43(rev2.0)22-5 t a ble of s p e c ial funct io n registers
tmp19a43 big-endian [8] k w up a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a d r reg i ster na me fff ff3 6 0 h k w u p s t 0 0 fff ff3 7 0 h kw upst16 fff ff3 80h pke y 0 fff ff3 9 0 h 1 h k w u p s t 0 1 1 h kwupst17 1h pke y 1 1 h 2 h k w u p s t 0 2 2 h kwupst18 2h pke y 2 2 h 3 h k w u p s t 0 3 3 h kwupst19 3h pke y 3 3 h 4 h k w u p s t 0 4 4 h kwupst20 4h k w u p c n t 4 h 5 h k w u p s t 0 5 5 h kwupst21 5h k w u p c l r 5 h 6 h k w u p s t 0 6 6 h kwupst22 6h 6 h 7 h k w u p s t 0 7 7 h kwupst23 7h 7 h 8 h k w u p s t 0 8 8 h kwupst24 8h k w u p i n t 0 8 h 9 h k w u p s t 0 9 9 h kwupst25 9h k w u p i n t 1 9 h a h k w u p s t 1 0 a h kwupst26 ah k w u p i n t 2 a h b h k w u p s t 1 1 b h kwupst27 bh k w u p i n t 3 b h c h k w u p s t 1 2 c h kwupst28 ch c h d h k w u p s t 1 3 d h kwupst29 dh d h e h k w u p s t 1 4 e h kwupst30 eh e h f h k w u p s t 1 5 f h kwupst31 fh f h [9 ] 3 2 -b it in pu t cap ture a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff 4 00h tccr fff ff4 10h cap0cr fff ff4 20h cap2cr fff ff4 3 0 h 1 h t b t r u n 1 h 1h 1 h 2 h t b t c r 2 h 2h 2 h 3 h 3 h 3h 3 h 4 h t b t c a p 0 4 h tccap0ll 4h tccap2ll 4 h 5 h t b t c a p 1 5 h tccap0lh 5h tccap2lh 5 h 6 h t b t c a p 2 6 h tccap0hl 6h tccap2hl 6 h 7 h t b t c a p 3 7 h tccap0hh 7h tccap2hh 7 h 8h tbtrdcapll 8 h c a p 1 c r 8h cap3cr 8 h 9h tbtrdcaplh 9 h 9h 9 h ah tbtrdcaphl a h ah a h bh tbtrdcaphh b h bh b h c h t c g 0 i m c h tccap1ll ch tccap3ll c h d h t c g 0 s t d h tccap1lh dh tccap3lh d h e h r e s e r v e d e h tccap1hl eh tccap3hl e h f h r e s e rv e d f h tccap1h h fh tccap3h h f h [1 0] 3 2 - bi t out put c o m p are a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff 4 40h tccmp0ll fff ff4 50h tccmp4ll fff ff4 60h fff ff4 7 0 h c m p c t l 0 1 h t c c m p 0 l h 1 h tccmp4l h 1h 1 h c m p c t l 1 2 h t c c m p 0 h l 2 h tccmp4h l 2h 2 h c m p c t l 2 3 h t c c m p 0 h h 3 h tccmp4h h 3h 3 h c m p c t l 3 4 h t c c m p 1 l l 4 h t c c m p 5 l l 4h 4 h c m p c t l 4 5 h t c c m p 1 l h 5 h tccmp5l h 5h 5 h c m p c t l 5 6 h t c c m p 1 h l 6 h tccmp5h l 6h 6 h c m p c t l 6 7 h t c c m p 1 h h 7 h tccmp5h h 7h 7 h c m p c t l 7 8 h t c c m p 2 l l 8 h t c c m p 6 l l 8h 8 h 9 h t c c m p 2 l h 9 h tccmp6l h 9h 9 h a h t c c m p 2 h l a h tccmp6hl ah a h b h t c c m p 2 h h b h tccmp6hh bh b h c h t c c m p 3 l l c h t c c m p 7 l l ch ch d h t c c m p 3 l h d h tccmp7l h dh dh e h t c c m p 3 h l e h tccmp7hl eh e h f h t c c m p 3 h h f h tccmp7h h fh f h tmp19a43(rev2.0)22-6 t a ble of s p e c ial funct io n registers
tmp19a43 big-endian [1 1] i n tc a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a d r reg i ster na me fff f e 0 0 0 h i m c 0 fff f e 0 1 0 h i m c 4 fff fe020h i m c 8 fff f e 0 3 0 h i m c c 1 h d i t t o 1 h d i t t o 1h d i t t o 1 h d i t t o 2 h d i t t o 2 h d i t t o 2h d i t t o 2 h d i t t o 3 h d i t t o 3 h d i t t o 3h d i t t o 3 h d i t t o 4 h i m c 1 4 h i m c 5 4h i m c 9 4 h i m c d 5 h d i t t o 5 h d i t t o 5h d i t t o 5 h d i t t o 6 h d i t t o 6 h d i t t o 6h d i t t o 6 h d i t t o 7 h d i t t o 7 h d i t t o 7h d i t t o 7 h d i t t o 8 h i m c 2 8 h i m c 6 8 h i m c a 8 h i m c e 9 h d i t t o 9 h d i t t o 9h d i t t o 9 h d i t t o a h d i t t o a h d i t t o ah d i t t o a h d i t t o b h d i t t o b h d i t t o bh d i t t o b h d i t t o c h i m c 3 c h i m c 7 c h i m c b c h i m c f d h d i t t o d h d i t t o dh d i t t o d h d i t t o e h d i t t o e h d i t t o eh d i t t o e h d i t t o f h d i t t o f h d i t t o fh d i t t o f h d i t t o a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a d r reg i ster na me fff f e 0 4 0 h i v r fff f e 0 5 0 h f f f fe060h i n t c l r f f f f e 0 7 0 h 1 h d i t t o 1 h 1 h d i t t o 1 h 2 h d i t t o 2 h 2 h d i t t o 2 h 3 h d i t t o 3 h 3 h d i t t o 3 h 4 h 4 h 4h 4 h 5 h 5 h 5h 5 h 6 h 6 h 6h 6 h 7 h 7 h 7h 7 h 8 h 8 h 8h 8 h 9 h 9 h 9h 9 h a h a h ah a h b h b h bh b h c h c h ch c h d h d h dh d h e h e h eh e h f h f h fh f h a dr reg i ster na me fff fe100h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh c h i l e v d h d i t t o e h d i t t o f h d i t t o tmp19a43(rev2.0)22-7 t a ble of s p e c ial funct io n registers
tmp19a43 big-endian [1 2] dm ac a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a d r reg i ster na me fff f e 2 0 0 h c c r 0 fff f e 2 1 0 h b c r 0 f f f fe220h c c r 1 f f f f e 2 3 0 h b c r 1 1 h d i t t o 1 h d i t t o 1h d i t t o 1 h d i t t o 2 h d i t t o 2 h d i t t o 2h d i t t o 2 h d i t t o 3 h d i t t o 3 h d i t t o 3h d i t t o 3 h d i t t o 4 h c s r 0 4 h 4 h c s r 1 4 h 5 h d i t t o 5 h 5 h d i t t o 5 h 6 h d i t t o 6 h 6 h d i t t o 6 h 7 h d i t t o 7 h 7 h d i t t o 7 h 8 h s a r 0 8 h d t c r 0 8 h s a r 1 8 h d t c r 1 9 h d i t t o 9 h d i t t o 9h d i t t o 9 h d i t t o a h d i t t o a h d i t t o ah d i t t o a h d i t t o b h d i t t o b h d i t t o bh d i t t o b h d i t t o c h d a r 0 c h c h d a r 1 c h d h d i t t o d h d h d i t t o d h e h d i t t o e h e h d i t t o e h f h d i t t o f h f h d i t t o f h a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a d r reg i ster na me fff f e 2 4 0 h c c r 2 fff f e 2 5 0 h b c r 2 f f f fe260h c c r 3 f f f f e 2 7 0 h b c r 3 1 h d i t t o 1 h d i t t o 1h d i t t o 1 h d i t t o 2 h d i t t o 2 h d i t t o 2h d i t t o 2 h d i t t o 3 h d i t t o 3 h d i t t o 3h d i t t o 3 h d i t t o 4 h c s r 2 4 h 4 h c s r 3 4 h 5 h d i t t o 5 h 5 h d i t t o 5 h 6 h d i t t o 6 h 6 h d i t t o 6 h 7 h d i t t o 7 h 7 h d i t t o 7 h 8 h s a r 2 8 h d t c r 2 8 h s a r 3 8 h d t c r 3 9 h d i t t o 9 h d i t t o 9h d i t t o 9 h d i t t o a h d i t t o a h d i t t o ah d i t t o a h d i t t o b h d i t t o b h d i t t o bh d i t t o b h d i t t o c h d a r 2 c h c h d a r 3 c h d h d i t t o d h d h d i t t o d h e h d i t t o e h e h d i t t o e h f h d i t t o f h f h d i t t o f h a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a d r reg i ster na me fff f e 2 8 0 h c c r 4 fff f e 2 9 0 h b c r 4 fff fe2a0h c c r 5 fff f e 2 b 0 h b c r 5 1 h d i t t o 1 h d i t t o 1h d i t t o 1 h d i t t o 2 h d i t t o 2 h d i t t o 2h d i t t o 2 h d i t t o 3 h d i t t o 3 h d i t t o 3h d i t t o 3 h d i t t o 4 h c s r 4 4 h 4 h c s r 5 4 h 5 h d i t t o 5 h 5 h d i t t o 5 h 6 h d i t t o 6 h 6 h d i t t o 6 h 7 h d i t t o 7 h 7 h d i t t o 7 h 8 h s a r 4 8 h d t c r 4 8 h s a r 5 8 h d t c r 5 9 h d i t t o 9 h d i t t o 9h d i t t o 9 h d i t t o a h d i t t o a h d i t t o ah d i t t o a h d i t t o b h d i t t o b h d i t t o bh d i t t o b h d i t t o c h d a r 4 c h c h d a r 5 c h d h d i t t o d h d h d i t t o d h e h d i t t o e h e h d i t t o e h f h d i t t o f h f h d i t t o f h tmp19a43(rev2.0)22-8 t a ble of s p e c ial funct io n registers
tmp19a43 big-endian a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a d r reg i ster na me fff fe2c0 h c c r 6 fff fe2d0 h b c r 6 f f f fe2e0h c c r 7 fff fe2f0 h b c r 7 1 h d i t t o 1 h d i t t o 1h d i t t o 1 h d i t t o 2 h d i t t o 2 h d i t t o 2h d i t t o 2 h d i t t o 3 h d i t t o 3 h d i t t o 3h d i t t o 3 h d i t t o 4 h c s r 6 4 h 4 h c s r 7 4 h 5 h d i t t o 5 h 5 h d i t t o 5 h 6 h d i t t o 6 h 6 h d i t t o 6 h 7 h d i t t o 7 h 7 h d i t t o 7 h 8 h s a r 6 8 h d t c r 6 8 h s a r 7 8 h d t c r 7 9 h d i t t o 9 h d i t t o 9h d i t t o 9 h d i t t o a h d i t t o a h d i t t o ah d i t t o a h d i t t o b h d i t t o b h d i t t o bh d i t t o b h d i t t o c h d a r 6 c h c h d a r 7 c h d h d i t t o d h d h d i t t o d h e h d i t t o e h e h d i t t o e h f h d i t t o f h f h d i t t o f h a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a d r reg i ster na me fff f e 3 0 0 h d c r fff f e 3 1 0 h fff fe320h fff f e 3 3 0 h 1 h d i t t o 1 h 1h 1 h 2 h d i t t o 2 h 2h 2 h 3 h d i t t o 3 h 3h 3 h 4 h r s r 4 h 4h 4 h 5 h d i t t o 5 h 5h 5 h 6 h d i t t o 6 h 6h 6 h 7 h d i t t o 7 h 7h 7 h 8 h 8 h 8h 8 h 9 h 9 h 9h 9 h a h a h ah a h b h b h bh b h c h d h r c h ch c h d h d i t t o d h dh d h e h d i t t o e h eh e h f h d i t t o f h fh f h a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a d r reg i ster na me fff f e 3 4 0 h fff f e 3 5 0 h fff fe360h fff f e 3 7 0 h 1 h 1 h 1h 1 h 2 h 2 h 2h 2 h 3 h 3 h 3h 3 h 4 h 4 h 4h 4 h 5 h 5 h 5h 5 h 6 h 6 h 6h 6 h 7 h 7 h 7h 7 h 8 h 8 h 8h 8 h 9 h 9 h 9h 9 h a h a h ah a h b h b h bh b h c h c h ch c h d h d h dh d h e h e h eh e h f h f h fh f h tmp19a43(rev2.0)22-9 t a ble of s p e c ial funct io n registers
tmp19a43 tmp19a43(rev2.0)22-10 t a ble of s p e c ial funct io n registers big-endian [1 3] c s / w a i t co nt r o l l e r a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a d r reg i ster na me fff f e 4 0 0 h b m a 0 fff f e 4 1 0 h f f f fe480h b 0 1 c s f f f f e 4 9 0 h 1 h d i t t o 1 h 1 h d i t t o 1 h 2 h d i t t o 2 h 2 h d i t t o 2 h 3 h d i t t o 3 h 3 h d i t t o 3 h 4 h b m a 1 4 h 4 h b 2 3 c s 4 h 5 h d i t t o 5 h 5 h d i t t o 5 h 6 h d i t t o 6 h 6 h d i t t o 6 h 7 h d i t t o 7 h 7 h d i t t o 7 h 8 h b m a 2 8 h 8h 8 h 9 h d i t t o 9 h 9h 9 h a h d i t t o a h ah a h b h d i t t o b h bh b h c h b m a 3 c h ch c h d h d i t t o d h dh d h e h d i t t o e h e h b e x c s e h f h d i t t o f h f h d i t t o f h [1 4] fl as h c ont rol a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me fff f e 5 1 0 h s e q m o d fff f e 5 2 0 h f l c s fff fe620h 1 h d i t t o 1 h d i t t o 1h 2 h d i t t o 2 h d i t t o 2h 3 h d i t t o 3 h d i t t o 3h 4 h s e q c n t 4 h r e s e r v e d 4h r e s e r v e d 5 h d i t t o 5 h r e s e r v e d 5h r e s e r v e d 6 h d i t t o 6 h r e s e r v e d 6h r e s e r v e d 7 h d i t t o 7 h r e s e r v e d 7h r e s e r v e d 8 h r o m s e c 1 8 h r e s e r v e d 8h 9 h d i t t o 9 h r e s e r v e d 9h a h d i t t o a h r e s e r v e d ah b h d i t t o b h r e s e r v e d bh c h r o m s e c 2 c h ch d h d i t t o d h dh e h d i t t o e h eh f h d i t t o f h fh [1 5] r o m c o rr ect i on a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a d r reg i ster na me fff f e 5 4 0 h a d d r e g 0 fff f e 5 5 0 h a d d r e g 4 fff fe560h a d d r e g 8 fff f e 5 7 0 h 1 h d i t t o 1 h d i t t o 1h d i t t o 1 h 2 h d i t t o 2 h d i t t o 2h d i t t o 2 h 3 h d i t t o 3 h d i t t o 3h d i t t o 3 h 4 h a d d r e g 1 4 h a d d r e g 5 4h a d d r e g 9 4 h 5 h d i t t o 5 h d i t t o 5h d i t t o 5 h 6 h d i t t o 6 h d i t t o 6h d i t t o 6 h 7 h d i t t o 7 h d i t t o 7h d i t t o 7 h 8 h a d d r e g 2 8 h a d d r e g 6 8h a d d r e g a 8 h 9 h d i t t o 9 h d i t t o 9h d i t t o 9 h a h d i t t o a h d i t t o ah d i t t o a h b h d i t t o b h d i t t o bh d i t t o b h c h a d d r e g 3 c h a d d r e g 7 ch a d d r e g b c h d h d i t t o d h d i t t o dh d i t t o d h e h d i t t o e h d i t t o eh d i t t o e h f h d i t t o f h d i t t o fh d i t t o f h attention
tmp19a43 big-endian [1 6] c l oc k t i m er a dr reg i ster na me a d r reg i ster na me fff f e 7 0 0 h fff f e 7 1 0 h 1 h 1 h 2 h 2 h 3 h 3 h 4 h r t c c r 4 h 5 h d i t t o 5 h 6 h d i t t o 6 h 7 h d i t t o 7 h 8 h r t c r e g 8 h 9 h d i t t o 9 h a h d i t t o a h b h d i t t o b h ch c h dh d h eh e h fh f h [1 7] u a r t /h s i o a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a dr reg i ster na me fff f e 8 0 0 h fff f e 8 1 0 h fff fe820h fff f e 8 4 0 h 1 h 1 h 1h 1 h 2 h 2 h 2h 2 h 3 h h s c 0 b u f 3 h h s c 1 b u f 3h h s c 2 b u f 3 h 4 h h s c 0 e n 4 h h s c 1 e n 4h h s c 2 e n 4 h 5 h h s c 0 m o d 2 5 h hsc1mod2 5h hsc2mod2 5 h 6 h h s c 0 m o d 1 6 h hsc1mod1 6h hsc2mod1 6 h 7 h h b r 0 a d d 7 h h b r 1 a d d 7h h b r 2 a d d 7 h 8 h h s c 0 t s t 8 h h s c 1 t s t 8h h s c 2 t s t 8 h 9 h h s c 0 r s t 9 h h s c 1 r s t 9h h s c 2 r s t 9 h a h h s c 0 t f c a h hsc1t f c ah hsc2t f c a h b h h s c 0 r f c b h hsc1rf c bh hsc2rf c b h c h h b r 0 c r c h h b r 1 c r ch h b r 2 c r c h d h h s c 0 m o d 0 d h hsc1mod0 dh hsc2mod0 d h e h h s c 0 c r e h h s c 1 c r eh h s c 2 c r e h f h h s c 0 f c n f f h hsc1fc nf fh hsc2fc nf f h [1 8] cg a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a dr reg i ster na me fff f e e 0 0 h s y scr 3 fff f e e 1 0 h i m c g a fff fee20h eicrc g fff f e e 4 0 h 1 h s y scr 2 1 h d i t t o 1h d i t t o 1 h 2 h s y scr 1 2 h d i t t o 2h d i t t o 2 h 3 h s y scr 0 3 h d i t t o 3h d i t t o 3 h 4 h 4 h i m c g b 4h nmifl g 4 h 5 h 5 h d i t t o 5h d i t t o 5 h 6 h 6 h d i t t o 6h d i t t o 6 h 7 h 7 h d i t t o 7h d i t t o 7 h 8 h 8 h i m c g c 8h 8 h 9 h 9 h d i t t o 9h 9 h a h a h d i t t o ah a h b h b h d i t t o bh b h c h c h i m c g d ch c h d h d h d i t t o dh d h e h e h d i t t o eh e h f h f h d i t t o fh f h tmp19a43(rev2.0)22-1 1 t a ble of s p e c ial funct io n registers
tmp19a43 little-endian [1 ] po r t r e g i ster s a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff0 0 0 h p 0 fff ff0 1 0 h fff ff0 20h p 4 c r fff ff0 3 0 h p 6 o d e 1 h p 1 1 h 1h p 4 f c 1 h p 9 o d e 2 h p 0 c r 2 h p 2 2h 2 h 3 h 3 h 3h 3 h 4 h p 1 c r 4 h p 2 c r 4h 4 h p b o d e 5 h p 1 f c 5 h p 2 f c 5h p 4 p e 5 h p c o d e 6 h 6 h p 2 f c 2 6h p 5 p e 6 h p d o d e 7 h 7 h 7h p 6 p e 7 h 8 h 8 h p 3 8h p 5 8 h 9 h 9 h 9h p 6 9 h a h a h p 3 c r ah a h b h b h p 3 f c bh b h c h p 0 p e c h p 2 p e ch p 5 c r c h p 5 f c 2 d h p 1 p e d h p 3 p e dh p 5 f c d h p 6 f c 2 e h e h p 4 eh p 6 c r e h r e s e r v e d f h f h fh p 6 f c f h r e s e rv e d a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff0 4 0 h p 7 fff ff0 5 0 h p b fff ff0 60h p f fff ff0 7 0 h 1 h p 8 1 h p c 1h p g 1 h 2 h p 9 2 h p d 2h p h 2 h 3 h p a 3 h p e 3h 3 h 4h ? 4 h p b c r 4h p f c r 4 h 5h ? 5 h p c c r 5h p g c r 5 h 6 h p 9 c r 6 h p d c r 6h p h c r 6 h 7 h p a c r 7 h p e c r 7h 7 h 8 h p 7 f c 8 h p b f c 8h p f f c 8 h 9 h p 8 f c 9 h p c f c 9h p g f c 9 h a h p 9 f c a h p d f c ah ? a h b h p a f c b h p e f c bh ? b h c h p 7 p e c h p b p e ch p f p e c h d h p 8 p e d h p c p e dh pg p e d h e h p 9 p e e h p d p e eh p h p e e h fh pape fh pepe fh fh a dr reg i ster na me a d r reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff0 c 0 h fff ff0 d 0 h fff ff0e0 h fff ff0 f 0 h 1 h 1 h 1h 1 h 2 h 2 h 2h 2 h 3 h 3 h 3h 3 h 4 h 4 h 4h 4 h 5h 5h 5h 5h 6h 6h 6h 6h 7h 7h 7h 7h 8h 8h 8h 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch ch ch ch dh dh dh dh eh eh eh eh fh fh fh fh tmp19a43(rev2.0)22-12 t a ble of s p e c ial funct io n registers
tmp19a43 little-endian [2] wd t a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff0 80h fff ff0 90h w d mod fff ff0a0 h fff ff0b0 h 1h 1h wdcr 1h 1h 2h 2h 2h 2h 3h 3h 3h 3h 4h 4h 4h 4h 5h 5h 5h 5h 6h 6h 6h 6h 7h 7h 7h 7h 8h 8h 8h 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch ch ch ch dh dh dh dh eh eh eh eh fh fh fh fh [3 ] 1 6 -b it ti m e r a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff1 40h tb0run fff ff1 50h tb1run fff ff1 60h tb2run fff ff1 70h tb3run 1h tb0cr 1h tb1cr 1h tb2cr 1h tb3cr 2h tb0mod 2h tb1mod 2h tb2mod 2h tb3mod 3h tb0ff cr 3h tb1ff cr 3h tb2ff cr 3h tb3ff cr 4h tb0st 4h tb1st 4h tb2st 4h tb3st 5h 5h 5h 5h 6h tb0ucl 6h tb1ucl 6h tb2ucl 6h tb3ucl 7h tb0uch 7h tb1uch 7h tb2uch 7h tb3uch 8h tb0r g0l 8h tb1r g0l 8h tb2r g0l 8h tb3r g0l 9h tb0r g0h 9h tb1r g0h 9h tb2r g0h 9h tb3r g0h ah tb0r g1l ah tb1r g1l ah tb2r g1l ah tb3r g1l bh tb0rg 1 h bh tb1rg 1 h bh tb2rg 1 h bh tb3rg 1 h ch tb0cp0l ch tb1cp0l ch tb2cp0l ch tb3cp0l dh tb0cp0h dh tb1cp0h dh tb2cp0h dh tb3cp0h eh tb0cp1l eh tb1cp1l eh tb2cp1l eh tb3cp1l fh tb0cp1h fh tb1cp1h fh tb2cp1h fh tb3cp1h a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff1 80h tb4run fff ff1 90h tb5run fff ff1a0 h t b6run fff ff1b0 h tb7run 1h tb4cr 1h tb5cr 1h tb6cr 1h tb7cr 2h tb4mod 2h tb5mod 2h tb6mod 2h tb7mod 3h tb4ff cr 3h tb5ff cr 3h tb6ff cr 3h tb7ff cr 4h tb4st 4h tb5st 4h tb6st 4h tb7st 5h 5h 5h 5h 6h tb4ucl 6h tb5ucl 6h tb6ucl 6h tb7ucl 7h tb4uch 7h tb5uch 7h tb6uch 7h tb7uch 8h tb4r g0l 8h tb5r g0l 8h tb6r g0l 8h tb7r g0l 9h tb4r g0h 9h tb5r g0h 9h tb6r g0h 9h tb7r g0h ah tb4r g1l ah tb5r g1l ah tb6r g1l ah tb7r g1l bh tb4rg 1 h bh tb 5r g1h bh tb6r g1h bh tb7rg 1 h ch tb4cp0l ch tb5cp0l ch tb6cp0l ch tb7cp0l dh tb4cp0h dh tb5cp0h dh tb6cp0h dh tb7cp0h eh tb4cp1l eh tb5cp1l eh tb6cp1l eh tb7cp1l fh tb4cp1h fh tb5cp1h fh tb6cp1h fh tb7cp1h tmp19a43(rev2.0)22-13 t a ble of s p e c ial funct io n registers
tmp19a43 little-endian a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff1 c0h tb8run fff ff1 d0h tb9run fff ff1e0 h t barun fff ff1 f0h tbbrun 1h tb8cr 1h tb9cr 1h tbacr 1h tbbcr 2h tb8mod 2h tb9mod 2h tbamod 2h tbbmo d 3h tb8ff cr 3h tb9ff cr 3h tbaffc r 3h tbbffc r 4h tb8st 4h tb9st 4h tbast 4h tbbst 5h 5h 5h 5h 6h tb8ucl 6h tb9ucl 6h tbaucl 6h tbbucl 7h tb8uch 7h tb9uch 7h tbauch 7h tbbuch 8h tb8r g0l 8h tb9r g0l 8h tbarg0 l 8h tbbrg0 l 9h tb8r g0h 9h tb9r g0h 9h tbarg0 h 9h tbbrg 0 h ah tb8r g1l ah tb9r g1l ah tbarg1 l ah tbbrg 1 l bh tb8rg 1 h bh tb9rg 1 h bh tbarg 1 h bh tbbrg 1 h ch tb8cp0l ch tb9cp0l ch tbacp0l ch tbbcp0l dh tb8cp0h dh tb9cp0h dh tbacp0h dh tbbcp0h eh tb8cp1l eh tb9cp1l eh tbacp1l eh tbbcp1l fh tb8cp1h fh tb9cp1h fh tbacp1h fh tbbcp1h a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff2 00h tbcru n fff ff2 10h tbdru n fff ff2 20h tberun fff ff2 30h tbfru n 1h tbccr 1h tbdcr 1h tbecr 1h tbfcr 2h tbcmod 2h tbdmod 2h tbemod 2h tbfm od 3h tbcf fcr 3h tbdf fcr 3h tbeffc r 3h tbff fcr 4h tbcst 4h tbdst 4h tbest 4h tbfst 5h 5h 5h 5h 6h tbcucl 6h tbducl 6h tbeucl 6h tbfuc l 7h tbcuc h 7h tbduc h 7h tbeuch 7h tbfuc h 8h tbcr g0l 8h tbdr g0l 8h tberg0 l 8h tbfr g0l 9h tbcr g0h 9h tbdr g0h 9h tberg0 h 9h tbfr g0h ah tbcrg 1l ah tbdrg 1l ah tberg 1 l ah tbfr g1l bh tbcr g1h bh tbdr g1h bh tberg1 h bh tbfr g1h ch tbccp0l ch tbdcp0l ch tbecp0l ch tbfcp0l dh tbccp0h dh tbdcp0h dh tbecp0h dh tbfcp0h eh tbccp1l eh tbdcp1l eh tbecp1l eh tbfcp1l fh tbccp1h fh tbdcp1h fh tbecp1h fh tbfcp1h tmp19a43(rev2.0)22-14 t a ble of s p e c ial funct io n registers
tmp19a43 little-endian [4] i2c/s i o [5] uar t/s i o a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff2 50h sbicr1 fff ff2 60h sc0buf fff ff2 70h sc1buf fff ff2 80h sc2buf 1h sbidbr 1h sc0cr 1h sc1cr 1h sc2cr 2h i2car 2h sc0mod 0 2h sc1mod 0 2h sc2mod 0 3h sbicr2/sr 3h br0cr 3h br1cr 3h br2cr 4h sbibr0 4h br0add 4h br1add 4h br2add 5h 5h sc0mod 1 5h sc1mod 1 5h sc2mod 1 6h 6h sc0mod 2 6h sc1mod 2 6h sc2mod 2 7h sbicr0 7h sc0en 7h sc1en 7h sc2en 8h 8h sc0rfc 8h sc1rfc 8h sc2rfc 9h 9h sc0tf c 9h sc1tf c 9h sc2tf c ah ah sc0rst ah sc1rst ah sc2rst bh bh sc0tst bh sc1tst bh sc2tst ch ch sc0fcn f ch sc1fcn f ch sc2fcn f dh dh dh dh eh eh eh eh fh fh fh fh a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff2 90h fff ff2a0 h fff ff2b0 h fff ff2 c0h 1h 1h 1h 1h 2h 2h 2h 2h 3h 3h 3h 3h 4h 4h 4h 4h 5h 5h 5h 5h 6h 6h 6h 6h 7h 7h 7h 7h 8h 8h 8h 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch ch ch ch dh dh dh dh eh eh eh eh fh fh fh fh [ 6 ] 1 0 -b it ad c [ 7 ] 8 - b it ad c a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff3 00h adreg08 l fff ff3 10h adregspl fff ff3 30h daccn t0 fff ff3 40h 1h adreg08 h 1h adregsph 1h dareg0 1h 2h adreg19 l 2h adcomregl 2h 2h 3h adreg19 h 3h adcomregh 3h 3h 4h adreg2al 4h admod0 4h 4h 5h adreg2ah 5h admod1 5h 5h 6h adreg3bl 6h admod2 6h 6h 7h adreg3bh 7h admod3 7h reserved 7h 8h adreg4 cl 8h admod4 8h daccn t1 8h 9h adreg 4 ch 9h adcbas 9h dareg 1 9h ah adreg 5 dl ah reserved ah ah bh adreg 5 dh bh reserved bh bh ch adreg6el ch adclk ch ch dh adreg6eh dh dh dh eh adreg 7 fl eh eh eh fh adreg7 fh fh fh res e rv ed fh tmp19a43(rev2.0)22-15 t a ble of s p e c ial funct io n registers
tmp19a43 little-endian a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me [8] k w up fff ff3 60h kw upst00 fff ff3 70h kw upst16 fff ff3 80h pke y 0 fff ff3 90h 1h kwupst01 1h kwupst17 1h pke y 1 1h 2h kwupst02 2h kwupst18 2h pke y 2 2h 3h kwupst03 3h kwupst19 3h pke y 3 3h 4h kwupst04 4h kwupst20 4h kwupcnt 4h 5h kwupst05 5h kwupst21 5h kwupclr 5h 6h kwupst06 6h kwupst22 6h 6h 7h kwupst07 7h kwupst23 7h 7h 8h kwupst08 8h kwupst24 8h kwupint0 8h 9h kwupst09 9h kwupst25 9h kwupint1 9h ah kwupst10 ah kwupst26 ah kwupint2 ah bh kwupst11 bh kwupst27 bh kwupint3 bh ch kwupst12 ch kwupst28 ch ch dh kwupst13 dh kwupst29 dh dh eh kwupst14 eh kwupst30 eh eh fh kwupst15 fh kwupst31 fh fh [9 ] 3 2 -b it in pu t cap ture a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff 4 00h tccr fff ff4 10h cap0cr fff ff4 20h cap2cr fff ff4 30h 1h tbtru n 1h 1h 1h 2h tbtcr 2h 2h 2h 3h 3h 3h 3h 4h tbtcap0 4h tccap0ll 4h tccap2ll 4h 5h tbtcap1 5h tccap0lh 5h tccap2lh 5h 6h tbtcap2 6h tccap0hl 6h tccap2hl 6h 7h tbtcap3 7h tccap0hh 7h tccap2hh 7h 8h tbtrdcapll 8h cap1cr 8h cap3cr 8h 9h tbtrdcaplh 9h 9h 9h ah tbtrdcaphl ah ah ah bh tbtrdcaphh bh bh bh ch tcg0im ch tccap1ll ch tccap3ll ch dh tcg0st dh tccap1lh dh tccap3lh dh eh reserved eh tccap1hl eh tccap3hl eh fh res e rv ed fh tccap1h h fh tccap3h h fh [1 0] 3 2 - bi t out put c o m p are a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff ff 4 40h tccmp0ll fff ff4 50h tccmp4ll fff ff4 60h fff ff4 70h cmpctl0 1h tccmp0l h 1h tccmp4l h 1h 1h cmpctl1 2h tccmp0h l 2h tccmp4h l 2h 2h cmpctl2 3h tccmp0h h 3h tccmp4h h 3h 3h cmpctl3 4h tccmp1ll 4h tccmp5ll 4h 4h cmpctl4 5h tccmp1l h 5h tccmp5l h 5h 5h cmpctl5 6h tccmp1h l 6h tccmp5h l 6h 6h cmpctl6 7h tccmp1h h 7h tccmp5h h 7h 7h cmpctl7 8h tccmp2ll 8h tccmp6ll 8h 8h 9h tccmp2l h 9h tccmp6l h 9h 9h ah tccmp2hl ah tccmp6hl ah ah bh tccmp2hh bh tccmp6hh bh bh ch tccmp3ll ch tccmp7ll ch ch dh tccmp3l h dh tccmp7l h dh dh eh tccmp3hl eh tccmp7hl eh eh fh tccmp3h h fh tccmp7h h fh fh tmp19a43(rev2.0)22-16 t a ble of s p e c ial funct io n registers
tmp19a43 little-endian [1 1] i n tc a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff fe000h imc0 fff fe010h imc4 fff fe020h imc8 fff fe030h imcc 1h ditto 1h ditto 1h ditto 1h ditto 2h ditto 2h ditto 2h ditto 2h ditto 3h ditto 3h ditto 3h ditto 3h ditto 4h imc1 4h imc5 4h imc9 4h imcd 5h ditto 5h ditto 5h ditto 5h ditto 6h ditto 6h ditto 6h ditto 6h ditto 7h ditto 7h ditto 7h ditto 7h ditto 8h imc2 8h imc6 8h imca 8h imce 9h ditto 9h ditto 9h ditto 9h ditto ah ditto ah ditto ah ditto ah ditto bh ditto bh ditto bh ditto bh ditto ch imc3 ch imc7 ch imcb ch imcf dh ditto dh ditto dh ditto dh ditto eh ditto eh ditto eh ditto eh ditto fh ditto fh ditto fh ditto fh ditto a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff fe040h ivr fff fe050h fff fe060h intclr fff fe070h 1h ditto 1h 1h ditto 1h 2h ditto 2h 2h ditto 2h 3h ditto 3h 3h ditto 3h 4h 4h 4h 4h 5h 5h 5h 5h 6h 6h 6h 6h 7h 7h 7h 7h 8h 8h 8h 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch ch ch ch dh dh dh dh eh eh eh eh fh fh fh fh a dr reg i ster na me fff fe100h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch ilev dh ditto eh ditto fh ditto tmp19a43(rev2.0)22-17 t a ble of s p e c ial funct io n registers
tmp19a43 little-endian [1 2] dm ac a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff fe200h ccr0 fff fe210h bcr0 fff fe220h ccr1 fff fe230h bcr1 1h ditto 1h ditto 1h ditto 1h ditto 2h ditto 2h ditto 2h ditto 2h ditto 3h ditto 3h ditto 3h ditto 3h ditto 4h csr0 4h 4h csr1 4h 5h ditto 5h 5h ditto 5h 6h ditto 6h 6h ditto 6h 7h ditto 7h 7h ditto 7h 8h sar0 8h dtcr0 8h sar1 8h dtcr1 9h ditto 9h ditto 9h ditto 9h ditto ah ditto ah ditto ah ditto ah ditto bh ditto bh ditto bh ditto bh ditto ch dar0 ch ch dar1 ch dh ditto dh dh ditto dh eh ditto eh eh ditto eh fh ditto fh fh ditto fh a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff fe240h ccr2 fff fe250h bcr2 fff fe260h ccr3 fff fe270h bcr3 1h ditto 1h ditto 1h ditto 1h ditto 2h ditto 2h ditto 2h ditto 2h ditto 3h ditto 3h ditto 3h ditto 3h ditto 4h csr2 4h 4h csr3 4h 5h ditto 5h 5h ditto 5h 6h ditto 6h 6h ditto 6h 7h ditto 7h 7h ditto 7h 8h sar2 8h dtcr2 8h sar3 8h dtcr3 9h ditto 9h ditto 9h ditto 9h ditto ah ditto ah ditto ah ditto ah ditto bh ditto bh ditto bh ditto bh ditto ch dar2 ch ch dar3 ch dh ditto dh dh ditto dh eh ditto eh eh ditto eh fh ditto fh fh ditto fh a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff fe280h ccr4 fff fe290h bcr4 fff fe2a0h ccr5 fff fe2b0h bcr5 1h ditto 1h ditto 1h ditto 1h ditto 2h ditto 2h ditto 2h ditto 2h ditto 3h ditto 3h ditto 3h ditto 3h ditto 4h csr4 4h 4h csr5 4h 5h ditto 5h 5h ditto 5h 6h ditto 6h 6h ditto 6h 7h ditto 7h 7h ditto 7h 8h sar4 8h dtcr4 8h sar5 8h dtcr5 9h ditto 9h ditto 9h ditto 9h ditto ah ditto ah ditto ah ditto ah ditto bh ditto bh ditto bh ditto bh ditto ch dar4 ch ch dar5 ch dh ditto dh dh ditto dh eh ditto eh eh ditto eh fh ditto fh fh ditto fh tmp19a43(rev2.0)22-18 t a ble of s p e c ial funct io n registers
tmp19a43 little-endian a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff fe2c0 h ccr6 fff fe2d0 h bcr6 fff fe2e0h ccr7 fff fe2f0 h bcr7 1h ditto 1h ditto 1h ditto 1h ditto 2h ditto 2h ditto 2h ditto 2h ditto 3h ditto 3h ditto 3h ditto 3h ditto 4h csr6 4h 4h csr7 4h 5h ditto 5h 5h ditto 5h 6h ditto 6h 6h ditto 6h 7h ditto 7h 7h ditto 7h 8h sar6 8h dtcr6 8h sar7 8h dtcr7 9h ditto 9h ditto 9h ditto 9h ditto ah ditto ah ditto ah ditto ah ditto bh ditto bh ditto bh ditto bh ditto ch dar6 ch ch dar7 ch dh ditto dh dh ditto dh eh ditto eh eh ditto eh fh ditto fh fh ditto fh a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff fe300h dcr fff fe310h fff fe320h fff fe330h 1h ditto 1h 1h 1h 2h ditto 2h 2h 2h 3h ditto 3h 3h 3h 4h rsr 4h 4h 4h 5h ditto 5h 5h 5h 6h ditto 6h 6h 6h 7h ditto 7h 7h 7h 8h 8h 8h 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch dhr ch ch ch dh ditto dh dh dh eh ditto eh eh eh fh ditto fh fh fh a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff fe340h fff fe350h fff fe360h fff fe370h 1h 1h 1h 1h 2h 2h 2h 2h 3h 3h 3h 3h 4h 4h 4h 4h 5h 5h 5h 5h 6h 6h 6h 6h 7h 7h 7h 7h 8h 8h 8h 8h 9h 9h 9h 9h ah ah ah ah bh bh bh bh ch ch ch ch dh dh dh dh eh eh eh eh fh fh fh fh tmp19a43(rev2.0)22-19 t a ble of s p e c ial funct io n registers
tmp19a43 tmp19a43(rev2.0)22-20 t a ble of s p e c ial funct io n registers little-endian [1 3] c s / w a i t co nt r o l l e r a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff fe400h bma0 fff fe410h fff fe480h b01cs fff fe490h 1h ditto 1h 1h ditto 1h 2h ditto 2h 2h ditto 2h 3h ditto 3h 3h ditto 3h 4h bma1 4h 4h b23cs 4h 5h ditto 5h 5h ditto 5h 6h ditto 6h 6h ditto 6h 7h ditto 7h 7h ditto 7h 8h bma2 8h 8h 8h 9h ditto 9h 9h 9h ah ditto ah ah ah bh ditto bh bh bh ch bma3 ch ch bexcs ch dh ditto dh dh ditto dh eh ditto eh eh eh fh ditto fh fh fh [1 4] fl as h c ont rol a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff fe510h seqmod fff fe520h flcs fff fe620h 1h ditto 1h 1h 2h ditto 2h 2h 3h ditto 3h 3h 4h seqcn t 4h reserved 4h reserved 5h ditto 5h reserved 5h reserved 6h ditto 6h reserved 6h reserved 7h ditto 7h reserved 7h reserved 8h romsec1 8h reserved 8h 9h 9h reserved 9h ah ah reserved ah bh bh reserved bh ch romsec2 ch ch dh dh dh eh eh eh fh fh fh [1 5] r o m c o rr ect i on a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff fe540h addreg0 fff fe550h addreg4 fff fe560h addreg8 fff fe570h 1h ditto 1h ditto 1h ditto 1h 2h ditto 2h ditto 2h ditto 2h 3h ditto 3h ditto 3h ditto 3h 4h addreg1 4h addreg5 4h addreg9 4h 5h ditto 5h ditto 5h ditto 5h 6h ditto 6h ditto 6h ditto 6h 7h ditto 7h ditto 7h ditto 7h 8h addreg2 8h addreg6 8h addrega 8h 9h ditto 9h ditto 9h ditto 9h ah ditto ah ditto ah ditto ah bh ditto bh ditto bh ditto bh ch addreg3 ch addreg7 ch addregb ch dh ditto dh ditto dh ditto dh eh ditto eh ditto eh ditto eh fh ditto fh ditto fh ditto fh attention
tmp19a43 little-endian [1 6] c l oc k t i m er a dr reg i ster na me a dr reg i ster na me fff fe700h fff fe710h 1h 1h 2h 2h 3h 3h 4h rtcc r 4h 5h 5h 6h 6h 7h 7h 8h rtcre g 8h 9h ditto 9h ah ditto ah bh ditto bh ch ch dh dh eh eh fh fh [1 7] u a r t /h s i o a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff fe800h hsc0buf fff fe810h hsc1buf fff fe820h hsc2buf fff fe840h 1h 1h 1h 1h 2h 2h 2h 2h 3h 3h 3h 3h 4h hbr0add 4h hbr1add 4h hbr2add 4h 5h hsc0mod1 5h hsc1mod1 5h hsc2mod1 5h 6h hsc0mod2 6h hsc1mod2 6h hsc2mod2 6h 7h hsc0en 7h hsc1en 7h hsc2en 7h 8h hsc0rf c 8h hsc1rf c 8h hsc2rf c 8h 9h hsc0t f c 9h hsc1t f c 9h hsc2t f c 9h ah hsc0rst ah hsc1rst ah hsc2rst ah bh hsc0tst bh hsc1tst bh hsc2tst bh ch hsc0fc nf ch hsc1fc nf ch hsc2fc nf ch dh hsc0cr dh hsc1cr dh hsc2cr dh eh hsc0mod0 eh hsc1mod0 eh hsc2mod0 eh fh hbr0cr fh hbr1cr fh hbr2cr fh [1 8] cg a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me a dr reg i ster na me fff fee00h s y scr 0 fff fee10h imcga fff fee20h eicrc g fff fee40h 1h s y scr 1 1h ditto 1h ditto 1h 2h s y scr 2 2h ditto 2h ditto 2h 3h s y scr 3 3h ditto 3h ditto 3h 4h 4h imcgb 4h nmifl g 4h 5h 5h ditto 5h 5h 6h 6h ditto 6h 6h 7h 7h ditto 7h 7h 8h 8h imcgc 8h 8h 9h 9h ditto 9h 9h ah ah ditto ah ah bh bh ditto bh bh ch ch imcgd ch ch dh dh ditto dh dh eh eh ditto eh eh fh fh ditto fh fh tmp19a43(rev2.0)22-21 t a ble of s p e c ial funct io n registers
tmp19a43 23. jt ag interface the tmp19a43 is equippe d with the bounda ry sca n in t e rface t h at conform s to th e joint t e st action group (jt a g) standa rd. t h is i n terface uses t h e i n dustry -stand a r d jt ag prot ocol (iee e s t anda rd 1 1 49.1/ d 6). t h is chapte r de scribes this jt ag interface with a m e ntion of bounda r y scan, inte rface pins, interface signals, and test access ports (t ap). 23.1 boundar y scan overvie w ic (inte g rate d circuit) density is eve r inc r e a sing, sm ds (surface m o unt de vices) cont inue t o decreas e in size, com pone nt s a r e n o w m ount ed o n bot h si des o f pri n t e d ci rcui t b o ar d s (pc b s ), an d t h ere are c o n s i d era b l e t echni cal de ve l opm ent s rel a t e d t o em bed d i ng h o l e s. c o nve nt i o nal i n t e rnal ci rcui t t e st i n g t ech ni q u es a r e depe ndent on the physical contact betw ee n internal circ uitry and c h ips and, t h erefore, th eir lim i t at io n s with respect to e f fi ciency and ac curacy a r e m a nifest. w ith t h e ev er -in c reasin g ic co m p lex ity , tests cond u c ted t o p e rform in sp ectio n s o n all ch ip s i n tegrated in to an ic a r e becom i ng la r g e r in scale, and it is becoming m o r e d i f f icu lt to d e si g n an ef ficien t, reliab l e ic testin g prog ram . t o ov erco m e th is d i f f icu lty in p e rform i n g ic tests, th e "bo und ar y scan " cir c u it w a s d e v e lop e d. i t is a g r ou p of sh ift reg i sters called "bou nd ary scan cells" estab lish e d b e tw een pi ns a n d i n t e rnal ci rcui t r y (see fig . 23 -1 ). these b oun d a ry scan cells are b y p a ssed un d e r n o rmal co n d ition s . wh en an ic g o e s in to test m o d e , d a ta is sen t fro m th e b oun dar y scan cells thr oug h th e sh if t r e gister bu s in res p o n se t o t h e i n st ruct i o n gi ven by a t e st p r og r a m , an d vari ous di a g n o s t i c t e st s are e x ecut e d. i n ic t e st s, fi ve signals tdi, t d o, tms, tc k a n d trs t are us ed. these si gnal s a r e e x p l ai ned i n t h e ne xt sect i o n. i n t egrat ed c i rc ui t p i ns on i c pac k age b oundary s c an c e l l s fig. 23-1 jt ag bounda ry scan cell s note) the option a l instruc tions idco de, userco de, intest and runbist ar e not imple m ented in the tmp19a43. tmp19a43(rev2.0) 23-1 jt ag interface
tmp19a43 23.2 jt ag interface signals jt ag i n terface signals are as follo ws (see fig. 2 3 - 2 ): ? tdi : t o inpu t jt ag serial d a ta ? tdo : t o out put j t ag seri al dat a ? tms : t o select j t ag test m ode ? tck : t o input jt ag se rial clock ? trst : t o inpu t jt ag test reset 30 i n s t ruct ion re gis t er tap c o n t r o lle r 0 b y pass reg i s t er 0 29 6 b o u ndary s c an regis t er j t di pin j t do pin j t m s pin j t ck pin t r s t pin fig. 23 -2 jt a g interface signal s and re gisters th e jt ag bou nd ar y scan m echanism (he r eafter called " j t a g m echani s m" ) ena b les testing of t h e proces sor , pri n t e d ci rc ui t boa r d s co n n ect ed t o t h e pr oce ssor , a n d co n n ect i ons bet w ee n ot her c o m ponent s on pri n t e d ci rcui t boa r d s. the j t ag m e chani s m does n o t ha ve a f u nct i on o f t e st i n g t h e pr ocess o r i t s el f. tmp19a43(rev2.0) 23-2 jt ag interface
tmp19a43 23.3 jt ag con t roller and registers th e fo llowing jt ag con t ro ller an d reg i sters are bu ilt in to t h e p r o cesso r: ? inst ructio n regi ster ? bo und ar y scan r e g i ster ? bypass re gister ? device i d entifi cation register ? t e st access port (t ap) c o ntroller in the jt ag basic m echanism , the t a p con t ro ller state mach in e m o n ito rs th e sign als inp u t th rou gh th e jtms pi n. as t h e j t ag m echani s m st art s operat i on, t h e t a p c ont rol l e r det e r m i n es a t e st f u nct i o n t o be e x ecut e d by lo ad ing d a ta i n to th e jt ag instru ction reg i st er (ir) and pe r f o r m i ng a se ri al dat a sca n vi a t h e d a t a re gi st er ( d r ) , as sh ow n i n t a bl e 2 3 - 1 . wh e n dat a i s sca n n e d, t h e st at e o f t h e jtm s pi n r e prese n t s new speci fi c dat a w o r d s a nd the end of data flow . the data re gister is sele cted acc o r d i ng to d a ta l o ad ed in to t h e instructio n reg i ster . 23.3.1 instruction register th e jt ag i n st ru ction reg i ster con s ists of fou r cells, in cl udin g sh ift reg i sters. it is u s ed to select eith er a test to be e x ec uted or a test data register t o be accesse d or to sel ect both. either the bounda ry sca n regi st er o r t h e by pass re gi st er i s sel ect ed acc or di n g t o c o m b i n at i ons sh o w n i n t a bl e 2 3 - 1 . t able 23-1 bit configu r atio ns of the jt ag instru ction regi ster in stru ctio n cod e mo st sig n i fican t to least sig n i fican t b i t in stru ctio n data r e g i ster t o b e selected 0000 extest boundar y scan r e gister 0001 sam p le/preload boundar y scan r e gister 0010 to 1110 reserved reserved 1 1 1 1 b y p a s s b y p a s s r e gister fi g. 2 3 - 3 s h ow s t h e fo rm at of t h e i n st r u ct i o n regi st er . 3 2 1 0 m s b l s b fig. 23-3 in structio n re gist er tmp19a43(rev2.0) 23-3 jt ag interface
tmp19a43 th e i n stru ctio n cod e is sh ifted fro m th e least sig n i fican t b it to th e in stru ction reg i ster . leas t s i gnif i c ant td o td i m o s t s i gnif i c ant fig. 23 -4 di re ction of a shif t of the instru ction code to the instru ctio n regi ster 23.3.2 by p a ss re gister the by pass re g i st er has a o n e- bi t wi dt h. if t h e t a p c ont ro ll er is in th e sh ift-dr state (b yp ass state), d a t a at t h e td i pi n i s shi f t e d i n t o t h e by pass re gi s t er , an d t h e o u t put fr om t h e b y p ass re gi st er i s shi f t e d out t o th e td o ou tput p i n . si m p ly p u t , the b y p a ss r e g i ster is a cir c u it f o r b y p a ssing th e d e v i ces in a ser i al bo undar y scan ch ain connected t o the substrates t h at are n o t re q u i r e d f o r a t e st t o be co n duct e d. fi g. 23 -5 s h o w s t h e l ogi c a l p o s ition o f th e b y p a ss reg i ster in a bo und ary scan ch ain. if t h e by pass r e gi st er i s used , t h e spe e d of a ccess t o boundary scan re gisters in a n active ic in a data pat h use d fo r s ubst r at e l e vel t e st i ng ca n be i n crease d . jt d o inp u t to s u b s t r at e i c pac k age s ubs t r at e jt d i by p a ss r e gi ste r p ad c e ll of bou ndary s c an regis t er inp u t fr o m s ubs t r at e jtd i jt d i jt d o jtd o jtd o jtd i jt d o jt d i fig. 23-5 f u n c tion of the byp a ss regi ster tmp19a43(rev2.0) 23-4 jt ag interface
tmp19a43 23.3.3 boundary scan register th e bou nd ar y scan r e g i ster has inpu ts and ou tpu t s f o r so me an al og ou tput sign als, as well as all si g n a l s fr om t h e tm p19 a 43 exce pt co nt rol si gnal s . pi ns o f t h e tm p1 9a 4 3 ca n dri v e any t e st pat t e rns by scann i ng d a ta in to t h e bou ndar y scan r e g i ster i n t h e sh ift-dr state. after t h e boundary scan register g o e s in t o th e cap t ure-dr state, d a ta en ters t h e process o r , is shifte d, and i n spected. the b o u n d a r y scan re gi st er f o rm s a dat a pat h . it ba si cal l y fu nct i o ns as a si ngl e s h i f t re g i st er of 29 7 - bi t wid t h. cells in th is d a ta p a th are co nn ected to all in pu t an d ou tpu t p a d s of t h e tmp19 a 43. th e tdi i n pu t is in trod u c ed to th e least sign ifican t bit (l sb) in the bounda ry scan re gister . the m o st si gni fi ca nt bi t i n t h e b o u n d a r y scan re gi st er i s t a ke n out of t h e t d o out put . 23.3.4 t est acces s port (t ap) the test acces s port (t ap) c onsists of five signal pi ns: t r st , t d i, t d o, tms, a n d tck. serial test data, instructi o ns a n d test control signals a r e sent a n d recei ved through the s e signal pi ns. dat a i s se ri al l y scan ned i n t o o n e of t h ree r e gi st ers (i nst r u c t i on regi st er , by pass re gi st er an d b o u n d ary scan regi st er ) vi a t h e td i pi n or i t i s scan n e d out fr om on e o f t h ese t h re e re gi st ers i n t o t h e t d o pi n, as sho w n i n fi g. 23 - 6 . th e tms inp u t is u s ed to con t ro l th e state tran sitio ns o f t h e m a in t a p co n t ro ller state m ach in e. the tck inp u t is a test clo c k ex clu s i v ely f o r sh if tin g ser i al jt ag data syn c hr onou sly; it w o rks i nde pen d e n t l y of a c h i p c o re cl ock o r a sy st em cl ock. tc k dat a is s e rially s c anned out . t d o i s s a m p led on t h e f a lling edge of t c k . t m s and t d i are s a m p led on t h e r i s i ng edge of t c k . dat a is s e rially s c anned i n . t d i pin t m s pin t d o pin 0 0 3 i n s t ruc t ion regis t er b y pas s regis t er 115 b oundary s c an regis t er 0 0 0 i n s t ruc t ion regis t er b y pas s regis t er 115 b oundary s c an regis t er 0 fig. 23-6 jt a g t e st access port dat a t h ro u gh t h e t d i an d t m s pi n s are sa m p l e d on t h e ri si ng e d ge of t h e i n p u t cl oc k si gnal tc k. dat a t h r o u g h t h e t d o pi n c h an ge s o n t h e fal l i n g ed ge of t h e cl ock si g n al tc k. tmp19a43(rev2.0) 23-5 jt ag interface
tmp19a43 23.3.5 t a p contro ller in the process o r , a 16-state t a p c ontroller s p ecifi ed in the ieee j t ag sta nda rd is im plem ented. 23.3.6 controller reset t o re set the sta t e m achine of t h e t a p c ont rol l er , assert the trs t signal input (low) t o reset the t a p c ont rol l er or ? ? cont i n ue t o as s e rt t h e i n p u t si gnal tm s by usi n g t h e ri si n g e dge of t h e tc k i n p u t fi v e t i m e s successi vely after clearing t h e re set state of t h e process o r . the reset state can be m a intained by kee p ing tms in an ass e rted state. tmp19a43(rev2.0) 23-6 jt ag interface
tmp19a43 23.3.7 s t ate t r ansitions of the t a p controller fig . 23 -7 sh ows th e state tran sitio n s of the t a p c ont roll er . t h e state of the t a p c o ntroller c h anges d e p e nd ing o n wh ich v a lu e tms will select on th e rising ed g e of tc k, 0 o r 1 . in th is figu re, th e arrow sh ows a state transitio n and t h e v a lu e that tms se lect s to ex ecu t e each st ate t r an sitio n is sho w n alongside of the arrow . t e s t -logi c - r e s e t 1 0 0 1 0 1 ru n-t e s t / i dl e se le c t - d r - scan 1 1 cap t ure-dr 0 s h ift- d r 1 ex it 1 - d r 0 p a us e-dr 1 ex it 2 - d r 1 up dat e-dr 0 1 0 0 1 se le ct- i r - s c a n c apt ure-i r 0 sh ift- ir 1 exit 1 - ir 0 p aus e-i r 1 exit 2 - ir 1 u pdat e-i r 0 1 1 00 1 0 0 0 fig. 23 -7 s t at e t r a n sition diag ram of th e t a p contro ller tmp19a43(rev2.0) 23-7 jt ag interface
tmp19a43 th e t a p co n t ro ller op erates in each state d e scrib e d b e low . in fi g . 23 -7 , a co lu m n to th e left is t h e d a ta co lu m n and a co lu m n to t h e ri g h t is th e in st ru ctio n co lu m n . th e d a ta co lum n rep r esen ts t h e d a ta reg i ster (dr), and th e in stru ctio n co l u m n rep r esen ts t h e instru cti o n reg i ster (ir). ? t e st-lo g ic-re s et if th e t a p con t ro ller is in a reset state, th e d e v i ce id en tificatio n reg i ster is selected b y d e fau lt. th e m o st si gni fi can t bi t i n t h e bo u nda ry sca n regi st er i s cl eare d t o " 0 ," a n d t h e out put i s di sa bl ed. th e t a p con t ro ller rem a in s i n th e t e st-lo g ic-reset state i f tms is "1 ." if "0 " is inp u t in to tms in the t e st -l ogic-reset state, the t a p c ont ro l l er goes i n to t h e run-t e st/idle state. ? ru n-t e st/id l e in t h e run-t e st/idle state, the ic goes int o test m ode only if a specific in struction, such as the b u ilt-in self test (bist) in st ructio n , is issu ed. if an i n stru ctio n t h at canno t b e ex ecu ted in th e run - t e st/id l e state h a s b e en issu ed , th e test d a ta reg i st er selected b y t h e last i n stru ctio n m a i n tain s th e existing state. th e t a p con t ro ller rem a in s in th e run - t e st /id l e state if tms is "0." if "1 " is i n pu t in t o tms, t h e t a p c ont roller goes i n to t h e select-dr-sca n state. ? select-dr-sca n the select-dr - sca n state of the t a p c ont roller is a tra n si ent state. in thi s state, the ic performs n o op eratio n s . if "0 " is i n pu t in to tms wh en th e t a p contro ller is i n th e select-dr - scan state, th e t a p con t ro ller go es i n to th e cap t ure-dr state. if "1 " is inp u t in t o tm s, th e i n stru ctio n co lu m n go es i n to th e se lect-ir-scan state. ? select-ir-sca n the select-ir -scan state of t h e t a p c o ntroller is a tra n sient state. in t h is s t ate, the ic perform s no ope rat i o ns. if "0 " is inpu t in to tm s wh en th e t a p con t ro ller is in t h e select-ir-scan state, th e t a p co n t ro ller goe s i n t o t h e c a pt ure -ir st a t e. if " 1 " i s i n put i n t o tms, th e t a p co n t ro ller ret u rn s to th e t e st- logic-reset st ate. ? c a pt ure - dr if th e d a ta reg i ster selected by th e in stru ction reg i ster h a s p a rallel in pu ts wh en th e t a p co n t ro ller is in th e cap t ure-dr state, data is lo ad ed i n to th e d a ta reg i ster in a p a rallel fash io n. if th e d a ta reg i ster do es no t h a v e p a rallel in pu ts o r if data do es no t need t o b e l o aded i n to t h e selected test dat a re gi st er , t h e dat a re gi st er m a in tain s th e ex istin g state. if "0 " is inp u t in to tms wh en t h e t a p co ntro ller is in t h e cap t u r e-dr state, th e t a p co n t ro ller g o e s i n to th e sh ift-dr state. if "1 " is inpu t i n to tms, th e t a p con t ro ller go es in to the ex it 1 - dr state. tmp19a43(rev2.0) 23-8 jt ag interface
tmp19a43 ? sh ift-dr if the t a p controller is i n t h e shift - dr state, da ta is serially sh ifted o u t b y t h e d a t a reg i ster connected between t d i a n d tdo. if th e t a p contro ller is in th e sh ift-dr state, th e sh i f t-dr state is m a in tai n ed wh ile tms is "0 ." if "1 " is i n pu t i n to tms, t h e t a p con t ro ller go es i n to t h e exit 1 - dr state. ? ex it 1-dr th e ex it 1-dr state o f th e t a p co n t ro ller is a tran sien t state. if "0 " is inp u t in to tms wh en the t a p co ntro ller is in t h e ex it 1 - dr st ate, th e t a p co n t ro ller g o e s in t o th e pau s e-dr state. if "1 " is i n pu t i n to tms, it g o es in to th e up date-dr state. ? pause - dr in the pa use-dr state, t h e shi f t ope r ation perf o r m e d by t h e dat a regi st er sel ect ed by t h e in stru ction register is te m p orarily su sp en ded . t h e i n st r u ct i on re gi st er and t h e dat a regi st er main tain th eir ex istin g state. th e t a p con t ro ller rem a in s i n th e pau s e-dr state wh ile tms is "0 ." if "1 " is in pu t into tms, it g o e s in t o th e ex it 2-dr state. ? ex it 2-dr th e ex it 2-dr state o f th e t a p co n t ro ller is a tran sien t state. if "0 " is inp u t in to tms wh en the t a p co ntro ller is in t h e ex it 2 - dr st ate, th e t a p co n t ro ller retu rn s to t h e sh ift-dr state. if "1 " is inpu t in to tms, it g o es in to th e up date-dr state. ? up date- d r in th e upd a te-dr state, d a ta is ou tpu t i n a paralle l fas h i o n fr om t h e dat a r e gi st er ha vi n g a pa ral l e l out put sy nch r o n o u sl y t o t h e ri si ng ed ge of tc k. the da t a regi st er wi t h a paral l e l o u t put l a t c h d o e s n o t ou tput d a ta during the sh ift op eration ; it ou tpu t s d a ta o n l y in th e upd a te-dr state. if "0 " is inp u t in to tms wh en th e t a p contro ller is in th e upd a te-dr st ate, th e t a p co n t ro ller g o e s in t o th e ru n-t e st/id l e state. if "1 " is inp u t i n to tms, it g o e s in to th e select-dr - scan state. ? c a pt ure -ir in th e cap t u r e-ir state, d a ta is l o ad ed in t o t h e i n stru ctio n reg i ster in a p a rallel fashio n . data lo ad ed is 000 1. th e cap t ure-ir state is u s ed t o test t h e i n stru ction reg i ster . a m a lfu n c tio n o f the in stru ction reg i ster can b e d e t ected b y sh ifti n g ou t th e d a ta lo ad ed . if "0 " is in pu t in to tms wh en th e t a p contro ller is in th e cap t u r e-ir st ate, th e t a p co n t ro ller g o e s in t o th e sh ift-ir state. if "1 " is i n pu t i n to tms, it go es in to t h e ex it 1-ir state. ? sh ift-ir in th e sh ift-ir state, t h e in stru ctio n reg i ster is connected between t d i a n d tdo, a n d da ta loa d ed syn c hrono usly to th e rising edg e o f tck is serially sh ifted o u t . th e t a p con t ro ller rem a in s i n th e sh ift-ir state wh ile tms is "0." if "1 " is i n pu t i n to tms, t h e t a p co n t ro ller go es i n to t h e ex it 1-ir state. ? ex it 1-ir the e x it 1-ir state of t h e t a p c ontroller is a transie n t state. if "0 " is i n pu t i n to tm s wh en th e t a p con t ro ller is in th e ex it 1-ir state, th e t a p con t ro ller g o e s in to th e pau s e-ir state. if "1 " is in pu t in t o tms, it go es i n to th e upd a te-ir state. tmp19a43(rev2.0) 23-9 jt ag interface
tmp19a43 ? pause -ir in th e pau s e-ir state, th e sh ift o p e ration p e rfor m e d b y th e in stru ction reg i ster is tem p o r arily sus p ende d. t h e existing sta t e of t h e inst ruction registe r and t h at of the data re gister are main tain ed . th e t a p co n t ro ller rem a in s in th e pau s e-ir state wh ile tms is "0 ." if "1 " is inpu t in t o tms, it g o e s in t o th e ex it 2-ir state. ? ex it 2-ir the e x it 2-ir state of t h e t a p c ontroller is a transie n t state. if "0 " is i n pu t i n to tm s wh en th e t a p con t ro ller is in th e ex it 2-ir state, th e t a p con t ro ller g o e s in to th e sh ift-ir state. if "1 " is inp u t i n to tms, it go es i n to th e upd a te-ir state. ? up date- i r in th e upd a te-ir state, i n structio n s sh ifted i n to th e i n stru ct io n reg i ster are up dated b y outp u ttin g t h em i n a paral l el fashi o n sy n c hr o n o u sl y t o t h e ri si ng ed ge of tc k . if "0 " is inpu t in to tms wh en th e t a p contro ller is in the up d a te-ir st ate, th e t a p co n t ro ller g o e s in t o th e ru n-t e st/id l e state. if "1 " is inp u t i n to tms, it g o e s in to th e select-dr - scan state. t a b l e 23 -2 show s the b oun d a ry scan sequ enc e relative to process o r signals . t able 23-2 jt ag scan seq uen ce relative to the tmp19a43 pro c e s sor pin s [tdi] 1 : p 9 0 2 : p e 5 3 : p 9 1 4 : p 9 3 5 : p e 6 6 : p 9 2 7: p94 8: pe7 9: p95 10: p97 11: p96 12: pa0 13: pa1 14: pa2 15: pa3 16: pa4 17: pa7 18:pa6 19: pa5 20: pb2 21: pb1 22: pb5 23:pb4 24: pb0 25: pb7 26: pb6 27: pb3 28: boot 29: p32 30: p36 31: p00 32: p37 33: p33 34: p04 35: p01 36: p34 37: p35 38: p 3 0 3 9 : p 0 5 4 0 : p 1 0 4 1 : p 3 1 42: p02 43: p11 44: p03 45: p06 46: p14 47: p07 48: p15 49: p12 50: p13 51:p16 52:p17 53:p20 54:p21 55:p22 56: p25 57: p24 58: p23 59: p27 60: p26 61: p53 62: p52 63: p57 64: p51 65: p56 66: p50 67: p63 68: p62 69: p55 70: p67 71: p66 72:p54 73: p 6 1 7 4 : p 4 1 7 5 : p 4 0 7 6 : p 4 3 7 7 : p 4 2 7 8 : p 6 5 7 9 : p 6 0 80:p 4 4 8 1 : p 4 5 8 2 : p 4 6 8 3 : p 4 7 84: p64 85: pg3 86: pg6 87: pg7 88:pg4 89:pg5 90:pg0 9 1 : p g 1 9 2 : p g 2 9 3 : t o v 94:ph 3 9 5 : d i n t 9 6 : p h 2 9 7 : p h 1 9 8 : p h 7 9 9 : d c l k 1 0 0 : p c s t 4 1 0 1 : p c s t 3 102: pcst2 103: pcst1 104:pcst0 105:ph6 106:ph0 107:pc3 108: pc4 109: ph5 110: ph4 111: pc1 1 1 2 : p c 7 1 1 3 : p c 6 1 1 4 : p c 5 1 1 5 : p c 2 1 1 6 : p c 0 1 1 7 : p f 6 1 1 8 : p f 3 1 1 9 : p f 7 1 2 0 : p f 4 1 2 1 : p f 5 122:pf1 1 2 3 : p f 2 1 2 4 : p f 0 1 2 5 : p d 0 1 2 6 : p d 1 1 2 7 : p d 2 1 2 8 : p d 3 1 2 9 : p d 4 1 3 0 : p d 5 1 3 1 : p d 6 1 3 2 : p 7 7 1 3 3 : p 7 6 1 3 4 : p 7 5 1 3 5 : p 8 7 1 3 6 : p 7 4 1 3 7 : p 8 5 1 3 8 : p 8 6 1 3 9 : p 8 4 1 4 0 : p 8 3 1 4 1 : p 7 3 1 4 2 : p 8 2 1 4 3 : p 8 1 1 4 4 : p 8 0 1 4 5 : p 7 1 1 4 6 : p 7 2 1 4 7 : p 7 0 1 4 8 : p e 0 1 4 9 : p e 1 150: p e 2 1 5 1 : p e 3 1 5 2 : p e 4 [ t d o ] terminal list to which jta g can be scanned. tmp19a43(rev2.0) 23-10 jt ag interface
tmp19a43 instructions suppor ted by the jt ag controller cells th is section d e scrib e s th e i n stru ction s supp orted b y th e jt ag con t ro ller cells o f t h e tm p19 a 43 . 23.3.8 extest in struction the e x te st i n struction is us ed for ex tern al in terconn ect test. if th is in st ructio n is issu ed, th e bsr cells at o u t p ut pi ns out put t e st pat t e rns i n t h e up dat e - d r st at e, and t h e b s r c e l l s at i n put pi ns ca pt ure t e st results i n the capture-dr state. before t h e extest in stru ctio n is selected , th e bou nd ary scan reg i ster i s usu a lly in itialized using t h e sample/pr eload in stru ctio n . if th e bou nd ary scan reg i ster h a s no t b e en i n itializ ed , t h ere is the p o s sib ility th at in d e term in ate d a ta will b e t r an sm itted in th e upd a te-dr state and b u s con f licts m a y o ccur b e tw een i c s. fi g . 23 -8 sh ow s th e f l ow of d a ta wh ile th e extest instru ction is sel ected . i n t e rnal l ogi c out put td o i nput td i b oundary s c an pat h fig. 23-8 flo w of dat a wh ile the extest instru ctio n is selected th e b a sic ex tern al in tercon n e ct test p r o cedure is as fo llows: 1 . in itialize th e t a p con t ro ller t o p u t it in th e t e st-log ic-reset state. 2. loa d the s a mple/prel oad inst ruction i n to t h e instru ctio n reg i ster . th is allows th e b oun d a ry scan register to be c o nnecte d betwee n t d i a n d t d o. 3 . in itialize th e bo und ary scan reg i ster b y sh iftin g i n d e term in ate d a ta. 4 . lo ad th e in itial test d a ta in t o t h e b oun d a ry scan reg i ster. 5 . lo ad th e extest instru cti o n in t o th e in st ru ctio n reg i ster . 6. c a pt ure t h e dat a ap pl i e d t o t h e i n p u t pi n a n d i n p u t i t i n t o t h e bo u nda ry sca n regi st er . 7 . sh ift ou t th e cap t ured d a ta while si m u ltan e o u sly sh ifting in th e n e x t test p a t t ern . 8. out put t o t h e o u t p ut pi n t h e t e st pat t e rn t h at wa s sh ifted in t o th e bou nd ary scan reg i ster fo r ou tpu t . repeat steps 6 through 8 for each test p a ttern. exte st inst ructio n cpu is work ing an d not e the termi nal in put , please when using it. exte st inst ructio npl ease t est a fter r eleas ing sy stem reset wh en using it. tmp19a43(rev2.0) 23-1 1 jt ag interface
tmp19a43 23.3.9 sample a nd preload instructions the samp le and prel oad inst ructio ns are used to c o nnect tdi a n d tdo b y way o f th e bo und ary scan register. each i n st r u ct i o n per f o r m s t h e fu nct i o n descri bed bel o w: ? th e sample in stru ction is used t o m o n ito r th e i/ o p a d o f an ic. wh ile sample is m o n ito ri n g t h e i/ o pa ds , t h e i n t e r n al l o g i c i s not di sc o nnect e d f r om t h e i/ o pi ns of an ic . t h i s i n s t ruct i o n i s execut e d i n t h e c a pt ure - dr st at e. a m a i n f unct i o n o f sa m p le i s t o re ad val u e s of t h e i/ o pi ns of a n ic at t h e ri si ng e d ge o f tc k d u r i n g n o rm al funct i o n a l ope rat i o n . f i g. 2 3 - 9 s h ows t h e fl o w o f d a ta wh ile th e sample i n stru ctio n is selected . inte r n a l log i c out p ut tdo i n put td i b ound ary s c a n pat h fig. 23-9 flow of dat a while sample i s selec t ed ? th e prelo a d i n stru ctio n i s used to in itialize th e bo undar y scan r e g i ster b e for e selectin g o t h e r in stru ction s . fo r ex am p l e, th e b oun d a ry scan reg i ster is in itialized u s in g pr eload b e fo re selecting t h e exte st i n struction, a s pre v ious ly ex p l ai n e d. preload sh ifts d a ta in to th e bo u nda ry sca n re gi st er wi t h o u t af fect i n g t h e n o rm al ope r a t i on of t h e s y st em l ogi c. f i g. 2 3 - 10 sh ows th e flow of d a ta wh ile th e preload in stru ction is selected . out p ut tdo i n put td i b ound ary s c a n pat h inte r n a l log i c fig. 23-1 0 flow of t e st da t a while p r eload is sele cted tmp19a43(rev2.0) 23-12 jt ag interface
tmp19a43 23.3.10 byp a ss in struction whe n c o nd uct i ng t h e t y pe o f t e st i n whi c h a n ic d o es not nee d t o be co nt rol l e d o r m oni t o red, t h e b y p a ss i n st r u ct i on i s used t o fo rm t h e short e st seri al pa t h by pas s i n g an ic by c o n n e c t i ng t h e by pa ss regi st er bet w ee n jt di an d j t d o . t h e b y p a ss i n st r u ct i o n does n o t a f fe ct t h e n o rm al operat i o n of t h e sy st em l ogi c i m pl em ent e d o n a c h i p . dat a pa sses t h r o u g h t h e by pass re gi st er w h i l e t h e b y p a s s in stru ction is selected , as shown in fig . 23-1 1 . td o td i b y pas s regis t er 1 bit fig. 23-1 1 flo w of dat a wh ile the byp a ss re giste r is selected 23.4 point s to note thi s sect i o n descri bes t h e poi nt s t o n o t e re gar d i n g j t ag bo u nda ry sca n o p erat i o ns i m pl em ent e d i n t h i s pr ocess o r . ? ? the x 2 a n d x 1 si gnal pa ds d o not c o m p l y wi t h j t a g . t o reset th e jt ag circu it, ex e c ute either of t h e following: c in itialize th e jt ag circu it b y asserting tr st , and th en d e assert trst . d set th e tms p i n to "1," an d su pp ly tck wit h m o re th an 5 clo c k s . tmp19a43(rev2.0) 23-13 jt ag interface
tmp19a43 tmp19a43 (rev2.0) 24-1 various protecting functions 24. various protecting functions 24.1 overview the rom protect function for designating the internal ro m (flash) area as a read-p rotected area and the dsu protect function for prohibiting the use of dsu (dsu-probe) are built into the tmp19a43. the read protect functions specifically include the following: ? flash protect function ? rom data protect function ? dsu protect function 24.2 features 24.2.1 flash protect function a built-in flash can prohibit the operation of writing and the deletion at every the block of every 128 kbyte. this function is called the block protecting. to make the block protecting function effective, it protects it corresponding to the block where it wants to put protecting. the bit is made "1". the block protecting can be released by making the protecting bit "0". (please see the chapter of the flash operation explanation about the program method. )the protecting bit can be monitored by flcs register < blpro3:0 > bit. the state to put protecting on all blocks is called the flash protecting. it is necessary to note it because all the protecting bits become "0" after auto matically deleting all data of the flash when the protecting release operates after it puts it into the st ate of the lash protection of 1f(operation that makes the protecting bit "0"). flash is always being protected in the mask version, and the flash protecting cannot be released. this function doesn't influence usual operation in the mask version. it is necessary to be protecting flash to make "rom data protecting" and "dsu protecting" that will explain in the future effective.
tmp19a43 tmp19a43 (rev2.0) 24-2 various protecting functions 24.2.2 rom data protect as for rom data protecting, the execution of the command to the flash is prohibited in the function it, and the flash version that limits reading data to building flash/rom into. when rom protecting register romsec1 bit is "1", rom data protecting becomes effective with flash protected. if instructions in the rom area have been replace d with instructions in the ram area in a pc by using the rom correction function, a pc shows the instructions as residing in the flash rom area. because they actually reside in the ram area, data cannot be read in a rom pr otected state. to read data by using instructions held in the overwritten ram area, it is necessary to write data to ram by using a program available in the rom area or to use other means. if the rom area is put in a protected state, th e following operations cannot be performed: ? using instructions placed in areas other than the rom area to load or store the data taken from the rom area ? store to dmac register (nmi by the bus error is generated. ) ? loading or storing the data taken from the rom area in accordance with ejtag ? using boot-rom to load or store the da ta taken from the rom area (flash only) ? executing flash writer to load or store the data taken from the rom area(flash only) ? using instructions placed in areas other than the rom area to access th e registers (romsec1, romsec2) that concern the protection of the rom area ? executing the command to unprotect automatic blocking in writer mode, performing the flash command sequences other than the automatic blocking unprotect command sequence, and performing the flash command sequence in single or boot mode by specifying an address in the rom area(flash only) the following operations can be performed even if the rom area is in a protected state: ? using instructions placed in the rom area to load the data taken from the rom area ? using instructions placed in all areas to load the data taken from areas other than the rom area ? using instructions placed in all areas to ma ke instructions branch off to the rom area ? performing pc trace (there are restrictions) or break on the rom area in accordance with ejtag ? data transfer of rom area by dmac
tmp19a43 tmp19a43 (rev2.0) 24-3 various protecting functions 24.2.3 dsu protect the dsu protecting function is a function for invalidating the connection of dsu-probe to enable third parties other than the user to read the data of a built-in flash easily. when seqmod register < dsuoff > bit is "1", the dsu protecting becomes effective with flash protected. in the dsuoff bit, the flash version, the mask versio n, and the state of the first stage are "1. "it enters the state of the dsu protecting as long as the flash protecting is always effective in the mask version, and the dsuoff bit is not set to "0" by the user program. it doesn't enter the state of the dsu protecting if protecting is not put on all blocks of flash in the flash version. an initial state enters the state of the dsu protecting as well as the mask version when flash is being protected putting protecting on all blocks of flash. (note) the dsuoff bit can be accessed only with the instruction put on built-in rom in the state of rom data protecting. it is necessary to note it beca use it is necessary to put the program of the dsu protecting release on built-in rom.
tmp19a43 tmp19a43 (rev2.0) 24-4 various protecting functions 24.3 protect configuratio n and protect statuses fig. 24-1 various protect statuses table 24-1 protect statuses in each mode protect bit setting flcs 1111 1111 rom protect enable bit roms ec1 1 0 don't care dsu protect enable bit seqmod 1 0 1 0 don't care flash read protect status on off rom protect status on off off dsu protect status on off on off off read of flash from internal rom { { { { { read of flash from areas other than internal rom *1 *1 { { { clearing of rom protect enable status (from rom) { { { clearing of rom protect enable status (from areas other than rom) *2 *2 { clearing of dsu protect enable status (from rom) { { { clearing of dsu protect enable status (from areas other than rom) *3 { { issuing of the command to erase protect bits *4 *4 { *8 { *8 { issuing of commands other than the command to erase protect bits *5 *5 *7 *7 ? *9 writing of data to the dmac setting register (from rom) { { { { { single /single boot mode writing of data to the dmac setting register (from areas other than rom) *6 *6 { { { *1 : the data of address "0xbfc0_00 00" or "0xbfc0_0002" can be read. *2 : stored data is masked. a write to registers canno t be executed (data in registers cannot be cleared). *3 : stored data is masked. a write to registers canno t be executed (data in registers cannot be cleared). *4 : a command address is masked, and fl ash memory does not recognize commands. *5 : a command address is masked, and fl ash memory does not recognize commands. *6 : a bus error exception occurs (when making the dmac register setting). *7 : because a read of flash memory is prohibited, commands are not recognized. *8 : because a read of flash memory is prohibited, issued commands are converted to the command for erasing the whole flash memory area and the command for erasing all protect bits. chip protect bit flcs if the bit is "1111" romsec1 rom data protect flash d protect function seqmod dsu protect cs_dmac a bus error exception occurs nmi 19a43f during a write of data from areas other than internal rom to the dmac register
tmp19a43 tmp19a43 (rev2.0) 24-5 various protecting functions 24.4 register flash control/status register this register shows the status of flash memory being monitored and the block protect status of flash memory. table 24-2 flash control register 7 6 5 4 3 2 1 0 flcs bit symbol blpro3 blpro2 blpro1 blpro0 romtype rdy/bsy (0xffff_e520) read/write r r r r r after reset by power-on 0 (1) 0 (1) 0 (1) 0 (1) 0 0 (1) 0 1 function protect area setti ng (in units of 128 kb) 0000: all blocks unprotected xxx1: block 0 protected xx1x: block 1 protected x1xx: block 2 protected 1xxx: block 3 protected mask ?1111? "0" is read. rom identification bit 0: flash 1: mrom "0" is read. ready/busy 0: in auto operation 1: auto operation completed (mask:?1?) 15 14 13 12 11 10 9 8 bit symbol read/write r after reset by power-on 0 0 0 0 0 0 0 0 function 23 22 21 20 19 18 17 16 bit symbol read/write r after reset by power-on 0 0 0 0 0 0 0 0 function 31 30 29 28 27 26 25 24 bit symbol read/write r after reset by power-on 0 0 0 0 0 0 0 0 function bit 0: ready/busy flag bit the rdy/bsy output is provided to identify the stat us of auto operation. this bit is a functional bit for monitoring this function by communicating with the cpu. if flash memory is in auto operation, "0" is output to show that flash memory is busy. as flash memory completes auto operation and goes into a ready state, "1" is outp ut and the next command will be accepted. if the result of auto operation is faulty, this bit continues to output "0." it returns to "1" upon a hardware reset. (note) before issuing a command, make sure that flash memory is in a ready state. if a command is issued when flash memory is busy, a right command cannot be generated and there is the possibility that subsequent commands may not be able to be input. in this case, you must return to a normal functional state by executing a system reset or issuing a reset command. bit 2: rom type identification bit this bit is used to identify the type of flash rom or the type of mask rom based on the value after a reset. flash rom: "0" mask rom: "1" bit [7:4]: protect bit (x: a combination setting can be made for each block) the protect bit (4-bit) value corresponds to the protect status of each block. if this bit is "1," the corresponding block is in a protected state. a protected block cannot be overwritten.
tmp19a43 tmp19a43 (rev2.0) 24-6 various protecting functions table 24-3 rom protect register 7 6 5 4 3 2 1 0 romsec1 bit symbol rsecon (0xffff_e518) read/write r r/w after reset by power-on 0 1 function "0" is always read. rom protect 1: on 0: off (see note) 15 14 13 12 11 10 9 8 bit symbol read/write r after reset by power-on 0 function "0" is always read. 23 22 21 20 19 18 17 16 bit symbol read/write r after reset by power-on 0 function 31 30 29 28 27 26 25 24 bit symbol read/write r after reset by power-on 0 function "0" is always read. (note) this register is initialized only by power-on reset in the flash version. the mask version is usually initialized at each reset. (note) to access this register, 32-bit access is required.
tmp19a43 tmp19a43 (rev2.0) 24-7 various protecting functions table 24-4 rom protect lock register 7 6 5 4 3 2 1 0 romsec2 bit symbol (0xffff_e51c) read/write w after reset undefined function see note. 15 14 13 12 11 10 9 8 bit symbol read/write w after reset undefined function see note. 23 22 21 20 19 18 17 16 bit symbol read/write w after reset undefined function see note. 31 30 29 28 27 26 25 24 bit symbol read/write w after reset undefined function see note. (note) if this register is set to "0x0000_003 d" after romsec1 is set, appropriate bit values are automatically set in romsec1. (note) if the rom area is protected, the registers romsec1 and romsec2 can be accessed only by using the instructions residing in the rom area. (note) to access this register, 32-bit access is required. (note) this register is a writ e-only register. if it is r ead, values will be undefined.
tmp19a43 tmp19a43 (rev2.0) 24-8 various protecting functions table 24-5 dsu protect mode register 7 6 5 4 3 2 1 0 seqmod bit symbol dsuoff (0xffff_e510) read/write r r/w after reset 0 1 function "0" is always read. 1: dsu disabled 0: dsu enabled 15 14 13 12 11 10 9 8 bit symbol read/write r after reset 0 function "0" is always read. 23 22 21 20 19 18 17 16 bit symbol read/write r after reset 0 function 31 30 29 28 27 26 25 24 bit symbol read/write r after reset 0 function "0" is always read. (note) this register is initialized only by power-on reset in the flash version. (note) the mask version is usually initialized at each reset. to access this register, 32-bit access is required. table 24-6 dsu protect control register 7 6 5 4 3 2 1 0 seqcnt bit symbol dsecode07 dsecode06 dsecode05 dsecode04 dsecode03 dsecode02 dsecode01 dsecode00 (0xffff_e514) read/write w after reset 0 function write "0x0000_00c5." 15 14 13 12 11 10 9 8 bit symbol dsecode15 dsecode14 dsecode13 dsecode12 dsecode11 dsecode10 dsecode09 dsecode08 read/write w after reset 0 function write "0x0000_00c5." 23 22 21 20 19 18 17 16 bit symbol dsecode23 dsecode22 dsecode21 dsecode20 dsecode19 dsecode18 dsecode17 dsecode16 read/write w after reset 0 function write "0x0000_00c5." 31 30 29 28 27 26 25 24 bit symbol dsecode31 dsecode30 dsecode29 dsecode28 dsecode27 dsecode26 dsecode25 dsecode24 read/write w after reset 0 function write "0x0000_00c5." (note) to access this register, 32-bit access is required. (note) this register is a writ e-only register. if it is r ead, values will be undefined.
tmp19a43 tmp19a43 (rev2.0) 24-9 various protecting functions 24.5 proted-related / release settings if it is necessary to overwrite flash memory or protect bits in a protected state, "automatic protect bit deletion" must be executed or the rom protect function must be disabled. dsu cannot be used if it is in a protected state. flash memory may go into a read-protect ed state after the automatic protect bit program is executed. in this case, it is necessary to set dsu-probe to "enable" before the automatic protect bit program is executed. the mask version is possible only the release of ro m security, and the protecting bit cannot be rewritten. if "automatic protect bit deletion" is executed when flas h memory is in a read-protected state, flash memory is automatically initialized inside this device. therefore, extra caution must be used when switching from one state to a read-protected state. (flash only) 24.5.1 flash protect function the flash protecting function cannot be released always effectively in the mask version. it becomes effective by putting the block protecting on all of the four blocks in the flash version. the flash memory command sequence and protect b it program commands are used to enable or disable the flash read protect function. for further information, refer to the command sequence explained in the chapter describing the operations of flash memory. (notes concerning flash version) the protecting bit is cleared after all the data of the flash is deleted when the protecting bit release command is executed with the flash protected , and the flash protecting is released. in the state of rom data protecting, explains as follows, the command execution to the flash is disregarded. it is necessary to release rom data protecting first clearing the rsecon bit of rom protecting register when the flash prot ecting is released with rom protected.
tmp19a43 tmp19a43 (rev2.0) 24-10 various protecting functions 24.5.2 rom data protect rom data protecting is effective the flash prot ecting and becomes effective at rom protecting register romsec1=?1". after releasing reset, the rsecon bit is initialized by "1". the flash protecting is sure to enter the state of rom data protecting in the mask version after releasing reset because it is always effective. it decides whether to enter the state of rom data pr otecting by the state of the flash protecting in the flash version. when rom protecting register is rewritten with rom data protected, rewriting can be executed only from the program put on built-in rom. theref ore, it is necessary to prepare the release program of rom data protecting on built-in rom. rom data protecting is released by setting rom protecting register romsec1?0" when protecting is released, and writing protecting code ?0x0000_003d" in rom protecting lock register romsec2. moreover, rom data protecting function can be set again by similarly setting rom protecting register romsec1?1" when rom protecting is set, and writing protecting code ?0x0000_003d" in rom protecting lock register romsec2. it is necessary to note the romsec2 register becaus e the reading data is different from original write data because of the register only for writing. the initialization of rom protecting register is diff erent in the flash version and the mask version. it provides with the power-on reset circuit in the fl ash version, rom protecting register is initialized by power-on reset, and the value doesn't usually change in reset. it is usually initialized by reset in the mask version because power-on reset is not provided. it is necessary to note it in the mask versio n because it is usually initialized at each reset. romsec1write romsec1write data clk reset rom p rotection romsec1read data romsec2 = 0x0000_003d it is not possible to access it excluding built-in rom at the time of rom data d q sd dq sd powon reset(flash) resetmask
tmp19a43 tmp19a43 (rev2.0) 24-11 various protecting functions 24.5.3 dsu protect dsu data protecting is effective the flash protecting and becomes effective at dsu protecting register seqmod=?1". after releasing reset, the dsuoff bit is initialized by "1". the flash protecting is sure to enter the state of dsu data protecting in the mask version af ter releasing reset because it is always effective. it decides whether to enter the state of rom data pr otecting by the state of the flash protecting in the flash version. when dsu protecting register is rewritten with ro m data protected, rewriting can be executed only from the program put on built-in rom. theref ore, it is necessary to prepare the release program of dsu data protecting on built-in rom. dsu protecting is released by setting dsu pr otecting register seqmod?0" when protecting is released, and writing protecting code ?0x0000_00c5" in rom protecting lock register seqcnt. moreover, dsu protecting function can be set again by similarly setting rom protecting register seqmod?1" when dsu protecting is set, and writing protecting code ?0x0000_00c5" in dsu protecting lock register seqcnt. it is necessary to note the seqcnt register becaus e the reading data is different from original write data because of the register only for writing. the initialization of dsu protecting register is diff erent in the flash version and the mask version. it provides with the power-on reset circuit in the flash version, dsu protecting register is initialized by power-on reset, and the value doesn't usually change in reset. it is usually initialized by reset in the mask version because power-on reset is not provided. it is necessary to note it in the mask versio n because it is usually initialized at each reset. seqmodwrite seqmodwrite data clk reset dsu p rotection seqmodread data seqcnt = 0x0000_00c5 it is not possible to access it excluding built-in rom at the time of rom data dq sd dq sd powon reset(flash) resetmask flash protection
tmp19a43 tmp19a43 (rev2.0) 24-12 various protecting functions 24.5.4 rom protect register: romsec1 the rom protect register is equipped with a power-on reset circuit. caution must be exercised as data read from the romsec1 bit is differen t from the actually written data. how data is processed is shown below. the mask version is usually initialized by reset though flash goods are initialized by power-on reset. 24.5.5 dsu protect mode register: seqmod the dsu protect mode register is equipped with a power-on reset circuit. caution must be exercised as data read from the seqmod bit is diff erent from the actually written data. how data is processed is shown below. the mask version is usually initialized by reset though flash goods are initialized by power-on reset. seqmod write write data to seqmod clk reset power-on reset dsu protect flash read protect function read data from seqmod dsusec2 = 0x0000_00c5 if the rom is in a protected state, access from areas other than the internal rom is disabled. d q sd dq sd romsec1 write write data to romsec1 clk reset power-on reset rom protect flash read protect function read data from romsec1 romsec2 = 0x0000_003d if the rom is in a protected state, access from areas other than the internal rom is disabled. d q sd dq sd
tmp19a43 tmp19a43 25-1 25. electrical characteristics 25.1 absolute maximum ratings parameter symbol rating unit v cc15 (core) ? 0.3to3.0 vcc3 i/o ? 0.3to3.9 avcc3a/d ? 0.3to3.9 davcc (d/a) ? 0.3to3.5 supply voltage dvcc3 ? 0.3to3.9 v supply voltage v in ? 0.3tov cc + 0.3 v per pin i ol 5 low-level output current total i ol 50 per pin i oh -5 high-level output current total i oh 50 ma power dissipation (ta = 85c) pd 600 mw soldering temperature (10 s) t solder 260 c storage temperature t stg ? 40to125 c exceptduring flash w/e - 20 to 85 operating temperature during flash w/e t opr 0 to 70 c write/erase cycles n ew 100 cycle v cc15 dvcc15 cvcc15 cvcch v cc 3 dvcc3=cvccl v ss dvss avss cvss=dagnd the letter x in equations presented in this chapter repr esents the cycle period of the fsys clock selected through the programming of the syscr1.sysck bit. th e fsys clock may be derived from either the high-speed or low-speed crystal oscillator. the programming of the clock gear function also affects the fsys frequency. all relevant values in this chapter are calculated with the high-speed (fc) system clock (syscr1.sysck = 0) and a cloc k gear factor of 1/fc (syscr1.gear[2:0] = 000). note: absolute maximum ratings are limiting values of operating and environmental conditions which should not be exceeded under the worst possible conditions. the equipment manufacturer should design so that no absolute maximum rating value is exceeded with respect to current, voltage, power dissipation, temperature, etc. exposure to conditions beyond those listed above may cause permanent damage to the device or affect device reliability, which could increase potential risks of personal injury due to ic blowup and/or burning.
tmp19a43 tmp19a43 25-2 25.2 dc electrical characteristics (1/3) ta20 to 85 parameter symbol rating min. typ. (note 1) max. unit dvcc15 cvcch 1.35 1.65 davcc 2.3 2.7 supply voltage avcc3 = 3.3v cvcch dvcc15 dvcc3=cvccl cvss dvss avss=dagnd=0v dvcc3 cvccl fosc = 8to10mhz fs = 30khzto34khz fsys = 15khzto34khz 4mhzto40mhz 2.7 3.6 v p7 to p8 (used as a port) v il1 2.7v Q avcc3 Q 3.6v 0.3 avcc3 normal port v il2 2.7v Q dvcc3 Q 3.6v 0.3 dvcc3 schmitt-triggered port v il3 2.7v Q dvcc3 Q 3.6v 0.2 dvcc3 x1 v il4 1.35v Q cvcc Q 1.65v 0.1 cvcch low-level input voltage xt1 v il5 2.7v Q cvcc Q 3.6v ? 0.3 0.1 cvccl v note 1: ta = 25c, dvcc15=1.5v,dvcc3= avcc3=3.3v,dvcc=2.5v, unless otherwise noted
tmp19a43 tmp19a43 25-3 ta20 to 85 parameter symbol rating min. typ. (note 1) max. unit p7 to p8 (used as a port) normal port v ih1 2.7v Q avcc3 Q 3.6v 0.7 avcc3 normal port v ih2 2.7v Q dvcc3 Q 3.6v 0.7 dvcc3 schmitt-triggered port v ih3 2.7v Q dvcc3 Q 3.6v 0.8 dvcc3 x1 v ih4 1.35v Q cvcch Q 1.65v 0.9 cvcch high-level input voltage xt2 v ih4 2.7v Q cvccl Q 3.6v 0.9 cvccl dvcc3 + 0.3 dvcc15 + 0.2 cvcch + 0.2 cvccl+0.3 v low-level output voltage v ol i ol = 2ma dvcc3 R 2.7v 0.4 high-level output voltage v oh i oh = ? 2ma dvcc3 R 2.7v 2.4 v note 1: ta = 25c, dvcc15=1.5v,dvcc3= avcc3=3.3v,dvcc=2.5v, unless otherwise noted
tmp19a43 tmp19a43 25-4 25.3 dc electrical characteristics (2/3) ta20 to 85 parameter symbol rating min. typ. (note 1) max. unit input leakage current i li 0.0 Q v in Q dvcc15 0.0 Q v in Q dvcc3 0.0 Q v in Q avcc3 0.0 Q v in Q davcc 0.02 5 output leakage current i lo 0.2 Q v in Q dvcc15 ? 0.2 0.2 Q v in Q dvcc3 ? 0.2 0.2 Q v in Q avcc3 ? 0.2 0.2 Q v in Q davcc ? 0.2 0.05 10 a pull-up resister at reset rrst dvcc3 = 2.7vto3.6v 20 50 150 k schmitt-triggered port vth 2.7v Q dvcc3 Q 3.6v 0.3 0.6 v programmable pull-up/ pull-down resistor pkh dvcc3 = 2.7v to3.6v 20 50 150 k pin capacitance (except power supply pins) c io fc = 1mhz 10 pf note 1: ta = 25c, dvcc15=1.5v,dvcc3= avcc3=3.3v,dvcc=2.5v, unless otherwise noted
tmp19a43 tmp19a43 25-5 25.4 dc electrical characteristics (3/3) dvcc15 cvcch 1.35vto1.65v, cvccl= dvcc3 avcc3 2.7vto3.6v, davcc=2.3vto2.7v ta 20 to 85 parameter symbol rating min. typ. (note 1) max. unit normal (note 2): gear = 1/1 50 74 idle(doze) (note 3) 20 29 idle(halt) (note 3) f sys = 40 mhz ( f osc = 10 mhz) 18 28 ma slow (note 4) fs = 32.768khz 140 995 a sleep (note 4) fs = 32.768khz 30 985 a stop i cc 27 980 a note 1: ta = 25c, dvcc15=1.5v,dvcc3= avcc3=3.3v,dvcc=2.5v, unless otherwise noted (note1) i cc normal: measured with the cpu dhrystone operati ng ( dsu is excluded.), ram, flash. all functions operating. d/a and a/d excluded. (note2) i cc idle : measured with all functions stoping. (note3) i cc slow sleep : measured with rtc on low-speed i cc the current where flows is included. dvcc15 dvcc3 cvcch cvccl avcc3 davcc
tmp19a43 tmp19a43 25-6 25.5 10-bit adc electrical characteristics dvcc15 cvcch 1.35vto1.65v, cvccl= dvcc3 avcc3 vrefh 2.7vto3.6v, davcc=2.3vto2.7v,avss = dvss ,ta 20 to 85 avcc3 load capacitanc = 3.3f, vrefh load capacitanc = 3.3f parameter symbol rating min typ max unit analog reference voltage ( + ) vrefh 2.7 3.3 3.6 v analog reference voltage ( ? ) vrefl avss avss avss v analog input voltage vain vrefl vrefh v a/d conversion dvss = avss = vrefl 4.5 5.5 ma analog supply current non-a/d conversion iref dvss = avss = vrefl 0.02 5 a supply current a/d conversion ? non-iref 3 ma inl error 2 3 dnl error 1 2 offset error 2 4 fullscale error ? ain resistance Q 600 ain load capacitance Q 30pf conversion time R 1.15 s 2 4 inl error 2 3 dnl error 1 2 offset error 2 4 fullscale error ? ain resistance Q 600 ain load capacitance R 0.1 f conversion time R 1.15 s 2 4 inl error 2 3 dnl error 1 2 offset error 2 4 fullscale error ? ain resistance Q 1.3k ain load capacitance R 0.1 f conversion time R 1.15 s 2 4 inl error 2 3 dnl error 1 2 offset error 2 4 fullscale error ? ain resistance Q 10k ain load capacitance R 0.1 f conversion time R 2.30 s 2 4 lsb (note 1) 1lsb = (vrefh ? vrefl) / 1024[v]
tmp19a43 tmp19a43 25-7 25.6 8bit d/a electrical characteristics dvcc15 cvcch 1.35v to 1.65v, cvccl= dvcc3 avcc3 2.7v to 3.6v, davcc=2.3v to 2.7v parameter symbol rating min typ max unit analog reference voltage ( + ) davref 2.3 2.5 2.7 v = 1 n=0,1 1 2 ma analog supply current = 0 n=0,1 idref 0.02 5 a supply current icc 5 ma output current ida0 ida1 1 ma range of output voltage da0 da1 dagnd 0.3 davcc 0.3 v fullscale error ? 2 3 lsb (note 1) 1lsb = (davref ? dagnd) / 256[v] (note 2) idref current valu is in the dual channel operation . (note 3) no guarantee about relative ac curacy in the dual channel operation (note 4) load maximum capacitance of each dax pin is 100pf.
tmp19a43 tmp19a43 25-8 25.7 ac electrical characteristics 25.7.1 multiplex bus mode (1) dvcc15 cvcc15 1.35vto1.65v, avcc3 = 2.7vto3.6v dvcc3 2.7vto3.6v davcc = 2.3vto2.7v,ta = 20to85 c ale width = 1 clock cycle, 2 programmed wait state equation 40 mhz (fsys) (note) no. parameter symbol min max min max unit 1 system clock period (x) t sys 25 ns 2 a0-a15 valid to ale low t al x ?11 14.0 ns 3 a0-a15 hold after ale low t la x ? 8 17.0 ns 4 ale pulse width high t ll x ? 6 19.0 ns 5 ale low to rd , wr or hwr asserted t lc x ? 8 17.0 ns 6 rd , wr or hwr negated to ale high t cl x ? 8 17.0 ns 7 a0-a15 valid to rd , wr or hwr asserted t acl 2x ? 11 39.0 ns 8 a16-a23 valid to rd , wr or hwr asserted t ach 2x ? 11 39.0 ns 9 a16-a23 hold after rd , wr or hwr negated t car x ? 11 14.0 ns 10 a0-a15 valid to d0-d15 data in t adl x (2 + tw+ale) ? 43 82.0 ns 11 a16-a23 valid to d0-d15 data in t adh x (2 + tw+ale) ? 43 82.0 ns 12 rd asserted to d0-d15 data in t rd x (1 + tw) ? 40 35.0 ns 13 rd width low t rr x (1 + tw) ? 6 69 ns 14 d0-d15 hold after rd negated t hr 0 0 ns 15 rd negated to next a0-a15 output t rae x ? 6 19.0 ns 16 wr / hwr width low t ww x (1 + tw) ? 6 69.0 ns 17 d0-d15 valid to wr or hwr negated t dw x (1 + tw) ? 11 64.0 ns 18 d0-d15 hold after wr or hwr negated t wd x ? 11 14.0 ns 19 a16-a23 valid to wait input t awh x+ x (ale) (tw- 1) 32 43.0 ns 20 a0-a15 valid to wait input t awl x+ x (ale) (tw- 1) 32 43.0 ns 21 wait hold after rd , wr or hwr asserted t cw (tw - 3)-16 (tw ? 1) ? 29 9.0 46.0 ns note 1: no. 1 to 21 internal 2 wait insertion ale 1 clock @40mhz tw = w + 2n , w : number of auto wait insertion , 2n : number of external wait insertion tw = 2 + 2 * 1 = 4 ac measurement conditions: output levels: high = 0.8dvcc3 v/low 0.2dvcc3 v, cl = 30 pf input levels: high = 0.7dvcc3 v/low 0.3dvcc3 v
tmp19a43 tmp19a43 25-9 ale width = 1 clock cycles, 2 programmed wait state equation 40 mhz (fsys) (note) no. parameter symb ol min max min max unit 1 system clock period (x) t sys 25 ns 2 a0-a15 valid to ale low t al x ?11 14.0 ns 3 a0-a15 hold after ale low t la x ? 8 17.0 ns 4 ale pulse width high t ll x ? 6 19.0 ns 5 ale low to rd , wr or hwr asserted t lc x ? 8 17.0 ns 6 rd , wr or hwr negated to ale high t cl x ? 8 17.0 ns 7 a0-a15 valid to rd , wr or hwr asserted t acl 2x ? 11 39.0 ns 8 a16-a23 valid to rd , wr or hwr asserted t ach 2x ? 11 39.0 ns 9 a16-a23 hold after rd , wr or hwr negated t car x ? 11 14.0 ns 10 a0-a15 valid to d0-d15 data in t adl x (2 + tw+ale) ? 43 82.0 ns 11 a16-a23 valid to d0-d15 data in t adh x (2 + tw+ale) ? 43 82.0 ns 12 rd asserted to d0-d15 data in t rd x (1 + tw) ? 40 35.0 ns 13 rd width low t rr x (1 + tw) ? 6 69 ns 14 d0-d15 hold after rd negated t hr 0 0 ns 15 rd negated to next a0-a15 output t rae x ? 6 19.0 ns 16 wr / hwr width low t ww x (1 + tw) ? 6 69.0 ns 17 d0-d15 valid to wr or hwr negated t dw x (1 + tw) ? 11 64.0 ns 18 d0-d15 hold after wr or hwr negated t wd x ? 11 14.0 ns 19 a16-a23 valid to wait input t awh x+ x (ale) (tw- 1) 32 43.0 ns 20 a0-a15 valid to wait input t awl x+ x (ale) (tw- 1) 32 43.0 ns 21 wait hold after rd , wr or hwr asserted t cw (tw - 3)-16 (tw ? 1) ? 29 9.0 46.0 ns note 1: no. 1 to 21 internal 2 wait insertion ale 1 clock @40mhz tw = w + 2n , w : number of auto wait insertion , 2n : number of external wait insertion tw = 2 + 2 * 1 = 4 ac measurement conditions: output levels: high = 0.8dvcc3 v/low 0.2dvcc3 v, cl = 30 pf input levels: high = 0.7dvcc3 v/low 0.3dvcc3 v
tmp19a43 tmp19a43 25-10 (1) read cycle timing, ale width = 1 cl ock cycle, 1 programmed wait state t car t rr t hr t adh t adl t la d0 15 t al t cl t ll ale internalclk ad0~15 rd a0 15 t acl t ach t lc t rd a16~23 5clk/1bus cycle s1i s2 s3 s1 w1 t rae cs0~3 r/w s1 s2 s0 s1i sw
tmp19a43 tmp19a43 25-11 (2) read cycle timing, ale width = 1 cl ock cycle, 2 programmed wait state t car t rr t hr t adh t adl t la d0 15 t al t cl t ll ale internalcl k ad0~1 5 rd a0 15 t acl t ach t lc t rd a16~2 3 6clk/1bus cycle t rae cs0~3 r/w
tmp19a43 tmp19a43 25-12 (3) read cycle timing, ale width = 1 cl ock cycle, 4 programmed wait state t awl/h ale internalclk ad0~15 rd ad16~23 8clk/1bus cycle wait d0 15 a0 15 t cw cs0~3 r/w
tmp19a43 tmp19a43 25-13 (4) read cycle timing, ale width = 2 cl ock cycle, 1 programmed wait state t rr t hr t adh t adl t la d0 15 t al t cl t ll ale internalclk ad0~15 rd s1i s1x sw s2 s0 a0 15 t acl t ach t lc t rd a16~23 6clk/1bus cycle s1 t rae cs0~3 r/w s1i
tmp19a43 tmp19a43 25-14 (5) read cycle timing, ale width = 2 cl ock cycle, 4 programmed wait state t awl/h ale internalclk ad0~15 rd ad16~23 9clk/1bus cycle wait d0 15 s1x s1 sw swex s0 a0 15 sw t cw cs0~3 r/w sw s2 s1x
tmp19a43 tmp19a43 25-15 (6) write cycle timing, ale width = 2 clock cycles, zero wait state t ww t car t dw t la d0 15 t al t cl t ll ale internalclk ad0~15 wr, hwr cs0~3 r/w a0 15 t acl t ach t lc ad16~23 5clk/1bus cycle t wd
tmp19a43 tmp19a43 25-16 (7) write cycle timing, ale width = 1 clock cycles, 2 wait state t ww t car t dw t la d0 15 t al t cl t ll ale internalcl k ad0~1 5 wr, hwr cs0~3 r/ w a0 15 t acl t ach t lc ad16~2 3 6clk/1bus cycle t wd
tmp19a43 tmp19a43 25-17 (8) write cycle timing, ale width = 2 clock cycles, 4 wait state ale internalclk ad0~1 5 wr, hwr cs0~3 r/w ad16~2 3 9clk/1bus cycle t ww t car t dw t la d0 15 t al t cl t ll a0 15 t acl t ach t lc t wd wait t cw t awl/h
tmp19a43 tmp19a43 25-18 25.7.2 separate bus mode (1) dvcc15 cvcch 1.35vto1.65v, dvcc3 avcc3 = 2.7vto3.6v, davcc =2.3 vto2.7v, ta = 20 to 85 c syscr3 = ?0?, 2 programmed wait state equation 40 mhz (fsys) (note) no. parameter symb ol min max min max unit 1 system clock period (x) t sys 25 ns 2 a0-a23 valid to rd , wr or hwr asserted t ac x(1 ale) ? 11 39.0 ns 3 a0-a23 hold after rd , wr or hwr negated t car x ? 11 14.0 ns 4 a0-a23 valid to d0-d15 data in t ad x (2 + tw+ale) ? 43 82.0 ns 5 rd asserted to d0-d15 data in t rd x (1 + tw) ? 40 35.0 ns 6 rd width low t rr x (1 + tw) ?6 69.0 ns 7 d0-d15 hold after rd negated t hr 0 0 ns 8 rd negated to next a0-a23 output t rae x ? 6 19.0 ns 9 wr /hwr width low t ww x (1 + tw) ?6 69.0 ns 10 wr or hwr asserted to d0-d15 valid t do 9.7 9.7 ns 11 d0-d15 hold after wr or hwr negated t dw x (1 + tw) ? 11 64.0 ns 12 d0-d15 hold after wr or hwr negated t wd x ? 11 14.0 ns 13 a0-a23 valid to wait input t aw x+ x (ale) (tw- 1) 32 43.0 ns 14 wait hold after rd , wr or hwr asserted t cw (tw - 3)-16 (tw ? 1) ? 29 9.0 46.0 ns note 1: no. 1 to 14 internal 2 wait insertion ale 1 clock @40mhz tw = w + 2n , w : number of auto wait insertion , 2n : number of external wait insertion tw = 2 + 2 * 1 = 4 ac measurement conditions: output levels: high = 0.8dvcc3 v/low 0.2dvcc3 v, cl = 30 pf input levels: high = 0.7dvcc3 v/low 0.3dvcc3 v
tmp19a43 tmp19a43 25-19 (1) read cycle timing (syscr3 = 0, 1 programmed wait state) t car t rr t hr t ad internalclk rd t ac t rd a0~23 4clk/1bus cycle s1 s2 s0 s1 sw d0 15 d0~15 t rae cs0~3 r/w
tmp19a43 tmp19a43 25-20 (2) read cycle timing (syscr3 = 1, 1 programmed wait state) t car t rr t hr t ad t ad internalclk rd s1i s1 s2 s0 s1i d0 15 d0~15 t ac t rd a16~23 5clk/1bus cycle sw t rae cs0~3 r/w
tmp19a43 tmp19a43 25-21 (3)read cycle timing syscr3 = 1, 4 externally generated wait states with n = 1) t aw internalclk rd a0~23 8clk/1bus cycle wait d0~15 d0 15 s1 sw swe sw s2 sw t cw cs0~3 r/w s1i s0
tmp19a43 tmp19a43 25-22 (4) write cycle timing (syscr3 = 1, zero wait sate) t ww t car t dw internalclk wr, hwr cs0~3 r/w t ac a0~23 4clk/1bus cycle t wd d0 15 d0~15 t do
tmp19a43 tmp19a43 25-23 (5) write cycle timing ( syscr3 =1, 4 wait state ) t ww t car t dw internalclk wr, hwr cs0~3 r/w t ac a0~23 4clk/1bus cycle t wd d0 15 d0~15 t do wait
tmp19a43 tmp19a43 25-24 (6) write cycle timing ( syscr3 = 1, 5 wait state ) t ww t car t dw internalclk wr, hwr cs0~3 r/w t ac a0~23 4clk/1bus cycle t wd d0 15 d0~15 t do wait
tmp19a43 tmp19a43 25-25 25.8 transfer with dma request the following shows an example of a transfer between the on-chip ram an d an external device in multiplex bus mode. ? 16-bit data bus width, non-recovery time ? level data transfer mode ? transfer size of 16 bits, devi ce port size (dps) of 16 bits ? source/destination: on-chip ram/external device the following shows transfer operation timing of th e on-chip ram to an external bus during write operation (memory-to-memory transfer). gclkin dreqn a le hwr lwr a d[15:0] n transfer (n-1) transfer (n+1) transfe cs tdreq_w tdreq_w r/w a dd a dd a dd data data data gack 2clk 2clk ??? gbstart tdreq_r tdreq_r (1) indicates the condition under which nth transfer is performed successfully. (2) indicates the condition under which (n + 1)th transfer is not performed. internal
tmp19a43 tmp19a43 25-26 dvcc15 cvcch 1.35vto1.65v, dvcc3 avcc3 = 2.7vto3.6v, davcc =2.3 vto2.7v, ta = 20to85 c equation 40 mhz (fsys) unit parameter symbol min max min max rd asserted to dreqn negated (external device to on-chip ram transfer) tdreq_r w+1x 2wale8x 51 50 224 ns wr / hwr rising to dreqn negated (on-chip ram to external device transfer) tdreq_w -(w+2)x 5+waitx51.8 -75 98.2 ns
tmp19a43 tmp19a43 25-27 25.9 serial channel timing (1) i/o interface mode dvcc32.7vto3.6v in the table below, the letter x represents the fsys cycle period, which varies depending on the programming of the clock gear function. sclk input mode sio0 to sio2 equation 40 mhz parameter sym bol min max min max unit sclk period tscy 12x 300 ns sclk clock high width(input) tsch 6x 150 ns sclk clock low width (input) tscl 6x 150 ns txd data to sclk rise or fall* toss 2x-30 20 ns txd data hold after sclk rise or fall* tohs 8x-15 185 ns rxd data valid to sclk rise or fall* tsrd 30 30 ns rxd data hold after sclk rise or fall* thsr 2x+30 80 ns * sclk rise or fall: measured relative to the programmed active edge of sclk. sclk output mode sio0 to sio2 equation 40 mhz parameter sym bol min max min max unit sclk period tscy 8x 200 ns txd data to sclk rise or fall* toss 4x-10 90 ns txd data hold after sclk rise or fall* tohs 4x-10 90 ns rxd data valid to sclk rise or fall* tsrd 45 45 ns rxd data hold after sclk rise or fall* thsr 0 0 ns output data txd input data rxd sclk sck output mode/ active-high scl input mod 0 valid t oss t scy t ohs 1 2 3 t srd t hsr 0 1 2 3 valid valid valid sclk active-low sck input mode
tmp19a43 tmp19a43 25-28 25.10 high speed serial channel timing (1) i/o interface mode dvcc32.7v to 3.6v in the table below, the letter x represents the fsys cycle period, which varies depending on the programming of the clock gear function. hsclk input mode hsio0 to hsio2 equation 40 mhz parameter sym bol min max min max unit hsclk period tscy 12(x/2) 150 ns hsclk clock high width(input) tsch 3x 75 ns hsclk clock low width (input) tscl 3x 75 ns txd data to hsclk rise or fall* toss 2(x/2)-30 -5 ns txd data hold after hsclk rise or fall* tohs 8(x/2)-15 85 ns rxd data valid to hsclk rise or fall* tsrd 30 30 ns rxd data hold after hsclk rise or fall* thsr 2(x/2)+30 55 ns * hsclk rise or fall: measured relative to the programmed active edge of hsclk. hsclk output mode hsio0 to hsio2 equation 40 mhz parameter sym bol min max min max unit hsclk period tscy 8(x/2) 100 ns txd data to hsclk rise or fall* toss 4(x/2)-10 40 ns txd data hold after hsclk rise or fall* tohs 4(x/2)-10 40 ns rxd data valid to hsclk rise or fall* tsrd 45 45 ns rxd data hold after hsclk rise or fall* thsr 0 0 ns output data txd input data rxd sclk sck output mode/ active-high scl input mod 0 valid t oss t scy t ohs 1 2 3 t srd t hsr 0 1 2 3 valid valid valid sclk active-low sck input mode
tmp19a43 tmp19a43 25-29 25.11 sbi timing (1) i2c mode in the table below, the letters x repr esent the fsys periods, respectively. n denotes the value of n programmed into the sck (scl output frequency select) field in the sbi0cr. equation standard mode fast mode parameter symbol min max min max min max unit scl clock frequency tsc 0 0 100 0 400 khz hold time for start condition thd:sta 4.0 0.6 s scl clock low width (input) (note 1) tlow 4.7 1.3 s scl clock high width (output) (note 2) thigh 4.0 0.6 s setup time for a repeated start condition tsu;sta (note 5) 4.7 0.6 s data hold time (input) (note 3, 4) thd;dat 0.0 0.0 s data setup time tsu;dat 250 100 ns setup time for stop condition tsu;sto 4.0 0.6 s bus free time between stop and start conditions tbuf (note 5) 4.7 1.3 s note 1: scl clock low width (output) is calculated with : (2 n-1 +58)/(fsys/2) note 2: scl clock high width (output) is calculated with (2 n-1 +12)/(fsys/2) note 3: the output data hold time is equal to 12x note 4: the philips i 2 c-bus specification states that a device must internally provide a hold time of at least 300 ns for the sda signal to bridge the undefined regi on of the fall edge of scl. however, this sbi does not satisfy this requirement. also, the ou tput buffer for scl does not incorporate slope control of the falling edges; therefore, the equipmen t manufacturer should design so that the input data hold time shown in the table is satisfied, including tr/tf of the scl and sda lines. note 5: software-dependent sda scl t low t hd;sta t scl t high t r t su;dat t hd;dat t su;sta t su;sto t buf s: start condition sr: repeated start condition p: stop condition t f s sr p notice: on i 2 c-bus specification, maximum speed of standard mode is 100khz ,fast mode is 400khz. internal scl clock frequency setti ng should be shown above note1 & note2.
tmp19a43 tmp19a43 25-30 (2) clock-synchronous 8-bit sio mode in the tables below, the letters x represent the fsys cycle periods, respectively. the letter n denotes the value of n programmed into the sck (scl output frequency select) field in the sbi0cr1. the electrical specifications below are for an sck signal with a 50% duty cycle. sck input mode equation 40 mhz parameter symb ol min max min max unit sck period tscy 16x 400 ns sck clock high width(input) tsch 8x 200 ns sckclock low width(input) tsch 8x 200 ns so data to sck rise toss (tscy/2) ? (6x + 20) 30 ns so data hold after sck rise tohs (tscy/2) + 4x 300 ns si data valid to sck rise tsrd 0 0 ns si data hold after sck rise thsr 4x + 10 110 ns sck output mode equation 40 mhz parameter symb ol min max min max unit sck period (programmable) t scy 2 n ? t 800 ns so data to sck rise t oss (t scy /2) ? 20 380 ns so data hold after sck rise t ohs (t scy /2) ? 20 t380 ns si data valid to sck rise t srd 2x + 30 55 ns si data hold after sck rise t hsr 0 0 ns output data txd input data txd sclk 0 valid t oss t scy t ohs 1 2 3 t srd t hsr 0 1 2 3 valid valid valid t sch t scl
tmp19a43 tmp19a43 25-31 25.12 event counter in the table below, the letter x represents the fsys cycle period. equation 40 mhz parameter symbol min max min max unit clock low pulse width t vckl 2x + 100 150 ns clock high pulse width t vckh 2x + 100 150 ns 25.13 timer capture in the table below, the letter x represents the fsys cycle period. equation 40 mhz parameter symbol min max min max unit low pulse width t cpl 2x + 100 150 ns high pulse width t cph 2x + 100 150 ns 25.14 general interrupts in the table below, the letter x represents the fsys cycle period. equation 40 mhz parameter symbol min max min max unit low pulse width for int0-inta t intal x + 100 125 ns high pulse width for int0-inta t intah x + 100 125 ns 25.15 stop /sleep/slow wake-up interrupts equation 40 mhz parameter symbol min max min max unit low pulse width for int0-intb t intbl 100 100 ns high pulse width for int0-intb t intbh 100 100 ns 25.16 scout pin equation 40 mhz parameter symbol min max min max unit clock high pulse width t sch 0.5t ? 5 7.5 ns clock low pulse width t scl 0.5t ? 5 7.5 ns note: in the above table, the letter t represents the cycle period of t he scout output clock. t sch t scl scout
tmp19a43 tmp19a43 25-32 25.17 bus request and bus acknowledge signals t aba (note1) busrq a le a 0~a23, rd , wr busak cs0 ~ cs3 , w / r, hwr a d0~ad15 t baa (note2) (note2) equation 40 mhz parameter symbol min max min max unit bus float to busak asserted t aba 0 80 0 80 ns bus float after busak negated t baa 0 80 0 80 ns note 1: if the current bus cycle has not te rminated due to wait-state insertion, the tmp19a43fdxbg does not respond to busrq until the wait state ends. note 2: this broken line indicates that output buffers are disabled, not that the signals are at indeterminate states. the pin holds t he last logic value present at that pin before the bus is relinquished. this is dy namically accomplished through external load capacitances. the equipment manufacturer may maintain the bus at a predefined state by means of off-chip re stores, but he or she should design, considering the time (determined by the cr constant) it takes for a signal to reach a desired state. the on-chip, integrated programmable pullup/pulldown resistors remain active, depending on internal signal states.
tmp19a43 tmp19a43 25-33 25.18 kwup input equation 40 mhz parameter symbol min max min max unit low pulse width for key tky tbl 100 100 ns high pulse width for key tky tbh 100 100 ns 25.19 dual pulse input equation 40 mhz parameter symbol min max min max unit dual input pulse period tdcyc 8y 400 ns dual input pulse setup tabs y 20 70 ns dual input pulse hold tabh y 20 70 ns y : fsys/ a b 25.20 adtrg input equation 40 mhz parameter symbol min max min max unit low pulse width for adtrg tad l fsys/2 20 32.5 ns high pulse width for adtrg tadh fsys/2 20 32.5 ns tabs tabh tdc y c
tmp19a43 tmp19a43 25-34 25.21 dsu equation 40 mhz parameter symbol min max min max unit pcst valid to dclk negated tsetup 11 11 ns pcst hold after dclk negated thold 0.5 0.5 ns tpc valid to dclk negated tsetup 11 11 ns tpc hold after dclk negated thold 0.5 0.5 ns tpd valid to dclk negated tsetup 11 11 ns tpd hold after dclk negated thold 0.5 0.5 ns output data pcst,tpc,tpd dclk 0 t setup t tclk t hold 1 2 3 25.22 ejtag equation 10 mhz() parameter symbol min max min max unit tck valid to tms/tdi data in ttsetup 40 40 ns tms/tdi hold after tck negated tthold 50 50 ns tdo hold after tck asserted tt out 10 10 ns operating frequency of tck is 10mhz only input data tms,tdi tck valid t tclk t tsetup t thold 0 1 2 3 valid valid valid output data tdo t tout