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december 2011 doc id 10397 rev 19 1/44 1 M41T62, m41t63 m41t64, m41t65 serial real-time clocks (rtcs) with alarm features serial real-time clock (rtc) with alarm functions ? 400 khz i 2 c serial interface ? memory mapped registers for seconds, minutes, hours, day, date, month, year, and century ? tenths/hundredths of seconds register 350 na timekeeping current at 3 v timekeeping down to 1.0 v 1.3 v to 4.4 v i 2 c bus operating voltage ? 4.4 v max v cc suitable for lithium-ion battery operation low operating current of 35 a (at 400 khz) 32 khz square wave output is on at power-up. suitable for driving a microcontroller in low- power mode. can be disabled. (M41T62/63/64) programmable 1 hz to 32 khz square wave output (M41T62/63/64) programmable alarm with interrupt function (M41T62/65) 32 khz crystal oscillator integrates crystal load capacitors, works with high series resistance crystals oscillator stop detect ion monitors clock operation accurate programmable watchdog ? 62.5 ms to 31 min timeout software clock calibration. can adjust timekeeping to withi n 2 parts per million ( 5 seconds per month) automatic leap year compensation ?40 to +85 c operation two package options: ? very small 3 mm x 3 mm, lead-free & halogen-free (ecopack2 ? ) 16-lead qfn ? ultra-small 1.5 mm x 3.2 mm, lead-free & halogen-free (ecopack2 ? ) 8-pin ceramic leadless chip carrier with embedded 32 khz crystal - no external oscillator components required (M41T62) 3mm 3mm 3.2 mm 1.5 mm qfn16 3 mm x 3 mm embedded crystal lcc8 1.5 mm x 3.2 mm no external components required table 1. device summary basic rtc alarms osc fail detect watchdog timer calibration sqw output irq output wdo output f 32k output M41T62 ?? ? ? ? ?? m41t63 (1) ?? ? ? ? ? ? m41t64 ?? ? ? ? ? ? m41t65 ?? ? ? ? ?? 1. contact local st sales office for availability. www.st.com
contents M41T62/63/64/65 2/44 doc id 10397 rev 19 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.1 bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.2 start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.3 stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.4 data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.5 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 rtc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5 watchdog output (wdo - m41t63/65 only) . . . . . . . . . . . . . . . . . . . . . . . 27 3.6 square wave output (M41T62/63/64) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.7 full-time 32 khz square wave output (m41t64) . . . . . . . . . . . . . . . . . . . 28 3.8 century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.9 output driver pin (M41T62/65) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.10 oscillator stop detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.11 initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
M41T62/63/64/65 contents doc id 10397 rev 19 3/44 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
list of tables M41T62/63/64/65 4/44 doc id 10397 rev 19 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. M41T62 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 4. m41t63 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 5. m41t64 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6. m41t65 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 7. alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 8. square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 9. initial power-on default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 10. century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 11. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 12. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 13. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 14. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 15. crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 16. crystals suitable for use with m41t6x series rtcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 17. oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 18. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 19. qfn16 ? 16-pin, quad, flat package, no-lead, 3 mm x 3 mm body size, mechanical data. 37 table 20. lcc8 ? 8-pin, 1.5 mm x 3.2 mm leadless chip carrier, mechanical data . . . . . . . . . . . . . 39 table 21. carrier tape dimensions for qfn16 3 mm x 3 mm package. . . . . . . . . . . . . . . . . . . . . . . . 40 table 22. reel dimensions for 12 mm carrier tape - qfn16 and lcc8 packages. . . . . . . . . . . . . . . 41 table 23. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 24. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
M41T62/63/64/65 list of figures doc id 10397 rev 19 5/44 list of figures figure 1. M41T62 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. m41t63 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. m41t64 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. m41t65 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. M41T62 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 6. m41t63 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 7. m41t64 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 8. m41t65 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 9. M41T62 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 10. m41t63 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 11. m41t64 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 12. m41t65 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 13. hardware hookup for supercap? backup operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 14. serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 15. acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 16. slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 17. read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 18. alternative read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 figure 19. write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 20. buffer/transfer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 21. crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 22. calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 23. alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 24. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 25. crystal isolation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 26. bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 27. qfn16 ? 16-pin, quad, flat package, no-lead, 3 mm x 3 mm body size, outline . . . . . . . . 37 figure 28. qfn16 ? 16-pin, quad, flat package, no-lead, 3 x 3 mm, recommended footprint . . . . . . . 38 figure 29. lcc8 ? 8-pin, 1.5 mm x 3.2 mm leadless chip carrier, outline . . . . . . . . . . . . . . . . . . . . . 38 figure 30. lcc8 ? 8-pin, 1.5 mm x 3.2 mm leadless chip carrier, recommended footprint . . . . . . . . 39 figure 31. carrier tape for qfn16 3 mm x 3 mm package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 32. carrier tape for lcc8 1.5 mm x 3.2 mm package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 33. reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
description M41T62/63/64/65 6/44 doc id 10397 rev 19 1 description the m41t6x is a low-power serial real-time cl ock (rtc) with a built-in 32.768 khz oscillator. eight registers are used for the clock/calendar function and are configured in binary coded decimal (bcd) format. an additional 8 regist ers provide status/control of alarm, 32 khz output, calibration, and watchdog functions. addresses and data are transferred serially via a two line, bidirectional i 2 c interface. the built-in address register is incremented automatically after each write or read data byte. functions available to the user include a time-of-day clock/calendar, alarm interrupts (M41T62/65), 32 khz output (M41T62/63/64), programmable square wave output (M41T62/63/64), and watchdog output (m41t63/65). the eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 hour bcd format. corrections for 28-, 29- (leap year), 30- and 31-day months are made automatically. the m41t6x is supplied in two very small packages: a tiny, 3 mm x 3 mm 16-pin qfn which requires a user-supplied 32 khz crystal, and an ultra-small 1.5 mm x 3.2 mm lcc with embedded crystal - no external crystal is required. figure 1. M41T62 logic diagram 1. open drain. 2. defaults to 32 khz on power-up. 3. not bonded on lcc package. scl v cc M41T62 v ss sda irq/out (1) sqw (2) xi (3) xo (3) ai09103
M41T62/63/64/65 description doc id 10397 rev 19 7/44 figure 2. m41t63 logic diagram 1. open drain. 2. defaults to 32 khz on power-up. figure 3. m41t64 logic diagram 1. open drain. 2. defaults to 32 khz on power-up. figure 4. m41t65 logic diagram 1. open drain. scl v cc m41t63 v ss sda wdo (1) sqw (2) xi xo ai09189 scl v cc m41t64 v ss sda f 32k (2) sqw (1) xi xo ai09108 scl v cc m41t65 v ss sda wdo (1) irq/ft/out (1) xi xo ai09109
description M41T62/63/64/65 8/44 doc id 10397 rev 19 figure 5. M41T62 connections 1. sqw output defaults to 32 khz upon power-up. 2. open drain. figure 6. m41t63 connections 1. sqw output defaults to 32 khz upon power-up. 2. open drain. figure 7. m41t64 connections 1. enabled on power-up. 2. open drain. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc nc nc nc nc nc xi xo sqw (1) v ss v ss v cc nc scl sda irq/out (2) ai09100 1 2 3 4 5 6 7 8 v ss nc scl sda irq/out (2) nc v cc qfn lcc sqw (1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc nc nc nc nc nc xi xo sqw (1) v ss v ss v cc nc scl sda wdo (2) ai09190 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc nc nc nc nc nc xi xo f 32k (1) v ss v ss v cc nc scl sda sqw (2) ai09101
M41T62/63/64/65 description doc id 10397 rev 19 9/44 figure 8. m41t65 connections 1. open drain. figure 9. M41T62 block diagram 1. open drain. 2. defaults to 32 khz on power-up. 3. not bonded on embedded crystal (lcc) package. table 2. signal names xi oscillator input xo oscillator output sda serial data input/output scl serial clock input irq /out interrupt or out output (open drain) irq /ft/out interrupt, frequency test , or out output (open drain) sqw programmable square wave - defaults to 32 khz on power-up (open drain for m41t64 only) f 32k dedicated 32 khz output (m41t64 only) wdo watchdog timer output (open drain) v cc supply voltage v ss ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc nc nc nc nc nc xi xo wdo (1) v ss v ss v cc nc scl sda irq/ft/out (1) ai09102 real time clock calendar rtc w/alarm oscillator fail detect square wave watchdog irq/out (1) sqw (2) ofie sda scl afe sqwe i 2 c interface 32khz oscillator xtal ai08899a (3) (3)
description M41T62/63/64/65 10/44 doc id 10397 rev 19 figure 10. m41t63 block diagram 1. open drain. 2. defaults to 32 khz on power-up. figure 11. m41t64 block diagram 1. defaults enabled on power-up. 2. open drain. figure 12. m41t65 block diagram 1. open drain. real time clock calendar rtc w/alarm oscillator fail detect square wave watchdog sqw (2) wdo (1) sda scl sqwe i 2 c interface 32khz oscillator xtal ai09191 real time clock calendar rtc w/alarm oscillator fail detect square wave watchdog sqw (2) f 32k (1) 32ke sda scl sqwe i 2 c interface 32khz oscillator xtal ai09192 real time clock calendar rtc w/alarm oscillator fail detect watchdog irq/ft/out (1) wdo (1) ofie sda scl ft afe i 2 c interface 32khz oscillator xtal ai09193
M41T62/63/64/65 description doc id 10397 rev 19 11/44 figure 13. hardware hookup for supercap? backup operation 1. diode required on open drain pin (m 41t65 only) for supercap (or battery) backup. low threshold bat42 diode recommended. 2. for M41T62 and m41t65 (open drain). 3. for m41t63 and m41t65 (open drain). 4. for m41t64 (open drain). ai10400b v cc port reset input sqwin serial clock line serial data line 32khz clkin xo xi m41t6x mcu v ss irq/ft/out (2) wdo (3) sqw (4) f 32k sda scl v cc v cc (1)
operation M41T62/63/64/65 12/44 doc id 10397 rev 19 2 operation the m41t6x clock operates as a slave device on the serial bus. access is obtained by implementing a start condition followed by the correct slave address (d0h). the 16 bytes contained in the device can then be accessed sequentially in the following order: 1 st byte: tenths/hundredths of a second register 2 nd byte: seconds register 3 rd byte: minutes register 4 th byte: hours register 5 th byte: square wave/day register 6 th byte: date register 7 th byte: century/month register 8 th byte: year register 9 th byte: calibration register 10 th byte: watchdog register 11 th - 15 th bytes: alarm registers 16th byte: flags register 2.1 2-wire bus characteristics the bus is intended for communication between di fferent ics. it consists of two lines: a bi- directional data signal (sda) and a clock signal (scl). both the sda and scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line, while the clock lin e is high, will be interpreted as control signals. accordingly, the following bus conditions have been defined: 2.1.1 bus not busy both data and clock lines remain high. 2.1.2 start data transfer a change in the state of the data line, from high to low, while the clock is high, defines the start condition. 2.1.3 stop data transfer a change in the state of the data line, from low to high, while the clock is high, defines the stop condition.
M41T62/63/64/65 operation doc id 10397 rev 19 13/44 2.1.4 data valid the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start co ndition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowledges with a ninth bit. by definition a device that gives out a message is called ?transmitter,? the receiving device that gets the message is called ?receiver.? th e device that controls the message is called ?master.? the devices that are controlled by the master are called ?slaves.? 2.1.5 acknowledge each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case the transmitter must leave the data line high to enable the master to generate the stop condition. figure 14. serial bus data transfer sequence ai005 8 7 data clock data line s table data valid s ta rt condition change of data allowed s top condition
operation M41T62/63/64/65 14/44 doc id 10397 rev 19 figure 15. acknowledgement sequence 2.2 read mode in this mode the master reads the m41t6x slave after setting the slave address (see figure 17 on page 15 ). following the write mode control bit (r/w =0) and the acknowledge bit, the word address 'an' is written to the on-chip address pointer. next the start condition and slave address are repeated followed by the read mode control bit (r/w =1). at this point the master transmitter becomes the master receiver. the data byte which was addressed will be tr ansmitted and the master rece iver will send an acknowledge bit to the slave transmitter. the address pointer is only incremented on reception of an acknowledge clock. the m41t6x slave transmi tter will now place the data byte at address an+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to ?an+2.? this cycle of reading consecutive addresses will continue until the mast er receiver sends a stop condition to the slave transmitter. the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resume due to a stop condition or when the pointer increments to any non-clock address (08h-0fh). note: this is true both in read mode and write mode. an alternate read mode may also be implemented whereby the master reads the m41t6x slave without first writing to the (volatile) address pointer. the first address that is read is the last one stored in the pointer (see figure 18 on page 15 ). figure 16. slave address location ai00601 data output by receiver data output by transmitter scl from master start clock pulse for acknowledgement 12 89 msb lsb ai00602 r/w s lave addre ss s ta rt a 01000 11 m s b l s b
M41T62/63/64/65 operation doc id 10397 rev 19 15/44 figure 17. read mode sequence figure 18. alternative read mode sequence ai00899 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address s start r/w slave address ack ai00 8 95 bu s activity: ack s ack ack ack no ack s top s ta rt p s da line bu s activity: ma s ter r/w data n data n+1 data n+x s lave addre ss
operation M41T62/63/64/65 16/44 doc id 10397 rev 19 2.3 write mode in this mode the master transmitter transmits to the m41t6x slave receiver. bus protocol is shown in figure 19 on page 16 . following the start condition and slave address, a logic '0' (r/w =0) is placed on the bus and indicates to the addressed device that word address ?an? will follow and is to be written to the on-chip add ress pointer. th e data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. the m41t6x slave receiver will send an acknowledge clock to the master transm itter after it has received the slave address see figure 16 on page 14 and again after it has received the word address and each data byte. figure 19. write mode sequence ai00591 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address
M41T62/63/64/65 clock operation doc id 10397 rev 19 17/44 3 clock operation the m41t6x is driven by a quartz-controlled oscillator with a nominal frequency of 32.768 khz. the accuracy of the real-time clock depends on the frequency of the quartz crystal that is used as the time-base for the rtc. the eight byte clock register (see table 3: M41T62 register map , table 4: m41t63 register map , table 5: m41t64 register map , and table 6: m41t65 register map ) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. a write to any clock register will result in the tenths/hundredths of seconds being reset to ?00,? and tenths/hundredths of seconds cannot be written to any value other than ?00.? bits d0 through d2 of register 04h contain the day (day of week). registers 05h, 06h, and 07h contain the date (day of month), month, and years. the ninth clock register is the calibration register (this is described in the clock calibration section). bit d7 of register 01h contains the stop bit (st). setting this bit to a '1' will cause the oscillator to stop. when reset to a '0' the oscillator rest arts within one second (typical). upon initial power-up, the user should set the st bit to a '1,' then immediately reset the st bit to '0.' this provides an additional ?kick-start? to the oscillator circuit. bit d7 of register 02h (minute register) contains the oscillator fail interrupt enable bit (ofie). when the user sets this bit to '1,' any conditi on which sets the oscillator fail bit (of) (see oscillator stop detection on page 29 ) will also generate an interrupt output. bits d6 and d7 of clock register 06h (century/month register) contain the century bit 0 (cb0) and century bit 1 (cb1). a write to any location within the first eight bytes of the clock register (00h-07h), including the ofie bit, rs0-rs3 bit, and cb0-cb1 bits will result in an update of the system clock and a reset of the divider chain. this could result in an inadvertent change of the current time. these non-clock related bits should be written prior to setting the clock, and remain unchanged until such time as a new clock time is also written. the eight clock registers may be read one byte at a time, or in a sequential block. provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. if a clock address is being read, an update of the clock registers will be halted. this will prevent a trans ition of data during the read.
clock operation M41T62/63/64/65 18/44 doc id 10397 rev 19 3.1 rtc registers the m41t6x user interface is comprised of 16 memory mapped registers which include clock, calibration, alarm, watchdog, flags, and square wave control. the eight clock counters are accessed indirectly via a set of buffer/transfer registers while the other eight registers are directly accessed. data in the clock and alarm registers is in bcd format. figure 20. buffer/transfer registers updates during normal operation when the user is not accessing the device, the buffer/transfer registers are kept updated with a copy of the rtc counters. at the start of an i 2 c read or write cycle, the updating is halted and the present time is frozen in the buffer/transfer registers. reads of the clock registers by halting the updates at the start of an i 2 c access, the user is ensured that all the data transferred out during a read sequence comes from the same instant in time. 32khz osc divide by 32768 1 hz read / write buffer tran s fer regi s ter s i 2 c i 2 c interface centuries years months date day-of-week hours minutes seconds counter counter counter counter counter counter counter counter 2 clock counter s are acce ss ed indirectly thru buffer/tran s fer regi s ter s flags non-clock registers calibration watchdog non-clock regi s ter s are directly acce ss ed data tran s ferred out of i 2 c interface on 8 th falling edge of s cl (on write s ) on write s , data tran s ferred from buffer s to counter s when addre ss pointer increment s to 8 or when i 2 c s top condition i s received at s tart of read, udate s from counter s are halted and pre s ent time i s frozen in buffer/tran s fer regi s ter s . am04 8 90v1
M41T62/63/64/65 clock operation doc id 10397 rev 19 19/44 write timing when writing to the device, the data is shifted into the M41T62's i 2 c interface on the rising edge of the scl signal. as shown in figure 20 , on the 8th clock cycle, the data is transferred from the i 2 c block into whichever register is being pointed to by the address pointer (not shown). writes to the clock registers (addresses 0-7) data written to the clock registers (addresses 0-7) is held in the buffer registers until the address pointer increments to 8, or an i 2 c stop condition occurs, at which time the data in the buffer/registers is simultaneously copied into the counters, and then the clock is re- started.
clock operation M41T62/63/64/65 20/44 doc id 10397 rev 19 keys: 0 = must be set to '0' af = alarm flag (read only) afe = alarm flag enable flag bmb0 - bmb4 = watchdog multiplier bits cb0-cb1 = century bits of = oscillator fail bit ofie = oscillator fail interrupt enable bit out = output level rb0 - rb2 = watchdog resolution bits rpt1-rpt5 = alarm repeat mode bits rs0-rs3 = sqw frequency bits s = sign bit sqwe = square wave enable bit st = stop bit wdf = watchdog flag bit (read only) table 3. M41T62 register map addr function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds 10ths/100ths of seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h ofie 10 minutes minutes minutes 00-59 03h 0 0 10 hours hours (24-hour format) hours 00-23 04h rs3 rs2 rs1 rs0 0 day of week day 01-7 05h 0 0 10 date date: day of month date 01-31 06h cb1 cb0 0 10m month century/ month 0-3/01-12 07h 10 years year year 00-99 08h out 0 s calibration calibration 09h rb2 bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 0ah afe sqwe 0 al 10m alarm month al month 01-12 0bh rpt4 rpt5 ai 10 date alarm date al date 01-31 0ch rpt3 0 ai 10 hour alarm hour al hour 00-23 0dh rpt2 alarm 10 minutes alarm minutes al min 00-59 0eh rpt1 alarm 10 seconds alarm seconds al sec 00-59 0fh wdf af 0 0 0 of 0 0 flags
M41T62/63/64/65 clock operation doc id 10397 rev 19 21/44 keys: 0 = must be set to '0' af = alarm flag (read only) bmb0 - bmb4 = watchdog multiplier bits cb0-cb1 = century bits of = oscillat or fail bit rb0 - rb2 = watchdog resolution bits rpt1-rpt5 = alarm repeat mode bits rs0-rs3 = sqw frequency bits s = sign bit sqwe = square wave enable bit st = stop bit wdf = watchdog flag bit (read only) table 4. m41t63 register map addr function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds 10ths/100ths of seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h 0 10 minutes minutes minutes 00-59 03h 0 0 10 hours hours (24-hour format) hours 00-23 04h rs3 rs2 rs1 rs0 0 day of week day 01-7 05h 0 0 10 date date: day of month date 01-31 06h cb1 cb0 0 10m month century/ month 0-3/01-12 07h 10 years year year 00-99 08h 0 0 s calibration calibration 09h rb2 bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 0ah 0 sqwe 0 al 10m alarm month al month 01-12 0bh rpt4 rpt5 ai 10 date alarm date al date 01-31 0ch rpt3 0 ai 10 hour alarm hour al hour 00-23 0dh rpt2 alarm 10 minutes alarm minutes al min 00-59 0eh rpt1 alarm 10 seconds alarm seconds al sec 00-59 0fh wdf af 0 0 0 of 0 0 flags
clock operation M41T62/63/64/65 22/44 doc id 10397 rev 19 keys: 0 = must be set to '0' 32ke = 32 khz enable bit af = alarm flag (read only) bmb0 - bmb4 = watchdog multiplier bits cb0-cb1 = century bits of = oscillat or fail bit rb0 - rb2 = watchdog resolution bits rpt1-rpt5 = alarm repeat mode bits rs0-rs3 = sqw frequency bits s = sign bit sqwe = square wave enable bit st = stop bit wdf = watchdog flag bit (read only) table 5. m41t64 register map addr function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds 10ths/100ths of seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h 0 10 minutes minutes minutes 00-59 03h 0 0 10 hours hours (24-hour format) hours 00-23 04h rs3 rs2 rs1 rs0 0 day of week day 01-7 05h 0 0 10 date date: day of month date 01-31 06h cb1 cb0 0 10m month century/ month 0-3/01-12 07h 10 years year year 00-99 08h 0 0 s calibration calibration 09h rb2 bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 0ah 0 sqwe 32ke al 10m alarm month al month 01-12 0bh rpt4 rpt5 ai 10 date alarm date al date 01-31 0ch rpt3 0 ai 10 hour alarm hour al hour 00-23 0dh rpt2 alarm 10 minutes alarm minutes al min 00-59 0eh rpt1 alarm 10 seconds alarm seconds al sec 00-59 0fh wdf af 0 0 0 of 0 0 flags
M41T62/63/64/65 clock operation doc id 10397 rev 19 23/44 keys: 0 = must be set to '0' af = alarm flag (read only) afe = alarm flag enable flag bmb0 - bmb4 = watchdog multiplier bits cb0-cb1 = century bits ft = frequency test bit of = oscillat or fail bit ofie = oscillator fa il interrupt enable bit out = output level rb0 - rb2 = watchdog resolution bits rpt1-rpt5 = alarm repeat mode bits s = sign bit st = stop bit wdf = watchdog flag bit (read only) table 6. m41t65 register map addr function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds 10ths/100ths of seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h ofie 10 minutes minutes minutes 00-59 03h 0 0 10 hours hours (24-hour format) hours 00-23 04h 0 0 0 0 0 day of week day 01-7 05h 0 0 10 date date: day of month date 01-31 06h cb1 cb0 0 10m month century/ month 0-3/01-12 07h 10 years year year 00-99 08h out ft s calibration calibration 09h rb2 bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 0ah afe 0 0 al 10m alarm month al month 01-12 0bh rpt4 rpt5 ai 10 date alarm date al date 01-31 0ch rpt3 0 ai 10 hour alarm hour al hour 00-23 0dh rpt2 alarm 10 minutes alarm minutes al min 00-59 0eh rpt1 alarm 10 seconds alarm seconds al sec 00-59 0fh wdf af 0 0 0 of 0 0 flags
clock operation M41T62/63/64/65 24/44 doc id 10397 rev 19 3.2 calibrating the clock the m41t6x real-time clock is driven by a quartz controlled oscillator with a nominal frequency of 32,768 hz. this provides the time-base for the rtc. the accuracy of the clock depends on the frequency accuracy of the crystal, and the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. the m41t6x oscillator is designed for use with a 6 - 7 pf crystal load c apacitance. when the calibration circuit is properly employed, accuracy improves to better than 2 ppm at 25 c. the oscillation rate of crystals changes with temperature (see figure 21 on page 25 ). therefore, the m41t6x design employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circui t at the divide by 256 stage, as shown in figure 22 on page 25 . the number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the calibration register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration bits occupy the five lower order bits (d4-d0) in the calibration register (08h). these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 1 28 or lengthened by 2 56 oscillator cycles. if a binary '1' is loaded into the register, only th e first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 ac tual oscillator cycles, that is +4.068 or ?2.034 ppm of adjustment per calibration step in the calibration register. assuming that the oscillator is running at exactly 32,768 hz, ea ch of the 31 increments in the calibration byte would represent +10.7 or ?5.35 seconds per day which corresponds to a total range of +5.5 or ?2.75 minutes per month (see figure 22 on page 25 ). two methods are available for ascertaining how much calibration a given m41t6x may require: the first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. calibration values, including the number of seconds lost or gained in a given period, can be found in application note an934, ?how to use the digital calibration feature in timekeeper ? and serial real-time clock (rtc) products.? this allows the designer to give the end user the ability to calibrate the clock as the enviro nment requires, even if the final product is packaged in a non-user serviceable enclosure. the designer could provide a simple utility that accesses th e calibration byte. the second approach is better suited to a manufacturing environment, and involves the use of either the sqw pin (M41T62/63/64) or the irq /ft/out pin (m41t65). the sqw pin will toggle at 512 hz when rs3 = '0,' rs2 = '1,' rs1 = '1,' rs0 = '0,' sq we = '1,' and st = '0.' alternatively, for the m41t65, the irq /ft/out pin will toggle at 512 hz when ft and out bits = '1' and st = '0.' any deviation from 512 hz indicates the degree and direction of oscilla tor frequency shift at the test temperature. for example, a reading of 512.010124 hz would indicate a +20 ppm oscillator frequency erro r, requiring a ?10 (xx001010) to be loaded into the ca libration byte for correction. note that setting or changing the calibration byte does not affect the frequency test or square wave output frequency.
M41T62/63/64/65 clock operation doc id 10397 rev 19 25/44 figure 21. crystal accuracy across temperature figure 22. calibration waveform ai07888 ?160 0 10203040506070 frequency (ppm) temperature c 80 ?10 ?20 ?30 ?40 ?100 ?120 ?140 ?40 ?60 ?80 20 0 ?20 = ?0.036 ppm/ c 2 0.006 ppm/ c 2 k f = k x (t ? t o ) 2 f t o = 25 c 5 c ai00594 b normal po s itive calibration negative calibration
clock operation M41T62/63/64/65 26/44 doc id 10397 rev 19 3.3 setting alarm clock registers address locations 0ah-0eh contain the alarm settings. the alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. bits rpt5?rpt1 put the alarm in the repeat mode of operation. table 7 on page 26 shows the possible configurations. codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. when the clock information matches the alarm clock settings based on the match criteria defined by rpt5?rpt1, the af (alarm flag) is set. if afe (alarm flag enable) is also set (M41T62/65), the alarm condition activates the irq /out or irq /ft/out pin. to disable the alarm, write '0' to the alarm date register and to rpt5?rpt1. note: if the address pointer is allowed to increment to the flag register address, an alarm condition will not cause the interrupt/flag to occur until the address poin ter is moved to a different address. it should also be noted that if the last address written is the ?alarm seconds,? the address pointer will incr ement to the flag address, ca using this situation to occur. the irq output is cleared by a read to the flags register as shown in figure 23 on page 26 . a subsequent read of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' figure 23. alarm interrupt reset waveform table 7. alarm repeat modes rpt5 rpt4 rpt3 rpt2 rpt1 alarm setting 1 1 1 1 1 once per second 1 1 1 1 0 once per minute 1 1 1 0 0 once per hour 1 1 0 0 0 once per day 1 0 0 0 0 once per month 0 0 0 0 0 once per year alarm flag bit (af) 0fh 0eh 00h high-z ai08898 irq/out or irq/ft/out register address
M41T62/63/64/65 clock operation doc id 10397 rev 19 27/44 3.4 watchdog timer the watchdog timer can be used to detect an out-of-control microprocessor. the user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. bits bmb4-bmb0 store a binary multiplier and the three bits rb2-rb0 select the resolution where: 000=1/16 second (16 hz); 001=1/4 second (4 hz); 010=1 second (1 hz); 011=4 seconds (1/4 hz); and 100 = 1 minute (1/60 hz). note: invalid combinations (101 , 110, and 111) will not enable a watchdog time-out. setting bmb4-bmb0 = 00000 with any comb ination of rb2-rb0, other th an 000, will result in an immediate watchdog time-out. the amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (for example: writing 00001110 in the watchdog register = 3*1 or 3 seconds). if the processor does not reset the timer within the specified period, the m41t6x sets the wdf (watchdog flag) and generates an interrupt on the irq pin (M41T62), or a watchdog output pulse (m41t63 and m41t65 only) on the wdo pin. the watchdog timer can only be reset by having the microprocessor perform a write of the watchdog register. the time-out period then starts over. should the watchdog timer time-out, any value may be written to the watchdog register in order to clear the irq pin. a value of 00h will disable the wa tchdog function until it is again programmed to a new value. a read of the fl ags register will reset the watchdog flag (bit d7; register 0fh). the watchdog function is automatically disabled upon power-up, and the watchdog register is cleared. note: a write to any clock register will restart the watchdog timer. 3.5 watchdog output (wdo - m41t63/65 only) if the processor does not reset the watchdog timer within the specified period, the watchdog output (wdo ) will pulse low for t rec (see table 18 on page 35 ). this output may be connected to the reset input of the processor in order to generate a processor reset. after a watchdog time-out occurs, th e timer will remain disabled until such time as a new countdown value is written into the watchdog register. note: the crystal oscillator must be running for the wdo pulse to be available. the wdo output is an n-channel, open drain output driver (with i ol as specified in table 14 on page 33 ).
clock operation M41T62/63/64/65 28/44 doc id 10397 rev 19 3.6 square wave output (M41T62/63/64) the M41T62/63/64 offers the user a programmable square wave function which is output on the sqw pin. rs3-rs0 bits located in 04h establish the square wave output frequency. these frequencies are listed in ta b l e 8 . once the selection of the sqw frequency has been completed, the sqw pin can be turned on and off under software control with the square wave enable bit (sqwe) located in register 0ah. the sqw output is an n-channel, open drain output driver for the m41t64, and a full cmos output driver for the M41T62/63. the initial power-up default for the sqw output is 32 khz (except for m41t64, which defaults disabled). 3.7 full-time 32 khz square wave output (m41t64) the m41t64 offers the user a special 32 kh z square wave function which is enabled on power-up to output on the f 32k pin as long as v cc 1.3 v, and the oscillator is running (st bit = '0'). this function is available withi n one second (typ) of initial power-up and can only be disabled by setting the 32ke bit to '0' or the st bit to '1.' if not used, the f 32k pin should be disconnected and allowed to float. table 8. square wave output frequency square wave bits square wave rs3 rs2 rs1 rs0 frequency units 0000none? 000132.768khz 00108.192khz 00114.096khz 01002.048khz 01011.024khz 0110512hz 0111256hz 1000128hz 100164hz 101032hz 101116hz 11008hz 11014hz 11102hz 11111hz
M41T62/63/64/65 clock operation doc id 10397 rev 19 29/44 3.8 century bits these two bits will increment in a binary fashio n at the turn of the century, and handle all leap years correctly. see table 10 on page 30 for additional explanation. 3.9 output driver pin (M41T62/65) when the ofie bit, afe bit, and watchdog register are not set to generate an interrupt, the irq /out pin becomes an output driver that reflects the contents of d7 of the calibration register. in other words, when d7 (out bit) is a '0,' then the irq /out pin will be driven low. note: the irq /out pin is an open drain which requires an external pull-up resistor. 3.10 oscillator stop detection if the oscillator fail (of) bit is internally set to a '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time and can be used to judge the validity of the clock and date data. this bit will be set to '1' any time the oscillator stops. in the event the of bit is found to be set to '1' at any time other than the initial power-up, the stop bit (st) should be written to a '1,' then im mediately reset to '0.' this will restart the oscillator. the following conditions can cause the of bit to be set: the first time power is applied (defaults to a '1' on power-up). note: if the of bit cannot be written to '0' four (4) seconds after the initial power-up, the stop bit (st) should be written to a '1,' then immediately reset to '0.' the voltage present on v cc or battery is insufficie nt to support oscillation. the st bit is set to '1.' external interference of the crystal if the oscillator fail interrupt enable bi t (ofie) is set to a '1,' the irq pin will also be activated. the irq output is cleared by resetting the ofie or of bit to '0' (not by reading the flag register). the of bit will remain set to '1' until written to logic '0.' the oscillator must start and have run for at least 4 seconds before attempting to reset the of bit to '0.' if the trigger event occurs during a power-down condit ion, this bit will be set correctly.
clock operation M41T62/63/64/65 30/44 doc id 10397 rev 19 3.11 initial power-on defaults upon application of power to the device, the regi ster bits will initially power-on in the state indicated in ta b l e 9 . table 9. initial power-on default values condition device st of ofie out ft afe sqwe 32ke rs3-1 rs0 watchdog initial power-up (1) 1. all other control bits power up in an undetermined state. M41T62 0 1 0 1 n/a 0 1 n/a 0 1 0 m41t63 0 1 n/a n/a n/a n/a 1 n/a 0 1 0 m41t64 0 1 n/a n/a n/a n/a 0 1 0 1 0 m41t65 0 1 0 1 0 0 n/a n/a n/a n/a 0 table 10. century bits examples cb0 cb1 leap year? example (1) 1. leap year occurs every four years (f or years evenly divisible by four), except for y ears evenly divisible by 100. the only exceptions are those years evenly divisible by 400 (the y ear 2000 was a leap year, year 2100 is not). 00yes2000 0 1 no 2100 1 0 no 2200 1 1 no 2300
M41T62/63/64/65 maximum ratings doc id 10397 rev 19 31/44 4 maximum ratings stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. table 11. absolute maximum ratings sym parameter conditions (1) 1. test conforms to jedec standard. value (2) 2. data based on characterization results, not tested in production. unit t stg storage temperature (v cc off, oscillator off) ?55 to 125 c v cc supply voltage ?0.3 to 5.0 v t sld (3) 3. reflow at peak temperature of 260 c. the time above 255 c must not exceed 30 seconds. lead solder temperature for 10 seconds 260 c v io input or output voltages ?0.2 to vcc+0.3 v i o output current 20 ma p d power dissipation 1 w v esd(hbm) electro-static discharge voltage (human body model) t a = 25 c >1500 v v esd(rcdm) electro-static discharge voltage (robotic charged device model) t a = 25 c >1000 v
dc and ac parameters M41T62/63/64/65 32/44 doc id 10397 rev 19 5 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. figure 24. ac measurement i/o waveform figure 25. crystal isolation example note: substrate pad should be tied to v ss . table 12. operating and ac measurement conditions (1) 1. output hi-z is defined as the point where data is no longer driven. parameter m41t6x supply voltage (v cc ) 1.3 v to 4.4 v ambient operating temperature (t a ) ?40 to 85 c load capacitance (c l ) 50 pf input rise and fall times 5 ns input pulse voltages 0.2 v cc to 0.8 v cc input and output timing ref. voltages 0.3 v cc to 0.7 v cc ai0256 8 0. 8 v cc 0.2v cc 0.7v cc 0. 3 v cc ai09127 crystal xi xo gnd local grounding plane (layer 2)
M41T62/63/64/65 dc and ac parameters doc id 10397 rev 19 33/44 table 13. capacitance symbol parameter (1)(2) 1. effective capacitance m easured with power supply at 3.6 v; sampled only, not 100% tested. 2. at 25c, f = 1 mhz. min max unit c in input capacitance - 7 pf c out (3) 3. outputs deselected. output capacitance - 10 pf t lp low-pass filter input time constant (sda and scl) - 50 ns table 14. dc characteristics sym parameter test condition (1) 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 1.3 v to 4.4 v (except where noted). min typ max unit v cc (2) 2. oscillator startup guaranteed at 1.5 v only. operating voltage clock 1.0 4.4 v i 2 c bus (400 khz) 1.3 4.4 v i cc1 supply current scl = 400 khz (no load) 4.4 v 100 a 3.6 v 50 70 a 3.0 v 35 a 2.5 v 30 a 2.0 v 20 a i cc2 supply current (standby) scl = 0 hz all inputs v cc ? 0.2 v v ss + 0.2 v sqw off 4.4 v 950 na 3.6 v 375 700 na 3.0 v at 25 c 350 na 2.0 v at 25 c 310 na v il input low voltage ?0.2 0.3 v cc v v ih input high voltage 0.7 v cc v cc +0.3 v v ol output low voltage v cc = 4.4 v, i ol = 3.0 ma (sda) 0.4 v v cc = 4.4 v, i ol = 1.0 ma (sqw, wdo , irq ) 0.4 v v oh output high voltage v cc = 4.4 v, i oh = ?1.0 ma (push-pull) 2.4 v pull-up supply voltage (open drain) irq /out, irq /ft/out, wdo , sqw (m41t64 only) 4.4 v i li input leakage current 0 v v in v cc 1 a i lo output leakage current 0 v v out v cc 1 a
dc and ac parameters M41T62/63/64/65 34/44 doc id 10397 rev 19 table 15. crystal electrical characteristics sym parameter (1)(2) min typ max units f o resonant frequency - 32.768 khz r s series resistance (t a = ?40 to 70 c, oscillator startup at 2.0 v) - 75 (3)(4) k c l load capacitance - 6 pf 1. for the qfn16 package, user-supplied external crystals are required. the 6 and 7 pf crystals listed in table 16 below have been evaluated by st and have been found to be sati sfactory for use with the m41t6x series rtc. 2. load capacitors are integrated within t he m41t6x. circuit board lay out considerations for the 32.768 khz crystal of minimum trace lengths and isolation from rf generating signals should be taken into account. 3. guaranteed by design. 4. r s (max) = 65 k for t a = ?40 to 85 c and oscillator startup at 1.5 v. table 16. crystals suitable for use with m41t6x series rtcs vendor order number package manufacturer?s specifications esr max temp. range (c) rated tolerance at 25 c rated load cap. citizen cmj206t-32.768kdzb-ub 8.3 x 2.5 mm leaded smt 50 k ?40/+85 20 ppm 6 pf citizen cm315-32.768kdzy-ub 3.2 x 1.5 x 0.9 mm smt 70 k ?40/+85 20 ppm 7 pf ecliptek e4wcda06-32.768k 2.0 x 6.0 mm thru-hole 50 k ?10/+60 20 ppm 6 pf ecliptek e5wsdc 07 - 32.768k 7 x 1.5 x 1.4 mm smt 65 k ?40/+85 20 ppm 7 pf ecs ecs-.327-6-17x-tr 3.8 x 8.5 x 2.5 mm smt 50 k ?40/+85 20 ppm 6 pf ecs ecs-.327-7-34b-tr 3.2 x 1.5 x 0.9 mm smt 70 k ?40/+85 20 ppm 7 pf ecs ecs-.327-7-38-tr 7 x 1.5 x 1.4 mm smt 65 k ?40/+85 20 ppm 7 pf epson mc-146 32.7680ka-ag: rohs (1) 7 x 1.5 x 1.4 mm smt 65 k ?40/+85 20 ppm 7 pf fox 298lf-0.032768-19 1.5 x 5.0 mm thru-hole 50 k ?20/+60 20 ppm 6 pf fox 299lf-0.032768-37 2.0 x 6.0 mm thru-hole 50 k ?20/+60 20 ppm 6 pf fox 414lf-0.032768-12 3.8 x 8.5 x 2.5 mm smt 50 k ?40/+85 20 ppm 6 pf fox 501lf-0.032768-5 7 x 1.5 x 1.4 mm smt 65 k ?40/+85 20 ppm 7 pf micro crystal ms3v-t1r 32.768khz 7pf 20ppm 6.7 x 1.4 mm leaded smt 65 k ?40/+85 20 ppm 7 pf pletronics sm20s - 32.768k - 6pf 3.8 x 8.5 x 2.5 mm smt 50 k ?40/+85 20 ppm 6 pf seiko sspt7f-7pf20ppm 7 x 1.5 x 1.4 mm smt 65 k ?40/+85 20 ppm 7 pf seiko vt200f-6pf20ppm 2.0 x 6.0 mm thru-hole 50 k ?10/+60 20 ppm 6 pf 1. epson mc-146 32.7680ka-e: rohs is 6 pf version.
M41T62/63/64/65 dc and ac parameters doc id 10397 rev 19 35/44 table 17. oscillator characteristics figure 26. bus timing requirements sequence table 18. ac characteristics symbol parameter conditions min typ max unit v sta oscillator start voltage 10 seconds 1.5 v t sta oscillator start time v cc = 3.0 v 1 s c g xin capacitance 12 pf c d xout capacitance 12 pf ic-to-ic frequency variation (1)(2) 1. reference value. t a = 25 c, v cc = 3.0 v, cmj-145 (c l = 6 pf, 32,768 hz) manufactured by citizen, c l = c g ? c d / (c g + c d ). 2. devices in lcc8 package ((M41T62lc6f) are tested not to exceed 20 ppm oscillator frequency error at 25 c, which equates to about 52 seconds per month. ?10 +10 ppm sym parameter (1) 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 1.3 to 4.4 v (except where noted). min max units f scl scl clock frequency 0 400 khz t low clock low period 1.3 s t high clock high period 600 ns t r sda and scl rise time 300 ns t f sda and scl fall time 300 ns t hd:sta start condition hold time (after this period the first clock pulse is generated) 600 ns t su:sta start condition setup time (only relevant for a repeated start condition) 600 ns t su:dat (2) 2. transmitter must internally provi de a hold time to bridge the undefined re gion (300 ns max) of the falling edge of scl. data setup time 100 ns t hd:dat data hold time 0 s t su:sto stop condition setup time 600 ns t buf time the bus must be free before a new transmission can start 1.3 s t rec watchdog output pulse width 96 98 ms ai005 8 9 s da p t s u: s to t s u: s ta t hd: s ta s r s cl t s u:dat t f t hd:dat t r t high t low t hd: s ta t buf s p
package mechanical information M41T62/63/64/65 36/44 doc id 10397 rev 19 6 package mechanical information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
M41T62/63/64/65 package mechanical information doc id 10397 rev 19 37/44 figure 27. qfn16 ? 16-pin, quad, flat package, no-lead, 3 mm x 3 mm body size, outline note: drawing is not to scale. table 19. qfn16 ? 16-pin, quad, flat package, no-lead, 3 mm x 3 mm body size, mechanical data a3 a a1 e k k b ch d2 e2 l e d 1 2 ddd 3 qfn16-a c symb mm inches typ min max typ min max a 0.90 0.80 1.00 0.035 0.032 0.039 a1 0.02 0.00 0.05 0.001 0.000 0.002 a3 0.20 ? ? 0.008 ? ? b 0.25 0.18 0.30 0.010 0.007 0.012 d 3.00 2.90 3.10 0.118 0.114 0.122 d2 1.70 1.55 1.80 0.067 0.061 0.071 e 3.00 2.90 3.10 0.118 0.114 0.122 e2 1.70 1.55 1.80 0.067 0.061 0.071 e0.50? ?0.020? ? k0.20? ?0.008? ? l 0.40 0.30 0.50 0.016 0.012 0.020 ddd ? 0.08 ? ? 0.003 ? ch ? 0.33 ? ? 0.013 ? n16 16
package mechanical information M41T62/63/64/65 38/44 doc id 10397 rev 19 figure 28. qfn16 ? 16-pin, quad, flat package, no-lead, 3 x 3 mm, recommended footprint note: dimensions shown are in millimeters (mm). figure 29. lcc8 ? 8-pin, 1.5 mm x 3.2 mm leadless chip carrier, outline 0.28 1.60 3.55 2.0 ai09126 8 241725_a top view b ottom view s ide view
M41T62/63/64/65 package mechanical information doc id 10397 rev 19 39/44 table 20. lcc8 ? 8-pin, 1.5 mm x 3.2 mm leadless chip carrier, mechanical data figure 30. lcc8 ? 8-pin, 1.5 mm x 3.2 mm leadless chip carrier, recommended footprint note: dimensions shown are typica l values, in millimeters (mm). symb mm inches typ min max typ min max a0.800.031 b 0.30 0.40 0.50 0.012 0.016 0.020 d 1.40 1.50 1.60 0.055 0.059 0.063 d1 0.40 0.50 0.60 0.016 0.020 0.024 e 3.10 3.20 3.30 0.122 0.126 0.130 e1 2.20 2.30 2.40 0.087 0.091 0.094 e 0.90 0.035 l 0.32 0.42 0.52 0.013 0.017 0.020 n8 8 0.9 0.9 0.9 0.5 0. 8 0. 8 0.4 2.0 3 .2
package mechanical information M41T62/63/64/65 40/44 doc id 10397 rev 19 figure 31. carrier tape for qfn16 3 mm x 3 mm package figure 32. carrier tape for lcc8 1.5 mm x 3.2 mm package note: dimensions shown are in millimeters (mm). t k 0 p 1 a 0 b 0 p 2 p 0 center line s of cavity w e f d top cover tape u s er direction of feed am0 3 07 3 v1 table 21. carrier tape dimensions for qfn16 3 mm x 3 mm package package w d e p 0 p 2 fa 0 b 0 k 0 p 1 tunit bulk qty qfn16 12.00 0.30 1.50 + 0.10 /-0.00 1.75 0.10 4.00 0.10 2.00 0.10 5.50 0.05 3.30 0.10 3.30 0.10 1.10 0.10 8.00 0.10 0.30 0.05 mm 3000 7604 7604 0.1 0.2 1.75 12 1. 5 0 .1 0.1 0. 1 0.05 0.1 0.02 0.1 0.1 3.45 4 0.1 2 ? 1. 5 ? 5.5 0.3 1.75 4 user direction of feed
M41T62/63/64/65 package mechanical information doc id 10397 rev 19 41/44 figure 33. reel schematic note: the dimensions given in ta b l e 2 2 incorporate tolerances that cover all variations on critical parameters. a d b f u ll r a di us t a pe s lot in core for t a pe s t a rt 2.5mm min.width g me asu red at h ub c n 40mm min. acce ss hole at s lot loc a tion t am0492 8 v1 table 22. reel dimensions for 12 mm carrier tape - qfn16 and lcc8 packages package a (max) b (min) c d (min) n (min) g t (max) qfn16 330 mm (13-inch) 1.5 mm 13 mm 0.2 mm 20.2 mm 60 mm 12.4 mm + 2/?0 mm 18.4 mm lcc8 180 mm (7-inch) 1.5 mm 13 mm 0.2 mm 20.2 mm 60 mm 12.4 mm + 2/?0 mm 18.4 mm
part numbering M41T62/63/64/65 42/44 doc id 10397 rev 19 7 part numbering table 23. ordering information scheme for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: m41t 62 q 6 f device family m41t device type and supply voltage 62 = v cc = 1.3 v to 4.4 v 63 (1) = v cc = 1.3 v to 4.4 v 1. contact the st sales office for availability. 64 = v cc = 1.3 v to 4.4 v 65 = v cc = 1.3 v to 4.4 v package q = qfn16 (3 mm x 3 mm) lc = lcc8 (1.5 mm x 3.2 mm) (M41T62 only) temperature range 6 = ?40 c to 85 c shipping method f = ecopack ? package, tape & reel
M41T62/63/64/65 revision history doc id 10397 rev 19 43/44 8 revision history table 24. document revision history date revision changes 26-jan-2010 12 minor textual changes; updated section 3.2 ; footnote 3 in ta b l e 1 1 ; footnote 1 in ta b l e 1 5 ; text in section 6 ; ta b l e 1 6 , 18 . 07-may-2010 13 updated title of datasheet, features , section 1 , section 3.1 , 3.2 , 3.4 , 3.10 , section 4 , figure 23 , ta b l e 1 6 ; added figure 20 , added embedded crystal package lcc8 (updated figure 1 , 5 , 29 , ta b l e 2 3 ). 25-may-2010 14 removed lcc8 package option throughout document; removed footnote from ta b l e 1 4 . 24-mar-2011 15 updated ta b l e 1 , 17 , 23 ; added lcc8 package option throughout datasheet; added tape and reel specifications for packages ( figure 31 , 32 , 33 , ta b l e 2 1 , 22 ). 22-jun-2011 16 updated features ; updated lcc8 package height in figure 29 . 10-oct-2011 17 updated v ol test condition in table 14: dc characteristics ; minor textual updates. 09-nov-2011 18 updated figure 29 , ta b l e 2 2 ; added ta bl e 2 0 , figure 30 . 01-dec-2011 19 updated title and ta bl e 1 6 .
M41T62/63/64/65 44/44 doc id 10397 rev 19 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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