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1 precision edge ? sy89873l micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 description guaranteed ac performance ?> 2.0ghz f max output toggle ?> 3.0ghz f max input ?< 800ps t pd (matched-delay between banks) ?< 15ps within-device skew ?< 190ps rise/fall time low jitter design ?< 1ps rms cycle-to-cycle jitter ?< 10ps pp total jitter unique input termination and v t pin for dc-coupled and ac-coupled inputs: any differential inputs (lvpecl, lvds, cml, hstl) precision differential lvds outputs matched delay: all outputs have matched delay, independent of divider setting ttl/cmos inputs for select and reset/disable two lvds output banks (matched delay) ? bank a: buffered copy of input clock (undivided) ? bank b: divided output ( 2, 4, 8, 16), two copies 3.3v power supply wide operating temperature range: C40 c to +85 c available in 16-pin (3mm 3mm) mlf ? package features 3.3v, 2.0ghz any diff. in-to-lvds programmable clock divider fanout buffer w/ internal termination precision edge ? sy89873l applications sonet/sdh line cards transponders high-end, multiprocessor servers rev.: f amendment: /0 issue date: february 2007 this 3.3v low-skew, low-jitter, precision lvds output clock divider accepts any high-speed differential clock input (ac- or dc-coupled) cml, lvpecl, hstl or lvds and divides down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. the sy89873l includes two output banks. bank a is an exact copy of the input clock (pass through) with matched propagation delay to bank b, the divided output bank. available divider ratios are 2, 4, 8 and 16. in a typical 622mhz clock system this would provide availability of 311mhz, 155mhz, 77mhz or 38mhz auxiliary clock components. the differential input buffer has a unique internal termination design that allows access to the termination network through a vt pin. this feature allows the device to easily interface to all ac- or dc-coupled differential logic standards. a v ref-ac reference is included for ac-coupled applications. the sy89873l is part of micrels high-speed precision edge ? timing and distribution family. for 2.5v applications, consider the sy89872u. for applications that require an lvpecl output, consider the sy89871u. the /reset input asynchronously resets the divider outputs (bank b). in the pass-through function (bank a) the /reset synchronously enables or disables the outputs on the next falling edge of in (rising edge of /n). refer to the timing diagram. all support documentation can be found on micrels web site at: www.micrel.com. functional block diagram typical application precision edge is a registered trademark of micrel, inc. micro leadframe and mlf are registered trademarks of amkor technology, inc. in 50 ? 50 ? /in s0 s1 qb1 /qb1 qb0 /qb0 qa /qa /reset v t v ref-ac divided by 2, 4, 8 or 16 decoder enable ff enable mux precision edge ? in /in qa /qa 622mhz lvds clock out 622mhz lvpecl clock in 622mhz/155.5mhz sonet clock generator bank b: 155.5mhz: for oc-3 line card set to divide-by-4 bank a: 622mhz: for oc-12 line card set to pass-through 155.5mhz lvds clock out oc-12 or oc-3 clock gen qb /qb
2 precision edge ? sy89873l micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 package/ordering information pin number pin name pin function 1, 2, 3, 4 qb0, /qb0 differential buffered output clocks: divide by 2, 4, 8, 16. qb1, /qb1 lvds compatible. 5, 6 qa, /qa differential buffered undivided output clock: lvds compatible. 7, 14 vcc positive power supply: bypass with 0.1 f//0.01 f low esr capacitors. 8 /reset, ttl/cmos compatible output reset and disable: internal 25k ? pull-up. input threshold /disable is v cc /2. logic low will reset the divider select, and align bank a and bank b edges. in addition, when low, banks a and b will be disabled. 12, 9 in, /in differential input: internal 50 ? termination resistors to v t input. see input interface applications section. 10 vref-ac reference voltage: equal to v cc C1.4v (approx.), and used for ac-coupled applications. maximum sink/source current is 0.5ma. see input interface applications section. 11 vt termination center-tap: for cml and lvds inputs, leave this pin floating. otherwise, see input interface applications section. 13 gnd ground: exposed pad is internally connected to gnd and must be connected to a ground plane for proper thermal operation. 16, 15 s0, s1 select pins: lvttl/cmos logic levels. internal 25k ? pull-up resistor. logic high if left unconnected (divided by 16 mode). s0 = lsb. input threshold is v cc /2. pin description 13 14 15 16 12 11 10 9 1 2 3 4 8 7 6 5 qb0 /qb0 qb1 /qb1 in vt vref-ac /in s0 s1 vcc gnd qa /qa vcc /reset /disable 16-pin mlf ? (mlf-16) /reset s1 s0 bank a output bank b outputs /disable 10 0 input clock input clock 2 10 1 input clock input clock 4 11 0 input clock input clock 8 11 1 input clock input clock 16 0x x qa = low, /qa = high (1) qb0 = low, /qb0 = high (2) qb1 = low, /qb1 = high (2) notes: 1. on the next negative transition of the input signal. 2. asynchronous reset/disable function. see "timing diagram." truth table ordering information (1) package operating package lead part number type range marking finish sy89873lmi mlf-16 industrial 873l sn-pb sy89873lmitr (2) mlf-16 industrial 873l sb-pb sy89873lmg (3) mlf-16 industrial 873l with nipdau pb-free bar line indicator pb-free sy89873lmgtr (2, 3) mlf-16 industrial 873l with nipdau pb-free bar line indicator pb-free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25 c, dc electricals only. 2. tape and reel. 3. pb-free package is recommended for new designs.
3 precision edge ? sy89873l micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 absolute maximum ratings (1) supply voltage (v cc ) .................................. C0.5v to +4.0v input voltage (v in ) .................................. C0.5v to v cc +0.3 lvds output current (i out ) .................................... 10ma input current in, /in (i in ) .......................................... 50ma v ref-ac input sink/source current (i vref-ac ) (3) ............ 2ma lead temperature (soldering, 20 sec.) ..................... 260 c storage temperature (t s ) ....................... C65 c to +150 c operating ratings (2) supply voltage (v cc ) ...................................... +3.3v 10% ambient temperature (t a ) ......................... C40 c to +85 c package thermal resistance mlf ? ( ja ) still-air ............................................................. 60 c/w 500 lfpm ........................................................... 54 c/w mlf ? ( jb ) (4) junction-to-board ............................................ 38 c/w t a = C40 c to +85 c; unless otherwise stated. symbol parameter condition min typ max units v cc power supply 3.0 3.3 3.6 v i cc power supply current no load, max v cc 85 115 ma r in differential input resistance 90 100 110 ? (in-to-/in) v ih input high voltage note 6 0.1 v cc +0.3 v in, /in v il input low voltage note 6 C0.3 v cc v in, /in v in input voltage swing notes 6, 7 0.1 3.6 v v diff_in differential input voltage swing notes 6, 7, 8 0.2 v |i in | input current note 6 45 ma in, /in v ref-ac reference voltage note 9 v cc C1.525 v cc C1.425 v cc C1.325 v notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. due to the limited drive capability use for input of the same package only. 4. junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the p cb. 5. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established . 6. due to the internal termination (see input buffer structure ) the input current depends on the applied voltages at in, /in and v t inputs. do not apply a combination of voltages that causes the input current to exceed the maximum limit! 7. see timing diagram for v in definition. v in (max) is specified when v t is floating. 8. see figures 1c and 1d for v diff definition. 9. operating using v in is limited to ac-coupled pecl or cml applications only. connect directly to v t pin. dc electrical characteristics (5)
4 precision edge ? sy89873l micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 v cc = 3.3v 10%; t a = C40 c to +85 c; unless otherwise stated. symbol parameter condition min typ max units v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current C125 20 a i il input low current C300 a notes: 10. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establishe d. 11. measured as per figure 1a, 100 ? across q and /q outputs. 12. see figure 1c. lvttl/cmos dc electrical characteristics (10) v cc = 3.3v 10%; t a = C40 c to +85 c; unless otherwise stated. symbol parameter condition min typ max units v out output voltage swing notes 11, 12 250 350 450 mv v oh output high voltage note 11 1.475 v v ol output low voltage note 11 0.925 v v ocm output common mode voltage note 11 1.125 1.275 v ? v ocm change in common mode voltage C50 50 mv lvds output dc electrical characteristics (10)
5 precision edge ? sy89873l micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 v cc = 3.3v 10%; t a = C40 c to +85 c; unless otherwise stated. symbol parameter condition min typ max units f max maximum output toggle frequency output swing: 200mv 2.0 ghz (bank a and bank b) maximum input frequency note 14 3.2 ghz t pd differential propagation delay input swing < 400mv 550 660 800 ps (in-to-q) input swing 400mv 500 610 750 ps t skew within-device skew (diff.) note 15 7 15 ps (qb0-to-qb1) within-device skew (diff.) note 15 12 30 ps (bank a-to-bank b) part-to-part skew (diff.) note 15 250 ps t rr reset recovery time note 16 600 ps t jitter cycle-to-cycle jitter note 17 1 ps rms total jitter note 18 10 ps pp t r , t f rise / fall time (20% to 80%) 60 110 190 ps notes: 13. measured with 400mv input signal, 50% duty cycle. all outputs terminated with 100 ? between q and /q, unless otherwise stated. 14. bank a (pass-through) maximum frequency is limited by the output stage. bank b (input-to-output 2, 4, 8, 16) can accept an input frequency >3ghz, while bank a will be slew-rate limited. 15. skew is measured between outputs under identical transitions. 16. see timing diagram. 17. cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pai rs. t jitter_cc =t n Ct n+1 , where t is the time between rising edges of the output signal. 18. total jitter definition: with an ideal clock input, of frequency f max (device), no more than one output edge in 10 12 output edges will deviate by more than the specified peak-to-peak jitter value. ac electrical characteristics (13)
6 precision edge ? sy89873l micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 timing diagram v in (swing) v out (swing) /reset in /in qb /qb qa /qa t pd t rr v cc/2 lvds output v out 100 ? 1% v oh , v ol v oh , v ol gnd figure 1a. lvds differential measurement gnd 50 ? 1% 50 ? 1% v ocm , ? v ocm figure 1b. lvds common mode measurement v in , v out 350mv (typical) figure 1c. single-ended swing v diff_in , v diff_out 700mv (typical) figure 1d. differential swing definition of single-ended and differential swing
7 precision edge ? sy89873l micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 typical operating characteristics v cc = 3.3v, v in = 400mv, t a = 25 c, unless otherwise stated. 0 50 100 150 200 250 300 350 0 500 1000 1500 2000 2500 qa amplitude (mv) frequency (mhz) output amplitude vs. frequency 400 500 600 700 800 0 200 400 600 800 1000 1200 propagation delay (ps) input swing (mv) nominal propagation delay vs. input swing 400 500 600 700 800 -40 -20 0 20 40 60 80 100 120 propagation delay (ps) temperature ( c) nominal propagation delay vs. temperature
8 precision edge ? sy89873l micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 functional characteristics qa @ 622mhz and qb @ 155.5mhz (divided-by-4) /qa qb qa 622mhz 4 155mhz /qb time (1ns/div.) output swing (100mv/div.) qa output @ 1.25ghz time (100ps/div.) output swing (50mv/div.) qa output @ 2.0ghz time (100ps/div.) output swing (50mv/div.) q /q conditions: v cc = 3.3v, t a = 25 c, unless otherwise stated.
9 precision edge ? sy89873l micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 input buffer structure v cc gnd 50 ? 50 ? in v t /in 1.86k ? 1.86k ? 1.86k ? 1.86k ? figure 2a. simplified differential input stage v cc gnd s0 s1 /reset r 25k ? r figure 2b. simplified ttl/cmos input
10 precision edge ? sy89873l micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 part number function data sheet link sy89871u 2.5ghz any diff. in-to-lvpecl programmable www.micrel.com/product-info/products/sy89871u.shtml clock divider/fanout buffer w/internal termination sy89872u 2.5v 2ghz any diff. in-to-lvds programmable www.micrel.com/product-info/products/sy89872u.shtml clock divider/fanout buffer w/internal termination mlf ? application note www.amkor.com/products/notes_papers/mlf_appnote_0902.pdf hbw solutions new products and applications www.micrel.com/product-info/products/solutions.shtml related micrel products and support documentation input interface applications cml in /in v t nc gnd sy89873l v cc = 3.3v v cc = 3.3v v ref-ac nc figure 3a. dc-coupled cml input interface v cc 0.01 f cml in /in v t gnd sy89873l v cc = 3.3v v cc = 3.3v v ref-ac figure 3b. ac-coupled cml input interface v cc = 3.3v v cc = 3.3v in /in v t gnd sy89873l v ref-ac nc v cc * bypass with 0.01 f to v cc 50 ? .01 f v cc C 2v* l vpecl figure 3c. dc-coupled lvpecl input interface l vpecl in /in v t gnd sy89873l v cc = 3.3v v cc = 3.3v v cc gnd 100 ? 100 ? v ref-ac 0.01 f figure 3d. ac-coupled lvpecl input interface l vds in /in v t nc gnd sy89873l v cc = 3.3v v cc = 3.3v v ref-ac nc figure 3e. lvds input interface figure 3f. hstl input interface
11 precision edge ? sy89873l micrel, inc. m9999-082407 hbwhelp@micrel.com or (408) 955-1690 16-pin micro leadframe ? (mlf-16) pa c kage ep- exposed pad die compside island heat dissipation heavy copper plane heavy copper plane v ee v ee heat dissipation pcb thermal consideration for 16-pin mlf ? package (always solder, or equivalent, the exposed pad to the pcb) package notes: 1. package meets level 2 moisture sensitivity classification, and is shipped in dry-pack form. 2. exposed pads must be soldered to a ground for proper thermal management. micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel + 1 (408) 944-0800 fax + 1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intend ed for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant inj ury to the user. a purchasers use or sale of micrel products for use in life support appliances, devices or systems is at purchasers own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2006 micrel, incorporated.

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