View SI4724CY-T1_4398622.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

vishay siliconix si4724 document number: 71863 s11-1185-rev. f, 13-jun-11 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 n-channel synchronous mosfets with break-before-make features ? 0 v to 30 v operation ? driver impedance-3 ? undervoltage lockout ? fast switching times ? 30 v mosfets ? high side: 0.0375 at v dd = 4.5 v ? low side: 0.029 at v dd = 4.5 v ? switching frequency: 250 khz to 1 mhz ? integrated schottky description the si4724cy n-channel synchronous mosfet with break-before-make (bbm) is a high speed driver designed to operate in high frequency dc/dc switchmode power supplies. it?s purpose is to simplify the use of n-channel mosfets in high frequency buck regulators. this device is designed to be used with any single output pwm ic or asic to produce a highly efficient lo w cost synchronous rectifier converter. a synchronous enable pin (disable = low, enable = high) controls the synchronous function for light load conditions. the si4724cy is packaged in vishay siliconix?s high performance little foot ? so-16 package. functional block diagram boot d 1 s 1 d 2 v dd in undervoltage lockout gnd q 2 q 1 - + v dd sync en v ref level shift s 2
www.vishay.com 2 document number: 71863 s11-1185-rev. f, 13-jun-11 vishay siliconix si4724 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. surface mounted on 1" x 1" fr4 board, full copper two sides. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. notes: a. surface mounted on 1" x 1" fr4 board. b. junction-to-foot thermal impedance repres ents the effective thermal impedance of al l heat carrying leads in parallel and is intended for use in conjunction with the ther mal impedance of the pc board pads to ambient (r thja = r thjf + r thpcb-a ). it can also be used to estimate chip tem- perature if power dissipation and the lead temperat ure of a heat carrying (drain) lead is known. absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol steady state unit logic supply v dd 7 v logic inputs v in - 0.7 to v dd + 0.3 drain voltage v d1 30 bootstrap voltage v boot v s1 + 7 synchronous pin voltage v sync - 0.7 to v dd + 0.3 continuous drain current t a = 25 c i d1 5.1 a t a = 70 c 4.09 t a = 25 c i d2 6.5 t a = 70 c 5.2 maximum power dissipation a p d 1.2 w operating junction and storage temperature range driver t j , t stg - 65 to 125 c mosfets - 65 to 150 recommended operating conditions parameter symbol steady state unit drain voltage v d1 0 to 30 v logic supply v dd 4.5 to 5.5 input logic high voltage v ih 0.7 x v dd to v dd input logic low voltage v il - 0.3 to 0.3 x v dd bootstrap capacitor c boot 0.1 to 1 ambient temperature t a - 40 to 85 c thermal resistance ratings parameter symbol typical maximum unit highside junction-to-ambient a steady state r thja1 85 105 c/w lowside junction-to-ambient a r thja2 68 85 highside junction-to-foot (drain) b r thjf1 28 35 lowside junction-to-foot (drain) b r thjf2 19 24
document number: 71863 s11-1185-rev. f, 13-jun-11 www.vishay.com 3 vishay siliconix si4724 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. pulse test; pulse width ? 300 s, duty cycle ? 2 %. b. typical values are for design aid only, not guaranteed nor subject to production testing. specifications parameter symbol test conditions unless specified t a = 25 c 4.5 v < v dd < 5.5 v, 4.5 v < v d1 < 30 v limits unit min. typ. max. power supplies logic voltage v dd 4.5 5.5 v logic current i dd(en) v dd = 4.5 v, v in = 4.5 v 280 500 a i dd(dis) v dd = 4.5 v, v in = 0 v 220 500 logic input logic input voltage (v in ) high v ih v dd = 4.5 - 40 c ?? t a ? 85 c 3.15 2.3 v low v il - 0.3 2.25 0.8 protection break-before-make reference v bbm v dd = 5.5 2.4 v undervoltage lockout v uvlo sync = 4.5 3.75 4 4.25 undervoltage lockout hysteresis v h 0.4 mosfet drivers driver impedance r dr1 v dd = 4.5 v driver 1 3 v r dr2 driver 2 2 mosfets drain-source voltage v ds i d = 250 a 30 v drain source on state resistance a r ds(on)1 v dd = 4.5 v, i d = 5 a t a = 25 c q1 30 37.5 m ? r ds(on)2 q2 24 29 diode forward voltage a v sd1 i s = 2 a, v gs = 0 q1 0.7 1.1 v v sd2 q2 0.7 1.1 dynamic b (unless specified-f s = 250 khz, v in = 12 v. v dd = 5 v, i = 5 a, refer to switching test setup) turn off delay t d(off)1 see timing diagram v in to g 1 28 56 ns t d(off)2 v in to g 2 17 40 ? t ? t 1-2 g 1 to g 2 16 32 ? t 2-1 g 2 to g 1 38 80 source-drain reverse recovery time-q 2 t frr i f 2.7 a, di/dt = 100 a/s 50 80 schottky specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min typ max unit forward voltage drop v f i f = 1 a 0.47 0.50 v i f = 1 a, t j = 125 c 0.36 0.42 maximum reverse leakage current i rm v r = 30 v 0.004 0.100 ma v r = 30 v, t j = 100 c 0.7 10 v r = - 30 v, t j = 125 c 320 junction capacitance c t v r = 10 v 50 pf
www.vishay.com 4 document number: 71863 s11-1185-rev. f, 13-jun-11 vishay siliconix si4724 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 application circuit pin configuration figure 1. mosfet drive circuitry with break-before- make si4724 c boot c boot d 1 s 1 d 2 s 2 v dd sync en in gnd + v out gnd dc-dc controller 0 v to 30 v 5 v gnd q 1 q 2 power up sequence: ensure v dd is within spec before allowing in or sync en to be set high. power down sequence: ensure in and sync en are low before turning v dd off. 13 so-16 14 15 16 2 3 4 1 10 11 12 5 6 7 9 8 top view d 1 s 1 d 1 s 1 gnd c boot in v dd sync en s 2 s 2 d 2 d 2 d 2 s 2 d 2 ordering information: SI4724CY-T1 SI4724CY-T1-e3 (lead (pb)-free) truth table sync en clk q 1 q 2 hhonoff hloffon lhonoff lloffoff pin description pin number symbol description 1, 2 d 1 highside mosfet drain 3 gnd ground 4 in input logic signal 5 sync en synchronous enable 6, 7, 8 s 2 lowside mosfet source 9, 10, 11, 12 d 2 lowside mosfet drain 13 v dd logic supply, decoupling to gnd with a cap is strongly recommended. 14 c boot bootstrap capacitor for upper mosfet 15, 16 s 1 highside mosfet source
document number: 71863 s11-1185-rev. f, 13-jun-11 www.vishay.com 5 vishay siliconix si4724 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 timing diagram switching test set-up figure 2. ? t 1-2 ? t 1 - 2 t d(off) g 1 g 2 output (s 1 /d 2 , not to scale) in figure 3. ? t 2-1 t d(off) ? t 2-1 g 2 g 1 in output (s 1 /d 2 , not to scale) figure 4. c boot c boot d 1 s 1 d 2 s 2 v dd sync en in gnd + r l gnd signal input 12 v 5 v gnd g 2 s 1 /d 2 g 1 mosfet drive circuitry with break-before- make c c l c l
www.vishay.com 6 document number: 71863 s11-1185-rev. f, 13-jun-11 vishay siliconix si4724 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c unless noted) on-resistance vs. gate-to-source voltage (q 1 ) on-resistance vs. ambient temperature input current vs. junction temperature 0 20 40 60 80 0246810 - on-resistance (m ? ) r ds(on) v gs - gate-to-source voltage (v) i d = 5 a 0.4 0.6 0.8 1.0 1.2 1.4 1.6 - 50 - 25 0 25 50 75 100 125 150 t a - ambient temperature (c) i d = 5 a v gs = 4.5 v r ds(on) - on-resistance (normalized) 100 150 200 250 300 350 - 50 - 25 0 25 50 75 100 125 150 i ddq at in = l t j - junction temperature (c) i ddq (a) i ddq at in = h output capacitance vs. drain voltage (q 1 and q 2 ) i cc vs. frequency source-drain diode forward voltage 0 100 200 300 400 500 600 700 800 0 6 12 18 24 30 v ds - drain-to-source voltage (v) c oss (pf) 0 2 4 6 8 10 12 14 16 0 200 400 600 800 1000 v in = 12 v v dd = 5 v dc = 25 % boot = 0.1 f i load = 1 a frequency (khz) i cc (ma) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 t j = 25 c 10 1 v sd - source-to-drain voltage (v) - source current (a) i s t j = 150 c
document number: 71863 s11-1185-rev. f, 13-jun-11 www.vishay.com 7 vishay siliconix si4724 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c unless noted) single pulse power, junction-to-foot (q 1 ) single pulse power, junction-to-foot (q 2 ) 0 30 50 10 20 power (w) pulse (s) 40 0.1 1000 1 0.01 10 100 0 30 50 10 20 power (w) pulse (s) 40 0.1 1000 1 0.01 10 100 single pulse power, junction-to-ambient (q 1 ) single pulse power, junction-to-ambient (q 2 ) 0 30 50 10 20 power (w) time (sec) 40 0.1 1000 1 0.01 10 100 0 30 50 10 20 power (w) time (sec) 40 0.1 1000 1 0.01 10 100 normalized thermal transient impedance, junction-to-ambient (q 1 ) 10 -3 10 -2 1 10 600 10 -1 10 -4 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single pulse duty cycle = 0.5 square wave pulse duration (sec) normalized eff ective transient thermal impedance 1. duty cycle, d = 2. per unit base = r thja = 85 c/w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 notes: 4. surface mounted p dm
www.vishay.com 8 document number: 71863 s11-1185-rev. f, 13-jun-11 vishay siliconix si4724 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c unless noted) vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?71863 . normalized thermal transient impedance, junction-to-foot (q 1 ) 10 -3 10 -2 1 1000 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single pulse duty cycle = 0.5 square wave pulse duration (sec) normalized effective transient thermal impedance 10 100 normalized thermal transient impedance, junction-to-ambient (q 2 ) 10 -3 10 -2 1 10 600 10 -1 10 -4 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single pulse duty cycle = 0.5 square wave pulse duration (sec) normalized eff ective transient thermal impedance 1. duty cycle, d = 2. per unit base = r thja = 68 c/w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 notes: 4. surface mounted p dm normalized thermal transient impedance, junction-to-foot (q 2 ) 10 -3 10 -2 1 1000 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single pulse duty cycle = 0.5 normalized effective transient thermal impedance 10 100 square wave pulse duration (sec)
all leads 0.101 mm 0.004 in e h c d e b a1 l 4 3 12 8 7 56 13 14 16 15 9 10 12 11 package information vishay siliconix document number: 71194 02-jul-01 www.vishay.com 1
jedec part number: ms-012 dim min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.38 0.51 0.015 0.020 c 0.18 0.23 0.007 0.009 d 9.80 10.00 0.385 0.393 e 3.80 4.00 0.149 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 l 0.50 0.93 0.020 0.037 0 8 0 8 ecn: s-03946?rev. f, 09-jul-01 dwg: 5300
application note 826 vishay siliconix www.vishay.com document number: 72608 24 revision: 21-jan-08 application note recommended minimum pads for so-16 recommended minimum pads for so-16 0.246 (6.248) recommended mi nimum pads dimensions in inches/(mm) 0.152 (3.861) 0.047 (1.194) 0.028 (0.711) 0.050 (1.270) 0.022 (0.559) 0.372 (9.449) return to index return to index
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

▲Up To Search▲

Price & Availability of SI4724CY-T1

	To Download SI4724CY-T1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .