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| hdmi/dvi buffer with equalization ad8195 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008 analog devices, inc. all rights reserved. features 1 input, 1 output hdmi/dvi link enables hdmi 1.3a-compliant front panel input 4 tmds channels per link supports 250 mbps to 2.25 gbps data rates supports 25 mhz to 225 mhz pixel clocks equalized inputs for operatio n with long hdmi cables (20 m at 2.25 gbps) preemphasized outputs fully buffered unidirectional inputs/outputs 50 on-chip terminations low added jitter transmitter disable feature reduces power dissipation disables input termination 3 auxiliary buffered channels per link bidirectional buffered ddc lines (sda and scl) bidirectional buffered cec line with integrated pull-up resistors (27 k) independently powered from +5 v of hdmi input connector logic level translation (3.3 v, 5 v) input/output capacitance isolation standards compatible: hdmi, dvi, hdcp, ddc, cec 40-lead lfcsp_vq package (6 mm 6 mm) applications front panel buffer for advanced television (hdtv) sets general description the ad8195 is an hdmi?/dvi buffer featuring equalized tmds inputs and preemphasized tmds outputs, ideal for systems with long cable runs. the ad8195 includes bidirec- tional buffering for the ddc bus and bidirectional buffering with integrated pull-up resistors for the cec bus. the ddc and cec buffers are powered independently of the tmds buffers so that ddc/cec functionality can be maintained when the system is powered off. the ad8195 is specified to operate over the ?40c to +85c temperature range. functional block diagram ip[3:0] in[3:0] vtti op[3:0] amuxvcc avee vtto avcc on[3:0] vref_in v ref_out + ? + ? eq buffer pe control logic 4 4 4 2 2 4 high speed buffered low speed buffered pe_en tx_en comp parallel bidirectional ad8195 scl_in sda_in scl_out sda_out cec_in cec_out 07049-001 figure 1. typical application 07049-002 media center set-top box dvd player hdtv set 4:1 hdmi switch ad8195 hdmi receiver front panel connector back panel connectors game console figure 2. typical ad8195 application for hdtv sets product highlights 1. enables a fully hdmi 1.3a-compliant front panel input. 2. supports data rates up to 2.25 gbps, enabling 1080p deep color (12-bit color) hdmi formats and greater than uxga (1600 1200) dvi resolutions. 3. input cable equalizer enables use of long cables; more than 20 meters (24 awg) at data rates up to 2.25 gbps. 4. auxiliary buffer isolates and buffers the ddc bus and cec line for a single chip, fully hdmi 1.3a-compliant solution. 5. auxiliary buffer is powered independently from the tmds link so that ddc/cec functionality can be maintained when the system is powered off.
ad8195 rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? typical application ........................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? tmds performance specifications ............................................ 3 ? auxiliary channel performance specifications........................ 4 ? power supply and control logic specifications ...................... 4 ? absolute maximum ratings ............................................................ 5 ? thermal resistance ...................................................................... 5 ? maximum power dissipation ..................................................... 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ..............................6 ? typical performance characteristics ..............................................8 ? theory of operation ...................................................................... 12 ? introduction ................................................................................ 12 ? input channels ........................................................................... 12 ? output channels ........................................................................ 12 ? preemphasis ................................................................................ 13 ? auxiliary lines ............................................................................ 13 ? applications information .............................................................. 14 ? front panel buffer for advanced tv ....................................... 14 ? cable lengths and equalization ............................................... 15 ? tmds output rise/fall times ................................................. 15 ? pcb layout guidelines .............................................................. 15 ? outline dimensions ....................................................................... 18 ? ordering guide .......................................................................... 18 ? revision history 8/08revision 0: initial version ad8195 rev. 0 | page 3 of 20 specifications t a = 27c, avcc = 3.3 v, vtti = 3.3 v, vtto = 3.3 v, amuxvcc = 5 v, vref_in = 5 v, vref_out = 5 v, avee = 0 v, differential input swing = 1000 mv, tmds outputs terminated with external 50 resistors to 3.3 v, unless otherwise noted. tmds performance specifications table 1. parameter conditions/comments min typ max unit tmds dynamic performance maximum data rate (dr) per channel nrz 2.25 gbps bit error rate (ber) prbs 2 23 ? 1 10 ?9 added data jitter dr 2.25 gbps, prbs 2 7 ? 1 31 ps p-p added clock jitter 1 ps rms differential intrapair skew at output 1 ps differential interpair skew at output 30 ps tmds equalization performance receiver 1 boost frequency = 1.125 ghz 12 db transmitter 2 boost frequency = 1.125 ghz 6 db tmds input characteristics input voltage swing differential 150 1200 mv input common-mode voltage (v icm ) avcc ? 800 avcc mv tmds output characteristics high voltage level single-ended high speed channel avcc ? 200 avcc + 10 mv low voltage level single-ended high speed channel avcc ? 600 avcc ? 400 mv rise/fall time (20% to 80%) 3 dr = 2.25 gbps 50 90 150 ps tmds termination input termination resistance single-ended 50 output termination resistance single-ended 50 1 output meets transmitter eye diagram as defined in the dvi standard revision 1.0 and hdmi standard revision 1.3a. 2 cable output meets receiver eye diagram mask as defined in the dvi standard revision 1.0 and hdmi standard revision 1.3a. 3 output rise/fall time measurement excludes external components, such as hdmi connector or external esd protection diodes. see the section for more information. applications information ad8195 rev. 0 | page 4 of 20 auxiliary channel performance specifications table 2. parameter conditions/comments min typ max unit ddc channels input capacitance, c aux dc bias = 2.5 v, ac voltage = 3.5 v p-p, f = 100 khz 10 15 pf input low voltage, v il 0.5 v input high voltage, v ih 0.7 vref 1 vref 1 v output low voltage, v ol i ol = 5 ma 0.25 0.4 v output high voltage, v oh vref 1 v rise time 10% to 90%, no load 140 ns fall time 90% to 10%, c load = 400 pf 100 200 ns leakage input voltage = 5.0 v 10 a cec channel input capacitance, c aux dc bias = 1.65 v, ac voltage = 2.5 v p-p, f = 100 khz, 2 k pull-up resistor from cec_out to 3.3 v 5 25 pf input low voltage, v il 0.8 v input high voltage, v ih 2.0 v output low voltage, v ol 0.25 0.6 v output high voltage, v oh 2.5 3.3 v rise time 10% to 90%, c load = 1500 pf, r pull-up = 27 k; or c load = 7200 pf, r pull-up = 3 k 50 100 s fall time 90% to 10%, c load = 1500pf, r pull-up = 27 k; or c load = 7200 pf, r pull-up = 3 k 5 10 s pull-up resistance 27 k leakage off leakage test conditions 2 1.8 a 1 vref is the voltage at the reference pin (vref_in for scl_in and sda_in, or vref_out for scl_ out and sda_out); nominally +5.0 v. 2 off leakage test conditions are described in the hdmi complian ce test specification 1.3b section 8, test id 8-14: remove powe r (mains) from dut. connect cec line to 3.63 v via 27 k 5% resistor with ammete r in series. measure cec line leakage. power supply and contro l logic specifications table 3. parameter conditions/comments min typ max unit power supply avcc operating range (3.3 v 10%) 3 3.3 3.6 v amuxvcc operating range (5 v 10%) 4.5 5 5.5 v vref_in, vref_out 3 5.5 v quiescent current avcc output disabled 20 40 ma output enabled, no preemphasis 32 50 ma output enabled, maximum preemphasis 66 80 ma vtti input termination on 40 54 ma vtto output termination on, no preemphasis 40 50 ma output termination on, maximum preemphasis 80 100 ma vref_in 120 200 a vref_out 120 200 a amuxvcc 10 20 ma power dissipation output disabled 116 254 mw output enabled, no preemphasis 180 663 mw output enabled, maximum preemphasis 736 1047 mw parallel control interface tx_en, pe_en input high voltage, v ih 2.4 v input low voltage, v il 0.8 v ad8195 rev. 0 | page 5 of 20 absolute maximum ratings table 4. parameter rating avcc to avee 3.7 v vtti avcc + 0.6 v vtto avcc + 0.6 v amuxvcc 5.5 v vref_in 5.5 v vref_out 5.5 v internal power dissipation 1.81 w high speed input voltage avcc ? 1.4 v < v in < avcc + 0.6 v high speed differential input voltage 2.0 v parallel control input voltage avee ? 0.3 v < v in < avcc + 0.6 v storage temperature range ?65c to +125c operating temperature range ?40c to +85c junction temperature 150c esd, human body model input pins only 5 kv all other pins 3 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance table 5. package ja jc unit 40-lead lfcsp_vq 36 5.0 c/w maximum power dissipation the maximum power that can be safely dissipated by the ad8195 is limited by the associated rise in junction tempera- ture. the maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 175c for an extended period can result in device failure. to ensure proper operation, it is necessary to observe the maximum power derating as determined by the thermal resistance coefficients. esd caution ad8195 rev. 0 | page 6 of 20 pin configuration and fu nction descriptions notes 1. the ad8195 lfcsp has an exposed pad on the underside of the package that aids in heat dissipation. the pad must be electrically connected to the avee supply plane in order to meet thermal specifications. ad8195 top view (not to scale) 1 in0 2 ip0 3 in1 4 ip1 5 vtti 6 in2 7 ip2 10 avcc 30 avcc 29 pe_en 28 tx_en 27 avee 26 avcc 25 avcc 24 avee 21 comp 40 scl_in 39 sda_in 38 cec_in 37 avee 36 vref_in 35 scl_out 34 sda_out 31 cec_out 11 on0 12 op0 13 vtto 14 on1 15 op1 16 avcc 17 on2 20 op3 9 ip3 8 in3 22 avcc 23 avcc 19 on3 18 op2 32 amuxvcc 33 vref_out pin 1 indicator 07049-003 figure 3. pin configuration table 6. pin function descriptions pin o. nemonic type 1 description 1 in0 hs i high speed input complement. 2 ip0 hs i high speed input. 3 in1 hs i high speed input complement. 4 ip1 hs i high speed input. 5 vtti power input termination supply. nominally connected to avcc. 6 in2 hs i high speed input complement. 7 ip2 hs i high speed input. 8 in3 hs i high speed input complement. 9 ip3 hs i high speed input. 10, 16, 22, 23, 25, 26, 30 avcc power positive analog supply. 3.3 v nominal. 11 on0 hs o high speed output complement. 12 op0 hs o high speed output. 13 vtto power output termination supply. nominally connected to avcc. 14 on1 hs o high speed output complement. 15 op1 hs o high speed output. 17 on2 hs o high speed output complement. 18 op2 hs o high speed output. 19 on3 hs o high speed output complement. 20 op3 hs o high speed output. 21 comp control power-on compensation pin. bypass to ground through a 10 f capacitor. 24, 27, 37, exposed pad avee power negative analog supply. 0 v nominal. 28 tx_en control high speed output enable parallel interface. 29 pe_en control high speed preemphasis enable parallel interface. 31 cec_out ls i/o cec output side. 32 amuxvcc power positive auxiliary buffer supply. 5 v nominal. ad8195 rev. 0 | page 7 of 20 pin no. mnemonic type 1 description 33 vref_out reference ddc output side pull-up reference voltage. 34 sda_out ls i/o ddc output side data line input/output. 35 scl_out ls i/o ddc output side clock line input/output. 36 vref_in reference ddc input side pull-up reference voltage. 38 cec_in ls i/o cec input side. 39 sda_in ls i/o ddc input side data line. 40 scl_in ls i/o ddc input side clock line 1 hs = high speed, ls = low speed, i = input, o = output. ad8195 rev. 0 | page 8 of 20 typical performance characteristics t a = 27c, avcc = 3.3 v, vtti = 3.3 v, vtto = 3.3 v, avee = 0 v, differential input swing = 1000 mv, pattern = prbs 2 7 ? 1, data rate = 2.25 gbps, tmds outputs terminated with external 50 resistors to 3.3 v, unless otherwise noted. reference eye diagram at tp1 digital pattern generator ad8195 evaluation board serial data analyzer sma coax cable hdmi cable tp1 tp2 tp3 07049-104 figure 4. test circuit diagram for rx eye diagrams 0.125ui/div at 2.25gbps 250mv/di v 07049-105 figure 5. rx eye diagram at tp2 (cable = 2 meters, 24 awg) 0.125ui/div at 2.25gbps 250mv/di v 07049-106 figure 6. rx eye diagram at tp2 (cable = 20 meters, 24 awg) 0.125ui/div at 2.25gbps 250mv/di v 07049-107 figure 7. rx eye diagram at tp3, eq = 12 db (cable = 2 meters, 24 awg) 0.125ui/div at 2.25gbps 250mv/di v 07049-108 figure 8. rx eye diagram at tp3, eq = 12 db (cable = 20 meters, 24 awg) ad8195 rev. 0 | page 9 of 20 t a = 27c, avcc = 3.3 v, vtti = 3.3 v, vtto = 3.3 v, avee = 0 v, differential input swing = 1000 mv, pattern = prbs 2 7 ? 1, data rate = 2.25 gbps, tmds outputs terminated with external 50 resistors to 3.3 v, unless otherwise noted. reference eye diagram at tp1 digital pattern generator sma coax cable hdmi cable tp1 tp2 tp3 ad8195 evaluation board serial data analyzer 07049-109 figure 9. test circuit diagram for tx eye diagrams 0.125ui/div at 2.25gbps 250mv/di v 07049-110 figure 10. tx eye diagram at tp2, pe = 0 db 0.125ui/div at 2.25gbps 250mv/di v 07049-111 figure 11. tx eye diagram at tp2, pe = 6 db 0.125ui/div at 2.25gbps 250mv/di v 07049-112 figure 12. tx eye diagram at tp3, pe = 0 db (cable = 6 meters, 24 awg) 0.125ui/div at 2.25gbps 250mv/di v 07049-113 figure 13. tx eye diagram at tp3, pe = 6 db (cable = 10 meters, 24 awg) ad8195 rev. 0 | page 10 of 20 t a = 27c, avcc = 3.3 v, vtti = 3.3 v, vtto = 3.3 v, avee = 0 v, differential input swing = 1000 mv, pattern = prbs 2 7 ? 1, data rate = 2.25 gbps, tmds outputs terminated with external 50 resistors to 3.3 v, unless otherwise noted. 25 0.6 0.5 0.4 0.3 0.2 0.1 0 0 5 10 15 20 jitter (ui) input cable length (m) all cables = 24 awg 480p, 8-bit 720p/1080i, 8-bit 1080p, 8- bit 1.65gbps 1080p, 12- bit 07049-114 figure 14. jitter vs. input cable length (see figure 4 for test setup) 2.42.22.0 1.81.61.41.21.0 0.80.60.40.2 50 40 30 20 10 0 0 jitter (ps) data rate (gbps) rj rms dj p-p 07049-115 figure 15. jitter vs. data rate 3.6 3.5 3.4 3.3 3.2 3.1 3.0 50 40 30 20 10 0 jitter (ps) supply voltage (v) rj rms dj p-p 07049-116 figure 16. jitter vs. supply voltage 16141210 8642 0.6 0.5 0.4 0.3 0.2 0.1 0 0 jitter (ui) output cable length (m) 1080p, 12-bit 1080p, 8-bit 1.65gbps 720p/1080i, 8-bit 480p, 8-bit all cables = 24 awg pe = 6db 07049-117 figure 17. jitter vs. output cable length (see figure 9 for test setup) 2.42.22.0 1.81.61.41.21.0 0.80.60.40.2 1.2 1.0 0.8 0.6 0.4 0.2 0 0 eye height (v) data rate (gbps) 07049-118 figure 18. eye height vs. data rate 3.6 3.5 3.4 3.3 3.2 3.1 3.0 eye height (v) supply voltage (v) 1.2 1.0 0.8 0.6 0.4 0.2 0 07049-119 figure 19. eye height vs. supply voltage ad8195 rev. 0 | page 11 of 20 t a = 27c, avcc = 3.3 v, vtti = 3.3 v, vtto = 3.3 v, avee = 0 v, differential input swing = 1000 mv, pattern = prbs 2 7 ? 1, data rate = 2.25 gbps, tmds outputs terminated with external 50 resistors to 3.3 v, unless otherwise noted. 2.0 1.5 1.0 0.5 80 70 60 50 40 30 20 10 0 0 jitter (ps) differential input voltage swing (v) dj p-p rj rms 07049-120 figure 20. jitter vs. differential input voltage swing 85 60 35 10 ?15 50 40 30 20 10 0 ?40 jitter (ps) temperature (c) dj p-p rj rms 07049-121 figure 21. jitter vs. temperature 07049-122 120 100 80 60 40 20 0 rise/fall time 20% to 80% (ps) ?40 ?20 0 20 40 60 80 temperature (c) rise fall figure 22. rise and fall time vs. temperature 3.7 3.3 3.5 3.1 2.9 2.7 50 45 35 40 30 25 20 15 10 5 0 2.5 jitter (ps) input common-mode voltage (v) dj p-p rj rms 07049-123 figure 23. jitter vs. input common-mode voltage 100 80 60 40 20 0 ?20 120 115 110 105 100 95 90 85 80 ?40 temperature (c) differential input resistance ( ? ) 07049-124 figure 24. differential input resistance vs. temperature 10 987654321 0.5 0.4 0.3 0.2 0.1 0 0 load current (ma) ddc/cec output logic low voltage; v ol (v) 07049-125 figure 25.ddc/cec outp ut logic low voltage (v ol ) vs. load current ad8195 rev. 0 | page 12 of 20 theory of operation introduction the primary function of the ad8195 is to buffer a single (hdmi or dvi) link. the hdmi or dvi link consists of four differential, high speed channels and three auxiliary single-ended, low speed control signals. the high speed channels include a data-word clock and three transition minimized differential signaling (tmds) data channels running at 10 the data-word clock frequency for data rates up to 2.25 gbps. the three low speed control signals consist of the display data ch annel (ddc) bus (sda and scl) and the consumer electronics control (cec) line. all four high speed tmds channels are identical; that is, the pixel clock can be run on any of the four tmds channels. receive channel compensation is provided for the high speed channels to support long input cables. the ad8195 also includes selectable preemphasis for driving high loss output cables. in the intended application, the ad8195 would be placed between a source and a sink, with long cable runs on the input and output. input channels each high speed input differential pair terminates to the 3.3 v vtti power supply through a pair of single-ended 50 on-chip resistors, as shown in figure 26 . when the transmitter of the ad8195 is disabled by setting the tx_en control pin, the input termination resistors are also disabled to provide a high impedance node at the tmds inputs. the input equalizer provides 12 db of high frequency boost. no specific cable length is suggested for this equalization level because cable performance varies widely between manufacturers; however, in general, the ad8195 does not degrade or over- equalize input signals, even for short input cables. the ad8195 can equalize more than 20 meters of 24 awg cable at 2.25 gbps, over reference cables that exhibit an insertion loss of ?15 db. cable eq 50 ? 50? ipx tx_en inx avee v tti 0 7049-004 figure 26. high speed input simplified schematic output channels each high speed output differential pair is terminated to the 3.3 v vtto power supply through two single-ended 50 on-chip resistors (see figure 27 ). the output termination resistors of the ad8195 back terminate the output tmds transmission lines. these back terminations, as recommended in the hdmi 1.3a specification, act to absorb reflections from impedance discontinuities on the output traces, improving the signal integrity of the output traces and adding flexibility to how the output traces can be routed. for example, interlayer vias can be used to route the ad8195 tmds outputs on multiple layers of the pcb without severely degrading the quality of the output signal. the ad8195 has an external control pin, tx_en, that disables the transmitter, reducing power when the transmitter is not in use. additionally, when the transmitter is disabled, the input termination resistors are also disabled to present a high impedance state at the input and indicate to any connected hdmi sources that the link through the ad8195 is inactive. table 7. transmitter enable setting tx_en function 0 tx/input termination disabled 1 tx/input termination enabled the ad8195 also includes two levels of programmable output preemphasis, 0 db and 6 db. the output preemphasis level can be manually configured by setting the pe_en pin. no specific cable length is suggested for use with either preemphasis setting, as cable performance varies widely among manufacturers. table 8. preemphasis setting pe_en pe boost 0 0 db 1 6 db v tto 50 ? 50 ? opx onx avee i out 0 7049-005 figure 27. high speed output simplified schematic ad8195 rev. 0 | page 13 of 20 preemphasis the preemphasized tmds outputs precompensate the trans- mitted signal to account for losses in systems with long cable runs. these long cable runs selectively attenuate the high frequency energy of the signal, leading to degraded transition times and eye closure. similar to a receive equalizer, the goal of the preemphasis filter is to boost the high frequency energy in the signal. however, unlike the receive equalizer, the preemphasis filter is applied before the channel, thus predistorting the transmitted signal to account for the loss of the channel. the series connection of the preemphasis filter and the channel results in a flatter frequency response than that of the channel, thus leading to improved high frequency energy, improved transition times, and improved eye opening on the far end of the channel. using a preemphasis filter to compensate for channel losses allows for longer cable runs with or without a receiver equalizer on the far end of the channel. in the case that there is no receive equalizer on the far end of the channel, the preemphasis filter should allow longer cable runs than would be acceptable with no preemphasis. in the case of both a preem- phasis filter on the near end and a receive equalizer on the far end of the channel, the allowable cable run should be longer than either compensation could achieve alone. the pulse response of a preemphasized waveform is shown in figure 28 . the output voltage levels and symbol descriptions are listed in table 9 and table 10 , respectively. v ocm v h v l v ose-boost v tto v ose-dc ad8195 rev. 0 | page 15 of 20 07049-007 0.01f 0.01f 47k ? 47k ? 1k ? 5 v 3.3 v ddc_scl ddc_sda tmds tmds 2k ? esd protection (optional) amuxvcc avcc, vtti, vtto edid eeprom hdmi receiver scl_out sda_out scl_in sda_in cec mcu 3.3v or 5v vref_out 2k? 2k? 3k? ipa3 ina3 ipa2 ina2 ipa1 ina1 ipa0 ina0 op3 on3 op2 on2 op1 on1 op0 on0 cec_in cec_out avee ad8195 d2+ d2? d1+ d1? d0+ d0? clk+ clk? vref_in amuxvcc 1f 0.01f amuxvcc cable or pcb interconnect edid eeprom typical edid placement optional edi d placement hdmi connector d2+ d2? d1+ d1? d0+ d0? clk+ clk? 5v ddc_scl ddc_sda cec hpd 6k ? comp 10f figure 30. ad8195 typical application simplified schematic cable lengths and equalization the ad8195 offers 12 db of equalization for the high speed inputs. the equalizer of the ad8195 is optimized for video data rates of 2.25 gbps and can equalize more than 20 meters of 24 awg hdmi cable at the input for data rates corresponding to the video format 1080p with deep color. the length of cable that can be used in a typical hdmi/dvi application depends on a large number of factors, including the following: ? cable quality: the quality of the cable in terms of conductor wire gauge and shielding. thicker conductors have lower signal degradation per unit length. ? data rate: the data rate being sent over the cable. the signal degradation of hdmi cables increases with data rate. ? edge rates: the edge rates of the source input. slower input edges result in more significant data eye closure at the end of a cable. ? receiver sensitivity: the sensitivity of the terminating receiver. tmds output rise/fall times the tmds outputs of the ad8195 are designed for optimal performance even when external components are connected, such as external esd protection, common-mode filters, and the hdmi connector. in applications where the output of the ad8195 is connected to an hdmi output connector, additional esd protection is recommended. the capacitance of the addi- tional esd protection circuits for the tmds outputs should be as low as possible. in a typical application, the output rise/fall times are compliant with the hdmi 1.3a specification at the output of the hdmi connector. pcb layout guidelines the ad8195 is used to buffer two distinctly different types of signals, both of which are required for hdmi and dvi video. these signal groups require different treatment when laying out a pcb. the first group of signals carries the audiovisual (av) data encoded by a technique called transition minimized differential signaling (tmds) and, in the case of hdmi, is also encrypted according to the high bandwidth digital copy protection (hdcp) standard. hdmi/dvi video signals are differential, unidirectional, and high speed (up to 2.25 gbps). the channels that carry the video data must have controlled impedance, be terminated at the receiver, and be capable of operating up to at least 2.25 gbps. it is especially important to note that the differential traces that carry the tmds signals should be designed with a controlled differential impedance of 100 . the ad8195 provides single- ended 50 terminations on chip for both its inputs and outputs. transmitter termination is not fully specified by the hdmi standard, but its inclusion improves the overall system signal integrity. the second group of signals consists of low speed auxiliary control signals used for communication between a source and a sink. these signals include the ddc bus (this is an i 2 c bus used to send edid information and hdcp encryption keys between the source and the sink) and the consumer electronics control (cec) line. these auxiliary signals are bidirectional, low speed, ad8195 rev. 0 | page 16 of 20 and transferred over a single-ended transmission line that does not need to have controlled impedance. the primary concern with laying out the auxiliary lines is ensuring that they conform to the i 2 c bus standard and do not have excessive capacitive loading. tmds signals in the hdmi/dvi standard, four differential pairs carry the tmds signals. in dvi, three of these pairs are dedicated to carrying rgb video and sync data. for hdmi, audio data is also interleaved with the video data; the dvi standard does not incorporate audio information. the fourth high speed differential pair is used for the av data-word clock and runs at one-tenth the speed of the tmds data channels. the four high speed channels of the ad8195 are identical. no concession was made to lower the bandwidth of the fourth channel for the pixel clock, so any channel can be used for any tmds signal. the user chooses which signal is routed over which channel. additionally, the tmds channels are symmetric; therefore, the p and n of a given differential pair are interchange- able, provided the inversion is consistent across all inputs and outputs of the ad8195. however, the routing between inputs and outputs through the ad8195 is fixed. for example, input channel 0 is always buffered to output channel 0, and so forth. the ad8195 buffers the tmds signals, and the input traces can be considered electrically independent of the output traces. in most applications, the quality of the signal on the input tmds traces is more sensitive to the pcb layout. regardless of the data being carried on a specific tmds channel, or whether the tmds line is at the input or the output of the ad8195, all four high speed signals should be routed on a pcb in accordance with the same rf layout guidelines. layout for the tmds signals the tmds differential pairs can be either microstrip traces, routed on the outer layer of a board, or stripline traces, routed on an internal layer of the board. if microstrip traces are used, there should be a continuous reference plane on the pcb layer directly below the traces. if stripline traces are used, they must be sandwiched between two continuous reference planes in the pcb stack-up. additionally, the p and n of each differential pair must have a controlled differential impedance of 100 . the characteristic impedance of a differential pair is a function of several variables, including the trace width, the distance separating the two traces, the spacing between the traces and the reference plane, and the dielectric constant of the pcb binder material. interlayer vias introduce impedance discontinuities that can cause reflections and jitter on the signal path; therefore, it is preferable to route the tmds lines exclusively on one layer of the board, particularly for the input traces. in addition, to prevent unwanted signal coupling and interference, route the tmds signals away from other signals and noise sources on the pcb. both traces of a given differential pair must be equal in length to minimize intrapair skew. maintaining the physical symmetry of a differential pair is integral to ensuring its signal integrity; excessive intrapair skew can introduce jitter through duty cycle distortion (dcd). the p and n of a given differential pair should always be routed together in order to establish the required 100 differential impedance. enough space should be left between the differential pairs of a given group so that the n of one pair does not couple to the p of another pair. for example, one technique is to make the interpair distance 4 to 10 times wider than the intrapair spacing. any group of four tmds channels (input or output) should have closely matched trace lengths to minimize interpair skew. severe interpair skew can cause the data on the four different channels of a group to arrive out of alignment with one another. a good practice is to match the trace lengths for a given group of four channels to within 0.05 inches on fr4 material. the length of the tmds traces should be minimized to reduce overall signal degradation. commonly used pcb material such as fr4 is lossy at high frequencies, so long traces on the circuit board increase signal attenuation, resulting in decreased signal swing and increased jitter through intersymbol interference (isi). controlling the characterist ic impedance of a tmds differential pair the characteristic impedance of a differential pair depends on a number of variables, including the trace width, the distance between the two traces, the height of the dielectric material between the trace and the reference plane below it, and the dielectric constant of the pcb binder material. to a lesser extent, the characteristic impedance also depends upon the trace thickness and the presence of solder mask. there are many combinations that can produce the correct characteristic impedance. it is generally required to work with the pcb fabricator to obtain a set of parameters to produce the desired results. one consideration is how to guarantee a differential pair with a differential impedance of 100 over the entire length of the trace. one technique is to change the width of the traces in a differential pair based on how closely one trace is coupled to the other. when the two traces of a differential pair are close and strongly coupled, they should have a width that produces a 100 differential impedance. when the traces split apart to go into a connector, for example, and are no longer so strongly coupled, the width of the traces should be increased to yield a differential impedance of 100 in the new configuration. ad8195 rev. 0 | page 17 of 20 tmds terminations the ad8195 provides internal 50 single-ended terminations for all of its high speed inputs and outputs. it is not necessary to include external termination resistors for the tmds differential pairs on the pcb. the output termination resistors of the ad8195 back terminate the output tmds transmission lines. these back terminations act to absorb reflections from impedance discontinuities on the output traces, improving the signal integrity of the output traces and adding flexibility to how the output traces can be routed. for example, interlayer vias can be used to route the ad8195 tmds outputs on multiple layers of the pcb without severely degrading the quality of the output signal. auxiliary control signals there are three single-ended control signals associated with each source or sink in an hdmi/dvi application. these are consumer electronics control (cec) and two display data channel (ddc) lines. the two signals on the ddc bus are sda and scl (serial data and serial clock, respectively). these three signals can be buffered through the ad8195 and do not need to be routed with the same strict considerations as the high speed tmds signals. in general, it is sufficient to route each auxiliary signal as a single-ended trace. these signals are not sensitive to impedance discontinuities, do not require a reference plane, and can be routed on multiple layers of the pcb. however, it is best to follow strict layout practices whenever possible to prevent the pcb design from affecting the overall application. the specific routing of the cec and ddc lines depends on the application in which the ad8195 is being used. for example, the maximum speed of signals present on the auxiliary lines is 100 khz i 2 c data on the ddc lines; therefore, any layout that enables 100 khz i 2 c to be passed over the ddc bus should suffice. the hdmi 1.3a specification, however, places a strict 50 pf limit on the amount of capacitance that can be measured on either sda or scl at the hdmi input connector. this 50 pf limit includes the hdmi connector, the pcb, and whatever capacitance is seen at the input of the ad8195. there is a similar limit of 150 pf of input capacitance for the cec line. the parasitic capacitance of traces on a pcb increases with trace length. to help ensure that a design satisfies the hdmi specification, the length of the cec and ddc lines on the pcb should be made as short as possible. additionally, if there is a reference plane in the layer adjacent to the auxiliary traces in the pcb stack-up, relieving or clearing out this reference plane immediately under the auxiliary traces significantly decreases the amount of parasitic trace capacitance. an example of the board stack-up is shown in figure 31 . pcb dielectric layer 1: microstrip silkscreen silkscreen pcb dielectric pcb dielectric layer 2: reference plane layer 3: reference plane layer 4: microstrip w 3w 3w reference layer relieved underneath microstrip 0 7049-009 figure 31. example board stack-up the ad8195 buffers the auxiliary signals; therefore, only the input traces, connector, and ad8195 input capacitance must be considered when designing a pcb to meet hdmi specifications. power supplies the ad8195 has four separate power supplies referenced to a single ground, avee. the supply/ground pairs are ? avc c /avee ? vtti/avee ? vtto/avee ? amuxvcc/avee. the avcc/avee (3.3 v) supply powers the core of the ad8195. the vtti/avee supply (3.3 v) powers the input termination (see figure 26 ). similarly, the vtto/avee supply (3.3 v) powers the output termination (see figure 27 ). the amuxvcc/ avee supply (5 v) powers the auxiliary buffer core. in a typical application, all pins labeled avee should be connected directly to ground. all pins labeled avcc, vtti, or vtto should be connected to 3.3 v, and pin amuxvcc should be tied to 5 v. the avcc supply powers the tmds buffers while amuxvcc powers the ddc/cec buffers. amuxvcc can be connected to the +5 v supply provided from the input hdmi connector to ensure that the ddc and cec buffers remain functional when the system is powered off. the supplies can also be powered individually, but care must be taken to ensure that each stage of the ad8195 is powered correctly. ddc reference inputs the vref_in and vref_out voltages (3.3 v to 5 v) provide reference levels for the ddc buffers. both voltages are referenced to avee. the voltage applied at these reference inputs should be the same as the pull-up voltage for corresponding ddc bus. ad8195 rev. 0 | page 18 of 20 outline dimensions 1 40 10 11 31 30 21 20 4.25 4.10 sq 3.95 top view 6.00 bsc sq pin 1 indicator 5.75 bsc sq 12 max 0.30 0.23 0.18 0.20 ref seating plane 1.00 0.85 0.80 0.05 max 0.02 nom coplanarity 0.08 0.80 max 0.65 typ 4.50 ref 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bot tom view) compliant to jedec standards mo-220-vjjd-2 072108-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 32. 40-lead lead frame chip scale package [lfcsp_vq] 6 mm 6 mm body, very thin quad (cp-40-1) dimensions shown in millimeters ordering guide model temperature range package description package option ordering quantity AD8195ACPZ 1 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 AD8195ACPZ-r7 1 ?40c to +85c 40-lead lead frame chip scale pa ckage [lfcsp_vq], 7 tape and reel cp-40-1 750 ad8195-evalz 1 evaluation board 1 z = rohs compliant part. ad8195 rev. 0 | page 19 of 20 notes ad8195 rev. 0 | page 20 of 20 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associ ated companies conveys a license for the purchaser under the phil ips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips . ?2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07049-0-8/08(0) |
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