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p r e l i min ar y cd24011a.fm 1 vision v v 6850 & VV5850 monolithic sensors high resolution cmos image sensor with support for external fpn product datasheet revision 1.0 distinctive characteristics general description cancellation and serial interface control, available in colour (6850) and block diagram monochrome (5850) versions. the vv6850 and VV5850 are highly inte- grated cmos camera devices. the devices both incorporate a 1016 x 804 pixel array image sensor configured to produce line by line pixel output for external digitisation and storage. the vv6850 is colourised in a red, green, blue bayer pattern, whereas the VV5850 is uncolourised. both are suitable for still image capture applications, and applications requir- ing digitisation of the pixel image. all clocking and sequencing control signals are user-defined, giving maximum flexibility of use. a two way serial interface and internal control register provide further control and monitoring of camera functions, giving many image capture operating modes. exposure control can be achieved with or without an electromechanical shutter, and (external) frame/line buffering and processing enables effective fixed pattern noise cancella- tion. image format 800 x 992 pixels pixel size 10.8 m m x 10.8 m m array size 8.640mm x 10.951mm sensitivity (colour) 50mv/lux @ 50ms exp. s/n typically 66db (with fpn cancellation) max. pixel rate 10mpix/s (5mpix/s for 0.1% settling) power supply 5v 5% power < 150 mw temperature 0 o c - 40 o c ? ? high resolution (800k) cmos sensor designed for use in digital colour stills cameras and machine vision applica- tions ? versatile operating modes, including live video/cine mode for viewfinder applications, and exposure monitoring modes ? digital control of pixel reading for flexibil- ity, including external adc interface ? control/configuration via serial interface ? external frame/line buffering schemes offer effective pixel offset cancellation and low noise operation ? bayer pattern r,g,b colourisation (other patterns/colours can be accommodated) ? monochrome version available - VV5850 - functionally identical to the vv6850, but with higher sensitivity ? low power operation (125mw typical) ? industry standard 84 pin lcc package 6$03/( +2/' +25,=217$/ 6+,)7 5(*,67(5 9,'(2 287387 67$*( 3+272',2'( $55$< 5() 92/7$*(6 &21752/ &&76 957 9eowz 9eorrp 9575hi 9eorrpuhi &2/6dp 9eowzuhi 9%* $92 9(57,&$/ 6+,)7 5(*,67(56 )5 '287 6(5,$/ ,) '/$7 '&. ',1 3;5' &'65 (9:7 5(6(7% %lw '$& &21752/ 5(*,67(5 $925hi /&. (9(1 ), 9&/5% 96(7% 3&. /6 (& +&/5% &lqh 6(/5hi 6$05hi &/$03 9&/ 9&/ 81%8))(5(' ;
pre l imi n ar y 2 16/06/97 vision v v 6850 & 5850 sensors: product datasheet revision 1.0 spectral response 400 500 600 700 800 900 1000 1100 1.0 0.8 0.6 0.4 0.2 wavelength, nm normalised response basic cmos response 0 ir filter (lens) sensor with ir filter 400 500 600 700 red green blue 1.0 0.8 0.6 0.4 0.2 0 with ir filter only sensor response wavelength, nm 350 450 550 650 colourisation filter responses (of rgb normalised response bayer pattern colour set 1). response of other colourisation patterns tbd. contents page main features 3 sensor architecture 4 video output 8 operating modes 12 control register & serial comms. 20 detailed operational timings 25 specifications 33 package details and pinout 35 example support circuits 38 appendix - fpn schemes 40
pre l imi n ar y 16/06/97 3 main features main features timing dsp i/o processing frame buffer picture storage lens sensor adc exposure control shutter flash asic/dsp typical application (image/colour processing) timing & control serial data the vv6850 sensor has been developed specifically for use in image processing appli- cations requiring pixel by pixel access. flexi- ble control options allow many operating modes, but the vv6850 is ideally suited to digital stills cameras with electromechanical shutter exposure control and a frame store memory available for pixel offset cancellation. note: the VV5850 monochrome sensor is identical in operation to the vv6850, but with higher sensitivity and simpler image process- ing, due to the absence of colour filters. pixel array the pixel array is colourised in a four pixel, red, green, blue bayer arrangement. this provides high colour fidelity images with low colour aliasing. (other colourisation schemes can be produced to suit specific application needs.) the pixel array includes a number of reference lines, and a useable image area of 992 x 800 valid video pixels. pixel access is by row and column shift regis- ters. each row of pixels, or line, is read at the same instant, and stored in a sample-and- hold stage. the columns are then read out alternately, and multiplexed through four output channels to the avo output stage. the image can then be unshuffled and recon- structed in external buffering and processing circuits. this scheme provides avo settling to better than 0.1% at a sampling rate of 5 msps. (higher sampling rates are possible, with reduced settling accuracy. video output the multiplexed column outputs are buffered to the analogue video output (avo) pin, as inverted video, that is black is higher than white. an avoref output is also generated, from the internal black reference level, to provide a pseudo differential output pair. a dc component is added to the avo and avoref signals at the ac coupled output stages by clamping these to vcl1 and vcl2, one of which can be set by an internal dac. this allows the avo level to be matched to the input range of an external adc. serial interface the serial interface allows an external control- ler to set certain parameters and to determine the vv6850s current state. this is done through the control register, which is loaded from din and examined at dout. the vv6850 receives serial data as one 22- bit data word, the 20 msb of which are clocked into a shift register. the shift register contents can then be latched into the control register.
pre l imi n ar y 4 cd24011a.fm vision v v 6850 & 5850 sensors: product datasheet revision 1.0 sensor architecture the vv6850 image sensor comprises an array of 1016 (vertical, lines) by 804 (horizontal) active photodiode cells feeding into a row of column source followers at the top of the pixel array. these columns are then in turn multiplexed on to four output channels, and finally onto the avo output. exposure, that is pixel integration time, is controlled by a reset vertical shift register with pixel readout controlled by the read vertical and horizontal shift registers. the first (bottom) line of the array is used internally, and is not read out. the next 6 lines are black reference lines. then there are 8 colour characterisation lines, 992 valid video lines and 8 more colour characterisation lines. at the top of the pixel array there is one more extra line which is not read out. the outer two columns on the left and right sides of the pixel array are also internal refer- ences, and not read out. thus the usable image area of the 1016 x 804 array is 992 x 800 pixels. 5-bit dac o/p fi, fr ls read vertical shift register - row select reset vertical shift register column amplifiers & sample/hold horizontal shift register - column select pixel array (804x1016) stage output buffers first pixel to be read out black reference 8x8 pixels top avo avoref line scan (0 - 802; 1 - 803) frame scan 0-even 1-even 2-even serial data 0-odd 1-odd 1013 0 2 4 1 3 5 first line } second line } g g r bayer colourisation b
pre l imi n ar y 16/06/97 5 sensor architecture reset and read vertical shift registers the resetting and reading of pixels is performed on a line by line basis, that is a row of column amplifiers reads a whole line of pixel voltages in parallel. the reset/integrate/read cycle for a line of pixels is controlled by the reset vertical and read vertical shift registers (vsrs). the length of the frame integrate pulse, fi, propagating along the reset vertical shift register sets the pixel integration time. fi going high at a point along the vsr releases that line of pixels from reset, starting the integration period. the two-line frame read pulse, fr, which comes at the end of the integrate period, starts the field readout, which proceeds from bottom to top. as fr propagates along the read vertical shift register, it controls which line is to be read. for exposure control by means of a shutter mechanism, fi should be held high throughout the frame integrate/read cycle. the vertical shift registers are clocked by the line clock pulse, lck. within a frame, first an even line, then an odd line is read. this is controlled by the even clock, which must be half the lck frequency and change two pcks before ls (line start) rises. a pair of lines may be skipped over (for example as in cine modesee: h orizontal s hift r egister ), by inserting two lck pulses and one even pulse between line readout sequences. . note: if fr does not rise with the rising edge of even, that is if even is high during the second line period of the fr pulse, the avo-valid line readout sequence is offset by one line. further control of the vsrs is effected by: vclrb (clear reset and read); vsetb (preset reset to ones); cdsr (reset row, but do not advance vsrs). the pxrd input to the read vsr enables a line of pixels to be read out. (see: o perating m odes for more details.) the first six lines in the array are black reference lines. the reset/integrate cycle for these lines is controlled by a third shift register, defined by bits cr[4] and cr[3] in the control register (see: c ontrol r egister /s erial d ata i nterface ). this shift register can either hold the black reference lines in permanent reset, allow minimum exposure or have the same integration time (exposure) as the rest of the array. the readout sequence, initiated by fr going high, is therefore: six black lines followed by eight colour characterisation lines, 992 valid video lines and another eight colour characterisation lines. for cine this becomes: four black lines, four colour characterisation, 496 valid video lines and four colour characterisation lines lck fi fr even avo valid video line black ref line avo not valid 1014 lines exposure
pre l imi n ar y 6 cd24011a.fm vision v v 6850 & 5850 sensors: product datasheet revision 1.0 horizontal shift register the horizontal shift register is clocked by the pixel clock, pck. columns are read out, from left to right, by the line start pulse, ls, propagating along the horizontal shift register. the ls pulse must be four pck periods long, with the first valid pixel being sampled after the falling edge (see d etailed t iming for exact relationship). to avoid bandwidth limitations within the output stage causing cross talk problems between the colours in a colour pixelated sensor, the horizontal shift register either reads out the odd or the even columns, under control of the ec signal. in order to read valid pixel data, the pixel read input to the read vsr, pxrd, must be high. (to skip lines, for example as in cine mode, pxrd must be held low during the two extra lck peri- ods.) when reading out either the even columns (ec=1) or the odd columns (ec=0) it is the central 400 pixels of the 402 pixels read out that are valid. in cine mode (selected with bit cr[3] in the control register), every second pixel within a row is read out; of the 202 pixels read out for either ec=1 or ec=0, the central 200 pixels are valid. the hclrb input (active low) clears the hsr to all zeros. hclrb can also be used, for example, to prematurely end a line scan, perhaps when only part of the image is required. note: the power-on reset signal, rstb, should be used to drive hclrb (and vclrb for the vertical shift registers) at power up. pxrd lck ls ec even even line odd line even line pxrd lck ls ec even even line odd line cine mode: avo even pixels odd pixels even pixels odd pixels skip two lines avo even odd even odd even odd
pre l imi n ar y 16/06/97 7 sensor architecture pixel read schematic bit-line, vx[m] pixel array avo pck reset[n] horizontal shift register d pix v pix bitline test/clamp circuitry hclrb vrt column[m] read[n] cr[0] vbltw cr[1] c pix pixel[m,n] cs[m] ls cs[401:0] output channel 0 output channel 1 output stage cso[401:0] cse[401:0] ec colsam output channel 2 output channel 3 ec vrt samref line reference avoref output channel clamp selref clamp cine vrt read[m] read vertical shift register reset vertical shift register fr fi lck vsetb vclrb pxrd even vbloom cdsr sample/hold source follower
pre l imi n ar y 8 cd24011a.fm vision v v 6850 & 5850 sensors: product datasheet revision 1.0 video output the four-pck long ls pulse initiates output of a line of video, with the first valid pixel being sampled after ls falls, and subsequent pixels appearing at avo as ls propagates along the hori- zontal shift register. the avo output for each pixel should then be sampled as close to the end of the pck cycle as possible to allow maximum settling time. the video output chain at the top of each column of the array is a sample and hold stage (controlled by colsam), which drives the output stage. the purpose of the sample & hold is to ensure that all the pixels in a line have the same exposure, as the outputs of a row of pixels are sampled at the same instant. if colsam is not used then each pixel will carry on integrating until it is read out. therefore, since all pixels within a line are released from reset at the same time, each pixel will have a different integration time, and hence exposure value. the columns are read out via four output channels. each channel is multiplexed onto the avo pin via an ac coupling stage to restore the dc content. the avoref pin provides a pseudo-differen- tial output, obtained from an internal black reference. (the pseudo-differential output stage cancels out leakage across the coupling capacitors since both output channels experience the same rate of decay.) note: the video at avo is inverted, that is black is higher than white. pixel level sampling ls pck avo avo output has settled pck [r] changes pixel pck [r] samples ls first valid pixel after ls is sampled on avo ? pck max. @ 5mhz
pre l imi n ar y 16/06/97 9 video output avo reference the dc content of the output stage is set by using the selref signal to simultaneously put the internal reference on the avo and avoref output channels, and then the clamp signal to charge the amplifier side of the coupling stages to vcl1 and vcl2 respectively. the integrated 5-bit dac, controlled by control register bits cr[15..11], can be used to adjust one or other of these clamping voltages. the clamp signal must fall before selref falls. the ac coupling capacitors must be refreshed at least once every still image capture sequence, or every frame of a live video. the sensors internal black reference, which drives the avoref output path, is derived from a separate 8 by 8 array of pixels connected in parallel. the input voltage to all pixels in the 8 by 8 array is vrt, that is the pixels are in reset. a sample & hold stage controlled by samref allows the vrt voltage driving the black reference pixels to be sampled, freezing the black reference value. normally the black level reference should be updated between every still image capture sequence or between every frame in live video mode. under very high illumination, however, the black refer- ence should be sampled between every line in live video mode. the internal black reference can be sampled at the beginning of a frame using samref. it can also be observed line by line by asserting selref (without clamp) in the dead period between reading rows of pixels out onto avo. avo selref white black peak clamp avo vcl2 vcl1 clamp avoref vrt 8x8 pixels samref pixel array + columns black reference selref 2:1
pre l imi n ar y 10 cd24011a.fm vision v v 6850 & 5850 sensors: product datasheet revision 1.0 the 5-bit dac the internal five bit resistive ladder dac is energised by a bias generator that is set by the inter- nal bandgap voltage reference, vbg, and the external 12k resistor connected from rset to agnd. the vdac output of the dac, which can be used to set either vcl1 or vcl2, is adjusted by bits 11 to 15 of the control register/serial interface. note: the vbg pin is a high impedance output, and can be over-ridden within the vcl input limits. parameter definition value comment vdactop 208/122 * vbg 2.08v vdacbot 176/122 * vbg 1.76v vdac3/4 199/122 * vbg 1.99v vdac cr[15..11] * (32/122 * vbg) - zdac vdac output impedance 21k ohms 25% 5-bit dac parameters 32 analogue vdac cr[15..11] resistive ladder, 32r agnd vdacbot vdactop vdac3/4 176r avcc i = vbg/122r r ~ 100 ohms 12k vbg mux(32:1) bias generator rset 5-bit dac
pre l imi n ar y 16/06/97 11 video output black reference lines there are six lines at the bottom of the pixel array that are covered with opaque masking. these black reference lines have their own reset shift register. a four to one multiplexer, controlled by control register bits cr[4] and cr[3], selects the input to this shift register (fbck), and hence the operating mode. the four modes of operation are: 1. permanent reset - by setting fbck low, the black lines are permanently reset to vrt. 2. minimum integration - fbck follows the field read pulse, fr; the black reference lines are held in minimum exposure. 3. integration - fbck follows the field read pulse, fi; the black reference lines therefore have the same exposure time as the array. 4. permanent integration; the reference lines continue to integrate until reset as in 1. option 1. is the most stable as it does not depend on either the quality of the black shield above the black pixels or any light incident on the pixels. however it is also the least accurate as it does not allow for dark current or the breakthrough of the falling edge of the pixel reset signal onto the pixel capacitance. the resulting reference value will be blacker than black due to the above errors. option 2. is more accurate than option 1. as the effect of the pixel reset signal breakthrough is included, but the effect of total dark current is not included since the black reference pixels are not integrating for the same time as the image section of the pixel array. the reference is, also, now sensitive to the effects of light reaching the black line pixels. option 3. includes the effect of dark current since the black reference pixels are integrating for the same time as the image section of the pixel array. the validity of the reference is, however, now even more sensitive to the effects of light reaching the pixel. option 4. in combination with option 1 allows the exposure time for the black reference lines to be controlled independently of the exposure of the rest of the image. note: for best results, it is recommended that the average of the four central lines of the black reference line group is used to characterise black for the frame. exposure control exposure control is achieved either electronically by varying the fi pulse duration, or directly by means of a shutter arrangement (mechanical, electro-mechanical, electro-optical, and so on). the correct exposure level for any scene can be assessed by processing a trial exposure of the scene, or by utilising the accumulate or parallel integration operating mode. see: o perating m odes for a full description of exposure control.
pre l imi n ar y 12 cd24011a.fm vision v v 6850 & 5850 sensors: product datasheet revision 1.0 operating modes there are five main operating modes for the sensor: ? still image capture with a frame buffer ? correlated double sampling (line by line fpn cancellation) ? live-video/cine modes ? accumulate ? parallel integration these are explained below in outline. the following section provides detailed timing requirements for the various control signals necessary to operate the sensor. removing noise in order to obtain high quality, low noise images from the vv6850 sensor pixel to pixel offset vari- ations, or fixed pattern noise (fpn), must be removed. this can be done by reading the image array more than once, for example reading in the dark to establish a reference for each pixel, then reading the exposed array to collect image plus offset data, then subtracting to remove the offsets. to obtain the lowest noise operation the random pixel reset noise must also be removed. sources of fixed pattern noise the major sources of fixed pattern noise in the sensor that can be cancelled are: ? transistor threshold offsets ? dark current each of the above can be effectively cancelled to a much lower residual random noise level by using the techniques described below. the residual noise sources in the sensor, such as flicker noise, dark current shot noise, thermal noise and adc quantisation noise, that cannot be cancelled, or are a function of the cancellation techniques, define the overall camera noise performance. methods of removing fixed pattern noise transistor threshold offsets each pixel amplifier, each column source follower and each output channel multiplexer, has a unique offset caused by process variations in the threshold voltage of the transistors. this offset is independent of exposure, and will be relatively stable with respect to temperature and operating conditions.to remove transistor threshold fpn, the vv6850 is used in conjunction with an adc and either a frame buffer or a line buffer: ? pixel offset removal frame by frame with a shutter: a frame buffer is used to obtain the pixel to pixel dc offsets for the whole image. the offsets are obtained by capturing a dark (fpn) frame with the shutter closed, and an image frame with the shutter open. the clean image data can then be extracted by subtraction. (this technique can only be used with a physical shutter, and with at least one extra dark frame acquisition period.)
pre l imi n ar y 16/06/97 13 operating modes ? pixel offset removal frame by frame with a reference frame: a non-volatile frame buffer is used to obtain the pixel to pixel dc offsets for the whole image at camera build. these off- sets are then subtracted from the exposed image as it is read to obtain the clean image data. (this technique gives the fastest frame acquisition time at the expense of accuracy.) ? pixel offset removal line by line: a line of pixel information is read and stored in a line buffer. the line is then reset to black using the cdsr signal, before being re-read to obtain the pixel to pixel dc offsets for that line. as the line is re-read the offset data for each pixel is subtracted from the value stored in the line buffer, the result being the image data. (the colsam signal must be used to ensure that samples in the same line have the same inte- gration period.) with line by line offset removal the time for reading out a complete frame is doubled, since each line has to be read twice. it is also not possible to remove pixel reset noise or dark current, thus there is a trade off between the frame rate and image quality, and the amount of memory required. full frame offset removal can be achieved in many ways, depending on what ancillary devices are available in the camera system, and constraints such as image quality required and acceptable minimum frame rate. dark current the dark current in a pixel photodiode is the inherent leakage that discharges the integrating capacitance in the same way as incident light. hence, dark current fpn builds up on the array whenever the array is released from reset, that is when fi is high. this means that the amount of dark signal depends on exposure time, and varies from pixel to pixel. the same degree of dark current charge build-up occurs in the array whether or not the array is exposed to light. therefore, if the array is allowed to integrate (fi high) with no incident light for the same length of time as for the image exposure, the dark current element of the exposed image data can be ascertained and removed from the image data by subtraction, leaving behind the dark current shot noise. since dark current also depends on temperature the dark frame should be taken close in time to the image frame, in order to avoid ambient temperature variations. reset noise cancellation one random noise source that can be cancelled is reset noise (or ktc noise), which is due to the switching of the photodiode capacitance when the pixel is released from reset. this is present in all subsequent reads of the array (without reset) to the same extent. these can therefore be extracted by reading the array immediately after reset (when fi goes high) and subtracting the value obtained from the exposed array data. this operation also cancels pixel threshold offsets. to achieve reset noise cancellation, fr should be taken high for two lck periods when fi goes high, and 1014 lines read before the array is exposed to the required image. the pixel data from this pass of fr through the vsrs must be stored in a frame buffer, and subtracted from the exposed image data. the exposed image is obtained when fr is pulsed high again, coincident with the last two lck periods of fi being high after the exposure period. it is not possible to describe all of the many operating schemes that can be devised for image capture and fpn reduction. the basic recommended modes for camera operation are described below, with detailed timing requirements in the following section.
pre l imi n ar y 14 cd24011a.fm vision v v 6850 & 5850 sensors: product datasheet revision 1.0 still image capture with a frame buffer this is the recommended operational mode for high quality still image capture in camera systems where there is an electro-mechanical shutter in front of the sensor and a frame buffer for tempo- rary image storage. fpn cancellation is central to this mode of operation, and is described in detail. other operational schemes that may be devised can include all or some of the techniques employed in this example, but the elements are essentially the same. (see: a ppendix , a pplication n otes , for a discussion of variations to this fpn cancellation scheme.) note: for the simplest possible image capture mode, with no fpn cancellation, see the descrip- tion of the vertical shift registers above. the basic still image capture cycle starts with the shutter closed. the array is released from reset by taking the input to the reset vertical shift registers, fi, high. the system controlling the camera must then wait for 1014 lines to allow this integrate wavefront to propagate through the shift register, before opening the shutter. when fi goes high fr should also be pulsed high for 2 lines to initiate the read sequence. reading each pixel as soon as it is released from reset yields a reset image which contains both the fixed pattern noise component for each pixel and the random reset noise due to that particular reset operation. this image should be stored in a frame buffer. when the shutter has closed after exposure fr must be pulsed high again for 2 lines to re-read the array and obtain the exposed image data. again, it will take 1014 lines to read all of the array pixels. fi should fall when fr falls, to return the active pixel array into reset. as the image frame is read out the appropriate pixel reset value, as stored in the frame buffer, is subtracted from the current pixel value and the result written to the frame store. this removes both pixel reset noise and pixel to pixel dc offsets from the image. (see d etailed o perational t iming below for exact relationships.) due to the relatively long time taken to read out an image (200 ms, assuming a 5 mhz clock rate), the dark current in each pixel is a significant part of the image data. to remove the fixed pattern noise injected by the dark current a dark image must be captured with the same integration time as the exposed image but with the shutter closed. subtracting the dark image from the exposed image removes the dark current fixed pattern noise, leaving a clean image. this process can be summarised as follows: lck fi 1014 lines fr even avo t 1 =exposure integrate=t 1 1014 lines 1014 lines 1014 lines image frame dark current frame valid video line black ref line avo not valid shutter
pre l imi n ar y 16/06/97 15 operating modes 1. with the shutter closed, release the sensor from reset and immediately read a frame into the buffer memory; this captures the array threshold fpn and reset noise (v reset ) 2. after 1014 line periods, open the shutter and expose the sensor to the required scene (the exposure time can be determined by parallel integration or accumulate see below) 3. close the shutter and immediately read the array; as each pixel is read, subtract the value for that position stored in the frame buffer, and overwrite that pixel location with the difference the memory now contains the image plus dark current fpn (v im + v dark ) 4. after the 1014 line periods of the second read, repeat the image capture cycle, but do not open the shutter; this time, load a second frame buffer with first the v reset value and then the v dark value (after subtraction) 5. after the second integration period, subtract the v dark value for each pixel that is stored in the second frame buffer from the (v im + v dark ) value for that position stored in the first frame buffer and overwrite that pixel location with the result. the frame buffer now contains the corrected image values, which can be processed for colour and so on, then transferred to permanent image storage memory. the pixel voltages for this method are illustrated schematically below: note: since the integrate wavefront must propagate through the vsr, the point at which the open shutter exposure occurs will vary progressively from line to line of the array from close to read2 on the bottom line to close to read1 at the top. reset[n] read[n] v pix vrt v black v white v reset read 2 read 4 v dark1 v im v dark1 shutter exposure not to scale v dark2 v dark2 + + image read 1 read 3 v dark = v dark1 + v dark2
pre l imi n ar y 16 cd24011a.fm vision v v 6850 & 5850 sensors: product datasheet revision 1.0 correlated double sampling (line by line) this is an alternative fpn cancellation mode for camera systems where there is only a line buffer available for temporary image capture, and not necessarily a mechanical shutter in front of the sensor. the method outlined below, using the cdsr signal, relates to a still image capture in a shuttered camera system, but the same principle could also be applied to exposure control with the fi pulse duration in still frame and live video modes. note: this method does not cancel dark current fpn, and as the pixel is reset twice, has two lots of reset noise sources. the array is released from reset by taking the input to the reset vertical shift registers, fi, high. the system controlling the camera must then wait for 1014 lines to allow this integrate wavefront to propagate through the shift register, before opening the shutter (or further extending the fi pulse). after the sensor has been exposed for the appropriate time, fr must be pulsed high for 2 lines to read the pixel array and obtain the exposed image data, which is loaded into the line buffer line by line. when a line of 804 pixels of image data has been read, the cdsr signal is pulsed high to reset the line of pixels to black (without advancing the hsr). colsam is then pulsed to resample the row, and as each pixel is read out this black offset value is subtracted from the value stored in the line buffer and the result passed on as corrected image data. note: during the 992-line image data readout, lck and even must be at least twice their minimum periods (with maximum pck rate of 5.0mhz), to allow for the second line read. (see d etailed o perational t iming below for the exact relationships, and also how cdsr, colsam and pxrd should interact.) lck fi 1014 lines fr even avo exposure 1014 lines read image black ref line avo not valid read black offset cdsr read image & offsets colsam
pre l imi n ar y 16/06/97 17 operating modes live-video & cine modes in the live video mode the effect is similar to a conventional video camera, with a frame rate of just under five frames/second (with a 5 mhz pixel clock). this can be used, for example, to provide a moving viewfinder display for a stills camera. cine mode is similar, but achieves higher frame rates. in live-video mode the exposure level for a frame is controlled electronically by varying the high duration of the fi waveform. the high duration of fi can be varied from 2 lines (minimum expo- sure) in multiples of 2 lines up to 1012 lines (maximum exposure). the falling edge of fi is fixed within the frame, therefore it is the leading edge of fi that must be moved to vary exposure. the field read pulse, fr, must be set high for the 2 lines preceding the falling edge of fi; this means that the fr waveform is identical to the fi waveform for minimum exposure. the neces- sary signal relationships are illustrated below: if a frame buffer is being used to store the pixel to pixel dc offsets the first image captured on entering live-video mode should have minimum exposure to obtain and store pixel offset data. however, if the offset data already exists in memory this step is not required. cine mode selecting cine mode via the serial data control register (cr[2]) subsamples the pixels in a line, reading out only every other pixel pair. (see: h orizontal s hift r egister for details.) cine mode enables higher frame rates to be achieved, for example 20 frames per second (at 5mhz) by also only reading every other line pair . to achieve this, the vertical shift registers must read out 2 lines and then skip the next 2 lines, by inserting 2 extra lck pulses and one extra even pulse between every second line read out. (see: v ertical s hift r egisters for details.) note: it is not essential to skip line pairs in cine mode, if aspect ratio need not be preserved. it is possible to skip more than one line pair, an also to increase pck (up to 10mhz) to further increase frame rate. for high frame rates, it is also best to read a dark frame into memory and subtract the fixed pattern noise as the array is read in order to reduce the frame overhead of either line-rate cds or the shuttered frame-rate cancellation schemes. lck fi 1014 lines (1 frame) fr even avo exposure exposure read pixel offsets live-video frames valid video line black ref line 1014 lines (1 frame) 1014 lines (1 frame) exposure
pre l imi n ar y 18 cd24011a.fm vision v v 6850 & 5850 sensors: product datasheet revision 1.0 parallel integration in this mode all of the pixels in the array are released from reset at the same time. this is achieved using the vclrb and vsetb signals for the vertical shift registers. (vsetb only effects the reset shift register). this can be used to give a quick but crude estimate of correct exposure by, for example, counting lines until a line is reached where all pixels in the line are saturated, then setting exposure to, say, 50% of the integration time taken to reach that line. the sequence of operations is as follows: 1. pulse vclrb low to reset the read and reset vertical shift registers to all zeros; this forces all pixels into reset 2. pulse vsetb low, this loads the reset shift register with all ones, which starts all of the pixels integrating. 3. then fr should be pulsed high for 2 lines to start the array readout. note: vclrb and vsetb must never be taken low at the same time. since all pixels start to integrate at the same time and readout is sequential (line by line), each line of pixels represents a different exposure value. if the fr pulse occurs on the next video line after vsetb goes high then the first valid video line readout will have been exposed for 6 lines (the black reference lines), and the last line of valid video will have been exposed for 1014 lines. valid video line black ref line avo not valid lck fi fr even avo vsetb vclrb
pre l imi n ar y 16/06/97 19 operating modes accumulate in accumulate mode the pixel array is repeatedly re-read without resetting the pixels. this mode is intended for exposure monitoring in conjunction with a flash when light levels are low, and more than one frame time is required to obtain sufficient integration. the array is released from reset by taking fi high. at the same time fr is pulsed high for 2 lines to read out the pixel reset values. then at the required intervals (of not less than 1014 line periods) fr is pulsed high for 2 lines to re-read the array. while the array is being repeatedly re-read fi must stay high. effectively, the successive reads of the array are monitoring the rate of charge accumulation in the pixels. when sufficient integration has occurred to produce, say 50% average saturation, reading can be terminated. the number of frames of exposure required to achieve this can then be used to calcu- late the flash energy required to correctly expose the scene. on the falling edge of fr for the final array read, fi should go low, to return the pixel array into reset. valid video line black ref line avo not valid lck fi 1014 lines fr even avo 1014 lines 1014 lines
pre l imi n ar y 20 cd24011a.fm vision v v 6850 & 5850 sensors: product datasheet revision 1.0 the control register & serial communication the vv6850 includes a full duplex serial interface, and can be controlled and configured by a host processor. data describing the current configuration of the camera is stored in a 20-bit control register. this register can be read from the camera on the serial interface, and can also be written to from the serial interface to change camera operation. when a 22-bit serial interface data word arrives at the camera on din, the first 20 (msb) bits are loaded into a shift register, and the last two bits (r/w) are examined to ascertain if a read oper- ation or a write operation is required. if a write is required (r/w = 00) the contents of the input shift register are transferred to the control register. otherwise, the current contents of the control register is output on dout. (note: in test mode, that is with cr[7..5]>0, certain other signals are monitored by dout and cr[19..0] is not transmitted.) the signals used to effect the serial data interface are: ? din serial data in; din is sampled on the rising edge of dck ? doutserial data output ? dck serial data clock ? dlat serial data latch; transfers the input data word to the control register (for write), and initiates control register output on dout (for cr[7..5]=0) 20-bit shift register control register cr[19..0] din dck dlat dout r/w 20 cr[19..0] 20 20 3 cr[7:5] 8 to 1 multiplexer &
pre l imi n ar y 16/06/97 21 the control register & serial communication serial communication protocol the host must perform the role of a communications master, while the camera acts as a slave receiver and transmitter. communication from host to camera takes the form of a 22-bit data word, with a 20-bit data word returned to the host. since the serial clock (dck, maximum frequency 100khz,) is generated by the host, the host determines the data transfer rate. the host sends the 20 bit control word, most significant bit first, then either holds din high for two clock cycles, to indicate a read, or holds din low for two clock cycles, to indicate a write. the host also takes dlat high for one clock cycle, corresponding to the last bit of the r/w pair. this defines the end of the transfer and latches the data word to the control register, if required (r/ w=00). dlat also (on the next rising edge of dck) transfers the contents of the control register to the shift register, which is then output to dout if cr[7..5] = 0. the data transfer protocol is illustrated below: dlat dck din dout* cr[19] * only valid when cr[7:5] = 000 (default) din dout* control register read timings: control register write timings: cr[18] cr[0] cr[1] cr[19] cr[18] cr[0] cr[1] 20 dck cycles 20 dck cycles cr[19] cr[18] cr[0] cr[1] dlat dck cr[2] cr[17] 20 dck cycles
pre l imi n ar y 22 cd24011a.fm vision v v 6850 & 5850 sensors: product datasheet revision 1.0 the serial data word the 22-bit serial data word consists of the two-bit wide r/w flag, and the 20 bits of control regis- ter data (cr[0..19]. the following tables defines the cr information contained in the messages: cr bit function/comment default 0 bit-line test enable 0 1 bit-line clamp enable 1 2 select cine mode: only every other colour pixel column is output 0 4,3 controls the integration mode for black reference lines 0 7..5 selects the node that dout is monitoring 0 8 enables the sample & hold circuits on the four output channels 0 9 connects the four black reference output channels together; the default is avoref cycling through the four channels 0 10 enable clamping circuitry on the four output channels 1 15..11 d[4..0] - 5-bit resistive dac value; d[4] is msb 16 16 switch in the output stage sample&hold capacitors 0 19..17 reserved 0 d[4] read = 11 d[3] d[2] d[1] d[0] swcp swcp rsh ocle cine ble cle r / w bm[0] bm[1] os[0] os[1] os[2] cr[19] cr[0] cr[9] cr[8] the 22-bit serial data word (msb first) read data format
pre l imi n ar y 16/06/97 23 the control register & serial communication control register definitions the various bits in the control register define operating modes and parameters as follows: cr[0] - bit-line test enable enables testing of the pixel column interconnections. this bit should always be 0. cr[1] - bit-line clamp enable the default is the bit-line clamp enabled, cr[1] = 1, which ensures that if a bit-line goes too low due to a pixel being heavily over-exposed, the bit-line is clamped to vbltw-vtn. note: due to internal variations, the absolute clamp voltage will vary from column to column. thus, care must be taken to ensure that the adc value clips before the bit-line clamp circuits operate otherwise column to column fixed pattern noise will appear in the saturated white regions of the image. cr[2] - cine mode setting cr[2] = 1 forces the horizontal shift register to read out every second red, green or blue pixel in each odd and even field. in this mode 202 pixels instead of 404 pixels are read out per colour per line. (note: the buffer columns on the left and right side of the pixel array are always read out.) cr[8] and cr[16] should also both be low for cine mode. cr[4:3] - black reference line integration mode select cr[4] and cr[3] control the selection of the four possible integration modes to the black reference lines. the table below defines the code associated with each of the four modes. (see: v ideo o utput - b lack r eference l ines for details of these modes.) cr[7:5] - select dout output output to the dout pin is multiplexed under the control of cr[7], cr[6] and cr[5] for test purposes. all three of these bits must be set to zero for image data to be observed on dout. cr[4] cr[3] integration mode for black reference lines 0 0 permanent reset. 0 1 minimum integration (fr) 1 0 same integration time as main array (fi) 1 1 always integrating.
pre l imi n ar y 24 cd24011a.fm vision v v 6850 & 5850 sensors: product datasheet revision 1.0 cr[8] - output channel sample & hold enable the sample and hold circuits in the avo and avoref output stages isolate the capacitive back injection which occurs when an output channel is multiplexed onto the ac coupling capacitor, which changes the nature of the back injection: ? without sample and hold (cr[8] = 0 (default)), the interaction of the back injection and the column output results in the avo overshooting slightly before settling to the desired value ? with sample and hold enabled (cr[8] = 1) the overshoot is eliminated, but the current pixel value will contain a very small contribution from the previous pixel value read out on avo note: cr[16] allows the output channel sample /hold capacitor to be isolated from the signal path. cr[9] - common up the black reference channels there are two options for operating the four black reference output channels: 1. cr[9]=0 : operate with the avoref cycling between each of the four black output channels. avoref will follow the shape of avo as the ac coupling capacitor is cycling in the same way within both output stages. any mismatch between the black reference output channels will appear as a four-cycle pattern on avoref. 2. cr[9]=1 : parallel up the operation of the black output channels. avoref represents the aver- age of the four black output channels. cr[10] - output channel clamp enable setting cr[10] = 1 (default) clamps the four output channels that are multiplexed onto avo to prevent them going beyond the designed operating voltage range. this ensures that each output channel always has enough time to recover from being inactive before outputing pixel data. cr[15:11] - 5-bit resistive dac data value (d[5:0]) data for the internal 5-bit resistive ladder dac (default = 16). cr[15] is the msb. cr[16] - switch in output stage sample/hold capacitors setting cr[16] high isolates the output channel sample/hold capacitors from the signal path. by isolating these capacitors the output channels settle to the desired value in a shorter time. note: cr[16] should only be set high when the output channel sample/holds are disabled. the primary use of this function is in cine mode. in this mode only two of the four output channels are in use. as the two output channels have only half the time to settle, compared with the normal readout sequence, cr[16] should be set high to improve settling of the output channels. cr[19:17] - reserved for future use
pre l imi n ar y 16/06/97 25 detailed operational timing detailed operational timing the following section describes in detail the recommended timing for the primary operating modes. there are many possible timing schemes, with more flexible setup and holds, but the recommended timings are safe. specifically, timing diagrams and tables are given for: ? normal array read ? correlated double sampling (line by line) system clocks line and pixel timing is done in pcks, and all signals should change on the falling edge of pck. the timings in the following tables have been expressed for a 5mhz pck. the symbols [t],[r],[f],[h],[l] signify transitional edge, rising edge, falling edge, high level and low level respectively. line start to pck timing the relative timing of the line start pulse, ls, and the pixel clock, pck, is extremely important for correct sensor operation. ls must be set up at least 20ns after the rising edge of pck, no later than (pck period)/4 after the rising edge of pck, and must be held for four pck cycles. this is illustrated below: min typ max units pck period 100 200 - ns pck duty cycle 40 - 60 % line period 1024 1024 - pcks line period (cine mode) 624 624 - pcks system clocks. ls pck pck [r] changes pixel on avo min: 20ns max: (pck period)/4
pre l imi n ar y 26 cd24011a.fm vision v v 6850 & 5850 sensors: product datasheet revision 1.0 initial power up timing ? on powering up the array should be reset by vclrb and hclrb, to help the settling of the internal references. an internal power-on-reset circuit generates rstb, which can be used to reset the sensor. ? the references vrt and vbg must be stable before the first frame; this will be a function of the decoupling. ? the internal reference and ac coupling stages should be put into sample mode by making selref, samref, and clamp high. ? to ensure that the array is inactive until the first frame on power up fi, fr, ls, pck, lck and even should all be low. note: serial data can only be sent after rstb rises. event timing min typ max units power on reset trigger voltage pu1 - 2.7 - v rstb pulse width pu2-pu1 100 - - us settling time pu4-pu3 10 - - ms recommended start-up timing. vdd fr/fi/ls hclrb/ vrt other references vbg vclrb rstb 4.5v 2.7v pu0 pu1 pu2 pu3 pu4 (rstb should be used to drive hclrb and vclrb to reset the sensor) selref/ samref/ power-up first frame clamp
pre l imi n ar y 16/06/97 27 detailed operational timing inter-frame timing when a frame is to be taken, the first task is to sample the reference with samref. this signal should be held high until the first line, which should be for at least 100us. if possible, samref should be held high between acquisition of still frames. in order to also ensure that the ac coupling stages do not drift, selref and clamp should also be held high. line read-out timing the following diagrams and tables define the relative timings of the various control signals required to read a line of pixels. not all of the signals shown will be required for all modes of oper- ation, but where they are these timing constraints must be observed. timings for correlated double sampling (using cdsr) are given after the standard line read definitions. lck is the master clock for the vertical shift registers, for reading and resetting rows. lck is a latching signal, and latches when high (to be reset on the next pck). the even signal transitions must straddle lck & pxrd, and fi & fr must straddle lck. pxrd must be high when colsam is pulsed. ec & even are not latched, and must therefore remain high while reading valid pixels. the first line of pixel information is read out when the even and fr signals are both high. if the even signal is high during the second line period of fr pulse, the line readout sequence will be offset by one line relative to that outlined in the timing specification. this is due to the fr and fi inputs only being sampled when both lck and even are high. event timing min typ max units samref period f1-f0 100 - - us clamp overlap of samref[f] f2-f1 1 us selref overlap of clamp[f} f3-f2 0.200 us inter frame timings inter frame timings f0 samref clamp selref f1 f2 f3 f4 frame valid pixels
pre l imi n ar y 28 cd24011a.fm vision v v 6850 & 5850 sensors: product datasheet revision 1.0 valid video data avo reference level avo not valid line timings for reading the array. black level peak white 1 line l0 l2 l3 l4 l5 l6 l7 l8 l1 l9 l10 reference level even columns (400 pixels) odd columns (400 pixels) pxrd lck ls ec even selref avo avo colsam cdsr l11 l12 l13 l14 l15 l16 l19 l17 l18 clamp * l20 l21 reference level * clamp is only used if line update of ac coupling is required in cine mode
pre l imi n ar y 16/06/97 29 detailed operational timing description #t pck cycles time (us) selref [r] - start of line l0 0 0 clamp [r] (only if line clamping is being done) l1 1 0.2 even [t] l2 2 0.4 lck [r]) l3 4 0.8 lck [f] l4 5 1.0 pxrd [r] l5 10 2.0 colsam [r] l6 11 2.2 colsam [f] l7 206 41.2 clamp [f] l8 207 41.4 selref [f] l9 208 41.6 ec [r] l10 209 41.8 ls [r] (even pixels) l11 210 42.0 ls [f] (even pixels l12 214 42.8 avo valid, even pixels, start l13 214.5 42.9 avo valid, even pixels, end l14 614.5 122.9 ec [f] l15 616 123.2 ls [r] (odd pixels) l16 617 123.4 ls [f] (odd pixels l17 621 124.2 avo valid, odd pixels, start l18 621.5 124.3 avo valid, odd pixels, end l19 1021.5 204.3 pxrd [f] l20 1023 204.6 end of line l21 1024 204.8 line length l21 - l0 1024 204.8 even [t] - lck [r] setup time l3 - l2 2 0.4 lck duration l4 - l3 1 0.2 lck [f] - pxrd [r] l5 - l4 5 1 pxrd [r] - colsam [r], setup l6 - l5 1 0.2 colsam duration l7 - l6 195 39.0 recommended line timings
pre l imi n ar y 30 cd24011a.fm vision v v 6850 & 5850 sensors: product datasheet revision 1.0 line timing using cdsr the following timing details relate to correlated double sampling on a line by line basis, that is using the cdsr signal to reset a line of pixels without advancing the vsr. the image capture part of the double read is exactly as described above, and all setup times and durations other than cdsr specific times are also identical. see: o perating m odes - c orrelated d ouble s ampling for full details. colsam [r] - clamp [f] l8 - l7 1 0.2 clamp [h] duration l8 - l1 206 41.2 selref [h] duration l9 - l0 208 41.6 selref overlap of clamp l1 - l0 l9 - l8 10.2 selref [f] - ec [r] l10 -l9 1 0.2 colsam (f) - ec (r) c10 -c7 3 0.6 ec [t] - ls [r] : even l11 - l10 l16 - l15 10.2 ls [h] duration 1 (even) duration 2 (odd) l12-l11 l17-l16 4 4 0.8 0.8 ls [f] - first valid even pixel first valid odd pixel l13 - l12 l18 - l17 0.5 0.1 valid pixels - even - odd l14 - l13 l19 - l18 400 80.0 pxrd [f] - selref [r] (next line) l21 - l20 1 0.2 note 1: all input signals should change on the falling edge of pck note 2: for cine mode the valid pixels is reduced from 400 to 200, giving a reduction in line time from 1024 to 624 pcks, all other relative timings remain unchanged description #t pck cycles time (us) recommended line timings
pre l imi n ar y 16/06/97 31 detailed operational timing valid video data avo reference level avo not valid line timings for reading pixel data and the black offset data using the cdsr signal. black level peak white 1 line c10 reference level even columns odd columns pxrd lck ls ec even selref avo avo cdsr reference (400 pixels) (400 pixels) level (400 pixels) black offsets even columns pixel data pixel data colsam c0 c2 c3 c4 c5 c6 c7 c8 c1 c9 c11 c12 c13 c14 c15 c16 c17 c18 c19 c20 c21 c22 c23 c24 c25 c26 c27 c28 c30 c31 c32 c33 c34 c35 (400 pixels) black offsets odd columns c36 c37 c29
pre l imi n ar y 32 cd24011a.fm vision v v 6850 & 5850 sensors: product datasheet revision 1.0 description #t pck cycles time (us) selref [r] - start of line c0 0 0 image line data (exactly as single image capture) c1 1023 204.6 cdsr [r] c21 1028 205.6 cdsr [f] c22 1053 210.6 pxrd [r] c23 1058 211.6 colsam [r} c24 1059 211.8 colsam [f} c25 1254 250.8 ec [r] c26 1257 251.4 ls [r] (even pixels, dark offsets) c27 1258 251.6 ls [f] (even pixels, dark offsets) c28 1262 252.4 avo valid, dark offsets even pixels, start c29 1262.5 252.5 avo valid, dark offsets even pixels, end c30 1662.5 332.5 ec [f] c31 1664 332.8 ls [r] (odd pixels) c32 1665 333.0 ls [f] (odd pixels c33 1669 333.8 avo valid, odd pixels, start c34 1669.5 333.9 avo valid, odd pixels, end c35 2069.5 413.9 pxrd [f] c36 2071 414.2 end of line c37 2072 414.4 line length c37 - c0 2072 414.4 cdsr setup times ls (f) - first valid pixel c13 - c12 (etc.) 0.5 0.1 valid exposed pixels - even - odd c14 - c13 c19 - c18 400 80.0 valid reset pixels - even - odd c30 - c29 c35 - c34 400 80.0 cdsr [h] duration c22 - c21 25 5.0 note: for cine mode the valid pixels is reduced from 400 to 200, giving a reduction in line time from 2072 to 1272 pcks, all other relative timings remain unchanged recommended line timings using cdsr
pre l imi n ar y 16/06/97 33 specifications specifications absolute maximum ratings note: stresses exceeding the absolute maximum ratings may induce failure. exposure to absolute maximum ratings for extended periods may reduce reliability. functionality at or above these conditions is not implied. dc operating conditions note 1.digital and analogue outputs unloaded. parameter value supply voltage -0.5 to +7.0 volts voltage on other input pins -0.5 to v dd + 0.5 volts temperature under bias -15 o c to 85 o c storage temperature -30 o c to 125 o c maximum dc ttl output current magnitude 10ma (per o/p, one at a time, 1sec. duration) symbol parameter min. typ. max. unit s notes v dd operating supply voltage 4.75 5.0 5.25 v i dd overall supply current 35 ma 1 v ih input voltage logic 1 2.4 v dd +0.5 v v il input voltage logic 0 -0.5 0.5 v v oh output voltage logic 1 v dd -0.5 v i=1ma v ol output voltage logic 0 0.5 v i=1ma i ilk input leakage current -1 m a v ih on input 1 m a v il on input c load digital input cap. load 10 pf
pre l imi n ar y 34 cd24011a.fm vision v v 6850 & 5850 sensors: product datasheet revision 1.0 ac operating conditions note 1. recommended clock rate for 0.1% settling of avo is 5.0mhz. note 2. serial interface clock must be generated by host processor. electrical characteristics video output characteristics symbol parameter min . typ. max. unit s note s pck pixel clock frequency 5 10 mhz 1 dck serial data clock 100 khz 2 symbol parameter min. typ. max. units notes vrtref internal reference for vrt 2.85 3.0 3.15 v unbuffered vbloomref internal reference for vbloom 1.90 2.0 2.10 v unbuffered vbltwref internal reference for vbltw 1.35 1.50 1.65 v unbuffered v bg internal bandgap reference 1.15 1.23 1.30 v decouple with 0.1f vcl1,2 video output clamp voltages 1.30 2.30 v an. inputs v dac 5-bit dac output 1.76 2.08 v for vcl1 or 2 r set resistor to set dac bias current -5% 12k +5% ohms i vrt load current on vrt 1.5 2.5 4.0 ma buffered from vrtref typical conditions, v dd = 5.0 v, t a = 25 o c symbol parameter min. typical max. units v black avo black level vcl1-30mv vcl1 vcl1+30mv v v white avo peak white - v black -1.0v - v pixel reset to pixel reset -0.125 0 0.125 v avoref pseudo-diff. avo reference vcl2-30mv vcl2 vcl2+30mv v i avo avo output current -2ma 4ma ma f avo avo bandwidth 33mhz c avo avo, avoref capacitive loading 30 pf r avo avo, avoref resistive loading 20k ohms
pre l imi n ar y 16/06/97 35 package details package details pinout 0.51 typ 1.0 typ 2.16 pin 1 1.016 pitch typ 23.37 0.55 0.51 0.42 glass lid sensor the optical array is centred within the package to a tolerance of +/- 0.2 mm, and rotated no more than +/- 0.5 o tolerances on package dimensions +/-0.2 all dimensions in millimetres viewed from below optical centre pin 11 standard 84 pin lcc 0.864 min. top 123456 79 80 81 82 83 84 32 31 30 29 28 27 26 25 24 23 22 21 47 46 45 44 43 42 53 52 51 50 49 48 54 55 56 57 58 59 60 61 62 63 64 65 avdd2 vdactop vdacbot avdd1 avoref avss1 avo vdac vbltwref vdac 3/4 vcl2 vcl1 dvdd4 agnd1 avcc1 dvss4 samref dout ls ec colsam clamp selref pck rstb din dlat dck viewed from top of package 35 34 33 41 40 39 38 37 36 agnd2 avcc2 dvdd3 dvss3 66 67 68 69 70 71 72 73 74 hclrb even fr fi vsetb vclrb pxrd lck cdsr 18 17 16 15 14 13 12 20 19 avcc3 vblwt agnd3 vbg rset vnb vbloom vrtref vblmref 75 76 77 78 dvss1 dvdd1 vrt1 78910 vrt2 dvss2 11 dvdd2 index top
pre l imi n ar y 36 cd24011a.fm vision v v 6850 & 5850 sensors: product datasheet revision 1.0 pin list pin name type function/comment power supplies 51, 35, 18 avcc1-3 pwr 5v supply for the column source followers. 50,36, 14 agnd1-3 gnd ground for the substrate and the column source followers. 28, 32 avdd1,2 pwr 5v supply for the output stage. 30 avss1 gnd ground supply for the output stage. 75, 11 dvdd1,2 pwr 5v supply for vertical shift registers 76, 10 dvss1,2 gnd ground for vertical shift registers 33 dvdd3 pwr 5v supply for output muxing. 34 dvss3 gnd ground for output muxing. 53 dvdd4 pwr 5v supply for horizontal shift register. 52 dvss4 gnd ground for horizontal shift register. power-on-reset 65 rstb od output of internal power-on-reset cell. should be applied to hclrb and vclrb at power up. analogue voltage references 77, 9 vrt1,2 ia pixel reset voltage and power supply. 12 vbloom ia anti-blooming pixel reset voltage. 13 vbltw ia defines white level for the bitline test. 19 vrtref oa unbuffered internally generated reference for vrt 20 vblmref oa unbuffered internally generated reference for vbloom 21 vbltwref oa unbuffered internally generated reference for vbltw. 15 vbg oa internal bandgap voltage reference (1.22 v); decouple with 10nf 17 vnb ia decoupling (10nf) for internally generated bias current 16 rset ia sets internal master bias current; connect to agnd via 12k res. 25 vcl1 ia ac clamp voltage for avo output. 26 vcl2 ia ac clamp voltage for avoref output. analogue output stage 31 avo oa buffered analogue video output; inverted - low = white 29 avoref oa buffered black level voltage reference. 55 selref id selref=0 - selects sensor output (video) at avo. selref=1 - selects line reference 54 samref id samples the line reference from vrt 56 clamp id controls ac clamping circuit in output stage.
pre l imi n ar y 16/06/97 37 package details key: reset and read vertical shift registers (vsr) 74 lck id line clock input for reset and read vertical shift registers 71 even id odd/even line clock. 72 pxrd id pixel read: control input to read a row of pixel voltages. 73 cdsr id correlated double sampling: control input to allow the row of pix- els currently being read to be reset without advancing the reset vsr. 67 vclrb id - clear reset and read vsrs. 68 vsetb id - preset the reset vsr to all ones. the read vsr is not preset. 69 fi id field integrate: resets vsr. high duration sets exposure time. 70 fr id field read: reads vsr. starts field read out. horizontal shift register (hsr) 60 pck id pixel clock 66 hclrb id - clear horizontal shift register 59 ls id line start: starts horizontal scan/pixel output. 58 ec id odd/ever column select. 57 colsam id sample the column source follower inputs (pixel row). serial data interface (sdi) 63 din id serial data input 64 dout od serial data output 62 dlat id latch serial data into control register 61 dck id serial data clock must be generated by host. 5-bit resistive ladder dac 22 vdactop ia voltage reference for the top of the resistive ladder 23 vdac3/4 oa three-quarter-point of the resistive ladder (unbuffered) 27 vdacbot ia voltage reference for the bottom of the resistive ladder 26 vdac oa dac output voltage (unbuffered) oa analogue output pad id digital input ia analogue input pad id - digital input with internal pull-up od digital output pad od digital output with internal pull-down pin name type function/comment
pre l imi n ar y 38 cd24011a.fm vision v v 6850 & 5850 sensors: product datasheet revision 1.0 adc interface circuit avo avoref sensor pipelined adc 2k black white black white reftf refbf line reference pixel array + columns vcl2 vcl1 clamp 5-bit resistor ladder dac vdactop vdacbot vdac vdac3/4 25k 25k 2p 1k 1k 33 10p a_in 10 bit / 20 msps cr[15..11]
pre l imi n ar y 16/06/97 39 analogue reference buffering analogue reference buffering vv6850 vrt vbloom vbltw vbg ic1-ic3 = low noise fet i/p opamps rset 12k vrtref vblmref vbltwref 1k 3k9 10 2n2 01 022 01 1k 3k9 10 2n2 01 022 1k 3k9 10 2n2 01 022 ic1 ic3 ic2
pre l imi n ar y 40 cd24011a.fm vision v v 6850 & 5850 sensors: product datasheet revision 1.0 appendix a - fpn cancellation schemes there are many possible ways achieve fpn cancellation in order to produce the highest quality stills images from the vv6850 sensor. the exact method chosen will depend on the intended use of the imager system, and the ancillary devices available in the system, such as the frame buffer and mechanical shutter typical of a digital stills camera. a number of schemes are discussed. multiple dark current periods the basic fpn cancellation scheme outlined in o perating m odes - s till i mage c apture can be modified in many ways to suit a particular application. one such variation might be to extend the post image exposure dark image capture period to some integral multiple of the image exposure period, in order to obtain a more accurate assessment of the dark current fpn: 1. with the shutter closed, release the sensor from reset and immediately read a frame into buffer a memory; this captures the array threshold fpn and reset noise (v reset ) 2. open the shutter and expose the sensor to the required scene 3. close the shutter and immediately read the array; as each pixel is read, subtract the value for that position stored in the frame buffer to obtain the image plus dark current fpn (v im +v dark1 ) value; store this value in second frame buffer, b 4. after a further (say) four frame periods, read the array again; as each pixel is read, subtract the reset value for that position as stored in the a frame buffer, and overwrite the position, leaving the v im + v dark1 + v dark2 value in the buffer 5. for each pixel, subtract the value in b from that in a to give v dark2 dark current value, which is equivalent to four times the v dark1 value 6. divide the v dark2 values in a by 4, then subtract them from the (v im + v dark1 ) values in b and store the result, which is the v im image data the frame buffer now contains the corrected image values, which can be transferred to image storage memory. this scheme is illustrated below: reset[n] read[n] v pix vrt v black v white read 1 v reset read 2 read 3 v dark1 v im v dark2 shutter exposure not to scale
pre l imi n ar y 16/06/97 41 appendix a - fpn cancellation schemes 16/06/97 uk headquarters aviation house, 31 pinkhill, edinburgh, uk eh12 7bf tel:+44 (0)131 539 7111 fax:+44 (0)131 539 7140 email: info@vvl.co.uk usa western office 18805 cox avenue, suite 260, saratoga, california 95070, usa tel:+1 408 374 5323 fax:+1 408 374 4722 email: info@vvl.co.uk vlsi vision limited vlsi vision ltd. reserves the right to make changes to its products and spec- ifications at any time. information furnished by vision is believed to be accurate, but no responsibility is assumed by vision for the use of said information, nor any infringements of patents or of any other third party rights which may result from said use. no license is granted by implication or other- wise under any patent or patent rights of any vision group company. ? copyright 1997, vlsi vision distributor/agent: usa eastern office 2517 highway 35, bldg. f, suite 202, manasquan, new jersey 08736, usa tel: + 1 908 528 2222 fax:+ 1 908 528 9305 email: info@vvl.co.uk

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