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752b?280 8b3=!13b 8b3=73;2585>r^]ca^[[ta fxcw bcp]s?28x]ctauprt p]s drwx_bd__^ac 9p]dpah! copyright 1994-2001 cologne chip ag all rights reserved the information presented can not be considered as assured characteristics. data can change without notice. parts of the information presented may be protected by patent or other rights. cologne chip products are not designed, intended, or authorized for use in any application intended to support or sustain life, or for any other application in which the failure of the cologne chip product could create a situation where personal injury or death may occur. 4qdqcxuud cologne chip
863c @39 1 "_v(# :q^eqbi " ! cologne chip revision history date remarks jan. 2001 information added to section: trm register bit description, gci/iom2 timing. changes made on: isdn pci card for 3.3v power supply (no d3 cold support) part list and isdn pci card for 3.3v power supply with d3 cold support part list: rg3, rg4 renamed to rg1, rg2 to match with the schematics. oct. 2000 changes made in section: sample circuitries: isdn pci card for 3.3 and 5v power supply (auto detect) with d3 cold support: connectors for alternative footprint removed. may 2000 information added to section: s/t module part numbers, sample circuitries. jan. 2000 section added: register list. information added to section: gci frame structure, sample circuitries. errors corrected in section: configuring test loops (register addresses corrected), register bit description (states register address corrected), auxiliary port write access (data out is valid until the next write access is initiated). aug. 1999 sections added: power management support of hfc-s pci a, configuring test loops. information added in section: states register bit description, s/t interface activation / deactivation layer 1 for finite state matrix for nt. apr. 1999 auxiliary port access timing diagrams added. mar. 1999 changes made on: s/t module part numbers and manufacturers. cologne chip cologne chip ag eintrachtstrasse 113 d-50668 k?ln germany tel.: +49 (0) 221 / 91 24-0 fax: +49 (0) 221 / 91 24-100 http://www.colognechip.com http://www.colognechip.de info@colognechip.com
863c @39 1 :q^eqbi " ! #_v(# cologne chip contents features....................................................................................................................... ................................. 6 1 general description........................................................................................................... ................. 6 1.1 applications ................................................................................................................ ..................... 7 2 pin description............................................................................................................... ..................... 8 2.1 pci bus interface........................................................................................................... ................... 8 2.2 auxiliary port.............................................................................................................. ................... 10 2.3 s/t interface transmit signals .............................................................................................. .......... 10 2.4 s/t interface receive signals............................................................................................... ........... 10 2.5 oscillator.................................................................................................................. ...................... 11 2.6 gci/iom2 bus interface ...................................................................................................... .......... 11 2.7 gci/iom2 timeslot enable signals ............................................................................................ ... 11 2.8 eeprom interface ............................................................................................................ ............ 11 2.9 power supply................................................................................................................ .................. 12 2.10 reset characteristics...................................................................................................... ......... 12 3 functional description ........................................................................................................ ............. 13 3.1 pci-interface ............................................................................................................... ................... 13 3.1.1 pci access types used by hfc-s pci a ............................................................................... 13 3.1.2 pci modes supported ....................................................................................................... ..... 13 3.1.3 pci buffer signaling and power supply environment............................................................ 13 3.1.4 pci configuration registers ............................................................................................... .... 14 3.2 internal hfc-s pci a register description................................................................................... .17 3.2.1 registers of the s/t section .............................................................................................. .... 18 3.2.2 registers of the gci/iom2 bus section ................................................................................ 19 3.2.3 interrupt and status registers ............................................................................................ ..... 20 3.2.4 register list ............................................................................................................. .............. 21 3.3 power management support of hfc-s pci a .............................................................................. 22 3.3.1 pme events ................................................................................................................ ........... 22 3.3.2 special considerations for support of d3 cold ......................................................................... 22 3.4 timer....................................................................................................................... ....................... 24 3.5 fifos ....................................................................................................................... ...................... 25 3.5.1 fifo counters location in memory window ........................................................................ 26 3.5.2 fifo data location in memory window ............................................................................... 27 3.5.3 fifo channel operation.................................................................................................... ..... 28 3.5.3.1 send channels (b1, b2 and d transmit)............................................................................ 28 3.5.3.2 automatically d-channel frame repetition ....................................................................... 29 3.5.3.3 fifo full condition in send channels................................................................................ 29 3.5.3.4 receive channels (b1, b2 and d receive) ....................................................................... 29 3.5.3.5 fifo full condition in receive channels ........................................................................... 31 3.5.3.6 fifo initialisation..................................................................................................... ........ 31 3.5.4 transparent mode of hfc-s pci a ...................................................................................... 32 3.6 configuring test loops...................................................................................................... .............. 33 4 register bit description...................................................................................................... .............. 34 4.1 register bit description of s/t section ..................................................................................... ..... 34 4.2 register bit description of gci/iom2 bus section ........................................................................ 37 4.3 register bit description of connect register............................................................................. 40
863c @39 1 $_v(# :q^eqbi " ! cologne chip 4.4 register bit description of auxiliary and cross data registers ........................................................ 41 5 electrical characteristics .................................................................................................... ............. 46 6 timing characteristics ........................................................................................................ ............. 50 6.1 pci bus timing .............................................................................................................. ................. 50 6.2 gci/iom2 bus clock and data alignment for mitel st tm bus....................................................... 50 6.3 gci/iom2 timing ............................................................................................................. ............. 51 6.3.1 master mode............................................................................................................... ........... 51 6.3.2 slave mode ................................................................................................................ ............ 52 6.4 eeprom access ............................................................................................................... ............. 53 6.5 auxiliary port access ....................................................................................................... .............. 54 6.5.1 write access .............................................................................................................. ............ 54 6.5.2 read access ............................................................................................................... ............ 55 7 s/t interface circuitry....................................................................................................... ............... 56 7.1 external receiver circuitry ................................................................................................. ............ 56 7.2 external transmitter circuitry.............................................................................................. ........... 57 7.3 oscillator circuitry ........................................................................................................ ................. 60 7.4 eeprom circuitry............................................................................................................ ............. 60 7.5 pme pin circuitry........................................................................................................... ................ 61 8 state matrices for nt and te .................................................................................................. ....... 62 8.1 s/t interface activation/deactivation layer 1 for finite state matrix for nt .................................. 62 8.2 activation/deactivation layer 1 for finite state matrix for te ....................................................... 63 9 binary organisation of the frames ............................................................................................. ..... 64 9.1 s/t frame structure ......................................................................................................... ............... 64 9.2 gci frame structure ......................................................................................................... .............. 65 10 clock synchronisation........................................................................................................ .............. 66 10.1 clock synchronisation in nt-mode........................................................................................... 66 10.2 clock synchronisation in te-mode ........................................................................................... 67 11 hfc-s pci a package dimensions............................................................................................... .. 68 12 isdn pci card sample circuitries with hfc-s pci a................................................................. 69 12.1 isdn pci card for 5v power supply (no d3 cold support).......................................................... 69 12.2 isdn pci card for 5v power supply with d3 cold support ......................................................... 72 12.3 isdn pci card for 3.3v power supply (no d3 cold support)....................................................... 75 12.4 isdn pci card for 3.3v power supply with d3 cold support ...................................................... 78 12.5 isdn pci card for 3.3 and 5v power supply (auto detect) with d3 cold support ....................... 81
863c @39 1 :q^eqbi " ! %_v(# cologne chip figures figure 1: hfc-s pci a block diagram............................................................................................ ............. 7 figure 2: pin connection ....................................................................................................... ....................... 8 figure 3: hfc-s pci a in i/o address mapped mode............................................................................... .17 figure 4: hfc-s pci a in memory address mapped mode ........................................................................ 17 figure 5: masking rst# for d3 cold support ............................................................................................... 23 figure 6: fifo organisation (shown for b-channel, similar for d-channel) ............................................. 28 figure 7: fifo data organisation ............................................................................................... ............... 30 figure 8: function of the connect register bits................................................................................ ..... 40 figure 9: gci/iom2 bus clock and data alignment................................................................................ .... 50 figure 10: external receiver circuitry......................................................................................... ................ 56 figure 11: external transmitter circuitry ...................................................................................... .............. 57 figure 12: oscillator circuitry................................................................................................ .................... 60 figure 13: eeprom circuitry .................................................................................................... ................ 60 figure 14: pme pin circuitry ................................................................................................... ................... 61 figure 15: frame structure at reference point s and t .......................................................................... ..... 64 figure 16: single channel gci format........................................................................................... ............. 65 figure 17: clock synchronisation in nt-mode .................................................................................... ...... 66 figure 18: clock synchronisation in te-mode .................................................................................... ....... 67 figure 19: hfc-s pci a package dimensions ...................................................................................... ..... 68 tables table 1: pci command types ..................................................................................................... ................. 13 table 2: pci configuration registers' initial values........................................................................... .......... 17 table 3: register list by address .............................................................................................. ................... 21 table 4: register list by name ................................................................................................. ................... 21 table 5: s/t module part numbers and manufacturer .............................................................................. .. 59 table 6: activation/deactivation layer 1 for finite state matrix for nt ..................................................... 62 table 7: activation/deactivation layer 1 for finite state matrix for te...................................................... 63 timing diagrams timing diagram 1: gci/iom2 timing.............................................................................................. ........... 51 timing diagram 2: eeprom access ................................................................................................ .......... 53 timing diagram 3: auxiliary port write access .................................................................................. ........ 54 timing diagram 4: auxiliary port read access................................................................................... ......... 55
863c @39 1 &_v(# :q^eqbi " ! cologne chip features ? single chip isdn-s-controller with b- and d-channel hdlc support ? independent read and write hdlc-channels for 2 isdn b-channels and one isdn d-channel ? b1- and b2-channel transparent mode independently selectable ? fifo-memory-window: 4x 7.5 kbyte (b-channel) and 2x 512 byte (d-channel) ? max. 31 hdlc frames (b-channel) and 15 hdlc frames (d-channel) per channel and direction in fifo ? 56 kbit/s restricted mode for u.s. isdn lines selectable ? full i.430 itu s/t isdn support in te and nt mode ? b1+b2 hdlc mode ? pcm30 interface configurable to interface mitel st tm bus (mvip tm ), siemens iom2 tm or gci tm for interface to u-chip or external codecs ? integrated pci spec. 2.2 bus interface (power management included, acpi ready) for 3.3v and 5v bus signal environment ? direct access to pcm30 interface for tone synthetisation ? 3.3v and 5v supply voltage ? rectangular qfp 100 case 1 general description the hfc-s pci a is an isdn s/t hdlc basic rate controller for so called ?passive isdn pc cards with integrated s/t interface and pcm30 highway interface. it is the first all in one solution for a pci isdn pc-card world wide with power management and windows 98 support. a 32kbyte memory window of the pc is used for the deep fifos. also an industrial standard serial interface for telecom peripheral ics is implemented. codecs are normally connected to this interface.
863c @39 1 :q^eqbi " ! '_v(# cologne chip 1.1 applications ? isdn pci pc card figure 1: hfc-s pci a block diagram
863c @39 1 (_v(# :q^eqbi " ! cologne chip 2 pin description 2.1 pci bus interface for further information please refer to the pci local bus specification. pin no. pin name input output function 47 ad0 i/o pci address bus address bit 0 46 ad1 i/o address bit 1 45 ad2 i/o address bit 2 44 ad3 i/o address bit 3 43 ad4 i/o address bit 4 42 ad5 i/o address bit 5 41 ad6 i/o address bit 6 40 ad7 i/o address bit 7 37 ad8 i/o address bit 8 36 ad9 i/o address bit 9 35 ad10 i/o address bit 10 34 ad11 i/o address bit 11 33 ad12 i/o address bit 12 32 ad13 i/o address bit 13 31 ad14 i/o address bit 14 30 ad15 i/o address bit 15 figure 2: pin connection
863c @39 1 :q^eqbi " ! )_v(# cologne chip pin no. pin name input output function 16 ad16 i/o address bit 16 15 ad17 i/o address bit 17 14 ad18 i/o address bit 18 13 ad19 i/o address bit 19 12 ad20 i/o address bit 20 11 ad21 i/o address bit 21 10 ad22 i/o address bit 22 9 ad23 i/o address bit 23 4 ad24 i/o address bit 24 3 ad25 i/o address bit 25 2 ad26 i/o address bit 26 1 ad27 i/o address bit 27 100 ad28 i/o address bit 28 99 ad29 i/o address bit 29 98 ad30 i/o address bit 30 97 ad31 i/o address bit 31 26 par i/o parity bit 38 c/be0# i/o bus command and byte enable 0 27 c/be1# i/o bus command and byte enable 1 18 c/be2# i/o bus command and byte enable 2 5 c/be3# i/o bus command and byte enable 3 93 clk i pci clock 92 rst# i reset 19 frame# i/o cycle frame 20 irdy# i/o initiator ready 21 trdy# i/o target ready 23 stop# i/o stop 6 idsel i initialisation device select 22 devsel# i/o device select 95 req# o request 94 gnt# i grant 24 perr# i/o parity error 25 serr# o system error 53 pme o power management event (high active) see also: figure 14 on page 61 91 inta# o interrupt a
863c @39 1 ! _v (# :q^eqbi " ! cologne chip 2.2 auxiliary port pin no. pin name input output function 75 daux0 i/o aux data bit 0 74 daux1 i/o aux data bit 1 73 daux2 i/o aux data bit 2 72 daux3 i/o aux data bit 3 71 daux4 i/o aux data bit 4 70 daux5 i/o aux data bit 5 69 daux6 i/o aux data bit 6 68 daux7 i/o aux data bit 7 67 /aux_wr o aux write 66 /aux_rd o aux read 65 /adr_wr i/o d) aux address write d) internal pull down 2.3 s/t interface transmit signals 88 tx2_hi o transmit output 2 87 /tx1_lo o gnd driver for transmitter 1 86 /tx_en o transmit enable 85 /tx2_lo o gnd driver for transmitter 2 84 tx1_hi o transmit output 1 see also: 7.2 external transmitter circuitry. 2.4 s/t interface receive signals 82 r2 i receive data 2 81 lev_r2 i level detect for r2 80 lev_r1 i level detect for r1 79 r1 i receive data 1 78 adj_lev o levelgenerator see also: 7.1 external receiver circuitry.
863c @39 1 :q^eqbi " ! !! _v (# cologne chip 2.5 oscillator pin no. pin name input output function 51 osc_in i oscillator input or quarz connection 12.288 mhz 50 osc_out o oscillator output or quarz connection 2.6 gci/iom2 bus interface 54 c4io i/o u) 4.096 mhz clock gci/iom2 bus clock master: output gci/iom2 bus clock slave: input (reset default) 55 f0io i/o u) frame synchronisation, 8khz pulse for gci/iom2 bus frame synchronisation gci/iom2 bus master: output gci/iom2 bus slave: input (reset default) 56 stio1 i/o u) gci/iom2 bus databus i slotwise programmable as input or output 57 stio2 i/o u) gci/iom2 bus databus ii slotwise programmable as input or output u) internal pull up 2.7 gci/iom2 timeslot enable signals (e. g. for pcm codecs) 58 f1_a o enable signal for external codec a programmable as positive (reset default) or negative pulse. 59 f1_b o enable signal for external codec b programmable as positive (reset default) or negative pulse. 2.8 eeprom interface the external eeprom is optional. ee_scl/en must be connected to gnd if no external eeprom is available. 63 ee_sda i/o u) serial data of external eeprom 62 ee_scl/en i/o u) clock of external eeprom / eeprom enable u) internal pull up
863c @39 1 !" _v (# :q^eqbi " ! cologne chip 2.9 power supply pin no. pin name function 7, 28, 48, 60, 76, 89 vdd vdd (+3.3v or +5v) 8, 17, 29, 39, 49, 52, 61, 64, 77, 83, 90, 96 gnd gnd * important! all power supply pins vdd must be directly connected to each other. also all pins gnd must be directly connected to each other. to keep vdd and gnd bounce to a minimum a bypass capacitor (10 nf to 100 nf) should be placed between each pair of vdd/gnd pins. 2.10 reset characteristics the reset signal (hardware reset or software reset) must be active for at least 4 clock cycles. the gci/iom2 bus lines stio1, stio2 and the interrupt lines are in tristate mode after a reset. the hfc-s pci a is in slave mode after reset. c4io and f0io are inputs. the s/t state machine is stuck to '0' after reset. this means the hfc-s pci a does not react to any signal on the s/t interface before the s/t state machine is initialised. the registers' initial values are described in the register bit description (section 4 of this data sheet). during initialisation phase the hfc-s pci a must not be accessed. bit 1 of the status register is cleared to '0' to indicate that the initialisation phase has been finished.
863c @39 1 :q^eqbi " ! !# _v (# cologne chip 3 functional description 3.1 pci-interface 3.1.1 pci access types used by hfc-s pci a c/be3# c/be2# c/be1# c/be0# command type hfc-s pci a mode 0 0 1 0 i/o read target mode 0 0 1 1 i/o write target mode 0 1 1 0 memory read target mode and master mode 1 1 0 0 memory read multiple target mode 1 1 1 0 memory read line target mode 0 1 1 1 memory write target mode and master mode 1 1 1 1 memory write and invalidate target mode 1 0 1 0 configuration read target mode 1 0 1 1 configuration write target mode table 1: pci command types memory read line and memory read multiple commands are aliased to memory read. memory write and invalidate is aliased to memory write. 3.1.2 pci modes supported the hfc-s pci a supports both target mode and master mode. before the hfc-s pci a can operate in master mode the 32k memory window base address register (mwba) must be configured. afterwards all fifo data accesses are done by the hfc-s pci a automatically by pci master accesses. only control and configuration register accesses must be done by pci target accesses by the host cpu. 3.1.3 pci buffer signaling and power supply environment the hfc-s pci a supports 5v and 3.3v pci bus environments. the environment mode is set during reset (rst# low) by the input value of /adr_wr. pci bus power and signaling environment /adr_wr during rst# low 3.3v high *) 5v low *) external pull-up resistor required (10k) warning! / adr_wr is an output after reset. so do not connect it directly to gnd or vdd.
863c @39 1 !$ _v (# :q^eqbi " ! cologne chip 3.1.4 pci configuration registers
863c @39 1 :q^eqbi " ! !% _v (# cologne chip the external eeprom is optional. if no eeprom is available, ee_scl/en must be connected to gnd. without eeprom the pci configuration registers will be loaded with the default values shown in table 2. all registers which can be read from eeprom can also be written by configuration write accesses. the addresses for configuration write are shown in the table below. register name default value remarks vendor id 1397h value can be read from eeprom. base address for configuration write is c0h. device id 2bd0h value can be read from eeprom. base address for configuration write is c0h. command register bits function 0 enables/disables i/o space accesses. 1 enables/disables memory space accesses. 2 enables/disables master accesses. 5..3 fixed to '0' 6 perr# enable/disable 7 fixed to '0' 8 serr# enable/disable 15..9 fixed to '0' status register 0210h bits[7:0] can be read from eeprom. base address for configuration write is c4h. bits function 3..0 reserved 4 fixed to '1' 5 66mhz capable 6 user definable features supported 7 fast back-to-back capable 8 data parity error detected 10..9 fixed to '01': timing of devsel# is medium 11 signaled target abort (fixed to '0') 12 received target abort 13 received master abort 14 signaled system error (addr. parity error) 15 detected partity error revision id 02h hfc-s pci a class code 02 80 00h value can be read from eeprom. base address for configuration write is c8h. latency timer 10h set to 16 clocks, value is fixed. header type 00h header type 0 bist 00h no build in self test supported. i/o base address bits[31:3] are r/w by configuration accesses memory base address bits[31:8] are r/w by configuration accesses subsystem vendor id 1397h value can be read from eeprom. base address for configuration write is ech. subsystem id 2bd0h value can be read from eeprom. base address for configuration write is ech. cap_ptr 40h offset to power management register block.
863c @39 1 !& _v (# :q^eqbi " ! cologne chip register name default value remarks interrupt line ffh this register must be configured by configuration write. interrupt pin 01h inta supported min_gnt 00h value can be read from eeprom. base address for configuration write is fch. max_lat 10h value can be read from eeprom. base address for configuration write is fch. cap_id 01h capability id. 01h identifies the linked list item as pci power management registers. next ptr 00h there are no next items in the linked list. pmc 7e21h power management capabilities. see also pci bus power management interface specification. this register's value can be read from eeprom. base address for configuration write is e0h. pme# can be asserted from d0, d1, d2 and d3 hot . device specific initialisation is required. the hfc-s pci a does not require pci-clock to generate pme# (if s/t change state is selected). this function complies with the pci power management spec. version 1.0. pmcsr 0000h power management control/status bits function 15 pme_status - this bit is set when the function would normally assert the pme # signal independent of the state of the pme_en bit. writing a '1' to this bit will clear it and cause the function to stop asserting a pme # (if enabled). writing a '0' has no effect. 14..9 fixed to '0' 8 pme_en - a '1' enables the function to assert pme#. when '0', pme # assertion is disabled. 7..2 fixed to '0' 1..0 powerstate - this 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. 00b - d0 01b - d1 10b - d2 11b - d3 hot all states except d0 disable hfc-s pci a master accesses.
863c @39 1 :q^eqbi " ! !' _v (# cologne chip register name default value remarks 32k memory window base address (mwba) 0000h bits[31:15] are r/w by configuration accesses. the 32k memory window is for hfc-s pci a internal use and for the b- and d-channel fifos. this register must be written by a "dword config write" to enable the hfc-s pci a to operate in master mode. table 2: pci configuration registers' initial values unimplemented registers return all 0's when read. 3.2 internal hfc-s pci a register description if the hfc-s pci a is used in memory mapped mode all register can directly be accessed by adding their cip address to the configured memory base address. in i/o address mapped mode the hfc-s pci a occupies 8 bytes in the i/o address space. byte 0 is for data read/write, byte 4 for register selection. the aux-port address is selected by byte 3, aux-port data is read/written by byte 1. figure 3: hfc-s pci a in i/o address mapped mode figure 4: hfc-s pci a in memory address mapped mode
863c @39 1 !( _v (# :q^eqbi " ! cologne chip 3.2.1 registers of the s/t section cip / i/o-address name r/w function 1100 0000 c0h states r/w state of the te/nt state machine 1100 0100 c4h sctrl w s/t control register 1100 1000 c8h sctrl_e w s/t control register (extended) 1100 1100 cch sctrl_r w receive enable for b-channels 1101 0000 d0h sq_rec r receive register for s/q bits sq_send w send register for s/q bits 1101 1100 dch clkdel w setup of the delay time between receive and send direction (te) receive data sample time (nt) 1111 0000 f0h b1_rec *) r b1-channel receive register b1_send *) w b1-channel transmit register 1111 0100 f4h b2_rec *) r b2-channel receive register b2_send *) w b2-channel transmit register 1111 1000 f8h d_rec *) r d-channel receive register d_send *) w d-channel transmit register 1111 1100 fch e_rec *) r e-channel receive register *) these registers are read/written automatically by the hdlc fifo controller (hfc) or gci/iom2 bus controller and need not be accessed by the user. to read/write data the fifos in the memory window should be used.
863c @39 1 :q^eqbi " ! !) _v (# cologne chip 3.2.2 registers of the gci/iom2 bus section gci/iom2 bus timeslot selection registers cip / i/o-address name r/w function 0000 1000 08h c/i r/w c/i command/indication register 0000 1100 0ch trxr r monitor tx ready handshake 0010 1000 28h mon1_d r/w first monitor byte 0010 1100 2ch mon2_d r/w second monitor byte gci/iom2 bus timeslot selection registers cip / i/o-address name r/w function 1000 0000 80h b1_ssl w b1-channel transmit slot (0..31) 1000 0100 84h b2_ssl w b2-channel transmit slot (0..31) 1000 1000 88h aux1_ssl w aux1-channel transmit slot (0..31) 1000 1100 8ch aux2_ssl w aux2-channel transmit slot (0..31) 1001 0000 90h b1_rsl w b1-channel receive slot (0..31) 1001 0100 94h b2_rsl w b2-channel receive slot (0..31) 1001 1000 98h aux1_rsl w aux1-channel receive slot (0..31) 1001 1100 9ch aux2_rsl w aux2-channel receive slot (0..31) gci/iom2 bus data registers cip / i/o-address name r/w function 1010 0000 a0h b1_d *) r/w gci/iom2 bus b1-channel data register 1010 0100 a4h b2_d *) r/w gci/iom2 bus b2-channel data register 1010 1000 a8h aux1_d r/w aux1-channel data register 1010 1100 ach aux2_d r/w aux2-channel data register *) these registers are read/written automatically by the hdlc fifo controller (hfc) or by the s/t controller and need not be accessed by the user.
863c @39 1 " _v (# :q^eqbi " ! cologne chip gci/iom2 bus configuration registers cip / i/o-address name r/w function 1011 0100 b4h mst_emod w extended mode register for gci/iom2 bus 1011 1000 b8h mst_mode w mode register for gci/iom2 bus 1011 1100 bch connect w connect functions for s/t, hfc, gci/iom2 3.2.3 interrupt and status registers cip / i/o address name r/w function 0100 0100 44h fifo_en w fifo enable/disable 0100 1000 48h trm w transparent mode interrupt mode register 0100 1100 4ch b_mode w mode of b-channels 0101 1000 58h chip_id r register for chip identification 0110 0000 60h cirm w interrupt selection and softreset register 0110 0100 64h ctmt w transparent mode and timer control register 0110 1000 68h int_m1 w interrupt mask register 1 0110 1100 6ch int_m2 w interrupt mask register 2 0111 1000 78h int_s1 r interrupt status register 1 0111 1100 7ch int_s2 r interrupt status register 2 0111 0000 70h status r common status register
863c @39 1 :q^eqbi " ! "! _v (# cologne chip 3.2.4 register list registers by address address name page 08h c/i 39 0ch trxr 39 28h mon1_d 19 2ch mon2_d 19 44h fifo_en 41 48h trm 43 4ch b_mode 42 58h chip_id 42 60h cirm 41 64h ctmt 42 68h int_m1 43 6ch int_m2 43 70h status 45 78h int_s1 44 7ch int_s2 44 80h b1_ssl 37 80h b2_ssl 37 88h aux1_ssl 37 8ch aux2_ssl 37 90h b1_rsl 37 94h b2_rsl 37 98h aux1_rsl 37 9ch aux2_rsl 37 a0h b1_d 37 a4h b2_d 37 a8h aux1_d 37 ach aux2_d 37 b4h mst_emod 39 b8h mst_mode 38 bch connect 40 c0h states 34 c4h sctrl 35 c8h sctrl_e 35 cch sctrl_r 36 d0h sq_rec 36 d0h sq_send 36 dch clkdel 36 f0h b1_rec 18 f0h b1_send 18 f4h b2_rec 18 f4h b2_send 18 f8h d_rec 18 f8h d_send 18 fch e_rec 18 table 3: register list by address registers by name address name page a8h aux1_d 37 98h aux1_rsl 37 88h aux1_ssl 37 ach aux2_d 37 9ch aux2_rsl 37 8ch aux2_ssl 37 4ch b_mode 42 a0h b1_d 37 f0h b1_rec 18 90h b1_rsl 37 f0h b1_send 18 80h b1_ssl 37 a4h b2_d 37 f4h b2_rec 18 94h b2_rsl 37 f4h b2_send 18 80h b2_ssl 37 08h c/i 39 58h chip_id 42 60h cirm 41 dch clkdel 36 bch connect 40 64h ctmt 42 f8h d_rec 18 f8h d_send 18 fch e_rec 18 44h fifo_en 41 68h int_m1 43 6ch int_m2 43 78h int_s1 44 7ch int_s2 44 28h mon1_d 19 2ch mon2_d 19 b4h mst_emod 39 b8h mst_mode 38 c4h sctrl 35 c8h sctrl_e 35 cch sctrl_r 36 d0h sq_rec 36 d0h sq_send 36 c0h states 34 70h status 45 48h trm 43 0ch trxr 39 table 4: register list by name
863c @39 1 :q^eqbi " ! "" _v (# cologne chip 3.3 power management support of hfc-s pci a because of the very low power dissipitation of hfc-s pci a device there is no need of reducing power in standby mode. furthermore the main source of power dissipation is the 33mhz pci clock. so the biggest reduction in power dissipation of the device can be achieved by stopping the pci clock which can only be done by the pci bridge generating the pci clock for the pci slot concerned. so the lowest power is needed in bus states b2 and b3. another minor reduction of power dissipation can be achieved by stopping the 12.288 mhz clock for the isdn part of the hfc-s pci a. if no awake (restart of oscillation) from s/t bus activity is selected the power dissipation can be reduced to less then 3mw if pci clock is also stopped. none of the settings above are accomplished by changing the power states from d0 to d1, d2 or d3 hot . the register settings are only implemented to be compatible to pci power management specification. so no reduction of power is achieved by purely changing the power states. in the following paragraph the awake scenarios for asserting pme# from different power states are described. 3.3.1 pme events generally the source for pme# generation can be selected from: 1. d-channel receive frame interrupt this is only possible in power state d0 and bus state b0 because d-channel data is put into the memory window (mw) of the hfc-s pci a which is located in the memory space of the host pc. 2. s/t state change normally generated due to s/t interface activation from outside this is the normal source of the pme# event. in this case the pme# pin can be asserted in any power state (d0 C d3 hot ). 3.3.2 special considerations for support of d3 cold the hfc-s pci a was not specially designed to support d3 cold . however it is possible to use the device even in d3 cold applications if an external power supply or the vaux3.3 is available. the device should be powered in a way that if the main supply is switched off the device is automatically feed by the auxiliary power supply. because pme context (pme_status and pme_en) bits in pcmcsr register is not maintained when the device is reset (rst# asserted) the device must be prevented from being reset if main power is off. this unwanted reset is normally done due to dropping of all pci input signals to gnd when power is switched off.
863c @39 1 :q^eqbi " ! "# _v (# cologne chip with the additional device in figure 5 the ability to react on rst# asserted can be switched off and on by masking the rst# pin. because of a power on reset circuitry connected to the auxiliary power source the rst# masking is switched off when power is first time switched on. in the preparation process for d3 cold e.g. when the context of the chip must be saved before power is switched off the device driver must set the res# mask bit to prevent an unwanted reset when the pc is switched off. after getting power again and the reinitialisation of the chip is initiated the rst# mask bit is reset again by the device driver. hfc-s pci a rst# all vc c pins /aux_w r daux0 gnd r1 10k r2 10k u3 74h c 74/lc c 14 20 8 13 9 12 6 18 3 16 4 19 2 2pr e vcc 1q 2q 1q 2q 1pr e 2d 1d 2c lk 1c lk 2c lr 1c lr r4 10k r3 1m c1 1u d2 1n 4148 d1 1n 4148 q1 bc 560c 1 2 3 q2 bc 560c 1 2 3 cb rst# (pci slot) v i/o pci 3.3v / 5v 3.3 vaux vdd hfc for universal pci board power supply can be 3.3v or 5v. for 3.3v pci board power supply must be 3.3v. for 5v pci board power supply must be 5v. the receiver and transmitter circuitry must be selected correspondingly. figure 5: masking rst# for d3 cold support
863c @39 1 "$ _v (# :q^eqbi " ! cologne chip for 3.3v pci boards vcc must be 3.3v and the 3.3v receiver/transmitter circuitry must be used which can be found in the hfc-s pci a datasheet. for 5v pci boards vcc must be 5v and the 5v receiver/transmitter circuitry must be used which can be found in the hfc-s pci a datasheet. for the universal pci board with auto power detection vcc can be either 3.3v or 5v and the receiver/transmitter circuitry for the universal pci board must be used which can be found in the universal pci board sample circuitry for 3.3v and 5v power supply (see 12.5). literature further information about pci power management can be found in the following specifications: - pci local bus specification, revision 2.2, december 18, 1998 - pci bus power management interface specification, revision 1.1, december 18, 1998 3.4 timer the hfc-s pci a includes a timer with interrupt capability. the timer counts f0io pulses. so the timer counter is incremented every 125s. it can be reset by bit 7 of of the ctmt register. furthermore the timer is reset at every hfc-s pci a access when bit 5 of the ctmt register is set. seven different timer values can be selected.
863c @39 1 :q^eqbi " ! "% _v (# cologne chip 3.5 fifos all fifos are located in the 32k memory window (mw) in host pc's memory. there are 6 fifos with 6 hdlc-controllers handled by the hfc-s pci a. the hdlc circuits are located on the s/t device side of the hfc-s pci a. so always plain data is stored in the fifo. zero insertion and deletion is done in hdlc mode: C if the data goes to the s/t or gci/iom device in send fifos and C when the hdlc data comes from the s/t device or gci/iom2 bus in receive operation. there are a send and a receive fifo for each of the two b-channels and for the d-channel. the fifos are realized as ring buffers in the 32k memory window in host pc's memory. to control them there are some counters. b-channel d-channel z1: fifo input counter 13 bit 9 bit z2: fifo output counter 13 bit 9 bit each counter points to a byte position in the memory window. this is an offset to the 32k memory window base address in the configuration space. on a fifo input operation z1 is incremented. on an output operation z2 is incremented. after every pulse on the f0io signal two hdlc-bytes are written into the s/t interface (fifos no. 0 and 2) and two hdlc-bytes are read from the s/t interface (fifos no. 1 and 3). d-channel data is handled in a similar way but only 2 bits are processed. * important! instead of the s/t interface also gci/iom2 bus is selectable for each b-channel (see connect register). if z1 = z2 the fifo is empty. additionally there are two counters f1 and f2 for every fifo channel (5bit for b-channel, 4bit for d- channel). they count the hdlc-frames in the fifos and form a ring buffer as z1 and z2 do, too. f1 is incremented when a complete frame has been received and stored in the fifo. f2 is incremented when a complete frame has been read from the fifo. if f1 = f2 there is no complete frame in the fifo. when the reset line is active or software reset is active z1, z2, f1 and f2 are all initialized to all 1s. all zx and fx counters are also stored in the memory window. so it is easy to read and write the counters by simple host memory accesses.
863c @39 1 "& _v (# :q^eqbi " ! cologne chip because the hfc-s pci a is limited to the 32k memory window data in different regions of the host pc can not be overwritten even if counter and pointer values are handled in a wrong way. * important! the counter state 0200h of the z-counters follows counter state 1fffh in the b-channel fifos. the counter state 000h of the z-counters follows counter state 1ffh in the d-channel fifos. the counter state 00h of the f-counters follows counter state 1fh in the b-channel fifos. the counter state 10h of the f-counters follows counter state 1fh in the d-channel fifos. 3.5.1 fifo counters location in memory window for each fifo one f1 and one f2 counter is available. the counters are located at the following offsets to the memory window base address (mwba) in the memory window (mw). fifo counter offset to memory window base address counter size in bytes b1-transmit f1 2080h 1 f2 *) 2081h 1 b1-receive f1 *) 6080h 1 f2 6081h 1 b2-transmit f1 2180h 1 f2 *) 2181h 1 b2-receive f1 *) 6180h 1 f2 6181h 1 d-transmit f1 20a0h 1 f2 *) 20a1h 1 d-receive f1 *) 60a0h 1 f2 60a1h 1 *) these counters are handled by the hfc-s pci a automatically and must not be written by software.
863c @39 1 :q^eqbi " ! "' _v (# cologne chip for each fifo an array of z1 and z2 counters is available. the offset of the counters to the memory window base address (mwba) can be calculated as shown in the following table. fifo counter offset to memory window base address counter size in bytes b1-transmit z1 2000h + (fx * 4) 2 z2 *) 2000h + (fx * 4) + 2 2 b1-receive z1 *) 6000h + (fx * 4) 2 z2 6000h + (fx * 4) + 2 2 b2-transmit z1 2100h + (fx * 4) 2 z2 *) 2100h + (fx * 4) + 2 2 b2-receive z1 *) 6100h + (fx * 4) 2 z2 6100h + (fx * 4) + 2 2 d-transmit z1 2080h + (fx * 4) 2 z2 *) 2080h + (fx * 4) + 2 2 d-receive z1 *) 6080h + (fx * 4) 2 z2 6080h + (fx * 4) + 2 2 *) these counters are handled by the hfc-s pci a automatically and must not be written by software. fx is either f1 or f2. f1 is used for input data in transmit fifos, f2 is used for output data in receive fifos. 3.5.2 fifo data location in memory window fifo starting at offset ending at offset offset to add to z-counters value b1-transmit 0200h 1fffh 0000h b1-receive 4200h 5fffh 4000h b2-transmit 2200h 3fffh 2000h b2-receive 6200h 7fffh 6000h d-transmit 0000h 01ffh 0000h d-receive 4000h 41ffh 4000h
863c @39 1 "( _v (# :q^eqbi " ! cologne chip 3.5.3 fifo channel operation 3.5.3.1 send channels (b1, b2 and d transmit) the send channels send data from the host bus interface to the fifo and the hfc-s pci a converts the data into hdlc code and tranfers it from the fifo into the s/t or/and the gci/iom2 bus interface write registers. the hfc-s pci a checks z1 and z2. if z1=z2 (fifo empty) the hfc-s pci a generates a hdlc-flag (01111110) and sends it to the s/t device. in this case z2 is not incremented. if also f1=f2 only hdlc flags are sent to the s/t interface and all counters remain unchanged. if the frame counters are unequal f2 is incremented and the hfc-s pci a tries to send the next frame to the output device. after the end of a frame (z2 reaches z1) it automatically generates the 16 bit crc checksum and adds the ending flag. if there is another frame in the fifo (f1 1 f2) the f2 counter is incremented. with every byte being sent from the host bus side to the fifo z1 is incremented automatically. if a complete frame has been sent f1 must be incremented to send the next frame. if the frame counter f1 is incremented also the z-counters may change because z1 and z2 are functions of f1 and f2. so there are z1(f1), z2(f1), z1(f2) and z2(f2) (see figure 6). z1(f1) is used for the frame which is just written from the pc-bus side. z2(f2) is used for the frame which is just beeing transmitted to the s/t device side of the hfc-s pci a. z1(f2) is the end of frame pointer of the current output frame. z1 00 z2 00 z2 02 z1 02 z1 06 z1 07 fx = 00h f2 = 02h f1 = 07h fx = 1fh 696? c`qsu y^ =u]_bi gy^t_g j3_e^dubc dqr\u y^ =u]_bi gy^t_g output fram e 02 fram e 03 end of fram e end of frame fram e 06 input fram e 07 f2 f1 figure 6: fifo organisation (shown for b-channel, similar for d-channel)
863c @39 1 :q^eqbi " ! ") _v (# cologne chip in the send channels f1 is only changed from the pc interface side if the software driver wants to say ?end of send frame. then the current value of z1 is stored, f1 is incremented and z1 is used as start address of the next frame. z1(f2) and z2(f2) can not be accessed. 3.5.3.2 automatically d-channel frame repetition the d-channel send fifo has a special feature. if the s/t interface signals a d-channel contention before the crc is sent the z2 counter is set to the starting address of the current frame and the hfc- s pci a tries to repeat the frame automatically. * important! the hfc-s pci a begins to transmit bytes from a fifo at the moment z1 1 z2. so if the z1 pointer is updated by software after writing the transmit data into the fifo space of the memory window the transmission starts. 3.5.3.3 fifo full condition in send channels fifo full condition can easily be calculated from the z1/z2 table in the memory window. remember that an increment of z-value 1fffh is 0200h in the b-channels! there are two different fifo full conditions. the first one is met when the fifo contents comes up to 31 frames (b-channel) or 15 frames (d-channel). there is no possibility for the hfc-s pci a to manage more frames even if the frames are very small. the second limitation is the size of the fifo which is 512 byte for the d-channel and 7.5 kbyte for the b-channels. 3.5.3.4 receive channels (b1, b2 and d receive) the receive channels receive data from the s/t or gci/iom2 bus interface read registers. the data is converted from hdlc into plain data and sent to the fifo. the data can then be read via the host bus interface. the hfc-s pci a checks the hdlc data coming in. if it finds a flag or more than 5 consecutive 1s it does not generate any output data. in this case z1 is not incremented. proper hdlc data being received is converted by the hfc-s pci a into plain data. after the ending flag of a frame the hfc-s pci a checks the hdlc crc checksum. if it is correct one byte with all 0s is inserted behind the crc data in the fifo named stat. this last byte of a frame in the fifo is different from all 0s if there is no correct crc field at the end of the frame.
863c @39 1 # _v (# :q^eqbi " ! cologne chip the ending flag of a hdlc-frame can also be the starting flag of the next frame. after a frame is received completely f1 is incremented by the hfc-s pci a automatically and the next frame can be received. after reading a frame via the host bus interface f2 must be incremented. if the frame counter f2 is incremented also the z-counters may change because z1 and z2 are functions of f1 and f2. so there are z1(f1), z2(f1), z1(f2) and z2(f2) (see figure 6). z1(f1) is used for the frame which is just received from the s/t device side of the hfc. z2(f2) is used for the frame which is just beeing transmitted to the host bus interface. z1(f2) is the end of frame pointer of the current output frame. to calculate the length of the current receive frame the software has to evaluate z1-z2+1. in the receive channels f2 must be incremented to point to the next z1/z2 pair. if z1 = z2 and f1 = f2 the fifo is totally empty. figure 7: fifo data organisation
863c @39 1 :q^eqbi " ! #! _v (# cologne chip 3.5.3.5 fifo full condition in receive channels because the isdn-b-channels and the isdn-d-channels have no hardware based flow control there is no possibility to stop input data if a receive fifo is full. so there is no fifo full condition implemented in the hfc-s pci a. the hfc-s pci a assumes that the fifos are so deep that the host processor hard- and software is able to avoid any overflow of the receive fifos. overflow conditions are again more than 31 input frames (15 frames for d-channel) or a real overflow of the fifo because of excessive data. because hdlc procedures only know a window size of 7 frames no more than 7 frames are sent without software intervention. due to the great size of the fifos of the hfc-s pci a it is easy to poll counters in the memory window even in large time intervalls without having to fear a fifo overflow condition. however to avoid any undetected fifo overflows the software driver should check the number of frames in the fifo which is f1-f2. an overflow exists if the number (f1-f2) is less than the number in the last reading even if there was no reading of a frame in between. after a detected fifo overflow condition this fifo must be reset. 3.5.3.6 fifo initialisation all counters z1, z2, f1 and f2 of all fifos are initialized to all 1s after a reset. then the result is z1 = z2 = 1fffh and f1 = f2 = 1fh for the b-channels and z1 = z2 = 1ffh and f1 = f2 = 1fh for the d-channel. this information is written in the memory window for initialisation. please mask bit 4 of d-channel from counter f1, f2. the same initialisation is done if the bit 3 in the cirm register is set (soft reset). during initialisation phase the hfc-s pci a must not be accessed. bit 1 of the status register is cleared to '0' to indicate that the initialisation phase has been finished.
863c @39 1 #" _v (# :q^eqbi " ! cologne chip 3.5.4 transparent mode of hfc-s pci a you can switch off hdlc operation for each b-channel independently. there is one bit for each b- channel in the ctmt control register. if this bit is set data in the fifo is sent directly to the s/t or gci/iom2 bus interface and data from the s/t or gci/iom2 bus interface is sent directly to the fifo. be sure to switch into transparent mode only if f1=f2. being in transparent mode the fx counters remain unchanged. z1 and z2 are the input and output pointers respectively. because f1=f2 both z-counters are always accessable and have valid data. if a send fifo channel changes to fifo empty condition no crc is generated and the last data byte written into the fifo is repeated until there is new data. in receive channels there is no check on flags or correct crcs and no status byte is added. the byte bounderies are not arbitrary like in hdlc mode where byte synchronisation is achieved with hdlc-flags. the data is just the same as it comes from the s/t or gci/iom2 bus interface or is sent to this. send and receive transparent data can be handled in two ways. the usual way is transmitting b-channel data with the lsb first as it is usual in hdlc mode. the second way is sending the bytes in reverse bit order as it is usual for pwm data. so the first bit is the msb. the bit order can be reversed by setting the corresponding bits in the cirm register.
863c @39 1 :q^eqbi " ! ## _v (# cologne chip 3.6 configuring test loops for electrical tests of layer 1 it is useful to create a s/t test loop for the b1/b2 channel. the test loop described here transmits the data that has been received on the b1 or b2 channel to the same channel on the s/t interface. the 32k memory window base address (mwba) pci configuration register must be written first to enable pci master accesses of the hfc-s pci a. to configure the test loop the following must be done: - write 0fh to register clkdel ( dch ) // adjust the phase offset between receive and // transmit direction (the value depends on the external // circuitry). - write 43h to register sctrl ( c4h ) // 03h is to enable b1, b2 at the s/t interface for // transmission // 40h is for tx_lo setup (capacitive line mode) - write 00h to register states ( c0h ) // release s/t state machine for activation over the // s/t interface by incoming info 2 or info 4. - write 03h to register sctrl_r ( cch ) // configure s/t b1 and b2 channel to normal // receive operation. - write 36h to register connect ( bch ) // configure connect register for b1/b2 channel // test loop. - write 80h to register b1_ssl ( 80h ) // enable transmit channel for gci/iom2 bus, pin // stio1 is used as output, use time slot #0. - write c0h to register b1_rsl ( 90h ) // enable receive channel for gci/iom2 bus, pin // stio1 is used as input, use time slot #0. - write 81h to register b2_ssl ( 84h ) // enable transmit channel for gci/iom2 bus, pin // stio1 is used as output, use transmission slot #1. - write c1h to register b2_rsl ( 94h ) // enable receive channel for gci/iom2 bus, pin // stio1 is used as input, use time slot #1. - write 01h to register mst_mode ( b8h ) // configure hfc-s pci a as gci/iom2 bus master.
863c @39 1 #$ _v (# :q^eqbi " ! cologne chip 4 register bit description 4.1 register bit description of s/t section name addr. bits r/w function states c0h 3..0 r binary value of actual state (nt: gx, te: fx) (read) 4 r frame-sync ('1'=synchronized) 5 r '1' timer t2 expired (nt mode only, see also 8.1 s/t interface activation/deactivation layer 1 for finite state matrix for nt on page 62) 6 r '1' receiving info0 7 r '0' no operation '1' in nt mode allows transition from g2 to g3. this bit is automatically cleared after the transition. states c0h 3..0 w binary value of new state (nt: gx, te: fx) (bit 4 must also be set to load the state). (write) 4 w '1' loads the prepared state (bit 3..0) and stops the state machine.this bit needs to be set for a minimum period of 5.21 p s and must be cleared by software. (reset default) '0' enables the state machine (bits 3..0 are ignored). after writing an invalid state the state machine goes to deactivated state (g1, f2) 6..5 w '00' no operation '01' no operation '10' start deactivation '11' start activation the bits are automatically cleared after activation/deactivation. 7 w '0' no operation '1' in nt mode allows transition from g2 to g3. this bit is automatically cleared after the transition. * important! the state machine is stuck to '0' after a reset. writing a '0' to bit 4 of the states register restarts the state machine. in this state the hfc-s pci a sends no signal on the s/t-line and it is not possible to activate it by incoming infox. nt mode: the nt state machine does not change automatically from g2 to g3 if the te side sends info3 frames. this transition must be activated each time by bit 7 of the states register. fix the nt state machine to state g3 when activated (by writing 13h into states register). this prevents deactivation of nt mode s/t interface due to sporadically errors on nt input data.
863c @39 1 :q^eqbi " ! #% _v (# cologne chip name addr. bits r/w function sctrl c4h b-channel enable 0 w '0' b1 send data disabled (permanent 1 sent in activated states, reset default) '1' b1 data enabled 1 w '0' b2 send data disabled (permanent 1 sent in activated states, reset default) '1' b2 data enabled 2 w s/t interface mode '0' te mode (reset default) '1' nt mode 3 w d-channel priority '0' high priority 8/9 (reset default) '1' low priority 10/11 4 w s/q bit transmission '0' s/q bit disable (reset default) '1' s/q bit and multiframe enable 5 w '0' normal operation (reset default) '1' send 96khz transmit test signal (alternating zeros) 6 w tx_lo line setup this bit must be configured depending on the used s/t module and circuitry to match the 400 w pulse mask test. '0' capacitive line mode (reset default) '1' non capacitive line mode 7 w power down '0' power up, oscillator active (reset default) '1' power down, oscillator stopped sctrl_e c8h 0 w power down mode bit '0' s/t awake disable (reset default) power up can only be programmed by register access (sctrl bit 7). '1' s/t awake enable. oscillator starts on every non info0 s/t signal. 1 w must be '0' 2 w d reset '0' normal operation (reset default) '1' d bits are forced to '1' 3 w d_u enable '0' normal operation (reset default) '1' d channel is always send enabled regardless of e receive bit 6..4 w must be '0' 7 w '0' normal operation (reset default) '1' b1/b2 are exchanged in the s/t interface
863c @39 1 #& _v (# :q^eqbi " ! cologne chip name addr. bits r/w function sctrl_r cch 0 1 w w b1-channel receive enable b2-channel receive enable '0' b-receive bits are forced to '1' '1' normal operation 7..2 w unused sq_rec d0h 3..0 r te mode: s bits (bit 3 = s1, bit 2 = s2, bit 1 = s3, bit 0 = s4) nt mode: q bits (bit 3 = q1, bit 2 = q2, bit 1 = q3, bit 0 = q4) 4 r '1' a complete s or q multiframe has been received reading sq_rec clears this bit. 6..5 r not defined 7 r '1' ready to send a new s or q multiframe writing to sq_send clears this bit. sq_send d0h 3..0 w te mode: q bits (bit 3 = q1, bit 2 = q2, bit 1 = q3, bit 0 = q4) nt mode: s bits (bit 3 = s1, bit 2 = s2, bit 1 = s3, bit 0 = s4) 7..4 w not defined clkdel dch 3..0 w te: 4 bit delay value to adjust the 2 bit delay time between receive and transmit direction. the delay of the external s/t-interface circuit can be compensated. the lower the value the smaller the delay between receive and transmit direction (see also figure 15) nt: data sample point. the lower the value the earlier the input data is sampled. the steps are 163ns. 6..4 w nt mode only early edge input data shaping low pass characteristic of extended bus configurations can be compensated. the lower the value the earlier input data pulse is sampled. no compensation means a value of 6 (110b). step size is the same as for bits 3-0. 7 w unused * note! the register is not initialized with a '0' after reset. the register should be initialized as follows before activating the te/nt state machine: te mode: 0dh .. 0fh nt mode: 6ch
863c @39 1 :q^eqbi " ! #' _v (# cologne chip 4.2 register bit description of gci/iom2 bus section timeslots for transmit direction name addr. bits r/w function b1_ssl 80h 4..0 w select gci/iom2 bus transmission slot (0..31) b2_ssl 84h 5 w unused aux1_ssl aux2_ssl 88h 8ch 6 w select gci/iom2 bus data lines '0' stio1 output '1' stio2 output 7 w transmit channel enable for gci/iom2 bus '0' disable (reset default) '1' enable * important! enabling more than one channel on the same slot causes undefined output data. timeslots for receive direction name addr. bits r/w function b1_rsl 90h 4..0 w select gci/iom2 bus receive slot (0..31) b2_rsl 94h 5 w unused aux1_rsl aux2_rsl 98h 9ch 6 w select gci/iom2 bus data lines '0' stio2 is input '1' stio1 is input 7 w receive channel enable for gci/iom2 bus '0' disable (reset default) '1' enable data registers name addr. bits r/w function b1_d b2_d aux1_d aux2_d a0h a4h a8h ach 0..7 r/w read/write data registers for selected timeslot data * note! if the data registers aux1_d and aux2_d are not overwritten, the transmisson slots aux1_ssl and aux2_ssl mirror the data received in aux1_rsl and aux2_rsl slots. this is useful for an internal connection between two codecs. this mirroring is disabled by setting bit 1 in mst_emod register
863c @39 1 #( _v (# :q^eqbi " ! cologne chip name addr. bits r/w function mst_mode b8h 0 w gci/iom2 bus mode '0' slave (reset default) (c4io and f0io are inputs) '1' master (c4io and f0io are outputs) 1 w polarity of c4- and c2o-clock '0' f0io is sampled on negative clock transition '1' f0io is sampled on positive clock transition 2 w polarity of f0-signal '0' f0 positive pulse '1' f0 negative pulse 3 w duration of f0-signal '0' f0 active for one c4-clock (244ns) (reset default) '1' f0 active for two c4-clocks (488ns) 5, 4 w time slot for codec-a signal f1_a '00' b1 receive slot '01' b2 receive slot '10' aux1 receive slot '11' signal c2o ? pin f1_a (c2o is 2048 khz clock) 7, 6 w time slot for codec-b signal f1_b '00' b1 receive slot '01' b2 receive slot '10' aux1 receive slot '11' aux2 receive slot the pulse shape and polarity of the codec signals f1_a and f1_b is the same as the pulseshape of the f0io signal. the polarity of c2o can be changed by bit 1. reset sets register mst_mode to all '0's.
863c @39 1 :q^eqbi " ! #) _v (# cologne chip name addr. bits r/w function mst_emod b4h 0 w slow down c4io clock adjustment (see figure 18) '0' c4io clock is adjusted in the 31th time slot twice for one half clock cycle (reset default) '1' c4io clock is adjusted in the 31th time slot once for one half clock cycle 1 w enable/disable aux channel mirroring '0' normal opration (reset default) '1' disable aux channel data mirroring 2 w unused 5..3 w select d-channel data flow (see also: connect register) destination source bit 3: '0' d-hfc ? d-s/t '1' d-hfc ? d-gci/iom2 bit 4: '0' d-s/t ? d-hfc '1' d-s/t ? d-gci/iom2 bit 5: '0' d-gci/iom2 ? d-hfc '1' d-gci/iom2 ? d-s/t 6 w unused 7 w enable gci/iom2 write slots '0' disable gci/iom2 write slots; slot #2 and slot #3 may be used for normal data '1' enables slot #2 and slot #3 as master, d- and c/i-channel c/i 08h 3..0 r/w on read: indication on write: command 7..4 unused trxr 0ch 0 r '1' monitor receive ready (2 bytes received) this bit is reset after read of second monitor byte (mon2_d) 1 r '1' monitor transmitter ready writing on mon2_d starts transmisssion and resets this bit. 5..2 r reserved 6rstio2 in 7rstio1 in reset sets register mst_emod to all '0's.
863c @39 1 $ _v (# :q^eqbi " ! cologne chip 4.3 register bit description of connect register name addr. bits r/w function connect bch 2..0 w select b1-channel data flow destination source bit 0: '0' b1-hfc ? b1-s/t '1' b1-hfc ? b1-gci/iom2 bit 1: '0' b1-s/t ? b1-hfc '1' b1-s/t ? b1-gci/iom2 bit 2: '0' b1-gci/iom2 ? b1-hfc '1' b1-gci/iom2 ? b1-s/t 5..3 w select b2-channel data flow destination source bit 3: '0' b2-hfc ? b2-s/t '1' b2-hfc ? b2-gci/iom2 bit 4: '0' b2-s/t ? b2-hfc '1' b2-s/t ? b2-gci/iom2 bit 5: '0' b2-gci/iom2 ? b2-hfc '1' b2-gci/iom2 ? b2-s/t 7..6 w unused reset sets connect register to all '0's. the following figure shows the different options for switching the b-channels with the connect register. figure 8: function of the connect register bits
863c @39 1 :q^eqbi " ! $! _v (# cologne chip 4.4 register bit description of auxiliary and cross data registers name addr. bits r/w function cirm 60h 2..0 w defines the length of the auxiliary port access: value cycle time (aux_wr or aux_rd low) 000b 1 pci-clock 001b 3 pci-clocks 010b 5 pci-clocks 011b 7 pci-clocks 100b 9 pci-clocks 101b 11 pci-clocks 110b 13 pci-clocks 111b 15 pci-clocks 3 w soft reset, similar as hardware reset; the registers cip, cirm and ctmt are not changed. the pci interface is not reset. the reset is active until the bit is cleared. '0' deactivate reset (reset default) '1' activate reset 5..4 w must be '0' 6 w select bit order for b1 channel '0' normal read/write data operation '1' reverse bit order read/write data operation 7 w select bit order for b2 channel '0' normal read/write data operation '1' reverse bit order read/write data operation fifo_en 44h 5..0 w fifo enable/disable ('1' = enable (reset default)) bit fifo 0 b1-transmit 1 b1-receive 2 b2-transmit 3 b2-receive 4 d-transmit 5 d-receive the enable/disable change becomes valid between 0 and 250s after the bit has been written. all pci bus accesses and fifo activities are disabled for the selected fifos. to avoid unnecessary pci transfers all unused fifos should be disabled. at least one fifo (usually d-receive) must be enabled. 7..6 w unused, should be '0'
863c @39 1 $" _v (# :q^eqbi " ! cologne chip name addr. bits r/w function ctmt 64h 0 w hdlc/transparent mode for b1-channel '0' hdlc mode (reset default) '1' transparent mode 1 w hdlc/transparent mode for b2-channel '0' hdlc mode (reset default) '1' transparent mode 4..2 w select timer (bit 4 = msb) timer '000' off '001' 3.125ms '010' 6.25ms '011' 12.5ms '100' 25ms '101' 50ms '110' 400ms '111' 800ms 5 w timer reset mode '0' reset timer by ctmt bit 7 (reset default) '1' automatically reset timer at each access to hfc-s pci a 6 w ignored 7 w reset timer '1' reset timer this bit is automatically cleared. chip_id 58h 0 r power supply '0' 5v pci signaling environment '1' 3.3v pci signaling environment 3..1 r reserved 7..4 r chip identification 0011b hfc-s pci a b_mode 4ch 1..0 w unused 2 w in 64 kbit/s mode: bit is ignored in 56 kbit/s mode: value of the lsb in 7-bit mode 3 w unused 4 w 56 kbit/s mode selection bit for b1-channel '0' 64 kbit/s mode (reset default) '1' 56 kbit/s mode 5 w 56 kbit/s mode selection bit for b2-channel '0' 64 kbit/s mode (reset default) '1' 56 kbit/s mode 6 w '0' data not inverted for b1-channel (reset default) '1' data inverted for b1-channel 7 w '0' data not inverted for b2-channel (reset default) '1' data inverted for b2-channel
863c @39 1 :q^eqbi " ! $# _v (# cologne chip name addr. bits r/w function int_m1 68h 0 w interrupt mask for channel b1 in transmit direction 1 w interrupt mask for channel b2 in transmit direction 2 w interrupt mask for channel d in transmit direction 3 w interrupt mask for channel b1 in receive direction 4 w interrupt mask for channel b2 in receive direction 5 w interrupt mask for channel d in receive direction 6 w interrupt mask for state change of te/nt state machine 7 w interrupt mask for timer for mask bits a '1' enables and a '0' disables interrupt. reset clears all bits to '0'. name addr. bits r/w function int_m2 6ch 0 w interrupt mask for processing/non processing phase transition 1 w interrupt mask for gci i-change 2 w interrupt mask for gci monitor receive 3 w enable for interrupt output ('1' = enable) 6..4 w unused 7 w pmesel '0' pme triggered on d-channel receive int '1' pme triggered on s/t interface state change for mask bits a '1' enables and a '0' disables interrupt. reset clears all bits to '0'. name addr. bits r/w function trm 48h 1..0 w interrupt in transparent mode is generated if z1 in receive fifos or z2 in transmit fifos change from: 00: x xxxx x011 1111 ? x xxxx x100 0000 01: x xxxx 0111 1111 ? x xxxx 1000 0000 10: x xxx0 1111 1111 ? x xxx1 0000 0000 11: x 0111 1111 1111 ? x 1000 0000 0000 4..2 w must be '0' 5w e ? b2 receive channel when set the e receive channel of the s/t interface is connected to the b2 receive channel. 6 w b1+b2 mode '0' normal operation (reset default) '1' b1+b2 are combined to one hdlc or transparent channel. all settings for data shape and connect are derived from b1. both b1 and b2 channel fifos must be enabled to use b1+b2 mode. 7 w iom test loop when set mst output data is looped to the mst input.
863c @39 1 $$ _v (# :q^eqbi " ! cologne chip name addr. bits r/w function int_s1 78h 0 1 r r b1-channel interrupt status in transmit direction b2-channel interrupt status in transmit direction in hdlc mode: '1' a complete frame has been transmitted, the frame counter f2 has been incremented in transparent mode: '1' interrupt as selected in trm register bits 1..0 2 r d-channel interrupt status in transmit direction '1' a complete frame was transmitted, the frame counter f2 was incremented 3 4 r r b1-channel interrupt status in receive direction b2-channel interrupt status in receive direction in hdlc mode: '1' a complete frame has been transmitted, the frame counter f1 has been incremented in transparent mode: '1' interrupt as selected in trm register bits 1..0 5 r d-channel interrupt status in receive direction '1' a complete frame was received, the frame counter f1 was incremented 6 r te/nt state machine interrupt status '1' state of state machine changed 7 r timer interrupt status '1' timer is elapsed int_s2 7ch 0 r processing/non processing transition interrupt status '1' the hfc-s pci a has changed from processing to non processing state. 1 r gci i-change interrupt '1' a different i-value on gci was detected 2 r receiver ready (rxr) of monitor channel '1' 2 monitor bytes have been received 6..3 r unused, '0' 7 r '1' fatal error: synchronisation lost. pci performance too low for hfc-s pci a. only soft reset recovers from this situation. * important! reading the int_s1 or int_s2 register resets all active read interrupts in the int_s1 or int_s2 register. new interrupts may occur during read. these interrupts are reported at the next read of int_s1 or int_s2. all interrupt bits are reported regardless of the mask registers settings (int_m1 and int_m2). the mask register settings only influence the interrupt output condition. the interrupt output goes inactive during the read of int_s1 or int_s2. if interrupts occur during this read the interrupt line goes active immediately after the read is finished. so processors with level or transition triggered interrupt inputs can be connected.
863c @39 1 :q^eqbi " ! $% _v (# cologne chip name addr. bits r/w function status 70h 0 r always '0' 1 r processing/non processing status '1' the hfc-s pci a is in processing phase (every 125s) '0' the hfc-s pci a is not in processing phase 2 r processing/non processing transition interrupt status '1' the hfc-s pci a has finished internal processing phase (every 125s) 3ralways '0' 4 r timer status '0' timer not elapsed '1' timer elapsed 5 r te/nt state machine interrupt state '1' state of state machine has changed 6 r frame interrupt has occured (any data channel interrupt) all masked d-channel and b-channel interrupts are "ored" 7 r any interrupt all masked interrupts are "ored" reading the status register clears no bit.
863c @39 1 $& _v (# :q^eqbi " ! cologne chip 5 electrical characteristics absolute maximum ratings parameter symbol rating supply voltage v dd -0.3v to +7.0v input voltage v i -0.3v to v dd + 0.3v output voltage v o -0.3v to v dd + 0.3v operating temperature t opr -10c to +85c storage temperature t stg -40c to +125c recommended operating conditions parameter symbol condition min. typ. max. supply voltage v dd v dd =5v v dd =3.3v 4.75v 3.15v 5.0v 3.3v 5.25v 3.45v operating temperature t opr 0c +70c electrical characteristics for 5v power supply v dd = 4.75v to 5.25v, t opr = 0c to +70c parameter symbol condition ttl level cmos level min. typ. max. min. typ. max. input low voltage v il 0.8v 1.0v input high voltage v ih 2.0v 3.5v output low voltage v ol 0.4v 0.4v output high voltage v oh 4.3v 4.3v output leakage current | i oz | high z 10a 10a pull-up resistor input current | i il |v i = v ss 50a 50a electrical characteristics for 3.3v power supply v dd = 3.15v to 3.45v, t opr = 0c to +70c parameter symbol condition ttl level cmos level min. typ. max. min. typ. max. input low voltage v il 0.8v 1.0v input high voltage v ih 2.0v 2.3v output low voltage v ol 0.4v 0.4v output high voltage v oh 2.4v 2.4v
863c @39 1 :q^eqbi " ! $' _v (# cologne chip dc current consumption of hfc-s pci a 25c ambient temperature, 5 v operating voltage, 33 mhz pci clock condition min. typ. max. pci master, pcm master (full operational) 24,5 ma power down, no s/t awake (12.288 mhz osc off) 15 ma all pins gnd (except power supply) 1 ma
863c @39 1 $( _v (# :q^eqbi " ! cologne chip i/o characteristics input interface level ad0-31 pci par pci c/be0-3 pci rst# pci frame# pci irdy# pci trdy# pci stop# pci idsel pci devsel# pci gnt# pci perr# pci daux0-7 ttl c4io ttl, internal pull-up resistor f0io ttl, internal pull-up resistor stio1-2 ttl, internal pull-up resistor ee_sda ttl, internal pull-up resistor ee_scl/en ttl, internal pull-up resistor
863c @39 1 :q^eqbi " ! $) _v (# cologne chip driver capability low high output 0.4v 0.6v v dd - 0.4v ad0-31 *) 6ma 3ma par *) 6ma 3ma c/be0-3 *) 6ma 3ma frame# *) 6ma 3ma irdy# *) 6ma 3ma trdy# *) 6ma 3ma stop# *) 6ma 3ma devsel# *) 6ma 3ma req# *) 6ma 3ma perr# *) 6ma 3ma serr# *) 6ma 3ma pme 2ma 1ma inta# *) 6ma 3ma daux0-7 4ma 2ma /aux_wr 2ma 1ma /aux_rd 2ma 1ma /adr_wr 8ma 4ma tx2_hi 6ma 3ma /tx1_lo 6ma 3ma /tx_en 4ma 2ma /tx2_lo 6ma 3ma tx1_hi 6ma 3ma adj_lev 1ma 0.5ma c4io 8ma 4ma f0io 8ma 4ma stio1-2 8ma 4ma f1_a-b 6ma 3ma ee_sda 1ma 0.5ma ee_scl/en 1ma 0.5ma *) pci buffer is pci spec. 2.2 compliant.
863c @39 1 % _v (# :q^eqbi " ! cologne chip 6 timing characteristics 6.1 pci bus timing the timing characteristics of the hfc-s pci as integrated pci bus interface is compliant with version 2.1 of the pci local bus specification. 6.2 gci/iom2 bus clock and data alignment for mitel st tm bus figure 9: gci/iom2 bus clock and data alignment
863c @39 1 :q^eqbi " ! %! _v (# cologne chip 6.3 gci/iom2 timing timing diagram 1: gci/iom2 timing *) f0io starts one c4io clock earlier if bit 3 in mst_mode register is set. if this bit is set f0io is also awaited one c4io clock cycle earlier. 6.3.1 master mode to configure the hfc-s pci a as gci/iom2 bus master bit 0 of the mst_mode register must be set. in this case c4io and f0io are outputs. symbol characteristics min. typ. max. t c4p clock c4io period (4.096 mhz) 180 ns *) 244.14 ns *) 308 ns *) t c4h clock c4io high width 78 ns *) 122 ns *) 166 ns *) t c4l clock c4io low width 78 ns *) 122 ns *) 166 ns *) t c2p clock c2o period 360 ns 488.28 ns 616 ns t c2h clock c2o high width 180 ns 244.14 ns 308 ns t c2l clock c2o low width 180 ns 244.14 ns 308 ns
863c @39 1 %" _v (# :q^eqbi " ! cologne chip symbol characteristics min. typ. max. short f0io 230 ns 244 ns 260 ns t f0iw f0io width long f0io 460 ns 488 ns 520 ns t stod stio1/2 delay fom c4io level 1 output 10 ns 25 ns 1 half clock adjust 124.955 us 125.000 us 125.045 us t f0icycle f0io cycle time 2 half clocks adjust 124.910 us 125.000 us 125.090 us all specifications are for 2.048 mb/s streams and f clk = 12.288 mhz. *) time depends on accuracy of osc_in frequency. because of clock adjustment in the 31st time slot these are the worst case timings when c4io is adjusted. 6.3.2 slave mode to configure the hfc-s pci a as gci/iom2 bus slave bit 0 of the mst_mode register must be cleared (reset default). in this case c4io and f0io are inputs. symbol characteristics min. typ. max. t c4p clock c4io period (4.096 mhz) 244.14 ns *) t c4h clock c4io high width 20 ns t c4l clock c4io low width 20 ns t c2p clock c2o period 488.28 ns *) t c2h clock c2o high width 25 ns t c2l clock c2o low width 25 ns t f0is f0io setup time to c4io 20 ns t f0ih f0io hold time after c4io 20 ns t f0iw f0io width 40 ns t stis stio2 setup time 20 ns t stih stio2 hold time 20 ns all specifications are for 2.048 mb/s streams and f clk = 12.288 mhz. *) if the s/t interface is synchronized from c4io (nt mode) the frequency must be stable to ? 10 -4 .
863c @39 1 :q^eqbi " ! %# _v (# cologne chip 6.4 eeprom access symbol characteristics typ. f scl serial clock frequency 32.2 khz *) t scl serial clock period 1 / f scl t hd:sta start condition hold time ? t scl t low clock low period ? t scl t high clock high period ? t scl t su:sta start condition setup time ? t scl t hd:dat output data change after clock 10 ns t su data in setup time 100 ns t dh data in hold time 100 ns *) with 33 mhz pci clock timing diagram 2: eeprom access
863c @39 1 %$ _v (# :q^eqbi " ! cologne chip 6.5 auxiliary port access 6.5.1 write access t clk t hold t adw low t setup t outsetup t axw rlow t d t d pciclk adr out data out **) daux0-7 /ad r_w r /au x_w r timing diagram 3: auxiliary port write access symbol characteristics typ. t clk pci clock period (33 mhz) 30 ns t setup address setup time before /adr_wr t clk t adwlow /adr_wr low time t clk t hold address hold time after /adr_wr - t clk t outsetup data out setup time before /aux_wr t clk t axwlow /aux_wr low time 3 x t clk *) t d delay time between pciclk - and /adr_wr or /aux_wr 10 ns *) configurable (see also: cirm register bit description) **) data out is valid until the next auxiliary port write access is initiated
863c @39 1 :q^eqbi " ! %% _v (# cologne chip 6.5.2 read access t clk t hold t in h o l d t in s et u p t adw low t setup t axrdlow t d t tri t d pciclk d ata in adr out daux0-7 /adr_wr /aux_rd timing diagram 4: auxiliary port read access symbol characteristics typ. t clk pci clock period (33 mhz) 30 ns t setup address setup time before /adr_wr t clk t adwlow /adr_wr low time t clk t hold address hold time after /adr_wr - t clk t insetup minimum data in setup time before /aux_rd - 20 ns t axrdlow /aux_rd low time 3 x t clk *) t inhold data in hold time after /aux_rd - 0 ns t d delay time between pciclk - and /adr_wr or /aux_rd 10 ns t tri time data floating after pciclk - 20 ns *) configurable (see also: cirm register bit description)
863c @39 1 %& _v (# :q^eqbi " ! cologne chip 7 s/t interface circuitry in order to comply to the physical requirements of itu-t recommendation i.430 and considering the national requirements concerning overvoltage protection and electromagnetic compatibility (emc), the hfc-s pci a needs some additional circuitry, which are shown in the following figures. 7.1 external receiver circuitry part list vdd 5v 3.3v r1, r1' 33 k : r2, r2' 100 k : r3 1 m : 680k : r4 3.9 k : r5, r5' 4.7 k : r6, r6' 4.7 k : r7 1.8 m : 1.2m : c1 47 nf c3, c3' 22pf d1, d2 1n4148 or ll4148 d3, d4 1n4148 or ll4148 s/t module see table 5 on page 59. c3, c3' are for reduction of high frequency input noise and should be located as close as possible to the hfc-s pci a. r5 adj_lev r4 r2 r2 lev_r2 c3 gnd c1 r7 r1 r1 lev_r1 r2 r1 c3 r5 gnd r3 vdd r6 d3 d4 12 14 rx - vdd d1 d2 r6 10 11 s/t module 5 s/t side 16 rx + figure 10: external receiver circuitry
863c @39 1 :q^eqbi " ! %' _v (# cologne chip 7.2 external transmitter circuitry part list vdd 5v 3.3v r1 2.2 k : ? 1% 560 : ? 1% r2 3.0 k : ? 1% 3.9 k : ? 1% r3, r3' *) 18 : 18 : r4 100 : 0 : r5 5.6 k : 3.3 k : r6 3.3 k : 2.2 k : r7 3.3 k : 1.8 k : r8 2.2 k : 2.2 k : c3 470 pf d2, d3 1n4148 or ll4148 d4, d5 1n4148 or ll4148 zd1 z-diode 2.7 v (e. g. bzv 55c 2v7) t1, t1' bc550c, bc850c or similar t2, t2' bc550c, bc850c or similar t3 bc560c, bc860c or similar s/t module see table 5 on page 59. *) value is depending on the used s/t module r2 tx2_lo t2 gnd d2 d4 r3 r8 r3 t2 t1 r1 tx1_hi r7 t1 t3 r4 c3 r6 r2 s/t module d5 d3 zd1 7 8 9 tx1_lo gnd tx - s/t side tx + 18 3 1 tx2_hi r1 tx_en r5 vdd figure 11: external transmitter circuitry
863c @39 1 %( _v (# :q^eqbi " ! cologne chip s/t module part number manufacturer apc 56624-1 apc 40495s (smd) s-hybrid modules with receiver and transmitter circuitry included: apc 5568-3v apc 5568-5v apc 5568ds-3v apc 5568ds-5v advanced power components united kingdom phone: +44 1634-290588 fax: +44 1634-290591 http://www.apcisdn.com fe 8131-55z fee gmbh singapore phone: +65 741-5277 fax: +65 741-3013 bangkok phone: +662 718-0726-30 fax: +662 718-0712 germany phone: +49 6106-82980 fax: +49 6106-829898 transformers: pe-64995 pe-64999 pe-65795 (smd) pe-65799 (smd) pe-68995 pe-68999 t5006 (smd) t5007 (smd) s 0 -modules: t5012 t5034 t5038 pulse engineering, inc. united states phone: +1-619-674-8100 fax: +1-619-674-8262 http://www.pulseeng.com transformers: sm tc-9001 sm st-9002 sm st-16311f s 0 -modules: sm tc-16311 sm tc-16311a sun myung korea phone: +82-348-943-8525 fax: +82-348-943-8527 http://www.sunmy ung.com transformers ut21023 s 0 -modules: ut 20795 (smd) ut 21624 ut 28624 a umec gmbh germany phone: +49 7131-7617-0 fax: +49 7131-7617-20 taiwan phone: +886-4-359-009-6 fax: +886-4-359-012-9 united states phone: +1-310-326-707-2 fax: +1-310-326-705-8 http://www.umec.de
863c @39 1 :q^eqbi " ! %) _v (# cologne chip s/t module part number manufacturer t 6040... transformers: 3-l4021-x066 3-l4025-x095 3-l5024-x028 3-l4096-x005 3-l5032-x040 s 0 -modules: 7-l5026-x010 (smd) 7-l5051-x014 7-m5051-x032 7-l5052-x102 (smd) 7-m5052-x110 7-m5052-x114 vac gmbh germany phone: +49 6181/ 38-0 fax: +49 6181/ 38-2645 http://www.vacuumschmelze.de transformers: st5069 s 0 -modules: pt5135 st5201 st5202 valor electronics, inc. asia phone: +852 2333-0127 fax: +852 2363-6206 north america phone: +1 800 31valor fax: +1 619 537-2525 europe phone: +44 1727-824-875 fax: +44 1727-824-898 http://www.valorinc.com 543 76 009 00 503 740 010 0 (smd) vogt electronic ag germany phone: +49 8591/ 17-0 fax: +49 8591/ 17-240 http://www.vogt-electronic.com table 5: s/t module part numbers and manufacturer
863c @39 1 & _v (# :q^eqbi " ! cologne chip 7.3 oscillator circuitry part list: q1 12.288 mhz quartz r1 0..50 : r2 1 m : c1, c2 47 pf the values of c1, c2 and r1 depend on the used quartz. for a load-free check of the oscillator frequency the c4o clock of the gci/iom2 bus should be measured (hfc-s pci a as master, s/t interface deactivated, 4.096 mhz frequency intented on the c4io). 7.4 eeprom circuitry osc_out c2 r1 osc_in c1 q1 r2 figure 12: oscillator circuitry figure 13: eeprom circuitry
863c @39 1 :q^eqbi " ! &! _v (# cologne chip 7.5 pme pin circuitry the pme pin (pin 53) on the hfc-s pci a is high active. to connect it to the low active pme# pin on the pci bus, the following circuitry is neccessary. figure 14: pme pin circuitry
863c @39 1 &" _v (# :q^eqbi " ! cologne chip 8 state matrices for nt and te 8.1 s/t interface activation/deactivation layer 1 for finite state matrix for nt state name reset deactive pending activation active pending deactivation state number g0 g1 g2 g3 g4 event i nfo 0 i nfo 0 i nfo 2 i nfo 4 i nfo 0 state machine release (note 3) g2|||| activate request g2 (note 1) g2 (note 1) || g2 (note 1) deactivate request ? | start timer t2 g4 start timer t2 g4 | expiry t2 (note 2) ???? g1 receiving info 0 ??? g2 g1 receiving info 1 ? g2 (note 1) ? / ? receiving info 3 ? / g3 (note 1) ?? info sent table 6: activation/deactivation layer 1 for finite state matrix for nt ? no state change / impossible by the definition of peer-to-peer physical layer procedures or system internal reasons | impossible by the definition of the physical layer service note 1: timer 1 (t1) is not implemented in the hfc-s pci a and must be implemented in software. note 2: timer 2 (t2) prevents unintentional reactivation. its value is 32ms (256 x 125s). this implies that a te has to recognize info 0 and to react on it within this time. note 3: after reset the state machine is fixed to g0. * hint! fix the nt state machine to state g3 when activated (by writing 13h into states register). this prevents deactivation of nt mode s/t interface due to sporadically errors on nt input data.
863c @39 1 :q^eqbi " ! &# _v (# cologne chip 8.2 activation/deactivation layer 1 for finite state matrix for te ? no change, no action | impossible by the definition of the layer 1 service / impossible situation notes note 1: after reset the state machine is fixed to f0. note 2: this event reflects the case where a signal is received and the te has not (yet) determined wether it is info 2 or info 4. note 3: bit- and frame-synchronisation achieved. note 4: loss of bit- or frame-synchronisation. note 5: timer 3 (t3) is not implemented in the hfc-s pci a and must be implemented in software. state name reset sensing deactivated awaiting signal identifying input synchronized activated lost framing state number f0 f2 f3 f4 f5 f6 f7 f8 event info 0 info 0 info 0 info 1 info 0 info 3 info 3 info 0 state machine release (note 1) f2 / / / / / / / activate ? |f5 | | ? | ? request ? |f4 | | ? | ? expiry t3 (note 5) ? / ? f3 f3 f3 ?? receiving info 0 ? f3 ??? f3 f3 f3 receiving any signal (note 2) ?? ? f5 ? // ? receiving info 2 (note 3) ? f6 f6 f6 f6 ? f6 f6 receiving info 4 (note 3) ? f7 f7 f7 f7 f7 ? f7 lost framing (note 4) ? / / / / f8 f8 ? info sent receiving any signal receiving info 0 table 7: activation/deactivation layer 1 for finite state matrix for te
863c @39 1 &$ _v (# :q^eqbi " ! cologne chip 9 binary organisation of the frames 9.1 s/t frame structure the frame structures are different for each direction of transmission. both structures are illustrated in figure 15. f framing bit n bit set to a binary value n = f a (nt to te) l d.c. balancing bit b1 bit within b-channel 1 d d-channel bit b2 bit within b-channel 2 e d-echo-channel bit a bit used for activation f a auxiliary framing bit s s-channel bit m multiframing bit * note! lines demarcate those parts of the frame that are independently d.c.-balanced. the f a bit in the direction te to nt is used as q bit in every fifth frame if s/q bit transmission is enabled (see sctrl register). the nominal 2-bit offset is as seen from the te. the offset can be adjusted with the clkdel register in te mode. the corresponding offset at the nt may be greater due to delay in the interface cable and varies by configuration. hdlc-b-channel data start with the lsb, pcm-b-channel data start with the msb. figure 15: frame structure at reference point s and t
863c @39 1 :q^eqbi " ! &% _v (# cologne chip 9.2 gci frame structure the binary organistation of a single gci channel frame is described below. c4io clock frequency is 4.096mhz. b7 b7 b7 b6 b6 b6 b5 b5 b5 b4 b4 b4 b3 b3 b3 b2 b1 b2 b2 b1 din f0io c4io dout b2 m tim e slot 2 dc/i tim e slot 3 m r m x b1 b1 b1 b1 b0 b0 b0 b1 b2 b4 b3 b2 b1 tim e slot 0 gci frame tim e slot 1 time slot 4 time slot 32 figure 16: single channel gci format b1 b-channel 1 data b2 b-channel 2 data m monitor channel data d d-channel data c/i command/indication bits for controlling activation/deactivation and for additional control functions mr handshake bit for monitor channel mx handshake bit for monitor channel
863c @39 1 && _v (# :q^eqbi " ! cologne chip 10 clock synchronisation 10.1 clock synchronisation in nt-mode figure 17: clock synchronisation in nt-mode
863c @39 1 :q^eqbi " ! &' _v (# cologne chip 10.2 clock synchronisation in te-mode the c4io clock is adjusted in the 31th time slot at the gci/iom bus twice for one half clock cycle. this can be reduced to one adjustment of a half clock cycle. this is useful if another hfc-s, hfc-s+, hfc- sp or hfc-s pci a is connected as slave in nt mode to the gci/iom2 bus. figure 18: clock synchronisation in te-mode
863c @39 1 &( _v (# :q^eqbi " ! cologne chip 11 hfc-s pci a package dimensions figure 19: hfc-s pci a package dimensions
863c @39 1 :q^eqbi " ! &) _v (# cologne chip 12 isdn pci card sample circuitries with hfc-s pci a 12.1 isdn pci card for 5v power supply (no d3 cold support) please see chapter 3.3 for details on power management support of hfc-s pci a and special considerations for support of power management state d3 cold . /ad r_w r a7 ad04 r3 lev_r2 pci_st1b pciint b8 a7 b7 a6 a19 intd# intc# intb# inta# pme# c3 q3 3.3vaux a3 c5 nc a5 optional ad18 nc vi/o rst# r1 ad23 a4 tx2_hi a6 49/52/61/64/77/83/90/96 gnd /tx2_lo c15 jp2 perr# c10 24c04 ad09 c9 vdd_hfc daux5 f0io r5 ad12 /au x_r d gnd gnd ad17 ad00 vdd_hfc c/be2# c4io vi/o trdy# daux5 p76/77 stio2 a0 gnt# daux1 gnd gnd c/be0# /a u x _ r d stop# c7 all gnd pins 8/17/29/39 tx1_hi pa r daux6 f1_a 10 /tx_en daux2 jp11 a1 c14 r12 c6 r1 nc ad11 p28/29 /tx1_lo optional jp1 daux1 /au x_w r + c1 ad27 ad05 pci_st1a pciadr b20 a20 b21 a22 b23 a23 b24 a25 b27 a28 b29 a29 b30 a31 b32 a32 a44 b45 a46 b47 a47 b48 a49 b52 b53 a54 b55 a55 b56 a57 b58 a58 b26 b33 b44 a52 a43 ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad09 ad08 ad07 ad06 ad05 ad04 ad03 ad02 ad01 ad0 c/be3# c/be2# c/be1# c/be0# pa r c4io ad21 f1_b ad29 pci_st1c pcispec b9 b11 a1 a3 b2 a4 b4 a40 a41 a15 b16 a17 b18 b42 b40 b39 a26 b37 a38 b35 a36 a34 b49 prsnt1# prsnt2# trst# tms tck tdi tdo sdone sbo# rst# clk gnt# req# serr# perr# lock# idsel devsel# stop# irdy# trdy# frame# m66en ad26 p7/8 +5v jp1 pcm 1 3 5 7 2 4 6 8 daux7 gnd req# jp10 stio [1:2],c 4io,f0io,f1_a,f1_b jp2 jp2 io 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 devsel# ad06 a7 a6 a5 2.0 isdn pci card for 5 v without d3cold support (c) 2000 by cologne chip ag a4 12 thursday, october 19, 2000 title size document number rev date: sheet of ad28 c11 74hc74 +5v f0io gnd vdd_hfc a3 serr# c8 optional /adr_wr daux0 p60/61 /au x _w r daux3 4 irdy# c30 ad15 f1_b stio2 daux3 ad31 ad01 c29 gnd ad07 + c16 daux0 vdd_hfc ad20 7/28/48/60/76/89 daux2 ad19 ad30 gnd a4 daux1 c12 vdd _ hfc gnd a1 ad03 pci_st1d pcipow +12v -12v +5v +3.3v 3.3vaux vi/o gnd pme_s a[0:7] clk daux2 q1 c/be1# u2 hfc-s pci a 97 98 99 100 1 2 3 4 9 10 11 12 13 14 15 16 30 31 32 33 34 35 36 37 40 41 42 43 44 45 46 47 38 27 18 5 26 19 21 20 23 22 6 24 25 95 94 93 92 91 68 69 70 71 72 73 75 74 65 66 67 63 62 57 56 54 55 58 59 88 87 86 85 84 78 80 79 82 81 50 51 53 8 89 ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 c/be0# c/be1# c/be2# c/be3# par frame# trdy# irdy# stop# devsel# idsel perr# serr# req# gnt# clk rst# inta# daux7 daux6 daux5 daux4 daux3 daux2 daux0 daux1 /adr_wr /aux_rd /a u x _w r ee__sda ee_scl/en stio2 stio1 c4io f0io f1_a f1_b tx2_hi /tx1_lo /tx_en /tx2_lo tx1_hi adj_lev lev_r1 r1 r2 lev_r2 osc_out osc_in pme gnd vdd_hfc c4 gnd vdd_hfc ad14 daux0 +5v c/be3# r11 stio1 daux4 a2 daux3 r6 74hc374 inta daux6 ad13 f1_a q2 all vdd_hfc pins vdd_hfc a0 24c04 a2 daux7 daux5 +5v lev_r1 ad10 u4 24c04 3 2 1 5 6 7 8 a2 a1 a0 sda scl test vcc frame# gnd ad02 ad16 ad25 ad24 r2 pme_s p89/90 c2 id se l /adr_wr stio1 daux7 gnd adj_lev daux4 daux6 ad22 ad08 en 1d c1 vcc u3 74hc374 20 1 11 3 4 7 8 13 14 17 18 19 16 15 12 9 6 5 2 p48/49 vi/o gnd gnd vi/o d au x [0:7],/au x_w r ,/au x_r d ,/ad r _w r gnd daux4 74hc374
863c @39 1 ' _v (# :q^eqbi " ! cologne chip gnd re2 2.0 is dn p ci c ard for 5 v w ithou t d 3cold s up po rt (c) 2 00 0 b y c olog ne c h ip a g a4 22 thursday, october 19, 2000 title size document number rev date: sheet of r18 d6 q10 ra1 tr1b trans r15 /tx2_lo gnd gnd tx2_hi gnd rf1 c24 rb1 q7 adj_lev r13 d8 rd1 gnd gnd q9 r19 lev_r2 ra2 d7 r17 r22 c18 c26 d4 gnd rf2 gnd vdd_hfc vdd_hfc lev_r1 gnd c22 + c19 r14 rd2 re1 q6 r2 rg1 tr1a rec c21 tx1_hi d3 gnd /tx1_lo /tx_en rc1 q8 +5v rg2 isdn_st1 rec1 rec2 trans1 trans2 r16 c20 rb2 r1 c23 c25 rc2
863c @39 1 :q^eqbi " ! '! _v (# cologne chip isdn pci card for 5 v without d3cold support capacitors resistors ic's c01 33 r01 10k u2 hfc-s pci a cologne chip ag c02 33n nearby u2 r03 1m u3 74hc374 optional c03 33n nearby u2 r05 330 u4 24c04 c04 33n nearby u2 r06 10k c05 33n nearby u2 r11 10k connectors c06 33n nearby u2 r12 10k c07 33n nearby u2 r13 3k9 jp1 pcm optional c08 33n nearby jp1 optiona l r14 680k jp2 io optional c09 33n nearby jp2 optional r15 1m2 jp10 eeprom options optional c10 33n nearby u1 r16 3k3 jp11 eeprom options optional c11 33n nearby u4 r17 100 c12 33n nearby u3 optional r18 5k6 c14 47p depends on crystal r19 3k3 transistors / crystals c15 47p depends on crystal r22 2k2 c16 33 ra1 100k q1 bc850c cmpt5088 or similar c18 22p nearby u2 ra2 100k q2 12.288m c19 33 rb1 33k q3 bc860c cmpt5087 or similar c20 22p nearby u2 rb2 33k q6 bc860c cmpt5087 or similar c21 0 optional rc1 4k7 q7 bc850c cmpt5088 or similar c22 0 optional rc2 4k7 q8 bc850c cmpt5088 or similar c23 47n rd1 4k7 q9 bc850c cmpt5088 or similar c24 470p rd2 4k7 q10 bc850c cmpt5088 or similar c25 0 optional re1 2k2 1% c26 0 optional re2 2k2 1% diodes c29 33n nearby jp2 optional rf1 15 c30 33n nearby jp2 optional rf2 15 d3 bav99 can also be 2*4148 c31 0r r esistor or connect to gnd rg1 3k 1% d4 bav99 can also be 2*4148 c32 0 optional rg2 3k 1% d6 bav99 can also be 2*4148 d7 2v7 d8 bav99 can also be 2*4148
863c @39 1 '" _v (# :q^eqbi " ! cologne chip 12.2 isdn pci card for 5v power supply with d3 cold support please see chapter 3.3 for details on power management support of hfc-s pci a and special considerations for support of power management state d3 cold . ad09 daux3 f1_b q2 gnd c/be0# d9 ad26 c4io vdd_hfc vi/o lev_r2 s t io [1:2 ],c 4io ,f 0io ,f1_ a ,f1_ b pci_st1d pcipow +12v -12v +5v +3.3v 3.3vaux vi/o gnd +5v ad11 stio2 24c04 c/be2# daux3 jp1 daux4 + c16 optional s r c1 1d vcc u1a 74hc74 14 4 3 2 1 6 5 gnd a[0:7] /a u x _r d vdd_hfc ad12 ad05 ad30 c2 r_sens optional gnd vdd_hfc rst_p r3 a6 c29 vi/o daux6 optional all vdd_hfc pins gnd gnd /adr_wr f1_b /a u x _ w r clk c30 c8 49/52/61/64/77/83/90/96 r_sens daux5 r4 +5v a3 a0 4 ad29 c17 gnd ad15 c6 nc vdd_hfc a0 jp2 io 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 /ad r_w r daux7 ad19 daux4 idse l stop# c7 stio1 p28/29 daux2 jp11 a1 ad07 gnd vdd_hfc f0io vi/o daux5 d2 p7/8 gnd tx2_hi a3 ad00 en 1d c1 vcc u3 74hc374 20 1 11 3 4 7 8 13 14 17 18 19 16 15 12 9 6 5 2 ad16 daux6 daux0 jp5 c15 c14 74hc74 vi/o r1 vdd_hf c gnd /au x_w r daux1 jp10 p89/90 vdd_hfc a4 daux0 ad13 pci_st1a pciadr b20 a20 b21 a22 b23 a23 b24 a25 b27 a28 b29 a29 b30 a31 b32 a32 a44 b45 a46 b47 a47 b48 a49 b52 b53 a54 b55 a55 b56 a57 b58 a58 b26 b33 b44 a52 a43 ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad09 ad08 ad07 ad06 ad05 ad04 ad03 ad02 ad01 ad0 c/be3# c/be2# c/be1# c/be0# par c4 req# f1_a rst_s daux5 7 trdy# + c1 pci_st1c pcispec b9 b11 a1 a3 b2 a4 b4 a40 a41 a15 b16 a17 b18 b42 b40 b39 a26 b37 a38 b35 a36 a34 b49 prsnt1# prsnt2# trst# tms tck tdi tdo sdone sbo# rst# clk gnt# req# serr# perr# lock# idsel devsel# stop# irdy# trdy# frame# m66en /a u x _ r d gnd gnd tx1_hi gnd vdd_hfc daux0 p60/61 jp2 rst_s c4io ad21 7/28/48/60/76/89 r11 power management ad02 ird y# p76/77 lev_r1 a4 r2 3.3vaux daux1 nc c/be3# q1 ad17 d au x[0:7],/a ux _w r,/a u x_r d,/adr _w r ad20 c5 gnd gnd 74hc374 q5 /t x1_lo daux3 ad03 f1_a daux7 c/be1# jp1 pcm 1 3 5 7 2 4 6 8 a5 ad10 p48/49 gnd a7 gnd ad01 /t x2_lo daux1 jp4 a7 r12 optional 10 vdd_hfc stio1 ad04 r6 f0io a2 gnt# perr# ad31 daux0 c9 serr# r2 daux7 ad24 a2 daux2 c10 gnd a1 a6 ad08 + c13 r5 q3 74hc74 gnd gnd r10 r1 nc frame# ad28 ad06 all gnd pins 8/17/29/39 r9 24c04 stio2 ad23 r30 ad27 pci_st1b pciint b8 a7 b7 a6 a19 intd# intc# in tb # in ta# pme# s r c1 1d vcc u1b 74hc74 14 10 11 12 13 8 9 vdd_hfc in ta /ad r_w r ad22 gnd a5 /a u x _w r daux2 d1 +5v jp3 3.3vaux daux4 c12 q4 pme_s par ad14 devsel# 2.0 isdn pci card for 5 v with d3cold support (c) 2000 by cologne chip ag a4 12 thursday, october 19, 2000 title size document number rev date: sheet of jp2 daux6 ad18 u2 hfc-s pci a 97 98 99 100 1 2 3 4 9 10 11 12 13 14 15 16 30 31 32 33 34 35 36 37 40 41 42 43 44 45 46 47 38 27 18 5 26 19 21 20 23 22 6 24 25 95 94 93 92 91 68 69 70 71 72 73 75 74 65 66 67 63 62 57 56 54 55 58 59 88 87 86 85 84 78 80 79 82 81 50 51 53 8 89 ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 c/be0# c/be1# c/be2# c/be3# par frame# trdy# irdy# stop# devsel# idsel perr# serr# req# gnt# clk rst# inta# daux7 daux6 daux5 daux4 daux3 daux2 daux0 daux1 /adr_wr /aux_rd /aux_w r ee__sda ee_scl/en stio2 stio1 c4io f0io f1_a f1_b tx2_hi /tx1_lo /tx_en /tx2_lo tx1_hi adj_lev lev_r1 r1 r2 lev_r2 osc_out osc_in pme gnd vdd_hfc +5v rst_p c3 u4 24c04 3 2 1 5 6 7 8 a2 a1 a0 sda scl test vcc gnd /tx_en adj_lev pme_s 74hc374 ad25 c11 the r_sens part is optional. it is used to decrease the receiver sensitivity for wake-up signals to avoid a wake-up caused by disturbance on the isdn line.
863c @39 1 :q^eqbi " ! '# _v (# cologne chip r1 gnd ra1 c21 r_sens gnd r13 vdd_hfc /tx1_lo r15 c24 re1 q7 r14 tr1b trans vdd_hfc q9 rg1 +5v ra2 rc2 d3 gnd rb2 c23 q10 r17 r16 gnd d8 rf2 re2 tx1_hi r18 rd1 d6 r2 rd2 c25 gnd rf1 lev_r2 rc1 rg2 d4 2.0 isdn pci card for 5 v with d3cold support (c) 2000 by cologne chip ag a4 22 thursday, october 19, 2000 title size document number rev date: sheet of c18 d7 gnd lev_r1 q8 gnd gnd tr1a rec is dn _s t1 rec1 rec2 trans1 trans2 tx2_hi c26 rb1 c20 q6 r19 /t x2_lo r22 c22 adj_lev /tx_en gnd gnd + c19
863c @39 1 '$ _v (# :q^eqbi " ! cologne chip isdn pci card for 5 v with d3cold support capacitors resistors ic's c01 33 r01 10k u1 74hc74 c02 33n nearby u2 r02 1m u2 hfc-s pci a cologne chip ag c03 33n nearby u2 r03 1m u3 74hc374 optional c04 33n nearby u2 r04 10k u4 24c04 c05 33n nearby u2 r05 330 c06 33n nearby u2 r06 10k c07 33n nearby u2 r09 10k c08 33n nearby jp1 optiona l r10 10k c09 33n nearby jp2 optional r11 10k connectors c10 33n nearby u1 r12 10k c11 33n nearby u4 r13 3k9 jp1 pcm optional c12 33n nearby u3 optional r14 680k jp2 io optional c13 1 r15 1m2 jp3 reset options c14 47p depends on crystal r16 3k3 jp4 power options c15 47p depends on crystal r17 100 jp5 power options c16 33 r18 5k6 jp10 eeprom options optional c17 33n r19 3k3 jp11 eeprom options optional c18 22p nearby u2 r22 2k2 c19 33 r30 680k * c20 22p nearby u2 ra1 100k c21 0 optional ra2 100k transistors / crystals c22 0 optional rb1 33k c23 47n rb2 33k q1 bc850c cmpt5088 or similar c24 470p rc1 4k7 q2 12.288m c25 0 optional rc2 4k7 q3 bc860c cmpt5087 or similar c26 0 optional rd1 4k7 q4 bc860c cmpt5087 or similar c29 33n nearby jp2 optional rd2 4k7 q5 bc860c cmpt5087 or similar c30 33n nearby jp2 optional re1 2k2 1% q6 bc860c cmpt5087 or similar c31 0r resistor or connect to gnd re2 2k2 1% q7 bc850c cmpt5088 or similar c32 0 optional rf1 15 q8 bc850c cmpt5088 or similar rf2 15 q9 bc850c cmpt5088 or similar rg1 3k 1% q10 bc850c cmpt5088 or similar rg2 3k 1% diodes d1 ll4148 or similar d2 ll4148 or similar d3 bav99 can also be 2*4148 d4 bav99 can also be 2*4148 d6 bav99 can also be 2*4148 d7 2v7 d8 bav99 can also be 2*4148 d9 ll4148 * or similar * optional, not on pcb layout v 2.0
863c @39 1 :q^eqbi " ! '% _v (# cologne chip 12.3 isdn pci card for 3.3v power supply (no d3 cold support) please see chapter 3.3 for details on power management support of hfc-s pci a and special considerations for support of power management state d3 cold . ad30 ad18 ad04 ad22 ad21 nc inta a4 7/28/48/60/76/89 r2 /adr_wr stio1 daux7 ad14 p76/77 r1 /tx1_lo c12 /tx_en ad23 c/be2# /aux_w r c30 par vi/o gnd daux0 q1 stio[1:2],c4io,f0io,f1_a,f1_b jp2 vdd_hfc gnd gnd tx1_hi q2 jp2 r1 ad09 /aux _w r jp1 pcm 1 3 5 7 2 4 6 8 a5 jp2 io 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 nc m66en daux1 ad17 a7 en 1d c1 vcc u3 74hc374 20 1 11 3 4 7 8 13 14 17 18 19 16 15 12 9 6 5 2 vdd_hfc gnd gnd gnt# c6 daux6 pci_st1c pcispec b9 b11 a1 a3 b2 a4 b4 a40 a41 a15 b16 a17 b18 b42 b40 b39 a26 b37 a38 b35 a36 a34 b49 prsnt1# prsnt2# trst# tms tck tdi tdo sdone sbo# rst# clk gnt# req# serr# perr# lock# idsel devsel# stop# ir dy# trdy# frame# m66en p89/90 pme_s optional vdd_hfc stio2 f1_b /aux_rd daux0 c11 r12 c4 daux4 daux4 c8 /tx2_lo rst# daux1 daux[0:7],/aux_w r,/aux_rd,/adr_w r 74hc74 gnd c2 gnd lev_r2 c7 daux5 frame# daux2 stio2 gnd stop# c4io req# all vdd_hfc pins ad20 2.0 isdn pci card for 3.3 v without d3cold support (c) 2000 by cologne chip ag a4 12 thursda y , october 19, 2000 title size document number rev date: sheet of +5v optional r6 jp12 gnd ad16 pci_st1d pcipow +12v -12v +5v +3.3v 3.3vaux vi/o gnd f1_a c5 +5v jp11 ad31 10 f0io irdy# ad00 ad08 c/be1# jp10 vi/o ad01 24c04 vi/o m66en ad15 a[0:7] r5 a3 a1 ad13 adj_lev daux1 a7 daux6 ad10 c14 daux3 /adr_wr u4 24c04 3 2 1 5 6 7 8 a2 a1 a0 sda scl test vcc a5 ad12 trdy# ad07 vdd_hfc pme_s ad25 tx2_hi + c1 optional a0 c/be3# daux7 daux0 daux5 devsel# ad03 p7/8 daux3 pci_st1a pciadr b20 a20 b21 a22 b23 a23 b24 a25 b27 a28 b29 a29 b30 a31 b32 a32 a44 b45 a46 b47 a47 b48 a49 b52 b53 a54 b55 a55 b56 a57 b58 a58 b26 b33 b44 a52 a43 ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad09 ad08 ad07 ad06 ad05 ad04 ad03 ad02 ad01 ad0 c/be3# c/be2# c/be1# c/be0# pa r pci_st1b pciint b8 a7 b7 a6 a19 in td# in tc# in tb# in ta # pme# gnd vdd_hfc c9 serr# 74hc374 a6 daux4 r3 a4 jp1 ad11 + c16 idsel c4io f1_a ad06 +5v /aux_rd daux6 a1 ad27 r11 f1_b c31 gnd a0 gnd /adr_wr vdd_hfc a2 ad02 f0io vi/o stio1 perr# 74hc374 ad28 q3 3.3vaux daux7 u2 hfc-s pci a 97 98 99 100 1 2 3 4 9 10 11 12 13 14 15 16 30 31 32 33 34 35 36 37 40 41 42 43 44 45 46 47 38 27 18 5 26 19 21 20 23 22 6 24 25 95 94 93 92 91 68 69 70 71 72 73 75 74 65 66 67 63 62 57 56 54 55 58 59 88 87 86 85 84 78 80 79 82 81 50 51 53 8 89 ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 c/be0# c/be1# c/be2# c/be3# pa r frame# trdy# ird y# stop# devsel# ids el perr# serr# req# gnt# clk rst# inta# daux7 daux6 daux5 daux4 daux3 daux2 daux0 daux1 /ad r_w r /au x_rd /au x_w r ee__sda ee_scl/en stio2 stio1 c4io f0io f1_a f1_b tx2_hi /tx1_lo /tx_en /tx2_lo tx1_hi adj_lev lev_r1 r1 r2 lev_r2 osc_out osc_in pme gnd vdd_hfc p60/61 daux5 daux2 c10 4 a3 c3 p48/49 clk ad26 daux3 gnd gnd vdd_hfc +5v lev_r1 ad05 nc ad29 c15 ad19 gnd gnd c/be0# all gnd pins 8/17/29/39 ad24 daux2 c29 49/52/61/64/77/83/90/96 a2 a6 p28/29 24c04
863c @39 1 '& _v (# :q^eqbi " ! cologne chip 2.0 isdn pci card for 3.3 v without d3cold support (c) 2000 by cologne chip ag a4 22 thursday, october 19, 2000 title size document number rev date: sheet of gnd c24 rc1 c18 r18 /tx1_lo r17 q7 /tx2_lo tx1_hi c25 lev_r1 q9 vdd_hfc d4 rf2 c23 q8 d8 r2 tr1b trans c21 rd2 rb2 r15 lev_r2 q6 vdd_hfc adj_lev tr1a rec gnd re1 r19 d3 r16 r1 rf1 gnd d6 c20 gnd gnd ra2 rg1 +5v gnd q10 gnd rg2 ra1 c22 r14 isdn_st1 rec1 rec2 trans1 trans2 gnd + c19 tx2_hi re2 r22 rb1 rc2 c26 r13 d7 /t x_e n rd1 gnd gnd
863c @39 1 :q^eqbi " ! '' _v (# cologne chip isdn pci card for 3.3 v without d3cold support capacitors resistors ic's c01 33 r01 10k u2 hfc-s pci a cologne chip ag c02 33n nearby u2 r03 1m u3 74hc374 optional c03 33n nearby u2 r05 330 u4 24c04 c04 33n nearby u2 r06 10k c05 33n nearby u2 r11 10k connectors c06 33n nearby u2 r12 10k c07 33n nearby u2 r13 3k9 jp1 pcm optional c08 33n nearby jp1 optiona l r14 680k jp2 io optional c09 33n nearby jp2 optional r15 1m2 jp10 eeprom options optional c10 33n nearby u1 r16 3k3 jp11 eeprom options optional c11 33n nearby u4 r17 100 jp12 33/66 mhz optional c12 33n nearby u3 optional r18 5k6 c14 47p depends on crystal r19 3k3 transistors / crystals c15 47p depends on crystal r22 2k2 c16 33 ra1 100k q1 bc850c cmpt5088 or similar c18 22p nearby u2 ra2 100k q2 12.288m c19 33 rb1 33k q3 bc860c cmpt5087 or similar c20 22p nearby u2 rb2 33k q6 bc860c cmpt5087 or similar c21 0 optional rc1 4k7 q7 bc850c cmpt5088 or similar c22 0 optional rc2 4k7 q8 bc850c cmpt5088 or similar c23 47n rd1 4k7 q9 bc850c cmpt5088 or similar c24 470p rd2 4k7 q10 bc850c cmpt5088 or similar c25 0 optional re1 430 1% c26 0 optional re2 430 1% diodes c29 33n nearby jp2 optional rf1 15 c30 33n nearby jp2 optional rf2 15 d3 bav99 can also be 2*4148 c31 10n optional rg1 3k9 1% d4 bav99 can also be 2*4148 rg2 3k9 1% d6 bav99 can also be 2*4148 d7 2v7 d8 bav99 can also be 2*4148
863c @39 1 '( _v (# :q^eqbi " ! cologne chip 12.4 isdn pci card for 3.3v power supply with d3 cold support please see chapter 3.3 for details on power management support of hfc-s pci a and special considerations for support of power management state d3 cold . p89/90 pci_st1b pciint b8 a7 b7 a6 a19 intd# intc# in tb # in ta# pme# r10 vdd_hfc gnd a5 ad26 devsel# r3 r1 jp4 lev_r1 r30 gnd gnd par ad28 perr# daux3 ad07 req# jp2 /ad r_w r daux7 c12 ad08 daux4 nc /a u x _r d frame# ird y# vdd_hfc c/be3# /a u x _ r d r2 ad15 24c04 jp5 49/52/61/64/77/83/90/96 daux0 daux0 f1_b daux5 c9 d2 ad11 pme_s /adr_wr c31 vdd_hfc gnd gnd daux2 r2 gnd a1 daux2 daux5 r6 optional p48/49 jp2 + c13 gnd gnd c17 +5v a2 /a u x _w r ad13 stio2 ad01 rst_s ad31 ad25 daux1 r9 ad17 a6 ad20 ad00 f1_b ad19 74hc74 ad06 jp2 io 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 ad24 jp3 a3 a1 f1_a c5 stio1 jp1 daux4 in ta a[0:7] a6 /ad r_w r 4 c8 74hc74 en 1d c1 vcc u3 74hc374 20 1 11 3 4 7 8 13 14 17 18 19 16 15 12 9 6 5 2 +5v daux1 all vdd_hfc pins daux7 rst_p a5 f0io 7/28/48/60/76/89 /t x2_lo idse l vi/o stio2 daux0 daux0 ad03 pci_st1d pcipow +12v -12v +5v +3.3v 3.3vaux vi/o gnd r5 c6 24c04 c30 jp11 vdd_hfc a3 daux2 ad10 daux5 jp1 pcm 1 3 5 7 2 4 6 8 jp12 s r c1 1d vcc u1a 74hc74 14 4 3 2 1 6 5 vi/o m66en 2.0 isdn pci card for 3.3 v with d3cold support (c) 2000 by cologne chip ag a4 12 thursday, october 19, 2000 title size document number rev date: sheet of gnd vdd_hfc /tx_en gnt# daux6 c29 serr# ad29 daux6 u2 hfc-s pci a 97 98 99 100 1 2 3 4 9 10 11 12 13 14 15 16 30 31 32 33 34 35 36 37 40 41 42 43 44 45 46 47 38 27 18 5 26 19 21 20 23 22 6 24 25 95 94 93 92 91 68 69 70 71 72 73 75 74 65 66 67 63 62 57 56 54 55 58 59 88 87 86 85 84 78 80 79 82 81 50 51 53 8 89 ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 c/be0# c/be1# c/be2# c/be3# par frame# trdy# irdy# stop# devsel# idsel perr# serr# req# gnt# clk rst# inta# daux7 daux6 daux5 daux4 daux3 daux2 daux0 daux1 /adr_wr /aux_rd /aux_w r ee__sda ee_scl/en stio2 stio1 c4io f0io f1_a f1_b tx2_hi /tx1_lo /tx_en /tx2_lo tx1_hi adj_lev lev_r1 r1 r2 lev_r2 osc_out osc_in pme gnd vdd_hfc ad02 optional gnd vi/o d au x[0:7],/a ux _w r,/a u x_r d,/adr _w r f1_a adj_lev 10 gnd gnd c/be0# ad04 daux6 r12 pci_st1c pcispec b9 b11 a1 a3 b2 a4 b4 a40 a41 a15 b16 a17 b18 b42 b40 b39 a26 b37 a38 b35 a36 a34 b49 prsnt1# prsnt2# trst# tms tck tdi tdo sdone sbo# rst# clk gnt# req# serr# perr# lock# idsel devsel# stop# irdy# trdy# frame# m66en a7 c3 c14 all gnd pins 8/17/29/39 ad16 c15 r4 gnd c/be2# r11 /a u x _ w r u4 24c04 3 2 1 5 6 7 8 a2 a1 a0 sda scl test vcc vdd_hfc tx2_hi ad18 c7 a0 gnd /t x1_lo ad09 p28/29 r_sens ad30 stop# q2 rst_s ad22 74hc374 + c16 daux3 d1 ad12 c4io c2 q3 +5v vdd_hfc ad14 pme_s ad23 ad21 r_sens (optional) a7 /au x_w r trdy# q5 optional m66en ad27 vi/o lev_r2 3.3vaux vdd_hfc tx1_hi nc a2 gnd daux3 + c1 q4 p7/8 a0 power management +5v a4 ad05 pci_st1a pciadr b20 a20 b21 a22 b23 a23 b24 a25 b27 a28 b29 a29 b30 a31 b32 a32 a44 b45 a46 b47 a47 b48 a49 b52 b53 a54 b55 a55 b56 a57 b58 a58 b26 b33 b44 a52 a43 ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad09 ad08 ad07 ad06 ad05 ad04 ad03 ad02 ad01 ad0 c/be3# c/be2# c/be1# c/be0# par vdd_hfc daux7 c11 d9 gnd f0io 7 stio1 jp10 74hc374 vdd_hfc nc 3.3vaux q1 p60/61 gnd gnd gnd gnd rst_p clk s t io [1:2 ],c 4io ,f 0io ,f1_ a ,f1_ b daux4 c/be1# c4 gnd c10 r1 a4 c4io daux1 s r c1 1d vcc u1b 74hc74 14 10 11 12 13 8 9 p76/77 the r_sens part is optional. it is used to decrease the receiver sensitivity for wake-up signals to avoid a wake-up caused by disturbance on the isdn line.
863c @39 1 :q^eqbi " ! ') _v (# cologne chip tx2_hi gnd tx1_hi r19 ra1 /tx_e n r_sens rb2 c22 gnd rd1 vdd_hfc r16 /tx1_lo tr1a rec rf1 r13 d7 gnd rg1 rf2 vdd_hf c gnd c24 rc1 gnd gnd d3 c26 q10 c20 rc2 gnd /tx2_lo isd n_st1 rec1 rec2 trans1 trans2 gnd gnd lev_r2 ra2 r2 r17 +5v c21 rd2 q9 d8 q8 re1 r22 r1 r14 d6 re2 r15 rg2 c25 2.0 is dn pc i card for 3.3 v with d3cold s upport (c) 2000 by cologne chip ag a4 22 thursday, october 19, 2000 title size document number rev date: sheet of q7 r18 adj_lev q6 tr1b trans lev_r1 rb1 c18 c23 gnd + c19 d4
863c @39 1 ( _v (# :q^eqbi " ! cologne chip isdn pci card for 3.3 v with d3cold support capacitors resistors ic's c01 33 r01 10k u1 74hc74 c02 33n nearby u2 r02 1m u2 hfc-s pci a cologne chip ag c03 33n nearby u2 r03 1m u3 74hc374 optional c04 33n nearby u2 r04 10k u4 24c04 c05 33n nearby u2 r05 330 c06 33n nearby u2 r06 10k c07 33n nearby u2 r09 10k c08 33n nearby jp1 optiona l r10 10k c09 33n nearby jp2 optional r11 10k connectors c10 33n nearby u1 r12 10k c11 33n nearby u4 r13 3k9 jp1 pcm optional c12 33n nearby u3 optional r14 680k jp2 io optional c13 1 r15 1m2 jp3 reset options c14 47p depends on crystal r16 3k3 jp4 power options c15 47p depends on crystal r17 100 jp5 power options c16 33 r18 5k6 jp10 eeprom options optional c17 33n r19 3k3 jp11 eeprom options optional c18 22p nearby u2 r22 2k2 jp12 33/66 mhz optional c19 33 r30 680k * c20 22p nearby u2 ra1 100k c21 0 optional ra2 100k transistors / crystals c22 0 optional rb1 33k c23 47n rb2 33k q1 bc850c cmpt5088 or similar c24 470p rc1 4k7 q2 12.288m c25 0 optional rc2 4k7 q3 bc860c cmpt5087 or similar c26 0 optional rd1 4k7 q4 bc860c cmpt5087 or similar c29 33n nearby jp2 optional rd2 4k7 q5 bc860c cmpt5087 or similar c30 33n nearby jp2 optional re1 430 1% q6 bc860c cmpt5087 or similar c31 10n optional re2 430 1% q7 bc850c cmpt5088 or similar rf1 15 q8 bc850c cmpt5088 or similar rf2 15 q9 bc850c cmpt5088 or similar rg1 3k9 1% q10 bc850c cmpt5088 or similar rg2 3k9 1% diodes d1 ll4148 or similar d2 ll4148 or similar d3 bav99 can also be 2*4148 d4 bav99 can also be 2*4148 d6 bav99 can also be 2*4148 d7 2v7 d8 bav99 can also be 2*4148 d9 ll4148 * or similar * optional, not on pcb layout v 2.0
863c @39 1 :q^eqbi " ! (! _v (# cologne chip 12.5 isdn pci card for 3.3 and 5v power supply (auto detect) with d3 cold support please see chapter 3.3 for details on power management support of hfc-s pci a and special considerations for support of power management state d3 cold . p60/61 gnd +5v ad18 vdd_hfc rst_p a3 ad29 daux7 daux1 f1_b ad21 nc gnd ad06 s r c1 1d vcc u1a 74hc74 14 4 3 2 1 6 5 a0 + c1 d2 daux4 3.3vaux daux2 daux6 all vdd_hfc pins all gnd pins 8/17/29/39 gnd jp2 io 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 r10 gnd pci_st1b pciint b8 a7 b7 a6 a19 intd# intc# in tb # in ta# pme# c4 gnd a6 f1_a in ta c12 gnd daux5 ad04 ad28 vi/o 7/28/48/60/76/89 vdd_hfc a3 /ad r_w r ad12 stio2 daux1 vi/o c31 24c04 daux0 f1_a jp10 2.0 isdn pci card for 3.3/5 v or universal power with d3cold support a4 12 tuesday, october 17, 2000 title size document number rev date: sheet of vdd_hfc gnd daux3 daux2 /t x1_lo ad08 s r c1 1d vcc u1b 74hc74 14 10 11 12 13 8 9 d1 + c13 c14 +5v jp1 pcm 1 3 5 7 2 4 6 8 tx2_hi p7/8 p76/77 c6 r2 optional p28/29 vdd_hfc req# 3.3vaux lev_r2 c/be2# ad20 p48/49 ad13 gnd ad17 ad03 ad19 optional daux7 daux0 f1_b + c16 r6 vi/o c11 r_sens r_sens (optional) vi/o jp2 74hc74 gnd gnd gnd a7 clk r12 c7 trdy# r11 r3 r4 idse l a1 d au x[0:7],/a ux _w r,/a u x_r d,/adr _w r daux3 r30 jp1 gnd vdd_hfc ad30 daux6 r9 q4 ad09 ad27 f0io r1 r1 ad02 a7 gnd ad14 ad10 pci_st1d pcipow +12v -12v +5v +3.3v 3.3vaux vi/o gnd q2 daux1 ad16 jp3 adj_lev pme_s jp12 nc gnd gnd a2 c17 c2 rst_s /au x_w r daux4 daux7 c10 m66en jp4 pme_s u2 hfc-s pci a 97 98 99 100 1 2 3 4 9 10 11 12 13 14 15 16 30 31 32 33 34 35 36 37 40 41 42 43 44 45 46 47 38 27 18 5 26 19 21 20 23 22 6 24 25 95 94 93 92 91 68 69 70 71 72 73 75 74 65 66 67 63 62 57 56 54 55 58 59 88 87 86 85 84 78 80 79 82 81 50 51 53 8 89 ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 c/be0# c/be1# c/be2# c/be3# par frame# trdy# irdy# stop# devsel# idsel perr# serr# req# gnt# clk rst# inta# daux7 daux6 daux5 daux4 daux3 daux2 daux0 daux1 /adr_wr /aux_rd /aux_w r ee__sda ee_scl/en stio2 stio1 c4io f0io f1_a f1_b tx2_hi /tx1_lo /tx_en /tx2_lo tx1_hi adj_lev lev_r1 r1 r2 lev_r2 osc_out osc_in pme gnd vdd_hfc r5 r2 4 7 ad31 gnd vdd_hfc lev_r1 s t io [1:2 ],c 4io ,f 0io ,f1_ a ,f1_ b c4io pci_st1c pcispec b9 b11 a1 a3 b2 a4 b4 a40 a41 a15 b16 a17 b18 b42 b40 b39 a26 b37 a38 b35 a36 a34 b49 prsnt1# prsnt2# trst# tms tck tdi tdo sdone sbo# rst# clk gnt# req# serr# perr# lock# idsel devsel# stop# irdy# trdy# frame# m66en c/be3# stio1 optional daux5 a4 24c04 gnd ad22 ad05 vdd_hfc rst_s devsel# gnd par a4 c29 c30 jp2 en 1d c1 vcc u3 74hc374 20 1 11 3 4 7 8 13 14 17 18 19 16 15 12 9 6 5 2 ad23 power management daux0 ad07 daux4 q1 jp11 10 /a u x _ r d a5 ad01 jp5 d9 c/be1# gnd m66en nc c15 a[0:7] stop# u4 24c04 3 2 1 5 6 7 8 a2 a1 a0 sda scl test vcc ad15 perr# /a u x _ w r rst_p daux3 a5 ird y# /adr_wr daux5 ad00 c8 74hc374 tx1_hi ad11 q5 +5v /ad r_w r daux2 49/52/61/64/77/83/90/96 ad24 stio1 c4io a0 gnt# /tx_en daux6 c/be0# daux0 vdd_hfc frame# stio2 f0io ad26 p89/90 vdd_hfc /a u x _w r c9 /a u x _r d ad25 pci_st1a pciadr b20 a20 b21 a22 b23 a23 b24 a25 b27 a28 b29 a29 b30 a31 b32 a32 a44 b45 a46 b47 a47 b48 a49 b52 b53 a54 b55 a55 b56 a57 b58 a58 b26 b33 b44 a52 a43 ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad09 ad08 ad07 ad06 ad05 ad04 ad03 ad02 ad01 ad0 c/be3# c/be2# c/be1# c/be0# par c5 serr# 74hc374 gnd vdd_hfc 74hc74 /t x2_lo c3 +5v a6 q3 gnd a2 a1 the r_sens part is optional. it is used to decrease the receiver sensitivity for wake-up signals to avoid a wake-up caused by disturbance on the isdn line.
863c @39 1 (" _v (# :q^eqbi " ! cologne chip d6 1 r22 3v3 5v/uni +5v rg1 c23 r13 gnd re2 d3 gnd r20 jp8 rb2 2.0 isdn pci card for 3.3/5 v or universal power with d3cold support a4 22 thursday, october 19, 2000 title size document number rev date: sheet of r15 jp9 5v r14 q10 rg4 tx1_hi lev_r1 r17 u5 1 4 2 3 6 7 vin adj vout vout vout vout q11 r24 c32 r16 /tx2_lo ra2 isd n_st1 rec1 rec2 trans1 trans2 r21 vdd_hfc vdd_hf c + c19 c24 c22 q9 d8 rc2 gnd gnd 1 gnd gnd r23 r19 tr1a rec d4 /tx_e n tx2_hi d7 ra1 d5 adj_lev c18 q6 gnd rf1 5v r1 5v/uni gnd gnd rb1 c27 1 /tx1_lo rd1 + c28 r18 rf2 re4 vi/o gnd lev_r2 r_sens rd2 3v3 rc1 c21 rg3 +5v q8 rg2 tr1b trans 1 c20 gnd r2 re1 3v3 re3 c25 3v3 jp6 jp7 q7 gnd c26
863c @39 1 :q^eqbi " ! (# _v (# cologne chip isdn pci card for 3.3/5 v or universal power with d3cold support capacitors resistors ic's c01 33 r01 10k u1 74hc74 c02 33n nearby u2 r02 1m u2 hfc-s pci a cologne chip ag c03 33n nearby u2 r03 1m u3 74hc374 optional c04 33n nearby u2 r04 10k u4 24c04 c05 33n nearby u2 r05 330 u5 lm317l/so c06 33n nearby u2 r06 10k c07 33n nearby u2 r09 10k c08 33n nearby jp1 optiona l r10 10k c09 33n nearby jp2 optional r11 10k connectors c10 33n nearby u1 r12 10k c11 33n nearby u4 r13 3k9 jp1 pcm optional c12 33n nearby u3 optional r14 680k jp2 io optional c13 1 r15 1m2 jp3 reset options c14 47p depends on crystal r16 3k3 jp4 power options c15 47p depends on crystal r17 100 jp5 power options c16 22 r18 5k6 jp6 power options c17 33n r19 3k3 jp7 power options c18 22p nearby u2 r20 180 jp8 power options c19 33 r21 1k jp9 power options c20 22p nearby u2 r22 2k2 jp10 eeprom options c21 0 optional r23 2k7 jp11 eeprom options c22 0 optional r24 150 jp12 66 mhz options only for 3.3v systems c23 47n r30 680k ** c24 470p ra1 100k c25 0 optional ra2 100k transistors / crystals c26 0 optional rb1 33k c27 33n rb2 33k q1 bc850c cmpt5088 or similar c28 1 rc1 4k7 q2 12.288m c29 33n nearby jp2 optional rc2 4k7 q3 bc860c cmpt5087 or similar c30 33n nearby jp2 optional rd1 4k7 q4 bc860c cmpt5087 or similar c31 10n only for 3.3v systems rd2 4k7 q5 bc860c cmpt5087 or similar c32 0 optional re1 2k2 1% q6 bc860c cmpt5087 or similar re2 2k2 1% q7 bc850c cmpt5088 or similar diodes re3 430 1% q8 bc850c cmpt5088 or similar re4 430 1% q9 bc850c cmpt5088 or similar d1 ll4148 or similar rf1 15 q10 bc850c cmpt5088 or similar d2 ll4148 or similar rf2 15 q11 bc860c cmpt5087 or similar d3 bav99 can also be 2*4148 * rg1 3k 1% d4 bav99 can also be 2*4148 * rg2 3k 1% d5 bav70 can also be 2*4148 * rg3 3k9 1% d6 bav99 can also be 2*4148 * rg4 3k9 1% d7 2v7 d8 bav99 can also be 2*4148 * d9 ll4148 ** or similar * alternative footprint required ** optional, not on pcb layout v 2.0

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