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[ak7770] ms0699-e-01-pb 2008/06 - 1 - the ak7770 is a digital signal processor with an integrated 4-channel audi o adc and a 6-channel audio dac, as well as an s/pdif transmitter. it utilizes an enhanced dual bit architecture that results in wide dynamic range for the adc, and the advanced multi-bit architecture of the dac enables wide dynamic range and low out-of-band noise. two sample-rate conver ters are integrated, a llowing for operation at 48khz sampling rate with input rate s of 32khz, 44.1khz, or 48khz. vo lume control, compression, eq and sound processing are performed by the dsp. in addition, delay adjustment up to 70ms is possible for four output channels through the integrat ed delay ram. the ak7770 is pa ckaged in a space-saving 80-pin lqfp package. dsp - data width: 24-bit (data ram f20.4 floating point) - processing speed: 13.5 ns (1536step/fs; fs = 48khz) - multiplication: 20 x 16 36-bit double precision arithmetic available - program ram: 1536 x 36-bit - coefficient ram: 1536 x 16-bit - offset ram: 64 x 14-bit - dram: 14kword (1word = f16.4 floating point) - sample rate: fs = 48khz - master / slave operation 4:2 selector with input pre-amp 4ch 24-bit adc - 64-times oversampling - sample rate: 48khz - s/(n+d): 84db (fs = 48khz) - dr, s/n: 96db (fs = 48khz) - digital hpf for offset dc cancellation - channel independent digital volume control (+24/-103db, 0.5db step) - soft mute 6ch 24-bit dac - 128-times oversampling - sample rate: 48khz - s/(n+d): 88db (fs = 48khz ) - dr, s/n: 100db - channel independent digital volume control (+12/-115db, 0.5dbstep) - soft mute - digital de-emphasis general description features audio dsp with multi-channel audio codec a k7770eq
[ak7770] ms0699-e-01-pb 2008/06 - 2 - stereo headphone amplifier with volume control - dac3 direct connection - s/(n+d): 73db (fs=48khz) - s/n: 86db (fs=48khz) - analog volume control (+0/- 50db,1.0/2.0/4. 0db per step) - output power: 22.5mw@16 ? - no click noise at power on/off headphone detection circuit (denounce circuit) high tolerance to clock jitter sample rate converter - dual 2ch src - input sample rate: 32khz~48khz - output sample rate: 48khz fixed dit - s/pdif, iec958, aes/ebu, eiaj cp1201 - output selector (dit or through) - 24 bit interface format - 16 bit interface format cmos level digital i/f (for 3.3v) master clock input: 256fs (fs=48khz) master clock output: 128fs, 192fs, 256fs, 384fs three digital audio inputs i2c p i/f power supply: +3.3v 0.3v, +1.8v 0.1v temperature range: -10 c~70 c package: 80pin lqfp (0.5mm pitch)
[ak7770] ms0699-e-01-pb 2008/06 - 3 - block diagram figure 1. block diagram figure 1 shows a simplified diagram of the ak7770, which is not the perfect same as the actual circuit diagram. scl cad0 cad1 pull down hi-z vref 3 adc2 vss1 avdd 3 asel2[1:0] 2 2 2 2 ainl1,ainr1 ainl2,ainr2 ainl3,ainr3 ainl4,ainr4 sdoutad2 dac1 vcom 2 aoutl1,aoutr1 aoutl2,aoutr2 2 sdinda1 xto xti clkgen lflt initrstn so sdout1 sdin3 sdin2 sdin1 dout3 dout2 din2 din1 dsp out2 out1 wdt sda crce testi3 crc wdten micif * clk0 dit tx 0 2 1 3 1 dout1 sdout2 0 2 1 3 0 2 1 3 hpl,hpr 2 2 frol2,fror2 fril2,frir2 testi2 cont 2 ckm[1:0] hdt hvcom hvdd vss2 4 3 vss3 dvdd 4 4 dvdd18 testi selckdit selditi[1:0] selo2[1:0] selo1[1:0] div clk3 bitclk3 lrclk3 mclk3 mclk2 mclk1 0 1 rom out3 sdout3 0 2 1 3 selo3[1:0] dit dito hmuten 0 2 seltx[1:0] hpa 3 status hpen open drain internal system clock 0 adc1 sdoutad1 2 2 fril1,frir1 frol1,fror1 asel1[1:0] src srco1 srci1 srcbick1 srclrck1 clk1 bitclk1 lrclk1 div srcmck1 src srco2 srci2 srcbick2 srclrck2 clk2 bitclk2 lrclk2 div srcmck2 dac2 2 dout4 sdinda2 dac3 sdinda3 dout5 internal system clock 3 sto hpen hp "l" external system clock 3 external system clock 0 external system clock 2 external system clock 1 din4 din3 srco1 srco2 lock2e lock1e unlock1 unlock2 detect clko bitclko lrclko mclko mbitclko mlrclk o clkoe bitclko lrclkoe selclk
[ak7770] ms0699-e-01-pb 2008/06 - 4 - cp0,cp1 cram 1536w 16bit dp0,dp1 dram 1536w 24bit mpx16 mpx20 ofreg 64w x 14bit x y multiply 16bit20bit 36bit micon i/f control pram 1536w 36bit dec pc stack : 5level(max) mul dbus shift a b a lu 40bit overflow margin: 4bit dr0 ~ 3 over flow data generator division 20 20 20 peak detector serial i/f cbus(16bit) dbus(24bit) 36bit 24bit 40bit 40bit 40bit dlram 14kw 20bit ptmp(lifo) 624bit dlp0,dlp1 224bit 224bit din1 din2 dout2 224bit 224bit 40bit dout3 dout1 tmp 824bit 224bit 224bit 224bit din3 din4 dout4 224/20/16bit 224/20/16bit dout5 figure 2. ak7770 dsp block diagram
[ak7770] ms0699-e-01-pb 2008/06 - 5 - ordering information ak7770eq -10 +70 c 80pin lqfp (0.5mm pitch) AKD7770 evaluation board pin assignment (top view) 80 p in lqf p aoutr1 hvdd 61 62 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 72 7 3 71 7 4 7 6 7 7 7 5 7 8 7 9 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 32 31 2 9 2 8 3 0 2 7 2 5 2 4 2 6 2 3 22 21 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 hpen sto dvdd vss3 dvdd18 testi3 hdt hpr hvcom vss2 hpl aoutr2 aoutl2 aoutl1 vss1 avdd ainl2 clk2 lrclk2 bitclk1 vss3 frol1 vss3 frir2 fror2 frol2 ainl3 ainr3 dvdd18 lrclk1 input output i/o power pin fril2 testi2 sdin1 sdout3 frir1 hmuten initrstn dvdd18 testi ckm[0] vss1 dvdd cad0 scl vss3 cad1 bitclk3 ckm[1] clk3 lrclk3 ainr1 dvdd bitclk2 sda sdin2 fror1 avdd vcom ainr4 vss1 lflt avdd fril1 ainl4 ainr2 xti lrclko clko sdout1 bitclko xto clk1 sdout2 ainl1 dvdd18 sdin3 tx dvdd input output i/o power pin
[ak7770] ms0699-e-01-pb 2008/06 - 6 - pin function no. pin name i/o functi on classification 1 frir1 i rch feedback resistance input pin for adc1 analog 2 fril1 i lch feedback resistance input pin for adc1 3 frol1 o lch feedback resistance output pin for adc1 at initial reset, this pin goes hi-z. 4 lflt o loop filter pin. connect a 10nf cap to avdd. the output is avdd at initial reset 5 avdd - analog power supply pin 3.3v (typ) 6 vss1 - analog ground pin 0v (c onnected to silicon substrate) analog power supply 7 testi i test pin (internal pull-down) connect to gnd. test 8 ckm [0] i clock mode selection pin connect to gnd. mode choice 9 hmuten i headphone amplifier mute pin headphones 10 initrstn i reset pin (for initialization) use to initialize the ak7770. reset 11 test2 i test pin connect to gnd. test 12 dvdd18 - digital power supply pin 1.8v(typ) 13 vss3 - digital ground pin 0v 14 dvdd - digital power supply pin 3.3v(typ) digital power supply 15 lrclko o left/right clock output pin the output in initial reset is ?l?. system clock 16 clko o clock output pin the output in initial reset is ?l?. 17 bitclko o bit clock output pin the output in initial reset is ?l?. 18 sdout1 o serial da ta output 1 pin the output in initial reset is ?l?. serial data 19 sdout2 o serial da ta output 2 pin the output in initial reset is ?l?. 20 sdout3 o serial da ta output 3 pin the output in initial reset is ?l?. 21 xto o crystal oscillator output pin connect a crystal oscillator between the xti pin and xto pin. leave open when using an external clock source. the output in initial reset is undetermined. 22 xti i crystal oscillator input pin connect a crystal oscillator between the xti pin and xto pin. input an external clock into the xti pin when not using a crystal oscillator. a system clock 23 dvdd - digital power supply pin 3.3v(typ) 24 vss3 - digital ground pin 0v 25 dvdd18 - digital power supply pin 1.8v(typ) digital power supply
[ak7770] ms0699-e-01-pb 2008/06 - 7 - no. pin name i/o functi on classification 26 lrclk1 i left/right clock input 1 pin system clock 27 clk1 i master clock 1 pin 28 bitclk1 i bit clock 1 pin 29 sdin1 i serial data input 1 pin serial data 30 lrclk2 i left/right clock input 2 pin system clock 31 clk2 i master clock 2 pin 32 bitclk2 i bit clock 2 pin 33 sdin2 i serial data input 2 pin 34 cad1 i i2c bus address pin 1 i2c interface 35 cad0 i i2c bus address pin 0 i2c interface 36 scl i i2c clock pin i2c interface 37 dvdd - digital power supply pin 3.3v(typ) 38 vss3 - digital ground pin 0v 39 dvdd18 - digital power supply pin 1.8v(typ) digital power supply 40 sda i/o i 2 c bus data clock pin sda goes to ?hi-z? during initial reset. i2c interface 41 hpen o headphone detect output pin initial reset for headphone search is determined by the state of hdt headphones 42 sto o status output pin when hdt = ?h?, sto = ?l? when hdt = ?l?, sto = ?h? the output in initial reset is ?h? status 43 tx o s/pdif transmitter output pin s/pdif data is output when seltx [1 :0] bit= ?00?. ?l? during initial rest. tx 44 dvdd - digital power supply pin 3.3v(typ) 45 vss3 - digital ground pin 0v 46 dvdd18 - digital power supply pin 1.8v(typ) digital power supply 47 sdin3 i serial data input 3 pin serial data 48 bitclk3 i bit clock 3 pin 49 clk3 i master clock 3 pin 50 lrclk3 i left/right clock 3 pin system clock 51 ckm [1] i clock mode selection pin connect to gnd. mode selection 52 testi3 i test pin this pin must be connected to dvdd. test
[ak7770] ms0699-e-01-pb 2008/06 - 8 - no. pin name i/o func tion classification 53 hdt i headphone detection pin headphones 54 hpr o headphone rch output pin output is vss2 at initial reset headphones 55 hvdd - headphone power supply pin 3.3v(typ) analog power supply 56 hvcom o headphone common voltage output pin connect a of 1 f cap to vss2. do not use for an outside circuits. output at initial reset is vss2 headphones 57 vss2 - headphone ground pin 0v analog power supply 58 hpl o headphone lch output pin output is vss2 at initial reset headphone output 59 aoutr2 o dac2 rch output pin output at initial reset is vss1 60 aoutl2 o dac2 lch output pin output at initial reset is vss1 61 aoutr1 o dac1 rch output pin output at initial reset is vss1 62 aoutl1 o dac1 lch output pin output at initial reset is vss1 analog output 63 vss1 - analog ground pin 0v (c onnected to silicon substrate) analog power supply 64 avdd - analog power supply pin 3.3v (typ) analog power supply 65 fror2 o adc2 rch feedback resistance output pin the output at initial reset is hi-z analog output 66 frir2 i adc2 rch feedback resistance input pin analog input 67 fril2 i adc2 lch feedback resistance input pin analog input 68 frol2 o adc2 lch feedback resistance input pin the output at initial reset is hi-z. analog output 69 ainr1 i adc rch single-ended input 1 pin 70 ainl1 i adc lch single-ended input 1 pin 71 ainr2 i adc rch single-ended input 2 pin 72 ainl2 i adc lch single-ended input 2 pin 73 ainr3 i adc rch single-ended input 3 pin 74 ainl3 i adc lch single-ended input 3 pin 75 ainr4 i adc rch single-ended input 4 pin 76 ainl4 i adc lch single-ended input 4 pin analog input 77 vss1 - analog power supply pin 0.0v analog power supply 78 vcom o analog common voltage output pin output at initial reset is vss1. c onnect capacitors of 0.1uf and 2.2uf between this pin and vss1. no external circuits should be connected to this pin. analog output 79 avdd - analog power supply pin 3.3v (typ) analog power supply 80 fror1 o rch feedback resistance output pin for adc1 the output in initial reset is hi-z analog output note 1. do not leave digital input pins floating. note 2. when analog input pins (ainl1-4 pins, ainr1-4) are not used, leave them open.
[ak7770] ms0699-e-01-pb 2008/06 - 9 - handling of unused pin the unused i/o pins should be processed appropriately as below. classification pin name setting analog frir1-2, fril1-2, frol1-2, fror1-2, xto, aoutl1-2, aoutr1-2, ainl1-4, ainr1-4 these pins should be open. lrclko,clko, bitclko, sdout1-3, hpen, hpr, hpl these pins should be open. testi2, clk1-3, bitclk1-3, lrclk1-3 sdin1-3, hdt these pins should be connected to vss3. digital hmuten this pin should be connected to dvdd. (vss1 = vss2 = vss3=0v: note 3 ) parameter symbol min max units power supply voltage analog analog digital digital avdd hvdd dvdd dvdd18 -0.3 -0.3 -0.3 -0.3 4.3 4.3 4.3 2.5 v v v v input current (except power supply pins) iin - 10 ma analog input voltage ainl1~ainl4, ainr1~ainr4 fril1, fril2, frir1, fril2 vina -0.3 avdd+0.3 v digital input voltage vind -0.3 dvdd+0.3 v ambient operating temperature ta -10 70 c storage temperature tstg -65 150 c note 3. all voltages referred to ground. connect vss1, vss2, vss3 to the same ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guara nteed at these extremes. (vss1 = vss2 = vss3=0v: note 3 ) parameter symbol min typ max units supply voltage analog analog digital digital avdd hvdd dvdd dvdd18 3.0 3.0 3.0 1.7 3.3 3.3 3.3 1.8 3.6 3.6 3.6 1.9 v v v v difference difference difference hvdd-avdd hvdd-dvdd avdd-dvdd -0.3 -0.3 -0.3 0 0 0 +0.3 +0.3 +0.3 v v v note 4. the power supply sequence for avdd hvdd, dvdd, dvdd 18 is not critical but all power supplies must be on before start operating the ak7770. note 5. do not turn off the power supply of the ak7770 with the power supply of the surrounding device turned on. dvdd must not exceed the pull-up of sda and scl of i 2 c bus. (the diode exists for dvdd in the sda and scl pins.) *akemd assumes no responsibility for the usag e beyond the conditions in this datasheet. absolute maximum ratings recommended oerating conditions
[ak7770] ms0699-e-01-pb 2008/06 - 10 - adc1/2 (ta=25 c; avdd=hvdd=dvdd=3.3v; dvdd18=1.8v; vss1=vss2 =vss3=0v; signal frequency = 1khz; measurement bandwidth =20hz~20khz , fs=48khz fs; src reset; unless otherwise specified) parameter min typ max units feedback resistance 10 30 k ? pre-amp s/(n+d) ( note 6 ) 99 db s/n (a-weighted) ( note 6 ) 105 db load capacitance 20 pf resolution 24 bits pre-amp dynamic characteristics + s/(n+d) fs = 48khz (-1dbfs) 74 84 db adc1 adc2 dynamic range fs = 48khz (a-weighted) ( note 7 , note 8 ) 88 96 db s/n fs = 48khz (a-weighted) ( note 7 ) 85 96 db interchannel isolation( (f=1khz) ( note 9 ) 85 100 db dc accuracy adc1 gain mis-match between channels 0.1 0.3 db adc2 analog input input voltage 2.05 2.2 2.35 vp-p note 6. value measured with an input resistance of 47k and a feedback resistance of 16k with a 2vrms input voltage. note 7. the value measured through the pre-amp and adc with an input resistance of 47k and a feedback resistance of 16k with a 2vrms input voltage. note 8. s/(n+d) with an input signal of -60dbfs note 9. isolation between ainl1-4, ainr1-4 with a -1dbfs input signal. note 10. when the src on dit operate asynchronously, the performance may be degraded. v dac1/2 (ta= 25 c; avdd=hvdd=dvdd=3.3v; dvdd18=1.8v; vss1=vss2=vss3=0v; signal frequency = 1khz; measurement bandwidth =20h z~20khz, fs=48khz fs; src reset; unless otherwise specified) parameter min typ max units resolution 24 bits dynamic characteristics s/(n+d) (0 dbfs) 78 88 db dynamic range (a-weighted) ( note 11 ) 92 100 db s/n (a-weighted) 92 100 db interchannel isolation (f=1khz) ( note 12 ) 90 100 db dc accuracy gain mis-match between channels 0.2 0.5 db analog output output voltage ( note 13 ) 2.02 2.18 2.34 vp-p load resistance 5 k ? dac1 dac2 load capacitance 30 pf note 11. s/(n+d) with a -60dbfs input signal note 12. isolation between lch-rch between each dac note 13. full scale output voltage analog characteristics
[ak7770] ms0699-e-01-pb 2008/06 - 11 - dac3 + hp amp (ta=25 c; avdd=hvdd=dvdd=3.3v; dvdd18=1.8v; vss1=vss2=vss3=0v; signal frequency = 1khz; measurement bandwidth =20hz~20khz , fs=48khz fs; src reset; fs=48khzs) parameter min typ max units analog volume control characteristics opga): maximum (opga[4:0] bits= ?1fh?) - +0 - db gain minimum (opga[4:0] bits= ?01h?) - -50 - db step size 0.1 1 - db 0.1 2 - db +0db -16db -16db -38db -38db -50db - 4 - db headphone-amp characteristics: dac hpl/hpr pins, rl=16 output voltage 1.53 1.7 1.87 vpp s/(n+d) ( ? 3dbfs) 63 73 - db s/n (a-weighted) 80 86 - db inter channel isolation 60 80 - db inter channel gain mismatch - 0.1 0.5 db load resistance (rl, figure 3 ) 16 - - load capacitance (c1, figure 3 ) - - 30 pf load capacitance (c2, figure 3 ) - - 300 pf figure 3. headphone amplifier output circuit ? + + c1 c2 rl 10 ? 0.22 f 47 f hpl pin hpr pin hp-amp measurement point
[ak7770] ms0699-e-01-pb 2008/06 - 12 - src (src1, src2) (ta=-10 c ~70 c; avdd=hvdd=dvdd=3.3v; dvdd18=1.8v; vss1=vss2=vss3=0v; input signal frequency = 1khz; measurement bandwidth = 20hz to fso/2, fs=48khz) parameter symbol min typ max units resolution 24 bits input sample rate fsi 32 48 khz output sample rate fso - 48 - khz thd+n (input= 1khz, 0dbfs) fso/fsi=48khz/44.1khz fso/fsi=48khz/32khz -112 -112 db db dynamic range (input= 1khz, -60dbfs) fso/fsi=48khz/44.1khz fso/fsi=48khz/32khz dynamic range (input= 1khz, -60dbfs, a-weighted) fso/fsi=48khz/32khz 113 113 115 db db db ratio between input and output sample rate fso/fsi 0.98 1.5 - (ta=-10 c ~70 c; avdd=hvdd=dvdd=3.0~3.6v, dvdd18=1.7~1.9v, vss1 = vss2 = vss3=0v) parameter symbol min typ max units high level input voltage ( note 14 ) vih 80%dvdd v low level input voltage ( note 14 ) vil 20%dvdd v scl, sda high level input voltage vih 70%dvdd v scl, sda low level input voltage vil 30%dvdd v hdt high level input voltage vih 85%hvdd v hdt low level input voltage vil 45%hvdd v high level output voltage iout=-100 a voh dvdd-0.5 v low level output voltage iout=100 a ( note 15 ) vol 0.5 v sda low level output voltage iout=3ma vol 0.4 v input leakage current ( note 16 ) input leakage current pull-down pin ( note 17 ) input leakage current xti pin iin iid iix 22 26 10 a a a note 14. scl, sda and hdt pins are not included. note 15. the sda pin is not included note 16. pull-down pins and the xti pin are not included. note 17. pull-down pins (typ 150k) and testi [description rule] regarding the input/output levels in the text, the low level will be represented as ?l?, and the high level as ?h?. in principle, ?0? and ?1? will be used to represent the bus (serial/parallel) such as registers. ##h means hexadecimal code. (#=0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f) dc characteristics
[ak7770] ms0699-e-01-pb 2008/06 - 13 - (ta=25 c; avdd=hvdd=dvdd=3.0~3.6v(typ=3.3 v, max=3.6v); dvdd18=1.7~1. 9v(typ=1.8v, max=1.9v); vss1= vss2 = vss3=0v) parameter min typ max units power supply power supply electric current normal operation avdd 75 - ma hvdd 6 - ma dvdd 5 - ma dvdd18 ( note 18 ) 58 85 ma avdd+hvdd+dvdd 120 ma reset (initrstn pin = ?l? reference data) avdd+hvdd+dvdd+dvdd18 ( note 19 ) 2 - ma note 18. dvdd18 value varies with us e frequency and dsp program contents. note 19. this is a reference value when using a crystal oscillator. since most of the supply current at the initial reset state is in the oscillator section, the value may vary slightly according to the crystal type a nd the external circuit. this is a ?reference data? only. adc1/2 (ta=-10 c ~70 c; avdd=dvdd=3.0~3.6v; dvdd18=1.7~1.9v; vss1 = vss2 = vss3=0v; fs=48khz; note 20 ) parameter symbol min typ max units passband (0.1db) ( note 21 ) (-0.2db) (-3.0db) pb 0 20.0 23.0 18.9 khz khz khz stopband sb 28 khz passband ripple ( note 21 ) pr 0.04 db stop band attenuation ( note 22 , note 23 ) sa 68 db group delay deviation ? gd 0 s group delay (ts=1/fs) gd 16 ts digital filter + analog filter amplitude characteristic 20hz~20.0khz ( note 24 ) 0.5 db note 20. frequency of each amplitude char acteristic is in proportion to fs (sampli ng rate). the characteristic of the high pass filter is not included. note 21. the passband is from dc to 18.9khz when fs=48khz. note 22. attenuation frequency is 48khz to 3.044mhz when fs=48khz. note 23. when fs = 48khz, the analog modulator samples the input signal at 3.072mhz. there is no attenuation of an input signal in band (n x 3.072mhz 21.99khz; n=0, 1, 2, 3?) of integer times the sampling frequency of the digital filter. note 24. value through pre-amp and adc. external input resistance is 47k ? , and feedback resistance is 16k . power consumption digital filter characteristics
[ak7770] ms0699-e-01-pb 2008/06 - 14 - dac1-3 (ta=-10 c ~70 c; avdd=dvdd=3.0~3.6v; dvdd18=1.7~1.9v; vss1 = vss2 = vss3=0v; fs=48khz; dem=off) parameter symbol min typ max units passband (0.05db) ( note 25 ) (-6.0db) pb 0 24 21.7 khz khz stopband ( note 25 ) sb 26.2 khz passband ripple pr 0.01 db stopband attenuation sa 64 db group delay (ts=1/fs) ( note 26 ) gd 24 ts digital filter + analog filter amplitude characteristic 20hz~20.0khz 0.5 db note 25. the pass band and stop band frequencies are proporti onal to ?fs? (system sampling rate), and represents pb=0.4535 * fs (@ -0.05db), and sb=0.5465 * fs, respectively. note 26. the digital filter?s delay is cal culated as the time from setting data into the input register until an analog signal is output. src1/2 (ta=-10 c ~70 c; avdd=hvdd=dvdd=3.0~3.6v; dvdd18=1.7~1.9v; vss1 = vss2 = vss3=0v) parameter symbol min typ max units passband -0.01db (0.980 fso/fsi 1.500) pb 0 0.4583fsi khz stop band (0.980 fso/fsi 1.500) sb 0.5417fsi khz passband ripple pr 0.01 db stop band attenuation sa 102.2 db group delay (ts=1/fs) ( note 27 ) gd 56 ts note 27. src delay time is calculated from the start of srclrck just after data input to the start of lrclko just after data output, when there is no phase difference between srclrck and lrclko.
[ak7770] ms0699-e-01-pb 2008/06 - 15 - system clock (ta=-10 c ~70 c; avdd=hvdd=dvdd=3.0~3.6v; dvdd18=1.7~1.9v; vss1 = vss2 = vss3=0v) parameter sysmbol min typ max units xti a) with a crystal oscillator fxti - 12.288 - mhz b) with an external clock duty cycle ratio 40 50 60 % fxti 11.0 12.4 mhz clk1, clk2 frequency ( note 28 ) fck 2.0 12.288 50 mhz duty cycle ratio 40 50 60 % clock speed 256 1024 fs lrclk1, lrclk2 frequency ( note 29) fs 8 48 48.4 khz bitclk1, bitclk2 frequency high level width low level width tbclkh tbclkl 150 150 ns ns clk3 frequency ( note 28 ) fck 11.0 12.288 50 mhz duty cycle ratio 40 50 60 % clock speed 256 1024 fs lrclk3 frequency ( note 29 ) fs 43 48 48.4 khz bitclk3 frequency high level width low level width tbclkh tbclkl 150 150 ns ns note 28. clkn and lrclkn must occur in the same period, but phase matching is not critical. note 29. the sample rate must match lrclk. reset (ta=-10 c ~70 c; avdd=hvdd=dvdd=3.0~3.6v; dvdd18=1.7~1.9v; vss1 = vss2 = vss3=0v) parameter symbol min typ max units initrstn ( note 30 ) trst 600 ns note 30. power supply must be up and a master clock must be present before initializing reset. switching characteristics
[ak7770] ms0699-e-01-pb 2008/06 - 16 - audio system interface 1. sdin1~sdin3, sdout1~sdout3 (ta=-10 c ~70 c; avdd=hvdd=dvdd=3.0~3.6v; dvdd18=1.7~1.9v; v ss1 = vss2 = vss3=0v; cl=20pf) parameter symbol min typ max units input delay time from bitclkn ? ?to lrclk ( note 31 ) tblrd 20 ns delay time from lrclkn to bitclkn ? ? ( note 31 ) tlrbd 20 ns serial data entry latch setup time tbsids 80 ns serial data entry latch hold time tbsidh 80 ns output bitclko frequency fbclk 64 fs bitclko duty cycle ratio 50 % delay time from bitclko ? ? to lrclko tmbl -20 40 ns delay time from lrclko to sdoutn (only msb) tlrd 80 ns delay time from bitclko to sdoutn tbsod 80 ns sdinn sdoutn ( note 32 ) delay time from sdinn to sdoutn tiod 50 ns note 31. bitclkn ? ? must not occur at the same time as lrckn edge note 32. sdin1 sdout1: control register setti ng selo1[1:0]= ?11?, out1e=1 sdin2 sdout2: control register setti ng selo2[1:0]= ?11?, out2e=1 sdin3 sdout3: control register setti ng selo3[1:0]= ?11?, out3e=1
[ak7770] ms0699-e-01-pb 2008/06 - 17 - microcontroller interface (i2cbus interface) (ta=-10 c ~70 c; avdd=hvdd=dvdd=3.0~3.6v; dvdd18=1.7~1.9v; vss1= vss2 = vss3=0v) parameter symbol min typ max unit i 2 c timing scl clock frequency fscl 400 khz bus free time between transmissions tbuf 1.3 s start condition hold time (prior to first clock pulse) thd:sta 0.6 s clock low time tlow 1.3 s clock high time thigh 0.6 s setup time for repeated start condition tsu:sta 0.6 s sda hold time from scl falling thd:dat 0 0.9 s sda setup time from scl rising tsu:dat 0.1 s rise time of both sda and scl lines tr 0.3 s fall time of both sda and scl lines tf 0.3 s setup time for stop condition tsu:sto 0.6 s pulse width of spike noise suppress by input filter tsp 0 50 ns capacitive load on bus cb 400 pf note 33. i2c is a registered tr ademark of philips semiconductors.
[ak7770] ms0699-e-01-pb 2008/06 - 18 - timing diagram figure 4. system clock figure 5. reset 1/fxti 1/fxti vih vil xti 1/fs 1/fs vih vil lrclkn tbclkl tbclkh 1/fbclk 1/fbclk vih vil bitclkn tbclk=1/fbclk txti=1/fxti ts=1/fs n = 1, 2, 3 n = 1, 2, 3 vil trst initrstn
[ak7770] ms0699-e-01-pb 2008/06 - 19 - figure 6. audio system interface stop start start stop thigh thd:dat sda scl tbuf tlow tr tf tsu:dat vih vil thd:sta tsu:sta vih vil tsu:sto tsp figure 7. microcontroller interface (i 2 c bus) sdout*=sdout1, sdout2, sdout3 sdin*=sdin1, sdin2, sdin3 lrclkn bitclkn sdout* sdin* lrclko bitclko tbsidh tbsids tbsod tlrd tblrd tlrbd 50%dvdd 50%dvdd 50%dvdd 50%dvdd tmbl tmbl
[ak7770] ms0699-e-01-pb 2008/06 - 20 - package 80-pin lqfp (unit: mm ) 14.00.2 12.00.2 0.50 1 20 21 40 41 60 61 80 12.00.2 14.00.2 1.25typ 0.08 m 0.125 +0.10 -0.05 0.500.2 1.85max 0.10 +0.15 -0.10 1.400.2 0.10 0.200.1 0 ~ 10 materials and lead specification package: epoxy lead frame: copper lead-finish: soldering plate (pb free)
[ak7770] ms0699-e-01-pb 2008/06 - 21 - marking revision history date (yy/mm/dd) revision reason page contents 08/01/08 00 first edition 08/06/24 01 error correct 15 switching characteristics system clock clk1, clk2 frequency; 11.0 2.0 1) pin #1 indication 2) date code: xxxxxxx(7digits) 3) marking code: ak7770eq 4) asahi kasei logo ak7770eq xxxxxxx akm
[ak7770] ms0699-e-01-pb 2008/06 - 22 - important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. z akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akemd products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akemd pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above cont ent and conditions, and the buyer or distributor agrees to assume any and all re sponsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification. thank you for your access to akemd products information. more detail product information is available, please contact our sales office or authorized distributors.

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