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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. april 2011 doc id 018725 rev 1 1/38 38 lsm303dlm sensor module: 3-axis accelerometer an d 3-axis magnetometer features analog supply voltage: 2.16 v to 3.6 v digital supply voltage ios: 1.8 v power-down mode 3 magnetic field channels and 3 acceleration channels 1.3 to 8.1 gauss magnetic field full-scale 2 g /4 g /8 g dynamically selectable full- scale high performance g-sensor i 2 c serial interface 2 independent programmable interrupt generators for free-fall and motion detection accelerometer sleep-to-wakeup function 6d orientation detection ecopack ? , rohs, and ?green? compliant applications compensated compass map rotation position detection motion-activated functions free-fall detection intelligent power-saving for handheld devices display orientation gaming and virtual reality input devices impact recognition and logging vibration monitoring and compensation description the lsm303dlm is a system-in-package featuring a 3d digital linear acceleration sensor and a 3d digital magnetic sensor. the various sensing elements are manufactured by using specialized micromachining processes, while the ic interfaces are realized using a cmos technology that allows the design of a dedicated circuit which is trimmed to better match the sensing element characteristics. the lsm303dlm has a linear acceleration full-scale of 2 g / 4 g / 8 g and a magnetic field full-scale of 1.3 / 1.9 / 2.5 / 4.0 / 4.7 / 5.6 / 8.1 gauss , both fully selectable by the user. the lsm303dlm includes an i 2 c serial bus interface that supports standard mode (100 khz) and fast mode (400 khz). the system can be configured to generate an interrupt signal by inertial wakeup/free-fall events, as well as by the position of the device itself. thresholds and timing of interrupt generators are programmable on the fly by the end user. magnetic and accelerometer parts can be enabled or put into power-down mode separately. the lsm303dlm is available in a plastic land grid array package (lga), and is guaranteed to operate over an extended temperature range from -40 to +85 c. table 1. device summary part number temp. range [c] package packing lsm303dlm -40 to +85 lga-28 tr ay LSM303DLMTR tape and reel lga-28l (5x5x1.0 mm) www.st.com
contents lsm303dlm 2/38 doc id 018725 rev 1 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.1 sensor i 2 c - inter ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 linear acceleration sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 sleep-to-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 high current wiring effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.1 i 2 c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.1.1 i 2 c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1.2 linear acceleration digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1.3 magnetic field digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
lsm303dlm contents doc id 018725 rev 1 3/38 9.1 linear acceleration register description . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.1.1 ctrl_reg1_a (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.1.2 ctrl_reg2_a (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.1.3 ctrl_reg3_a (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.1.4 ctrl_reg4_a (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.1.5 ctrl_reg5_a (24h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ) 26 9.1.6 hp_filter_reset_a (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.1.7 reference_a (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.1.8 status_reg_a(27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.1.9 out_x_l_a (28h), out_x_h_a (29h) . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.1.10 out_y_l_a (2ah), out_y_h_a (2bh) . . . . . . . . . . . . . . . . . . . . . . . . 27 9.1.11 out_z_l_a (2ch), out_z_h_a (2dh) . . . . . . . . . . . . . . . . . . . . . . . . 27 9.1.12 int1_cfg_a (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.1.13 int1_src_a (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.1.14 int1_ths_a (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.1.15 int1_duration_a (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.1.16 int2_cfg_a (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.1.17 int2_src_a (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.1.18 int2_ths_a (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.1.19 int2_duration_a (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.2 magnetic field sensing register description . . . . . . . . . . . . . . . . . . . . . . . 32 9.2.1 cra_reg_m (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.2.2 crb_reg_m (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.2.3 mr_reg_m (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.2.4 out_x_h_m (03), out_x_lh_m (04h) . . . . . . . . . . . . . . . . . . . . . . . . 33 9.2.5 out_z_h_m (05), out_z_l_m (06h) . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.2.6 out_y_h_m (07), out_y_l_m (08h) . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.2.7 sr_reg_m (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.2.8 ir_reg_m (0ah/0bh/0ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.2.9 who_am_i _m (0f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
list of tables lsm303dlm 4/38 doc id 018725 rev 1 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3. sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. i 2 c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 7. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 10. transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 11. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 16 table 12. sad and read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 13. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 17 table 14. sad and read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 15. register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 16. ctrl_reg1_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 17. ctrl_reg1_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 18. power mode and low-power output data rate configurations . . . . . . . . . . . . . . . . . . . . . . . 21 table 19. normal-mode output data rate configurations and low-pass cut-off frequencies . . . . . . . . 22 table 20. ctrl_reg2_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 21. ctrl_reg2_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 22. high-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 23. high-pass filter cut-off frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 24. ctrl_reg3_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 25. ctrl_reg3_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 26. data signal on int 1 and int 2 pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 27. ctrl_reg4_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 28. ctrl_reg4_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 29. ctrl_reg5_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 30. ctrl_reg5_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 31. sleep-to-wakeup configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 32. reference_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 33. reference_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 34. status_reg_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 35. status_reg_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 36. int1_cfg_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 37. int1_cfg_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 38. interrupt 1 source configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 39. int1_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 40. int1_src_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 41. int1_ths register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 42. int1_ths description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 43. int1_duration_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 44. int2_duration_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 45. int2_cfg_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 46. int2_cfg_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 47. interrupt mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 48. int2_src_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
lsm303dlm list of tables doc id 018725 rev 1 5/38 table 49. int2_src_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 50. int2_ths register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 51. int2_ths description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 52. int2_duration_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 53. int2_duration_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 54. cra_reg_m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 55. cra_reg_m description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 56. data rate configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 57. cra_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 58. gain setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 59. mr_reg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 60. mr_reg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 61. magnetic sensor operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 62. sr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 63. sr register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 64. ira_reg_m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 65. irb_reg_m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 66. irc_reg_m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 67. who_am_i_m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 68. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
block diagram and pin description lsm303dlm 6/38 doc id 018725 rev 1 1 block diagram and pin description 1.1 block diagram figure 1. block diagram y+ z+ y- z- x+ x- mux s da_m s cl_m i ( a ) + - charge amplifier s en s ing block s en s ing interf a ce a/d control logic converter di i2c int1 int2 mux i (m) + - charge amplifier y+ z+ y- z- x+ x- interrupt gen. clock trimming circuit s reference off s et circuit s built-in circuit s s et/re s et s da_a s cl_a am092 3 9v1
lsm303dlm block diagram and pin description doc id 018725 rev 1 7/38 1.2 pin description figure 2. pin connection table 2. pin description pin# name function 1 reserved connect to gnd 2 gnd 0 v supply 3 reserved connect to gnd 4 sa0_a linear acceleration signal i 2 c less significant bit of the device address (sa0) 5 nc internally not connected 6vddpower supply 7 reserved connect to vdd 8 reserved leave unconnected 9 reserved leave unconnected 10 reserved leave unconnected 11 reserved leave unconnected 12 set2 s/r capacitor connection (c2) 13 reserved leave unconnected 14 reserved leave unconnected 15 c1 reserved capacitor connection (c1) 16 set1 s/r capacitor connection (c2) 17 reserved connect to gnd 18 drdy_m magnetic signal interface data ready 19 sda_m magnetic signal interface i 2 c serial data (sda) $)2%#4)/./& $%4%#4!",% -!'.%4)#&)%,$3 9 8 : $)2%#4)/./& $%4%#4!",% !##%,%2!4)/.3 2%3 &),46$$ 3#,?! 2%3 &),4).9 '.$ "/44/- 6)%7 2%3 2%3 3$!?! ).4 ).4 6dd?)/ 2%3 2%3 3%4 2%3 2%3 2%3 .# 3$!?- .# 3#,?- 2%3 3%4 6$$ $2$9?- ,3-$- 3!?! 2%3 # 2%3 9 8 : !-v
block diagram and pin description lsm303dlm 8/38 doc id 018725 rev 1 20 scl_m magnetic signal interface i 2 c serial clock (scl) 21 nc internally not connected 22 vdd_io signal interface power supply for i/o pins 23 reserved connect to vdd_io 24 scl_a linear acceleration signal interface i 2 c serial clock (scl) 25 sda_a linear acceleration signal interface i 2 c serial data (sda) 26 int1 inertial interrupt 1 27 int2 inertial interrupt 2 28 reserved connect to gnd table 2. pin description (continued) pin# name function
lsm303dlm module specifications doc id 018725 rev 1 9/38 2 module specifications 2.1 sensor characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted (a) . a. the product is factory calibrated at 2.5 v. the opera tional power supply range is from 2.16 v to 3.6 v. table 3. sensor characteristics symbol parameter test conditions min. typ. (1) max. unit la_fs linear acceleration measurement range (2) fs bit set to 00 2.0 g fs bit set to 01 4.0 fs bit set to 11 8.0 m_fs magnetic measurement range gn bits set to 001 1.3 gauss gn bits set to 010 1.9 gn bits set to 011 2.5 gn bits set to 100 4.0 gn bits set to 101 4.7 gn bits set to 110 5.6 gn bits set to 111 8.1 la_so linear acceleration sensitivity fs bit set to 00 12-bit representation 1 m g /digit fs bit set to 01 12-bit representation 2 fs bit set to 11 12-bit representation 3.9 m_gn magnetic gain setting gn bits set to 001 (x,y) 1100 lsb/ gauss gn bits set to 001 (z) 980 gn bits set to 010 (x,y) 855 gn bits set to 010 (z) 760 gn bits set to 011 (x,y) 670 gn bits set to 011 (z) 600 gn bits set to 100 (x,y) 450 gn bits set to 100 (z) 400 gn bits set to 101 (x,y) 400 gn bits set to 101 (z) 355 gn bits set to 110 (x,y) 330 gn bits set to 110 (z) 295 gn bits set to 111 (2) (x,y) 230 gn bits set to 111 (2) (z) 205
module specifications lsm303dlm 10/38 doc id 018725 rev 1 2.2 electrical characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted. la_tcso linear acceleration sensitivity change vs. temperature fs bit set to 00 0.01 %/c la_tyoff linear acceleration typical zero- g level offset accuracy (3),(4) fs bit set to 00 60 m g la_tcoff linear acceleration zero- g level change vs. temperature max. delta from 25 c 0.5 m g /c m_cas magnetic cross-axis sensitivity cross field = 0.5 gauss h applied = 3 gauss 1 %fs/ gauss m_ef maximum exposed field no permitting effect on zero reading 10000 gauss m_r magnetic resolution 5 mgauss m_df disturbing field sensitivity starts to degrade. use s/r pulse to restore sensitivity 20 gauss top operating temperature range -40 +85 c 1. typical specificat ions are not guaranteed. 2. verified by wafer level test and measur ement of initial offset and sensitivity. 3. typical zero- g level offset value after msl3 preconditioning. 4. offset can be eliminated by enabl ing the built-in high-pass filter. table 3. sensor characteristics (continued) symbol parameter test conditions min. typ. (1) max. unit table 4. electrical characteristics symbol parameter test conditions min. typ. (1) max. unit vdd supply voltage - 2.16 3.6 v vdd_io module power supply for i/o 1.71 1.8 vdd+0.1 v idd current consumption in normal mode (2) 360 a iddpdn current consumption in power- down mode 2a top operating temperature range -40 +85 c 1. typical specificat ions are not guaranteed. 2. magnetic sensor setting odr = 7.5 hz . accelerometer sensor odr = 50 hz.
lsm303dlm module specifications doc id 018725 rev 1 11/38 2.3 communication interface characteristics 2.3.1 sensor i 2 c - inter ic control interface subject to general operating conditions for vdd and top. figure 3. i 2 c slave timing diagram (b) table 5. i 2 c slave timing values symbol parameter i 2 c standard mode (1) i 2 c fast mode (1) unit min. max. min. max. f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0.01 3.45 0.01 0.9 s t r(sda) t r(scl) sda and scl rise time 1000 20 + 0.1c b (2) 300 ns t f(sda) t f(scl) sda and scl fall time 300 20 + 0.1c b (2) 300 t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. data based on standard i 2 c protocol requirement, not tested in production. 2. cb = total capacitance of one bus line, in pf. b. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both ports. 6'$ 6&/ w i6'$ w vx63 w z6&// w vx6'$ w u6'$ w vx65 w k67 w z6&/+ w k6'$ w u6&/ w i6&/ w z6365 67$57 5(3($7(' 67$57 6723 67$57
absolute maximum ratings lsm303dlm 12/38 doc id 018725 rev 1 3 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 6. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 4.8 v vdd_io i/o pins supply voltage -0.3 to 4.8 v vin input voltage on any control pin (scl, sda) -0.3 to vdd_io +0.3 v a pow acceleration (any axis, powered, vdd = 2.5 v) 3,000 for 0.5 ms g 10,000 for 0.1 ms g a unp acceleration (any axis, unpowered) 3,000 for 0.5 ms g 10,000 for 0.1 ms g t op operating temperature range -40 to +85 c t stg storage temperature range -40 to +125 c this is a mechanical shock sensitive device, improper handling can cause permanent damage to the part. this is an esd sensitive device, improper handling can cause permanent damage to the part.
lsm303dlm terminology doc id 018725 rev 1 13/38 4 terminology 4.1 linear acceleration sensitivity linear acceleration sensitivity describes the gain of the accelerometer sensor and can be determined by applying 1 g acceleration to it. as the sensor can measure dc accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing to the sky) and noting the output value again. by doing so, a 1 g acceleration is applied to the sensor. subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. this value changes very little over temperature and over time. the sensitivity tolerance describes the range of sensitivities of a large number of sensors. 4.2 zero- g level zero- g level offset (la_tyoff) describes the deviation of an actual output signal from the ideal output signal if no linear acceleration is present. a sensor in steady-state on a horizontal surface measures 0 g on both the x and y axes, whereas the z axis measures 1 g . ideally, the output is in the middle of the dynamic range of the sensor (content of out registers 00h, data expressed as 2?s complement number). a deviation from the ideal value in this case is called zero- g offset. offset is, to some extent, a result of stress to the mems sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive me chanical stress. offset changes little over temperature, see ?linear acceleration zero- g level change vs. temperature? (la_tcoff) in table 3. the zero- g level tolerance (tyoff) describes the standard deviation of the range of zero- g levels of a group of sensors. 4.3 sleep-to-wakeup the ?sleep-to-wakeup? function, in conjunction with low-power mode, allows further reduction of system power consumption and the development of new smart applications. the lsm303dlm may be set to a low-power operating mode, characterized by lower data rate refreshing. in this way, the device, even if sleeping, continues sensing acceleration and generating interrupt requests. when the sleep-to-wakeup function is activated, the lsm303dlm is able to automatically wake up as soon as the interrupt event has been detected, increasing the output data rate and bandwidth. with this feature the system may be efficiently switched from low-power mode to full-performance depending on user-selectable positioning and acceleration events, therefore ensuring powe r-saving and flexibility.
functionality lsm303dlm 14/38 doc id 018725 rev 1 5 functionality the lsm303dlm is a system-in-package featuring a 3d digital linear acceleration and 3d digital magnetic field detection sensor. the system includes specific sensing element s and an ic interface capable of measuring both the linear acceleration and the magnetic field applied on it and to provide a signal to the external world through an i 2 c serial interface with separated digital output. the sensing system is manufactured using specialized micromachining processes, while the ic interfaces are realized using a cmos technology that allows the design of a dedicated circuit which is trimmed to better match the sensing element characteristics. the lsm303dlm features two data-ready signals (rdy) which indicate when a new set of measured acceleration data and magnetic data are available, therefore simplifying data synchronization in the digital system that uses the device. the lsm303dlm may also be configured to generate an inertial wakeup and free-fall interrupt signal according to a programmed acceleration event along the enabled axes. both free-fall and wakeup can be used simultaneously on two different accelerometer interrupts. 5.1 factory calibration the ic interface is factory calibrated for linea r acceleration sensitiv ity (la_so), and linear acceleration zero- g level (la_tyoff). the trimming values are stored inside the device in non-volatile memory. when the device is turned on, the trimming parameters are downloaded into the registers to be used during normal operation. this allows the use of the device without further calibration.
lsm303dlm application hints doc id 018725 rev 1 15/38 6 application hints figure 4. lsm303dlm electrical connection - recommended for i 2 c fast mode 6.1 external capacitors the c1 and c2 external capacitors should have a low sr value ceramic type construction. reservoir capacitor c1 is nominally 4.7 f in capacitance, with the set/reset capacitor c2 nominally 0.22 f in capacitance. the device core is supplied through the vdd line. power supply decoupling capacitors (c4=100 nf ceramic, c3=10 f al) should be placed as near as possible to the supply pin of the device (common design practice). all the voltage and ground supplies must be present at the same time to obtain proper behavior of the ic (refer to figure 4 ). the functionality of the device and the measured acceleration/magnetic field data is selectable and accessible through the i 2 c interface. the functions, the threshold, and the timing of the two interrupt pins (int 1 and int 2) can be completely programmed by the user through the i 2 c interface. direction s of detectable magnetic field s direction s of detectable acceleration s re s s cl_a re s gnd (top view) re s 4 1 8 re s s da_a int1 int2 vdd_io re s vdd s da_m nc s cl_m s et1 re s drdy_m l s m 3 0 3 dlm s a0 re s 1 7 2 8 22 21 15 c1 c2=0.22 u f gnd c1=4.7 u f vdd_io vdd c4 = 100 u f c 3 = 10 u f y x z 1 y x z 1 nc gnd s et2 re s re s re s vdd_io rp u electrical connection rp u =10kohm re s vdd_io rp u rp u =10kohm am09240v1
application hints lsm303dlm 16/38 doc id 018725 rev 1 6.2 soldering information the lga package is compliant with the ecopack ? , rohs and ?green? standard. it is qualified for soldering heat resist ance according to jedec j-std-020. leave ?pin 1 indicator? unconnected during soldering. land pattern and soldering recommendations are available at www.st.com . 6.3 high current wiring effects high current in the wiring and printed circuit traces can be the cause of errors in magnetic field measurements for compassing. conductor-generated magnetic fields add to t he earth?s magnetic field, creating errors in compass heading computation. keep currents that are higher than 10 ma a fe w millimeters further away from the sensor ic.
lsm303dlm digital interfaces doc id 018725 rev 1 17/38 7 digital interfaces the registers embedded inside the lsm303dlm are accessible through two separate i 2 c serial interfaces; one for the accelerometer core and the other for the magnetometer core. the two interfaces can be connected together on the pcb. 7.1 i 2 c serial interface the lsm303dlm i 2 c is a bus slave. the i 2 c is employed to write the data into the registers whose content can also be read back. the relevant i 2 c terminology is given in the table below. there are two signals associated with the i 2 c bus; the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving the data to/from the interface. table 7. serial interface pin description pin name pin description scl_a i 2 c serial clock (scl) for accelerometer sda_a i 2 c serial data (sda) for accelerometer scl_m i 2 c serial clock (scl) for magnetometer sda_m i 2 c serial data (sda) for magnetometer table 8. serial interface pin description term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals, and terminates a transfer slave the device addressed by the master
digital interfaces lsm303dlm 18/38 doc id 018725 rev 1 7.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high to low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the 8 th bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. the i 2 c embedded inside the lsm303dlm behaves like a slave device and the following protocol must be adhered to. after the start condition (st) a slave address is sent. once a slave acknowledge (sak) has been returned, an 8-bit sub-a ddress (sub) is transmitted; the 7 lsbs represent the actual register address while the msb enables address auto- increment. if the msb of the sub field is ?1?, the sub (register address) is automatically increased to allow multiple data read/write. data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver cannot receive another complete byte of data until it has performed some other function, it can hold the clock line scl low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver does not acknowledge the slave address (i.e. it is not able to receive because it is performing a real-time function) the data line must be left high by the slave. the master can then abort the transfer. a low to high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. table 9. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak table 10. transfer when master is writing multiple bytes to slave master st sad + w sub data data sp slave sak sak sak sak table 11. transfer when master is receiving (reading) one byte of data from slave master st sad + w sub sr sad + r nmak sp slave sak sak sak data
lsm303dlm digital interfaces doc id 018725 rev 1 19/38 7.1.2 linear accelera tion digital interface for linear acceleration, the default (factory) 7-bit slave address is 001100xb. the sdo/sa0 pad can be used to modify the least significan t bit of the device address. if the sa0 pad is connected to voltage supply, the lsb is ?1? (address 0011001b) otherwise, if the sa0 pad is connected to ground, the lsb value is ?0? (address 0011000b). this solution permits connecting and addressing two different accelerometers to the same i 2 c lines. the slave address is completed with a read/write bit. if the bit is ?1? (read), a repeated start (sr) condition must be issued after the two sub-address bytes; if the bit is ?0? (write), the master transmits to the slave with the direction unchanged. table 12 explains how the sad+read/write bit pattern is composed, listing all the possible configurations. in order to read multiple bytes, it is necessary to assert the most significant bit of the sub- address field. in other words, sub(7) must be equal to 1 while sub(6-0) represents the address of the first register to be read. in the presented communication format, mak is master acknowledge and nmak is no master acknowledge. 7.1.3 magnetic fiel d digital interface for magnetic sensors the default (factory) 7-bit slave address is 0011110xb. the slave address is completed with a read/write bit. if the bit is ?1? (read), a repeated start (sr) condition must be issued after the two sub-address bytes; if the bit is ?0? (write), the master transmits to the slave with the direction unchanged. table 14 explains how the sad is composed. table 12. sad and read/write patterns command sad[6:1] sad[0] = sa0 r/w sad+r/w read 001100 0 1 00110001 (31h) write 001100 0 0 00110000 (30h) read 001100 1 1 00110011 (33h) write 001100 1 0 00110010 (32h) table 13. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data data data table 14. sad and read/write patterns command sad[6:0] r/w sad+r/w read 0011110 1 00111101 (3dh) write 0011110 0 00111100 (3ch)
digital interfaces lsm303dlm 20/38 doc id 018725 rev 1 magnetic signal interface reading/writing the interface uses an address pointer to indicate which register location is to be read from or written to. these pointer locations are sent from the master to this slave device and succeed the 7-bit address plus 1 bit read/write identifier. to minimize communication between the master and magnetic digital interface of lsm303dlm, the address pointer updates automatically without master intervention. this automatic address pointer update has two additional features. first, when address 12 or higher is accessed, the pointer updates to address 00, and secondly, when address 08 is reached, the pointer rolls back to address 03. logically, the address pointer operation functions as shown below. if (address pointer = 08) then the address pointer = 03 or else, if (address pointer >= 12) then the address pointer = 0 or else, (address pointer) = (address pointer) + 1 the address pointer value itself cannot be read via the i 2 c bus. any attempt to read an invalid address location returns 0, and any write to an invalid address location, or an undefined bit within a valid address location, is ignored by this device.
lsm303dlm register mapping doc id 018725 rev 1 21/38 8 register mapping table 15 provides a listing of the 8-bit registers embedded in the device and the related addresses: table 15. register address map name slave address type register address default comment hex binary reserved (do not modify) table 12 -- 00 - 1f -- -- reserved ctrl_reg1_a table 12 rw 20 010 0000 00000111 ctrl_reg2_a table 12 rw 21 010 0001 00000000 ctrl_reg3_a table 12 rw 22 010 0010 00000000 ctrl_reg4_a table 12 rw 23 010 0011 00000000 ctrl_reg5_a table 12 rw 24 010 0100 00000000 hp_filter_reset_a table 12 r 25 010 0101 -- dummy register reference_a table 12 rw 26 010 0110 00000000 status_reg_a table 12 r 27 010 0111 00000000 out_x_l_a table 12 r 28 010 1000 output out_x_h_a table 12 r 29 010 1001 output out_y_l_a table 12 r 2a 010 1010 output out_y_h_a table 12 r 2b 010 1011 output out_z_l_a table 12 r 2c 010 1100 output out_z_h_a table 12 r 2d 010 1101 output reserved (do not modify) table 12 -- 2e - 2f -- -- reserved int1_cfg_a table 12 rw 30 011 0000 00000000 int1_source_a table 12 r 31 011 0001 00000000 int1_ths_a table 12 rw 32 011 0010 00000000 int1_duration_a table 12 rw 33 011 0011 00000000 int2_cfg_a table 12 rw 34 011 0100 00000000 int2_source_a table 12 r 35 011 0101 00000000 int2_ths_a table 12 rw 36 011 0110 00000000 int2_duration_a table 12 rw 37 011 0111 00000000 reserved (do not modify) table 12 -- 38 - 3f -- -- reserved cra_reg_m table 14 rw 00 00000000 00010000 crb_reg_m table 14 rw 01 00000001 00100000 mr_reg_m table 14 rw 02 00000010 00000011
register mapping lsm303dlm 22/38 doc id 018725 rev 1 registers marked as ?reserved? must not be changed. writing to these registers may cause permanent damage to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory calibrated values. their content is automatically restored when the device is powered up. out_x_h_m table 14 r 03 00000011 output out_x_l_m table 14 r 04 00000100 output out_y_h_m table 14 r 07 00000101 output out_y_l_m table 14 r 08 00000110 output out_z_h_m table 14 r 05 00000111 output out_z_l_m table 14 r 06 00001000 output sr_reg_mg table 14 r 09 00001001 00000000 ira_reg_m table 14 r 0a 00001010 01001000 irb_reg_m table 14 r 0b 00001011 00110100 irc_reg_m table 14 r 0c 00001100 00110011 reserved (do not modify) table 14 -- 0d - 0e -- -- reserved who_am_i_m table 14 r 0f 00001111 00111100 who am i id reserved (do not modify) table 14 -- 10 - 3a -- -- reserved table 15. register address map (continued) name slave address type register address default comment hex binary
lsm303dlm register description doc id 018725 rev 1 23/38 9 register description the device contains a set of registers which are used to control its behavior and to retrieve acceleration data. the register address, made up of 7 bits, is used to identify them and to write the data through the serial interface. 9.1 linear acceleration register description 9.1.1 ctrl_reg1_a (20h) pm bits allow selection between power-down and two operating active modes. the device is in power-down mode when the pd bits are set to ?000? (default value after boot). table 18 shows all the possible power mode configurations and respective output data rates. output data in the low-power modes are computed with a low-pass filter cut-off frequency defined by dr1 and dr0 bits. dr bits, in normal-mode operation, select the data rate at which acceleration samples are produced. in low-power mode they define the output data resolution. table 19 shows all the possible configurations for the dr1 and dr0 bits. table 16. ctrl_reg1_a register pm2 pm1 pm0 dr1 dr0 zen yen xen table 17. ctrl_reg1_a description pm2 - pm0 power mode selection. default value: 000 (000: power-down; others: refer to table 18 ) dr1, dr0 data rate selection. default value: 00 (00:50 hz; others: refer to table 19 ) zen z axis enable. default value: 1 (0: z axis disabled; 1: z axis enabled) ye n y axis enable. default value: 1 (0: y axis disabled; 1: y axis enabled) xen x axis enable. default value: 1 (0: x axis disabled; 1: x axis enabled) table 18. power mode and low-power output data rate configurations pm2 pm1 pm0 power mode selection output data rate [hz] odr lp 0 0 0 power-down -- 0 0 1 normal mode odr 0 1 0 low-power 0.5
register description lsm303dlm 24/38 doc id 018725 rev 1 9.1.2 ctrl_reg2_a (21h) the boot bit is used to refresh the content of internal registers stored in the flash memory block. at device power-up, the content of the flash memory block is transferred to the internal registers related to trimming functions to permit good device behavior. if, for any 0 1 1 low-power 1 1 0 0 low-power 2 1 0 1 low-power 5 1 1 0 low-power 10 table 19. normal-mode output data rate configurations and low-pass cut-off frequencies dr1 dr0 output data rate [hz] odr low-pass filter cut-off frequency [hz] 00 50 37 01 100 74 1 0 400 292 1 1 1000 780 table 18. power mode and low-power output data rate configurations (continued) pm2 pm1 pm0 power mode selection output data rate [hz] odr lp table 20. ctrl_reg2_a register boot hpm1 hpm0 fds hpen2 hpen1 hpcf1 hpcf0 table 21. ctrl_reg2_a description boot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content) hpm1, hpm0 high-pass filter mode selection. default value: 00 (00: normal mode; others: refer to table 22 ) fds filtered data selection. default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register) hpen2 high-pass filter enabled for interrupt 2 source. default value: 0 (0: filter bypassed; 1: filter enabled) hpen1 high-pass filter enabled for interrupt 1 source. default value: 0 (0: filter bypassed; 1: filter enabled) hpcf1, hpcf0 high-pass filter cut-off frequency c onfiguration. default value: 00 (00: hpc=8; 01: hpc=16; 10: hpc=32; 11: hpc=64)
lsm303dlm register description doc id 018725 rev 1 25/38 reason, the content of the trimming registers has changed, it is sufficient to use this bit to restore the correct values. when the boot bit is set to ?1? the content of the internal flash is copied to the corresponding internal registers and is used to calibrate the device. these values are factory-trimmed and are different for every accelerometer. they permit good device behavior and normally do not have to be modified. at the end of the boot process, the boot bit is again set to ?0?. hpcf[1:0] . these bits are used to configure the high-pass filter cut-off frequency (f t) , which is given by: the equation can be simplified to the following approximated equation: 9.1.3 ctrl_reg3_a (22h) table 22. high-pass filter mode configuration hpm1 hpm0 high-pass filter mode 0 0 normal mode (reset reading hp_reset_filter) 0 1 reference signal for filtering 1 0 normal mode (reset reading hp_reset_filter) table 23. high-pass filter cut-off frequency configuration hpcoeff2,1 f t [hz] data rate = 50 hz f t [hz] data rate = 100 hz f t [hz] data rate = 400 hz f t [hz] data rate = 1000 hz 00 1 2 8 20 01 0.5 1 4 10 10 0.25 0.5 2 5 11 0.125 0.25 1 2.5 f t 1 1 hpc ----------- - ? ?? ?? f s 2 ------ ? ln = f t f s 6hpc ? ---------------------- = table 24. ctrl_reg3_a register ihl pp_od lir2 i2_cfg1 i2_cfg0 lir1 i1_cfg1 i1_cfg0 table 25. ctrl_reg3_a description ihl interrupt active high, low. default value: 0 (0: active high; 1: active low) pp_od push-pull/open drain selection on interrupt pad. default value 0. (0: push-pull; 1: open drain)
register description lsm303dlm 26/38 doc id 018725 rev 1 9.1.4 ctrl_reg4_a (23h) the bdu bit is used to inhibit output register updates between the reading of the upper and lower register parts. in default mode (bdu = ?0?), the lower and upper register parts are updated continuously. if it is not certain whether to read faster than the output data rate, it is recommended to set bdu bit to ?1?. in this way, after the reading of the lower (upper) register part, the content of that output register is not updated until the upper (lower) part is read also. this feature avoids reading lsb and msb related to different samples. lir2 latch interrupt request on int2_src register, with int2_src register cleared by reading int2_src itself. default value: 0. (0: interrupt request not latched; 1: interrupt request latched) i2_cfg1, i2_cfg0 data signal on int 2 pad control bits. default value: 00. (see table 26 ) lir1 latch interrupt request on int1_src register, with int1_src register cleared by reading int1_src register. default value: 0. (0: interrupt request not latched; 1: interrupt request latched) i1_cfg1, i1_cfg0 data signal on int 1 pad control bits. default value: 00. (see table 26 ) table 26. data signal on int 1 and int 2 pad i1(2)_cfg1 i1(2)_cfg0 int 1(2) pad 0 0 interrupt 1 (2) source 0 1 interrupt 1 source or interrupt 2 source 1 0 data ready 1 1 boot running table 25. ctrl_reg3_a description (continued) table 27. ctrl_reg4_a register bdu ble fs1 fs0 0 0 0 (1) 1. this bit must be set to ?0? for correct working of the device. --- table 28. ctrl_reg4_a description bdu block data update. default value: 0 (0: continuos update; 1: output register s not updated between msb and lsb reading) ble big/little endian data selection. default value 0. (0: data lsb @ lower address; 1: data msb @ lower address) fs1, fs0 full-scale selection. default value: 00. (00: 2 g ; 01: 4 g ; 11: 8 g )
lsm303dlm register description doc id 018725 rev 1 27/38 9.1.5 ctrl_reg5_a (24h) turnon bits are used for turning on the sleep-to-wakeup function. by setting the turnon [1:0] bits to 11, the ?sleep-to-wakeup? function is enabled. when an interrupt event occurs, the device goes into normal mode, increasing the odr to the value defined in ctrl_reg1_a. although the device is in normal mode, ctrl_reg1_a content is not automatically changed to ?normal mode? configuration. 9.1.6 hp_filter_reset_a (25h) dummy register. reading at this address instantaneously zeroes the content of the internal high-pass filter. if the high-pass filter is enabled, all three axes are instantaneously set to 0 g. this makes it possible to surmount the settling time of the high-pass filter. 9.1.7 reference_a (26h) this register sets the acceleration value taken as a reference for the high-pass filter output. when the filter is turned on (at least one fds, hpen2, or hpen1 bit is equal to ?1?) and hpm bits are set to ?01?, filter out is generated taking this value as a reference. table 29. ctrl_reg5_a register 000000turnon1turnon0 table 30. ctrl_reg5_a description tu r n o n 1 , tu r n o n 0 turn-on mode selection for sleep-to-wakeup function. default value: 00. table 31. sleep-to-wakeup configuration turnon1 turnon0 slee p-to-wakeup status 0 0 sleep-to-wakeup function is disabled 11 turned on: the device is in low-power mode (odr is defined in ctrl_reg1_a) table 32. reference_a register ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 table 33. reference_a description ref7 - ref0 reference value for high-pass filter. default value: 00h.
register description lsm303dlm 28/38 doc id 018725 rev 1 9.1.8 status_reg_a(27h) 9.1.9 out_x_l_a (28h ), out_x_h_a (29h) x-axis acceleration data. the value is expressed as 2?s complement. 9.1.10 out_y_l_a (2ah ), out_y_h_a (2bh) y-axis acceleration data. the value is expressed as 2?s complement. 9.1.11 out_z_l_a (2ch), out_z_h_a (2dh) z-axis acceleration data. the value is expressed as 2?s complement. 9.1.12 int1_cfg_a (30h) table 34. status_reg_a register zyxor zor yor xor zyxda zda yda xda table 35. status_reg_a description zyxor x, y, and z axis data overrun. default value: 0 (0: no overrun has occurred, 1: new da ta has overwritten the previous one) zor z axis data overrun. default value: 0 (0: no overrun has occurred, 1: new data fo r the z-axis has overwritten the previous one) yor y axis data overrun. default value: 0 (0: no overrun has occurred, 1: new data fo r the y-axis has overwritten the previous one) xor x axis data overrun. default value: 0 (0: no overrun has occurred, 1: new data fo r the x-axis has overwritten the previous one) zyxda x, y, and z axis new data available. default value: 0 (0: a new set of data is not yet available, 1: a new set of data is available) zda z axis new data available. default value: 0 (0: new data for the z-axis is not yet available, 1: new data for the z-axis is available) yda y axis new data available. default value: 0 (0: new data for the y-axis is not yet available, 1: new data for the y-axis is available) xda x axis new data available. default value: 0 (0: new data for the x-axis is not yet available, 1: new data for the x-axis is available) table 36. int1_cfg_a register aoi 6d zhie zlie yhie ylie xhie xlie
lsm303dlm register description doc id 018725 rev 1 29/38 configuration register for interrupt 1 source. 9.1.13 int1_src_a (31h) table 37. int1_cfg_a description aoi and/or combination of interrupt events. default value: 0 (see table 38 ). 6d 6-direction detection function enable. default value: 0 (see table 38 ). zhie enable interrupt generation on z high event. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value higher than preset threshold) zlie enable interrupt generation on z low event. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value lower than preset threshold) yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value lower than preset threshold) table 38. interrupt 1 source configurations aoi 6d interrupt mode 0 0 or combination of interrupt events 0 1 6-direction movement recognition 1 0 and combination of interrupt events 1 1 6-direction position recognition table 39. int1_src register 0 ia zhzlyhylxhxl
register description lsm303dlm 30/38 doc id 018725 rev 1 interrupt 1 source register. read-only register. reading at this address clears the int1_src_a ia bit (and the interrupt signal on the int 1 pin) and allows the refreshing of data in the int1_src_a register if the latched option was chosen. 9.1.14 int1_ths_a (32h) 9.1.15 int1_duration_a (33h) the d6 - d0 bits set the minimum duration of the interrupt 2 event to be recognized. duration steps and maximum values depend on the odr chosen. table 40. int1_src_a description ia interrupt active. default value: 0 (0: no interrupt has been generated, 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt, 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt, 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt, 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt, 1: y low event has occurred) xh x high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt, 1: x low event has occurred) table 41. int1_ths register 0 ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 42. int1_ths description ths6 - ths0 interrupt 1 threshold. default value: 000 0000 table 43. int1_duration_a register 0 d6d5d4d3d2d1d0 table 44. int2_duration_a description d6 - d0 duration value. default value: 000 0000
lsm303dlm register description doc id 018725 rev 1 31/38 9.1.16 int2_cfg_a (34h) configuration register for interrupt 2 source. table 45. int2_cfg_a register aoi 6d zhie zlie yhie ylie xhie xlie table 46. int2_cfg_a description aoi and/or combination of interrupt events. default value: 0 (see table 47 ). 6d 6-direction detection function enable. default value: 0 (see table 47 ). zhie enable interrupt generation on z high event. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value higher than preset threshold) zlie enable interrupt generation on z low event. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value lower than preset threshold) yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request, 1: enable interrupt request on measured accel. value lower than preset threshold) table 47. interrupt mode configuration aoi 6d interrupt mode 0 0 or combination of interrupt events 0 1 6-direction movement recognition 1 0 and combination of interrupt events 1 1 6-direction position recognition
register description lsm303dlm 32/38 doc id 018725 rev 1 9.1.17 int2_src_a (35h) interrupt 2 source register. read-only register. reading at this address clears the int2_src_a ia bit (and the interrupt signal on the int 2 pin) and allows the refreshing of data in the int2_src_a register if the latched option was chosen. 9.1.18 int2_ths_a (36h) 9.1.19 int2_duration_a (37h) table 48. int2_src_a register 0 ia zhzlyhylxhxl table 49. int2_src_a description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt, 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt; 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt, 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt, 1: y low event has occurred) xh x high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt, 1: x low event has occurred) table 50. int2_ths register 0 ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 51. int2_ths description ths6 - ths0 interrupt 1 threshold. default value: 000 0000 table 52. int2_duration_a register 0 d6d5d4d3d2d1d0
lsm303dlm register description doc id 018725 rev 1 33/38 the d6 - d0 bits set the minimum duration of the interrupt 2 event to be recognized. duration time steps and maximum values depend on the odr chosen. 9.2 magnetic field sensing register description 9.2.1 cra_reg_m (00h) 9.2.2 crb_reg_m (01h) table 53. int2_duration_a description d6 - d0 duration value. default value: 000 0000 table 54. cra_reg_m register 0 (1) 0 (1) 1. this bit must be set to ?0? for correct working of the device. 0 (1) do2 do1 do0 0 (1) 0 (1) table 55. cra_reg_m description do2 to do0 data output rate bits. these bits set the rate at which data is written to all three data output registers (refer to table 56 ). default value: 100 table 56. data rate configurations do2 do1 do0 minimum data output rate (hz) 00 0 0.75 00 1 1.5 01 0 3.0 01 1 7.5 10 0 15 10 1 30 11 0 75 1 1 1 220 table 57. cra_reg register gn2 gn1 gn0 0 (1) 1. this bit must be set to ?0? for correct working of the device. 0 (1) 0 (1) 0 (1) 0 (1) cra_reg description gn1-0 gain configuration bits. the gain configur ation is common for all channels (refer to table 58 )
register description lsm303dlm 34/38 doc id 018725 rev 1 9.2.3 mr_reg_m (02h) 9.2.4 out_x_h_m (03) , out_x_lh_m (04h) x-axis magnetic field data. the value is expressed as 2?s complement. 9.2.5 out_z_h_m (05), out_z_l_m (06h) z-axis magnetic field data. the val ue is expressed as 2?s complement. 9.2.6 out_y_h_m (0 7), out_y_l_m (08h) y-axis magnetic field data. the val ue is expressed as 2?s complement. table 58. gain setting gn2 gn1 gn0 sensor input field range [gauss] gain x/y and z [lsb/gauss] gain z [lsb/gauss] output range 0 0 1 1.3 1100 980 0xf800?0x07ff (-2048?2047) 010 1.9 855 760 011 2.5 670 600 100 4.0 450 400 101 4.7 400 355 110 5.6 330 295 111 8.1 230 205 table 59. mr_reg 0 (1) 1. this bit must be set to ?0? for correct working of the device 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) md1 md0 table 60. mr_reg description md1-0 mode select bits. these bits select the operation mode of this device (refer to table 61 ) table 61. magnetic sensor operating mode md1 md0 mode 0 0 continuous-conversion mode 0 1 single-conversion mode 1 0 sleep-mode. device is placed in sleep-mode 1 1 sleep-mode. device is placed in sleep-mode
lsm303dlm register description doc id 018725 rev 1 35/38 9.2.7 sr_reg_m (09h) 9.2.8 ir_reg_m (0ah/0bh/0ch) 9.2.9 who_am_i _m (0f) table 62. sr register -- -- -- -- -- -- lock drdy table 63. sr register description lock data output register lock. once a new se t of measurements is available, this bit is set when the first magnetic field data register has been read. drdy data ready bit. this bit is when a new set of measurements is available. table 64. ira_reg_m 01001000 table 65. irb_reg_m 00110100 table 66. irc_reg_m 00110011 table 67. who_am_i_m 00111100
package information lsm303dlm 36/38 doc id 018725 rev 1 10 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions, and product status are available at: www.st.com. ecopack is an st trademark. figure 5. lga-28: mechanical data and package dimensions dimensions ref. mm min. typ. max. a1 1 a2 0.785 a3 0.200 d1 4.850 5.000 5.150 e1 4.850 5.000 5.150 l1 1.650 l2 3.300 n1 0.550 m 0.040 0.100 0.160 t1 0.260 0.300 0.340 t2 0.360 0.400 0.440 d 0.200 k 0.050 h 0.100 lga-28 (5x5x1) land grid array packages outline and 8192208_b mechanical data
lsm303dlm revision history doc id 018725 rev 1 37/38 11 revision history table 68. document revision history date revision changes 11-apr-2011 1 initial release.
lsm303dlm 38/38 doc id 018725 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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