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w83176r-733 W83176G-733 winbond dual bank ddr buffer for via chipset date: mar/22/2006 revision: 1.0
dual bank ddr buffer for via chipset publication release date: march, 2006 - i - revision 1.0 w83176 r -733/W83176G-733 w83176r-733/W83176G-733 data sheet revision history pages dates version web version main contents 1 all of the versions before 0.50 are for internal use. 2 n.a. 09/09/03 0.5 n.a. first pub lished preliminary version. 3 3,4,5,8 12/18/03 0.6 n.a. correction ic version, correction some description and default value 4 03/22/2006 1.0 1.0 update on web and add lead free part 5 6 7 8 9 10 please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.
dual bank ddr buffer for via chipset - ii - w83176 r -733/W83176G-733 table of content- 1. general des cription ......................................................................................................... 1 2. product f eatures .............................................................................................................. 1 3. pin config uration .............................................................................................................. .1 4. block diagram .................................................................................................................. .... 2 5. pin descri ption................................................................................................................ ..... 3 5.1 clock function pins............................................................................................................ ......3 5.2 control signal pins............................................................................................................ .......3 6. power pins ..................................................................................................................... ........ 4 7. i2c control and stat us registers .............................................................................. 4 7.1 register 0 ~ register 5 reserved.......................................................................................4 7.2 register 6: output control (1 = enable, 0 = disable) (default: ffh)......................................4 7.3 register 7: output control (1 = enable, 0 = disable) (default: ffh)......................................4 7.4 register 8 ~ register 17 reserved ...............................................................................5 7.5 skew step reference table ...................................................................................................... 5 7.6 register 18: skew control (default: 88h) ................................................................................5 7.7 register 19: skew control (default: 80h) ................................................................................5 7.8 slew rate reference table ...................................................................................................... ...6 7.9 register 20: skew & slew rate control (default: 8ah) ..........................................................6 7.10 register 21: slew rate control (default: aah) .......................................................................6 7.11 register 22: slew rate control (default: aah) .......................................................................6 7.12 register 23: slew rate control (default: aah) .......................................................................7 8. access inte rface ............................................................................................................... .8 8.1 block write protocol ........................................................................................................... ......8 8.2 block read protocol............................................................................................................ .....8 8.3 byte write protocol............................................................................................................ .......8 8.4 byte read protocol ............................................................................................................. .....8 9. specificat ions ................................................................................................................. ..... 9 9.1 absolute maximum ratings .........................................................................................9 9.2 ac characteristics.........................................................................................................9 9.3 dc characteristics ........................................................................................................9 10. ordering info rmatio n..................................................................................................... 10 11. how to read the top marking...................................................................................... 10 12. package drawing an d dimens ions.............................................................................. 11
dual bank ddr buffer for via chipset publication release date: march, 2006 - 1 - revision 1.0 w83176 r -733/W83176G-733 1. general description the w83176r-733 is a 2.5v dual bank d.d.r. clock buffer designed for via system. w83176r-733 can support 4 d.d.r. dram dimms. the w83176r-733 provides i 2 c serial bus interface to program the registers to enable or disable each clock outputs. the w83176r-733 accepts a referenc e clock as its input and runs on 2.5v supply. 2. product features ? low skew outputs (< 100ps) ? two feedback pins for synchronous for each bank. ? supports up to 4 d.d.r. dimms ? supports pc3200 d. d.r. sdram ? i 2 c 2-wire serial interface and supports byte or block date rw ? 48-pin ssop package 3. pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vdd2.5 gnd fb_ou tb buf_inb ddrbt0 ddrbc0 ddrbt1 ddrbc1 gnd vdd2.5 ddrat0 ddrac0 ddrat1 ddrac1 gnd vdd2.5 fb_o uta bu f_ina ddrat2 ddrac2 ddrat3 ddrac3 vdd2.5 gnd vdd2.5 gnd oe_odd* oe_even* ddrbt2 ddrbc2 ddrbt3 ddrbc3 gnd vdd2.5 ddrat4 ddrac4 ddrat5 ddrac5 gnd vdd2.5 ddrbt4 ddrbc4 ddrbt5 ddrbc5 vdd2.5 gnd sdata* sclk* *: internal pull-up resistor 120k to vdd
dual bank ddr buffer for via chipset - 2 - w83176 r -733/W83176G-733 4. block diagram control logic fb_outa ddrat[5:0] ddrac[5:0] fb_outb ddrbt[5:0] ddrbc[5:0] sclk* sdata* buf_ina buf_inb oe_odd* oe_even*
dual bank ddr buffer for via chipset publication release date: march, 2006 - 3 - revision 1.0 w83176 r -733/W83176G-733 5. pin description buffer type symbol description in input out output i/od bi-directional pin, open drain * internal 120k ? pull-up 5.1 clock function pins pin pin name type description 18 buf_inta in bank a ddr buffer true reference clock input. 36,35,38,37,2 1,22,20,19,14 ,13,11,12 ddrat/c [5:0] out bank a ddr buffer clocks of differential pair outputs. 17 fb_outa out bank a ddr buffer true feedback output, dedicated for external feedback. 4 buf_intb in bank b ddr buffer true reference clock input. 30,29,32,31,42,4 1,44,43,7,8,5,6 ddrbt/c [5:0] out bank b ddr buffer clocks of differential pair outputs. 3 fb_outb out bank b ddr buffer true feedback output, dedicated for external feedback. 5.2 control signal pins pin pin name type description 26 sdata * i/od serial data of i 2 c 2-wire control interface internal pull-up resi stor 120k to vdd2.5 25 sclk * in serial clock of i 2 c 2-wire control interface internal pull-up resi stor 120k to vdd2.5 45 oe_even* in oe_even=1 enable, oe_even =0 disable, even buffer clock output pairs (ddr0, 2,4), internal pull-up resistor 120k to vdd2.5 46 oe_odd* in oe_odd=1 enable, oe_odd=0 disable, odd buffer clock output pairs (ddr1, 3, 5), internal pull-up resistor 120k to vdd2.5
dual bank ddr buffer for via chipset - 4 - w83176 r -733/W83176G-733 6. power pins pin pin name description 2,9,15,24,27,34,40,47 gnd ground 1,10,16,23,28,33,39,48 vdd2.5 power supply 2.5v 7. i2c control and status registers 7.1 register 0 ~ register 5 reserved 7.2 register 6: output control (1 = enable, 0 = disable) (default: ffh) bit pin no pwd description 7 reserved 1 reserved 6 17 1 fb_outa output control 5 36,35 1 ddra_t5/c5 output control 4 38,37 1 ddra_t4/c4 output control 3 21,22 1 ddra_t3/c3 output control 2 20,19 1 ddra_t2/c2 output control 1 13,14 1 ddra_t1/c1 output control 0 11,12 1 ddra_t0/c0 output control 7.3 register 7: output control (1 = enable, 0 = disable) (default: ffh) bit pin no pwd description 7 reserved 1 reserved 6 3 1 fb_outb output control 5 30,29 1 ddrb_t5/c5 output control 4 32,31 1 ddrb_t4/c4 output control 3 42,41 1 ddrb_t3/c3 output control 2 44,43 1 ddrb_t2/c2 output control 1 7,8 1 ddrb_t1/c1 output control 0 5,6 1 ddrb_t0/c0 output control
dual bank ddr buffer for via chipset publication release date: march, 2006 - 5 - revision 1.0 w83176 r -733/W83176G-733 7.4 register 8 ~ register 17 reserved 7.5 skew step reference table skew<2:0>/<1:0> delay time (ps) 000 0 001 250 010 500 011 750 100 1000 101 1250 110 1500 111 1750 7.6 register 18: skew control (default: 88h) bit name pwd description 7 reserved 1 reserved 6 ddra_tskew<2> 0 5 ddra_tskew<1> 0 4 ddra_tskew<0> 0 ddra true clock outputs wi th fb_outa true clock skew control bits 3 reserved 1 reserved 2 ddra_cskew<2> 0 1 ddra_cskew<1> 0 0 ddra_cskew<0> 0 ddra complementary clock outputs with fb_outa true clock skew control bits 7.7 register 19: skew control (default: 80h) bit name pwd description 7 reserved 1 reserved 6 ddrb_cskew<2> 0 5 ddrb_cskew<1> 0 4 ddrb_cskew<0> 0 ddrb complementary clock outputs with fb_outb true clock skew control bits 3 faout_skew<1> 0 2 faout_skew<0> 0 fb_outa, ddra clock outputs with buf_ina clock skew control bits 1 fbout_skew<1> 0 0 fbout_skew<0> 0 fb_outb, ddrb clock outputs with buf_inb clock skew control bits
dual bank ddr buffer for via chipset - 6 - w83176 r -733/W83176G-733 7.8 slew rate reference table sr<1:0> status 10/01 normal (default) 11 strong 00 weak 7.9 register 20: skew & slew rate control (default: 8ah) bit name pwd description 7 reserved 1 reserved 6 ddrb_tskew<2> 0 5 ddrb_tskew<1> 0 4 ddrb_tskew<0> 0 ddrb true clock outputs with fb_outb true clock skew control bits 3 ddrat/c0_sr<1> 1 2 ddrat/c0_sr<0> 0 ddrat/c0 slew rate control bits 1 ddrat/c1_sr<1> 1 0 ddrat/c1_sr<0> 0 ddrat/c1 slew rate control bits 7.10 register 21: slew rate control (default: aah) bit name pwd description 7 ddrat/c2_sr<1> 1 6 ddrat/c2_sr<0> 0 ddrat/c2 slew rate control bits 5 ddrat/c3_sr<1> 1 4 ddrat/c3_sr<0> 0 ddrat/c3 slew rate control bits 3 ddrat/c4_sr<1> 1 2 ddrat/c4_sr<0> 0 ddrat/c4 slew rate control bits 1 ddrat/c5_sr<1> 1 0 ddrat/c5_sr<0> 0 ddrat/c5 slew rate control bits 7.11 register 22: slew rate control (default: aah) bit name pwd description 7 ddrbt/c0_sr<1> 1 6 ddrbt/c0_sr<0> 0 ddrbt/c0 slew rate control bits 5 ddrbt/c1_sr<1> 1 4 ddrbt/c1_sr<0> 0 ddrbt/c1 slew rate control bits
dual bank ddr buffer for via chipset publication release date: march, 2006 - 7 - revision 1.0 w83176 r -733/W83176G-733 register 22: slew rate control (default: aah), continued bit name pwd description 3 ddrbt/c2_sr<1> 1 2 ddrbt/c2_sr<0> 0 ddrbt/c2 slew rate control bits 1 ddrbt/c3_sr<1> 1 0 ddrbt/c3_sr<0> 0 ddrbt/c3 slew rate control bits 7.12 register 23: slew rate control (default: aah) bit name pwd description 7 ddrbt/c4_sr<1> 1 6 ddrbt/c4_sr<0> 0 ddrbt/c4 slew rate control bits 5 ddrbt/c5_sr<1> 1 4 ddrbt/c5_sr<0> 0 ddrbt/c5 slew rate control bits 3 fbout_sr<1> 1 2 fbout_sr<0> 0 fb_outb slew rate control bits 1 faout_sr<1> 1 0 faout_sr<0> 0 fb_outa slew rate control bits
dual bank ddr buffer for via chipset - 8 - w83176 r -733/W83176G-733 8. access interface the w83176r-733 provides i 2 c serial bus for microprocessor to r ead/write internal registers. in the w83176r-733 is provided block read/block wr ite and byte-data read/write protocol. the i 2 c write address is defined at 0xd4. the i 2 c read address is defined at 0xd5. 8.1 block write protocol 8.2 block read protocol ## in block mode, the comm and code must filled ?00h? 8.3 byte write protocol 8.4 byte read protocol
dual bank ddr buffer for via chipset publication release date: march, 2006 - 9 - revision 1.0 w83176 r -733/W83176G-733 9. specifications 9.1 absolute maximum ratings stresses greater than those listed in this table may cause permanent damage to the device. precautions should be taken to avoid applicati on of any voltage higher than the maximum rated voltages to this circuit. maximum conditions fo r extended periods may affect reliability. unused inputs must always be tied to an appropriate logic voltage level (ground or vdd2.5). parameter rating voltage on any pin with respect to gnd - 0.5 v to + 3.6 v storage temperature - 65 c to + 150 c ambient temperature - 55 c to + 125 c operating temperature 0 c to + 70 c input esd protection (human body model) 2000v 9.2 ac characteristics vdd2.5 = 2.5v 5 %, t a = 0 c to +70 c, test load = 10 pf parameter symbol min typ max units test conditions operating clock frequency f in 100 200 mhz input clock duty cycle dtin 45 55 % dynamic supply current idd 200 ma fin=100 to 200mhz cycle to cycle jitter c-cjitter 200 ps fout=100 to 200mhz output to output skew tskew 100 ps fout=100 to 200mhz output clock rise time tor 650 950 ps fout=100 to 200mhz output clock fall time tof 650 950 ps fout=100 to 200mhz output clock duty cycle dtot 45 55 % fout=100 to 200mhz output differential-pair crossing voltage voc (vdd/2) -0.2 vdd/ 2 (vdd/2) + 0.2 v fout=100 to 200mhz 9.3 dc characteristics vdd2.5= 2.5v 5 %, t a = 0 c to +70 c parameter symbol min typ max units test conditions sdata, sclk input low voltage sv il 1.0 v dc sdata, sclk input high voltage sv ih 2.2 v dc buf_in input voltage low v il 0.4 v dc fin=100 to 200mhz buf_in input voltage high v ih 2.1 v dc fin=100 to 200mhz input pin capacitance c in 5 pf output pin capacitance c out 6 pf input pin inductance l in 7 nh
dual bank ddr buffer for via chipset - 10 - w83176 r -733/W83176G-733 10. ordering information part number package type production flow w83176r-733 48 pin ssop commercial, 0 c to +70 c W83176G-733 48 pin ssop(lead free part) commercial, 0 c to +70 c 11. how to read the top marking 1st line: winbond logo and the type number: normal:w83176r-733, lead free part: W83176G-733 2nd line: tracking code 2 8051234 2 : wafers manufactured in winbond fab 2 8051234 : wafer production series lot number 3rd line: tracking code 342 g e d sa 342 : packages made in '2003, week 42 g : assembly house id; o means ose, g means gr a : internal use code a : ic revision sa : internal use code all the trade marks of products and companies mentioned in this data sheet belong to their respective owners . w83176r-733 28051234 342 g a a sa W83176G-733 28051234 342 g a a sa
dual bank ddr buffer for via chipset publication release date: march, 2006 - 11 - revision 1.0 w83176 r -733/W83176G-733 12. package drawing and dimensions e e b y seating plane c l c l1 0 0.008 0.400 0.292 7.52 0 7.42 8 7.59 10.31 b e d c 18.2 9 10.16 a1 a2 a 10.41 18.54 18.42 2.79 2.34 8 0.299 0.296 0.092 0.110 0.410 0.720 0.730 0.725 0.406 min. dimension in inch symbol dimension in mm min. nom max. max. nom 0.20 e l l1 y 0.008 0.0135 0.005 0.010 0.024 0.032 0.055 0.003 0.20 0.34 0.13 0.25 0.51 0.76 0.64 0.020 0.030 0.025 0.61 0.81 1.40 0.08 h e 2.57 0.101 .045 .055 .035 .045 he 0.40/0.50 dia top view end view see detail "a" parting line side view d a1 a2 a detail"a" 0.095 0.012 0.016 0.088 0.090 0.010 0.040 2.41 0.30 0.41 2.24 2.29 0.25 1.02 please note that all data and specifications are subj ect to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surg ical implantation, at omic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c.

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