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1. general description the sc16c751b is a universal asynchronous receiver and transmitter (uart) used for serial data communications. its principal function is to convert parallel data into serial data, and vice versa. the uart can handle serial data rates up to 5 mbit/s. the sc16c751b is functionally equivalent to the sc16c750b, and requires a special software initialization sequence to con?gure the device to operate (see section 6.6 ). programming of control registers enables the added features of the sc16c751b. some of these added features are the 64-byte receive and transmit fifos, automatic hardware ?ow control. the selectable auto-?ow control feature signi?cantly reduces software overload and increases system ef?ciency while in fifo mode by automatically controlling serial data ?ow using r ts output and cts input signals. on-board status registers provide the user with error indications, operational status, and modem interface control. system interrupts may be tailored to meet user requirements. an internal loopback capability allows on-board diagnostics. the sc16c751b operates at 5 v, 3.3 v and 2.5 v, the industrial temperature range and is available in the plastic hvqfn24 package. 2. features n single channel n 5 v, 3.3 v and 2.5 v operation n 5 v tolerant on input only pins 1 n industrial temperature range ( - 40 c to +85 c) n after reset, all registers are identical to the typical 16c450 register set n capable of running with all existing generic 16c450 software n up to 5 mbit/s transmit/receive operation at 5 v, 3.3 v; 3 mbit/s at 2.5 v n 64-byte transmit fifo n 64-byte receive fifo with error ?ags n programmable auto- r ts and auto- cts u in auto- cts mode, cts controls transmitter u in auto- r ts mode, receive fifo contents and threshold control r ts n automatic hardware ?ow control n software selectable baud rate generator n four selectable receive interrupt trigger levels n standard modem interface n sleep mode sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos rev. 02 10 october 2008 product data sheet 1. for data bus pins d7 to d0, see t ab le 22 limiting v alues .
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 2 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos n standard asynchronous error and framing bits (start, stop, and parity overrun break) n independent receiver clock input n transmit, receive, line status, and data set interrupts independently controlled n fully programmable character formatting: u 5-bit, 6-bit, 7-bit, or 8-bit characters u even, odd, or no-parity formats u 1, 1 1 2 , or 2-stop bit u baud generation (dc to 5 mbit/s) n false start-bit detection n complete status reporting capabilities n 3-state output ttl drive capabilities for bidirectional data bus and control bus n line break generation and detection n internal diagnostic capabilities: u loopback controls for communications link fault isolation n prioritized interrupt system controls n modem control functions ( cts, r ts) 3. ordering information table 1. ordering information industrial: v dd = 2.5 v, 3.3 v or 5 v 10 %; t amb = - 40 c to +85 c. type number package name description version sc16c751bibs hvqfn24 plastic thermal enhanced very thin quad ?at package; no leads; 24 terminals; body 4 4 0.85 mm sot616-3
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 3 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos 4. block diagram 5. pinning information 5.1 pinning fig 1. block diagram of sc16c751b tx rx sc16c751b xtal2 xtal1 d0 to d7 ior, iow reset 002aad010 data b u s and control logic register select logic a0 to a2 cs interrupt control logic int clock and baud rate generator interconnect bus lines and control signals modem control logic rts cts receive shift register receive fifo registers flow control logic flow control logic transmit shift register transmit fifo registers fig 2. pin con?guration for hvqfn24 002aad011 sc16c751bibs transparent top view a1 tx cs a0 rx int d7 rts d6 reset d5 cts xtal1 xtal2 iow v ss ior a2 d4 d3 d2 d1 d0 v dd terminal 1 index area 6 13 5 14 4 15 3 16 2 17 1 18 7 8 9 10 11 12 24 23 22 21 20 19
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 4 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos 5.2 pin description table 2. pin description symbol pin type description a0 14 i register select. a0 to a2 are used during read and write operations to select the uart register to read from or write to. refer to t ab le 3 for register addresses. a1 13 i a2 12 i cs 6 i chip select. when cs is low, the uart is selected. cts 18 i clear to send. cts is a modem status signal. its condition can be checked by reading bit 4 (cts) of the modem status register (msr). msr[3] ( d cts) indicates that cts has changed states since the last read from the msr. if the modem status interrupt is enabled when cts changes levels and the auto- cts mode is not enabled, an interrupt is generated. cts is also used in the auto- cts mode to control the transmitter. d0 20 i/o data bus. eight data lines with 3-state outputs provide a bidirectional path for data, control and status information between the uart and the cpu. d1 21 i/o d2 22 i/o d3 23 i/o d4 24 i/o d5 1 i/o d6 2 i/o d7 3 i/o int 15 o interrupt. when active (high), int informs the cpu that the uart has an interrupt to be serviced. four conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed out (fifo mode only), an empty transmitter holding register or an enabled modem status interrupt. int is reset (deactivated) either when the interrupt is serviced or as a result of a master reset. reset 17 i master reset. when active (high), reset clears most uart registers and sets the levels of various output signals. ior 11 i read input. when ior is active (low) while the uart is selected, the cpu is allowed to read status information or data from a selected uart register. r ts 16 o request to send. when active, r ts informs the modem or data set that the uart is ready to receive data. r ts is set to the active level by setting the r ts modem control register bit and is set to the inactive (high) level either as a result of a master reset or during loopback mode operations or by clearing bit 1 ( r ts) of the mcr. in the auto- r ts mode, r ts is set to the inactive level by the receiver threshold control logic. rx 4 i serial data input. rx is serial data input from a connected communications device. tx 5 o serial data output. tx is composite serial data output to a connected communication device. tx is set to the marking (high) level as a result of master reset. v dd 19 power 2.5 v, 3 v or 5 v supply voltage. v ss [1] 10 power ground voltage.
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 5 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos [1] hvqfn24 package die supply ground is connected to both v ss pin and exposed center pad. v ss pin must be connected to supply ground for proper device operation. for enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the pcb in the thermal pad region. [2] in sleep mode, xtal2 is left ?oating. 6. functional description the sc16c751b provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. these functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol). data integrity is insured by attaching a parity bit to the data character. the parity bit is checked by the receiver for any transmission bit errors. the sc16c751b is fabricated with an advanced cmos process to achieve low drain power and high speed requirements. the sc16c751b is an upward solution that provides 64 bytes of transmit and receive fifo memory, instead of none in the 16c450, or 16 bytes in the 16c550. the sc16c751b is designed to work with high speed modems and shared network environments that require fast data processing time. increased performance is realized in the sc16c751b by the larger transmit and receive fifos. this allows the external processor to handle more networking tasks within a given time. in addition, the four selectable levels of fifo trigger interrupt and automatic hardware ?ow control is uniquely provided for maximum data throughput performance, especially when operating in a multi-channel environment. the combination of the above greatly reduces the bandwidth requirement of the external controlling cpu, increases performance, and reduces power consumption. the sc16c751b is capable of operation up to 5 mbit/s with an 80 mhz external clock input (at 5 v). the rich feature set of the sc16c751b is available through internal registers. automatic hardware ?ow control, selectable transmit and receive fifo trigger level, selectable tx and rx baud rates, modem interface controls, and a sleep mode are some of these features. 6.1 internal registers the sc16c751b provides 12 internal registers for monitoring and control. these registers are shown in t ab le 3 . these twelve registers are similar to those already available in the standard 16c550. these registers function as data holding registers (thr/rhr), interrupt io w9i write input. when io w is active (low) and while the uart is selected, the cpu is allowed to write control words or data into a selected uart register. xtal1 7 i crystal connection or external clock input. xtal2 [2] 8o crystal connection or the inversion of xtal1 if xtal1 is driven. table 2. pin description continued symbol pin type description
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 6 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos status and control registers (ier/isr), a fifo control register (fcr), line status and control registers (lcr/lsr), modem status and control registers (mcr/msr), programmable data rate (clock) control registers (dll/dlm), and a user accessible scratchpad register (spr). register functions are more fully described in the following paragraphs. [1] these registers are accessible only when lcr[7] is a logic 0. [2] these registers are accessible only when lcr[7] is a logic 1. 6.2 fifo operation the 64-byte transmit and receive data fifos are enabled by the fifo control register bit 0 (fcr[0]). the receiver fifo section includes a time-out function to ensure data is delivered to the external cpu. an interrupt is generated whenever the receive holding register (rhr) has not been read following the loading of a character or the receive trigger level has not been reached. table 3. internal registers decoding a2 a1 a0 read mode write mode general register set (thr/rhr, ier/isr, mcr/msr, fcr, lcr/lsr, spr) [1] 0 0 0 receive holding register transmit holding register 0 0 1 interrupt enable register interrupt enable register 0 1 0 interrupt status register fifo control register 0 1 1 line control register line control register 1 0 0 modem control register modem control register 1 0 1 line status register n/a 1 1 0 modem status register n/a 1 1 1 scratchpad register scratchpad register baud rate register set (dll/dlm) [2] 0 0 0 lsb of divisor latch lsb of divisor latch 0 0 1 msb of divisor latch msb of divisor latch table 4. flow control mechanism selected trigger level (characters) int pin activation negate r ts assert r ts 16-byte fifo 1110 4440 8880 14 14 14 0 64-byte fifo 1110 16 16 16 0 32 32 32 0 56 56 56 0
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 7 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos 6.3 hardware ?ow control when automatic hardware ?ow control is enabled, the sc16c751b monitors the cts pin for a remote buffer over?ow indication and controls the r ts pin for local buffer over?ows. automatic hardware ?ow control is selected by setting mcr[5] (rts) and mcr[1] (cts) to a logic 1. if cts transitions from a logic 0 to a logic 1 indicating a ?ow control request, the sc16c751b will suspend tx transmissions as soon as the stop bit of the character in process is shifted out. transmission is resumed after the cts input returns to a logic 0, indicating more data may be sent. with the auto- r ts function enabled, an interrupt is generated when the receive fifo reaches the programmed trigger level. the r ts pin will not be forced to a logic 1 (rts off), until the receive fifo reaches the next trigger level. however, the r ts pin will return to a logic 0 after the data buffer (fifo) is emptied. however, under the above described conditions, the sc16c751b will continue to accept data until the receive fifo is full. 6.4 time-out interrupts when two interrupt conditions have the same priority, it is important to service these interrupts correctly. receive data ready and receive time out have the same interrupt priority (when enabled by ier[0]). the receiver issues an interrupt after the number of characters have reached the programmed trigger level. in this case, the sc16c751b fifo may hold more characters than the programmed trigger level. following the removal of a data byte, the user should re-check lsr[0] for additional characters. a receive time out will not occur if the receive fifo is empty. the time-out counter is reset at the center of each stop bit received or each time the receive holding register (rhr) is read. the actual time-out value is 4 character time. 6.5 programmable baud rate generator the sc16c751b supports high speed modem technologies that have increased input data rates by employing data compression schemes. for example, a 33.6 kbit/s modem that employs data compression may require a 115.2 kbit/s input data rate. a 128.0 kbit/s isdn modem that supports data compression may need an input data rate of 460.8 kbit/s. a single baud rate generator is provided for the transmitter and receiver, allowing independent tx/rx channel control. the programmable baud rate generator is capable of accepting an input clock up to 80 mhz, as required for supporting a 5 mbit/s data rate. the sc16c751b can be con?gured for internal or external clock operation. for internal clock oscillator operation, an industry standard microprocessor crystal (parallel resonant, 22 pf to 33 pf load) is connected externally between the xtal1 and xtal2 pins (see figure 3 ). alternatively, an external clock can be connected to the xtal1 pin to clock the internal baud rate generator for standard or custom rates (see t ab le 5 ).
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 8 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos the generator divides the input 16 clock by any divisor from 1 to (2 16 - 1). customized baud rates can be achieved by selecting the proper divisor values for the msb and lsb sections of baud rate generator. programming the baud rate generator registers dlm (msb) and dll (lsb) provides a user capability for selecting the desired ?nal baud rate. the example in t ab le 5 shows selectable baud rates when using a 1.8432 mhz crystal. for custom baud rates, the divisor value can be calculated using equation 1 : (1) fig 3. crystal oscillator connection table 5. baud rates using 1.8432 mhz or 3.072 mhz crystal using 1.8432 mhz crystal using 3.072 mhz crystal desired baud rate divisor for 16 clock baud rate error desired baud rate divisor for 16 clock baud rate error 50 2304 50 3840 75 1536 75 2560 110 1047 0.026 110 1745 0.026 134.5 857 0.058 134.5 1428 0.034 150 768 150 1280 300 384 300 640 600 192 600 320 1200 96 1200 160 1800 64 1800 107 0.312 2000 58 0.69 2000 96 2400 48 2400 80 3600 32 3600 53 0.628 4800 24 4800 40 7200 16 7200 27 1.23 9600 12 9600 20 19200 6 19200 10 38400 3 38400 5 56000 2 2.86 002aaa870 c2 47 pf xtal1 xtal2 x1 1.8432 mhz c1 22 pf c2 33 pf xtal1 xtal2 1.5 k w x1 1.8432 mhz c1 22 pf divisor in decimal () xtal1 clock frequency serial data rate 16 ---------------------------------------------------------------- =
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 9 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos 6.6 special software initialization sequence upon reset, the sc16c751b will not be able to receive. a special software initialization sequence must be sent to the device to enable its receiver clock. the following software sequence can be added to the uart initialization routine, and this must be done before other registers are initialized. write lcr 00 write msr aa write msr 55 write msr cc write msr 33 write msr a5 write msr c3 write msr 5c write msr 3a write lsr 20 6.7 sleep mode the sc16c751b is designed to operate with low power consumption. a special sleep mode is included to further reduce power consumption (the internal oscillator driver is disabled) when the chip is not being used. with ier[4] enabled (set to a logic 1), the sc16c751b enters the sleep mode, but resumes normal operation when a start bit is detected, a change of state of rx, cts, or a transmit data is provided by the user. if the sleep mode is enabled and the sc16c751b is awakened by one of the conditions described above, it will return to the sleep mode automatically after the last character is transmitted or read by the user. in any case, the sleep mode will not be entered while an interrupt(s) is pending. the sc16c751b will stay in the sleep mode of operation until it is disabled by setting ier[4] to a logic 0. 6.8 low power mode in low power mode the oscillator is still running and only the clock to the uart core is cut off. this helps to reduce the operating current to about 1 3 . the uart wakes up under the same conditions as in sleep mode. 6.9 loopback mode the internal loopback capability allows on-board diagnostics. in the loopback mode, the normal modem interface pins are disconnected and recon?gured for loopback internally. mcr[3:0] register bits are used for controlling loopback diagnostic testing. the transmitter output (tx) and the receiver input (rx) are disconnected from their associated interface pins, and instead are connected together internally (see figure 4 ). the cts is disconnected from its normal modem control input pins, and instead is connected internally to r ts. loopback test data is entered into the transmit holding register via the user data bus interface, d0 to d7. the transmit uart serializes the data and passes the serial data to the receive uart via the internal loopback connection. the receive uart converts the serial data back into parallel data that is then made available at the user data interface d0 to d7. the user optionally compares the received data to the initial transmitted data for verifying error-free operation of the uart tx/rx circuits.
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 10 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos fig 4. internal loopback mode diagram sc16c751b xtal2 xtal1 d0 to d7 ior, iow reset 002aad012 data b u s and control logic register select logic a0 to a2 cs interrupt control logic int clock and baud rate generator interconnect bus lines and control signals modem control logic receive shift register receive fifo registers flow control logic flow control logic transmit shift register transmit fifo registers cts tx rx rts mcr[4] = 1
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 11 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos 7. register descriptions t ab le 6 details the assigned bit functions for the ?fteen sc16c751b internal registers. the assigned bit functions are more fully de?ned in section 7.1 through section 7.10 . [1] the value shown represents the registers initialized hex value; x = n/a. [2] these registers are accessible only when lcr[7] = 0. [3] do not write a logic 1 to the reserved bits. read of the reserved bits re?ect unknown values. [4] the special register set is accessible only when lcr[7] is set to a logic 1. table 6. sc16c751b internal registers a2 a1 a0 register default [1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 general register set [2] 0 0 0 rhr xx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 thr xx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 1 ier 00 0 0 low power mode sleep mode modem status interrupt receive line status interrupt transmit holding register receive holding register 0 1 0 fcr 00 rcvr trigger (msb) rcvr trigger (lsb) 64-byte fifo enable reserved [3] reserved [3] xmit fifo reset rcvr fifo reset fifo enable 0 1 0 isr 01 fifos enabled fifos enabled 64-byte fifo enable 0 int priority bit 2 int priority bit 1 int priority bit 0 int status 0 1 1 lcr 00 divisor latch enable set break set parity even parity parity enable stop bits word length bit 1 word length bit 0 1 0 0 mcr 00 0 0 ?ow control enable loopback reserved [3] reserved [3] r ts reserved [3] 1 0 1 lsr 60 fifo data error trans. empty trans. holding empty break interrupt framing error parity error overrun error receive data ready 1 1 0 msr x0 reserved reserved reserved cts reserved reserved reserved d cts 1 1 1 spr ff bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 special register set [4] 0 0 0 dll xx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 1 dlm xx bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 12 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos 7.1 transmit and receive holding registers (thr and rhr) the serial transmitter section consists of an 8-bit transmit hold register (thr) and transmit shift register (tsr). the status of the thr is provided in the line status register (lsr). writing to the thr transfers the contents of the data bus (d7 to d0) to the thr, providing that the thr or tsr is empty. the thr empty ?ag in the lsr register will be set to a logic 1 when the transmitter is empty or when data is transferred to the tsr. note that a write operation can be performed when the thr empty ?ag is set (logi c 0 = fifo full; logi c 1 = at least one fifo location available). the serial receive section also contains an 8-bit receive holding register (rhr). receive data is removed from the sc16c751b and receive fifo by reading the rhr register. the receive section provides a mechanism to prevent false starts. on the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16 clock rate. after 7 1 2 clocks, the start bit time should be shifted to the center of the start bit. at this time the start bit is sampled, and if it is still a logic 0 it is validated. evaluating the start bit in this manner prevents the receiver from assembling a false character. receiver status codes will be posted in the lsr. 7.2 interrupt enable register (ier) the interrupt enable register (ier) masks the interrupts from receiver ready, transmitter empty, line status and modem status registers. these interrupts would normally be seen on the int output pin. table 7. interrupt enable register bits description bit symbol description 7:6 ier[7:6] not used. 5 ier[5] low power mode. logic 0 = disable low power mode (normal default condition) logic 1 = enable low power mode 4 ier[4] sleep mode. logic 0 = disable sleep mode (normal default condition) logic 1 = enable sleep mode. see section 6.7 sleep mode for details. 3 ier[3] modem status interrupt. logic 0 = disable the modem status register interrupt (normal default condition) logic 1 = enable the modem status register interrupt 2 ier[2] receive line status interrupt. this interrupt will be issued whenever a fully assembled receive character is transferred from rsr to the rhr/fifo, i.e., data ready, lsr[0]. logic 0 = disable the receiver line status interrupt (normal default condition) logic 1 = enable the receiver line status interrupt 1 ier[1] transmit holding register interrupt. this interrupt will be issued whenever the thr is empty, and is associated with lsr[1]. logic 0 = disable the transmitter empty interrupt (normal default condition) logic 1 = enable the transmitter empty interrupt
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 13 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos 7.2.1 ier versus receive fifo interrupt mode operation when the receive fifo (fcr[0] = logic 1), and receive interrupts (ier[0] = logic 1) are enabled, the receive interrupts and register status will re?ect the following: ? the receive data available interrupts are issued to the external cpu when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. ? fifo status will also be re?ected in the user accessible isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared when the fifo drops below the trigger level. ? the data ready bit (lsr[0]) is set as soon as a character is transferred from the shift register to the receive fifo. it is reset when the fifo is empty. 7.2.2 ier versus receive/transmit fifo polled mode operation when fcr[0] = logic 1, resetting ier[3:0] enables the sc16c751b in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr, either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ? lsr[0] will be a logic 1 as long as there is one byte in the receive fifo. ? lsr[4:1] will provide the type of errors encountered, if any. ? lsr[5] will indicate when the transmit fifo is empty. ? lsr[6] will indicate when both the transmit fifo and transmit shift register are empty. ? lsr[7] will indicate any fifo data errors. 0 ier[0] receive holding register interrupt. this interrupt will be issued when the fifo has reached the programmed trigger level, or is cleared when the fifo drops below the trigger level in the fifo mode of operation. logic 0 = disable the receiver ready interrupt (normal default condition) logic 1 = enable the receiver ready interrupt table 7. interrupt enable register bits description continued bit symbol description
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 14 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos 7.3 fifo control register (fcr) this register is used to enable the fifos, clear the fifos and set the receive fifo trigger levels. 7.3.1 fifo mode table 8. fifo control register bits description bit symbol description 7:6 fcr[7] (msb), fcr[6] (lsb) rcvr trigger. these bits are used to set the trigger level for the receive fifo interrupt. an interrupt is generated when the number of characters in the fifo equals the programmed trigger level. however, the fifo will continue to be loaded until it is full. refer to t ab le 9 . 5 fcr[5] 64-byte fifo enable. logic 0 = 16-byte mode (normal default condition) logic 1 = 64-byte mode 4:3 fcr[4:3] reserved 2 fcr[2] xmit fifo reset. logic 0 = no fifo transmit reset (normal default condition) logic 1 = clears the contents of the transmit fifo and resets the fifo counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. 1 fcr[1] rcvr fifo reset. logic 0 = no fifo receive reset (normal default condition) logic 1 = clears the contents of the receive fifo and resets the fifo counter logic (the receive shift register is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. 0 fcr[0] fifo enable. logic 0 = disable the transmit and receive fifo (normal default condition) logic 1 = enable the transmit and receive fifo table 9. rcvr trigger levels fcr[7] fcr[6] rx fifo trigger level (bytes) 16-byte operation 64-byte operation 001 1 014 16 108 32 1114 56
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 15 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos 7.4 interrupt status register (isr) the sc16c751b provides four levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with four interrupt status bits. performing a read cycle on the isr will provide the user with the highest pending interrupt level to be serviced. no other interrupts are acknowledged until the pending interrupt is serviced. whenever the interrupt status register is read, the interrupt status is cleared. however, it should be noted that only the current pending interrupt is cleared by the read. a lower level interrupt may be seen after re-reading the interrupt status bits. t ab le 10 interr upt source shows the data values (bit 0 to bit 4) for the four prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels. table 10. interrupt source priority level isr[3] isr[2] isr[1] isr[0] source of the interrupt 1 0 1 1 0 lsr (receiver line status register) 2 0 1 0 0 rxrdy (received data ready) 2 1 1 0 0 rxrdy (receive data time-out) 3 0 0 1 0 txrdy (transmitter holding register empty) 4 0 0 0 0 msr (modem status register) table 11. interrupt status register bits description bit symbol description 7:6 isr[7:6] fifos enabled. these bits are set to a logic 0 when the fifo is not being used. they are set to a logic 1 when the fifos are enabled. logic 0 or cleared = default condition 5 isr[5] 64-byte fifo enable. logic 0 = 16-byte operation logic 1 = 64-byte operation 4 isr[4] not used 3:1 isr[3:1] int priority bit 2 to bit 0. these bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (see t ab le 10 ). logic 0 or cleared = default condition 0 isr[0] int status. logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine logic 1 = no interrupt pending (normal default condition)
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 16 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos 7.5 line control register (lcr) the line control register is used to specify the asynchronous data communication format. the word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. table 12. line control register bits description bit symbol description 7 lcr[7] divisor latch enable. the internal baud rate counter latch and enhanced feature mode enable. logic 0 = divisor latch disabled (normal default condition) logic 1 = divisor latch and enhanced feature register enabled 6 lcr[6] set break. when enabled, the break control bit causes a break condition to be transmitted (the tx output is forced to a logic 0 state). this condition exists until disabled by setting lcr[6] to a logic 0. logic 0 = no tx break condition (normal default condition) logic 1 = forces the transmitter output (tx) to a logic 0 for alerting the remote receiver to a line break condition 5 lcr[5] set parity. if the parity bit is enabled, lcr[5] selects the forced parity format. programs the parity conditions (see t ab le 13 ). logic 0 = parity is not forced (normal default condition) lcr[5] = logic 1 and lcr[4] = logic 0: parity bit is forced to a logic 1 for the transmit and receive data lcr[5] = logic 1 and lcr[4] = logic 1: parity bit is forced to a logic 0 for the transmit and receive data 4 lcr[4] even parity. if the parity bit is enabled with lcr[3] set to a logic 1, lcr[4] selects the even or odd parity format. logic 0 = odd parity is generated by forcing an odd number of logic 1s in the transmitted data. the receiver must be programmed to check the same format (normal default condition). logic 1 = even parity is generated by forcing an even number of logic 1s in the transmitted data. the receiver must be programmed to check the same format. 3 lcr[3] parity enable. parity or no parity can be selected via this bit. logic 0 = no parity (normal default condition) logic 1 = a parity bit is generated during the transmission, receiver checks the data and parity for transmission errors 2 lcr[2] stop bits. the length of stop bit is speci?ed by this bit in conjunction with the programmed word length (see t ab le 14 ). logic 0 or cleared = default condition 1:0 lcr[1:0] word length bit 1, bit 0. these two bits specify the word length to be transmitted or received (see t ab le 15 ). logic 0 or cleared = default condition
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 17 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos table 13. lcr[5] parity selection lcr[5] lcr[4] lcr[3] parity selection x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity 1 1 1 1 forced parity 0 table 14. lcr[2] stop bit length lcr[2] word length (bits) stop bit length (bit times) 0 5, 6, 7, 8 1 15 1 1 2 1 6, 7, 8 2 table 15. lcr[1:0] word length lcr[1] lcr[0] word length (bits) 005 016 107 118
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 18 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos 7.6 modem control register (mcr) this register controls the interface with the modem or a peripheral device. the ?ow control can be con?gured by programming mcr[1] and mcr[5] as shown in t ab le 17 . table 16. modem control register bits description bit symbol description 7 mcr[7] reserved; set to 0 6 mcr[6] reserved; set to 0 5 mcr[5] afe. this bit is the auto ?ow control enable. when this bit is set, the auto ?ow control is enabled. 4 mcr[4] loopback. enable the local loopback mode (diagnostics). in this mode the transmitter output (tx) and the receiver input (rx), cts are disconnected from the sc16c751b i/o pins. internally the modem data and control pins are connected into a loopback data con?guration (see figure 4 ). in this mode, the receiver and transmitter interrupts remain fully operational. the modem control interrupts are also operational, but the interrupts sources are switched to the lower four bits of the modem control. interrupts continue to be controlled by the ier register. logic 0 = disable loopback mode (normal default condition) logic 1 = enable local loopback mode (diagnostics) 3:2 mcr[3:2] reserved 1 mcr[1] r ts logic 0 = force r ts output to a logic 1 (normal default condition) logic 1 = force r ts output to a logic 0 0 mcr[0] reserved table 17. flow control con?guration mcr[5] (afe) mcr[1] ( r ts) flow con?guration 1 1 auto r ts and cts enabled 1 0 auto cts only enabled 0 x auto r ts and cts disabled
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 19 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos 7.7 line status register (lsr) this register provides the status of data transfers between the sc16c751b and the cpu. table 18. line status register bits description bit symbol description 7 lsr[7] fifo data error. logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error or break indication is in the current fifo data. this bit is cleared when lsr register is read. 6 lsr[6] thr and tsr empty. this bit is the transmit empty indicator. this bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. it is reset to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode, this bit is set to logic 1 whenever the transmit fifo and transmit shift register are both empty. 5 lsr[5] thr empty. this bit is the transmit holding register empty indicator. this bit indicates that the uart is ready to accept a new character for transmission. in addition, this bit causes the uart to issue an interrupt to cpu when the thr interrupt enable is set. the thr bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register. the bit is reset to a logic 0 concurrently with the loading of the transmitter holding register by the cpu. in the fifo mode, this bit is set when the transmit fifo is empty; it is cleared when at least 1 byte is written to the transmit fifo. 4 lsr[4] break interrupt. logic 0 = no break condition (normal default condition) logic 1 = the receiver received a break signal (rx was a logic 0 for one character frame time). in the fifo mode, only one break character is loaded into the fifo. 3 lsr[3] framing error. logic 0 = no framing error (normal default condition) logic 1 = framing error. the receive character did not have a valid stop bit(s). in the fifo mode, this error is associated with the character at the top of the fifo. 2 lsr[2] parity error. logic 0 = no parity error (normal default condition) logic 1 = parity error. the receive character does not have correct parity information and is suspect. in the fifo mode, this error is associated with the character at the top of the fifo. 1 lsr[1] overrun error. logic 0 = no overrun error (normal default condition) logic 1 = overrun error. a data overrun error occurred in the receive shift register. this happens when additional data arrives while the fifo is full. in this case, the previous data in the shift register is overwritten. note that under this condition, the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error. 0 lsr[0] receive data ready. logic 0 = no data in receive holding register or fifo (normal default condition) logic 1 = data has been received and is saved in the receive holding register or fifo
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 20 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos 7.8 modem status register (msr) this register provides the current state of the control interface signals from the modem, or other peripheral device to which the sc16c751b is connected. four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a control input from the modem changes state. these bits are set to a logic 0 whenever the cpu reads this register. [1] whenever any msr[0] is set to logic 1, a modem status interrupt will be generated if modem status interrupt is enabled. 7.9 scratchpad register (spr) the sc16c751b provides a temporary data register to store 8 bits of user information. 7.10 sc16c751b external reset conditions table 19. modem status register bits description bit symbol description 7:5 msr[7:5] reserved 4 msr[4] clear to send. cts. cts functions as hardware ?ow control signal input if it is enabled via mcr[5]. flow control (when enabled) allows starting and stopping the transmissions based on the external modem cts signal. a logic 1 at the cts pin will stop sc16c751b transmissions as soon as current character has ?nished transmission. normally msr[4] is the complement of the cts input. however, in the loopback mode, this bit is equivalent to the rts bit in the mcr register. 3:1 msr[3:1] reserved 0 msr[0] d cts [1] logic 0 = no cts change (normal default condition) logic 1 = the cts input to the sc16c751b has changed state since the last time it was read. a modem status interrupt will be generated. table 20. reset state for registers register reset state ier ier[7:0] = 0 isr isr[7:1] = 0; isr[0] = 1 lcr lcr[7:0] = 0 mcr mcr[7:0] = 0 lsr lsr[7] = 0; lsr[6:5] = 1; lsr[4:0] = 0 msr msr[7:4] = input signals; msr[3:0] = 0 fcr fcr[7:0] = 0 table 21. reset state for outputs output reset state tx high r ts high int low
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 21 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos 8. limiting values 9. static characteristics table 22. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage - 7 v v n voltage on any other pin at d7 to d0 pins v ss - 0.3 v dd + 0.3 v at any input only pin v ss - 0.3 5.3 v t amb ambient temperature operating - 40 +85 c t stg storage temperature - 65 +150 c p tot /pack total power dissipation per package - 500 mw table 23. static characteristics t amb = - 40 c to +85 c; tolerance of v dd = 10 %, unless otherwise speci?ed. symbol parameter conditions v dd = 2.5 v v dd = 3.3 v v dd = 5.0 v unit min max min max min max v il(clk) clock low-level input voltage - 0.3 0.45 - 0.3 0.6 - 0.5 0.6 v v ih(clk) clock high-level input voltage 1.8 v dd 2.4 v dd 3.0 v dd v v il low-level input voltage - 0.3 0.65 - 0.3 0.8 - 0.5 0.8 v v ih high-level input voltage 1.6 - 2.0 - 2.2 v dd v v ol low-level output voltage on all outputs [1] i ol =5ma (data bus) - 0.4 - 0.4 - 0.4 v i ol =4ma (other outputs) - 0.4 - 0.4 - 0.4 v i ol =2ma (data bus) - 0.4 - 0.4 - 0.4 v i ol = 1.6 ma (other outputs) - 0.4 - 0.4 - 0.4 v v oh high-level output voltage i oh = - 5ma (data bus) 1.85 - 2.0 - 2.0 - v i oh = - 1ma (other outputs) 1.85 - 2.0 - 2.0 - v i oh = - 800 m a (data bus) 1.85 - 2.0 - 2.0 - v i oh = - 400 m a (other outputs) 1.85 - 2.0 - 2.0 - v i lil low-level input leakage current - 10 - 10 - 10 m a i l(clk) clock leakage current - 30 - 30 - 30 m a i dd(av) average supply current - 3.5 - 4.5 - 4.5 ma i dd(sleep) sleep mode supply current [2] -50-50-50 m a i dd(lp) low-power mode supply current - 1.0 - 1.5 - 1.5 ma c i input capacitance - 5 - 5 - 5 pf r pu(int) internal pull-up resistance 500 - 500 - 500 - k w
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 22 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos [1] except for xtal2, v ol = 1 v typically. [2] sleep current might be higher if there is activity on the uart data bus during sleep mode. 10. dynamic characteristics table 24. dynamic characteristics t amb = - 40 c to +85 c; tolerance of v dd = 10 %, unless otherwise speci?ed. symbol parameter conditions v dd = 2.5 v v dd = 3.3 v v dd = 5.0 v unit min max min max min max t w2 pulse width low 10 -6-6-ns t w1 pulse width high 10 -6-6-ns f xtal1 frequency on pin xtal1 [1] -48-80-80mhz t 6s address set-up time 10 - 10 - 5 - ns t 7d ior delay from chip select 10 - 10 - 10 - ns t 7w ior strobe width 25 pf load 77 - 26 - 23 - ns t 7h chip select hold time from ior 0-0-0-ns t 7h address hold time 5-5-5-ns t 9d read cycle delay 25 pf load 20 - 20 - 20 - ns t 12d delay from ior to data 25 pf load - 77 - 26 - 23 ns t 12h data disable time 25 pf load - 15 - 15 - 15 ns t 13d io w delay from chip select 10 - 10 - 10 - ns t 13w io w strobe width 20 - 20 - 15 - ns t 13h chip select hold time from io w 0-0-0-ns t 14d io w delay from address 10 - 10 - 10 - ns t 15d write cycle delay 25 - 25 - 20 - ns t 16s data set-up time 20 - 20 - 15 - ns t 16h data hold time 15 -5-5-ns t 17d delay from io w to output 25 pf load - 100 - 33 - 29 ns t 18d delay to set interrupt from modem input 25 pf load - 100 - 24 - 23 ns t 19d delay to reset interrupt from ior 25 pf load; figure 7 - 100 - 24 - 23 ns t 20d delay from stop to set interrupt [2] -1t rclk -1t rclk -1t rclk s t 21d delay time ior to reset interrupt 25 pf load; figure 9 - 100 - 29 - 28 ns t 22d delay from start to set interrupt - 100 - 45 - 40 ns t 23d delay time from io w to transmit start [2] 8t rclk 24t rclk 8t rclk 24t rclk 8t rclk 24t rclk s t 24d delay from io w to reset interrupt - 100 - 45 - 40 ns t reset reset pulse width [3] 100-40-40-ns n baud rate divisor 1 2 16 - 112 16 - 112 16 - 1
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 23 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos [1] applies to external clock, crystal oscillator max 24 mhz. [2] rclk is an internal signal derived from divisor latch lsb (dll) and divisor latch msb (dlm) divisor latches. [3] reset pulse must happen when these signals are inactive: cs, ior, io w. 10.1 timing diagrams fig 5. general read timing 002aad015 t 6s' t 7h' t 7w t 9d t 12d t 12h a0 to a2 ior d0 to d7 t 7h' t 6s' t 7w t 12d t 12h valid address valid address active active active data cs t 7d fig 6. general write timing 002aad014 t 6s' t 7h' t 13w t 15d a0 to a2 iow d0 to d7 t 7h' t 6s' t 16s t 16h t 16s t 16h data active active active t 13w cs valid address valid address t 13d
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 24 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos fig 7. modem input/output timing t 17d change of state t 18d t 18d t 19d 002aad013 change of state change of state change of state active active active active active active active rts iow cts int ior fig 8. external clock timing external clock 002aaa112 t w3 t w2 t w1 f xtal1 1 t w3 ------- =
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 25 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos fig 9. receive timing d0 d1 d2 d3 d4 d5 d6 d7 active active 16 baud rate clock 002aaa113 rx int ior t 21d t 20d 5 data bits 6 data bits 7 data bits stop bit parity bit start bit data bits (0 to 7) next data start bit fig 10. transmit timing active transmitter ready active 16 baud rate clock 002aaa116 t 24d int iow active d0 d1 d2 d3 d4 d5 d6 d7 tx 5 data bits 6 data bits 7 data bits stop bit parity bit start bit data bits (0 to 7) next data start bit t 22d t 23d
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 26 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos 11. package outline fig 11. package outline sot616-3 (hvqfn24) 0.5 1 0.2 a 1 e h b unit y e references outline version european projection issue date iec jedec jeita mm 4.1 3.9 d h 2.75 2.45 y 1 4.1 3.9 2.75 2.45 e 1 2.5 e 2 2.5 0.30 0.18 c 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot616-3 mo-220 04-11-19 05-03-10 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot616-3 hvqfn24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 712 24 19 18 13 6 1 x d e c b a e 2 terminal 1 index area terminal 1 index area a c c b v m w m 1/2 e 1/2 e e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 27 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos 12. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 12.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 12.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 12.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 28 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos 12.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 12 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 25 and 26 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 12 . table 25. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 26. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 29 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 13. abbreviations msl: moisture sensitivity level fig 12. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 27. abbreviations acronym description brg baud rate generator cmos complementary metal-oxide semiconductor cpu central processing unit dll divisor latch lsb dlm divisor latch msb fifo first in, first out lsb least signi?cant bit msb most signi?cant bit ttl transistor-transistor logic uart universal asynchronous receiver and transmitter
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 30 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos 14. revision history table 28. revision history document id release date data sheet status change notice supersedes sc16c751b_2 20081010 product data sheet - sc16c751b_1 modi?cations: ? section 2 f eatures , 5 th bullet item re-written; added f ootnote 1 on page 1 ? section 7.3 fifo control register (fcr) ,1 st paragraph: removed phrase and select the dma mode ? t ab le 22 limiting v alues : C symbol v n split to show 2 separate conditions: at d7 to d0 pins and at input only pins sc16c751b_1 20080424 product data sheet - -
sc16c751b_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 10 october 2008 31 of 32 nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 15.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 15.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors sc16c751b 5 v, 3.3 v and 2.5 v uart with 64-byte fifos ? nxp b.v. 2008. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 10 october 2008 document identifier: sc16c751b_2 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional description . . . . . . . . . . . . . . . . . . . 5 6.1 internal registers. . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 fifo operation . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.3 hardware ?ow control . . . . . . . . . . . . . . . . . . . . 7 6.4 time-out interrupts . . . . . . . . . . . . . . . . . . . . . . 7 6.5 programmable baud rate generator . . . . . . . . . 7 6.6 special software initialization sequence . . . . . . 9 6.7 sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.8 low power mode . . . . . . . . . . . . . . . . . . . . . . . 9 6.9 loopback mode . . . . . . . . . . . . . . . . . . . . . . . . 9 7 register descriptions . . . . . . . . . . . . . . . . . . . 11 7.1 transmit and receive holding registers (thr and rhr) . . . . . . . . . . . . . . . . . . . . . . . 12 7.2 interrupt enable register (ier) . . . . . . . . . . . 12 7.2.1 ier versus receive fifo interrupt mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.2.2 ier versus receive/transmit fifo polled mode operation . . . . . . . . . . . . . . . . . . 13 7.3 fifo control register (fcr) . . . . . . . . . . . . . 14 7.3.1 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.4 interrupt status register (isr) . . . . . . . . . . . . 15 7.5 line control register (lcr) . . . . . . . . . . . . . . 16 7.6 modem control register (mcr) . . . . . . . . . . . 18 7.7 line status register (lsr) . . . . . . . . . . . . . . . 19 7.8 modem status register (msr). . . . . . . . . . . . 20 7.9 scratchpad register (spr) . . . . . . . . . . . . . . 20 7.10 sc16c751b external reset conditions . . . . . . 20 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 21 9 static characteristics. . . . . . . . . . . . . . . . . . . . 21 10 dynamic characteristics . . . . . . . . . . . . . . . . . 22 10.1 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 23 11 package outline . . . . . . . . . . . . . . . . . . . . . . . . 26 12 soldering of smd packages . . . . . . . . . . . . . . 27 12.1 introduction to soldering . . . . . . . . . . . . . . . . . 27 12.2 wave and re?ow soldering . . . . . . . . . . . . . . . 27 12.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 27 12.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 28 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 29 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 30 15 legal information . . . . . . . . . . . . . . . . . . . . . . 31 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 31 15.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 15.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 31 15.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 31 16 contact information . . . . . . . . . . . . . . . . . . . . 31 17 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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