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i 2 c is a licensed trademark of philips electronics, n.v. american microsystems, inc., reserves the right to change the detail spe cifications as may be required to permit improvements in the design of its products. FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic 1.0 features ? just-in-time customization of clock frequencies via internal non-volatile 128-bit serial eeprom ? i 2 c -bus serial interface ? three on-chip plls with programmable reference and feedback dividers ? four independently programmable muxes and post dividers ? programmable power-down of all plls and output clock drivers ? tristate outputs for board testing ? one pll and two mux/post-divider combinations can be modified via sel_cd input ? 5v to 3.3v operation ? accepts 5mhz to 27mhz crystal resonators ? rom-based device available for cost reduction mi- gration path ? contact your ami sales representative for more information 2.0 description the fs6370 is a cmos clock generator ic designed to minimize cost and component count in a variety of elec- tronic systems. three eeprom-programmable phase- locked loops (plls) driving four programmable muxes and post dividers provide a high degree of flexibility. an internal eeprom permits just-in-time factory pro- gramming of devices for end user requirements. figure 1: pin configuration 1 16 2 3 4 5 6 7 8 15 14 13 12 11 10 9 vss sel_cd pd/scl vss xin xout oe/sda vdd mode clk_d vss clk_c clk_b vdd clk_a vdd fs6370 16-pin (0.150?) soic figure 2: block diagram i 2 c-bus interface eeprom power down control post divider c post divider b fs6370 pd/scl oe/sda post divider a clk_a clk_b clk_c reference oscillator pll a pll b mode xout xin mux b mux c pll c post divider d clk_d mux d mux a sel_cd
2 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic table 1: pin descriptions key: ai = analog input; ao = analog output; di = digital input; di u = input with internal pull-up; di d = input with internal pull-down; dio = digital input/output; di-3 = three-level digital input, do = digital output; p = power/ground; # = active low pin pin type name description 1 p vss ground 2di u sel_cd selects one of two programmed pll c, mux c/d, and post divider c/d combinations 3di u pd/scl power-down input (run mode) or serial interface clock input (program mode) 4 p vss ground 5 ai xin crystal oscillator feedback 6 ao xout crystal oscillator drive 7di u o oe/sda output enable input (run mode) or serial interface data input/output (program mode) 8 p vdd power supply (5v to 3.3v) 9di u mode selects either program mode (low) or run mode (high) 10 do clk_d d clock output 11 p vss ground 12 do clk_c c clock output 13 do clk_b b clock output 14 p vdd power supply (5v to 3.3v) 15 do clk_a a clock output 16 p vdd power supply (5v to 3.3v) 3.0 functional block description 3.1 phase locked loops each of the three on-chip phase-locked loops (plls) is a standard phase- and frequency-locked loop architecture that multiplies a reference frequency to a desired fre- quency by a ratio of integers. this frequency multiplica- tion is exact. as shown in figure 3, each pll consists of a reference divider, a phase-frequency detector (pfd), a charge pump, an internal loop filter, a voltage-controlled oscil- lator (vco), and a feedback divider. during operation, the reference frequency (f ref ), gener- ated by the on-board crystal oscillator, is first reduced by the reference divider. the divider value is often referred to as the modulus, and is denoted as n r for the refer- ence divider. the divided reference is fed into the pfd. the pfd controls the frequency of the vco (f vco ) through the charge pump and loop filter. the vco pro- vides a high-speed, low noise, continuously variable fre- quency clock source for the pll. the output of the vco is fed back to the pfd through the feedback divider (the modulus is denoted by n f ) to close the loop. figure 3: pll block diagram reference divider (n r ) phase- frequency detector charge pump up down feedback divider (n f ) loop filter refdiv[7:0] fbkdiv[10:0] lftc cp f ref f vco voltage controlled oscillator f pd
3 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic the pfd will drive the vco up or down in frequency until the divided reference frequency and the divided vco frequency appearing at the inputs of the pfd are equal. the input/output relationship between the reference fre- quency and the vco frequency is = r f ref vco n n f f . 3.1.1 reference divider the reference divider is designed for low phase jitter. the divider accepts the output of the reference oscillator and provides a divided-down frequency to the pfd. the reference divider is an 8-bit divider, and can be pro- grammed for any modulus from 1 to 255 by programming the equivalent binary value. a divide-by-256 can also be achieved by programming the eight bits to 00h. 3.1.2 feedback divider the feedback divider is based on a dual-modulus prescaler technique. the technique allows the same granularity as a fully programmable feedback divider, while still allowing the programmable portion to operate at low speed. a high-speed pre-divider (also called a prescaler) is placed between the vco and the program- mable feedback divider because of the high speeds at which the vco can operate. the dual-modulus technique insures reliable operation at any speed that the vco can achieve and reduces the overall power consumption of the divider. for example, a fixed divide-by-eight prescaler could have been used in the feedback divider. unfortunately, a di- vide-by-eight would limit the effective modulus of the en- tire feedback divider to multiples of eight. this limitation would restrict the ability of the pll to achieve a desired input-frequency-to-output-frequency ratio without making both the reference and feedback divider values com- paratively large. generally, very large values are unde- sirable as they degrade the bandwidth of the pll, in- creasing phase jitter and acquisition time. to understand the operation of the feedback divider, refer to figure 4. the m-counter (with a modulus always equal to m) is cascaded with the dual-modulus prescaler. the a-counter controls the modulus of the prescaler. if the value programmed into the a-counter is a, the prescaler will be set to divide by n+1 for a prescaler outputs. thereafter, the prescaler divides by n until the m-counter output resets the a-counter, and the cycle begins again. note that n=8, and a and m are binary numbers. figure 4: feedback divider dual modulus prescaler a counter m counter f vco f pd fbkdiv[10:3] fbkdiv[2:0] suppose that the a-counter is programmed to zero. the modulus of the prescaler will always be fixed at n; and the entire modulus of the feedback divider becomes m n. next, suppose that the a-counter is programmed to a one. this causes the prescaler to switch to a divide-by- n+1 for its first divide cycle and then revert to a divide-by- n. in effect, the a-counter absorbs (or ?swallows?) one extra clock during the entire cycle of the feedback di- vider. the overall modulus is now seen to be equal to m n+1. this example can be extended to show that the feed- back divider modulus is equal to m n+a, where a m. 3.1.3 feedback divider programming for proper operation of the feedback divider, the a- counter must be programmed only for values that are less than or equal to the m-counter. therefore, not all divider moduli below 56 are available for use. this is shown in table 2. above a modulus of 56, the feedback divider can be programmed to any value up to 2047. table 2: feedback divider modulus under 56 a-counter: fbkdiv[2:0] m-counter: fbkdiv[10:3] 000 001 010 011 100 101 110 111 00000001 89------ 00000010 161718----- 00000011 24252627---- 00000100 32 33 34 35 36 - - - 00000101 40 41 42 43 44 45 - - 00000110 48 49 50 51 52 53 54 - 00000111 56 57 58 59 60 61 62 63 feedback divider modulus
4 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic 3.2 post divider muxes as shown in figure 2, a mux in front of each post divider stage can select from any one of the three pll frequen- cies or the reference frequency. the mux selection is controlled by bits in the eeprom or the control registers. the input frequency on two of the four multiplexers (muxes c and d in figure 2) can be altered without re- programming by a logic-level input on the sel_cd pin. 3.3 post dividers a post divider performs several useful functions. first, it allows the vco to be operated in a narrower range of speeds compared to the variety of output clock speeds that the device is required to generate. second, it changes the basic pll equation to = p r f ref clk n n n f f 1 where n p is the post divider modulus. the extra integer in the denominator permits more flexibility in the program- ming of the loop for many applications where frequencies must be achieved exactly. the modulus on two of the four post dividers (post divid- ers c and d in figure 2) can be altered without repro- gramming by a logic level on the sel_cd pin. 4.0 device operation the fs6370 has two modes of operation: program mode , during which either the eeprom or the fs6370 control registers can be programmed di- rectly with the desired pll settings, and run mode , where the pll settings stored the eeprom are transferred to the fs6370 control reg- isters on power-up, and the device then operates based on those settings. note that the eeprom locations are not physically the same registers used to control the fs6370. direct access to either the eeprom or the fs6370 con- trol registers is achieved in program mode. the eeprom register contents are automatically transferred to the fs6370 control registers in normal device opera- tion (run mode). 4.1 mode pin the mode pin controls the mode of operation. a logic- low places the fs6370 in program mode. a logic-high puts the device in run mode. a pull-up on this pin de- faults the device into run mode. reprogramming of either the control registers or the eeprom is permitted at any time if the mode pin is a logic-low. note, however, that a logic-high state on the mode pin is latched so that only one transfer of eeprom data to the fs6370 control registers can occur. if a second transfer of eeprom data into the fs6370 is desired, power (vdd) must be removed and reapplied to the device. the mode pin also controls the function of the pd/scl and oe/sda pins. in run mode, these two pins function as power-down (pd) and output enable (oe) controls. in program mode, the pins function as the i 2 c interface for clock (scl) and data (sda). 4.2 sel_cd pin the sel_cd pin provides a way to alter the operation of pll c, muxes c and d, and post dividers c and d with- out having to reprogram the device. a logic-low on the sel_cd pin selects the control bits with a ?c1? or ?d1? notation, per table 3. a logic-high on the sel_cd pin selects the control bits with ?c2? or ?d2? notation, per table 3. note that changing between two running frequencies us- ing the sel_cd pin may produce glitches in the output, especially if the post-divider(s) is/are altered. 4.3 oscillator overdrive for applications where an external reference clock is provided (and the crystal oscillator is not required), the reference clock should be connected to xout and xin must be left unconnected (float). for best results, make sure the reference clock signal is as jitter-free as possible, can drive a 40pf load with fast rise and fall times, and can swing rail-to-rail. if the reference clock is not a rail-to-rail signal, the refer- ence must be ac coupled to xout through a 0.01f or 0.1f capacitor. a minimum 1v peak-to-peak signal is required to drive the internal differential oscillator buffer.
5 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic 5.0 run mode if the mode pin is set to a logic-high, the device enters the run mode. the high state is latched (see mode pin). the fs6370 then copies the stored eeprom data into its control registers and begins normal operation based on that data when the self-load is complete. the self-load process takes about 89,000 clocks of the crystal oscillator. during the self-load time, all clock out- puts are held low. at a reference frequency of 27mhz, the self-load takes about 3.3ms to complete. if the eeprom is empty (all zeros), the crystal reference frequency provides the clock for all four outputs. no external programming access to the fs6370 is possi- ble in run mode. the dual-function pd/scl and oe/sda pins become a power-down (pd) and output enable (oe) control, respectively. 5.1 power-down and output enable a logic-high on the pd/scl pin powers down only those portions of the fs6370 which have their respective power-down control bits enabled. note that the pd/scl pin has an internal pull-up. when a post divider is powered down, the associated output driver is forced low. when all plls and post di- viders are powered down the crystal oscillator is also powered down. the xin pin is forced low, and the xout pin is pulled high. a logic-low on the oe/sda pin tristates all output clocks. note that this pin has an internal pull-up. 6.0 program mode if the mode pin is logic-low, the device enters the pro- gram mode. all internal registers are cleared to zero, de- livering the crystal frequency to all outputs. the device allows programming of either the internal 128-bit eeprom or the on-chip control registers via i 2 c control over the pd/scl and oe/sda pins. the eeprom and the fs6370 act as two separate parallel devices on the same on-chip i 2 c-bus. choosing either the eeprom or the device control registers is done via the i 2 c device address. the dual-function pd/scl and oe/sda pins become the serial data i/o (sda) and serial clock input (scl) for normal i 2 c communications. note that power-down and output enable control via the pd/scl and oe/sda pins is not available. 6.1 eeprom programming data must be loaded into the eeprom in a most- significant-bit (msb) to least-significant-bit (lsb) order. the register map of the eeprom is noted in table 3. the device address of the eeprom is: a6 a5 a4 a3 a2 a1 a0 1010xxx 6.1.1 write operation the eeprom can only be written to with the random register write procedure (see page 8). the procedure consists of the device address, the register address, a r/w bit, and one byte of data. following the stop condition, the eeprom initiates its internally timed 4ms write cycle, and commits the data byte to memory. no acknowledge signals are generated during the eeprom internal write cycle. if a stop bit is transmitted before the entire write com- mand sequence is complete, then the command is aborted and no data is written to memory. if more than eight bits are transmitted before the stop bit is sent, then the eeprom will clear the previously loaded data byte and will begin loading the data buffer again. 6.1.2 acknowledge polling the eeprom does not acknowledge while it internally commits data to memory. this feature can be used to increase data throughput by determining when the inter- nal write cycle is complete. the process is to initiate the random register write pro- cedure with a start condition, the eeprom device address, and the write command bit (r/w=0). if the eeprom has completed its internal 4ms write cycle, the eeprom will acknowledge on the next clock, and the write command can continue. if the eeprom has not completed the internal 4ms write cycle, the random register write procedure must be restarted by sending the start condition, device ad- dress, and r/w bit. this sequence must be repeated until the eeprom acknowledges. 6.1.3 read operation the eeprom supports both the random register read procedure and the sequential register read procedure (both are outlined on page 8).
6 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic for sequential read operations, the eeprom has an in- ternal address pointer that increments by one at the end of each read operation. the pointer directs the eeprom to transmit the next sequentially addressed data byte, allowing the entire memory contents to be read in one operation. 6.2 direct register programming the fs6370 control registers may be directly accessed by simply using the fs6370 device address in the read or write operations. the operation of the device will follow the register values. the register map of the fs6370 is identical to that of the eeprom shown in table 3. the fs6370 supports the random read and write pro- cedures, as well as the sequential read and write pro- cedures described on page 7. the device address for the fs6370 is: a6 a5 a4 a3 a2 a1 a0 1011100 7.0 cost reduction migration path the fs6370 is compatible with the programmable regis- ter-based fs6377 or a fixed-frequency rom-based clock generator. attention should be paid to the board layout if a migration path to either of these devices is desired. 7.1 programming migration path if the design can support i 2 c programming overhead, a cost reduction from the eeprom-based fs6370 to the register-based fs6377 is possible. figure 5 shows the five pins that may not be compatible between the various devices if programming of the fs6370 or the fs6377 is desired. figure 5: fs6370 to fs6377 1 16 2 3 4 5 6 7 8 15 14 13 12 11 10 9 vss ( fs6370 ) sel_cd vss xin xout vdd clk_d vss clk_c clk_b vdd clk_a fs6370 / fs6377 sda ( fs6377 ) pd/scl ( fs6370 ) pd ( fs6377) oe/sda ( fs6370 ) oe ( fs6377) mode ( fs6370 ) addr ( fs6377 ) vdd ( fs6370 ) scl ( fs6377 ) 7.2 non-programming migration path if the design has solidified on a particular eeprom pro- gramming pattern, the eeprom pattern can be hard- coded into a rom-based device. for high-volume re- quirements, a rom-based device offers significant cost savings over the fs6370. contact an ami sales repre- sentative for more detail.
7 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic 8.0 i 2 c-bus control interface this device is a read/write slave device meeting all philips i 2 c-bus specifications except a ?general call.? the bus has to be controlled by a master device that generates the serial clock scl, controls bus access, and generates the start and stop conditions while the device works as a slave. both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. a device that sends data onto the bus is defined as the transmitter, and a device re- ceiving data as the receiver. i 2 c-bus logic levels noted herein are based on a percent- age of the power supply (v dd ). a logic-one corresponds to a nominal voltage of v dd , while a logic-low corre- sponds to ground (v ss ). 8.1 bus conditions data transfer on the bus can only be initiated when the bus is not busy. during the data transfer, the data line (sda) must remain stable whenever the clock line (scl) is high. changes in the data line while the clock line is high will be interpreted by the device as a start or stop condition. the following bus conditions are defined by the i 2 c-bus protocol. 8.1.1 not busy both the data (sda) and clock (scl) lines remain high to indicate the bus is not busy. 8.1.2 start data transfer a high to low transition of the sda line while the scl in- put is high indicates a start condition. all commands to the device must be preceded by a start condition. 8.1.3 stop data transfer a low to high transition of the sda line while scl is held high indicates a stop condition. all commands to the device must be followed by a stop condition. 8.1.4 data valid the state of the sda line represents valid data if the sda line is stable for the duration of the high period of the scl line after a start condition occurs. the data on the sda line must be changed only during the low period of the scl signal. there is one clock pulse per data bit. each data transfer is initiated by a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions is determined by the master device, and can continue indefinitely. however, data that is overwritten to the de- vice after the first sixteen bytes will overflow into the first register, then the second, and so on, in a first-in, first- overwritten fashion. 8.1.5 acknowledge when addressed, the receiving device is required to gen- erate an acknowledge after each byte is received. the master device must generate an extra clock pulse to co- incide with the acknowledge bit. the acknowledging de- vice must pull the sda line low during the high period of the master acknowledge clock pulse. setup and hold times must be taken into account. the master must signal an end of data to the slave by not generating and acknowledge bit on the last byte that has been read (clocked) out of the slave. in this case, the slave must leave the sda line high to enable the master to generate a stop condition. 8.2 i 2 c-bus operation all programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital inter- face. the device accepts the following i 2 c-bus com- mands. 8.2.1 device address after generating a start condition, the bus master broadcasts a seven-bit device address followed by a r/w bit. the device address of the fs6370 is: a6 a5 a4 a3 a2 a1 a0 1011100 any one of eight possible addresses are available for the eeprom. the least significant three bits are don?t care?s. a6 a5 a4 a3 a2 a1 a0 1010xxx
8 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic 8.2.2 random register write procedure random write operations allow the master to directly write to any register. to initiate a write procedure, the r/w bit that is transmitted after the seven-bit device ad- dress is a logic-low. this indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. the register address is written into the slave?s address pointer. fol- lowing an acknowledge by the slave, the master is al- lowed to write eight bits of data into the addressed regis- ter. a final acknowledge is returned by the device, and the master generates a stop condition. if either a stop or a repeated start condition occurs during a register write, the data that has been trans- ferred is ignored. 8.2.3 random register read procedure random read operations allow the master to directly read from any register. to perform a read procedure, the r/w bit that is transmitted after the seven-bit address is a logic-low, as in the register write procedure. this indi- cates to the addressed slave device that a register ad- dress will follow after the slave device acknowledges its device address. the register address is then written into the slave?s address pointer. following an acknowledge by the slave, the master gen- erates a repeated start condition. the repeated start terminates the write procedure, but not until after the slave?s address pointer is set. the slave address is then resent, with the r/w bit set this time to a logic-high, indicating to the slave that data will be read. the slave will acknowledge the device address, and then transmits the eight-bit word. the master does not acknowledge the transfer but does generate a stop condition. 8.2.4 sequential register write procedure sequential write operations allow the master to write to each register in order. the register pointer is automati- cally incremented after each write. this procedure is more efficient than the random register write if several registers must be written. to initiate a write procedure, the r/w bit that is transmit- ted after the seven-bit device address is a logic-low. this indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. the register address is written into the slave?s address pointer. following an acknowledge by the slave, the master is allowed to write up to sixteen bytes of data into the addressed register before the register ad- dress pointer overflows back to the beginning address. an acknowledge by the device between each byte of data must occur before the next data byte is sent. registers are updated every time the device sends an acknowledge to the host. the register update does not wait for the stop condition to occur. registers are therefore updated at different times during a sequential register write. 8.2.5 sequential register read procedure sequential read operations allow the master to read from each register in order. the register pointer is automati- cally incremented by one after each read. this procedure is more efficient than the random register read if sev- eral registers must be read. to perform a read procedure, the r/w bit that is trans- mitted after the seven-bit address is a logic-low, as in the register write procedure. this indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. the reg- ister address is then written into the slave?s address pointer. following an acknowledge by the slave, the master gen- erates a repeated start condition. the repeated start terminates the write procedure, but not until after the slave?s address pointer is set. the slave address is then resent, with the r/w bit set this time to a logic-high, indicating to the slave that data will be read. the slave will acknowledge the device address, and then transmits all sixteen bytes of data starting with the initial addressed register. the register address pointer will overflow if the initial register address is larger than zero. after the last byte of data, the master does not acknowledge the transfer but does generate a stop condition.
9 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic figure 6: random register write procedure a a data w a from bus host to device s register address p from device to bus host device address register address acknowledge stop condition data acknowledge acknowledge start command write command 7-bit receive device address figure 7: random register read procedure a r a a a w s register address p s device address start command write command acknowledge register address acknowledge read command acknowledge data no acknowledge stop condition from bus host to device from device to bus host 7-bit receive device address 7-bit receive device address device address data repeat start figure 8: sequential register write procedure a a a w s p start command write command acknowledge register address acknowledge data data acknowledge data stop command acknowledge acknowledge from bus host to device from device to bus host 7-bit receive device address device address a a register address data data data figure 9: sequential register read procedure a w s start command write command acknowledge register address acknowledge data acknowledge data stop command acknowledge read command no acknowledge from bus host to device from device to bus host 7-bit receive device address 7-bit receive device address device address a a register address a r a p s device address data data repeat start
10 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic 9.0 programming information table 3: register map (note: all register bits are cleared to zero on power-up.) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 15 mux_d2[1:0] (selected via sel_cd = 1) mux_c2[1:0] (selected via sel_cd = 1) pdpost_d pdpost_c pdpost_b pdpost_a byte 14 post_d2[3:0] (selected via sel_cd = 1) post_c2[3:0] (selected via sel_cd = 1) byte 13 post_d1[3:0] (selected via sel_cd = 0) post_c1[3:0] (selected via sel_cd = 0) byte 12 post_b[3:0] post_a[3:0] byte 11 mux_d1[1:0] (selected via sel_cd = 0) reserved (0) lftc_c2 (sel_cd=1) cp_c2 (sel_cd=1) fbkdiv_c2[10:8] m-counte r (selected via sel_cd pin = 1) byte 10 fbkdiv_c2[7:3] m-counter (selected via sel_cd pin = 1) fbkdiv_c2[2:0] a-counter (selected via sel_cd pin = 1) byte 9 refdiv_c2[7:0] (selected via sel_cd pin = 1) byte 8 mux_c1[1:0] (selected via sel_cd = 0) pdpll_c lftc_c1 (sel_cd=0) cp_c1 (sel_cd=0) fbkdiv_c1[10:8] m-counter (selected via sel_cd = 0) byte 7 fbkdiv_c1[7:3] m-counter (selected via sel_cd = 0) fbkdiv_c1[2:0] a-counter (selected via sel_cd = 1) byte 6 refdiv_c1[7:0] (selected via sel_cd = 0) byte 5 mux_b[1:0] pdpll_b lftc_b cp_b fbkdiv_b[10:8] m-counte r byte 4 fbkdiv_b[7:3] m-counter fbkdiv_b[2:0] a-counter byte 3 refdiv_b[7:0] byte 2 mux_a[1:0] pdpll_a lftc_a cp_a fbkdiv_a[10:8] m-counte r byte 1 fbkdiv_a[7:3] m-counter fbkdiv_a[2:0] a-counter byte 0 refdiv_a[7:0] 9.1 control bit assignments if any pll control bit is altered during device operation, including those bits controlling the reference and feed- back dividers, the output frequency will slew smoothly (in a glitch-free manner) to the new frequency. the slew rate is related to the programmed loop filter time constant. however, any programming changes to any mux or post divider control bits will cause a glitch on an operating clock output. 9.1.1 power down all power-down functions are controlled by enable bits. that is, the bits select which portions of the fs6370 to power-down when the pd input is asserted. if the power- down bit contains a one, the related circuit will shut down if the pd pin is high (run mode only). when the pd pin is low, power is enabled to all circuits. if the power-down bit contains a zero, the related circuit will continue to function regardless of the pd pin state. table 4: power-down bits name description power-down pll a bit = 0 power on pdpll_a (bit 21) bit = 1 power off power-down pll b bit = 0 power on pdpll_b (bit 45) bit = 1 power off power-down pll c bit = 0 power on pdpll_c (bit 69) bit = 1 power off reserved (0) (bit 69) set these reserved bits to zero (0)
11 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic table 5: power-down bits, continued name description power-down post divider a bit = 0 power on pdpost_a (bit 120) bit = 1 power off power-down post divider b bit = 0 power on pdpost_b (bit 121) bit = 1 power off power-down post divider c bit = 0 power on pdpostc (bit 122) bit = 1 power off power-down post divider d bit = 0 power on pdpostd (bit 123) bit = 1 power off table 6: divider control bits name description refdiv_a[7:0] (bits 7-0) reference divider a (n r ) refdiv_b[7:0] (bits 31-24) reference divider b (n r ) refdiv_c1[7:0] (bits 55-48) reference divider c1 (n r ) selected when the sel_cd pin = 0 refdiv_c2[7:0] (bits 79-72) reference divider c2 (n r ) selected when the sel_cd pin = 1 feedback divider a (n f ) fbkdiv_a[2:0] a-counter value fbkdiv_a[10:0] (bits 18-8) fbkdiv_a[10:3] m-counter value feedback divider b (n f ) fbkdiv_b[2:0] a-counter value fbkdiv_b[10:0] (bits 42-32) fbkdiv_b[10:3] m-counter value feedback divider c1 (n f ) selected when the sel_cd pin = 0 fbkdiv_c1[2:0] a-counter value fbkdiv_c1[10:0] (bits 66-56) fbkdiv_c1[10:3] m-counter value feedback divider c2 (n f ) selected when the sel_cd pin = 1 fbkdiv_c2[2:0] a-counter value fbkdiv_c2[10:0] (bits 90-80) fbkdiv_c2[10:3] m-counter value table 7: post divider control bits name description post_a[3:0] (bits 99-96) post divider a (see table 8) post_b[3:0] (bits 103-100) post divider b (see table 8) post_c1[3:0] (bits 107-104) post divider c1 (see table 8) selected when the sel_cd pin = 0 post_c2[3:0] (bits 115-112) post divider c2 (see table 8) selected when the sel_cd pin = 1 post_d1[3:0] (bits 111-108) post divider d1 (see table 8) selected when the sel_cd pin = 0 post_d2[3:0] (bits 119-116) post divider d2 (see table 8) selected when the sel_cd pin = 1 table 8: post divider modulus bit [3] bit [2] bit [1] bit [0] divide by 00 0 0 1 00 0 1 2 00 1 0 3 00 1 1 4 01 0 0 5 01 0 1 6 01 1 0 8 01 1 1 9 10 0 010 10 0 112 10 1 015 10 1 116 11 0 018 11 0 120 11 1 025 11 1 150
12 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic table 9: pll tuning bits name description loop filter time constant a bit = 0 short time constant: 7 s lftc_a (bit 20) bit = 1 long time constant: 20 s loop filter time constant b bit = 0 short time constant: 7 s lftc_b (bit 44) bit = 1 long time constant: 20 s loop filter time constant c1 selected when the sel_cd pin = 0 bit = 0 short time constant: 7 s lftc_c1 (bit 68) bit = 1 long time constant: 20 s loop filter time constant c2 selected when the sel_cd pin = 1 bit = 0 short time constant: 7 s lftc_c2 (bit 92) bit = 1 long time constant: 20 s charge pump a bit = 0 current = 2 a cp_a (bit 19) bit = 1 current = 10 a charge pump b bit = 0 current = 2 a cp_b (bit 43) bit = 1 current = 10 a charge pump c1 selected when the sel_cd pin = 0 bit = 0 current = 2 a cp_c1 (bit 67) bit = 1 current = 10 a charge pump c2 selected when the sel_cd pin = 1 bit = 0 current = 2 a cp_c2 (bit 91) bit = 1 current = 10 a table 10: mux select bits name description mux a frequency select bit 23 bit 22 0 0 reference frequency 0 1 pll a frequency 1 0 pll b frequency mux_a[1:0] (bits 23-22) 1 1 pll c frequency mux b frequency select bit 47 bit 46 0 0 reference frequency 0 1 pll a frequency 1 0 pll b frequency mux_b[1:0] (bits 47-46) 1 1 pll c frequency mux c1 frequency select selected when the sel_cd pin = 0 bit 71 bit 70 0 0 reference frequency 0 1 pll a frequency 1 0 pll b frequency mux_c1[1:0] (bits 71-70) 1 1 pll c frequency mux c2 frequency select selected when the sel_cd pin = 1 bit 125 bit 124 0 0 reference frequency 0 1 pll a frequency 1 0 pll b frequency mux_c2[1:0] (bits 125-124) 1 1 pll c frequency mux d1 frequency select selected when the sel_cd pin = 0 bit 95 bit 94 0 0 reference frequency 0 1 pll a frequency 1 0 pll b frequency mux_d1[1:0] (bits 95-94) 1 1 pll c frequency mux d2 frequency select selected when the sel_cd pin = 1 bit 127 bit 126 0 0 reference frequency 0 1 pll a frequency 1 0 pll b frequency mux_d2[1:0] (bits 127-126) 1 1 pll c frequency
13 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic 10.0 electrical specifications table 11: absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. exposure to maximum rati ng conditions for extended conditions may affect device performance, functionality, and reliability. parameter symbol min. max. units supply voltage, dc (v ss = ground) v dd v ss -0.5 7 v input voltage, dc v i v ss -0.5 v dd +0.5 v output voltage, dc v o v ss -0.5 v dd +0.5 v input clamp current, dc (v i < 0 or v i > v dd )i ik -50 50 ma output clamp current, dc (v i < 0 or v i > v dd )i ok -50 50 ma storage temperature range (non-condensing) t s -65 150 c ambient temperature range, under bias t a -55 125 c junction temperature t j 150 c lead temperature (soldering, 10s) 260 c input static discharge voltage protection (mil-std 883e, method 3015.7) 2 kv caution: electrostatic sensitive device permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy ele c- trostatic discharge. table 12: operating conditions parameter symbol conditions/description min. typ. max. units 5v 10% 4.5 5 5.5 supply voltage v dd 3.3v 10% 3 3.3 3.6 v ambient operating temperature range t a 070c crystal resonator frequency f xin 527mhz crystal resonator load capacitance c xl parallel resonant, at cut 18 pf serial data transfer rate standard mode 10 100 kb/s output driver load capacitance c l 15 pf
14 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic table 13: dc electrical specifications unless otherwise stated, v dd = 5.0v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 from typical. negative currents indicate current flows out of the device. parameter symbol conditions/description min. typ. max. units overall supply current, dynamic i dd v dd = 5.5v, f clk = 50mhz, c l = 15pf see figure 11 for more information 43 ma supply current, write i dd(write) additional operating current demand, eeprom program mode, v dd = 5.5v 2ma supply current, read i dd(read) additional operating current demand eeprom program mode, v dd = 5.5v 1ma supply current, static i ddl v dd = 5.5v, powered down via pd pin 0.3 ma dual function i/o (pd/scl, oe/sda) v dd = 5.5v 3.85 v dd +0.3 run mode (pd, oe) v dd = 3.6v 2.52 v dd +0.3 v dd = 5.5v 3.85 v dd +0.3 register program mode (sda, scl) v dd = 3.6v 2.52 v dd +0.3 v dd = 5.5v 3.85 v dd +0.3 high-level input voltage v ih eeprom program mode (sda, scl) v dd = 3.6v 2.52 v dd +0.3 v v dd = 5.5v v ss -0.3 1.65 run mode (pd, oe) v dd = 3.6v v ss -0.3 1.08 v dd = 5.5v v ss -0.3 1.65 register program mode (sda, scl) v dd = 3.6v v ss -0.3 1.08 v dd = 5.5v v ss -0.3 1.65 low-level input voltage v il eeprom program mode (sda, scl) v dd = 3.6v v ss -0.3 1.08 v v dd = 5.5v 2.20 run mode (pd, oe) v dd = 3.6v 1.44 v dd = 5.5v 2.20 register program mode (sda, scl) v dd = 3.6v 1.44 v dd = 5.5v 0.275 hysteresis voltage v hys eeprom program mode (sda, scl) v dd = 3.6v 0.18 v run / register program mode -1 1 high-level input current i ih eeprom program mode -1 1 a low-level input current (pull-up) i il v il = 0v -20 -36 -80 a run / register program mode, v ol = 0.4v 26 low-level output sink current (sda) i ol eeprom program mode, v ol = 0.4v 3.0 ma mode and frequency select inputs (mode, sel_cd) v dd = 5.5v 2.4 v dd +0.3 high-level input voltage v ih v dd = 3.6v 2.0 v dd +0.3 v v dd = 5.5v v ss -0.3 0.8 low-level input voltage v il v dd = 3.6v v ss -0.3 0.8 v high-level input current i ih -1 1 a low-level input current (pull-up) i il -20 -36 -80 a
15 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic table 14: dc electrical specifications, continued unless otherwise stated, v dd = 5.0v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 from typical. negative currents indicate current flows out of the device. parameter symbol conditions/description min. typ. max. units crystal oscillator feedback (xin) v dd = 5.5v 2.9 threshold bias voltage v th v dd = 3.6v 1.7 v v dd = 5.5v 54 a high-level input current i ih v dd = 5.5v, oscillator powered down 5 15 ma low-level input current i il -25 -54 -75 a crystal loading capacitance * c l(xtal) as seen by an external crystal connected to xin and xout 18 pf input loading capacitance * c l(xin) as seen by an external clock driver on xout; xin unconnected 36 pf crystal oscillator drive (xout) high-level output source current i oh v dd = v(xin) = 5.5v, v o = 0v 10 21 30 ma low-level output sink current i ol v dd = 5.5v, v(xin) = v o = 5.5v -10 -21 -30 ma clock outputs (clk_a, clk_b, clk_c, clk_d) high-level output source current i oh v o = 2.4v -125 ma low-level output sink current i ol v o = 0.4v 23 ma z oh v o = 0.5v dd ; output driving high 29 output impedance z ol v o = 0.5v dd ; output driving low 27 ? tristate output current i z -10 10 a short circuit source current * i sch v dd = 5.5v, v o = 0v; shorted for 30s, max. -150 ma short circuit sink current * i scl v dd = v o = 5.5v, shorted for 30s, max. 123 ma figure 10: clk_a, clk_b, clk_c, clk_d clock outputs low drive current (ma) high drive current (ma) voltage (v) min. typ. max. voltage (v) min. typ. max. 0 0 0 0 0 -87 -112 -150 0.2 9 11 12 0.5 -85 -110 -147 0.5 22 25 29 1 -83 -108 -144 0.7 29 34 40 1.5 -80 -104 -139 1 394655 2 -74-97-131 1.2 445264 2.5 -65-88-121 1.5 516176 2.7 -61-84-116 1.7 556683 3 -53-77-108 2 607392 3.2 -48-71-102 2.2 627797 3.5 -39-62-92 2.5 65 81 104 3.7 -32 -55 -85 2.7 65 83 108 4 -21 -44 -74 3 66 85 112 4.2 -13 -36 -65 3.5 67 87 117 4.5 0 -24 -52 4 68 88 119 4.7 -15 -43 4.5 69 89 120 5 0 -28 5 91 121 5.2 -11 5.5 123 5.5 0 -200 -150 -100 -50 0 50 100 150 - 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 output voltage (v) output current (ma) min typ max the data in this table represents nominal characterization data only.
16 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic figure 11: dynamic current vs. output frequency vdd = 5.0v; reference frequency = 27.00mhz; vco frequency = 200mhz, c l = 17pf except where noted 0 10 20 30 40 50 60 70 80 90 100 110 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 output frequency (mhz) dynamic current (ma) all outputs off except output under test, c l = 0pf all outputs off except output under test all outputs at 4mhz except output under test all outputs at the same frequency, all outputs at 200mhz except output under test all out p uts at the same fre q uenc y c l = 0pf vdd = 3.3v; reference frequency = 27.00mhz; vco frequency = 100mhz, c l = 17pf except where noted 0 5 10 15 20 25 30 35 40 45 0 102030405060708090100 output frequency (mhz) dynamic current (ma) all out p uts at the same fre q uenc y all outputs at 100mhz except output under test all outputs at the same frequency, c l = 0pf all outputs at 2mhz except output under test all outputs off except out p ut under test all outputs off except output under test, c l = 0pf
17 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic table 15: ac timing specifications unless otherwise stated, v dd = 5.0v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 from typical. parameter symbol conditions/description clock (mhz) min. typ. max. units overall eeprom write cycle time t wc 4ms v dd = 5.5v 0.8 150 output frequency * f o v dd = 3.6v 0.8 100 mhz v dd = 5.5v 40 230 vco frequency * f vco v dd = 3.6v 40 170 mhz vco gain * a vco 400 mhz/v lftc bit = 0 7 loop filter time constant * lftc bit = 1 20 s v o = 0.5v to 4.5v; c l = 15pf 2.0 rise time * t r v o = 0.3v to 3.0v; c l = 15pf 2.1 ns v o = 4.5v to 0.5v; c l = 15pf 1.8 fall time * t f v o = 3.0v to 0.3v; c l = 15pf 1.9 ns tristate enable delay * t pzl, t pzh 18ns tristate disable delay * t plz, t phz 18ns output active from power-up, run mode via pd pin 100 s clock stabilization time * t stb after last register is written, register program mode 1 ms divider modulus feedback divider n f see also table 2 8 2047 reference divider n r 1 255 post divider n p see also table 8 1 50 clock outputs (pll a clock via clk_a pin) duty cycle * ratio of pulse width (as measured from rising edge to next falling edge at 2.5v) to one clock period 100 45 55 % on rising edges 500 s apart at 2.5v relative to an ideal clock, c l =15pf, f xin =14.318mhz, n f =220, n r =63, n px =50, no other plls active 100 45 jitter, long term ( y ( )) * t j(lt) on rising edges 500 s apart at 2.5v relative to an ideal clock, c l =15pf, f xin =14.318mhz, n f =220, n r =63, n px =50, all other plls active (b=60mhz, c=40mhz, d=14.318mhz) 50 165 ps from rising edge to the next rising edge at 2.5v, c l =15pf, f xin =14.318mhz, n f =220, n r =63, n px =50, no other plls active 100 110 jitter, period (peak-peak) * t j( ? p) from rising edge to the next rising edge at 2.5v, c l =15pf, f xin =14.318mhz, n f =220, n r =63, n px =50, all other plls active (b=60mhz, c=40mhz, d=14.318mhz) 50 390 ps
18 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic table 16: ac timing specifications, continued unless otherwise stated, v dd = 5.0v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 from typical. parameter symbol conditions/description clock (mhz) min. typ. max. units clock outputs (pll b clock via clk_b pin) duty cycle * ratio of pulse width (as measured from rising edge to next falling edge at 2.5v) to one clock period 100 45 55 % on rising edges 500 s apart at 2.5v relative to an ideal clock, c l =15pf, f xin =14.318mhz, n f =220, n r =63, n px =50, no other plls active 100 45 jitter, long term ( y ( )) * t j(lt) on rising edges 500 s apart at 2.5v relative to an ideal clock, c l =15pf, f xin =14.318mhz, n f =220, n r =63, n px =50, all other plls active (a=50mhz, c=40mhz, d=14.318mhz) 60 75 ps from rising edge to the next rising edge at 2.5v, c l =15pf, f xin =14.318mhz, n f =220, n r =63, n px =50, no other plls active 100 120 jitter, period (peak-peak) * t j( ? p) from rising edge to the next rising edge at 2.5v, c l =15pf, f xin =14.318mhz, n f =220, n r =63, n px =50, all other plls active (a=50mhz, c=40mhz, d=14.318mhz) 60 400 ps clock outputs (pll_c clock via clk_c pin) duty cycle * ratio of pulse width (as measured from rising edge to next falling edge at 2.5v) to one clock period 100 45 55 % on rising edges 500 s apart at 2.5v relative to an ideal clock, c l =15pf, f xin =14.318mhz, n f =220, n r =63, n px =50, no other plls active 100 45 jitter, long term ( y ( )) * t j(lt) on rising edges 500 s apart at 2.5v relative to an ideal clock, c l =15pf, f xin =14.318mhz, n f =220, n r =63, n px =50, all other plls active (a=50mhz, b=60mhz, d=14.318mhz) 40 105 ps from rising edge to the next rising edge at 2.5v, c l =15pf, f xin =14.318mhz, n f =220, n r =63, n px =50, no other plls active 100 120 jitter, period (peak-peak) * t j( ? p) from rising edge to the next rising edge at 2.5v, c l =15pf, f xin =14.318mhz, n f =220, n r =63, n px =50, all other plls active (a=50mhz, b=60mhz, d=14.318mhz) 40 440 ps clock outputs (crystal oscillator via clk_d pin) duty cycle * ratio of pulse width (as measured from rising edge to next falling edge at 2.5v) to one clock period 14.318 45 55 % on rising edges 500 s apart at 2.5v relative to an ideal clock, c l =15pf, f xin =14.318mhz, no other plls active 14.318 20 jitter, long term ( y ( )) * t j(lt) from rising edge to the next rising edge at 2.5v, c l =15pf, f xin =14.318mhz, all other plls active (a=50mhz, b=60mhz, c=40mhz) 14.318 40 ps from rising edge to the next rising edge at 2.5v, c l =15pf, f xin =14.318mhz, no other plls active 14.318 90 jitter, period (peak-peak) * t j( ? p) from rising edge to the next rising edge at 2.5v, c l =15pf, f xin =14.318mhz, all other plls active (a=50mhz, b=60mhz, c=40mhz) 14.318 450 ps
19 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic table 17: serial interface timing specifications unless otherwise stated, all power supplies = 5.0v 5%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 from typical. standard mode parameter symbol conditions/description min. max. units clock frequency f scl scl 0 100 khz bus free time between stop and start t buf 4.7 s set up time, start (repeated) t su:sta 4.7 s hold time, start t hd:sta 4.0 s set up time, data input t su:dat sda 250 ns hold time, data input t hd:dat sda 0 s output data valid from clock t aa minimum delay to bridge undefined region of the fall- ing edge of scl to avoid unintended start or stop 3.5 s rise time, data and clock t r sda, scl 1000 ns fall time, data and clock t f sda, scl 300 ns high time, clock t hi scl 4.0 s low time, clock t lo scl 4.7 s set up time, stop t su:sto 4.0 s figure 12: bus timing data scl sda ~ ~ ~ ~ ~ ~ stop t su:sto t hd:sta start t su:sta address or data valid data can change figure 13: data transfer sequence scl sda in t hd:dat ~ ~ t hd:sta t su:sta t su:sto t lo t hi sda out t su:dat ~ ~ ~ ~ t buf t r t f t aa t aa
20 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic 11.0 package information table 18: 16-pin soic (0.150") package dimensions dimensions inches millimeters min. max. min. max. a 0.061 0.068 1.55 1.73 a1 0.004 0.0098 0.102 0.249 a2 0.055 0.061 1.40 1.55 b 0.013 0.019 0.33 0.49 c 0.0075 0.0098 0.191 0.249 d 0.386 0.393 9.80 9.98 e 0.150 0.157 3.81 3.99 e 0.050 bsc 1.27 bsc h 0.230 0.244 5.84 6.20 h 0.010 0.016 0.25 0.41 l 0.016 0.035 0.41 0.89 0 8 0 8 be d a 1 seating plane h e 16 1 all radii: 0.005" to 0.01" base plane a 2 c l 7 typ. h x 45 a american microsystems, inc. r table 19: 16-pin soic (0.150") package characteristics parameter symbol conditions/description typ. units thermal impedance, junction to free-air 16-pin 0.150? soic ja air flow = 0 m/s 109 c/w corner lead 4.0 lead inductance, self l 11 center lead 3.0 nh lead inductance, mutual l 12 any lead to any adjacent lead 0.4 nh lead capacitance, bulk c 11 any lead to v ss 0.5 pf
21 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic 12.0 ordering information 12.1 device ordering codes ordering code device number font package type operating temperature range shipping configuration 11575-801 fs6370 -01 16-pin (0.150?) soic (small outline package) 0 c to 70 c (commercial) tape-and-reel 11575-811 fs6370 -01 16-pin (0.150?) soic (small outline package) 0 c to 70 c (commercial) tubes 12.2 demo kit ordering codes ordering code kit for device number: description 11575-301 FS6370-01 kit includes: ? populated board with example device ? interface cable ? demonstration software 11575-201 FS6370-01 kit includes: ? populated board with single programming socket ? interface cable ? demonstration software purchase of i 2 c components of american microsystems, inc., or one of its sublicensed associated compa- nies conveys a license under philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. copyright ? 1998, 1999 american microsystems, inc. devices sold by ami are covered by the warranty and patent indemnification provisions appearing in its terms of sale only. ami makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. ami makes no warranty of merchantability or fitness for any purposes. ami reserves the right to discontinue production and change specifications and prices at any time and without notice. ami?s products are intended for use in commercial applications. applications requiring ex- tended temperature range, unusual environmental requirements, or high reliability applications, such as military, medi- cal life-support or life-sustaining equipment, are specifically not recommended without additional processing by ami for such applications. american microsystems, inc., 2300 buckskin rd., pocatello, id 83201, (208) 233-4690, fax (208) 234-6796, www address: http://www.amis.com e-mail: t g p @ amis.com
22 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic 13.0 demonstration board and software a simple demonstration board and windows 3.1x/95/98- based software is available from american microsystems that illustrates the capabilities of the fs6370. the soft- ware can operate under windows nt but cannot com- municate with the board. the board schematic is shown below. components listed with an asterisk (*) are not required in an actual applica- tion, and are used here to preserve signal integrity with the cabling associated with the board. a cabled interface between a computer parallel port (db25 connector) and the board (j1) is provided. components shown in dashed lines are optional, depending on the application. contact your local sales representative for more informa- tion. figure 14: board schematic american microsystems, inc. fs6370 board fs6370 vss sel_cd pd/scl vss xin xout oe/sda vdd vdd clk_a vdd clk_b clk_c vss clk_d mode c1 2.2f c3 0.1f y1 scl sda addr/ mode 5 4 1 2 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 j1* 6 gnd +v r1 100 ? r2 100 ? r3 100 ? r4 10 ? +5v +v +v r10 100 ? sel +5v/3.3v red +v tp1 r11 4.7k ? c11 100pf r12 4.7k ? r13 4.7k ? c12 100pf c14 100pf r14 4.7k ? +v +v c13 100pf gnd blk tp2 r5 10 ? c2 2.2f c4 0.1f +v r11 10 ? c5 2.2f c6 0.1f +v clk_b r7* 47 ? tp4 c8 10pf +v clk_a r6* 47 ? tp3 c7 10pf +v clk_c r8* 47 ? tp5 c9 10pf +v clk_d r9* 47 ? tp6 c10 10pf +v d1 d2 d3 d4 u1
23 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic 13.1 demo kit contents ? demonstration board ? interface cable (db25 to 6-pin connector) ? data sheet ? demonstration software, totaling 24 compressed files which will expand to 1.8mb, including fs6370.exe after installation. 13.2 requirements ? pc running ms windows 3.1x or 95/98 with an ac- cessible parallel (lpt1) port. software also runs on windows nt in a calculation mode only. ? 1.8mb available space on hard drive c. 13.3 board setup and software installation instructions 1. at the appropriate disk drive prompt (a:\) unzip the compressed demo files to a directory of your choice. run setup.exe to install the software. 2. connect a power supply to the board: red = power, black = ground. 3. connect the supplied interface cable to the parallel port (db25 connector) and to the demo board (6-pin connector). make sure the cable is facing away from the board. pin 1 is the red wire per table 20. 4. connect the clock outputs to the target application board with a twisted-pair cable. 13.4 demo program operation launch the fs6370.exe program. note that the parallel port can not be accessed if your machine is running windows nt. a warning message will appear stating: ?this version of the demo program cannot communicate with the fs6370 hardware when running on a windows nt operating system. do you want to con- tinue anyway, using just the calculation features of this program?? clicking ok starts the program for calculation only. the opening screen is shown in figure 15. figure 15: opening screen
24 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic 13.4.1 example programming type a value for the crystal resonator frequency in mhz in the reference crystal box. this frequency provides the basis for all of the pll calculations that follow. next, click on the pll a box. a pop-up screen similar to figure 16 should appear. type in a desired output clock frequency in mhz, set the operating voltage (3.3v or 5v), and the desired maximum output frequency error. press- ing calculate solutions generates several possible di- vider and vco-speed combinations. figure 16: pll screen for a 100mhz output, the vco should ideally operate at a higher frequency, and the reference and feedback dividers should be as small as possible. in this example, highlight solution #7. notice the vco operates at 200mhz with a post divider of 2 to obtain an optimal 50% duty cycle. now choose which mux and post divider to use (that is, choose an output pin for the 100mhz output). selecting a places the postdiv value in solution #7 into post divider a and switches mux a to take the output of pll a. the pll screen should disappear, and now the value in the pll a box is the new vco frequency chosen in solu- tion #7. note that mux a has been switched to pll a and the post divider a has the chosen 100mhz output dis- played. repeat the steps for pll b. pll c supports two different output frequencies depend- ing on the setting of the sel_cd pin. both mux c and mux d are also affected by the logic level on the sel_cd pin, as are the post dividers c and d (see section 4.2 for more detail). figure 17: post divider menu click on pll c1 to open the pll screen. set a desired frequency, however, now choose the post divider b as the output divider. notice the post divider box has split in two (as shown in figure 17). the post divider b box now shows that the divider is dependent on the setting of the sel_cd pin for as long as mux b is the pll c output. clicking on post divider a reveals a pull-down menu provided to permit adjustment of the post divider value independently of the pll screen. a typical menu is shown in figure 17. the range of possible post divider values is also given in table 8. once all of the plls, switches, and post dividers have been set, the information can be downloaded out the pc parallel port to the fs6370 (not available on windows nt). the eeprom settings are shown to the left in the screen shown in figure 15. clicking on a register location dis- plays a screen shown in figure 18. individual bits can be poked, or the entire register value can be changed. figure 18: register screen
25 FS6370-01 FS6370-01 FS6370-01 FS6370-01 eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic eeprom programmable 3-pll clock generator ic table 20: cable interface color j1 db25 signal red 1 2, 13 scl white 2 3, 12 sda green 3 8 mode blue 4 5 sel brown 5 4 +5v black 6 25 gnd figure 19: cable diagram 100 1 2 3 4 5 6 j1 db-25 2 3 8 5 4 13 12 25 100 pin pin red wht grn blu brn blk figure 20: board layout figure 21: board layout with socket

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