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32bit tx system risc tx19a family tmp19a43fd/fzxbg rev2.0 2007.apr.9
tmp19a43 tmp19a43 (rev2.0) 1-1 overview and features 32-bit risc microprocessor - tx19 family TMP19A43FZXBG, fdxbg 1. overview and features the tx19 family is a high-performance 32-bit risc pro cessor series that toshiba originally developed by integrating the mips16 tm ase (application specific extension), which is an extended instruction set of high code efficiency. tmp19a43 is a 32-bit risc microprocessor with a tx19a processor core and various peripheral functions integrated into one package. it can operate at low voltage with low power consumption. features of tmp19a43 are as follows: restrictions on product use 070122ebp ? the information contained herein is subject to change without notice. 021023_d ? toshiba is continually working to improve the quality a nd reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inher ent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba pr oducts, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba produc ts are used within specified operating ranges as set forth in the most recent toshiba produc ts specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor device s,? or ?toshiba semiconductor reliability handbook? etc. 021023_a ? the toshiba products listed in this document are intend ed for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipmen t, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may ca use loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instrument s, airplane or spaceship in struments, transportation instruments, traffic signal instruments, combustion cont rol instruments, medical instru ments, all types of safety devices, etc. unintended usage of tosh iba products listed in this document shall be made at the customer?s own risk. 021023_b ? the products described in this document shall not be us ed or embedded to any downstream products of which manufacture, use and/or sale are prohibited und er any applicable laws and regulations. 060106_q ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patents or other rights of to shiba or the third parties. 070122_c ? the products described in this document are subject to foreign exchange and foreign trade control laws. 060925_e ? for a discussion of how the reliability of microcontrollers ca n be predicted, please refer to section 1.3 of the chapter entitled quality and reliability assurance/handling precautions. 030619_s
tmp19a43 tmp19a43 (rev2.0) 1-2 overview and features (1) tx19a processor core 1) improved code efficiency and operating performance have been realized through the use of two isa (instruction set architecture) modes - 16- and 32-bit isa modes. ? the 16-bit isa mode instructions are compatible with the mips16 tm ase instructions of superior code efficiency at the object level. ? the 32-bit isa mode instructions are compatible w ith the tx39 instructions of superior operating performance at the object level. 2) both high performance and low power dissipation have been achieved. z high performance ? almost all instructions can be executed with one clock. ? high performance is possible via a th ree-operand operation instruction. ? 5-stage pipeline ? built-in high-speed memory ? dsp function: a 32-bit multiplication and accumulation operation can be executed with one clock. z low power dissipation ? optimized design using a low power dissipation library ? standby function that stops the op eration of the processor core 3) high-speed interrupt response suitable for real-time control ? independency of the entry address ? automatic generation of factor -specific vector addresses ? automatic update of interrupt mask levels (2) internal program memory and data memory product name built-in rom built-in ram tmp19a43czxbg 384kbyte 20kbyte tmp19a43cdxbg * 512kbyte 24kbyte TMP19A43FZXBG * 384kby te (flash) 20kbyte tmp19a43fdxbg 512kbyte (flash) 24kbyte the product indicated by an aste risk * is under development. ? rom correction function: 1 word 8 blocks, 8 words 4 blocks (3) external memory expansion ? expandable to 16 megabytes (for both programs and data) ? external data bus: separate bus/multiplexed bus : coexistence of 8- and 16-bit widths is possible. chip select/wait controller : 4 channels (4) dma controller : 8 channels (2 interrupt factors) ? activated by an interrupt or software ? data to be transferred to internal memory, in ternal i/o, external memory, and external i/o (5) 16-bit timer : 16 channels ? 16-bit interval timer mode ? 16-bit event counter mode ? 16-bit ppg output (every 4 channels, synchronous outputs are possible) ? input capture function ? 2-phase pulse input counter function (4 channels assigned to perform this function): multiplication- by-4 mode
tmp19a43 tmp19a43 (rev2.0) 1-3 overview and features (6) 32-bit timer ? 32-bit input capture register : 4 channels ? 32-bit compare register : 8 channels ? 32-bit time base timer : 1 channel (7) clock timer : 1 channel (8) general-purpose serial interface : 3 channels ? selectable between the uart m ode and the synchronization mode (9) high-speed serial interface : 3 channels ? selectable between the uart mode and the high -speed synchronization mode (maximum speed: 10 mbps in the high-speed synchronization mode @40mhz) (10) serial bus interface : 1 channel ? selectable between the i 2 c bus mode and the clock synchronization mode (11) 10-bit a/d converter (with s/h) : 16 channels ? start by an external trigger, and the internal timer activated by a trigger ? fixed channel/scan mode ? single/repeat mode ? high-priority conversion mode ? timer monitor function ? conversion time 1.15 sec(@ 40mhz) (12) 8-bit d/a converter : 2 channels (13) watchdog timer : 1 channel (14) interrupt function ? cpu: 2 factors ...................software interrupt instruction ? internal: 46 factors.............the order of precedence can be set over 7 levels (except the watchdog timer interrupt). ? external: 48 factors ..........the order of precedence can be set over 7 levels. because 32 factors are associated w ith kwup, the number of interrupt factors is one. (15) input and output ports ...............143 terminals (16) standby function ? three standby modes (idle, sleep, stop) (17) clock generator ? built-in pll (multiplication by 4) ? clock gear function: the high-speed clock can be divided into 3/4, 1/2, 1/4 or 1/8. ? sub-clock: slow and sleep modes (32.768 khz) (18) endian: bi-endian (big-endian/little-endian) (19) maximum operating frequency ? 40 mhz (pll multiplication) (20) operating voltage range ? core: 1.35 v to 1.65 v ? i/o and adc: 2.7 v to 3.6 v ? dac: 2.3 v to 2.7 v (21) package p-fbga193 (12 mm 12 mm, 0.65 mm pitch)
tmp19a43 tmp19a43 (rev2.0) 1-4 overview and features fig. 1-1 tmp19a43 block diagram tx19 processor core tx19a cpu mac ejtag 512k/384byte flash 24k/20kbyte ram rom correction dmac (8ch) clock generator (cg) intc external bus interface i/o bus interface 16-bit tmrb 0 to 15 ( 16ch ) 32-bit tmrc tbt ( 1ch ) 32-bit tmrc input capture 0 to 3 (4ch) 32-bit tmrc compare 0 to 7 (8ch) 10-bit adc (16ch) sio/uart 0 to 2 ( 3ch ) i2c/sio ( 1ch ) port0 to port6 (also function as external bus i/f) wdt kwup (32ch) port7 to port8 (also function to receive adc inputs) port9 to porth (also function as functional pins) clock timer (1ch) 8-bit dac (2ch) hsio/uart 0 to 2 (3ch)
tmp19a43 tmp19a43 (rev2.0) 2-1 pin layout and pin functions 2. pin layout and pin functions this section shows the pin layout of tmp19a43 and describes the names and functions of input and output pins. 2.1 pin layout (top view) fig. 2-1 pin layout diagram (p-fbga193) shows the pin layout of tmp19a43. a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 c1 c2 c16c17 d1 d2 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d16 d17 e1 e2 e4 e5 e6 e7 e8 e9 e10 e11 e12 e13 e14 e16 e17 f1 f2 f4 f5 f6 f13 f14 f16 f17 g1 g2 g4 g5 g13 g14 g16 g17 h1 h2 h4 h5 h13 h14 h16 h17 j1 j2 j4 j5 j13 j14 j16 j17 k1 k2 k4 k5 k13 k14 k16 k17 l1 l2 l4 l5 l13 l14 l16 l17 m1 m2 m4 m5 m13 m14 m16 m17 n1 n2 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n16 n17 p1 p2 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p16 p17 r1 r2 r16r17 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u13 u14 u15 u16 u17 fig. 2-1 pin layout diagram (p-fbga193)
tmp19a43 tmp19a43 (rev2.0) 2-2 pin layout and pin functions 2.2 pin numbers and names table 2-1 shows the pin numbers and names of tmp19a43. table 2-1 pin numbers and names pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name a1 dvss d2 pf3/key19/dack4 g2 p95/sclk2/cts2 m1 pb5/htxd1 r2 p33/wait/rdy a2 p81/an9/key05 d4 p71/an1 g4 p94/rxd2 m2 pb4/hsclk0/hcts0 r16 p45/busmd a3 p83/an11/key07 d5 p73/an3 g5 p93/txd2 m4 pb3/hrxd0 r17 p46/endian a4 p85/an13/int7 d6 p74/an4/key00 g13 ph1/tpc1/tpd1 m5 test4 t1 p37/ale/tc3in a5 p87/an15/int9 d7 p76/an6/key02 g14 ph7/tpc7/tpd7 m13 fvcc3 t2 p34/busrq/tbeout a6 da0 d8 pd5/tbdout g16 pcst4 m14 pg3/tpd3 t3 p30/rd a7 cvref0 d9 pd3/tbbout g17 dclk m16 pg4/tpd4 t4 p02/d2/ad2 a8 da1 d10 pd0/htxd2 h1 pc1/tcout0 m17 pg5/tpd2 t5 p06/d6/ad6 a9 cvref1 d11 pe0/key8 h2 pc0/tbtin/key30 n1 pb7/hsclk1/hcts1 t6 p12/d10/ad10/a10 a10 pd2/hsclk2/hcts2 d12 pe3/key11 h4 p97/tbaout n2 pb6/hrxd1 t7 p16/d14/ad14/a14 a11 pe2/key10 d13 pa2/int2/tb7in0 h5 dvcc3 n4 p00/d0/ad0 t8 p21/a17/a1/tb0in1 a12 pe5/key13 d14 ph4/tpc4/tpd4 h13 ph2/tpc2/tpd2 n5 p04/d4/ad4 t9 p24/a20/a4/tb4in0 a13 pe7/key15 d16 pa3/int3/tb7in1 h14 trst n6 p10/d8/ad8/a8 t10 p26/a22/a6/tb5in0 a14 x1 d17 xt1 h16 tms n7 p14/d12/ad12/a12 t11 p52/a2/inte a15 x2 e1 pf6/key22/tcout6 h17 eje n8 fvcc3 t12 p56/a6/tb2out/key28 a16 cvcch e2 pf5/key21/tcout5 j1 pc4/tcout3 n9 dvss t13 p62/a10/sclk0/cts0 a17 cvss e4 p70/an0 j2 pc3/tcout2 n10 dvcc15 t14 p66/a14/tb4out b1 pf0/key16/dreq0 e5 p72/an2 j4 pc2/tcout1 n11 p50/a0/intc t15 p40/cs0/key24 b2 p80/an8/key04 e6 vrefh j5 dvcc15 n12 p54/a4/tb0out t16 p42/cs2/key26 b3 p82/an10/key06 e7 avss j13 ph3/tpc3/tpd3 n13 p60/a8/txd0 t17 p44/scout b4 p84/an12/int6 e8 davcc j14 dint n14 p64/a12/rxd1/intb u1 test2 b5 p86/an14/int8 e9 davref j16 tdo n16 pg6/tpd6 u2 p35/busak/tc1in b6 p75/an5/key01 e10 dagnd j17 dvss n17 pg7/tpd7 u3 p31/wr b7 p77/an7/key03 e11 dvcc3 k1 pc7/sck p1 boot u4 p03/d3/ad3 b8 pd6/key31/aftrg e12 pa0/int0/tb6in0 k2 pc6/si/scl p2 p32/hwr/tc0in u5 p07/d7/ad7 b9 pd4/tbcout e13 pa1/int1/tb6in1 k4 pc5/so/sda p4 p01/d1/ad1 u6 p13/d11/ad11/a11 b10 pd1/hrxd2 e14 ph5/tpc5/tpd5 k5 dvss p5 p05/d5/ad5 u7 p17/d15/ad15/a15 b11 pe1/key09 e16 pcst0 k13 dvcc15 p6 p11/d9/ad9/a9 u8 p22/a18/a2/tb1in0 b12 pe4/key12 e17 pcst1 k14 tovr/tsta p7 p15/d13/ad13/a13 u9 p25/a21/a5/tb4in1 b13 pe6/key14 f1 pf7/key23/tcout7 k16 tdi p8 p20/a16/a0/tb0in0 u10 p27/a23/a7/tb5in1 b14 pa5/int5/tb8in1 f2 p92/tb8out k17 tck p9 p23/a19/a3/tb1in1 u11 p53/a3/intf b15 pa6/ tb2in0 f4 p91/tb7out l1 pb2/htxd0 p10 test0 u12 p57/a7/tb3out/key29 b16 pa7/tb2in1 f5 p90/tb6out l2 pb1/tb3in1 p11 p51/a1/intd u13 p63/a11/txd1 b17 cvccl f6 avcc3 l4 pb0/tb3in0 p12 p55/a5/tb1out u14 p67/a15/tb5out c1 pf2/key18/dreq4 f13 ph0/tpc0/tpd0 l5 test1 p13 p61/a9/rxd0/inta u15 p41/cs1/key25 c2 pf1/key17/dack0 f14 ph6/tpc6/tpd6 l13 dvss p14 p65/a13/sclk1/cts1 u16 p43/cs3/key27 c16 pa4/int4/tb8in0 f16 pcst2 l14 pg0/tpd0 p16 p47/tbfout u17 test3 c17 xt2 f17 pcst3 l16 pg1/tpd1 p17 reset d1 pf4/key20/tcout4 g1 p96/tb9out l17 pg2/tpd2 r1 p36/rw/tc2in
tmp19a43 tmp19a43 (rev2.0) 2-3 pin layout and pin functions 2.3 pin names and functions table 2-2 through table 2-7 show the names and functions of input and output pins. table 2-2 pin names and functions (1 of 6) pin name number of pins input or output function p00-p07 8 input/output port 0: input/output port (with pull-up) th at allows input/output to be set in units of bits d0-d7 input/output data (lower): data bus 0 to 7 (separate bus mode) ad0-d7 input/output address data (lower): addre ss data bus 0 to 7 (multiplexed bus mode) p10-p17 8 input/output port 1: input/output port (with pull-up) th at allows input/output to be set in units of bits d8-d15 input/output data (upper): data bus 8 to 15 (separate bus mode) ad8-ad15 input/output address data (upper): address data bus 8 to 15 (multiplexed bus mode) a8-a15 output address: address bus 8 to 15 (multiplexed bus mode) p20-p27 8 input/output port 2: input/output port (with pull-up) th at allows input/output to be set in units of bits a16-a23 output address: address bus 15 to 23 (separate bus mode) a0-a7 output address: address bus 0 to 7 (multiplexed bus mode) tb0in0,tb0in1 input 16-bit timer 0 input 0,1: for inputting the count/capture trigger of a 16-bit timer 0 tb1in0,tb1in1 input 16-bit timer 1 input 0,1: for inputting the count/capture trigger of a 16-bit timer 1 tb4in0,tb4in1 input 16-bit timer 4 input 0,1: for inputting the count/capture trigger of a 16-bit timer 4 tb5in0,tb5in1 input 16-bit timer 5 input 0,1: for inputting the count/capture trigger of a 16-bit timer 5 p30 1 output port 30: port used exclusively for output rd output read: strobe signal for reading external memory p31 1 output port 31: port used exclusively for output wr output write: strobe signal for writing data of d0 to d7 pins p32 1 input/output port 32: input/output port (with pull-up) hwr output write upper-pin data: strobe signal for writing data of d8 to d15 pins tc0in input for inputting the captu re trigger for 32-bit timer p33 1 input/output port 33: input/output port (with pull-up) wait input wait: pin for requesting cpu to put a bus in a wait state rdy input ready: pin for notifying cpu that a bus is ready p34 1 input/output port 34: input/output port (with pull-up) busrq input bus request: signal requesting cpu to allow an external master to take the bus control authority tbeout output 16-bit timer e output: pin for outputting 16-bit timer e p35 1 input/output port 35: input/output port (with pull-up) busak output bus acknowledge: signal notifying that cpu ha s released the bus control authority in response to busrq tc1in input for inputting the captu re trigger for 32-bit timer p36 1 input/output port 36: input/output port (with pull-up) w / r output read/write: "1" shows a read cycle or a dummy cycle. "0" shows a write cycle. tc2in input for inputting the captu re trigger for 32-bit timer p37 1 input/output port 37: input/output port (with pull-up) ale output address latch enable (address la tch is enabled only if access to external memory is taking place) tc3in input for inputting the captu re trigger for 32-bit timer p40 1 input/output port 40: input/output port (with pull-up) cs0 output chip select 0: "0" is output if the address is in a designated address area. key24 input key on wake up input 24: (dynamic pull up is selectable) input with schmitt trigger with noise filter p41 1 input/output port 41: input/output port (with pull-up) cs1 output chip select 1: "0" is output if the address is in a designated address area. key25 input key on wake up input 25: (dynamic pull up is selectable) input with schmitt trigger with noise filter p42 1 input/output port 42: input/output port (with pull-up) cs2 output chip select 2: "0" is output if the address is in a designated address area. key26 input key on wake up input 26: (dynamic pull up is selectable) input with schmitt trigger with noise filter
tmp19a43 tmp19a43 (rev2.0) 2-4 pin layout and pin functions table 2-3 pin names and functions (2 of 6) pin name number of pins input or output function p43 1 input/output port 43: input/output port (with pull-up) cs3 output chip select 3: "0" is output if the address is in a designated address area. key27 input key on wake up input 27: (dynamic pull up is selectable) input with schmitt trigger with noise filter p44 1 input/output port 44: input/output port (with pull-up) scout output system clock output: selectable between high- and low-speed clock outputs, as in the case of cpu p45 1 input/output port 45: input/output port (with pull-up) busmd input pin for setting an external bus mode: this pin functions as a multiplexed bus by sampling the "h (dvcc3) level" at the rise of a reset signal. it also functions as a separate bus by sampling "l" at the rise of a reset signal. when performing a reset operation, pull it up or down according to a bus mode to be us ed. input with schmitt trigger. (after a reset operation is performed, it can be used as a port.) p46 1 input/output port 46: input/output port (with pull-up) endian input this pin is used to set a mode. it pe rforms a big-endian operation by sampling the "h (dvcc3) level" at the rise of a reset signal, and performs a little-endi an operation by sampling "l" at the rise of a reset signal. when performing a reset operation, pull it up or down according to the type of endian to be used. (after a reset operation is performed, it can be used as a port.) input with schmitt trigger p47 1 input/output port 47: input/output port (with pull-up) tbfout output 16-bit timer f output: pin for outputting a 16-bit timer f p50-p53 4 input/output port 5: input/output port (with pull-up) th at allows input/output to be set in units of bits a0-a3 output address: address buses 0 to 3 (separate bus mode) intc-intf input interrupt request pins c to f: selectable be tween "h" level, "l" leve l, rising edge, and falling edge input pin with schmitt trigger with noise filter p54,p55 2 input/output port 5: input/output port (with pull-up) th at allows input/output to be set in units of bits a4,a5 output address: address buses 4 and 5 (separate bus mode) tb0out output 16-bit timer 0 output: pin for outputting a 16-bit timer 0 tb1out output 16-bit timer 1 output: pin for outputting a 16-bit timer 1 p56,p57 2 input/output port 5: input/output port (with pull-up) th at allows input/output to be set in units of bits a6,a7 output address: address buses 6 and 7 (separate bus mode) tb2out output 16-bit timer 2 output: pin for outputting a 16-bit timer 2 tb3out output 16-bit timer 3 output: pin for outputting a 16-bit timer 3 key28,key29 input key on wake up input 28 and 29: (dynamic pull up is selectable) input pin with schmitt trigger with noise filter p60 1 input/output port 60: input/output port (with pull-up) a8 output address: address bus 8 (separate bus mode) txd0 output sending serial data 0: open drai n output pin depending on the program used p61 1 input/output port 61: input/output port (with pull-up) a9 output address: address bus 9 (separate bus mode) rxd0 input receiving serial data 0 inta input interrupt request pin a: selectable between "h" level, "l" level, rising edge, falling edge, and both rising and falling edges. input pin with schmitt trigger with noise filter p62 1 input/output port 62: input/output port (with pull-up) a10 output address: address bus 10 (separate bus mode) sclk0 input/output serial clock input/output 0 cts0 input handshake input pin open drain output pin depending on the program used p63 1 input/output port 63: input/output port (with pull-up) a11 output address: address bus 11 (separate bus mode) txd1 output sending serial data 1: open drai n output pin depending on the program used p64 1 input/output port 64: input/output port (with pull-up) a12 output address: address bus 12 (separate bus mode) rxd1 input receiving serial data 1 intb input interrupt request pin b: selectable between "h" level, "l" level, rising edge, falling edge, and both rising and falling edges. input pin with schmitt trigger with noise filter
tmp19a43 tmp19a43 (rev2.0) 2-5 pin layout and pin functions table 2-4 pin names and functions (3 of 6) pin name number of pins input or output function p65 1 input/output port 65: input/output port (with pull-up) a13 output address: address bus 13 (separate bus mode) sclk1 input/output serial clock input/output 1 cts1 input handshake input pin. open drain output pin depending on the program used p66,p67 2 input/output port 6: input/output port (with pull-up) th at allows input/output to be set in units of bits a14,a15 output address: address buses 14 and 15 (separate bus mode) tb4out output 16-bit timer 4 output: pin for outputting a 16-bit timer 4 tb5out output 16-bit timer 5 output: pin for outputting a 16-bit timer 5 p70-p73 4 input port 7: port used exclusively for input (with pull-up) ain0-ain3 input analog input: input from a/d converter p74-p77 4 input port 7: port used exclusively for input (with pull-up) ain4-ain7 input analog input: input from a/d converter key00-key03 input key on wake up input 00 to 03: (dynamic pull up is selectable) input pin with schmitt trigger with noise filter p80-p83 4 input port 8: port used exclusively for input (with pull-up) ain8-ain11 input analog input: input from a/d converter key04-key07 input key on wake up input 04 to 07: (dynamic pull up is selectable) input pin with schmitt trigger with noise filter p84-p87 4 input port 8: port used exclusively for input (with pull-up) ain12-ain15 input analog input: input from a/d converter int6-9 interrupt request pins 6 to 9: selectable bet ween "h" level, "l" level, rising edge, falling edge, and both rising and falling edges. input pin with schmitt trigger with noise filter p90-p92 3 input/output port 9: input/output port (with pull-up) th at allows input/output to be set in units of bits tb6out output 16-bit timer 6 output: pin for outputting a 16-bit timer 6 tb7out output 16-bit timer 7 output: pin for outputting a 16-bit timer 7 tb8out output 16-bit timer 8 output: pin for outputting a 16-bit timer 8 p93 1 input/output port 93: input/output port (with pull-up) txd2 output sending serial data 2: open drai n output pin depending on the program used p94 1 input/output port 94: input/output port (with pull-up) rxd2 input receiving serial data 2 p95 1 input/output port 95: input/output port (with pull-up) sclk2 input/output serial clock input/output 2 cts2 input handshake input pin open drain output pin depending on the program used p96,p97 2 input/output ports 96 and 97: input/output port (with pull- up) that allows input/output to be set in units of bits tb9out output 16-bit timer 9 output: pin for outputting a 16-bit timer 9 tbaout output 16-bit timer a output: pin for outputting a 16-bit timer a pa0 1 input/output port a0: input/output port (with pull-up) tb6in0 input 16-bit timer 6 input 0: for inputti ng the capture trigger of a 16-bit timer 6 int0 input interrupt request pin 0: selectable between "h" level, "l" level, rising edge, falling edge, and both rising and falling edges. input pin with schmitt trigger with noise filter pa1 1 input/output port a1: input/output port (with pull-up) tb6in1 input 16-bit timer 6 input 1: for inputti ng the capture trigger of a 16-bit timer 6 int1 input interrupt request pin 1: selectable between "h" level, "l" level, rising edge, falling edge, and both rising and falling edges input pin with schmitt trigger with noise filter pa2 1 input/output port a2: input/output port (with pull-up) tb7in0 input 16-bit timer 7 input 0: for inputti ng the capture trigger of a 16-bit timer 7 int2 input interrupt request pin 0: selectable "h" le vel, "l" level, rising e dge, falling edge, and both rising and falling edges. input pin with schmitt trigger with noise filter pa3 1 input/output port a3: input/output port (with pull-up) tb7in1 input 16-bit timer 7 input 1: for inputti ng the capture trigger of a 16-bit timer 7 int3 input interrupt request pin 1: selectable between "h" level, "l" level, rising edge, falling edge, and both rising and falling edges. input pin with schmitt trigger with noise filter
tmp19a43 tmp19a43 (rev2.0) 2-6 pin layout and pin functions table 2-5 pin names and functions (4 of 6) pin name number of pins input or output function pa4 1 input/output port a4: input/output port (with pull-up) tb8in0 input 16-bit timer 8 input 0: for inputti ng the capture trigger of a 16-bit timer 8 int4 input interrupt request pin 0: selectable between "h" level, "l" level, rising edge, falling edge, and both rising and falling edges input pin with schmitt trigger with noise filter pa5 1 input/output port a5: input/output port (with pull-up) tb8in1 input 16-bit timer 8 input 1: for inputti ng the capture trigger of a 16-bit timer 8 int5 input interrupt request pin 1: selectable between "h" level, "l" level, rising edge, falling edge, and both rising and falling edges input pin with schmitt trigger with noise filter pa6 1 input/output port a6: input/output port (with pull-up) tb2in0 input 16-bit timer 2 input 0: for inputti ng the capture trigger of a 16-bit timer 2 pa7 input/output port a7: input/output port (with pull-up) tb2in1 input 16-bit timer 2 input 1: for inputti ng the capture trigger of a 16-bit timer 2 pb0 1 input/output port b0: input/output port (with pull-up) tb3in0 input 16-bit timer 3 input 0: for inputti ng the capture trigger of a 16-bit timer 3 pb1 1 input/output port b1: input/output port (with pull-up) tb3in1 input 16-bit timer 3 input 1: for inputti ng the capture trigger of a 16-bit timer 3 pb2 1 input/output port b2: input/output port (with pull-up) htxd0 output sending serial data 0 at high speeds: op en drain output pin depending on the program used pb3 1 input/output port b3: input/output port (with pull-up) hrxd0 input receiving serial data 0 at high speeds pb4 1 input/output port b4: input/output port (with pull-up) hsclk0 input/output high-speed se rial clock input/output 0 hcts0 input handshake input pin: open drain output pin depending on the program used pb5 1 input/output port b5: input/output port (with pull-up) htxd1 output sending serial data 1 at high speeds: op en drain output pin depending on the program used pb6 1 input/output port b6: input/output port (with pull-up) hrxd1 input receiving serial data 1 at high speeds pb7 1 input/output port b7: input/output port (with pull-up) hsclk1 input/output high-speed se rial clock input/output 1 hcts1 input handshake input pin: open drain output pin depending on the program used pc0 1 input/output port c0: input/output port (with pull-up) tbtin input 32-bit time base timer input: for inputting a 32-bit time base timer key30 key on wake up input 30: (dynamic pull up is selectable) input with schmitt trigger with noise filter pc1-pc4 4 input/output ports c1 to c4: input/output ports (with pu ll-up) that allow input/output to be set in units of bits tcout0- output outputting 32-bit timer if th e result of a comparison is a match tcout3 pc5 1 input/output port c5: input/output port (with pull-up) so output pin for sending data if the serial bus interface operates in the sio mode sda input/output pin for sending and r eceiving data if the serial bus interface operates in the i2c mode open drain output pin depending on the program used input with schmitt trigger pc6 1 input/output port c6: input/output port (with pull-up) si input pin for receiving data if the seri al bus interface operates in the sio mode scl input/output pin for inputting and outputting a clock if the serial bus interface operates in the i2c mode open drain output pin depending on the program used input with schmitt trigger pc7 1 input/output port c7: input/output port (with pull-up) sck input/output pin for inputting and outputting a clock if the serial bus interface operates in the sio mode open drain output pin depending on the program used
tmp19a43 tmp19a43 (rev2.0) 2-7 pin layout and pin functions table 2-6 pin names and functions (5 of 6) pin name number of pins input or output function pd0 1 input/output port d0: input/output port (with pull-up) htxd2 output sending serial data 2 at high speeds: op en drain output pin depending on the program used pd1 1 input/output port d1: input/output port (with pull-up) hrxd2 input receiving serial data 2 at high speeds pd2 1 input/output port d2: input/output port (with pull-up) hsclk2 input/output high-speed se rial clock input/output 2 hcts2 input handshake input pin: open drain output pin depending on the program used pd3-pd5 3 input/output ports d3 to d5: input/output ports (with pu ll-up) that allow input/output to be set in units of bits tbbout- output 16-bit timers b, c and d outputs: pin for outputting 16-bit timers b, c and d tbdout pd6 1 input/output port d6: input/output port (with pull-up) th at allows input/output to be set in units of bits adtrg input pin (with schmitt trigger) for starting a/d tri gger or a/d converter from an external source key31 input key on wake up input 31: (dynamic pull up is selectable) input with schmitt trigger with noise filter pe0-pe7 8 input/output port e: input/output port (with pull-up) th at allows input/output to be set in units of bits key08-key15 input key on wake up input 08 to 15: (dynamic pull up is selectable) input with schmitt trigger with noise filter pf0,pf2 2 input/output port f: input/output port (with pull-up) that allows input/output to be set in units of bits dreq0,4 input dma request signals 0 and 4: for inputting the request to transfer data by dma from an external i/o device to dmac0 or dmac4 key16,key18 input key on wake up input 16 to 19: (dynamic pull up is selectable) input with schmitt trigger with noise filter pf1,pf3 2 input/output port f: input/output port (with pull-up) that allows input/output to be set in units of bits dack0,4 output dma acknowledge signals 0 and 4: signal showing that dreq0 and dreq4 have acknowledged a dma transfer request key17,key19 input key on wake up input 16 to 19: (dynamic pull up is selectable) input with schmitt trigger with noise filter pf4-pf7 4 input/output port f: input/output port (with pull-up) that allows input/output to be set in units of bits key20 - key23 input key on wake up input 20 to 23: (dynamic pull up is selectable) tcout4 - input with schmitt trigger tcout7 output outputting 32-bit timer if th e result of a comparison is a match with noise filter pg0-pg7 8 input/output port g: input/output port (with pull-up) th at allows input/output to be set in units of bits tpd0-tpd7 output outputting trace data from the data access address: signal for dsu-ice ph0-ph7 8 input/output port h: input/output port (with pull-up) th at allows input/output to be set in units of bits tpc0-tpc7 output outputting trace data from th e program counter: signal for dsu-ice tpd0-tpd7 output outputting trace data from the data access address: signal for dsu-ice dclk 1 output debug clock: signal for dsu-ice eje 1 input dsu-ice enable: signal for dsu-ic e (with schmitt trigger) (with pull-up) with noise filter pcst4-0 4 output pc trace status: signal for dsu-ice dint 1 input debug interrupt: signal for dsu-ice (input with schmitt trigger and pull-up) with noise filter tovr/tsr 1 output outputting the status of pd data overflow status: signal for dsu-ice tck 1 input test clock input: signal fo r testing dsu-ice (with schmitt trigger and pull-up) with noise filter tms 1 input test mode select input: signal for te sting dsu-ice (with schmitt trigger and pull-up) tdi 1 input test data input e: signal for tes ting jtag (with schmitt trigger and pull-up) tdo 1 output test data output: signal for testing dsu-ice trst 1 input test reset input: signal for testing dsu-ice (with schmitt trigger and pull-down) with noise filter reset 1 input reset: initializing lsi (with pull-up) input with schmitt trigger with noise filter x1/x2 2 input/output pin for connecting a high-speed oscillator (x1: input with schmitt trigger) xt1/xt2 2 input/output pin for connecting a low-speed oscillator (xt1: input with schmitt trigger)
tmp19a43 tmp19a43 (rev2.0) 2-8 pin layout and pin functions table 2-7 pin names and functions (6 of 6) pin name number of pins input or output function boot 1 input pin for setting a single boot mode: this pin goes into single boot mode by sampling "l" at the rise of a reset signal. it is used to overwrite internal flash memory. by sampling "h (dvcc3) level" at the rise of a reset signal, it performs a normal operation. this pin should be pulled up under normal operating conditions. pull it up when resetting. (with pull-up) vrefh 1 input pin (h) for supplying the a/d c onverter with a reference power supply connect this pin to avcc3 if the a/d converter is not used. avcc3 1 ? pin for supplying the a/d converter with a power supply. connect it to a power supply even if the a/d converter is not used. avss 1 ? a/d converter gnd pin (0 v). connect this pin to gnd even if the a/d converter is not used. pin (l) for supplying the a/d converter with a reference power supply test0 1 input test pin: to be fixed to dvcc3 (with schmitt trigger) test1 1 input test pin: to be fixed to dvcc3 test2 1 input test pin: set to open. test3 1 input test pin: set to open. test4 1 input test pin: set to open. cvcch 1 ? pin for supplying a high-frequency oscilla tor with power: 1.5 v power supply cvccl 1 ? pin for supplying a low-frequency osc illator with power: 3 v power supply cvss 1 ? oscillator gnd pin (0 v) dvcc15 3 ? power supply pin: 1.5 v power supply dvcc3 4 ? power supply pin: 3 v power supply dvss 5 ? power supply pin: gnd pin (0 v) davcc 1 ? power supply pin for the d/a converter: 2.5 v power supply if the d/a converter is not used , connect (fix) this pin to gnd. cvref 1 ? reference power supply pin for the d/a converter if the d/a converter is not used , connect (fix) this pin to gnd. dagnd 1 ? gnd pin (0 v) for the d/a converter connect this pin to gnd even if the d/a converter is not used. cvref0 1 ? pin for connecting a stabilizing capacitor to the d/a converter cvref1 1 ? pin for connecting a stabilizing capacitor to the d/a converter da0 1 output d/a converter 0 output pin da1 1 output d/a converter 1 output pin
tmp19a43 tmp19a43 (rev2.0) 2-9 2.4 pin names and power supply pins table 2-8 pin names and power supplies pin name power supply pin name power supply p0 dvcc3 pcst4-0 dvcc3 p1 dvcc3 dclk dvcc3 p2 dvcc3 eje dvcc3 p3 dvcc3 trst dvcc3 p4 dvcc3 tdi dvcc3 p5 dvcc3 tdo dvcc3 p6 dvcc3 tms dvcc3 p7 avcc3 tck dvcc3 p8 avcc3 dint dvcc3 p9 dvcc3 tovr/tsta dvcc3 pa dvcc3 busmd dvcc3 pb dvcc3 boot dvcc3 pc dvcc3 x1, x2 cvcch pd dvcc3 xt1, xt2 cvccl pe dvcc3 reset dvcc3 pf dvcc3 da0,1 davcc pg dvcc3 ph dvcc3 2.5 pin numbers and power supply pins table 2-9 pin numbers and power supplies power supply pin number voltage range dvcc15 j5, k13, n10 1.35 v to 1.65 v dvcc3 e11, h5 1.65 v to 3.6 v avcc3 f6 2.7 v to 3.6 v fvcc3 m13, n8 2.7 v to 3.6 v cvcch a16 1.35 v to 1.65 v cvccl b17 2.7 v to 3.6 v davcc e8 2.3 v to 2.7 v
tmp19a43 tmp19a43 (rev2.0)3-1 flash memory operation 3. flash memory operation this section describes the hardware configuration and operation of the flash memory. the feature of this device is that the internal rom of tmp19a43cdxbg is replaced by an internal flash memory. other configurations and functions of the device remain the same as with tmp19a43cdxbg. please refer to the tmp19a43cdxbg data sheet for functions not described in this section. 3.1 flash memory 3.1.1 features 1) memory size the tmp19a43fdxbg device contains 4m bits (512 kb) of flash memory. the memory area consists of 4 independent memory blocks (128 kb 4) to enable independent write access to each block. when the cpu is to access the internal flash memory, 32-bit data bus width is used. 2) flash memory access interleave access is used in this device. 3) write/erase time write time: 2 sec/chip (typ) 0.5 sec/128 kbyte (typ.) erase: 0.4 sec/chip (typ) 100 msec/128 kbyte (typ.) (note) the above values are theoretical va lues not including data transfer time. the write time per chip depends on the write method to be used by the user. 4) programming method the onboard programming mode is available for the user to program (rewrite) the device while it is mounted on the user's board. 4-1) user boot mode the user's original rewriting method can be supported. 4-2) single boot mode the rewriting method to use serial data transfer (toshiba's unique method) can be supported. rewriting method the flash memory included in this device is gene rally compliant with the applicable jedec standards except for some specific functions. th erefore, if the user is currently using an external flash memory device, it is easy to implement the functions into this device. furthermore, the user is not required to build his/her own programs to realize complicated write and erase functions because such functions are automatically performed using the circuits already built-in the flash memory chip. this device is also implemented with a read-protect function to inhibit reading flash memory data from any external writer device. on the other hand, rewrite protection is available only through command- based software programming; any hardware setting method to apply +12vdc is not supported. the above described protection function is automatically enabled when all the four area are configured for protection. when the user removes protection, the in ternal data is automatically erased before the protection is actually removed.
tmp19a43 tmp19a43 (rev2.0)3-2 flash memory operation jedec compliant functions modified, added, or deleted functions ? automatic programming ? automatic chip erase ? automatic block erase ? data polling/toggle bit block protect (only so ftware protection is supported) erase resume - suspend function automatic multiple block erase (supported to the chip level) 3.1.2 block diagram of the flash memory section fig. 3-1 block diagram of the flash memory section internal address bus rom controller/interleave control control a ddress data flash memory column decoder/sense amplifier data latch address latch erase block decoder control circuit (includes automatic sequence control) command register internal data bus internal control bus flash memory cell 512 kb row decoder
tmp19a43 tmp19a43 (rev2.0)3-3 flash memory operation 3.2 operation mode this device has three operation modes including the mode not to use the internal flash memory. table 3-1 operation modes operation mode operation details single chip mode after reset is cleared, it starts up from the internal flash memory. normal mode in this operation mode, two diffe rent modes, i.e., the mode to execute user application programs and the mode to rewrite the flash memory onboard the user?s card, are defined. the former is referred to as "normal mode" an d the latter "user boot mode." user boot mode the user can uniquely configur e the system to switch be tween these two modes. for example, the user can freely design the system such that the normal mode is selected when the port "00" is set to "1" and the user boot mode is selected when it is set to "0." the user should prepare a routine as part of the application program to make the decision on the selection of the modes. single boot mode after reset is cleared, it starts up from the in ternal boot rom (mask rom). in the boot rom, an algorithm to enable flash memory rewriting on the user?s set through the serial port of this device is programmed. by connecting to an exte rnal host computer through the serial port, the internal flash memory can be programmed by transferring data in accordance with predefined protocols. among the flash memory operation modes listed in the above table, the user boot mode and the single boot mode are the programmable modes. these two modes, the user boot mode and the single boot mode, are referred to as "onboard programming" modes wher e onboard rewriting of internal flash memory can be made on the user's card.
tmp19a43 tmp19a43 (rev2.0)3-4 flash memory operation either the single chip or single boot operation mode can be selected by externally setting the level of the boot input pin while the device is in reset status. after the level is set, the cpu starts operation in th e selected operation mode when the reset condition is removed. regarding the test0, test1, and boot pins, be sure not to change the levels during operation once the mode is selected. the mode setting method and the mode transition diagram are shown below: table 3-2 operation mode setting input pin operation mode reset boot single chip mode 0 to 1 1 single boot mode 0 to 1 0 fig. 3-2 mode transition diagram 3.2.1 reset operation to reset the device, ensure that the power supply voltage is within the operating voltage range, that the internal oscillator has been stabilized, and that the reset input is held at "0" for a minimum duration of 12 system clocks (2.4 s with 40mhz operation; the "1/8" clock gear mode is applied after reset). (note 1) regarding power-on reset of devices with internal flash memory; for devices with internal flash memory, it is necessary to apply "0" to the reset inputs upon power on for a minimum duration of 500 microseconds regardless of the operating frequency. (note 2) while flash programming or deletion is in progress, at least 0.5 microseconds of reset period is required regardless of the system clock frequency. onboard programming mode user to set the switch method single chip mode reset state normal mode user boot mode single boot mode
tmp19a43 tmp19a43 (rev2.0)3-5 flash memory operation 3.2.2 dsu (ejtag) - probe interface this interface is used when the ds u probe is used in debugging. th is is the dedicated interface for connection to the dsu probe. please refer to the op eration manual for the dsu probe you are going to use for details of debugging procedures to use the dsu probe. here, the function to enable/disable the dsu probe in the dsu (ejtag) mode is described. 1) protect function this device allows use of on-board dsu probes for debugging. to facilitate this, the device is implemented with a protection function to prevent easy reading of the internal flash memory by a third party other than the authorized user. by enabling the protection function, it becomes impossible to read the internal flash memory from a dsu probe. use this function together with the protection function of the internal flash memory itself as described later. 2) dsu probe enable/disable function this device allows use of on-board dsu probes for debugging operations. to facilitate this, the device is implemented with the "dsu probe inhibit" function (hereafter referred to as the "dsu inhibit" function ) to prevent easy reading of the internal flash memory by a third party other than the authorized user. by enabling the dsu inhi bit function, use of any dsu probe becomes impossible. 3) dsu enable (enables use of dsu probes for debugging) in order to prevent the dsu inhibit function from being accidentally removed by system runaway, etc., the method to cancel the dsu inhibit function is in double protection structure so it is necessary to set seqmod to "0" and also write the protect code "0x0000_00c5" to the dsu protect control register seqcnt to cancel the function. then, debugging to use a dsu probe can be allowed. while power to the device is still applied, setting seqmod to "1" and writing "0x0000_00c5" to the seqcnt register will enable the protection function again. table 3-3 dsu protect mode register 7 6 5 4 3 2 1 0 seqmod bit symbol dsuoff (0xffff_e510) read/write r r/w after reset 0 1 function always reads "0." 1: dsu disable 0: dsu available 15 14 13 12 11 10 9 8 bit symbol read/write r after reset 0 function always reads "0." 23 22 21 20 19 18 17 16 bit symbol read/write r after reset 0 function 31 30 29 28 27 26 25 24 bit symbol read/write r after reset 0 function always reads "0." (note) this register must be 32-bit accessed. (note)this register is in itialized only by power-on reset. it is not initialized in reset usually. flash
tmp19a43 tmp19a43 (rev2.0)3-6 flash memory operation table 3-4 dsu protect control register 7 6 5 4 3 2 1 0 seqcnt bit symbol (0xffff_e514) read/write w after reset function write "0x0000_00c5." 15 14 13 12 11 10 9 8 bit symbol read/write w after reset function write "0x0000_00c5." 23 22 21 20 19 18 17 16 bit symbol read/write w after reset function write "0x0000_00c5." 31 30 29 28 27 26 25 24 bit symbol read/write w after reset function write "0x0000_00c5." (note 1) this register must be 32-bit accessed. 4) example use by the user an example to use a dsu probe together with this function is shown as follows: figure 3-3 example use of dsu inhibit function [dsu-probe available] dsu can be used until power is turned off. power on dsu availability decision program (to be prepared by the user) dsu inhibit cleared? clear dsu inhibit function by writing to seqmod and seqcn [dsu-probe disabled] dsu remains unavailable y n external ports data, etc. protection bit set to 1111 y n [dsu-probe available] clear rom protection (only for internal rom/flash)
tmp19a43 tmp19a43 (rev2.0)3-7 flash memory operation (1-a) method 1: storing a programming routine in the flash memory (1) determine the conditions (e.g., pin states) required for the flash memory to enter user boot mode and the i/o bus to be used to transfer new program code. create hardware and software accordingly. before installing the tmp19a43fdxbg on a printed circuit board, write the following program routines into an arbitrary flash block using programming equipment. ? mode judgment routine: code to determine whether or not to switch to user boot mode ? programming routine: code to download new program code from a host controller and re- program the flash memory ? copy routine: code to copy the flash programming routine from the tmp19a43fdxbg flash memory to either the tmp19a43fdxbg on-chip ram or external memory device. (2) after reset is released, the reset procedure determines whether to put the tmp19a43fdxbg flash memory in user boot mode. if mode switching conditions are met, the flash memory enters user boot mode. (all interrupts including nmi must be globally disabled while in user boot mode.) tmp19a43fdxbg flash memory ram [reset procedure] ( a ) mode jud g ment routine old application program code host controlle r new application program code i/o (b) programming routine (c) copy routine tmp19a43fdxbg flash memory ram [reset procedure] old application program code host controlle r new application program code i/o (a) mode judgment routine (b) programming routine (c) copy routine 0 1 reset conditions for entering user boot mode (defined by the user) user boot mode
tmp19a43 tmp19a43 (rev2.0)3-8 flash memory operation (3) once user boot mode is entered, execute the copy routine to copy the flash programming routine to either the tmp19a43fdxbg on-chip ram or an external memory device. (in the following figure, the on-chip ram is used.) (4) jump program execution to the flash programming routine in the on-chip ram to erase a flash block containing the old application program code. tmp19a43fdxbg flash memory ram [reset procedure] (a) mode judgment routine old application program code host controller new application program code i/o (b) programming routine (c) copy routine (b) programming routine tmp19a43fdxbg flash memory ram [reset procedure] (a) mode judgment routine host controlle r new application program code i/o (b) programming routine (c) copy routine (b) programming routine erased
tmp19a43 tmp19a43 (rev2.0)3-9 flash memory operation (5) continue executing the flash programming routine to download new program code from the host controller and program it into the erased flash bl ock. once programming is complete, turn on the protection of that flash block. (6) drive reset low to reset the tmp19a43fdxbg. upon reset, the on-chip flash memory is put in normal mode. after reset is released, the cpu will start executing the new application program code. tmp19a43fdxbg flash memory ram [reset procedure] (a) mode judgment routine new application program code host controlle r new application program code i/o (b) programming routine (c) copy routine (b) programming routine tmp19a43fdxbg flash memory ram [reset procedure] (a) mode judgment routine new application program code e host controlle r (i/o) (b) programming routine (c) copy routine 0 1 reset set to normal mode
tmp19a43 tmp19a43 (rev2.0)3-10 flash memory operation (1-b) method 2: transferring a progra mming routine from an external host (1) determine the conditions (e.g., pin states) required for the flash memory to enter user boot mode and the i/o bus to be used to transfer new program code. create hardware and software accordingly. before installing the tmp19a43fdxbg on a printed circuit board, write the following program routines into an arbitrary flash block using programming equipment. mode judgment routine: code to determine whether or not to switch to user boot mode transfer routine: code to download new program code from a host controller also, prepare a programming routine on the host controller: programming routine: code to download new program code from an external host controller and re-program the flash memory (2) after reset is released, the reset procedure determ ines whether to put the tmp19a43fdxbg flash memory in user boot mode. if mode switching conditions are met, the flash memory enters user boot mode. (all interrupts including nmi must be globally disabled while in user boot mode.) tmp19a43fdxbg flash memory ram [reset procedure] (a) mode judgment routine old application program code host controlle r new application program code i/o (b) transfer routine (c) programming routine tmp19a43fdxbg host controller i/o 0 1 reset conditions for entering user boot mode (defined by the user) flash memory ram [reset procedure] ( a ) mode jud g ment routine old application program code ( b ) transfer routine new application program code (c) programming routine
tmp19a43 tmp19a43 (rev2.0)3-11 flash memory operation (3) once user boot mode is entered, execute the tr ansfer routine to download the flash programming routine from the host controller to either the tmp19a43fdxbg on-chip ram or an external memory device. (in the following figure, the on-chip ram is used.) (4) jump program execution to the flash programming routine in the on-chip ram to erase a flash block containing the old application program code. tmp19a43fdxbg flash memory ram [reset procedure] (a) mode judgment routine old application program code host controlle r new application program code i/o ( b ) transfer routine (c) programming routine ( c ) pro g rammin g routine tmp19a43fdxbg flash memory ram [reset procedure] (a) mode judgment routine host controller new application program code i/o (b) transfer routine (c) programming routine ( c ) pro g rammin g routine erased
tmp19a43 tmp19a43 (rev2.0)3-12 flash memory operation (5) continue executing the flash programming routine to download new program code from the host controller and program it into the erased flash bl ock. once programming is complete, turn on the protection of that flash block. drive reset low to reset the tmp19a43fdxbg. upon reset, the on-chip flash memory is put in normal mode. after reset is released, the cpu will start executing the new application program code. tmp19a43fdxbg flash memory ram [reset procedure] (a) mode judgment routine new application program code host controlle r new application program code i/o (b) transfer routine (c) programming routine (c) programming routine tmp19a43fdxbg host controlle r i/o 0 1 reset set to normal mode flash memory ram [reset procedure] (a) mode judgment routine new application program code (b) transfer routine
tmp19a43 tmp19a43 (rev2.0)3-13 flash memory operation 3.3 single boot mode in single boot mode, the flash memory can be re-programmed by using a program contained in the tmp19a43fdxbg on-chip boot rom. this boot rom is a masked rom. when single boot mode is selected upon reset, the boot rom is mapped to the addr ess region including the interrupt vector table while the flash memory is mapped to an address region different from it. single boot mode allows for serial programming of the flash memory. channel 0 of the sio (sio0) of the tmp19a43fdxbg is connected to an external host controller. via this serial link, a programming routine is downloaded from the host controller to the tmp19a43fdxbg on-chip ram. then, the flash memory is re- programmed by executing the programming routine. the host sends out both commands and programming data to re-program the flash memory. communications between the sio0 and the host must follow the protocol described later. to secure the contents of the flash memory, the validity of the application?s password is checked before a programming routine is downloaded into the on-chip ram. if password matching fails, the transfer of a programming routine itself is aborted. as in the case of user boot mode, all interrupts including the nonmaskable (nmi) interrupt must be globally disabled in single boot mode while the flash memory is being erased or programmed. in single boot mode, the boot-rom programs are executed in normal mode. once re-programming is complete, it is recommended to protect relevant flash blocks from accidental corruption during subsequent single-chip (normal mode) operations. for a detailed description of the erase and program sequence, refer to on-board programming and erasure.
tmp19a43 tmp19a43 (rev2.0)3-14 flash memory operation (2-a) general procedure: using the program in the on-chip boot rom (1) the flash block containing the older version of the program code need not be erased before executing the programming routine. since a programming routine and programming data are transferred via the sio0, the sio0 must be connected to a ho st controller. prepare a programming routine on the host controller. (2) reset the tmp19a43fdxbg with the mode setting pins held at appropriate logic values, so that the cpu re-boots from the on-chip boot rom. th e 12-byte password transferred from the host controller is first compared to the contents of sp ecial flash memory locations. (if the flash block has already been erased, the password is 0xffff.) tmp19a43fdxbg flash memory ram old application program code (or erased state) host controlle r new application program code i/o (a) programming routine boot rom sio0 tmp19a43fdxbg host controlle r i/o 0 1 reset conditions for entering single boot mode new application program code (a) programming routine flash memory ram old application program code (or erased state) boot rom sio0 boot mode
tmp19a43 tmp19a43 (rev2.0)3-15 flash memory operation if the password was correct, the boot program down loads, via the sio0, th e programming routine from the host controller into the on-chip ram of the tmp19a43fdxbg. the programming routine must be stored in the address range 0xfffd_6000 ? 0xfffd_efff. (3) the cpu jumps to the programming routine in the on-chip ram to erase the flash block containing the old application program code. the block erase or chip erase command may be used. tmp19a43fdxbg flash memory ram old application program code (or erased state) host controller new application program code i/o (a) programming routine boot rom sio0 (a) programming routine tmp19a43fdxbg flash memory ram host controller new application program code i/o (a) programming routine boot rom sio0 (a) programming routine erased
tmp19a43 tmp19a43 (rev2.0)3-16 flash memory operation next, the programming routine downloads new application program code from the host controller and programs it into the erased flash block. once programming is complete, protection of that flash block is turned on. it is not allowed to move program control from the programming routine back to the boot rom. in the example below, new program code comes from the same host controller via the same sio channel as for the programming routine. however, once the programming routine has begun to execute, it is free to change the tr ansfer path and the source of th e transfer. create board hardware and a programming routine to suit your particular needs. (4) when programming of the flash memory is complete, power off the board and disconnect the cable leading from the host to the target board. turn on the power again so that the tmp19a43fdxbg re-boots in single-chip (normal) mode to execute the new program. tmp19a43fdxbg flash memory ram new application program code host controller new application program code i/o (a) programming routine boot rom sio0 (a) programming routine tmp19a43fdxbg host controlle r 0 1 reset set to single-chip (normal) mode flash memory ram new application program code boot rom sio0
tmp19a43 tmp19a43 (rev2.0)3-17 flash memory operation 3.3.1 configuring for single boot mode for on-board programming, boot the tmp19a43fdxbg in single boot mode, as follows: boot = 0 reset = 0 1 set the reset input at logic 0, and the bw0, bw1 and boot inputs at the logic values shown above, and then release reset (high). 3.3.2 memory map figure 3.1 shows a comparison of the memory maps in normal and single boot modes. in single boot mode, the on-chip flash memory is mapped to physical addresses (0x4000_0000 through 0x4007_ffff), virtual addresses (0x0000_0000 throug h 0x0007_ffff), and the on-chip boot rom is mapped to physical addresses 0x1fc0_0000 through 0x1fc0_1fff. figure 3.1 memory maps for normal and single boot modes (physical addresses) on-chip peripherals normal mode single boot mode 0x1fc0_1fff 0x1fc0_0000 0x0000_0000 0xffff_ffff 0xffff_dfff 0xffff_8000 0xff3f_ffff 0xff20_0000 0xc000_0000 0x400f_ffff 0x4000_0000 0x1fc7_ffff 0x1fc0_0500 0x1fc0_0000 0x2000_0000 0x0000_0000 0xff00_0000 0xbf00_0000 0xffff_ffff 0xffff_dfff 0xffff_8000 0xff3f_ffff 0xff20_0000 0xc000_0000 0x4007_ffff 0x4000_0000 0x2000_0000 0xff00_0000 0xbf00_0000 on-chip ram (24 kb) (reserved) used for debugging (reserved) (reserved) (reserved) on-chip rom shadow inaccessible (512 mb) user program area maskable interrupt area exception vector area on-chip peripherals on-chip ram (24 kb) (reserved) used for debugging (reserved) (reserved) (reserved) on-chip flash rom inaccessible (512 mb) boot rom (6 kb) internal rom
tmp19a43 tmp19a43 (rev2.0)3-18 flash memory operation 3.3.3 interface specification in single boot mode, an sio channel is used for communications with a programming controller. both uart (asynchronous) and i/o interface (syn chronous) modes are supported. the communication formats are shown below. in the subsections that follow, virtual addresses are indicated, unless otherwise noted. ? uart mode communication channel: sio channel 0 (sio0) transfer mode: uart (asynchronous) mode, full-duplex data length: 8 bits parity bits: none stop bits: 1 baud rate: arbitrary baud rate ? i/o interface mode communication channel: sio channel 0 (sio0) transfer mode: i/o interface mode, half-duplex synchronization clock (sclk0): input handshaking signal: p67 configured as an output baud rate: arbitrary baud rate table 3.1 required pin connections interface pin uart mode i/o interface mode dvcc15 required required power supply pins dvss required required mode-setting pin boot required required reset pin reset required required txd0 required required rxd0 required required sclk0 not required required (input mode) communication pins p67 not required required (output mode) 3.3.4 data transfer format the host controller is to issue one of the commands listed in table 3.2 to the target board. table 3.3 to table 3.5 illustrate the sequence of two-way communications that should occur in response to each command. table 3.2 single boot mode commands code command 10h ram transfer 20h show flash memory sum 30h show product information
tmp19a43 tmp19a43 (rev2.0)3-19 flash memory operation table 3.3 transfer format for the ram transfer command byte data transferred from the controller to the tmp19a43fdxbg baud rate data transferred from the tmp19a43fdxbg to the controller boot rom 1st byte serial operation mode and baud rate for uart mode 86h for i/o interface mode 30h desired baud rate (note 1) ? 2nd byte ? ack for the serial operation mode byte for uart mode normal acknowledge 86h (the boot program aborts if the baud rate is can not be set correctly.) for i/o interface mode normal acknowledge 30h 3rd byte command code (10h) ? 4th byte ? ack for the command code byte (note 2) normal acknowledge 30h negative acknowledge x1h communication error x8h 5th byte thru 16th byte password sequence (12 bytes) (0x4000_0474 thru 0x4000_047f) ? 17th byte checksum value for bytes 5?16 ? 18th byte ? ack for the checksum byte (note 2) normal acknowledge 10h negative acknowledge x1h communication error x8h 19th byte ram storage start address (bits 31?24) ? 20th byte ram storage start address (bits 23?16) ? 21st byte ram storage start address (bits 15?8) ? 22nd byte ram storage start address (bits 7?0) ? 23rd byte ram storage byte count (bits 15?8) ? 24th byte ram storage byte count (bits 7?0) ? 25th byte checksum value for bytes 19?24 ? 26th byte ? ack for the checksum byte (note 2) normal acknowledge 10h negative acknowledge x1h communication error x8h 27th byte thru mth byte ram storage data ? (m + 1)th byte checksum value for bytes 27?m ? (m + 2)th byte ? ack for the checksum byte (note 2) normal acknowledge 10h non-acknowledge x1h communications error x8h ram (m + 3)th byte ? jump to ram storage start address note 1: in i/o interface mode, the baud rate for the transfers of the first and second bytes must be 1/16 of the desired baud rate. note 2: in case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (3rd byte). in i/o interface mode, if a communication error occurs, a negative acknowledge does not occur. note 3: the 19th to 25th bytes must be within the ram address range 0xfffd_8000?0xffff_cfff
tmp19a43 tmp19a43 (rev2.0)3-20 flash memory operation table 3.4 transfer format for the show flash memory sum command byte data transferred from the controller to the tmp19a43fdxbg baud rate data transferred from the tmp19a43fdxbg to the controller boot rom 1st byte serial operation mode and baud rate for uart mode 86h for i/o interface mode 30h desired baud rate (note 1) ? 2nd byte ? ack for the serial operation mode byte for uart mode normal acknowledge 86h (the boot program aborts if the baud rate can not be set correctly.) for i/o interface mode normal acknowledge 30h 3rd byte command code (20h) ? 4th byte ? ack for the command code byte (note 2) normal acknowledge 20h negative acknowledge x1h communication error x8h 5th byte ? sum (upper byte) 6th byte ? sum (lower byte) 7th byte ? checksum value for bytes 5 and 6 8th byte (wait for the next command code.) ? note 1: in i/o interface mode, the baud rate for the transfers of the first and second bytes must be 1/16 of the desired baud rate. note 2: in case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (3rd byte). in i/o interface mode, if a communication error occurs, a negative acknowledge does not occur.
tmp19a43 tmp19a43 (rev2.0)3-21 flash memory operation table 3.5 transfer format for the show product information command (1/2) byte data transferred from the controller to the tmp19a43fdxbg baud rate data transferred from the tmp19a43fdxbg to the controller boot rom 1st byte serial operation mode and baud rate for uart mode 86h for i/o interface mode 30h ? 2nd byte ? desired baud rate (note 1) ack for the serial operation mode byte for uart mode normal acknowledge 86h (the boot program aborts if the baud rate can not be set correctly.) for i/o interface mode normal acknowledge 30h 3rd byte command code (30h) ? 4th byte ? ack for the command code byte (note 2) normal acknowledge 10h negative acknowledge x1h communication error x8h 5th byte ? flash memory data (at address 0x4000_0470) 6th byte ? flash memory data (at address 0x4000_0471) 7th byte ? flash memory data (at address 0x4000_0472) 8th byte ? flash memory data (at address 0x4000_0473) 9th byte thru 20th byte ? product name (12-byte ascii code) ?tx19a43fd? from the 9th byte 21st byte thru 24th byte ? password comparison start address (4 bytes) 74h, 04h, 00h and 00h from the 21st byte 25th byte thru 28th byte ? ram start address (4 bytes) 00h, 80h, ffh and ffh from the 25th byte 29th byte thru 32nd byte ? dummy data (4 bytes) ffh, 8fh, ffh and ffh from the 29th byte 33rd byte thru 36th byte ? ram end address (4 bytes) ffh, dfh, ffh and ffh from the 33rd byte 37th byte thru 40th byte ? dummy data (4 bytes) 00h,90h, ffh and ffh from the 37th byte 41st byte thru 44th byte ? dummy data (4 bytes) ffh, cfh, ffh and ffh from the 41st byte 45th byte thru 46th byte ? fuse information (2 bytes) 00h and 00h from the 45th byte 47th byte thru 50th byte ? flash memory start address (4 bytes) 00h, 00h, 00h and 00h from the 47th byte 51st byte thru 54th byte ? flash memory end address (4 bytes) ffh, ffh, 07h and 00h from the 51st byte 55th byte thru 56th byte ? flash memory block count (2 bytes) 00h and 00h from at the 55th byte
tmp19a43 tmp19a43 (rev2.0)3-22 flash memory operation table 3.5 transfer format for the show product information command (2/2) byte data transferred from the controller to the tmp19a43fdxbg baud rate data transferred from the tmp19a43fdxbg to the controller 57th byte thru 60th byte ? start address of a group of the same-size flash blocks (4 bytes) 00h, 00h, 00h and 00h from the 57th byte boot rom 61st byte thru 64th byte ? size (in halfwords) of the same-size flash blocks (4 bytes) 00h, 00h, 01h and 00h from the 61st byte 65th byte ? number of flash blocks of the same size (1 byte) 04h 66th byte ? checksum value for bytes 5 to 65 67th byte (wait for the next command code.) ? 3.3.5 overview of the boot program commands when single boot mode is selected, the boot program is automatically executed on startup. the boot program offers these three commands, the details of which are provided on the following subsections. ? ram transfer command the ram transfer command stores program code transferred from a host controller to the on- chip ram and executes the program once the transfer is successfu lly completed. the maximum program size is 36 kbytes. the ram storage start address must be within the range. the ram transfer command can be used to download a flash programming routine of your own; this provides the ability to control on-board programming of the flash memory in a unique manner. the programming routine must utilize the flash memory command sequences described in section 3.6.17 before initiating a transfer, the ram transfer command checks a password sequence coming from the controller against that stored in the flash memory. if they do not match, the ram transfer command aborts. once the ram transfer command is comple te, the whole on-chip ram is accessible. ? show flash memory sum command the show flash memory sum command adds the contents of the 512 kbytes of the flash memory together. the boot program does not provide a command to read out the contents of the flash memory. instead, the flash memory sum command can be used for software revision management. ? show product information command the show product information command provides the product name, on-chip memory configuration and the like. this command also reads out the contents of the flash memory locations at addresses 0x0000_03f0 through 0x0000_03f3. in addition to the show flash memory sum command, these locations can be used for software revision management. note 1: in i/o interface mode, the baud rate for the transfers of the first and second bytes must be 1/16 of the desired baud rate. note 2: in case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (3rd byte). in i/o interface mode, if a communication error occurs, a negative acknowledge does not occur.
tmp19a43 tmp19a43 (rev2.0)3-23 flash memory operation 3.3.6 ram transfer command see table 3.3. (5) the 1st byte specifies which one of the two serial operation modes is used. for a detailed description of how the serial operation mode is determined, see section 3.3.10. if it is determined as uart mode, the boot program then checks if the sio0 is programmable to the baud rate at which the 1st byte was transferred. during the fi rst-byte interval, the rxe bit in the sc0mod register is cleared. ? to communicate in uart mode send, from the controller to the target board, 86h in uart data format at the desired baud rate. if the serial operation mode is determined as uart, then the boot progr am checks if the sio0 can be programmed to the baud rate at which the fi rst byte was transferred. if that baud rate is not possible, the boot program aborts, disabling any subsequent communications. ? to communicate in i/o interface mode send, from the controller to the target board, 30 h in i/o interface data format at 1/16 of the desired baud rate. also send the 2nd byte at the same baud rate. then send all subsequent bytes at a rate equal to the desired baud rate. in i/o interface mode, the cpu sees the serial r eceive pin as if it were a general input port in monitoring its logic transitions. if the baud rate of the incoming data is high or the chip?s operating frequency ishigh, the cpu may not be able to keep up with the speed of logic transitions. to prevent such situations, the 1st a nd 2nd bytes must be transferred at 1/16 of the desired baud rate; then the boot program calculates 16 times that as the desired baud rate. when the serial operation mode is determined as i/o interface mode, the sio0 is configured for sclk input mode. beginning with the third byte, the controller must ensure that its ac timing restrictions are satisfied at the selected baud rate. in the case of i/o interface mode, the boot program does not check the receive error fl ag; thus there is no such thing as error acknowledge (x8h). (6) the 2nd byte, transmitted from the target board to the controller, is an acknowledge response to the 1st byte. the boot program echoes back the first byte: 86h for uart mode and 30h for i/o interface mode. ? uart mode if the sio0 can be programmed to the baud rate at which the 1st byte was transferred, the boot program programs the br0cr and sends back 86h to the controller as an acknowledge. if the sio0 is not programmable at that baud rate, the boot program simply aborts with no error indication. following the 1st byte, the controller should allow for a time-out period of five seconds. if it does not receive 86h within th e alloted time-out period, the controller should give up the communication. the boot program sets the rxe bit in the sc0mod register to enable reception before loading the sio transmit buffer with 86h.
tmp19a43 tmp19a43 (rev2.0)3-24 flash memory operation ? i/o interface mode the boot program programs the sc0mod0 and sc0cr registers to configure the sio0 in i/o interface mode (clocked by the rising edge of sclk0), writes 30h to the sc0buf. then, the sio0 waits for the sclk0 signal to come from the controller. following the transmission of the 1st byte, the controller should send the sclk clock to the target board after a certain idle time (several microseconds). this must be done at 1/16 the desire baud rate. if the 2nd byte, which is from the target board to the controller, is 30h, then the controller should take it as a go-ahead. the controller must then delivers the 3rd byte to the target board at a rate equal to the desired baud rate. the boot program sets the rxe bit in the sc0mod register to enable reception before loading the si o transmit buffer with 30h. ? (7) the 3rd byte, which the target boa rd receives from the controller, is a command. the code for the ram transfer command is 10h. ? (8) the 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. before sending back the acknowledge response, the boot program checks for a receive error. if there was a receive erro r, the boot program transmits x8h an d returns to the state in which it waits for a command again. in this case, the up per four bits of the ac knowledge response are undefined ? they hold the same values as the upper four bits of the previously issued command. when the sio0 is configured for i/o interf ace mode, the boot program does not check for a receive error. if the 3rd byte is equal to any of the command codes listed in table 3.2, the boot program echoes it back to the controller. when the ram transfer command was received, the boot program echoes back a value of 10h and then bran ches to the ram transf er routine. once this branch is taken, a password check is done. password checking is detailed in section 3.3.11. if the 3rd byte is not a valid command, the boot program sends back x1h to the controller and returns to the state in which it waits for a command ag ain. in this case, the upper four bits of the acknowledge response are undefined ? they hold the same values as the upp er four bits of the previously issued command. ? (9) the 5th to 16th bytes, which the target board recei ves from the controller, are a 12-byte password. the 5th byte is compared to the contents of address 0x0000_03f4 in the flash memory; the 6th byte is compared to the contents of address 0x0000_03f5 in the flash memory; likewise, the 16th byte is compared to the contents of address 0x0000_03ff in the flash memory. if the password checking fails, the ram tr ansfer routine sets th e password error flag. ? (10) the 17th byte is a checksum value for the password sequence (5th to 16th bytes). to calculate the checksum value for the 12-byte password, add the 12 bytes together, drop the carries and take the two?s complement of the total sum. transmit this checksum value from the controller to the target board. the checksum calculation is described in details in section 3.3.13.
tmp19a43 tmp19a43 (rev2.0)3-25 flash memory operation (11) the 18th byte, transmitted from the target board to the controller, is an acknowledge response to the 5th to 17th bytes. first, the ram transfer routine checks for a receive error in the 5th to 17th bytes. if there was a receive error, the boot program sends back 18h and returns to the state in which it waits for a command (i.e., the 3rd byte) again. in this case, the upper four bits of the acknowledge response are the same as those of the previously issued co mmand (i.e., all 1s). when the sio0 is configured for i/o interface mode, the ram transfer r outine does not check for a receive error. next, the ram transfer routine performs the checksum operation to ensure data integrity. adding the series of the 5th to 17th bytes must result in zero (with the carry dropped ). if it is not zero, one or more bytes of data has been corrupted. in case of a checksum error, the ram transfer routine sends back 11h to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. finally, the ram transfer routine examines the result of the password check. the following two cases are treated as a password error. in these cases, the ram transfer r outine sends back 11h to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. ? irrespective of the result of the password comparison, all of the 12 bytes of a password in the flash memory are the same value other than ffh. ? not all of the password bytes transmitted from the controller matched those contained in the flash memory. when all the above checks have been successful, the ram transfer routine returns a normal acknowledge response (10h) to the controller. (12) the 19th to 22nd bytes, which the target board receives from th e controller, indicate the start address of the ram region where subsequent data (e.g., a flash programming routine) should be stored. the 19th byte corresponds to bits 31?24 of the address, and the 22nd byte corresponds to bits 7?0 of the address. (13) the 23rd and 24th bytes, which the target board receives from the controller, indicate the number of bytes that will be transferred from the controller to be stored in the ram. the 23rd byte corresponds to bits 15?8 of the number of bytes to be transferred, and the 24th byte corresponds to bits 7?0 of the number of bytes. (14) the 25th byte is a checksum value for the 19th to 24th bytes. to calculate the checksum value, add all these bytes together, drop the carries and take the two?s complement of the total sum. transmit this checksum value from the controller to the ta rget board. the checksum calculation is described in details in section 3.3.13. (15) the 26th byte, transmitted from the target board to the controller, is an acknowledge response to the 19th to 25th bytes of data.first, the ram transf er routine checks for a r eceive error in the 19th to 25th bytes. if there was a receive error, the ram transfer routine sends back 18h and returns to the state in which it waits for a command (i.e., the 3r d byte) again. in this case, the upper four bits of the acknowledge response are the same as those of the previously issued command (i.e., all 1s). when the sio0 is configured for i/o interface m ode, the ram transfer rou tine does not check for a receive error. next, the ram transfer routine performs the checksum operation to ensure data integrity. adding the series of the 19th to 25th bytes must result in zero (with the carry dropped). if it is not zero, one or more bytes of data has been corrupted. in case of a checksum er ror, the ram transfer routine sends back 11h to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again.
tmp19a43 tmp19a43 (rev2.0)3-26 flash memory operation ? the ram storage start address must be within the range 0xfffd_6000?0xfffd_efff. when the above checks have been successful, the ram transfer rou tine returns a normal acknowledge response (10h) to the controller. (16) the 27th to mth bytes from the controller are stored in the on-chip ram of the tmp19a43fdxbg. storage begins at the address specified by the 19th?22nd bytes and continues for the number of bytes specified by the 23rd?24th bytes. (17) the (m+1)th byte is a checksum value. to calculat e the checksum value, add the 27th to mth bytes together, drop the carries and take the two?s complement of the total sum. transmit this checksum value from the controller to the target board. the checksum calculation is described in details in section 3.3.13. (18) the (m+2)th byte is a acknowledge response to the 27th to (m+1)th bytes. first, the ram transfer routine ch ecks for a receive error in the 27th to (m+1)th bytes. if there was a receive error, the ram transf er routine sends back 18h and re turns to the state in which it waits for a command (i.e., the 3rd byte) again. in th is case, the upper four bits of the acknowledge response are the same as those of the previously issued command (i.e., all 1s). when the sio0 is configured for i/o interface mode, the ram transfer routine does not check for a receive error. (19) next, the ram transfer routine pe rforms the checksum operation to ensure data integrity. adding the series of the 27th to (m+1)th bytes must resu lt in zero (with the carry dropped). if it is not zero, one or more bytes of data has been corrupted. in case of a checksum error, the ram transfer routine sends back 11h to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. when the above checks have been successful, the ram transfer routine returns a normal acknowledge response (10h) to th e controller. if the (m+2)th byte was a normal acknowledge response, a branch is made to the address specified by the 19th to 22nd bytes in 32- bit isa mode. 3.3.7 show flash memory sum command see table 3.4. (20) the processing of the 1st and 2nd bytes are the same as for the ram transfer command. (21) the 3rd byte, which the target board receives from the controller, is a co mmand. the code for the show flash memory sum command is 20h. (22) the 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. before sending back the acknowledge response, the boot program checks for a receive error. if there was a receive erro r, the boot program transmits x8h and returns to the state in which it waits for a command again. in this case, the up per four bits of the ac knowledge response are undefined ? they hold the same values as the upper four bits of the previously issued command. when the sio0 is configured for i/o interf ace mode, the boot program does not check for a receive error. if the 3rd byte is equal to any of the command codes listed in table 3.2 on page 3-18, the boot program echoes it back to the controller. when the show flash memory sum command was received, the boot program echoe s back a value of 20h and then branches to the show flash memory sum routine.
tmp19a43 tmp19a43 (rev2.0)3-27 flash memory operation if the 3rd byte is not a valid command, the boot program sends back x1h to the controller and returns to the state in which it waits for a command ag ain. in this case, the upper four bits of the acknowledge response are undefined ? they hold the same values as the upp er four bits of the previously issued command. (23) the show flash memory sum routine adds all the bytes of the flash memory together. the 5th and 6th bytes, transmitted from the target board to the controller, indicate the upper and lower bytes of this total sum, respectively. for details on sum calculation, see section 3.3.12. (24) the 7th byte is a checksum value for the 5th and 6th bytes. to calculate the checksum value, add the 5th and 6th bytes together, drop the carry and take the two?s complement of the sum. transmit this checksum value from the c ontroller to the target board. (25) the 8th byte is the next command code. 3.3.8 show product information command see table 3.5. (26) the processing of the 1st and 2nd bytes are the same as for the ram transfer command. (27) the 3rd byte, which the target board receives from the controller, is a co mmand. the code for the show product information command is 30h. (28) the 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. before sending back the acknowledge response, the boot program checks for a receive error. if there was a receive erro r, the boot program transmits x8h and returns to the state in which it waits for a command again. in this case, the up per four bits of the ac knowledge response are undefined ? they hold the same values as the upper four bits of the previously issued command. when the sio0 is configured for i/o interf ace mode, the boot program does not check for a receive error. if the 3rd byte is equal to any of the command codes listed in table 3.2 on page 3-18, the boot program echoes it back to the controller. when the show flash memory sum command was received, the boot program echoes back a value of 30h and then branch es to the show flash memory sum routine. if the 3rd byte is not a valid command, the boot program sends back x1h to the controller and returns to the state in which it waits for a command ag ain. in this case, the upper four bits of the acknowledge response are undefined ? they hold the same values as the upp er four bits of the previously issued command. (29) the 5th to 8th bytes, transmitted from the target board to the controller, are the data read from addresses 0x0000_03f0?0x0000_03f3 in the flash memory. software version management is possible by storing a software id in these locations. (30) the 9th to 20th bytes, transmitted from the target board to the controller, indicate the product name, which is ?tx19a43fd_ _ _? in ascii code (where _ is a space).
tmp19a43 tmp19a43 (rev2.0)3-28 flash memory operation (31) the 21st to 24th bytes, transmitted from the target board to the controller, indicate the start address of the flash memory area containing th e password, i.e., f4h, 03h, 00h, 00h. (32) the 25th to 28th bytes, transmitted from the target board to the controller, indicate the start address of the on-chip ram, i.e., 00h, 60h, fdh, ffh. (33) the 29th to 32nd bytes, transmitted from the targ et board to the controlle r, are dummy data (ffh, 6fh, fdh, ffh). (34) the 33rd to 36th bytes, transmitted from the target board to the controller, indicate the end address of the on-chip ram, i.e., ffh, ffh, fdh, ffh. (35) the 37th to 40th bytes, transmitted from the targ et board to the controller, are 00h, 70h, fdh and ffh. the 41st to 44th bytes, transmitted from the target board to the controller, are ffh, efh, fdh and ffh. (36) the 45th and 46th bytes, transmitted from the target board to the controller, indicate the presence or absence of the security and protect bits and whether the flash memory is divided into blocks. bit 0 indicates the presence or absence of the security b it; it is 0 if the security bit is available. bit 1 indicates the presence or absence of the protect bits ; it is 0 if the protect bits are available. if bit 2 is 0, it indicates that the flash memory is divided into blocks. the remaining bits are undefined. the 45th and 46th bytes are 01h, 00h. (37) the 47th to 50th bytes, transmitted from the target board to the controller, indicate the start address of the on-chip flash memory, i.e., 00h, 00h, 00h, 00h. (38) the 51st to 54th bytes, transmitted from the target board to the controller, indicate the end address of the on-chip flash memory, i.e., ffh, ffh, 0fh, 00h. (39) the 55th to 56th bytes, transmitted from the target board to the controller, indicate the number of flash blocks available, i.e., 08h, 00h. (40) the 57th to 92nd bytes, transmitted from the target board to the controller, contain information about the flash blocks. flash blocks of the same size are treated as a grou p. information about the flash blocks indicate the start address of a group, the size of the blocks in that group (in halfwords) and the number of the blocks in that group. the 57th to 65th bytes are the information about the 128-kbyte blocks (block 0 to block 7). see table 3.5 for the values of bytes transmitted. (41) the 66th byte, transmitted from the target board to the controller, is a checksum value for the 5th to 65th bytes. the checksum value is calculated by adding all these bytes together, dropping the carry and taking the two?s complement of the total sum. (42) the 67th byte is the next command code.
tmp19a43 tmp19a43 (rev2.0)3-29 flash memory operation 3.3.9 acknowledge responses the boot program represents processing states with specific codes. table 3.6 to table 3.8 show the values of possible acknowledge responses to the recei ved data. the upper four bits of the acknowledge response are equal to those of the command being executed. bit 3 of th e code indicates a receive error. bit 0 indicates an invalid command error, a checksu m error or a password error. bit 1 and bit 2 are always 0. receive error checking is not done in i/o interface mode. table 3.6 ack response to the serial operation mode byte return value meaning 86h the sio can be configured to operate in uart mode. (see note) 30h the sio can be configured to operate in i/o interface mode. table 3.7 ack response to the command byte return value meaning x8h (see note) a receive error occurred while getting a command code. x1h (see note) an undefined command code was received. (reception was completed normally.) 10h the ram transfer command was received. 20h the show flash memory sum command was received. 30h the show product information command was received. table 3.8 ack response to the checksum byte return value meaning 18h a receive error occurred. 11h a checksum or password error occurred. 10h the checksum was correct. note: if the serial operation mode is determined as uart, the boot program checks if the sio can be programmed to the baud rate at which the operation mode byte was transferred. if that baud rate is not possible, the boot program aborts, without sending back any response. note: the upper four bits of the ack response are the same as those of the previous command code.
tmp19a43 tmp19a43 (rev2.0)3-30 flash memory operation 3.3.10 determination of a serial operation mode the first byte from the controller determines the serial operation mode. to use uart mode for communications between the controller and the target board, the controller must first send a value of 86h at a desired baud rate to the target board. to use i/o interface mode, the controller must send a value of 30h at 1/16 the desired baud rate. figure 3.2 shows the waveforms for the first byte. figure 3.2 serial operation mode byte after reset is released, the boot program monitors the first serial byte from the controller, with the sio reception disabled, and calculates the intervals of tab, tac and tad. figure 3.3 shows a flowchart describing the steps to determine the intervals of tab, tac and tad. as shown in the flowchart, the boot program captures timer counts each time a logi c transition occurs in the first serial byte. consequently, the calculated tab, tac and tad intervals are bound to have slight errors. if the transfer goes at a high baud rate, the cpu might not be able to keep up with the speed of logic transitions at the serial receive pin. in particular, i/ o interface mode is more prone to th is problem since its baud rate is generally much higher than that for uart mode. to avoid such a situation, the controller should send the first serial byte at 1/16 the desired baud rate. the flowchart in figure 3.4 shows how the boot program distinguishes between uart and i/o interface modes. if the length of ta b is equal to or less than the le ngth of tcd, the serial operation mode is determined as uart mode. if the legnth of tab is greater than the length of tcd, the serial operation mode is determined as i/o interface mode. bear in mind that if the baud rate is too high or the timer operating frequency is too low, the timer resolution will be coarse, relative to the intervals between logic transitions. this becomes a problem due to inherent errors caused by the way in which timer counts are captured by software; consequently the boot program might not be able to determine the serial operation mode correctly. for example, the serial operation mode may be determined to be i/o interface mode when the intended mode is uart mode. to avoid such a situation, when uart mode is utilized, the controller should allow for a time-out period within which it e xpects to receive an echo-b ack (86h) from the target board. the controller should give up the communication if it fails to get that echo-back within the alloted time. when i/o interface mode is utilized, once the first serial byte has been transmitted, the controller should send the sclk clock after a certain idle time to get an acknowledge response. if the received acknowledge response is not 30h, the c ontroller should give up further communications. uart (86h) tab point a point b point c point d bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 start stop tcd i/o interface (30h) tab bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 tcd point a point b point c point d
tmp19a43 tmp19a43 (rev2.0)3-31 flash memory operation figure 3.3 serial operatio n mode byte reception flow initialize 16-bit timer 0 ( t1 = 8/fc, counter cleared) set tb0rg1 to 0xffff prescaler is on. 16-bit timer 0 starts counting up point a stop operation (infinite loop) high-to-low transition on serial receive pin? yes yes yes start low-to-high transition on serial receive pin? software-capture and save timer value (tab) high-to-low transition on serial receive pin? software-capture and save timer value (tac) yes low-to-high transition on serial receive pin? software-capture and save timer value (tad) 16-bit timer 0 stops counting tac tad? make backup copy of tad value done yes point b point c point d
tmp19a43 tmp19a43 (rev2.0)3-32 flash memory operation figure 3.4 serial operation mode determination flow 3.3.11 password the ram transfer command (10h) causes the boot program to perform a password check. following an echo-back of the command code, the boot program checks the contents of the 12-byte password area (0x4000_0474 to 0x4000_047f) within the flash memory. if all these address locations contain the same bytes of data other than ffh, a pa ssword area error occurs. in this case, the boot program returns an error acknowledge (11h) in response to the checksum byte (the 17th byte), regardless of whether the password sequence sent from the controller is all ffhs. the password sequence received from the controller (5th to 16th bytes) is compared to the password stored in the flash memory. table 3.9 shows how they are compared byte-by-byte. all of the 12 bytes must match to pass the password check. otherwis e, a password error occurs, which causes the boot program to return an error acknowledge in response to the checksum byte (the 17th byte). figure 3.5 password area check flow tcd tad ? tac tab > tcd? start yes uart mode i/o interface mode are all bytes equal to ffh? start yes password area error are all bytes the same? password area is normal. yes no no
tmp19a43 tmp19a43 (rev2.0)3-33 flash memory operation table 3.9 relationship between received bytes and flash memory locations received byte compared flash memory data rom protect 5th byte address 0x0000_0474 address 0x0000_0004 6th byte address 0x0000_0475 address 0x0000_0005 7th byte address 0x0000_0476 address 0x0000_0006 8th byte address 0x0000_0477 address 0x0000_0007 9th byte address 0x0000_0478 address 0x0000_0008 10th byte address 0x0000_0479 address 0x0000_0009 11th byte address 0x0000_047a address 0x0000_000a 12th byte address 0x0000_047b address 0x0000_000b 13th byte address 0x0000_047c address 0x0000_000c 14th byte address 0x0000_047d address 0x0000_000d 15th byte address 0x0000_047e address 0x0000_000e 16th byte address 0x0000_047f address 0x0000_000f 3.3.12 calculation of the show flash memory sum command the show flash memory sum command adds all 512 kbytes of the flash memory together and provides the total sum as a halfword quantity. the sum is sent to the controller, with the upper eight bits first, followed by the lower eight bits. example: 3.3.13 checksum calculation the checksum byte for a series of bytes of data is calculated by adding the bytes together, dropping the carries, and taking the two?s complement of th e total sum. the show flash memory sum command and the show product information command perform the checksum calculation. the controller must perform the same checksum operation in transmitting checksum bytes. example: assume the show flash memory sum command provides the upper and lower bytes of the sum as e5h and f6h. to calculate the checks um for a series of e5h and f6h: (43) add the bytes together. e5h + f6h = 1dbh (44) drop the carry. (45) take the two?s complement of the sum, and that is the checksum byte. 0 ? dbh = 25h a1h b2h c3h d4h for the interest of simplicity, assume the depth of the flash memory is four locations. then the sum of the four bytes is calculated as: a1h + b2h + c3h + d4h = 02eah hence, 02h is first sent to the controller, followed by eah.
tmp19a43 tmp19a43 (rev2.0)3-34 flash memory operation 3.3.14 general boot program flowchart figure 3.6 shows an overall flowchart of the boot program. figure 3.6 overall boot program flow initialize i/o interface single boot program starts get sio operation mode data sio operation mode? set i/o interface mode ack data received data (30h) (send 30h) normal response prepare to get a command receive routine get a command ack data ack data & 0xf0 no normally receive error? ram transfer? ack data received data (10h) transmission routine (send 10h: normal response) yes (10h) ram transfer processing processed normall y ? jump to ram yes normally baud rate settin g ? program uart mode and baud rate ack data received data (86h) (send 86h) normal response ack data ack data 0x08 stop operation uart cannot be set transmission routine (send x8h: receive error) show flash memory sum? show product information? command error yes (20h) yes (30h) ack data received data (20h) ack data received data (30h) ack data ack data | 0x01 transmission routine (send 20h: normal response) transmission routine (send 30h: normal response) transmission routine (send x1h: command error) show flash memory sum processing show product information processing yes can be set
tmp19a43 tmp19a43 (rev2.0)3-35 flash memory operation 3.4 on-board programming of fl ash memory (rewrite/erase) in on-board programming, the cpu is to execute softwa re commands for rewriting or erasing the flash memory. the rewrite/erase control program should be prepared by the user beforehand. because the flash memory content cannot be read while it is being written or eras ed, it is necessary to run the rewrite/erase program from the internal ram or from an external memory device after shifting to the user boot mode. in this section, flash memory addresses are represented in virtual addresses unless otherwise noted. 3.4.1 flash memory except for some functions, writing and erasing flash memory data are in accordance with the standard jedec commands. in writing or er asing, use the sw command of the cpu to enter commands to the flash memory. once the command is entered, the act ual write or erase operation is automatically performed internally. table 3-5 flash memory functions major functions description automatic page program writes data automatically. automatic chip erase erases the entire area of the flash memory automatically. automatic block erase erases a selected block automatically. (128 kb at a time) write protect the write or erase function can be individually inhibited for each block (of 128 kb). when all blocks are set for protection, the entire protection function is automatically enabled. protect function by writing a 4-bit protection code, the write or erase function can be individually inhibited for each block. note that addressing of operation commands is different from the case of standard commands due to the specific interface arrangements with the cpu as de tailed operation of the user boot mode and ram transfer mode is described later. also note that the flash memory is written in 32-bit blocks. so, 32-bit (word) data transfer commands must be used in writing the flash memory. (1) block configuration 0xbfc0_0000 128 kb 128 kb 128 kb 0xbfc7_ffff 128 kb fig. 3-4 block configuration of flash memory 128 words 128 words | x 256
tmp19a43 tmp19a43 (rev2.0)3-36 flash memory operation (2) basic operation generally speaking, this flash memory device has the following two operation modes: ? the mode to read memory data (read mode) ? the mode to automatically erase or rewrite memory data (automatic operation) transition to the automatic mode is made by executing a command sequence while it is in the memory read mode. in the automatic operation mode, flash memory data cannot be read and any commands stored in the flash memory cannot be executed. in the automatic operation mode, any interrupt or exception generation cannot set the device to the read mode except when a hardware reset is generated. during automatic operation, be sure not to cause any exceptions other than debug exceptions and reset while a dsu probe is connected. any interrupt or exception generation cannot set the device to the read mode except when a hardware reset is generated. 1) read when data is to be read, the flash memory must be set to the read mode. the flash memory will be set to the read mode immediately after power is a pplied, when cpu reset is removed, or when an automatic operation is normally terminated. in order to return to the read mode from other modes or after an automatic operation has been abnormal ly terminated, either the read/reset command (a software command to be described later) or a hardwa re reset is used. the device must also be in the read mode when any command written on the flash memory is to be executed. ? read/reset command and read command (software reset) when an automatic operation is abnormally terminated, the flash memory cannot return to the read mode by itself (when flcs = 0, data read from the flash memory is undefined.) in this case, the read/reset command can be used to return the flash memory to the read mode. also, when a command that has not been completely written has to be canceled, the read/reset command must be used to return to the read mode. the read command is used to return to the read mode after executing the sw command to write the data "0x0000_00f0" to an arbitr ary address of the flash memory. ? with the read/reset command, the device is returned to the read mode after completing the third bus write cycle. 2) command write this flash memory uses the command control method. commands are exec uted by executing a command sequence to the flash memory. the fl ash memory executes automatic operation commands according to the address and data combinations applied (refer to command sequence). if it is desired to cancel a command write opera tion already in progress or when any incorrect command sequence has been entered, the read/reset command is to be executed. then, the flash memory will terminate the command execution and return to the read mode. while commands are generally comprised of several bus cycles, the operation to apply the sw command to the flash memory is called "bus write cycl e." the bus write cycles are to be in a specific sequential order and the flash memory will perfor m an automatic operation when the sequence of the bus write cycle data and address of a command wr ite operation is in accordance with a predefined specific sequence. if any bus write cycle does not follow a predefined command write sequence, the flash memory will terminate the command execution a nd return to the read mode. the address [31:21] in each bus write cycle should be the virtual address [31:21] of command execution. it will be explained later for the address bits [20:8].
tmp19a43 tmp19a43 (rev2.0)3-37 flash memory operation (note 1) command sequences are executed from outside the flash memory area. (note 2) the interval between bus write cycles for this device must be 15 system clock cycles or longer . the command sequencer in the flash memory device requires a certain time period to recognize a bus write cycle. if more than one bus write cycles are executed within this time period, normal operation cannot be expected. for adjusting the applicable bus write cycle interval using a software timer to be operated at the operating frequency, use the section 10) "id-read" to check for the appropriateness. (note 3) between the bus write cycles, never use any load command (such as lw, lh, or lb) to the flash memory or perform a dma transmission by specifying the flash area as the source address. also, don't execute a jump comma nd to the flash memory. while a command sequence is being executed, don't generate any interrupt such as maskable interrupts (except debug exceptions when a dsu probe is connected). if such an operation is made , it can result in an unexpected read access to the flash memory and the command sequencer may not be able to correctly recognize the command. while it could cause an abnormal termination of the command sequence, it is also possible that the written command is incorrectly recognized. (note 4) the sync command must be executed i mmediately after the sw command for each bus write cycle. (note 5) for the command sequencer to recognize a command, the device must be in the read mode prior to executing the command. be sure to check before the first bus write cycle that the flcs[0] rdy/bsy bit is set to "1." it is recommended to subsequently execute a read command. (note 6) upon issuing a command, if any address or data is incorrectly written, be sure to perform a system reset operation or issue a reset command to return to the read mode again. 3) reset hardware reset the flash memory has a reset input as the memory block and it is connected to the cpu reset signal. therefore, when the reset input pin of this device is set to v il or when the cpu is reset due to any overflow of the watch dog timer, the flash memory will return to the read mode terminating any automatic operation that may be in progress. the cpu reset is also used in returning to the read mode when an automatic operation is abnormally terminated or when any mode set by a command is to be canceled. it should also be noted that applying a hardware reset during an automatic operation can result in incorrect rewriting of data. in such a case, be sure to perform the rewriting again. refer to section 24.2.1 "reset operation" for cp u reset operations. after a given reset input, the cpu will read the reset vector data from the flash memory and starts operation after the reset is removed. 4) automatic page programming writing to a flash memory device is to make "1" data cells to "0" data cells. any "0" data cell cannot be changed to a "1" data cell. for making "0 " data cells to "1" data cells, it is necessary to perform an erase operation. the automatic page programming function of this device writes data in 128 word blocks. a 128 word block is defined by a same [31:9] address and it starts from the address [8:0] = 0 and ends at the address [8:0] = 0x1ff. this programming unit is hereafter referred to as a "page."
tmp19a43 tmp19a43 (rev2.0)3-38 flash memory operation writing to data cells is automatically performed by an internal sequencer and no external control by the cpu is required. the state of automatic page programming (whether it is in writing operation or not) can be checked by the flcs [0] register. also, any new command sequence is not accepted while it is in the automatic page programming mode. if it is desired to interrupt the automatic pa ge programming, use the hardware reset function. if the operation is stopped by a hardware reset operation, it is necessary to once erase the page and then perform the automatic page programming again because writing to the page has not been normally terminated. the automatic page programming operation is allowed only once for a page already erased. no programming can be performed twice or more times irrespective of the data cell value whether it is "1" or "0." note that rewriting to a page that has been once written requires execution of the automatic block erase or automatic chip erase command before executing the automatic page programming command again. note that an attempt to rewrite a page two or more times without erasing the content can cause damages to the device. no automatic verify operation is performed internally to the device. so, be sure to read the data programmed to confirm that it has been correctly written. the automatic page programming operation starts when the fourth bus write cycle of the command cycle is completed. on and after the fifth bus wr ite cycle, data will be written sequentially starting from the next address of the addr ess specified in the fourth bus wr ite cycle (in the fourth bus write cycle, the page top address will be command written) (32 bits of data is input at a time). be sure to use the sw command in writing commands on and af ter the fourth bus cycle. in this, any sw command shall not be placed across word boundary. on and after the fifth bus write cycle, data is command written to the same page area. even if it is desired to write the page only partially, it is required to perform the automatic page programmi ng for the entire page. in this case, the address input for the fourth bus write cycle shall be set to the top address of the page. be sure to perform command write operation with the input data set to "1" for the data cells not to be set to "0." for example, if the top address of a page is not to be written, set the input data of the fourth bus write cycle to 0xffffffff to command write the data. once the fourth bus cycle is executed, it is in the automatic programming operation. this condition can be checked by monitoring the register bit flcs [0] (see table 24.6). any new command sequence is not accepted while it is in automatic page programming mode. if it is desired to stop operation, use the hardwa re reset function. be careful in doing so because data cannot be written normally if the operation is interrupt ed. when a single page has been command written normally terminating the automatic page writing pr ocess, the flcs [0] bit is set to "1" and it returns to the read mode. when multiple pages are to be written, it is n ecessary to execute the page programming command for each page because the number of pages to be written by a single execution of the automatic page program command is limited to only one page. it is not allowed for automatic page programming to process input data across pages. data cannot be written to a protected block. when automatic programming is finished, it automatically returns to the read mode. this condition can be checked by monitoring flcs [0] (see table 24.6). if automatic programming has failed, the flash memory is locked in the mode and will not return to the read mode. for returning to the read mode, it is necessary to use the reset command or hardware reset to reset the flash memory or the device. in this case, while writing to the address has failed, it is recommended not to use the device or not to use the block that includes the failed address.
tmp19a43 tmp19a43 (rev2.0)3-39 flash memory operation note: software reset becomes ineffective in bus write cycles on and after the fourth bus write cycle of the automatic page programming command. 5) automatic chip erase the automatic chip erase operati on starts when the sixth bus write cycle of the command cycle is completed. this condition can be checked by monitoring flcs [0] (see table 24.6). while no automatic verify operation is performed internally to the device, be sure to read the data to confirm that data has been correctly erased. any new command sequence is not accepted while it is in an automatic chip erase operation. if it is desired to stop operation, use the hardware reset function. if the operation is forced to stop, it is necessary to perform the automatic ch ip erase operation again because the data erasing operation has not been normally terminated. also, any protected blocks cannot be erased. if all the blocks are protected, the automatic chip erase operation will not be performed and it returns to the read mode after completing the sixth bus read cycle of the command sequence. when an automatic chip erase operation is normally terminated, it automatically returns to the read mode. if an automatic chip erase operation has failed, the flash memory is locked in the mode and will not return to the read mode. for returning to the read mode, it is necessary to use the reset command or hardware reset to reset the flash memory or the device. in this case, the failed block cannot be detected. it is recommended not to use the device anymore or to identify the failed block by using the block erase function for not to use the identified block anymore. 6) automatic block erase (128 kb at a time) the automatic block erase operation starts when th e sixth bus write cycle of the command cycle is completed. this status of the automatic block erase operation can be checked by monitoring flcs [0] (see table 24.6). while no automatic verify operation is performed internally to the device, be sure to read the data to confirm that data has been correctly erased. any new command sequence is not accepted while it is in an automatic block erase operation. if it is desired to stop operation, use the hardware reset function. in this case, it is necessary to perform the automatic block erase operation again because the data eras ing operation has not been normally terminated. also, any protected blocks cannot be erased. if an automatic block erase operation has failed, the flash memory is locked in the mode and will not return to the read mode. in this case, use the reset command or hardware reset to reset the flash memory or the device. 7) automatic programming of protection bits this device is implemented with four protection bits . the protection bits can be individually set in the automatic programming. the applicable protection bit is specified in the seventh bus write cycle. by automatically programming the protection bits, write and/or erase functions can be inhibited (for protection) individually for each block. the protection status of each block can be checked by the flcs register to be described later. this status of the automatic programming operation to set protection bits can be checked by monitoring flcs (see table 24.6). any new command sequence is not accepted while automatic programming is in progress to program the protection bits. if it is desired to stop the programming operation, use the hardware reset function. in this case, it is necessary to perform the programming operation again
tmp19a43 tmp19a43 (rev2.0)3-40 flash memory operation because the protection bits may not have been corr ectly programmed. if all the protection bits have been programmed, the flash memory cannot be read from any area outside the flash memory such as the internal ram. in this condition, the flcs bits are set to "0 x f" indicating that it is in the protected state (see table 24.6). after this, no command writing can be performed. note: software reset is ineffective in the seventh bus write cycle of the automatic protection bit programming command. the flcs bit turns to "0" after entering the seventh bus write cycle. 8) automatic erasing of protection bits different results will be obtained when the auto matic protection bit erase command is executed depending on the status of the protection bits. it depends on the status of flcs before the command execution whether it is set to "0 x f" or to any other values. be sure to check the value of flcs before execu ting the automatic protection bit erase command. ? when flcs is set to "0 x f" (all the protection bits are programmed): when the automatic protection bit erase comma nd is command written, the flash memory is automatically initialized within the device. when the seventh bus write cycle is completed, the entire area of the flash memory data cells is erased and then the prot ection bits are erased. this operation can be checked by monitoring flcs . if the automatic operation to erase protection bits is normally terminated, flcs will be set to "0x01." while no automatic verify operation is performed internally to the device, be sure to read the data to confirm that it has been correc tly erased. for returning to the read mode while the automatic operation after the seventh bus cycle is in progress, it is necessary to use the hardware reset to reset the flash memory or the device. if this is done, it is necessary to check the status of protection bits by flcs after retuning to the read mode and perform either the automatic protection bit erase, automatic chip erase, or automatic block erase operation, as appropriate. ? when flcs is other than "0 x f" (not all the protection bits are programmed): the protection condition can be canceled by the automatic protection bit erase operation. with this device, protection bits can be erased hand ling two bits at a time. the target bits are specified in the seventh bus write cycle and wh en the command is completed, the device is in a condition the two bits are erased. the protection status of each block can be checked by flcs to be described later. this status of the programming operation for automatic protection bits can be checked by monitoring flcs . when the automatic operation to erase protection bits is no rmally terminated, the two protection bits of flcs selected for erasure are set to "0." in any case, any new command sequence is not acce pted while it is in an automatic operation to erase protection bits. if it is desired to stop the operation, use the hardware reset function. when the automatic operation to erase protection bits is normally terminated, it returns to the read mode. the flcs bit is "0" while in automatic operation and it turns to "1" when the automatic operation is terminated.
tmp19a43 tmp19a43 (rev2.0)3-41 flash memory operation 9) flash control/ status register this resister is used to monitor the status of the flash memory and to indicate the block protection status. table 3-6 flash control register 7 6 5 4 3 2 1 0 flcs bit symbol blpro3 blpro2 blpro1 blpro0 romtype rdy/bsy (0xffff_e520) read/write r r r r r after reset 0 0 0 0 0 0 0 1 function protection area setting (for each 128 kb) 0000: no blocks are protected xxx1: block 0 is protected xx1x: block 1 is protected x1xx: block 2 is protected 1xxx: block 3 is protected always reads "0." rom id bit 0: flash 1: mrom always reads "0." ready/busy 0: in operation 1: operation terminated 15 14 13 12 11 10 9 8 bit symbol read/write r after reset 0 0 0 0 0 0 0 0 function 23 22 21 20 19 18 17 16 bit symbol read/write r after reset 0 0 0 0 0 0 0 0 function 31 30 29 28 27 26 25 24 bit symbol read/write r after reset 0 0 0 0 0 0 0 0 function fig. 3-5 bit 0: ready/busy flag bit the rdy/bsy output is provided as a means to monitor the status of automatic operation. this bit is a function bit for the cpu to monitor the function. when th e flash memory is in automatic operation, it outputs "0" to indicate that it is busy. when the automatic ope ration is terminated, it returns to the ready state and outputs "1" to accept the next command. if the automatic operation has failed, this bit maintains the "0" output. by applying a hardware reset, it returns to "1." (note)please issue it after confirming the command issue is always a ready state. a normal command not only is sent when the command is issu ed to a busy inside but also there is a possibility that the command after that cannot be input. in that case, pleas e return by system reset or the reset command. bit 2: rom type identification bit this bit is read after reset to identify whether the rom is a flash rom or a mask rom. flash rom: "0" mask rom: "1" bits [7:4]: protection status bits (can be set to any combination of blocks) each of the protection bits (4 bits) represents the protection status of the corresponding block. when a bit is set to "1," it indicate s that the block corresponding to the bit is protected. when the block is protected, data cannot be written to it.
tmp19a43 tmp19a43 (rev2.0)3-42 flash memory operation 10) id-read using the id-read command, you can obtain the type and other information on the flash memory contained in the device. the data to be loaded will be different depending on the address [15:14] of the fourth and subsequent bus write cycles (any input data other than 0xf can be used). on and after the fourth bus write cycle, when an lw comm and (to read an arbitrary flash memory area) is executed after an sw command, the id value will be loaded (execute a sync command immediately after the lw command) . once the fourth bus write cy cle of an id-read command has passed, the device will not automatically return to the read mode. in this condition, the set of the fourth bus write cycle and lw/sync commands can be repetitively executed. for returning to the read mode, reset the system or use the read or read/reset command. the id-read command can be used when it is necessary for an application to identify whether the device in the product has an internal flash memory or an internal rom. this is effective because a mask rom doesn't have a command sequencer so it interprets any id-read command written as simply a pair of sw and lw commands applied to the mask rom. if an id-read command is to be executed on a device with an in ternal mask rom, it is necessary to select an address at which the rt value to a normal lw command is differen t from the id-read execution result (id) from a device with an internal flash memory, also taking into account any applicable protection conditions. (important) the "interval between bus write cycles " between successive command sequences must be 15 system clock cycles or longer irrespective of the operating frequency used. this device doesn't have any function to automatically adjust the interval between bus write cycles regarding execution of multiple sw commands to the flash memo ry. therefore, if an inadequate interval is used between two sets of bus write cycles, the flash memory cannot be written as expected. prior to setting the device to work in the onboard programming mode, adjust the bus write cycle interval using a software timer, etc., to verify that th e id-read command can be successfully executed at the operating frequency of the application program. in the onboard programming mode, use the bus write cycle interval at which the id-read command can be operate d normally to execute command sequences to rewrite the flash memory.
tmp19a43 tmp19a43 (rev2.0)3-43 flash memory operation (4) list of command sequences table 3-7 flash memory access from the internal cpu first bus cycle second bus cycle third bus cycle fourth bus cycle fifth bus cycle sixth bus cycle seventh bus cycle addr. addr. addr. addr. addr. addr. addr. command sequence data data data data data data data 0xxx ra read 0xf0 rd 0x55xx 0xaaxx 0x55xx ra read/reset 0xaa 0x55 0xf0 rd 0x55xx 0xaaxx 0x55xx ia 0xxx ? id-read 0xaa 0x55 0x90 0x00 id ? 0x55xx 0xaaxx 0x55xx pa pa pa pa automatic page programming (note) 0xaa 0x55 0xa0 pd0 pd1 pd2 pd3 0x55xx 0xaaxx 0x55xx 0x55xx 0xaaxx 0x55xx ? automatic chip erase 0xaa 0x55 0x80 0xaa 0x55 0x10 ? 0x55xx 0xaaxx 0x55xx 0x55xx 0xaaxx ba ? auto block erase (note) 0xaa 0x55 0x80 0xaa 0x55 0x30 ? 0x55xx 0xaaxx 0x55xx 0x55xx 0xaaxx 0x55xx pba protection bit programming 0xaa 0x55 0x9a 0xaa 0x55 0x9a 0x9a 0x55xx 0xaaxx 0x55xx 0x55xx 0xaaxx 0x55xx pba protection bit erase 0xaa 0x55 0x6a 0xaa 0x55 0x6a 0x6a fig. 3-6 (5) supplementary explanation ? ra: read address ? rd: read data ? ia: id address ? id: id data ? pa: program page address ? pd: program data (32-bit data) after the fourth bus cycle, enter data in the order of the address for a page. ? ba: block address ? pba: protection bit address (note 1) always set "0" to the address bits [1:0] in the entire bus cycle. (setting values to bits [7:2] are undefined.) (note 2) bus cycles are "bus write cycles" except for the second bus cycle of the read command, the fourth bus cycle of the read/reset command, and the fifth bus cycle of the id-read command. bus write cycles are executed by sw commands. use "data" in the table for the rt register [7 :0] of sw commands. the address [31:16] in each bus write cycle should be the target flash memory address [31:16] of the command sequence. use "addr." in the table for the address [15:0]. (note 3) in executing the bus write cycles, the interval between each bus write cycle shall be 15 system clocks or more. (note 4) the "sync command" must be executed immediately after completing each bus write cycle. (note 5) execute the "sync command" immediately following the "lw command" after the fourth bus write cycle of the id- read command.
tmp19a43 tmp19a43 (rev2.0)3-44 flash memory operation (5) address bit configura tion for bus write cycles table 20.5.1.3 address bit configuration for bus write cycles address addr [31:21] addr [20] addr [19] addr [18:17] addr [16] addr [15] addr [14] addr [13] addr [12:9] addr [8] addr [7:0] normal bus write cycle address configuration normal commands flash area "0" is recommended command addr [1:0]=0 (fixed), others: 0 (recommended) ba: block address (set the sixth bus write cycle address for block erase operation) block erase flash area "0" is recommended block selection addr[1:0]=0 (fixed), others: 0 (recommended) pa: program page address (set the fourth bus write cycle address for page programming operation) auto page program- ming flash area "0" is recommended block selection page selection addr[1:0]=0 (fixed), others: 0 (recommended) ia: id address (set the fourth bus write cycle address for id-read operation) id-read flash area "0" is recommended id address addr[1:0]=0 (fixed), others: 0 (recommended) pba: protection bit address (set the seventh bus write cycle address for protection bit programming) protection bit program- ming flash area "0" is recommended protection bit write 00: block 0 01: block 1 10: block 2 11: block 3 addr[1:0]=0 (fixed), others: 0 (recommended) pba: protection bit address (set the seventh bus write cycle address for protection bit erasure) protection bit erase flash area "0" is recommended erase protection for 0: blocks 0, 1 1: blocks 2, 3 addr[1:0]=0 (fixed), others: 0 (recommended) (note) table 20.5.1.2 "flash memory access from the internal cpu" can also be used. (note) address setting can be performed according to the "normal bus write cycle address configuration" from the first bus cycle. (note) ""0" is recommended" can be changed as necessary.
tmp19a43 tmp19a43 (rev2.0)3-45 flash memory operation table 3-8 block erase address table address range ba flash memory address when applied to the projected area size block 0 0xbfc0_0000-0xbfc1_ffff 0x0000_0000-0x0001_ffff 128 kb block 1 0xbfc2_0000-0xbfc3_ffff 0x0002_0000-0x0003_ffff 128 kb block 2 0xbfc4_0000-0xbfc5_ffff 0x0004_0000-0x0005_ffff 128 kb block 3 0xbfc6_0000-0xbfc7_ffff 0x0006_0000-0x0007_ffff 128 kb example: when ba0 is to be selected, any single address in the range 0xbfc0_0000 to 0xbfc1_ffff may be entered. table 3-9 protection bit programming address table the seventh bus write cycle address [15:14] opba address [15] address [14] block 0 0 0 block 1 0 1 block 2 1 0 block 3 1 1 table 3-10 protection bit erase address table the seventh bus write cycle address [15:14] opba address [15] address [14] block 0 0 x block 1 0 x block 2 1 x block 3 1 x the protection bit erase command will erase bits 0 and 1 together. the bits 2 and 3 are also erased together. table 3-11 the id-read command's fourth bus write cycle id address (ia) and the data to be read by the following lw command (id) ia [15:14] id [7: 0] code 00b 0x98 manufacturer code 01b 0x5a device code 10b reserved --- 11b 0x05 macro code
tmp19a43 tmp19a43 (rev2.0) 4-1 various protecting functions 4. various protecting functions 4.1 overview the rom protect function for designating the internal ro m (flash) area as a read-p rotected area and the dsu protect function for prohibiting the use of dsu (dsu-probe) are built into the tmp19a43. the read protect functions specifically include the following: ? flash protect function ? rom data protect function ? dsu protect function 4.2 features 4.2.1 flash protect function a built-in flash can prohibit the operation of writing and the deletion at every the block of every 128 kbyte. this function is called the block protecting. to make the block protecting function effective, it protects it corresponding to the block where it wants to put protecting. the bit is made "1". the block protecting can be released by making the protecting bit "0". (please see the chapter of the flash operation explanation about the program method. )the protecting bit can be monitored by flcs register < blpro3:0 > bit. the state to put protecting on all blocks is called the flash protecting. it is necessary to note it because all the protecting bits become "0" after auto matically deleting all data of the flash when the protecting release operates after it puts it into the st ate of the lash protecting of 1f(operation that makes the protecting bit "0"). flash is always being protected in the mask version, and the flash protecting cannot be released. this function doesn't influence usual operation in the mask version. it is necessary to be protecting flash to make "rom data protecting" and "dsu protecting" that will explain in the future effective.
tmp19a43 tmp19a43 (rev2.0) 4-2 various protecting functions 4.2.2 rom data protect as for rom data protecting, the execution of the command to the flash is prohibited in the function it, and the flash version that limits reading data to building flash/rom into. when rom protecting register romsec1 bit is "1", rom data protecting becomes effective with flash protected. if instructions in the rom area have been replace d with instructions in the ram area in a pc by using the rom correction function, a pc shows the instructions as residing in the flash rom area. because they actually reside in the ram area, data cannot be read in a rom pr otected state. to read data by using instructions held in the overwritten ram area, it is necessary to write data to ram by using a program available in the rom area or to use other means. if the rom area is put in a protected state, th e following operations cannot be performed: ? using instructions placed in areas other than the rom area to load or store the data taken from the rom area ? store to dmac register (nmi by the bus error is generated. ) ? loading or storing the data taken from the rom area in accordance with ejtag ? using boot-rom to load or store the da ta taken from the rom area (flash only) ? executing flash writer to load or store the data taken from the rom area(flash only) ? using instructions placed in areas other than the rom area to access th e registers (romsec1, romsec2) that concern the protection of the rom area ? executing the command to unprotect automatic blocking in writer mode, performing the flash command sequences other than the automatic blocking unprotect command sequence, and performing the flash command sequence in single or boot mode by specifying an address in the rom area(flash only) the following operations can be performed even if the rom area is in a protected state: ? using instructions placed in the rom area to load the data taken from the rom area ? using instructions placed in all areas to load the data taken from areas other than the rom area ? using instructions placed in all areas to ma ke instructions branch off to the rom area ? performing pc trace (there are restrictions) or break on the rom area in accordance with ejtag ? data transfer of rom area by dmac
tmp19a43 tmp19a43 (rev2.0) 4-3 various protecting functions 4.2.3 dsu protect the dsu protecting function is a function for invalidating the connection of dsu-probe to enable third parties other than the user to read the data of a built-in flash easily. when seqmod register < dsuoff > bit is "1", the dsu protecting becomes effective with flash protected. in the dsuoff bit, the flash version, the mask versio n, and the state of the first stage are "1. "it enters the state of the dsu protecting as long as the flash protecting is always effective in the mask version, and the dsuoff bit is not set to "0" by the user program. it doesn't enter the state of the dsu protecting if protecting is not put on all blocks of flash in the flash version. an initial state enters the state of the dsu protecting as well as the mask version when flash is being protected putting protecting on all blocks of flash. (note) the dsuoff bit can be accessed only with the instruction put on built-in rom in the state of rom data protecting. it is necessary to note it beca use it is necessary to put the program of the dsu protecting release on built-in rom.
tmp19a43 tmp19a43 (rev2.0) 4-4 various protecting functions 4.3 protect configuratio n and protect statuses fig. 4-1 various protect statuses table 4-1 protect statuses in each mode protect bit setting flcs 1111 1111 rom protect enable bit roms ec1 1 0 don't care dsu protect enable bit seqmod 1 0 1 0 don't care flash read protect status on off rom protect status on off off dsu protect status on off on off off read of flash from internal rom { { { { { read of flash from areas other than internal rom *1 *1 { { { clearing of rom protect enable status (from rom) { { { clearing of rom protect enable status (from areas other than rom) *2 *2 { clearing of dsu protect enable status (from rom) { { { clearing of dsu protect enable status (from areas other than rom) *3 { { issuing of the command to erase protect bits *4 *4 { *8 { *8 { issuing of commands other than the command to erase protect bits *5 *5 *7 *7 ? *9 writing of data to the dmac setting register (from rom) { { { { { single /single boot mode writing of data to the dmac setting register (from areas other than rom) *6 *6 { { { *1 : the data of address "0xbfc0_00 00" or "0xbfc0_0002" can be read. *2 : stored data is masked. a write to registers canno t be executed (data in registers cannot be cleared). *3 : stored data is masked. a write to registers canno t be executed (data in registers cannot be cleared). *4 : a command address is masked, and fl ash memory does not recognize commands. *5 : a command address is masked, and fl ash memory does not recognize commands. *6 : a bus error exception occurs (when making the dmac register setting). *7 : because a read of flash memory is prohibited, commands are not recognized. *8 : because a read of flash memory is prohibited, issued commands are converted to the command for erasing the whole flash memory area and the command for erasing all protect bits. chip protect bit flcs if the bit is "1111" romsec1 rom data protect flash d protect function seqmod dsu protect cs_dmac a bus error exception occurs nmi 19a43f during a write of data from areas other than internal rom to the dmac register
tmp19a43 tmp19a43 (rev2.0) 4-5 various protecting functions 4.4 register flash control/status register this register shows the status of flash memory being monitored and the block protect status of flash memory. table 4-2 flash control register 7 6 5 4 3 2 1 0 flcs bit symbol blpro3 blpro2 blpro1 blpro0 romtype rdy/bsy (0xffff_e520) read/write r r r r r after reset by power-on 0 (1) 0 (1) 0 (1) 0 (1) 0 0 (1) 0 1 function protect area setti ng (in units of 128 kb) 0000: all blocks unprotected xxx1: block 0 protected xx1x: block 1 protected x1xx: block 2 protected 1xxx: block 3 protected mask ?1111? "0" is read. rom identification bit 0: flash 1: mrom "0" is read. ready/busy 0: in auto operation 1: auto operation completed (mask:?1?) 15 14 13 12 11 10 9 8 bit symbol read/write r after reset by power-on 0 0 0 0 0 0 0 0 function 23 22 21 20 19 18 17 16 bit symbol read/write r after reset by power-on 0 0 0 0 0 0 0 0 function 31 30 29 28 27 26 25 24 bit symbol read/write r after reset by power-on 0 0 0 0 0 0 0 0 function bit 0: ready/busy flag bit the rdy/bsy output is provided to identify the stat us of auto operation. this bit is a functional bit for monitoring this function by communicating with the cpu. if flash memory is in auto operation, "0" is output to show that flash memory is busy. as flash memory completes auto operation and goes into a ready state, "1" is outp ut and the next command will be accepted. if the result of auto operation is faulty, this bit continues to output "0." it returns to "1" upon a hardware reset. (note) before issuing a command, make sure that flash memory is in a ready state. if a command is issued when flash memory is busy, a right command cannot be generated and there is the possibility that subsequent commands may not be able to be input. in this case, you must return to a normal functional state by executing a system reset or issuing a reset command. bit 2: rom type identification bit this bit is used to identify the type of flash rom or the type of mask rom based on the value after a reset. flash rom: "0" mask rom: "1" bit [7:4]: protect bit (x: a combination setting can be made for each block) the protect bit (4-bit) value corresponds to the protect status of each block. if this bit is "1," the corresponding block is in a protected state. a protected block cannot be overwritten.
tmp19a43 tmp19a43 (rev2.0) 4-6 various protecting functions table 4-3 rom protect register 7 6 5 4 3 2 1 0 romsec1 bit symbol rsecon (0xffff_e518) read/write r r/w after reset by power-on 0 1 function "0" is always read. rom protect 1: on 0: off (see note) 15 14 13 12 11 10 9 8 bit symbol read/write r after reset by power-on 0 function "0" is always read. 23 22 21 20 19 18 17 16 bit symbol read/write r after reset by power-on 0 function 31 30 29 28 27 26 25 24 bit symbol read/write r after reset by power-on 0 function "0" is always read. (note) this register is initialized only by power-on reset in the flash version. the mask version is usually initialized at each reset. (note) to access this register, 32-bit access is required.
tmp19a43 tmp19a43 (rev2.0) 4-7 various protecting functions table 4-4 rom protect lock register 7 6 5 4 3 2 1 0 romsec2 bit symbol (0xffff_e51c) read/write w after reset undefined function see note. 15 14 13 12 11 10 9 8 bit symbol read/write w after reset undefined function see note. 23 22 21 20 19 18 17 16 bit symbol read/write w after reset undefined function see note. 31 30 29 28 27 26 25 24 bit symbol read/write w after reset undefined function see note. (note) if this register is set to "0x0000_003 d" after romsec1 is set, appropriate bit values are automatically set in romsec1. (note) if the rom area is protected, the registers romsec1 and romsec2 can be accessed only by using the instructions residing in the rom area. (note) to access this register, 32-bit access is required. (note) this register is a writ e-only register. if it is r ead, values will be undefined.
tmp19a43 tmp19a43 (rev2.0) 4-8 various protecting functions table 4-5 dsu protect mode register 7 6 5 4 3 2 1 0 seqmod bit symbol dsuoff (0xffff_e510) read/write r r/w after reset 0 1 function "0" is always read. 1: dsu disabled 0: dsu enabled 15 14 13 12 11 10 9 8 bit symbol read/write r after reset 0 function "0" is always read. 23 22 21 20 19 18 17 16 bit symbol read/write r after reset 0 function 31 30 29 28 27 26 25 24 bit symbol read/write r after reset 0 function "0" is always read. (note) this register is initialized only by power-on reset in the flash version. (note) the mask version is usually initialized at each reset. to access this register, 32-bit access is required. table 4-6 dsu protect control register 7 6 5 4 3 2 1 0 seqcnt bit symbol dsecode07 dsecode06 dsecode05 dsecode04 dsecode03 dsecode02 dsecode01 dsecode00 (0xffff_e514) read/write w after reset 0 function write "0x0000_00c5." 15 14 13 12 11 10 9 8 bit symbol dsecode15 dsecode14 dsecode13 dsecode12 dsecode11 dsecode10 dsecode09 dsecode08 read/write w after reset 0 function write "0x0000_00c5." 23 22 21 20 19 18 17 16 bit symbol dsecode23 dsecode22 dsecode21 dsecode20 dsecode19 dsecode18 dsecode17 dsecode16 read/write w after reset 0 function write "0x0000_00c5." 31 30 29 28 27 26 25 24 bit symbol dsecode31 dsecode30 dsecode29 dsecode28 dsecode27 dsecode26 dsecode25 dsecode24 read/write w after reset 0 function write "0x0000_00c5." (note) to access this register, 32-bit access is required. (note) this register is a writ e-only register. if it is r ead, values will be undefined.
tmp19a43 tmp19a43 (rev2.0) 4-9 various protecting functions 4.5 proted-related / release settings if it is necessary to overwrite flash memory or protect bits in a protected state, "automatic protect bit deletion" must be executed or the rom protect function must be disabled. dsu cannot be used if it is in a protected state. flash memory may go into a read-protect ed state after the automatic protect bit program is executed. in this case, it is necessary to set dsu-probe to "enable" before the automatic protect bit program is executed. the mask version is possible only the release of ro m security, and the protecting bit cannot be rewritten. if "automatic protect bit deletion" is executed when flas h memory is in a read-protected state, flash memory is automatically initialized inside this device. therefore, extra caution must be used when switching from one state to a read-protected state. (flash only) 4.5.1 flash protect function the flash protecting function cannot be released always effectively in the mask version. it becomes effective by putting the block protecting on all of the four blocks in the flash version. the flash memory command sequence and protect b it program commands are used to enable or disable the flash read protect function. for further information, refer to the command sequence explained in the chapter describing the operations of flash memory. (notes concerning flash version) the protecting bit is cleared after all the data of the flash is deleted when the protecting bit release command is executed with the flash protected , and the flash protecting is released. in the state of rom data protecting, explains as follows, the command execution to the flash is disregarded. it is necessary to release rom data protecting first clearing the rsecon bit of rom protecting register when the flash prot ecting is released with rom protected.
tmp19a43 tmp19a43 (rev2.0) 4-10 various protecting functions 4.5.2 rom data protect rom data protecting is effective the flash prot ecting and becomes effective at rom protecting register romsec1=?1". after releasing reset, the rsecon bit is initialized by "1". the flash protecting is sure to enter the state of rom data protecting in the mask version after releasing reset because it is always effective. it decides whether to enter the state of rom data pr otecting by the state of the flash protecting in the flash version. when rom protecting register is rewritten with rom data protected, rewriting can be executed only from the program put on built-in rom. theref ore, it is necessary to prepare the release program of rom data protecting on built-in rom. rom data protecting is released by setting rom protecting register romsec1?0" when protecting is released, and writing protecting code ?0x0000_003d" in rom protecting lock register romsec2. moreover, rom data protecting function can be set again by similarly setting rom protecting register romsec1?1" when rom protecting is set, and writing protecting code ?0x0000_003d" in rom protecting lock register romsec2. it is necessary to note the romsec2 register becaus e the reading data is different from original write data because of the register only for writing. the initialization of rom protecting register is diff erent in the flash version and the mask version. it provides with the power-on reset circuit in the fl ash version, rom protecting register is initialized by power-on reset, and the value doesn't usually change in reset. it is usually initialized by reset in the mask version because power-on reset is not provided. it is necessary to note it in the mask versio n because it is usually initialized at each reset. romsec1write romsec1write data clk reset rom p rotection romsec1read data romsec2 = 0x0000_003d it is not possible to access it excluding built-in rom at the time of rom data d q sd dq sd powon reset(flash) resetmask
tmp19a43 tmp19a43 (rev2.0) 4-11 various protecting functions 4.5.3 dsu protect dsu data protecting is effective the flash protecting and becomes effective at dsu protecting register seqmod=?1". after releasing reset, the dsuoff bit is initialized by "1". the flash protecting is sure to enter the state of dsu data protecting in the mask version af ter releasing reset because it is always effective. it decides whether to enter the state of rom data pr otecting by the state of the flash protecting in the flash version. when dsu protecting register is rewritten with ro m data protected, rewriting can be executed only from the program put on built-in rom. theref ore, it is necessary to prepare the release program of dsu data protecting on built-in rom. dsu protecting is released by setting dsu pr otecting register seqmod?0" when protecting is released, and writing protecting code ?0x0000_00c5" in rom protecting lock register seqcnt. moreover, dsu protecting function can be set again by similarly setting rom protecting register seqmod?1" when dsu protecting is set, and writing protecting code ?0x0000_00c5" in dsu protecting lock register seqcnt. it is necessary to note the seqcnt register becaus e the reading data is different from original write data because of the register only for writing. the initialization of dsu protecting register is diff erent in the flash version and the mask version. it provides with the power-on reset circuit in the flash version, dsu protecting register is initialized by power-on reset, and the value doesn't usually change in reset. it is usually initialized by reset in the mask version because power-on reset is not provided. it is necessary to note it in the mask versio n because it is usually initialized at each reset. seqmodwrite seqmodwrite data clk reset dsu p rotection seqmodread data seqcnt = 0x0000_00c5 it is not possible to access it excluding built-in rom at the time of rom data dq sd dq sd powon reset(flash) resetmask flash protection
tmp19a43 tmp19a43 (rev2.0) 4-12 various protecting functions 4.5.4 rom protect register: romsec1 the rom protect register is equipped with a power-on reset circuit. caution must be exercised as data read from the romsec1 bit is differen t from the actually written data. how data is processed is shown below. the mask version is usually initialized by reset though flash goods are initialized by power-on reset. 4.5.5 dsu protect mode register: seqmod the dsu protect mode register is equipped with a power-on reset circuit. caution must be exercised as data read from the seqmod bit is diff erent from the actually written data. how data is processed is shown below. the mask version is usually initialized by reset though flash goods are initialized by power-on reset. seqmod write write data to seqmod clk reset power-on reset dsu protect flash read protect function read data from seqmod dsusec2 = 0x0000_00c5 if the rom is in a protected state, access from areas other than the internal rom is disabled. d q sd dq sd romsec1 write write data to romsec1 clk reset power-on reset rom protect flash read protect function read data from romsec1 romsec2 = 0x0000_003d if the rom is in a protected state, access from areas other than the internal rom is disabled. d q sd dq sd
tmp19a43 tmp19a43 5-1 5. electrical characteristics 5.1 absolute maximum ratings parameter symbol rating unit v cc15 (core) ? 0.3to3.0 vcc3 i/o ? 0.3to3.9 avcc3a/d ? 0.3to3.9 davcc (d/a) ? 0.3to3.5 supply voltage dvcc3 ? 0.3to3.9 v supply voltage v in ? 0.3tov cc + 0.3 v per pin i ol 5 low-level output current total i ol 50 per pin i oh -5 high-level output current total i oh 50 ma power dissipation (ta = 85c) pd 600 mw soldering temperature (10 s) t solder 260 c storage temperature t stg ? 40to125 c exceptduring flash w/e - 20 to 85 operating temperature during flash w/e t opr 0 to 70 c write/erase cycles n ew 100 cycle v cc15 dvcc15 cvcc15 cvcch v cc 3 dvcc3=cvccl v ss dvss avss cvss=dagnd the letter x in equations presented in this chapter repr esents the cycle period of the fsys clock selected through the programming of the syscr1.sysck bit. th e fsys clock may be derived from either the high-speed or low-speed crystal oscillator. the programming of the clock gear function also affects the fsys frequency. all relevant values in this chapter are calculated with the high-speed (fc) system clock (syscr1.sysck = 0) and a cloc k gear factor of 1/fc (syscr1.gear[2:0] = 000). note: absolute maximum ratings are limiting values of operating and environmental conditions which should not be exceeded under the worst possible conditions. the equipment manufacturer should design so that no absolute maximum rating value is exceeded with respect to current, voltage, power dissipation, temperature, etc. exposure to conditions beyond those listed above may cause permanent damage to the device or affect device reliability, which could increase potential risks of personal injury due to ic blowup and/or burning.
tmp19a43 tmp19a43 5-2 5.2 dc electrical characteristics (1/3) ta20 to 85 parameter symbol rating min. typ. (note 1) max. unit dvcc15 cvcch 1.35 1.65 davcc 2.3 2.7 supply voltage avcc3 = 3.3v cvcch dvcc15 dvcc3=cvccl cvss dvss avss=dagnd=0v dvcc3 cvccl fosc = 8to10mhz fs = 30khzto34khz fsys = 15khzto34khz 4mhzto40mhz 2.7 3.6 v p7 to p8 (used as a port) v il1 2.7v Q avcc3 Q 3.6v 0.3 avcc3 normal port v il2 2.7v Q dvcc3 Q 3.6v 0.3 dvcc3 schmitt-triggered port v il3 2.7v Q dvcc3 Q 3.6v 0.2 dvcc3 x1 v il4 1.35v Q cvcc Q 1.65v 0.1 cvcch low-level input voltage xt1 v il5 2.7v Q cvcc Q 3.6v ? 0.3 0.1 cvccl v note 1: ta = 25c, dvcc15=1.5v,dvcc3= avcc3=3.3v,dvcc=2.5v, unless otherwise noted
tmp19a43 tmp19a43 5-3 ta20 to 85 parameter symbol rating min. typ. (note 1) max. unit p7 to p8 (used as a port) normal port v ih1 2.7v Q avcc3 Q 3.6v 0.7 avcc3 normal port v ih2 2.7v Q dvcc3 Q 3.6v 0.7 dvcc3 schmitt-triggered port v ih3 2.7v Q dvcc3 Q 3.6v 0.8 dvcc3 x1 v ih4 1.35v Q cvcch Q 1.65v 0.9 cvcch high-level input voltage xt2 v ih4 2.7v Q cvccl Q 3.6v 0.9 cvccl dvcc3 + 0.3 dvcc15 + 0.2 cvcch + 0.2 cvccl+0.3 v low-level output voltage v ol i ol = 2ma dvcc3 R 2.7v 0.4 high-level output voltage v oh i oh = ? 2ma dvcc3 R 2.7v 2.4 v note 1: ta = 25c, dvcc15=1.5v,dvcc3= avcc3=3.3v,dvcc=2.5v, unless otherwise noted
tmp19a43 tmp19a43 5-4 5.3 dc electrical characteristics (2/3) ta20 to 85 parameter symbol rating min. typ. (note 1) max. unit input leakage current i li 0.0 Q v in Q dvcc15 0.0 Q v in Q dvcc3 0.0 Q v in Q avcc3 0.0 Q v in Q davcc 0.02 5 output leakage current i lo 0.2 Q v in Q dvcc15 ? 0.2 0.2 Q v in Q dvcc3 ? 0.2 0.2 Q v in Q avcc3 ? 0.2 0.2 Q v in Q davcc ? 0.2 0.05 10 a pull-up resister at reset rrst dvcc3 = 2.7vto3.6v 20 50 150 k schmitt-triggered port vth 2.7v Q dvcc3 Q 3.6v 0.3 0.6 v programmable pull-up/ pull-down resistor pkh dvcc3 = 2.7v to3.6v 20 50 150 k pin capacitance (except power supply pins) c io fc = 1mhz 10 pf note 1: ta = 25c, dvcc15=1.5v,dvcc3= avcc3=3.3v,dvcc=2.5v, unless otherwise noted
tmp19a43 tmp19a43 5-5 5.4 dc electrical characteristics (3/3) dvcc15 cvcch 1.35vto1.65v, cvccl= dvcc3 avcc3 2.7vto3.6v, davcc=2.3vto2.7v ta 20 to 85 parameter symbol rating min. typ. (note 1) max. unit normal (note 2): gear = 1/1 50 74 idle(doze) (note 3) 20 29 idle(halt) (note 3) f sys = 40 mhz ( f osc = 10 mhz) 18 28 ma slow (note 4) fs = 32.768khz 140 995 a sleep (note 4) fs = 32.768khz 30 985 a stop i cc 27 980 a note 1: ta = 25c, dvcc15=1.5v,dvcc3= avcc3=3.3v,dvcc=2.5v, unless otherwise noted (note1) i cc normal: measured with the cpu dhrystone operati ng ( dsu is excluded.), ram, flash. all functions operating. d/a and a/d excluded. (note2) i cc idle : measured with all functions stoping. (note3) i cc slow sleep : measured with rtc on low-speed i cc the current where flows is included. dvcc15 dvcc3 cvcch cvccl avcc3 davcc
tmp19a43 tmp19a43 5-6 5.5 10-bit adc electrical characteristics dvcc15 cvcch 1.35vto1.65v, cvccl= dvcc3 avcc3 vrefh 2.7vto3.6v, davcc=2.3vto2.7v,avss = dvss ,ta 20 to 85 avcc3 load capacitanc = 3.3f, vrefh load capacitanc = 3.3f parameter symbol rating min typ max unit analog reference voltage ( + ) vrefh 2.7 3.3 3.6 v analog reference voltage ( ? ) vrefl avss avss avss v analog input voltage vain vrefl vrefh v a/d conversion dvss = avss = vrefl 4.5 5.5 ma analog supply current non-a/d conversion iref dvss = avss = vrefl 0.02 5 a supply current a/d conversion ? non-iref 3 ma inl error 2 3 dnl error 1 2 offset error 2 4 fullscale error ? ain resistance Q 600 ain load capacitance Q 30pf conversion time R 1.15 s 2 4 inl error 2 3 dnl error 1 2 offset error 2 4 fullscale error ? ain resistance Q 600 ain load capacitance R 0.1 f conversion time R 1.15 s 2 4 inl error 2 3 dnl error 1 2 offset error 2 4 fullscale error ? ain resistance Q 1.3k ain load capacitance R 0.1 f conversion time R 1.15 s 2 4 inl error 2 3 dnl error 1 2 offset error 2 4 fullscale error ? ain resistance Q 10k ain load capacitance R 0.1 f conversion time R 2.30 s 2 4 lsb (note 1) 1lsb = (vrefh ? vrefl) / 1024[v]
tmp19a43 tmp19a43 5-7 5.6 8bit d/a electrical characteristics dvcc15 cvcch 1.35v to 1.65v, cvccl= dvcc3 avcc3 2.7v to 3.6v, davcc=2.3v to 2.7v parameter symbol rating min typ max unit analog reference voltage ( + ) davref 2.3 2.5 2.7 v = 1 n=0,1 1 2 ma analog supply current = 0 n=0,1 idref 0.02 5 a supply current icc 5 ma output current ida0 ida1 1 ma range of output voltage da0 da1 dagnd 0.3 davcc 0.3 v fullscale error ? 2 3 lsb (note 1) 1lsb = (davref ? dagnd) / 256[v] (note 2) idref current valu is in the dual channel operation . (note 3) no guarantee about relative ac curacy in the dual channel operation (note 4) load maximum capacitance of each dax pin is 100pf.
tmp19a43 tmp19a43 5-8 5.7 ac electrical characteristics 5.7.1 multiplex bus mode (1) dvcc15 cvcc15 1.35vto1.65v, avcc3 = 2.7vto3.6v dvcc3 2.7vto3.6v davcc = 2.3vto2.7v,ta = 20to85 c ale width = 1 clock cycle, 2 programmed wait state equation 40 mhz (fsys) (note) no. parameter symbol min max min max unit 1 system clock period (x) t sys 25 ns 2 a0-a15 valid to ale low t al x ?11 14.0 ns 3 a0-a15 hold after ale low t la x ? 8 17.0 ns 4 ale pulse width high t ll x ? 6 19.0 ns 5 ale low to rd , wr or hwr asserted t lc x ? 8 17.0 ns 6 rd , wr or hwr negated to ale high t cl x ? 8 17.0 ns 7 a0-a15 valid to rd , wr or hwr asserted t acl 2x ? 11 39.0 ns 8 a16-a23 valid to rd , wr or hwr asserted t ach 2x ? 11 39.0 ns 9 a16-a23 hold after rd , wr or hwr negated t car x ? 11 14.0 ns 10 a0-a15 valid to d0-d15 data in t adl x (2 + tw+ale) ? 43 82.0 ns 11 a16-a23 valid to d0-d15 data in t adh x (2 + tw+ale) ? 43 82.0 ns 12 rd asserted to d0-d15 data in t rd x (1 + tw) ? 40 35.0 ns 13 rd width low t rr x (1 + tw) ? 6 69 ns 14 d0-d15 hold after rd negated t hr 0 0 ns 15 rd negated to next a0-a15 output t rae x ? 6 19.0 ns 16 wr / hwr width low t ww x (1 + tw) ? 6 69.0 ns 17 d0-d15 valid to wr or hwr negated t dw x (1 + tw) ? 11 64.0 ns 18 d0-d15 hold after wr or hwr negated t wd x ? 11 14.0 ns 19 a16-a23 valid to wait input t awh x+ x (ale) (tw- 1) 32 43.0 ns 20 a0-a15 valid to wait input t awl x+ x (ale) (tw- 1) 32 43.0 ns 21 wait hold after rd , wr or hwr asserted t cw (tw - 3)-16 (tw ? 1) ? 29 9.0 46.0 ns note 1: no. 1 to 21 internal 2 wait insertion ale 1 clock @40mhz tw = w + 2n , w : number of auto wait insertion , 2n : number of external wait insertion tw = 2 + 2 * 1 = 4 ac measurement conditions: output levels: high = 0.8dvcc3 v/low 0.2dvcc3 v, cl = 30 pf input levels: high = 0.7dvcc3 v/low 0.3dvcc3 v
tmp19a43 tmp19a43 5-9 ale width = 1 clock cycles, 2 programmed wait state equation 40 mhz (fsys) (note) no. parameter symb ol min max min max unit 1 system clock period (x) t sys 25 ns 2 a0-a15 valid to ale low t al x ?11 14.0 ns 3 a0-a15 hold after ale low t la x ? 8 17.0 ns 4 ale pulse width high t ll x ? 6 19.0 ns 5 ale low to rd , wr or hwr asserted t lc x ? 8 17.0 ns 6 rd , wr or hwr negated to ale high t cl x ? 8 17.0 ns 7 a0-a15 valid to rd , wr or hwr asserted t acl 2x ? 11 39.0 ns 8 a16-a23 valid to rd , wr or hwr asserted t ach 2x ? 11 39.0 ns 9 a16-a23 hold after rd , wr or hwr negated t car x ? 11 14.0 ns 10 a0-a15 valid to d0-d15 data in t adl x (2 + tw+ale) ? 43 82.0 ns 11 a16-a23 valid to d0-d15 data in t adh x (2 + tw+ale) ? 43 82.0 ns 12 rd asserted to d0-d15 data in t rd x (1 + tw) ? 40 35.0 ns 13 rd width low t rr x (1 + tw) ? 6 69 ns 14 d0-d15 hold after rd negated t hr 0 0 ns 15 rd negated to next a0-a15 output t rae x ? 6 19.0 ns 16 wr / hwr width low t ww x (1 + tw) ? 6 69.0 ns 17 d0-d15 valid to wr or hwr negated t dw x (1 + tw) ? 11 64.0 ns 18 d0-d15 hold after wr or hwr negated t wd x ? 11 14.0 ns 19 a16-a23 valid to wait input t awh x+ x (ale) (tw- 1) 32 43.0 ns 20 a0-a15 valid to wait input t awl x+ x (ale) (tw- 1) 32 43.0 ns 21 wait hold after rd , wr or hwr asserted t cw (tw - 3)-16 (tw ? 1) ? 29 9.0 46.0 ns note 1: no. 1 to 21 internal 2 wait insertion ale 1 clock @40mhz tw = w + 2n , w : number of auto wait insertion , 2n : number of external wait insertion tw = 2 + 2 * 1 = 4 ac measurement conditions: output levels: high = 0.8dvcc3 v/low 0.2dvcc3 v, cl = 30 pf input levels: high = 0.7dvcc3 v/low 0.3dvcc3 v
tmp19a43 tmp19a43 5-10 (1) read cycle timing, ale width = 1 cl ock cycle, 1 programmed wait state t car t rr t hr t adh t adl t la d0 15 t al t cl t ll ale internalclk ad0~15 rd a0 15 t acl t ach t lc t rd a16~23 5clk/1bus cycle s1i s2 s3 s1 w1 t rae cs0~3 r/w s1 s2 s0 s1i sw
tmp19a43 tmp19a43 5-11 (2) read cycle timing, ale width = 1 cl ock cycle, 2 programmed wait state t car t rr t hr t adh t adl t la d0 15 t al t cl t ll ale internalcl k ad0~1 5 rd a0 15 t acl t ach t lc t rd a16~2 3 6clk/1bus cycle t rae cs0~3 r/w
tmp19a43 tmp19a43 5-12 (3) read cycle timing, ale width = 1 cl ock cycle, 4 programmed wait state t awl/h ale internalclk ad0~15 rd ad16~23 8clk/1bus cycle wait d0 15 a0 15 t cw cs0~3 r/w
tmp19a43 tmp19a43 5-13 (4) read cycle timing, ale width = 2 cl ock cycle, 1 programmed wait state t rr t hr t adh t adl t la d0 15 t al t cl t ll ale internalclk ad0~15 rd s1i s1x sw s2 s0 a0 15 t acl t ach t lc t rd a16~23 6clk/1bus cycle s1 t rae cs0~3 r/w s1i
tmp19a43 tmp19a43 5-14 (5) read cycle timing, ale width = 2 cl ock cycle, 4 programmed wait state t awl/h ale internalclk ad0~15 rd ad16~23 9clk/1bus cycle wait d0 15 s1x s1 sw swex s0 a0 15 sw t cw cs0~3 r/w sw s2 s1x
tmp19a43 tmp19a43 5-15 (6) write cycle timing, ale width = 2 clock cycles, zero wait state t ww t car t dw t la d0 15 t acl t ach t lc ad16~23 5clk/1bus cycle t wd
tmp19a43 tmp19a43 5-16 (7) write cycle timing, ale width = 1 clock cycles, 2 wait state t ww t car t dw t la d0 15 t acl t ach t lc ad16~2 3 6clk/1bus cycle t wd
tmp19a43 tmp19a43 5-17 (8) write cycle timing, ale width = 2 clock cycles, 4 wait state ale internalclk ad0~1 5 wr, hwr cs0~3 r/w ad16~2 3 9clk/1bus cycle t ww t car t dw t la d0 15 t acl t ach t lc t wd wait t cw t awl/h
tmp19a43 tmp19a43 5-18 5.7.2 separate bus mode (1) dvcc15 cvcch 1.35vto1.65v, dvcc3 avcc3 = 2.7vto3.6v, davcc =2.3 vto2.7v, ta = 20 to 85 c syscr3 = ?0?, 2 programmed wait state equation 40 mhz (fsys) (note) no. parameter symb ol min max min max unit 1 system clock period (x) t sys 25 ns 2 a0-a23 valid to rd , wr or hwr asserted t ac x(1 ale) ? 11 39.0 ns 3 a0-a23 hold after rd , wr or hwr negated t car x ? 11 14.0 ns 4 a0-a23 valid to d0-d15 data in t ad x (2 + tw+ale) ? 43 82.0 ns 5 rd asserted to d0-d15 data in t rd x (1 + tw) ? 40 35.0 ns 6 rd width low t rr x (1 + tw) ?6 69.0 ns 7 d0-d15 hold after rd negated t hr 0 0 ns 8 rd negated to next a0-a23 output t rae x ? 6 19.0 ns 9 wr /hwr width low t ww x (1 + tw) ?6 69.0 ns 10 wr or hwr asserted to d0-d15 valid t do 9.7 9.7 ns 11 d0-d15 hold after wr or hwr negated t dw x (1 + tw) ? 11 64.0 ns 12 d0-d15 hold after wr or hwr negated t wd x ? 11 14.0 ns 13 a0-a23 valid to wait input t aw x+ x (ale) (tw- 1) 32 43.0 ns 14 wait hold after rd , wr or hwr asserted t cw (tw - 3)-16 (tw ? 1) ? 29 9.0 46.0 ns note 1: no. 1 to 14 internal 2 wait insertion ale 1 clock @40mhz tw = w + 2n , w : number of auto wait insertion , 2n : number of external wait insertion tw = 2 + 2 * 1 = 4 ac measurement conditions: output levels: high = 0.8dvcc3 v/low 0.2dvcc3 v, cl = 30 pf input levels: high = 0.7dvcc3 v/low 0.3dvcc3 v
tmp19a43 tmp19a43 5-19 (1) read cycle timing (syscr3 = 0, 1 programmed wait state) t car t rr t hr t ad internalclk rd t ac t rd a0~23 4clk/1bus cycle s1 s2 s0 s1 sw d0
tmp19a43 tmp19a43 5-20 (2) read cycle timing (syscr3 = 1, 1 programmed wait state) t car t rr t hr t ad t ad internalclk rd s1i s1 s2 s0 s1i d0 15 d0~15 t ac t rd a16~23 5clk/1bus cycle sw t rae cs0~3 r/w
tmp19a43 tmp19a43 5-21 (3)read cycle timing syscr3 = 1, 4 externally generated wait states with n = 1) t aw internalclk rd a0~23 8clk/1bus cycle wait d0~15 d0 15 s1 sw swe sw s2 sw t cw cs0~3 r/w s1i s0
tmp19a43 tmp19a43 5-22 (4) write cycle timing (syscr3 = 1, zero wait sate) t ww t car t dw internalclk wr, hwr cs0~3 r/w t ac a0~23 4clk/1bus cycle t wd d0
tmp19a43 tmp19a43 5-23 (5) write cycle timing ( syscr3 =1, 4 wait state ) t ww t car t dw internalclk wr, hwr cs0~3 r/w t ac a0~23 4clk/1bus cycle t wd d0 15 d0~15 t do wait
tmp19a43 tmp19a43 5-24 (6) write cycle timing ( syscr3 = 1, 5 wait state ) t ww t car t dw internalclk wr, hwr cs0~3 r/w t ac a0~23 4clk/1bus cycle t wd d0 15 d0~15 t do wait
tmp19a43 tmp19a43 5-25 5.8 transfer with dma request the following shows an example of a transfer between the on-chip ram an d an external device in multiplex bus mode. ? 16-bit data bus width, non-recovery time ? level data transfer mode ? transfer size of 16 bits, devi ce port size (dps) of 16 bits ? source/destination: on-chip ram/external device the following shows transfer operation timing of th e on-chip ram to an external bus during write operation (memory-to-memory transfer). gclkin dreqn a le hwr lwr a d[15:0] n transfer (n-1) transfer (n+1) transfe cs tdreq_w tdreq_w r/w a dd a dd a dd data data data gack 2clk 2clk ??? gbstart tdreq_r tdreq_r (1) indicates the condition under which nth transfer is performed successfully. (2) indicates the condition under which (n + 1)th transfer is not performed. internal
tmp19a43 tmp19a43 5-26 dvcc15 cvcch 1.35vto1.65v, dvcc3 avcc3 = 2.7vto3.6v, davcc =2.3 vto2.7v, ta = 20to85 c equation 40 mhz (fsys) unit parameter symbol min max min max rd asserted to dreqn negated (external device to on-chip ram transfer) tdreq_r w+1x 2wale8x 51 50 224 ns wr / hwr rising to dreqn negated (on-chip ram to external device transfer) tdreq_w -(w+2)x 5+waitx51.8 -75 98.2 ns
tmp19a43 tmp19a43 5-27 5.9 serial channel timing (1) i/o interface mode dvcc32.7vto3.6v in the table below, the letter x represents the fsys cycle period, which varies depending on the programming of the clock gear function. sclk input mode sio0 to sio2 equation 40 mhz parameter sym bol min max min max unit sclk period tscy 12x 300 ns sclk clock high width(input) tsch 6x 150 ns sclk clock low width (input) tscl 6x 150 ns txd data to sclk rise or fall* toss 2x-30 20 ns txd data hold after sclk rise or fall* tohs 8x-15 185 ns rxd data valid to sclk rise or fall* tsrd 30 30 ns rxd data hold after sclk rise or fall* thsr 2x+30 80 ns * sclk rise or fall: measured relative to the programmed active edge of sclk. sclk output mode sio0 to sio2 equation 40 mhz parameter sym bol min max min max unit sclk period tscy 8x 200 ns txd data to sclk rise or fall* toss 4x-10 90 ns txd data hold after sclk rise or fall* tohs 4x-10 90 ns rxd data valid to sclk rise or fall* tsrd 45 45 ns rxd data hold after sclk rise or fall* thsr 0 0 ns output data txd input data rxd sclk sck output mode/ active-high scl input mod 0 valid t oss t scy t ohs 1 2 3 t srd t hsr 0 1 2 3 valid valid valid sclk active-low sck input mode
tmp19a43 tmp19a43 5-28 5.10 high speed serial channel timing (1) i/o interface mode dvcc32.7v to 3.6v in the table below, the letter x represents the fsys cycle period, which varies depending on the programming of the clock gear function. hsclk input mode hsio0 to hsio2 equation 40 mhz parameter sym bol min max min max unit hsclk period tscy 12(x/2) 150 ns hsclk clock high width(input) tsch 3x 75 ns hsclk clock low width (input) tscl 3x 75 ns txd data to hsclk rise or fall* toss 2(x/2)-30 -5 ns txd data hold after hsclk rise or fall* tohs 8(x/2)-15 85 ns rxd data valid to hsclk rise or fall* tsrd 30 30 ns rxd data hold after hsclk rise or fall* thsr 2(x/2)+30 55 ns * hsclk rise or fall: measured relative to the programmed active edge of hsclk. hsclk output mode hsio0 to hsio2 equation 40 mhz parameter sym bol min max min max unit hsclk period tscy 8(x/2) 100 ns txd data to hsclk rise or fall* toss 4(x/2)-10 40 ns txd data hold after hsclk rise or fall* tohs 4(x/2)-10 40 ns rxd data valid to hsclk rise or fall* tsrd 45 45 ns rxd data hold after hsclk rise or fall* thsr 0 0 ns output data txd input data rxd sclk sck output mode/ active-high scl input mod 0 valid t oss t scy t ohs 1 2 3 t srd t hsr 0 1 2 3 valid valid valid sclk active-low sck input mode
tmp19a43 tmp19a43 5-29 5.11 sbi timing (1) i2c mode in the table below, the letters x repr esent the fsys periods, respectively. n denotes the value of n programmed into the sck (scl output frequency select) field in the sbi0cr. equation standard mode fast mode parameter symbol min max min max min max unit scl clock frequency tsc 0 0 100 0 400 khz hold time for start condition thd:sta 4.0 0.6 s scl clock low width (input) (note 1) tlow 4.7 1.3 s scl clock high width (output) (note 2) thigh 4.0 0.6 s setup time for a repeated start condition tsu;sta (note 5) 4.7 0.6 s data hold time (input) (note 3, 4) thd;dat 0.0 0.0 s data setup time tsu;dat 250 100 ns setup time for stop condition tsu;sto 4.0 0.6 s bus free time between stop and start conditions tbuf (note 5) 4.7 1.3 s note 1: scl clock low width (output) is calculated with : (2 n-1 +58)/(fsys/2) note 2: scl clock high width (output) is calculated with (2 n-1 +12)/(fsys/2) note 3: the output data hold time is equal to 12x note 4: the philips i 2 c-bus specification states that a device must internally provide a hold time of at least 300 ns for the sda signal to bridge the undefined regi on of the fall edge of scl. however, this sbi does not satisfy this requirement. also, the ou tput buffer for scl does not incorporate slope control of the falling edges; therefore, the equipmen t manufacturer should design so that the input data hold time shown in the table is satisfied, including tr/tf of the scl and sda lines. note 5: software-dependent sda scl t low t hd;sta t scl t high t r t su;dat t hd;dat t su;sta t su;sto t buf s: start condition sr: repeated start condition p: stop condition t f s sr p notice: on i 2 c-bus specification, maximum speed of standard mode is 100khz ,fast mode is 400khz. internal scl clock frequency setti ng should be shown above note1 & note2.
tmp19a43 tmp19a43 5-30 (2) clock-synchronous 8-bit sio mode in the tables below, the letters x represent the fsys cycle periods, respectively. the letter n denotes the value of n programmed into the sck (scl output frequency select) field in the sbi0cr1. the electrical specifications below are for an sck signal with a 50% duty cycle. sck input mode equation 40 mhz parameter symb ol min max min max unit sck period tscy 16x 400 ns sck clock high width(input) tsch 8x 200 ns sckclock low width(input) tsch 8x 200 ns so data to sck rise toss (tscy/2) ? (6x + 20) 30 ns so data hold after sck rise tohs (tscy/2) + 4x 300 ns si data valid to sck rise tsrd 0 0 ns si data hold after sck rise thsr 4x + 10 110 ns sck output mode equation 40 mhz parameter symb ol min max min max unit sck period (programmable) t scy 2 n ? t 800 ns so data to sck rise t oss (t scy /2) ? 20 380 ns so data hold after sck rise t ohs (t scy /2) ? 20 t380 ns si data valid to sck rise t srd 2x + 30 55 ns si data hold after sck rise t hsr 0 0 ns output data txd input data txd sclk 0 valid t oss t scy t ohs 1 2 3 t srd t hsr 0 1 2 3 valid valid valid t sch t scl
tmp19a43 tmp19a43 5-31 5.12 event counter in the table below, the letter x represents the fsys cycle period. equation 40 mhz parameter symbol min max min max unit clock low pulse width t vckl 2x + 100 150 ns clock high pulse width t vckh 2x + 100 150 ns 5.13 timer capture in the table below, the letter x represents the fsys cycle period. equation 40 mhz parameter symbol min max min max unit low pulse width t cpl 2x + 100 150 ns high pulse width t cph 2x + 100 150 ns 5.14 general interrupts in the table below, the letter x represents the fsys cycle period. equation 40 mhz parameter symbol min max min max unit low pulse width for int0-inta t intal x + 100 125 ns high pulse width for int0-inta t intah x + 100 125 ns 5.15 stop /sleep/slow wake-up interrupts equation 40 mhz parameter symbol min max min max unit low pulse width for int0-intb t intbl 100 100 ns high pulse width for int0-intb t intbh 100 100 ns 5.16 scout pin equation 40 mhz parameter symbol min max min max unit clock high pulse width t sch 0.5t ? 5 7.5 ns clock low pulse width t scl 0.5t ? 5 7.5 ns note: in the above table, the letter t represents the cycle period of t he scout output clock. t sch t scl scout
tmp19a43 tmp19a43 5-32 5.17 bus request and bus acknowledge signals t aba (note1) busrq a le a 0~a23, rd , wr busak cs0 ~ cs3 , w / r, hwr a d0~ad15 t baa (note2) (note2) equation 40 mhz parameter symbol min max min max unit bus float to busak asserted t aba 0 80 0 80 ns bus float after busak negated t baa 0 80 0 80 ns note 1: if the current bus cycle has not te rminated due to wait-state insertion, the tmp19a43fdxbg does not respond to busrq until the wait state ends. note 2: this broken line indicates that output buffers are disabled, not that the signals are at indeterminate states. the pin holds t he last logic value present at that pin before the bus is relinquished. this is dy namically accomplished through external load capacitances. the equipment manufacturer may maintain the bus at a predefined state by means of off-chip re stores, but he or she should design, considering the time (determined by the cr constant) it takes for a signal to reach a desired state. the on-chip, integrated programmable pullup/pulldown resistors remain active, depending on internal signal states.
tmp19a43 tmp19a43 5-33 5.18 kwup input equation 40 mhz parameter symbol min max min max unit low pulse width for key tky tbl 100 100 ns high pulse width for key tky tbh 100 100 ns 5.19 dual pulse input equation 40 mhz parameter symbol min max min max unit dual input pulse period tdcyc 8y 400 ns dual input pulse setup tabs y 20 70 ns dual input pulse hold tabh y 20 70 ns y : fsys/ a b 5.20 adtrg input equation 40 mhz parameter symbol min max min max unit low pulse width for adtrg tad l fsys/2 20 32.5 ns high pulse width for adtrg tadh fsys/2 20 32.5 ns tabs tabh tdc y c
tmp19a43 tmp19a43 5-34 5.21 dsu equation 40 mhz parameter symbol min max min max unit pcst valid to dclk negated tsetup 11 11 ns pcst hold after dclk negated thold 0.5 0.5 ns tpc valid to dclk negated tsetup 11 11 ns tpc hold after dclk negated thold 0.5 0.5 ns tpd valid to dclk negated tsetup 11 11 ns tpd hold after dclk negated thold 0.5 0.5 ns output data pcst,tpc,tpd dclk 0 t setup t tclk t hold 1 2 3 5.22 ejtag equation 10 mhz() parameter symbol min max min max unit tck valid to tms/tdi data in ttsetup 40 40 ns tms/tdi hold after tck negated tthold 50 50 ns tdo hold after tck asserted tt out 10 10 ns operating frequency of tck is 10mhz only input data tms,tdi tck valid t tclk t tsetup t thold 0 1 2 3 valid valid valid output data tdo t tout

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