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? semiconductor components industries, llc, 2001 november, 2001 rev. 3 1 publication order number: ntd4302/d ntd4302 power mosfet 68 amps, 30 volts nchannel dpak features ? ultra low r ds(on) ? higher efficiency extending battery life ? logic level gate drive ? diode exhibits high speed, soft recovery ? avalanche energy specified ? i dss specified at elevated temperature ? dpak mounting information provided applications ? dcdc converters ? low voltage motor control ? power management in portable and battery powered products: i.e., computers, printers, cellular and cordless telephones, and pcmcia cards 68 amperes 30 volts 10 m w @ v gs = 10 v device package shipping ordering information ntd4302 dpak 75 units/rail case 369a dpak (bend lead) style 2 marking diagrams & pin assignments http://onsemi.com nchannel d s g ntd43021 dpak straight lead 75 units/rail 4302 = device code y = year ww = work week t = mosfet yww t 4302 1 gate 3 source 2 drain ntd4302t4 dpak 2500/tape & reel 4 drain 1 2 3 4 yww t 4302 1 gate 3 source 2 drain 4 drain 1 2 3 4 case 369 dpak (straight lead) style 2
ntd4302 http://onsemi.com 2 maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit draintosource voltage v dss 30 vdc gatetosource voltage continuous v gs 20 vdc thermal resistance junctiontoambient (note 1) total power dissipation @ t a = 25 c continuous drain current @ t a = 25 c (note 6) continuous drain current @ t a = 100 c r q jc p d i d i d 1.65 75 68 43 c/w watts amps amps thermal resistance junctiontoambient (note 2) total power dissipation @ t a = 25 c continuous drain current @ t a = 25 c continuous drain current @ t a = 100 c pulsed drain current (note 5) r q ja p d i d i d i dm 25 5.0 18.5 11.5 60 c/w watts amps amps amps thermal resistance junctiontoambient (note 3) total power dissipation @ t a = 25 c continuous drain current @ t a = 25 c continuous drain current @ t a = 100 c pulsed drain current (note 5) r q ja p d i d i d i dm 67 1.87 11.3 7.1 36 c/w watts amps amps amps thermal resistance junctiontoambient (note 4) total power dissipation @ t a = 25 c continuous drain current @ t a = 25 c continuous drain current @ t a = 100 c pulsed drain current (note 5) r q ja p d i d i d i dm 120 1.04 8.4 5.3 28 c/w watts amps amps amps operating and storage temperature range t j , t stg 55 to 150 c single pulse draintosource avalanche energy starting t j = 25 c (v dd = 30 vdc, v gs = 10 vdc, peak i l = 17 apk, l = 5.0 mh, r g = 25 w ) e as 722 mj maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c 1. mounted on heat sink, steady state. 2. mounted on 2 square fr4 board (1 sq. 2 oz. cu 0.06 thick single sided), time 10 seconds. 3. mounted on 2 square fr4 board (1 sq. 2 oz. cu 0.06 thick single sided), steady state. 4. minimum fr4 or g10 pcb, steady state. 5. pulse test: pulse width = 300 m s, duty cycle = 2%. 6. current limited by internal lead wires.
ntd4302 http://onsemi.com 3 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drainsource breakdown voltage (v gs = 0 vdc, i d = 250 m a) positive temperature coefficient v (br)dss 30 25 vdc mv/ c zero gate voltage drain current (v gs = 0 vdc, v ds = 30 vdc, t j = 25 c) (v gs = 0 vdc, v ds = 30 vdc, t j = 125 c) i dss 1.0 10 m adc gatebody leakage current (v gs = 20 vdc, v ds = 0 vdc) i gss 100 nadc on characteristics gate threshold voltage (v ds = v gs , i d = 250 m adc) negative temperature coefficient v gs(th) 1.0 1.9 3.8 3.0 vdc static drainsource onstate resistance (v gs = 10 vdc, i d = 20 adc) (v gs = 10 vdc, i d = 10 adc) (v gs = 4.5 vdc, i d = 5.0 adc) r ds(on) 0.0078 0.0078 0.010 0.010 0.010 0.013 w forward transconductance (v ds = 15 vdc, i d = 10 adc) gfs 20 mhos dynamic characteristics input capacitance (v 24 vd v 0 vd c iss 2050 2400 pf output capacitance (v ds = 24 vdc, v gs = 0 vdc, f=10 mhz) c oss 640 800 reverse transfer capacitance f = 1 . 0 mh z ) c rss 225 310 switching characteristics (note 8) turnon delay time t d(on) 11 20 ns rise time (v dd = 25 vdc, i d = 1.0 adc, v gs 10 vdc t r 15 25 turnoff delay time v gs = 10 vdc, r g = 6 . 0 w ) t d(off) 85 130 fall time r g = 6 . 0 w ) t f 55 90 turnon delay time t d(on) 11 20 ns rise time (v dd = 25 vdc, i d = 1.0 adc, v gs 10 vdc t r 13 20 turnoff delay time v gs = 10 vdc, r g = 2.5 w ) t d(off) 55 90 fall time r g = 2 . 5 w ) t f 40 75 turnon delay time t d(on) 15 ns rise time (v dd = 24 vdc, i d = 20 adc, v gs 10 vdc t r 25 turnoff delay time v gs = 10 vdc, r g = 2.5 w ) t d(off) 40 fall time r g = 2 . 5 w ) t f 58 gate charge (v 24 vd i 2 0 ad q t 55 80 nc gaec age (v ds = 24 vdc, i d = 2.0 adc, v gs = 10 vdc) q gs (q1) 5.5 v gs = 10 vd c ) q gd (q2) 15 bodydrain diode ratings (note 7) diode forward onvoltage (i s = 2.3 adc, v gs = 0 vdc) (i s = 20 adc, v gs = 0 vdc) (i s = 2.3 adc, v gs = 0 vdc, t j = 125 c) v sd 0.75 0.90 0.65 1.0 vdc reverse recovery time (i 23ad v 0vd t rr 39 65 ns e e se eco e y e (i s = 2.3 adc, v gs = 0 vdc, di s /dt = 100 a/ m s) t a 20 s di s /dt = 100 a/ m s ) t b 19 reverse recovery stored charge q rr 0.043 m c 7. indicates pulse test: pulse width = 300 m sec max, duty cycle 2%. 8. switching characteristics are independent of operating junction temperature.
ntd4302 http://onsemi.com 4 1.6 1.4 1 1.2 0.8 0.6 10 1 100 1000 10000 40 20 50 10 30 0 60 0.005 0 30 2 1.5 1 i d , drain current (amps) 0 v gs , gatetosource voltage (v) figure 1. onregion characteristics figure 2. transfer characteristics i d , drain current (amps) 0 0.1 0.075 0.05 0.025 4 0 26810 figure 3. onresistance vs. gatetosource voltage v gs , gatetosource voltage (v) figure 4. onresistance vs. drain current and gate voltage i d , drain current (amps) r ds(on) , draintosource resistance ( w ) figure 5. onresistance variation with temperature t j , junction temperature ( c) figure 6. draintosource leakage current vs. voltage v ds , draintosource voltage (v) i dss , leakage (na) 50 50 100 75 0 25 125 150 23 6 0.00e+00 1.00e+01 0 0.01 0.015 525 20 15 10 30 v ds , draintosource voltage (v) 10 20 40 2.5 3 v gs = 0 v t j = 150 c t j = 100 c i d = 18.5 a v gs = 10 v v gs = 4.5 v v gs = 10 v t j = 25 c i d = 10 a t j = 25 c v ds > = 10 v t j = 25 c t j = 55 c t j = 100 c v gs = 10 v v gs = 7 v v gs = 5 v v gs = 4.6 v v gs = 4 v r ds(on) , draintosource resistance ( w ) r ds(on) , draintosource resistance (normalized) v gs = 4.4 v v gs = 3.8 v v gs = 3.4 v v gs = 3.2 v v gs = 3.0 v t j = 25 c 50 25 45 v gs = 2.8 v 0.5 2.00e+01 3.00e+01 4.00e+01 5.00e+01 6.00e+01
ntd4302 http://onsemi.com 5 v gs v ds 5 10 7.5 0 12.5 10 10 4000 20 10 0 c, capacitance (pf) 0 q g , total gate charge (nc) figure 7. capacitance variation figure 8. gatetosource and draintosource voltage vs. total charge v gs , gatetosource voltage (v) 1 1000 100 10 10 100 figure 9. resistive switching time variation vs. gate resistance r g , gate resistance ( w ) figure 10. diode forward voltage vs. current v sd , sourcetodrain voltage (v) i s , source current (amps) t, time (ns) 6000 010 60 0.5 0.9 0.8 0.7 0.6 1 15 5 0 20 25 gatetosource or draintosource voltage (v) 2000 3000 5000 30 2.5 i d = 2 a t j = 25 c q 2 q 1 v gs q t v dd = 24 v i d = 18.5 a v gs = 10 v t r t d(off) t d(on) t f v gs = 0 v t j = 25 c v gs = 0 v v ds = 0 v t j = 25 c c rss c iss c oss c rss c iss 20 30 40 50 1000 v d 15 25 20 0 30 10 v ds , draintosource voltage (v)
ntd4302 http://onsemi.com 6 figure 11. maximum rated forward biased safe operating area 0.1 v ds , drain-to-source voltage (volts) 1 i d , drain current (amps) r ds(on) limit thermal limit package limit 10 dc 1 100 100 10 10 ms 1 ms 100 s v gs = 10 v single pulse t c = 25 c di/dt t rr t a t p i s 0.25 i s time i s t b figure 12. diode reverse recovery waveform r q ja (t) = r(t) r q ja d curves apply for power pulse train shown read time at t 1 t j(pk) - t a = p (pk) r q ja (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 figure 13. thermal response various duty cycles t, time (seconds) rthj a (t) , effective transient thermal resistance 1000 1 d = 0.5 1e-05 1e-03 1e-02 1e-01 0.2 0.01 0.01 0.02 0.05 0.1 1e+00 1e+01 1e+03 single pulse 1e-04 1e+02 mounted to minimum recommended footprint duty cycle 100 10 0.1
ntd4302 http://onsemi.com 7 information for using the dpak surface mount package recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. with the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.190 4.826 mm inches 0.100 2.54 0.063 1.6 0.165 4.191 0.118 3.0 0.243 6.172 solder stencil guidelines prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. solder stencils are used to screen the optimum amount. these stencils are typically 0.008 inches thick and may be made of brass or stainless steel. for packages such as the sc59, sc70/sot323, sod123, sot23, sot143, sot223, so8, so14, so16, and smb/smc diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. this is not the case with the dpak and d 2 pak packages. if one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or atombstoningo may occur due to an excess of solder. for these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. the opening for the leads is still a 1:1 registration. figure 14 shows a typical stencil for the dpak and d 2 pak packages. the pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. ?? ?? ?? ?? ?? ?? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ?? ?? figure 14. typical stencil for dpak and d 2 pak packages solder paste openings stencil soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling. * * soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * * due to shadowing and the inability to set the wave height to incorporate other surface mount components, the d 2 pak is not recommended for wave soldering.
ntd4302 http://onsemi.com 8 typical solder heating profile for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones and a figure for belt speed. taken together, these control settings make up a heating aprofileo for that particular circuit board. on machines controlled by a computer, the computer remembers these profiles from one operating session to the next. figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems, but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows temperature versus time. the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/infrared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. step 1 preheat zone 1 arampo step 2 vent asoako step 3 heating zones 2 & 5 arampo step 4 heating zones 3 & 6 asoako step 5 heating zones 4 & 7 aspikeo step 6 vent step 7 cooling 200 c 150 c 100 c 5 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies desired curve for high mass assemblies 100 c 150 c 160 c 170 c 140 c figure 15. typical solder heating profile
ntd4302 http://onsemi.com 9 package dimensions style 2: pin 1. gate 2. drain 3. source 4. drain dpak case 369a13 issue ab d a k b r v s f l g 2 pl m 0.13 (0.005) t e c u j h t seating plane z dim min max min max millimeters inches a 0.235 0.250 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.033 0.040 0.84 1.01 f 0.037 0.047 0.94 1.19 g 0.180 bsc 4.58 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.090 bsc 2.29 bsc r 0.175 0.215 4.45 5.46 s 0.020 0.050 0.51 1.27 u 0.020 --- 0.51 --- v 0.030 0.050 0.77 1.27 z 0.138 --- 3.51 --- notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 123 4
ntd4302 http://onsemi.com 10 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. style 2: pin 1. gate 2. drain 3. source 4. drain 123 4 v s a k t seating plane r b f g d 3 pl m 0.13 (0.005) t c e j h dim min max min max millimeters inches a 0.235 0.250 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.033 0.040 0.84 1.01 f 0.037 0.047 0.94 1.19 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.350 0.380 8.89 9.65 r 0.175 0.215 4.45 5.46 s 0.050 0.090 1.27 2.28 v 0.030 0.050 0.77 1.27 dpak case 36907 issue m
ntd4302 http://onsemi.com 11 notes
ntd4302 http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. ntd4302/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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