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32bit tx system risc tx19a family TMP19A64C1DXBG rev1.1 2007.march.16
TMP19A64C1DXBG contents TMP19A64C1DXBG 1. ? overview and features 2. ? pin layout and pin functions 3. ?processor core 4. ?memory map 5. ? clock/standby control 6. ? interrupts 7. ? input/output ports 8. ?external bus interface 9. ? chip selector and wait contoroller 10. ? dma controller (dmac) 11. ? 16-bit timer /event counters (tmrb) 12. ? 32-bit timer (tmrc) 13. ?serial channel (sio) 14. ?serial bus interface (sbi) 15. ? analog/digital converter 16. ? watchdog timer (runaway detection timer) 17. ? backup module (clock timer ,backup ram) 18. ? key-on wakeup 19. ?rom correction function 20. ?security function 21. ? table of special function registers 22. ?electrical characteristics 23. ? notations, precautions and restrictions tmp19a64(rev1.1)-1 tmp19a64c1d tmp19a64(rev1.1)1-1 32-bit risc microprocessor - tx19 family TMP19A64C1DXBG 1. overview and features the tx19 family is a high-performance 32-bit risc pro cessor series that toshiba originally developed by integrating the mips16 tm ase (application specific extension), which is an extended instruction set of high code efficiency. tmp19a64 is a 32-bit risc microprocessor with a tx19a processor core and various peripheral functions integrated into one package. it can operate at low voltage with low power consumption. features of tmp19a64 are as follows: (1) tx19a processor core 1) improved code efficiency and operating performance have been realized through the use of two isa (instruction set architecture) modes - 16- and 32-bit isa modes. ? the 16-bit isa mode instructions are compatible with the mips16e-tx instructions of superior code efficiency at the object level. ? the 32-bit isa mode instructions are compatible w ith the tx39 instructions of superior operating performance at the object level. 2) both high performance and low power consumption have been achieved. restrictions on product use 070122ebp ? the information contained herein is s ubject to change without notice. 021023_d ? toshiba is continually working to improve the quality and re liability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulner ability to physical stress. it is the re sponsibility of the buyer, when utilizing toshiba products, to comply with th e standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failu re of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?tos hiba semiconductor reliability handbook? etc. 021023_a ? the toshiba products listed in this document are intended for usage in general electronics appl ications (computer, personal equipment, office equipment, meas uring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instru ments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. 021023_b ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_q ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assum ed by toshiba for any infringements of patents or other rights of th e third parties which may result from its use. no license is granted by implication or otherwise under any patents or other rights of toshiba or the third parties. 070122_c ? the products described in this document are subjec t to foreign exchange and foreign trade control laws. 060925_e ? for a discussion of how the reliability of microcontrollers c an be predicted, please refer to section 1.3 of the chapter entit led quality and reliability assurance/handling precautions. 030619_s tmp19a64c1d tmp19a64(rev1.1)1-2 z high performance ? almost all instructions can be executed with one clock. ? high performance is possible via a th ree-operand operation instruction. ? 5-stage pipeline ? built-in high-speed memory ? dsp function: a 32-bit multiplication and accumulation operation can be executed with one clock. z low power consumption ? optimized design using a low power consumption library ? standby function that stops the op eration of the processor core 3) high-speed interrupt response suitable for real-time control ? independency of the entry address ? automatic generation of factor -specific vector addresses ? automatic update of interrupt mask levels (2) on chip program memory and data memory product name on chip rom on chip ram tmp19a64f20axbg 2 mbytes (flash) 64 kbytes TMP19A64C1DXBG 1.5 mbytes 56 kbytes ? rom correction function: 1 word 8 blocks, 8 words 4 blocks ? backup ram: 512 bytes (3) external memory expansion ? 16-mbyte q h h e j k r c f f t g u u h q t e q f g c p f f c v g ? external data bus: separate bus/multiplexed bus : dynamic bus sizing for 8- and 16-bit widths ports. ? chip select/wait controller : 6 channels (4) dma controller : 8 channels ? data to be transferred to internal memory, in ternal i/o, external memory, and external i/o (5) 16-bit timer : 11 channels ? 16-bit interval timer mode ? 16-bit event counter mode ? 16-bit ppg output ? event capture function ? 2-phase pulse input counter function (1 channel assigned to perform this function): multiplication-by-4 mode (6) 32-bit timer ? 32-bit input capture register : 4 channels ? 32-bit compare register : 10 channels ? 32-bit time base timer : 1 channel (7) clock timer : 1 channel (8) general-purpose serial interface: 7 channels ? either uart mode or synchronous mode can be selected. tmp19a64c1d tmp19a64(rev1.1)1-3 (9) serial bus interface : 1 channel ? either i 2 c bus mode or clock synchronous mode can be selected (10) 10-bit a/d converter with (s/h) : 24 channels ? conversion speed: 54 clocks (7.85 s@54 mhz) ? start by an internal timer trigger ? fixed channel/scan mode ? single/repeat mode ? high-priority conversion mode ? timer monitor function (11) watchdog timer : 1 channel (12) interrupt source ? cpu: 2 factors ............. software interrupt instruction ? internal: 50 factors....... the order of precedence can be set over 7 levels (except the watchdog timer interrupt). ? external: 20 factors...... the order of precedence can be set over 7 levels (except the nmi interrupt). because 8 factors are associated w ith kwup, the number of interrupt factors is one. (13) 209 pins input/output ports (14) standby mode ? 4 standby modes (idle, sleep, stop and backup) (15) clock generator ? on-chip pll (multiplication by 4) ? clock gear function: the high-speed clock can be divided into 8/8, 7/8, 6/8, 5/8, 4/8, 2/8 or 1/8. ? sub-clock: slow, sleep and backup modes (32.768 khz) (16) endian: bi-endian (big-endian/little-endian) (17) maximum operating frequency ? 54 mhz (pll multiplication) (18) operating voltage range core: 1.35 v to 1.65 v i/o: 1.65 v to 3.3 v adc: 2.7 v to 3.3 v backup block : 2.3 v to 3.3 v (under normal operating conditions) : 1.8 v to 3.3 v (in backup mode) (19) package ? p-fbga281 (13 mm 13 mm, 0.65 mm pitch) tmp19a64c1d tmp19a64(rev1.1)1-4 tx19 processor core tx19a cpu mac ejtag 1.5-mbyte flash 56-kbyte ram rom correction dmac ( 8ch ) cg intc ebif i/o bus i/f 16-bit tmrb 0 to a ( 11ch ) 32-bit tmrc tbt (1ch) 32-bit tmrc input capture 0 to 3 ( 4ch ) 32-bit tmrc compare 0 to 9 ( 10ch ) 10-bit adc (24ch) sio/uart 0 to 6 ( 7ch ) i2c/sio ( 1ch ) port0 to port6 (also function as external bus i/f) wdt kwup 0 to 7 (8ch) port7 to port9 (also function to receive adc inputs) porta to portk, porto (also function as functional pins) portl to portn portp to portq (general-purpose ports) backup block clock timer (1ch) backup ram (512 bytes) fig. 1-1 TMP19A64C1DXBG block diagram tmp19a64c1d tmp19a64(rev1.1)2-1 2. pin layout and pin functions 2.1 pin layout fig. 2.1.1 shows the pin layout of tmp19a64. fig. 2.1.1 pin layout diagram (p-fbga281) a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 17 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 e11 e12 e13 e14 e15 e16 e17 e18 f1 f2 f3 f4 f5 f7 f8 f9 f10 f11 f12 f14 f15 f16 f17 f18 g1 g2 g3 g4 g5 g6 g13 g14 g15 g16 g17 g18 h1 h2 h3 h4 h5 h6 h13 h14 h15 h16 h17 h18 j1 j2 j3 j4 j5 j6 j13 j14 j15 j16 j17 j18 k1 k2 k3 k4 k5 k6 k13 k14 k15 k16 k17 k18 l1 l2 l3 l4 l5 l6 l13 l14 l15 l16 l17 l18 m1 m2 m3 m4 m5 m6 m13 m14 m15 m16 m17 m18 n1 n2 n3 n4 n5 n7 n8 n9 n10 n11 n12 n14 n15 n16 n17 n18 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u13 u14 u15 u16 u17 u18 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 v16 v17 table 2.1.2 shows the pin numbers and names of tmp19a64. table 2.1.2 pin numbers and names (1 of 2) pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name a1 n.c. a13 pn2 b8 p75/an5 c2 pcst3 (ejtag) c14 pm7 a2 vrefl a14 pn0 b9 pl0 c3 p92/an18 c15 pm3 a3 p90/an16 a15 pm5 b10 pl3 c4 p95/an21 c16 pk3/key3 a4 p93/an19 a16 pm1 b11 po5/txd6 c5 p82/an10 c17 cvcc15 a5 p80/an8 a17 x2 b12 po1/int1 c6 p85/an13 c18 xt2 a6 p83/an11 b1 avcc31 b13 pn3 c7 p72/an2 d1 tdo (ejtag) a7 p70/an0 b2 vrefh b14 pn1 c8 avss d2 pcst2 (ejtag) a8 p74/an4 b3 p91/an17 b15 pm4 c9 pl1 d3 dint (ejtag) a9 po7/sclk6/cts6 b4 p94/an20 b16 pm0 c10 pl4 d4 dvcc15 a10 pl2 b5 p81/an9 b17 cvss/bvss c11 po4/int4 d5 p96/an22 a11 po6/rxd6 b6 p84/an12 b18 x1 c12 pn6 d6 p86/an14 a12 po0/int0 b7 p71/an1 c1 pcst0 (ejtag) c13 pn4 d7 p73/an3 tmp19a64c1d tmp19a64(rev1.1)2-2 table 2.1.1 pin numbers and names (2 of 2) pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name d8 dvcc15 f18 p46/scout k14 pi1/int1 n18 p14/d12/ad12/a12 t8 pd4/txd4 d9 dvss g1 reset k15 pi3/int3 p1 pe4 t9 pc0/txd0 d10 pl5 g2 tdi (ejtag) k16 pi4/int4 p2 pa2/tb0out t10 pc3/txd1 d11 po3/int3 g3 fvcc15 k17 dvcc30 p3 pa3/tb1in0/int7 t11 ph4/tcout8 d12 pn7 g4 dvss k18 pi2/int2 p4 pa4/tb1in1/int8 t12 ph6 d13 pn5 g5 tovr/tsta (ejtag) l1 fvcc3 p5 pa5/tb1out t13 p53/a3 d14 pm2 g6 bw0 l2 pq1/tpd1/tpc1 (ejtag) p6 pb6/tbain0 t14 p61/a9 d15 dvcc34 g13 pk7/key7 l3 pq2/tpd2/tpc2 (ejtag) p7 pg2/tc2in t15 p21/a17/a1/a17 d16 pk2/key2 g14 breset l4 pq3/tpd3/tpc3 (ejtag) p8 pd6/sclk4/cts4 t16 p23/a19/a3/a19 d17 pk4/key4 g15 p41/cs1 l5 pe6/inta p9 pc2/sclk0/cts0 t17 p00/d0/ad0 d18 xt1 g16 p37/ale l6 pe7/intb p10 pc5/sclk1/cts1 t18 p01/d1/ad1 e1 dclk (ejtag) g17 p35/busak l13 p13/ d11/ad11/a11 p11 p52/a2 u1 pb4/tb8out e2 pcst1 (ejtag) g18 fvcc15 l14 p17/d 15/ad15/a15 p12 p62/a10 u2 pb3/tb7out e3 trst (ejtag) h1 nmi l15 fv cc15 p13 p65/a13 u3 pb7/tbain1 e4 pcst4 (ejtag) h2 dvcc31 l16 pi0/int0 p14 p26/a22/a6/a22 u4 pf1/si/scl e5 endian h3 pp7/tpd7 (ejtag) l17 p 45/cs5 p15 p02/d2/ad2 u5 pf5/dreq3 e6 p97/an23 h4 bw1 l18 pj3/dack3 p16 p10/d8/ad8/a8 u6 pg1/tc1in e7 p87/an15 h5 plloff m1 pq0/tpd0/tpc0 (ejtag) p17 p12/d10/ad10/a10 u7 pd2/rxd3 e8 p76/an6 h6 tck (ejtag) m2 pq7/tpd7/tpc7 (ejtag) p18 p11/d9/ad9/a9 u8 dvcc32 e9 p77/an7 h13 test1 m3 pq4/tpd4/tpc4 (ejtag) r1 pa0/tb0in0/int5 u9 pc7/rxd2 e10 pl6 h14 p31/wr m4 pe3 r2 pa1/tb0in1/int6 u10 ph1/tcout5 e11 pl7 h15 p32/hwr m5 pa7/tb3out r3 pf3/dreq2 u11 ph5/tcout9 e12 pm6 h16 p33/wait/rdy m6 dvcc32 r4 pf4/dack2 u12 p50/a0 e13 pk6/key6 h17 p30/rd m13 p06/ d6/ad6 r5 pf7/tbtin u13 p55/a5 e14 pk5/key5 h18 p40/cs0 m14 p07/ d7/ad7 r6 pg7/tcout3 u14 dvcc33 e15 bvcc j1 pp2/tpd2 (ejtag) m15 dvss r7 pg4/tcout0 u15 p64/a12 e16 pk1/key1 j2 pp3/tpd3 (ejtag) m16 pj0/ dreq2 r8 pd5/rxd4 u16 p20/a16/a0/a16 e17 pk0/key0 j3 pp4/tpd4 (ejtag) m17 pj2/ dreq3 r9 pc1/rxd0 u17 p24/a20/a4/a20 e18 dvcc15 j4 pp5/tpd5 (ejtag) m18 pj1/dack2 r10 pc4/rxd1 u18 fvcc3 f1 dvss j5 pp6/tpd6 (ejtag) n1 pe5 r11 ph3/tcout7 v2 pb5/tb9out f2 tms (ejtag) j6 fvcc15 n2 pe0/ txd5 r12 p51/a1 v3 pg0/tc0in f3 eje (ejtag) j13 dvss n3 pe2/sclk5/cts5 r13 p57/a7 v4 pf0/so/sda f4 busmd j14 p47 n4 pe1/rxd5 r14 p66/a14 v5 pg3/tc3in f5 boot j15 n.c. n5 pa6/tb2out r15 p25/a21/a5/a21 v6 pg6/tcout2 f7 avss j16 p44/cs4 n7 dvss r16 p03/d3/ad3 v7 pd1/txd3 f8 avss j17 p36/ r/w n8 pd7/int9 r17 p04/d4/ad4 v8 pd0/sclk2/cts2 f9 avcc32 j18 p34/busrq n9 dvcc15 r18 p05/d5/ad5 v9 pc6/txd2 f10 dvcc34 k1 pp0/tpd0 (ejtag) n10 dvss t1 pb0/tb4out v10 ph2/tcout6 f11 po2/int2 k2 pp1/tpd1 (ejtag) n11 p 56/a6 t2 pb1/tb5out v11 ph0/tcout4 f12 dvss k3 pq5/tpd5/tpc5 (ejtag) n12 dvss t3 pb2/tb6out v12 ph7 f14 bupmd k4 pq6/tpd6/tpc6 (ejtag) n14 p27/a23/a7/a23 t4 pf2/sck v13 p54/a4 f15 p42/cs2 k5 dvss n15 p15/d13/ad13/a13 t5 pf6/dack3 v14 p60/a8 f16 p43/cs3 k6 dvss n16 test3 t6 pg5/tcout1 v15 p63/a11 f17 dvcc33 k13 test2 n17 p16/d14/ad14/ a14 t7 pd3/sclk3/cts3 v16 p67/a15 v17 p22/a18/a2/a18 tmp19a64c1d tmp19a64(rev1.1)2-3 2.2 pin names and functions table 2.2.1 shows the names and functions of input/output pins. table 2.2.1 pin names and functions (1 of 6) pin name number of pins input or output function p00-p07 d0-d7 ad0-ad7 8 input/output input/output input/output port 0: input/output port that allows input/output to be set in units of bits data (lower): data buses 0 to 7 (separate bus mode) address data (lower): address data buses 0 to 7 (multiplexed bus mode) p10-p17 d8-d15 ad8-ad15 a8-a15 8 input/output input/output input/output output port 1: input/output port that allows input/output to be set in units of bits data (upper): data buses 8 to 15 (separate bus mode) address data (upper): address data buses 8 to 15 (multiplexed bus mode) address: address buses 8 to 15 (multiplexed bus mode) p20-p27 a16-a23 a0-a7 a16-a23 8 input/output output output output port 2: input/output port that allows input/output to be set in units of bits address: address buses 16 to 23 (separate bus mode) address: address buses 0 to 7 (multiplexed bus mode) address: address buses 16 to 23 (multiplexed bus mode) p30 rd 1 output output port 30: port used exclusively for output read: strobe signal for reading external memory p31 wr 1 output output port 31: port used exclusively for output write: strobe signal for writing data of d0 to d7 pins p32 hwr 1 input/output output port 32: input/output port (with pull-up) write upper-pin data: strobe signal for writing data of d8 to d15 pins p33 wait rdy 1 input/output input input port 33: input/output port (with pull-up) wait: pin for requesting cpu to put a bus in a wait state ready: pin for notifying cpu that a bus is ready p34 busrq 1 input/output input port 34: input/output port (with pull-up) bus request: signal requesting cpu to allow an exte rnal master to take the bus control authority p35 busak 1 input/output output port 35: input/output port (with pull-up) bus acknowledge: signal notifying that cpu has rel eased the bus control authority in response to busrq p36 r/w 1 input/output output port 36: input/output port (with pull-up) read/write: "1" shows a read cycle or a dummy cycle. "0" shows a write cycle. p37 ale 1 input/output output port 37: input/output port address latch enable (address latch is enabled only if access to external memory is taking place) p40 cs0 1 input/output output port 40: input/output port (with pull-up) chip select 0: "0" is output if the address is in a designated address area. p41 cs1 1 input/output output port 41: input/output port (with pull-up) chip select 1: "0" is output if the address is in a designated address area. p42 cs2 1 input/output output port 42: input/output port (with pull-up) chip select 2: "0" is output if the address is in a designated address area. p43 cs3 1 input/output output port 43: input/output port (with pull-up) chip select 3: "0" is output if the address is in a designated address area. p44 cs4 1 input/output output port 44: input/output port (with pull-up) chip select 4: "0" is output if the address is in a designated address area. p45 cs5 1 input/output output port 45: input/output port (with pull-up) chip select 5: "0" is output if the address is in a designated address area. p46 scout 1 input/output output port 46: input/output port system clock output: selectable between high- a nd low-speed clock outputs, as in the case of cpu p47 1 input/output port 47: input/output port p50-p57 a0-a7 8 input/output output port 5: input/output port that allows input/output to be set in units of bits address: address buses 0 to 7 (separate bus mode) p60-p67 a8-a15 8 input/output output port 6: input/output port that allows input/output to be set in units of bits address: address buses 8 to 15 (separate bus mode) tmp19a64c1d tmp19a64(rev1.1)2-4 table 2.2.1 pin names and functions (2 of 6) pin name number of pins input or output function p70-p77 an0-an7 8 input input port 7: port used exclusively for input analog input: input from a/d converter p80-p87 an8-an15 8 input input port 8: port used exclusively for input analog input: input from a/d converter p90-p97 an16-an23 8 input input port 9: port used exclusively for input analog input: input from a/d converter pa0 tb0in0 int5 1 input/output input input port a0: input/output port 16-bit timer 0 input 0: for inputting the c ount/capture trigger of a 16-bit timer 0 interrupt request pin 5: selectable between "h" level, "l" level, risi ng edge, and falling edge input pin with schmitt trigger pa1 tb0in1 int6 1 input/output input input port a1: input/output port 16-bit timer 0 input 1: for inputting the c ount/capture trigger of a 16-bit timer 0 interrupt request pin 6: selectable "h" leve l, "l" level, rising edge and falling edge input pin with schmitt trigger pa2 tb0out 1 input/output output port a2: input/output port 16-bit timer 0 output: 16-bit timer 0 output pin pa3 tb1in0 int7 1 input/output input input port a3: input/output port 16-bit timer 1 input 0: for inputting the c ount/capture trigger of a 16-bit timer 1 interrupt request pin 7: selectable between "h" level, "l" level, risi ng edge and falling edge input pin with schmitt trigger pa4 tb1in1 int8 1 input/output input input port a4: input/output port 16-bit timer 1 input 1: for inputting the c ount/capture trigger of a 16-bit timer 1 interrupt request pin 8: selectable between "h" level, "l" level, risi ng edge and falling edge input pin with schmitt trigger pa5 tb1out 1 input/output output port a5: input/output port 16-bit timer 1 output: 16-bit timer 1 output pin pa6 tb2out 1 input/output output port a6: input/output port 16-bit timer 2 output: 16-bit timer 2 output pin pa7 tb3out 1 input/output output port a7: input/output port 16-bit timer 3 output: 16-bit timer 3 output pin pb0 tb4out 1 input/output output port b0: input/output port 16-bit timer 4 output: 16-bit timer 4 output pin pb1 tb5out 1 input/output output port b1: input/output port 16-bit timer 5 output: 16-bit timer 5 output pin pb2 tb6out 1 input/output output port b2: input/output port 16-bit timer 6 output: 16-bit timer 6 output pin pb3 tb7out 1 input/output output port b3: input/output port 16-bit timer 7 output: 16-bit timer 7 output pin pb4 tb8out 1 input/output output port b4: input/output port 16-bit timer 8 output: 16-bit timer 8 output pin pb5 tb9out 1 input/output output port b5: input/output port 16-bit timer 9 output: 16-bit timer 9 output pin pb6 tbain0 1 input/output input port b6: input/output port 16-bit timer a input 0: for inputting the c ount/capture trigger of a 16-bit timer a 2-phase pulse counter input 0 pb7 tbain1 1 input/output input port b7: input/output port 16-bit timer a input 1: for inputting the c ount/capture trigger of a 16-bit timer a 2-phase pulse counter input 1 tmp19a64c1d tmp19a64(rev1.1)2-5 table 2.2.1 pin names and functions (3 of 6) pin name number of pins input or output function pc0 txd0 1 input/output output port c0: input/output port sending serial data 0: open drain out put pin depending on the program used pc1 rxd0 1 input/output input port c1: input/output port receiving serial data 0 pc2 sclk0 cts0 1 input/output input/output input port c2: input/output port serial clock input/output 0 ready to send serial data 0 (clear to send): open drain output pin depending on the program used pc3 txd1 1 input/output output port c3: input/output port sending serial data 1: open drain out put pin depending on the program used pc4 rxd1 1 input/output input port c4: input/output port receiving serial data 1 pc5 sclk1 cts1 1 input/output input/output input port c5: input/output port serial clock input/output 1 ready to send serial data 1 (clear to send): open drain output pin depending on the program used pc6 txd2 1 input/output output port c6: input/output port sending serial data 2: open drain out put pin depending on the program used pc7 rxd2 1 input/output input port c7: input/output port receiving serial data 2 pd0 sclk2 cts2 1 input/output input/output input port d0: input/output port serial clock input/output 2 ready to send serial data 2 (clear to send): open drain output pin depending on the program used pd1 txd3 1 input/output output port d1: input/output port sending serial data 3: open drain out put pin depending on the program used pd2 rxd3 1 input/output input port d2: input/output port receiving serial data 3 pd3 sclk3 cts3 1 input/output input/output input port d3: input/output port serial clock input/output 3 ready to send serial data 3 (clear to send): open drain output pin depending on the program used pd4 txd4 1 input/output output port d4: input/output port sending serial data 4: open drain out put pin depending on the program used pd5 rxd4 1 input/output input port d5: input/output port receiving serial data 4 pd6 sclk4 cts4 1 input/output input/output input port d6: input/output port serial clock input/output 4 ready to send serial data 4 (clear to send): open drain output pin depending on the program used pd7 int9 1 input/output input port d7: input/output port interrupt request pin 9: selectable between "h" level, "l" level, risi ng edge and falling edge input pin with schmitt trigger tmp19a64c1d tmp19a64(rev1.1)2-6 table 2.2.1 pin names and functions (4 of 6) pin name number of pins input or output function pe0 txd5 1 input/output output port e0: input/output port sending serial data 5: open drain out put pin depending on the program used pe1 rxd5 1 input/output input port e1: input/output port receiving serial data 5 pe2 sclk5 cts5 1 input/output input/output input port e2: input/output port serial clock input/output 5 ready to send serial data 5 (clear to send): open drain output pin depending on the program used pe3-pe5 3 input/output ports e3 to e5: input/output ports that allow input/output to be set in units of bits pe6 inta 1 input/output input port e6: input/output port interrupt request pin a: selectable between "h" level, "l" level, risi ng edge, and falling edge input pin with schmitt trigger pe7 intb 1 input/output input port e7: input/output port interrupt request pin b: selectable between "h" level, "l" level, risi ng edge, and falling edge input pin with schmitt trigger pf0 so sda 1 input/output output input/output port f0: input/output port pin for sending data if the serial bus interface operates in the sio mode pin for sending and receiving data if the serial bus interface operates in the i 2 c mode open drain output pin depending on the program used. input with schmitt trigger pf1 si scl 1 input/output input input/output port f1: input/output port pin for receiving data if the serial bus interface operates in the sio mode pin for inputting and outputting a clock if the serial bus interface operates in the i 2 c mode open drain output pin depending on the program used input with schmitt trigger pf2 sck 1 input/output input/output port f2: input/output port pin for inputting and outputting a clock if the se rial bus interface operates in the sio mode pf3 dreq2 1 input/output input port f3: input/output port dma request signal 2: for inputting the request to transfer data by dma from an external i/o device to dmac2 pf4 dack2 1 input/output output port f4: input/output port dma acknowledge signal 2: signal showing th at dreq2 has acknowledged a dma transfer request pf5 dreq3 1 input/output input port f5: input/output port dma request signal 3: for inputting the request to transfer data by dma from an external i/o device to dmac3 pf6 dack3 1 input/output output port f6: input/output port dma acknowledge signal 3: signal showing th at dreq3 has acknowledged a dma transfer request pf7 tbtin 1 input/output input port f7: input/output port 32-bit time base timer input: for inputting the count for 32-bit time base timer pg0-pg3 tc0in-tc3in 4 input/output input ports g0 to g3: input/output ports that allo w input/output to be se t in units of bits for inputting the capture tr igger for 32-bit timer pg4-pg7 tcou0-tcout3 4 input/output output ports g4 to g7: input/output ports that allo w input/output to be se t in units of bits outputting 32-bit timer if the re sult of a comparison is a match ph0-ph5 tcou4-tcout9 6 input/output output ports h0 to h5: input/output ports that allo w input/output to be se t in units of bits outputting 32-bit timber if the re sult of a comparison is a match ph6-ph7 2 input/output ports h6 to h7: input/output ports that allow input/output to be set in units of bits pi0 int0 1 input/output input port i0: input/output port interrupt request pin 0: selectable between "h" level, "l" level, risi ng edge and falling edge input pin with schmitt trigger pi1 int1 1 input/output input port i1: input/output port interrupt request pin 1: selectable between "h" level, "l" level, risi ng edge and falling edge input pin with schmitt trigger pi2 int2 1 input/output input port i2: input/output port interrupt request pin 2: selectable between "h" level, "l" level, risi ng edge and falling edge input pin with schmitt trigger tmp19a64c1d tmp19a64(rev1.1)2-7 table 2.2.1 pin names and functions (5 of 6) pin name number of pins input or output function pi3 int3 1 input/output input port i3: input/output port interrupt request pin 3: selectable between "h" level, "l" level, risi ng edge and falling edge input pin with schmitt trigger pi4 int4 1 input/output input port i4: input/output port interrupt request pin 4: selectable between "h" level, "l" level, risi ng edge and falling edge input pin with schmitt trigger pj0 dreq2 1 input/output input port j0: input/output port dma request signal 2: for inputting the request to transfer data by dma from an external i/o device to dmac2 pj1 dack2 1 input/output output port j1: input/output port dma acknowledge signal 2: signal showing th at dreq2 has acknowledged a dma transfer request pj2 dreq3 1 input/output input port j2: input/output port dma request signal 3: for inputting the request to transfer data by dma from an external i/o device to dmac3 pj3 dack3 1 input/output output port j3: input/output port dma acknowledge signal 3: signal showing th at dreq3 has acknowledged a dma transfer request pk0-pk7 key0-key7 8 input/output input port k: input/output port that allows i nput/output to be set in units of bits key on wake up input 0 to 7 (with pull-up) with schmitt trigger pl0-pl7 8 input/output port l: input/output port that allows input/output to be set in units of bits pm0-pm7 8 input/output port m: input/output port that allows input/output to be set in units of bits pn0-pn7 8 input/output port n: input/output port that allows input/output to be set in units of bits po0 int0 1 input/output input port o0: input/output port interrupt request pin 0: selectable between "h" level, "l" level, risi ng edge and falling edge input pin with schmitt trigger po1 int1 1 input/output input port o1: input/output port interrupt request pin 1: selectable between "h" level, "l" level, risi ng edge and falling edge input pin with schmitt trigger po2 int2 1 input/output input port o2: input/output port interrupt request pin 2: selectable between "h" level, "l" level, risi ng edge and falling edge input pin with schmitt trigger po3 int3 1 input/output input port o3: input/output port interrupt request pin 3: selectable between "h" level, "l" level, risi ng edge and falling edge input pin with schmitt trigger po4 int4 1 input/output input port o4: input/output port interrupt request pin 4: selectable between "h" level, "l" level, risi ng edge and falling edge input pin with schmitt trigger po5 txd6 1 input/output output port o5: input/output port sending serial data 6: open drain out put pin depending on the program used po6 rxd6 1 input/output input port o6: input/output port receiving serial data 6 po7 sclk6 cts6 1 input/output input/output input port o7: input/output port serial clock input/output 6 ready to send serial data 6 (clear to send): open drain output pin depending on the program used pp0-pp7 tpd0-tpd7 8 input/output output port p: input/output port that allows input/output to be set in units of bits outputting trace data from the data access address: signal for dsu-ice pq0-pq7 tpc0-tpc7 tpd0-tpd7 8 input/output output output port p: input/output port that allows input/output to be set in units of bits outputting trace data from the program counter: signal for dsu-ice outputting trace data from the data access address: signal for dsu-ice tmp19a64c1d tmp19a64(rev1.1)2-8 table 2.2.1 pin names and functions (6 of 6) pin name number of pins input or output function dclk 1 output debug clock: signal for dsu-ice eje 1 input ejtag enable: signal for dsu-ice (input with schmitt trigger and built-in noise filter) pcst4-0 5 output pc trace status: signal for dsu-ice dint 1 input debug interrupt: signal for dsu-ice (input with schmitt trigger, pull-up and built-in noise filter) tovr/tsta 1 output outputting the status of pd data overflow status: signal for dsu-ice tck 1 input test clock input: signal for testing jtag (input with schmitt trigger and pull-up) tms 1 input test mode select input: signal for te sting jtag (input with schmitt trigger and pull-up) tdi 1 input test data input: signal for testi ng jtag (input with schmitt trigger and pull-up) tdo 1 output test data output: signal for testing jtag trst 1 input test reset input: signal for testi ng jtag (input with schmitt trigger and pull-down) nmi 1 input nonmaskable interrupt request pin: pi n for requesting an interrupt at the falling edge input with schmitt trigger and built-in noise filter plloff 1 input fix this pin to the "h ( dvcc15) level."(input with schmitt trigger) reset 1 input reset: initializing lsi (with pull-up) input with schmitt trigger and built-in noise filter x1/x2 2 input/output pin for conn ecting to a high-speed oscillator xt1/xt2 2 input/output pin for conn ecting to a low-speed oscillator bupmd 1 input backup mode trigger pin: this pin must be set to "l level" in backup mode. breset 1 input backup module reset: initia lizing the backup module (with pull-up) input with schmitt trigger busmd 1 input pin for setting an external bus mode: th is pin functions as a multiplexed bus by sampling the "h (dvcc15) level" upon the rising of a reset signa l. it also functions as a separate bus by sampling "l" upon the rising of a reset signal. when performing a reset operation, pull it up or down according to a bus mode to be used. endian 1 input pin for setting endian: this pin is used to set a mode. it performs a big-endian operation by sampling the "h (dvcc15) level" upon the risi ng of a reset signal, and performs a little- endian operation by sampling "l" upon the rising of a reset signal. when performing a reset operation, pull it up or down according to the type of endian to be used. boot 1 input pin for setting a single boot mode: this pin goes into single boot mode by sampling "l" upon the rising of a reset signal. it is used to overwrite internal flash memory. by sampling "h (dvcc15) level" upon the rising of a reset signa l, it performs a normal operation. this pin should be pulled up under normal operati ng conditions. pull it up when resetting. bw0-1 2 input fix these pins to bw0 = "h (dvcc15)" and bw1 = "h (dvcc15)," respectively. (input with schmitt trigger) vrefh 1 input pin (h) for supplying the a/d converter with a reference power supply connect this pin to avcc31 if the a/d converter is not used. vrefl 1 input pin (l) for supplying the a/d converter with a reference power supply connect this pin to avss if the a/d converter is not used. avcc31-32 2 ? pin for supplying the a/d converter with a power supply. connect it to a power supply even if the a/d converter is not used. avss 3 ? a/d converter gnd pin (0 v). connect this pin to gnd even if the a/d converter is not used. test1-3 3 input test pin: to be fixed to gnd. cvcc15 1 ? pin for supplying oscillators w ith power: 1.5 v power supply cvss/bvss 1 ? gnd pin (0 v) for oscillators and backup modules dvcc15 4 ? power supply pin: 1.5 v power supply bvcc 1 ? pin exclusively for supplying backup modules with power: 3 v power supply dvcc30-34 8 ? power supply pin: 3 v power supply dvss 11 ? gnd pin (0 v) tmp19a64c1d tmp19a64(rev1.1)2-9 note 1: for busmd, endian and boot pins, the state designated for each pin ("h" or "l" level) must be maintained during one system clock before and after the rising of a reset signal. the reset pin must always be in a stable state at both "l" and "h" levels. note 2: for dreq2, dack2, dreq3 and dack3, it is necessary to go to the port function register and to select one port from two groups of ports, pf3 to pf6 and pj0 to pj3. two ports cannot be operated simultaneously to use the same function. likewise, for pins int0 through int4, one port must be selected from ports pi0 to pi4 and ports po0 to po4. table 2.2.2 shows the pin names and power supply pins. table 2.2.2 pin names and power supply pins pin name power supply pin pin name power supply pin p0 dvcc33 pcst4 to 0 dvcc31 p1 dvcc33 dclk dvcc31 p2 dvcc33 eje dvcc31 p3 dvcc33 trst dvcc31 p4 dvcc33 tdi dvcc31 p5 dvcc33 tdo dvcc31 p6 dvcc33 tms dvcc31 p7 avcc32 tck dvcc31 p8 avcc32 dint dvcc31 p9 avcc31 tov dvcc31 pa dvcc32 busmd dvcc15 pb dvcc32 boot dvcc15 pc dvcc32 endian dvcc15 pd dvcc32 nmi dvcc15 pe dvcc32 breset bvcc pf dvcc32 bupmd bvcc pg dvcc32 x1, x2 cvcc15 ph dvcc32 xt1, xt2 bvcc pi dvcc30 bw0 and 1 dvcc15 pj dvcc33 plloff dvcc15 pk dvcc34 reset dvcc15 pl dvcc34 pm dvcc34 pn dvcc34 po dvcc34 pp dvcc31 pq dvcc31 z 2.7 v avcc32 avcc31 tmp19a64c1d tmp19a64(rev1.1)2-10 table 2.2.3 shows the pin numbers and power supply pins. table 2.2.3 pin numbers and power supply pins power supply pin pin number voltage range dvcc15 d4, d8, e18, n9 1.35 v to 1.65 v cvcc15 c17 1.35 v to 1.65 v dvcc30 k17 1.65 v to 3.3 v dvcc31 h2 1.65 v to 3.3 v dvcc32 m6, u8 1.65 v to 3.3 v dvcc33 f17, u14 1.65 v to 3.3 v dvcc34 d15, f10 1.65 v to 3.3 v avcc31 b1 2.7 v to 3.3 v avcc32 f9 2.7 v to 3.3 v bvcc e15 2.3 v to 3.3 v (under normal operating conditions) 1.8 v to 3.3 v (in backup mode) tmp19a64c1d tmp19a64 (rev1.1) 3-1 3. processor core the tmp19a64 has a high-performance 32 -bit processor core (tx19a processor core). for information on the operations of this processor core, please re fer to the "tx19a family architecture." this chapter describes the functions unique to the tmp19a64 that are not explained in that document. 3.1 reset operation to reset the device, ensure that the power supply voltage is in the operating voltage range, the oscillation of the internal high-frequency oscillator has stabilized at the specified frequency and that the reset input has been "0" for at least 12 system clocks (1.78 s during external 13.5 mhz operation). note that the pll multiplication clock is quadrupled and the clock gear is initialized to the 1/8 mode during the reset period. when the reset request is authorized, ? the system control coprocessor (cp0) register of the tx19a processor core is initialized. for further details, please refer to the chapter about architecture. ? after the reset exception handling is executed, the program branches of f to the exception handler. the address to which the program branches off to (add ress where exception handling starts) is called an exception vector address. this exce ption vector address of a reset exception (for example, nonmaskable interrupt) is 0xbfc0_0000h (virtual address). ? the register of the internal i/o is initialized. ? the port pin (including the pin that can also be used by the internal i/o) is set to a general-purpose input or output port mode. (note 1) set the reset pin to "0" before turning the power on. perform the reset after the power supply voltage has stabilized suffic iently within the operating range. (note 2) the reset operation can alter the internal ram state, but does not alter data in the backup ram. (note 3) make sure that the power supply voltage has stabilized, wait for 500 s or longer, and perform the reset. (note 4) in the flash program, the reset period of 0.5 us or longer is required independently of the system clock. tmp19a64c1d tmp19a64 (rev1.1) 4-1 4. memory map fig. 4.1 shows the memory map of the tmp19a64. fig. 4.1 memory map (note 1) the internal rom is physically present in 0x1fc0_0000-0x1fdf_ffff (2 mb). the internal ram is physically present in 0xfffd_0000-0xfffd_ffff (64 kb). 0xffff_0000-0xffff_dfff (56 kb) becomes the projection area. you can access the internal ram by accessing this area. the internal backup ram area becomes 0xffff_e800-0xffff_e9ff (512 b). (note 2) for the tmp19a64, a physical space of only 16 mb is available as external address space to be accessed. it is possible to place this 16-mb physical address space in a chip select area of your choice inside the 3.5-gb physical address space of the cpu. access to internal memory, internal i/o space and reserved areas is given priority over access to the external address space. therefore, access to the external address space is denied if any of the internal memory, internal i/o space or reserved areas are being accessed. (note 3) do not place an instruction in the last four words of a physical area, specifically the last four words of an area where memory is mounted for external rom extension (this varies depending on the system of the user). internal rom: 0x1fdf_fff0-0x1fdf_ffff 0xffff ffff virtual address 16 mb reserved kseg1 (cash disabled) kseg2 (cash enabled) 16 mb reserved kseg0 (cash enabled) kuseg (cash enabled) 0xff00 0000 0xbfcf ffff 0xbfc0 0000 0xa000 0000 0x8000 0000 0x000f ffff 0x0000 0000 physical address 16 mb reserved kseg2 (1 gb) 16 mb reserved kuseg (2 gb) internal rom area projection inaccessible internal rom 512 mb internal i/o internal ram (64 kb) reserved for debugging (2 mb) user program area exception vector area 0xffff e000 0xffff 0000 (reserved) 0xff3f ffff 0x401f ffff 0x4000 0000 0x1fdf ffff 0x1fc0 0000 0xff20 0000 (reserved) maskable interrupt area 0xff00 0000 0x1fdf ffff 0x1fc0 0400 0x1fc0 0000 0xffff dfff internal ram area (56 kb) projection 0xfffd 0000 0xfffd ffff (reserved) tmp19a64c1d tmp19a64 (rev1.1) 5-1 5. clock/standby control 5.1 system operation modes the system operation modes contain the standby modes in which the processor core operations are stopped to reduce power consumption. fig. 5.1.1 state transition diagram of each operation mode is shown below. reset normal mode ( fc/ g ear value ) reset has been performed idle mode (cpu stop) (i/o selective operation) instruction interrupt stop mode (entire circuit stop) instruction interrupt state transition diagram of clock mode when no power is supplied to the backup module normal mode (fc/gear value) idle mode (cpu stop) (i/o selective operation) reset stop mode (note 1) slow mode (fs) main power on external input & main power off (note 2) external input & main power off backup mode (fs only) sleep mode (fs only) (note 2) instruction interru p t interrup t instruction interrupt instruction interru p t instruction interru p t instruction reset has been performed instruc- tion state transition diagram of clock mode when power is supplied to the backup module (note 1) stop mode: all the circuits except the backup module are brought to a stop. the backup module continues operation (fs continues oscillation). (note 2) external input: it is necessary to activate the bupmd pin during the reset period. for details, see the chapter on backup ram. fig. 5.1.1 state transition diagram of each operation mode tmp19a64c1d tmp19a64 (rev1.1) 5-2 5.2 default state of the system clock reset normal mode fc = fpll = fosc 4 fsys = fc/8 fsys = fosc/2 fperiph = fgear = fsys reset has been performed plloff pin ("h") use the pll clock fig. 5.2.1 initial stat e of the system clock fosc: high-frequency clock frequency to be input via the x1 and x2 pins fpll: clock frequency multiplied (quadrupled) by the pll fc: clock frequency when the plloff pin is in the "h" state fs: low-frequency clock frequency to be input via the xt1 and xt2 pins fgear: clock frequency selected by the sy stem control register syscr1 tmp19a64c1d tmp19a64 (rev1.1) 5-3 5.3 clock system block diagram 5.3.1 main system clock ? allows for oscillator connection or external clock input. ? keep the plloff pin (pll (quadruple)) at the "h" level. ? clock gear (8/8, 7/8, 6/8, 5/8, 4/8, 2/8, 1/8) (default is 1/8.) ? input frequency (high frequency) input frequency range maximum operating frequency lowest operating frequency pll operation (for both oscillators and external input) 8-13.5 (mhz) 54 mhz 4 mhz * * clock gear 1/8 (default) is us ed when 8 mhz (min) is input. ? input frequency (low frequency) input frequency range maximum operating frequency lowest operating frequency 30 khz to 34 khz 34 khz 30 khz (note) (precautions for switching the high-speed clock gear) switching of clock gear is executed when a value is written to the syscr1 tmp19a64c1d tmp19a64 (rev1.1) 5-5 5.4 cg registers 5.4.1 system control registers 7 6 5 4 3 2 1 0 syscr0 bit symbol xen rxen wuef prck1 prck0 (0xffff_ee00) read/write r/w r/w r/w r/w r r/w r/w r/w after reset 1 1 1 1 0 0 0 0 function high-speed oscillator 0: stop 1: oscillation write "1." high-speed oscillator after the stop mode is released 0: stop 1: oscillation write "1." this can be read as "0." control of warm-up timer (wup) for oscillator 0 write: don't care 1 write: wup start 0 read: wup finished 1 read: wup operating select prescaler clock 00: fperiph/16 01: fperiph/8 10: fperiph/4 11: fperiph/2 15 14 13 12 11 10 9 8 syscr1 bitsymbol sysckflg sysc k fpsel sgear gear2 gear1 gear0 (0xffff_ee01) read/write r r r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 1 1 1 function this can be read as "0." system clock status flag 0: high speed (fc) 1: low speed (fs) select system clock 0: high speed (fc) 1: low speed (fs) select fperiph 0: fgear 1: fc select gear of low-speed clock 0: fs/1 1:fs/2 select gear of high-speed clock (fc) 000: fc 100: fc4/8 001: fc7/8 101: reserved 010: fc6/8 110: fc2/8 011: fc5/8 111: fc1/8 23 22 21 20 19 18 17 16 syscr2 bitsymbol drvosch wupt1 wupt0 stby1 stby0 drve (0xffff_ee02) read/write r/w r/w r/w r/w r/w r/w r r/w after reset 0 0 1 0 1 1 0 0 function high-speed oscillator current control 0: high capability 1: low capability write 0. select oscillator warm-up time 00: no wup 01: 2 /input frequency 10: 2 14 /input frequency 11: 2 16 /input frequency select standby mode 00:reserved 01:stop 10:sleep 11:idle this can be read as "0." 1: drive the pin even in the stop mode. 31 30 29 28 27 26 25 24 syscr3 bitsymbol scosel1 scosel0 alesel (0xffff_ee03) read/write r r/w r/w r/w r after reset 0 0 1 1 0 0 0 0 function this can be read as "0." select scout output 00:fs 01:fperiph 10:fsys 11: t0 set ale output width 0:fsys 1 1:fsys 2 this can be read as "0." ? don't switch the sysck and the gear<2:0> simultaneously. ? if the system enters the stop mode with syscr2 tmp19a64c1d tmp19a64 (rev1.1) 5-6 5.5 system clock controller by resetting the system clock controller, the controller status is initialized to tmp19a64c1d tmp19a64 (rev1.1) 5-7 tmp19a64c1d tmp19a64 (rev1.1) 5-8 5.5.3 reducing the oscillator driving capability this function is intended for restricting oscillation nois e generated from the oscillator and reducing the power consumption of the oscillator when it is connected to the oscillator connection pin. setting the syscr2 tmp19a64c1d tmp19a64 (rev1.1) 5-9 5.6 prescaler clock controller each internal i/o (tmrb0-a, tmrc, sio0-6 and sbi) has a prescaler for dividing a clock. the clock t0 to be input to each prescaler is obtained by selecting the "fperiph" clock at the syscr1 tmp19a64c1d tmp19a64 (rev1.1) 5-10 5.9 standby controller the tx19a core has several low-consumption modes. to shift to the stop, sleep or idle (halt or doze) mode, set the rp bit in the cpo status register , and then execute th e wait instruction. before shifting to the mode, you need to select the st andby mode at the system control register (syscr2). the idle, sleep and stop modes have the following features: idle: only the cpu is stopped in this mode. the internal i/o has one bit of the on/off setting register for operation in the idle mode in the register of each module. this enables operation settings for the idle mode. when the internal i/o has been set not to operate in the idle mode, it stops operation and holds the state when the system enters the idle mode. table 5.9.1 shows a list of idle setting registers. table 5.9.1 internal i/o setting registers for the idle mode internal i/o idle m ode setting register tmrb0-a tbxrun tmp19a64c1d tmp19a64 (rev1.1) 5-11 5.9.1 cg operations in each mode table5.9.1 status of cg in each operation mode clock source mode oscillation circuit pll clock supply to peripheral i/o clock supply to cpu oscillator normal { { { { slow { partial supply (note) { idle (halt) { { selectable idle (doze) { { selectable sleep fs only backup block/2-phase pulse input counter stop { : on or clock supply : off or no clock supply (note) peripheral functions that can work in the slow mode: intc, external bus interface, io port, backup block and 2-phase pulse input counter 5.9.2 block operations in each mode table 5.9.2 block operating status in each operation mode block normal slow idle (doze) idle (halt) sleep stop backup tx19a processor core dmac intc external bus i/f io port { { { { { { { { { { { { { { { adc sio i2c tmrb tmrc wdt 2-phase counter backup block { { { { { { { { { (note 1) on/off selectable for each module { { { / (note 3) { kwup { { { { { cg { { { { { high-speed oscillator (fc) { (note 2) { { low-speed oscillator (fs) { { { { { { { { : on : off ? low-speed oscillation is active when the bvcc is applied, and not active when the bvcc is shut off. (note 1) the backup ram is inaccessible in the slow mode. (note 2) when the system ente rs the slow mode, the high-sp eed oscillator must be stopped by setting the syscr1 tmp19a64c1d tmp19a64 (rev1.1) 5-12 5.9.3 releasing the standby state the standby state can be released by an interrupt request when the interrupt level is higher than the interrupt mask level, or by the reset. the standby release source that can be used is determined by a combination of the standby mode and the state of the interr upt mask register tmp19a64c1d tmp19a64 (rev1.1) 5-13 table 5.9.3 standby release source s and standby release operations (interrupt level)>(interrupt mask) interrupt accepting state interrupt enabled ei= "1" interrupt disabled ei= "0" standby mode idle (programmable) sleep stop idle (programmable) sleep stop intwdt ? ? int0-b (note 1) { { { (note 1) kwup0-7 (note 1) { { { (note 1) intrtc { { inttba (note 2) { { inttb0-9 { intrx0-6, tx0-6 { ints { standby release source interrupt intad/adhp/adm { : starts the interrupt handling after the standby mode is released. (the lsi is initialized by the reset.) { : starts the processing at the address next to the standby instruction (without executing the interrupt handling) after the st andby mode is released. : cannot be used for releasing the standby mode ? : cannot execute masking with an interruption mask when a nonmaskable interrupt is selected. (note 1) the standby mode is released after the warm-up time has elapsed. (note 2) these operations are applicable only when the 2-phase pulse input counter mode is selected. if any other modes are selected, the operations will be the same as those for the inttb0 to inttb9. z to release the standby mode by using the level mode interrupt in the interruptible state, keep the level until the interrupt handling is started. changing the level before then will prevent the interrupt processing from starting properly. z to enter the standby mode when the cpu has disabled the acceptance of interrupts, disable interrupts other than the recovery factors in advance by using the interrupt controller (intc). otherwise, the standby mode can be released by any other interrupts than the recovery factors. z to recover from the standby mode when the cpu has disabled the acceptance of interrupts, set the interrupt level higher than the interrupt mask (interrupt level > interrupt mask). if the interrupt level is equal to or lower than the interrupt mask (interrupt level interrupt mask), the system cannot recover from the standby mode. tmp19a64c1d tmp19a64 (rev1.1) 5-14 5.9.4 stop mode in the stop mode, all the internal circuits, including the internal oscillators, are brought to a stop. the pin states in the stop mode vary depending on the settin g of the syscr2 tmp19a64c1d tmp19a64 (rev1.1) 5-15 (note)19a64 requires a recovery time from warming up state as following sleep mode (fs) normal mode (fc/ gear) idle mode reset reset release software interru p t stop mode software softwar interrupt (cpu stop) (selective i/o ) interrupt slow mode (fs) interrupt softwar softwar interrupt soft all stoped a b c d e f g h state transition diagram wup trigger state transition running mode after wup minimum required operation time before wait instruction done (sec) a stop/sleep 64 / fsys in nomal mode stop release b stop/sleep 16 / fsys in slow mode c stop/sleep 64 / fsys in nomal mode sleep release d stop/sleep - tmp19a64c1d tmp19a64 (rev1.1) 5-16 5.9.5 recovery from the stop or sleep mode 1. transition of operation modes: normal stop normal normal normal stop fsys (high-speed clock) mode cg (high-speed clock) system clock off warm-up (w-up) start of high-speed clock oscillation start of warm-up end of warm-up when @fosc=13.5 mhz selection of warm-up time syscr2 tmp19a64c1d tmp19a64 (rev1.1) 5-17 3. transition of operation modes: slow stop slow (note) the low-speed clock (f s) continues oscillation. the re is no need to make a warm-up setting. 4. transition of operation modes: slow sleep slow (note) the low-speed clock (f s) continues oscillation. the re is no need to make a warm-up setting. slow slow stop slow slow stop fsys (low-speed clock) mode cg (fs) (low-speed clock) s y stem clock off s y stem clock off fsys (low-speed clock) mode cg (fs) (low-speed clock) tmp19a64c1d tmp19a64 (rev1.1) 5-18 table 5.9.6 pin states in the stop mode in each state of syscr2 tmp19a64c1d tmp19a64 (rev1.1) 5-19 table 5.9.6 pin states in the stop mode in each state of syscr2 tmp19a64c1d tmp19a64(rev1.1) 6-1 6. interrupts 6.1 overview the features of the tx19a6 4 interrupts are as follows: ? 2 interrupts from the cpu itself (software interrupt instruction) ? 21 external pins ( nmi , int0 to intb, kwup0 to 7) ? 51 interrupts from internal i/o (including wdt interrupt) ? generation of vectors for each interrupt factor ? seven interrupt levels for each interrupt factor ? an interrupt can be used to activate the dmac. (1) preparation for interrupt settings ? settings required before generating interrupts: set the exception table base address (the base ad dress of the table of maskable interrupt jump addresses) to ivr. set the interrupt jump addresses to the "exception table base address + ivr offset address" memory. set status tmp19a64c1d tmp19a64(rev1.1) 6-2 fig. 6.1.1 interrupt connection diagram intnen standby clear control 15 detection circuit h/l level or edge setting h level 15 active h level 15 kwup int0 to b 12 kwup0 to 7 1 cg other interrupts intc core 15 h/l level or edge setting input enable/disable for each interrupt factor kwup status register imcxx register imcgxx register kwup0 to 7 register rising edge 1 1 inttba rising edge nmi wdt write bus error 3 tmrb rtc tmp19a64c1d tmp19a64(rev1.1) 6-3 (2) interrupts from external pins (int0 - intb and kwup0-7) when any external interrupt is to be used for setting to clear the standby mode, use the following steps: c set ports d set functions e set cg f clear the eicrcg and intclr registers of cg g enable interrupts with int a) int0 - intb z if it is used to clear the stop mode: imcgx tmp19a64c1d tmp19a64(rev1.1) 6-4 (3) interrupt operation z basic interrupt handling { in the interrupt handler (refer to table 6.2.1 interrupt jump address for the starting address of the interrupt handler): ? read the ivr value (in the figure, ivr value is 0x8000) ? substitute the ivr value for iclr to clear the interrupt factor. ? obtain the exception handling jump address by using the ivr value (in the figure, it is 0x8000) as the corresponding address in the table (in the figure, the "jump to" address is 0x9000). ? jump to the exception handling routine using the "jump to" address. { in the interrupt processing routine: ? execute the interrupt processing ? set ilev tmp19a64c1d tmp19a64(rev1.1) 6-5 6.2 interrupt factor the starting address of an exception handler is defined as "exception vector address." the exception vector address for a reset exceptio n and non-maskable interrupts is 0xbfc0_0000. the exception vector address for a debug exception is 0xbfc0_0480 (ejtag proben = 0). for other exceptions, the corresponding exception vector addresses are determined depending on the bev bit of status register [23] and the iv bit of the cause register [23] of the system control coprocessor register (cp0). table 6.2.1 interrupt branch address bev=0 bev=1 exception virtual address logical address virtual address logical address reset 0xbfc0_0000 0x1fc0_0000 0xbfc0_0000 0x1fc0_0000 ejtag debug (en=0) 0xbfc0_0480 0x1fc0_0480 0xbfc0_0480 0x1fc0_0480 ejtag debug (en=1) 0xff20_0200 0xff20_0200 0xff20_0200 0xff20_0200 interrupt (iv=0) 0x8000_0180 0x0000_0180 0xbfc0_0380 0x1fc0_0380 interrupt (iv=1) 0x8000_0200 0x0000_0200 0xbfc0_0400 0x1fc0_0400 all others 0x8000_0180 0x0000_0180 0xbfc0_0380 0x1fc0_0380 (note 1) if vector addresses are to be placed in the internal rom, set the status bit tmp19a64c1d tmp19a64(rev1.1) 6-6 table 6.2.2 list of hardware interrupt factors interrupt number ivr[8:0] interrupt factor interrupt control register address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 0x000 0x004 0x008 0x00c 0x010 0x014 0x018 0x01c 0x020 0x024 0x028 0x02c 0x030 0x034 0x038 0x03c 0x040 0x044 0x048 0x04c 0x050 0x054 0x058 0x05c 0x060 0x064 0x068 0x06c 0x070 0x074 0x078 0x07c 0x080 0x084 0x088 0x08c 0x090 0x094 0x098 0x09c 0x0a0 0x0a4 0x0a8 0x0ac 0x0b0 0x0b4 0x0b8 0x0bc 0x0c0 0x0c4 0x0c8 0x0cc 0x0d0 0x0d4 0x0d8 0x0dc 0x0e0 0x0e4 0x0e8 0x0ec 0x0f0 0x0f4 0x0f8 0x0fc software set int0 pin int1 pin int2 pin int3 pin int4 pin int5 pin int6 pin int7 pin int8 pin int9 pin inta pin intb pin kwup intrx0 : serial receiving (channel.0) inttx0 : serial transmit (channel.0) intrx1 : serial receiving (channel.1) inttx1 : serial transmit (channel.1) intrx2 : serial receiving (channel.2) inttx2 : serial transmit (channel.2) intsbi : serial bus interface 0 intadhp : highest priority adc complete interrupt intadm : adc monitor function interrupt inttb0 : 16-bit timer 0 inttb1 : 16-bit timer 1 inttb2 : 16-bit timer 2 inttb3 : 16-bit timer 3 inttb4 : 16-bit timer 4 intcapg : input capture group intcmp0 : compare interrupt 0 intcmp1 : compare interrupt 1 intcmp2 : compare interrupt 2 intcmp3 : compare interrupt 3 intcmp4 : compare interrupt 4 reserved intrx3 : serial receiving (channel.3) inttx3 : serial transmit (channel.3) intrx4 : serial receiving (channel.4) inttx4 : serial transmit (channel.4) intrx5 : serial receiving (channel.5) inttx5 : serial transmit (channel.5) intrx6 : serial receiving (channel.6) inttx6 : serial transmit (channel.6) inttb5 : 16-bit timer 5 inttb6 : 16-bit timer 6 inttb7 : 16-bit timer 7 inttb8 : 16-bit timer 8 inttb9 : 16-bit timer 9 inttba : 16-bit timer a intcmp5 : compare interrupt 5 intcmp6 : compare interrupt 6 intcmp7 : compare interrupt 7 intcmp8 : compare interrupt 8 intcmp9 : compare interrupt 9 intrtc : clock timer intad : adc completed intdma0 : completion of dma transfer (channel.0) intdma1 : completion of dma transfer (channel.1) intdma2 : completion of dma transfer (channel.2) intdma3 : completion of dma transfer (channel.3) intdma4 : completion of dma transfer (channel.4) intdma5 : completion of dma transfer (channel.5) intdma6 : completion of dma transfer (channel.6) intdma7 : completion of dma transfer (channel.7) imc0 imc1 imc2 imc3 imc4 imc5 imc6 imc7 imc8 imc9 imca imcb imcc imcd imce imcf 0xffff_e000 0xffff_e004 0xffff_e008 0xffff_e00c 0xffff_e010 0xffff_e014 0xffff_e018 0xffff_e01c 0xffff_e020 0xffff_e024 0xffff_e028 0xffff_e02c 0xffff_e030 0xffff_e034 0xffff_e038 0xffff_e03c tmp19a64c1d tmp19a64(rev1.1) 6-7 table 6.2.3 interrupt factors to cancel stop/sleep/idle modes number interrupt factor note 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 int0 int1 int2 int3 int4 int5 int6 int7 int8 int9 inta intb kwup intrtc inttba reserved external interrupt 0 external interrupt 1 external interrupt 2 external interrupt 3 external interrupt 4 external interrupt 5 external interrupt 6 external interrupt 7 external interrupt 8 external interrupt 9 external interrupt a external interrupt b key on wake up interrupt clock timer interrupt two-phase pulse input counter interrupt * number 0 to 13 interrupt factors can cancel stop/sleep modes. * number 14 interrupt factor can cancel the sleep mode. * each factor can clear the idle mode. tmp19a64c1d tmp19a64(rev1.1) 6-8 6.3 interrupt detection if any interrupt is used to cancel the stop mode, interrupt active states of int0 to intb must be set in the emcgxx field of the imcgx register in cg and the eimxx of the imcx register in intc must be set to "h" level. for kwup0 to 7, the emcg field of the imcgd re gister in cg must be set to "h" and the eimxx field of the imcx register in intc must be set to "h" leve l. the active state as well as enable/disable is set in kwupstn for each interrupt. for setting ot her interrupts, the eimxx field of th e imcx register in intc is used. four types of active states, "h" level, "l" level, rising edge, and falling edge, are used. when the interrupt detection circuit of tmp19a64 recogni zes that any input state matches w ith the predefined active state, it notifies the processor core or intc of an interrupt request. if the interrupts that can be used to cancel the stop mode are not to be used for canceling stop mode, it is unnecessary to configure them in cg. in this case, int0 to intb can be set only by intc and kwup 0 to 7 can be set in intc and kwupstx. the interrupt signal is negated by the interrupt handler after the interrupt factor is identified. in the case of int0 to intb, appropriate values are wr itten to the icrcg field of the eicrcg register and to the eiclr field of the intclr register in intc. kwup0 to 7 are negated by setting kwupclr. other interrupt signals are negated by writing a given value in the eiclr field of the intclr register in the intc. to negate the interrupt factor whose active state is level- sensitive, an external circuit that has asserted the intx signal must be operated so that it negates intx. however, please ensure that the level input is not negated until the specified interrupt vect or (ivr) has been read. (note) please ensure that each setting is performed in the order of setting the active state, clearing an interrupt request, and enabling an interrupt. (example int0 setting to cancel stop mode) imcga tmp19a64c1d tmp19a64(rev1.1) 6-9 6.4 interrupt priority arbitration (1) seven levels of interrupt priority seven levels of priority are available and each interrupt factor can be assigned to one of these levels. the interrupt level is set by the interrupt mode cont rol register (imcx) which has a 3-bit field (ilx) for level settings. the greater the value (interrupt level) set in imcx tmp19a64c1d tmp19a64(rev1.1) 6-10 6.5 intc register table 6.5.1 intc register map address register symbol register corresponding interrupt number 0xffff_e000 imc0 interrupt mode control register 0 3 - 0 0xffff_e004 imc1 interrupt mode control register 1 7 - 4 0xffff_e008 imc2 interrupt mode control register 2 11 - 8 0xffff_e00c imc3 interrupt mode control register 3 15 - 12 0xffff_e010 imc4 interrupt mode control register 4 19 - 16 0xffff_e014 imc5 interrupt mode control register 5 23 - 20 0xffff_e018 imc6 interrupt mode control register 6 27 - 24 0xffff_e01c imc7 interrupt mode control register 7 31 - 28 0xffff_e020 imc8 interrupt mode control register 8 35 - 32 0xffff_e024 imc9 interrupt mode control register 9 39 - 36 0xffff_e028 imca interrupt mode control register a 43 - 40 0xffff_e02c imcb interrupt mode control register b 47 - 44 0xffff_e030 imcc interrupt mode control register c 51 - 48 0xffff_e034 imcd interrupt mode control register d 55 - 52 0xffff_e038 imce interrupt mode control register e 59 - 56 0xffff_e03c imcf interrupt m ode control register f 63 - 60 0xffff_e040 ivr interrupt vector register 0xffff_e060 intclr interrupt request clear register 0xffff_e10c ilev interrupt level register (note) unless otherwise specified, the abov e registers must be 32-bit accessed for both reading and writing. tmp19a64c1d tmp19a64(rev1.1) 6-11 6.5.1 interrupt vector register (ivr) the vector of each interrupt factor to be generated is listed below. 7 6 5 4 3 2 1 0 ivr bit symbol ivr7 ivr6 ivr5 ivr4 ivr3 ivr2 ivr1 ivr0 (0xffff_e040) read/write r after reset 0 0 0 0 0 0 0 0 function the vector of the interrupt factor generated is set. 15 14 13 12 11 10 9 8 bit symbol ivr8 read/write r/w r after reset 0 0 0 0 0 0 0 0 function the vector of the interrupt factor generated is set. 23 22 21 20 19 18 17 16 bit symbol read/write r/w after reset 0 0 0 0 0 0 0 0 function 31 30 29 28 27 26 25 24 bit symbol read/write r/w after reset 0 0 0 0 0 0 0 0 function tmp19a64c1d tmp19a64(rev1.1) 6-12 6.5.2 interrupt level register 7 6 5 4 3 2 1 0 ilev bit symbol D pmask0 D cmask (0xffff_e10c) read/write r r/w (note 1) after reset 0 000 0 000 function always reads "0." interrupt mask level (previous) 0 always reads "0." interrupt mask level (current) 15 14 13 12 11 10 9 8 bit symbol D pmask2 D pmask1 read/write r after reset 0 000 0 000 function always reads "0." interrupt mask level (previous) 2 always reads "0." interrupt mask level (previous) 1 23 22 21 20 19 18 17 16 bit symbol D pmask4 D pmask3 read/write r after reset 0 000 0 000 function always reads "0." interrupt mask level (previous) 4 always reads "0." interrupt mask level (previous) 3 31 30 29 28 27 26 25 24 bit symbol mlev pmask6 D pmask5 read/write w r after reset 0 000 0 000 function interrupt level change 0: decrement the interrupt level by 1 1: change cmask interrupt mask level (previous) 6 always reads "0." interrupt mask level (previous) 5 note) this register must be 32-bit accessed. note) when a new interrupt is generated, the corres ponding interrupt level is stored in cmask and any previously stored values are shifted in their mask levels such that the previous cmask is saved in pmask0 and pmask0 is saved in pmask1 and so on. note 1) upon setting mlev to "1," set the cmask value simultaneously. the pmaskx values are unchanged. note) when tmp19a64c1d tmp19a64(rev1.1) 6-13 6.5.3 transition of interrupt mask level the transition sequence of the interrupt level register is illustrated below. fig. 6.5.3 transition of interrupt mask level pmask6 pmask5 pmask4 pmask3 pmask2 pmask1 pmask0 cmask new interrupt level pmask6 pmask5 pmask4 pmask3 pmask2 pmask1 pmask0 cmask pmask6 pmask5 pmask4 pmask3 pmask2 pmask1 pmask0 cmask "000" interrupt processing mlev="0" tmp19a64c1d tmp19a64(rev1.1) 6-14 6.5.4 interrupt level register (imcx) the interrupt level, active state, and whether it is a f actor to activate dmac or not are set for each interrupt factor. 7 6 5 4 3 2 1 0 imc0 bit symbol eim01 eim00 dm0 il02 il01 il00 (0xffff_e000) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request: 00: "l" level 01: disable 10: disable 11: disable be sure to set "00." set as dmac activation factor. 0: non- activation factor 1: interrupt number 0 is set as the activation factor always reads "0." if dm0 = 0, select the interrupt level for interrupt number 0 (software set). 000: disable interrupt 001 to 111: 1 to 7 if dm0 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim11 eim10 dm1 il12 il11 il10 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge set as dmac activation factor. 0: non- activation factor 1: interrupt number 1 to be the activation factor. always reads "0." if dm1 = 0, select the interrupt level for interrupt number 1 (int0). 000: disable interrupt 001 to 111: 1 to 7 if dm1 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim21 eim20 dm2 il22 il21 il20 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge set as dmac activation factor. 0: non- activation factor 1: interrupt number 2 to be the activation factor. always reads "0." if dm2 = 0, select the interrupt level for interrupt number 2 (int1). 000: disable interrupt 001 to 111: 1 to 7 if dm2 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim31 eim30 dm3 il32 il31 il30 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge set as dmac activation factor. 0: non- activation factor 1: interrupt number 3 to be the activation factor. always reads "0." if dm3 = 0, select the interrupt level for interrupt number 3 (int2). 000: disable interrupt 001 to 111: 1 to 7 if dm3 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 tmp19a64c1d tmp19a64(rev1.1) 6-15 7 6 5 4 3 2 1 0 imc1 bit symbol eim41 eim40 dm4 il42 il41 il40 (0xffff_e004) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge set as dmac activation factor. 0: non- activation factor 1: interrupt number 4 is set as the activation factor always reads "0." if dm4 = 0, select the interrupt level for interrupt number 4 (int3) 000: disable interrupt 001 to 111: 1 to 7 if dm4 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim51 eim50 dm5 il52 il51 il50 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge set as dmac activation factor. 0: non- activation factor 1: interrupt number 5 to be the activation factor. always reads "0." if dm5 = 0, select the interrupt level for interrupt number 5 (int4). 000: disable interrupt 001 to 111: 1 to 7 if dm5 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim61 eim60 dm6 il62 il61 il60 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge set as dmac activation factor. 0: non- activation factor 1: interrupt number 6 to be the activation factor. always reads "0." if dm6 = 0, select the interrupt level for interrupt number 6 (int5). 000: disable interrupt 001 to 111: 1 to 7 if dm6 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim71 eim70 dm7 il72 il71 il70 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge set as dmac activation factor. 0: non- activation factor 1: interrupt number 7 to be the activation factor. always reads "0." if dm7 = 0, select the interrupt level for interrupt number 7 (int6). 000: disable interrupt 001 to 111: 1 to 7 if dm7 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 tmp19a64c1d tmp19a64(rev1.1) 6-16 7 6 5 4 3 2 1 0 imc2 bit symbol eim81 eim80 dm8 il82 il81 il80 (0xffff_e008) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge set as dmac activation factor. 0: non- activation factor 1: interrupt number 8 is set as the activation factor always reads "0." if dm8 = 0, select the interrupt level for interrupt number 8 (int7). 000: disable interrupt 001 to 111: 1 to 7 if dm8 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim91 eim90 dm9 il92 il91 il90 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge set as dmac activation factor. 0: non- activation factor 1: interrupt number 9 to be the activation factor. always reads "0." if dm9 = 0, select the interrupt level for interrupt number 9 (int8). 000: disable interrupt 001 to 111: 1 to 7 if dm9 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eima1 eima0 dma ila2 ila1 ila0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge set as dmac activation factor. 0: non- activation factor 1: interrupt number 10 to be the activation factor. always reads "0." if dma = 0, select the interrupt level for interrupt number 10 (int9). 000: disable interrupt 001 to 111: 1 to 7 if dma = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eimb1 eimb0 dmb ilb2 ilb1 ilb0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge set as dmac activation factor. 0: non- activation factor 1: interrupt number 11 to be the activation factor. always reads "0." if dmb = 0, select the interrupt level for interrupt number 11 (inta) 000: disable interrupt 001 to 111: 1 to 7 if dmb = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 tmp19a64c1d tmp19a64(rev1.1) 6-17 7 6 5 4 3 2 1 0 imc3 bit symbol eimc1 eimc0 dmc ilc2 ilc1 ilc0 (0xffff_e00c) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge set as dmac activation factor. 0: non- activation factor 1: interrupt number 12 is set as the activation factor always reads "0." if dmc = 0, select the interrupt level for interrupt number 12 (intb) 000: disable interrupt 001 to 111: 1 to 7 if dmc = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eimd1 eimd0 dmd ild2 ild1 ild0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 01: "h" level be sure to set "01." set as dmac activation factor. 0: non- activation factor 1: interrupt number 13 to be the activation factor. always reads "0." if dmd = 0, select the interrupt level for interrupt number 13 (kwup) 000: disable interrupt 001 to 111: 1 to 7 if dmd = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eime1 eime0 dme ile2 ile1 ile0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 14 to be the activation factor. always reads "0." if dme = 0, select the interrupt level for interrupt number 14 (intrx0) 000: disable interrupt 001 to 111: 1 to 7 if dme = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eimf1 eimf0 dmf ilf2 ilf1 ilf0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 15 to be the activation factor. always reads "0." if dmf = 0, select the interrupt level for interrupt number 15 (inttx0) 000: disable interrupt 001 to 111: 1 to 7 if dmf = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 tmp19a64c1d tmp19a64(rev1.1) 6-18 7 6 5 4 3 2 1 0 imc4 bit symbol eim101 eim100 dm10 il102 il101 il100 (0xffff_e010) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 16 is set as the activation factor always reads "0." if dm10 = 0, select the interrupt level for interrupt number 16 (intrx1) 000: disable interrupt 001 to 111: 1 to 7 if dm10 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim111 eim110 dm11 il112 il111 il110 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 17 to be the activation factor. always reads "0." if dm11 = 0, select the interrupt level for interrupt number 17 (inttx1) 000: disable interrupt 001 to 111: 1 to 7 if dm11 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim121 eim120 dm12 il122 il121 il120 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 18 to be the activation factor. always reads "0." if dm12 = 0, select the interrupt level for interrupt number 18 (intrx2). 000: disable interrupt 001 to 111: 1 to 7 if dm12 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim131 eim130 dm13 il132 il131 il130 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 19 to be the activation factor. always reads "0." if dm13 = 0, select the interrupt level for interrupt number 19 (inttx2) 000: disable interrupt 001 to 111: 1 to 7 if dm13 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use. tmp19a64c1d tmp19a64(rev1.1) 6-19 7 6 5 4 3 2 1 0 imc5 bit symbol eim141 eim140 dm14 il142 il141 il140 (0xffff_e014) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 20 is set as the activation factor always reads "0." if dm14 = 0, select the interrupt level for interrupt number 20 (intsb1). 000: disable interrupt 001 to 111: 1 to 7 if dm14 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim151 eim150 dm15 il152 il151 il150 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 21 to be the activation factor. always reads "0." if dm15 = 0, select the interrupt level for interrupt number 21 (intadhp) 000: disable interrupt 001 to 111: 1 to 7 if dm15 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim161 eim160 dm16 il162 il161 il160 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 22 to be the activation factor. always reads "0." if dm16 = 0, select the interrupt level for interrupt number 22 (intadm). 000: disable interrupt 001 to 111: 1 to 7 if dm16 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim171 eim170 dm17 il172 il171 il170 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 23 to be the activation factor. always reads "0." if dm17 = 0, select the interrupt level for interrupt number 23 (inttb0). 000: disable interrupt 001 to 111: 1 to 7 if dm17 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use. tmp19a64c1d tmp19a64(rev1.1) 6-20 7 6 5 4 3 2 1 0 imc6 bit symbol eim181 eim180 dm18 il182 il181 il180 (0xffff_e018) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 24 is set as the activation factor always reads "0." if dm18 = 0, select the interrupt level for interrupt number 24 (inttb1). 000: disable interrupt 001 to 111: 1 to 7 if dm18 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim191 eim190 dm19 il192 il191 il190 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 25 to be the activation factor. always reads "0." if dm19 = 0, select the interrupt level for interrupt number 25 (inttb2). 000: disable interrupt 001 to 111: 1 to 7 if dm19 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim1a1 eim1a0 dm1a il1a2 il1a1 il1a0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 26 to be the activation factor. always reads "0." if dm1a = 0, select the interrupt level for interrupt number 26 (inttb3). 000: disable interrupt 001 to 111: 1 to 7 if dm1a = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim1b1 eim1b0 dm1b il1b2 il1b1 il1b0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 27 to be the activation factor. always reads "0." if dm1b = 0, select the interrupt level for interrupt number 27 (inttb4). 000: disable interrupt 001 to 111: 1 to 7 if dm1b = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use. tmp19a64c1d tmp19a64(rev1.1) 6-21 7 6 5 4 3 2 1 0 imc7 bit symbol eim1c1 eim1c0 dm1c il1c2 il1c1 il1c0 (0xffff_e01c) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 28 to be the activation factor. always reads "0." if dm1c = 0, select the interrupt level for interrupt number 28 (intcapg). 000: disable interrupt 001 to 111: 1 to 7 if dm1c = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim1d1 eim1d0 dm1d il1d2 il1d1 il1d0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 29 to be the activation factor. always reads "0." if dm1d = 0, select the interrupt level for interrupt number 29 (intcomp0). 000: disable interrupt 001 to 111: 1 to 7 if dm1d = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim1e1 eim1e0 dm1e il1e2 il1e1 il1e0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 30 to be the activation factor. always reads "0." if dm1e = 0, select the interrupt level for interrupt number 30 (intcmp1). 000: disable interrupt 001 to 111: 1 to 7 if dm1e = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim1f1 eim1f0 dm1f il1f2 il1f1 il1f0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 31 to be the activation factor. always reads "0." if dm1f = 0, select the interrupt level for interrupt number 31 (intcmp2) 000: disable interrupt 001 to 111: 1 to 7 if dm1f = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use. tmp19a64c1d tmp19a64(rev1.1) 6-22 7 6 5 4 3 2 1 0 imc8 bit symbol eim201 eim200 dm20 il202 il201 il200 (0xffff_e020) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 32 to be the activation factor. always reads "0." if dm20 = 0, select the interrupt level for interrupt number 32 (intcmp3) 000: disable interrupt 001 to 111: 1 to 7 if dm20 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim211 eim210 dm21 il212 il211 il210 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 33 to be the activation factor. always reads "0." if dm21 = 0, select the interrupt level for interrupt number 33 (intcmp4). 000: disable interrupt 001 to 111: 1 to 7 if dm21 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim221 eim220 dm26 il222 il221 il220 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." be sure to set "00." be sure to set "0." always reads "0." be sure to set "00." 31 30 29 28 27 26 25 24 bit symbol eim231 eim230 dm23 il232 il231 il230 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 35 to be the activation factor. always reads "0." if dm23 = 0, select the interrupt level for interrupt number 35 (intrx3) 000: disable interrupt 001 to 111: 1 to 7 if dm23 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use. tmp19a64c1d tmp19a64(rev1.1) 6-23 7 6 5 4 3 2 1 0 imc9 bit symbol eim241 eim240 dm24 il242 il241 il240 (0xffff_e024) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 36 to be the activation factor. always reads "0." if dm24 = 0, select the interrupt level for interrupt number 36 (inttx3). 000: disable interrupt 001 to 111: 1 to 7 if dm24 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim251 eim250 dm25 il252 il251 il250 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 37 to be the activation factor. always reads "0." if dm25 = 0, select the interrupt level for interrupt number 37 intrx4). 000: disable interrupt 001 to 111: 1 to 7 if dm25 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim261 eim260 dm26 il262 il261 il260 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 38 to be the activation factor. always reads "0." if dm26 = 0, select the interrupt level for interrupt number 38 (inttx4). 000: disable interrupt 001 to 111: 1 to 7 if dm26 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim271 eim270 dm27 il272 il271 il270 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 39 to be the activation factor. always reads "0." if dm27 = 0, select the interrupt level for interrupt number 39 (intrx5). 000: disable interrupt 001 to 111: 1 to 7 if dm27 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use. tmp19a64c1d tmp19a64(rev1.1) 6-24 7 6 5 4 3 2 1 0 imca bit symbol eim281 eim280 dm28 il282 il281 il280 (0xffff_e028) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 40 to be the activation factor. always reads "0." if dm28 = 0, select the interrupt level for interrupt number 40 (inttx5). 000: disable interrupt 001 to 111: 1 to 7 if dm28 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim291 eim290 dm29 il292 il291 il290 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 41 to be the activation factor. always reads "0." if dm29 = 0, select the interrupt level for interrupt number 41 (intrx6). 000: disable interrupt 001 to 111: 1 to 7 if dm29 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim2a1 eim2a0 dm2a il2a2 il2a1 il2a0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 42 to be the activation factor. always reads "0." if dm2a = 0, select the interrupt level for interrupt number 42 (inttx6). 000: disable interrupt 001 to 111: 1 to 7 if dm2a = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim2b1 eim2b0 dm2b il2b2 il2b1 il2b0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 43 to be the activation factor. always reads "0." if dm2b = 0, select the interrupt level for interrupt number 43 (inttb5). 000: disable interrupt 001 to 111: 1 to 7 if dm2b = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use. tmp19a64c1d tmp19a64(rev1.1) 6-25 7 6 5 4 3 2 1 0 imcb bit symbol eim2c1 eim2c0 dm2c il2c2 il2c1 il2c0 (0xffff_e02c) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 44 to be the activation factor. always reads "0." if dm2c = 0, select the interrupt level for interrupt number 44 (inttb6). 000: disable interrupt 001 to 111: 1 to 7 if dm2c = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim2d1 eim2d0 dm2d il2d2 il2d1 il2d0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 45 to be the activation factor. always reads "0." if dm2d = 0, select the interrupt level for interrupt number 45 (inttb7). 000: disable interrupt 001 to 111: 1 to 7 if dm2d = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim2e1 eim2e0 dm2e il2e2 il2e1 il2e0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 46 to be the activation factor. always reads "0." if dm2e = 0, select the interrupt level for interrupt number 46 (inttb8). 000: disable interrupt 001 to 111: 1 to 7 if dm2e = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim2f1 eim2f0 dm2f il2f2 il2f1 il2f0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 47 to be the activation factor. always reads "0." if dm2f = 0, select the interrupt level for interrupt number 47 (inttb9). 000: disable interrupt 001 to 111: 1 to 7 if dm2f = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use. tmp19a64c1d tmp19a64(rev1.1) 6-26 7 6 5 4 3 2 1 0 imcc bit symbol eim301 eim300 dm30 il302 il301 il300 (0xffff_e030) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 01: "h" level be sure to set "01." set as dmac activation factor. 0: non- activation factor 1: interrupt number 48 to be the activation factor. always reads "0." if dm30 = 0, select the interrupt level for interrupt number 48 (inttba). 000: disable interrupt 001 to 111: 1 to 7 if dm30 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim311 eim310 dm31 il312 il311 il310 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 1: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 49 to be the activation factor. always reads "0." if dm31 = 0, select the interrupt level for interrupt number 49 (intcmp5) 000: disable interrupt 001 to 111: 1 to 7 if dm31 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim321 eim320 dm32 il322 il321 il320 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 1: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 50 to be the activation factor. always reads "0." if dm32 = 0, select the interrupt level for interrupt number 50 (intcmp6) 000: disable interrupt 001 to 111: 1 to 7 if dm32 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim331 eim330 dm33 il332 il331 il330 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 51 to be the activation factor. always reads "0." if dm33 = 0, select the interrupt level for interrupt number 51 (intcmp7) 000: disable interrupt 001 to 111: 1 to 7 if dm33 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use. tmp19a64c1d tmp19a64(rev1.1) 6-27 7 6 5 4 3 2 1 0 imcd bit symbol eim341 eim340 dm34 il342 il341 il340 (0xffff_e034) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 52 to be the activation factor. always reads "0." if dm34 = 0, select the interrupt level for interrupt number 52 (intcmp8) 000: disable interrupt 001 to 111: 1 to 7 if dm34 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim351 eim350 dm35 il352 il351 il350 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 53 to be the activation factor. always reads "0." if dm35 = 0, select the interrupt level for interrupt number 53 (intcmp9) 000: disable interrupt 001 to 111: 1 to 7 if dm35 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim361 eim360 dm36 il362 il361 il360 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 01: "h" level be sure to set "01." set as dmac activation factor. 0: non- activation factor 1: interrupt number 54 to be the activation factor. always reads "0." if dm36 = 0, select the interrupt level for interrupt number 54 (intrtc) 000: disable interrupt 001 to 111: 1 to 7 if dm36 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim371 eim370 dm37 il372 il371 il370 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 11: rising edge be sure to set "11." set as dmac activation factor. 0: non- activation factor 1: interrupt number 55 to be the activation factor. always reads "0." if dm37 = 0, select the interrupt level for interrupt number 55 (intad) 000: disable interrupt 001 to 111: 1 to 7 if dm37 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use. tmp19a64c1d tmp19a64(rev1.1) 6-28 7 6 5 4 3 2 1 0 imce bit symbol eim381 eim380 dm38 il382 il381 il380 (0xffff_e038) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 10: falling edge be sure to set "10." set as dmac activation factor. 0: non- activation factor 1: interrupt number 56 to be the activation factor. always reads "0." if dm38 = 0, select the interrupt level for interrupt number 56 (intdma0) 000: disable interrupt 001 to 111: 1 to 7 if dm38 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim391 eim390 dm39 il392 il391 il390 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 10: falling edge be sure to set "10." set as dmac activation factor. 0: non- activation factor 1: interrupt number 57 to be the activation factor. always reads "0." if dm39 = 0, select the interrupt level for interrupt number 57 (intdm1) 000: disable interrupt 001 to 111: 1 to 7 if dm39 = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim3a1 eim3a0 dm3a il3a2 il3a1 il3a0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 10: falling edge be sure to set "10." set as dmac activation factor. 0: non- activation factor 1: interrupt number 58 to be the activation factor. always reads "0." if dm3a = 0, select the interrupt level for interrupt number 58 (intdma2) 000: disable interrupt 001 to 111: 1 to 7 if dm3a = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim3b1 eim3b0 dm3b il3b2 il3b1 il3b0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 10: falling edge be sure to set "10." set as dmac activation factor. 0: non- activation factor 1: interrupt number 59 to be the activation factor. always reads "0." if dm3b = 0, select the interrupt level for interrupt number 59 (intdma3). 000: disable interrupt 001 to 111: 1 to 7 if dm3b = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use. tmp19a64c1d tmp19a64(rev1.1) 6-29 7 6 5 4 3 2 1 0 imcf bit symbol eim3c1 eim3c0 dm3c il3c2 il3c1 il3c0 (0xffff_e03c) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 10: falling edge be sure to set "10." set as dmac activation factor. 0: non- activation factor 1: interrupt number 60 to be the activation factor. always reads "0." if dm3c = 0, select the interrupt level for interrupt number 60 (intdma4) 000: disable interrupt 001 to 111: 1 to 7 if dm3c = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 15 14 13 12 11 10 9 8 bit symbol eim3d1 eim3d0 dm3d il3d2 il3d1 il3d0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 10: falling edge be sure to set "10." set as dmac activation factor. 0: non- activation factor 1: interrupt number 61 to be the activation factor. always reads "0." if dm3d = 0, select the interrupt level for interrupt number 61 (intdma5) 000: disable interrupt 001 to 111: 1 to 7 if dm3d = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 23 22 21 20 19 18 17 16 bit symbol eim3e1 eim3e0 dm3e il3e2 il3e1 il3e0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 10: falling edge be sure to set "10." set as dmac activation factor. 0: non- activation factor 1: interrupt number 62 to be the activation factor. always reads "0." if dm3e = 0, select the interrupt level for interrupt number 62 (intdma6). 000: disable interrupt 001 to 111: 1 to 7 if dm3e = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 31 30 29 28 27 26 25 24 bit symbol eim3f1 eim3f0 dm3f il3f2 il3f1 il3f0 read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function always reads "0." selects active state of interrupt request. 10: falling edge be sure to set "10." set as dmac activation factor. 0: non- activation factor 1: interrupt number 63 to be the activation factor. always reads "0." if dm3f = 0, select the interrupt level for interrupt number 63 (intdma7). 000: disable interrupt 001 to 111: 1 to 7 if dm3f = 1, select the dmac channel. 000 to 011: 0 to 3 100 to 111: 4 to 7 note: default values of eimxx0 and eimxx1 are different from the values to be used. properly set them to the specified values before use. tmp19a64c1d tmp19a64(rev1.1) 6-30 note 1: please ensure that the type of active state is selected before enabling an interrupt request. note 2: when making interrupt requests dmac activation factors, please ensure that you put the dmac into standby mode after setting the intc. 6.5.5 interrupt request clear register this register is used to clear in terrupt requests. interrupt requests ar e cleared by setting the ivr tmp19a64c1d tmp19a64(rev1.1) 6-31 6.5.6 intcg registers (interrupts to clear stop, sleep and idle modes) z int0 to intb, kwup0 to kwup7: stop/sleep/idle z intrtc, inttba (two-phase pulse input counter): sleep 7 6 5 4 3 2 1 0 imcga bit symbol emcg01 emcg00 int0en (0xffff_ee10) read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." always reads "0." set active state of int0 standby clear request. 00: "l" level 01: ?h? level 10: falling edge 11: rising edge always reads "0." always reads "0." always reads "0." int0 clear input 0: disable 1: enable 15 14 13 12 11 10 9 8 bit symbol emcg11 emcg10 int1en read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." always reads "0." set active state of int1 standby clear request. 00: "l" level 01: ?h? level 10: falling edge 11: rising edge always reads "0." always reads "0." always reads "0." int1 clear input 0: disable 1: enable 23 22 21 20 19 18 17 16 bit symbol emcg21 emcg20 int2en read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." always reads "0." set active state of int2 standby clear request. 00: "l" level 01: ?h? level 10: falling edge 11: rising edge always reads "0." always reads "0." always reads "0." int2 clear input 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol emcg31 emcg30 int3en read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." always reads "0." set active state of int3 standby clear request. 00: "l" level 01: ?h? level 10: falling edge 11: rising edge always reads "0." always reads "0." always reads "0." int3 clear input 0: disable 1: enable tmp19a64c1d tmp19a64(rev1.1) 6-32 7 6 5 4 3 2 1 0 imcgb bit symbol emcg41 emcg40 int4en (0xffff_ee14) read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." always reads "0." set active state of int4 standby clear request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge always reads "0." always reads "0." always reads "0." int4 clear input 0: disable 1: enable 15 14 13 12 11 10 9 8 bit symbol emcg51 emcg50 int5en read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." always reads "0." set active state of int5 standby clear request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge always reads "0." always reads "0." always reads "0." int5 clear input 0: disable 1: enable 23 22 21 20 19 18 17 16 bit symbol emcg61 emcg60 int6en read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." always reads "0." set active state of int6 standby clear request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge always reads "0." always reads "0." always reads "0." int6 clear input 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol emcg71 emcg70 int7en read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." always reads "0." set active state of int7 standby clear request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge always reads "0." always reads "0." always reads "0." int7 clear input 0: disable 1: enable tmp19a64c1d tmp19a64(rev1.1) 6-33 7 6 5 4 3 2 1 0 imcgc bit symbol emcg81 emcg80 int8en (0xffff_ee18) read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." always reads "0." set active state of int8 standby clear request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge always reads "0." always reads "0." always reads "0." int8 clear input 0: disable 1: enable 15 14 13 12 11 10 9 8 bit symbol emcg91 emcg90 int9en read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." always reads "0." set active state of int9 standby clear request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge always reads "0." always reads "0." always reads "0." int9 clear input 0: disable 1: enable 23 22 21 20 19 18 17 16 bit symbol emcga1 emcga0 intaen read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." always reads "0." set active state of inta standby clear request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge always reads "0." always reads "0." always reads "0." inta clear input 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol emcgb1 emcgb0 intben read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." always reads "0." set active state of intb standby clear request. 00: "l" level 01: "h" level 10: falling edge 11: rising edge always reads "0." always reads "0." always reads "0." intb clear input 0: disable 1: enable tmp19a64c1d tmp19a64(rev1.1) 6-34 7 6 5 4 3 2 1 0 imcgd bit symbol emcgc1 emcgc0 kwupen (0xffff_ee1c) read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." always reads "0." set active state of kwup standby clear request. 01: "h" level be sure to set "01." always reads "0." always reads "0." always reads "0." kwup clear input 0: disable 1: enable 15 14 13 12 11 10 9 8 bit symbol emcgd1 emcgd0 intrtcen read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function always reads "0." always reads "0." set active state of intrtc standby clear request. 11: rising edge be sure to set "11." always reads "0." always reads "0." always reads "0." intrtc clear input 0: disable 1: enable 23 22 21 20 19 18 17 16 bit symbol emcge1 emcge0 inttbaen read/write r r/w r r/w after reset 0 0 1 0 0 0 function always reads "0." always reads "0." set active state of inttba standby clear request. 11: rising edge be sure to set "11." always reads "0." always reads "0." always reads "0." inttba clear input 0: disable 1: enable 31 30 29 28 27 26 25 24 bit symbol read/write r r/w r r/w after reset 0 0 1 0 0 0 function always reads "0." always reads "0." undefined always reads "0." always reads "0." always reads "0." write "1." note: in imcgd, the initial value to request clearing of the standby mode is different from the setting to be made in an operation condition. be sure to set appropriate parameters before it is used to clear the standby mode. tmp19a64c1d tmp19a64(rev1.1) 6-35 be sure to set active state of the clear request if interrupt is enabled for clearing the stop, sleep, or idle standby mode. (note1) when using interrupts, be sure to follow the following sequence of action: c if shared with other general ports, enable the target interrupt input. d set active state, etc., upon initialization. e clear interrupt requests. f enable interrupts (note 2) settings must be performed while interrupts are disabled. (note 3) for clearing the stop, sleep and idle m odes with tmp19a64, 15 factors, i.e., int0 to intb, intrtc, inttba, and kwup (kwup0 to 7) are available as clearing interrupts. whether or not int0 to intb are to be used as clearing interrupts as well as active state edge/level selection is set with cg. whether or not kwup0 to 7 are to be used as stop/sleep/idle clearing interrupts is set with cg and active state edge/level selection is set with kwupstn tmp19a64c1d tmp19a64(rev1.1) 6-36 eicrcg 7 6 5 4 3 2 1 0 (0xffff_ee20) bit symbol icrcg3 icrcg2 icrcg1 icrcg0 read/write r w/r after reset 0 0 0 0 0 0 0 0 function always reads "0." always reads "0." clear interrupt requests. 0000: int0 0101: int5 1010: inta 0001: int1 0110: int6 1011: intb 0010: int2 0111: int7 1100: kwup 0011: int3 1000: int8 1101: intrtc 0100: int4 1001: int9 1110: inttba 1111: reserved 15 14 13 12 11 10 9 8 bit symbol read/write r after reset 0 0 0 0 0 0 0 0 function always reads "0." 23 22 21 20 19 18 17 16 bit symbol read/write r after reset 0 0 0 0 0 0 0 0 function always reads "0." 31 30 29 28 27 26 25 24 bit symbol read/write r after reset 0 0 0 0 0 0 0 0 function always reads "0." (note 5) to clear interrupt request of the above 15 factors that are assigned to clear stop/sleep/idle modes, c for kwup, use kwupst d for int0 to intb, inttba and intrtc use the eicrcg register in the above cg block and then use the intclr register in the intc block (two locations). e for clearing any other interrupt requests, only intclr register is to be cleared. tmp19a64c1d tmp19a64(rev1.1) 6-37 nmiflg 7 6 5 4 3 2 1 0 (0xffff_ee24) bit symbol nmi wdt wber read/write r after reset 0 0 0 0 0 0 0 0 function always reads "0." nmi factor 1: nmi generated by nmi pin input nmi factor 1: nmi generated by wdt interrupt nmi factor 1: nmi generated by write bus error 15 14 13 12 11 10 9 8 bit symbol read/write r after reset 0 0 0 0 0 0 0 0 function always reads "0." 23 22 21 20 19 18 17 16 bit symbol read/write r after reset 0 0 0 0 0 0 0 0 function always reads "0." 31 30 29 28 27 26 25 24 bit symbol read/write r after reset 0 0 0 0 0 0 0 0 function always reads "0." ? nmi, wdt and wber are cleared to "0" when they are read. tmp19a64c1d tmp19a64 (rev1.1) 7-1 7. input/output ports 7.1 port 0 (p00 through p07) the port 0 is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register p0cr. a reset allows all bits of p0cr to be cleared to "0" and the port 0 to be put in input mode. besides the general-purpose input/output function, the port 0 performs other functions: d0 through d7 function as a data bus and ad0 through ad7 function as an address data bus. when external memory is accessed, the port 0 automatically functions as either a data bus or an address data bus, and all bits of p0cr are cleared to "0." if the busmd pin is set to "l" level during a reset, the port 0 is put in separate bus mode (d0 to d7). if it is set to "h" level during a reset, the port 0 is put in multiplexed mode (ad0 to ad7). during external access external read when output externally 0 y direction control (in units of bits) ? p0cr output latch p0 p0 read port 0 p00 through p07 (d0 through d7) (ad0 through ad7) output buffer syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-2 port 0 register 7 6 5 4 3 2 1 0 p0 bit symbol p07 p06 p05 p04 p03 p02 p01 p00 (0xffff_f000) read/write r/w after reset input mode (output latch register is cleared to "0.") port 0 control register 7 6 5 4 3 2 1 0 p0cr bit symbol p07c p06c p05c p04c p03c p02c p01c p00c (0xffff_f002) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output (when an external area is accessed, d7-0 or ad7- 0 is used and this register is cleared to "0.") fig. 7.1.2 port 0 registers tmp19a64c1d tmp19a64 (rev1.1) 7-3 7.2 port 1 (p10 through p17) the port 1 is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register p1cr and the function register p1fc. a reset allows all bits of the output latch p1, p1cr and p1fc to be cleared to "0" and the port 1 to be put in input mode. besides the general-purpose input/output function, the po rt 1 performs other functions: d8 through d15 function as a data bus, ad8 through ad15 function as an addre ss data bus, and a8 through a15 function as an address bus. to access external memory, the port 1 must be designa ted as an address bus or address data bus by making proper p1cr and p1fc settings. if the busmd pin is set to "l" level during a reset, the port 1 is put in separate bus mode (d8 to d15). if it is set to "h" level during a reset, the port 1 is put in multiplexed mode (ad8 to ad15 or a8 to a15). external read when output external direction control (in units of bits) p1cr output latch p1 p1 read port 1 p10 through p17 (d8 through d15) (ad8 through ad15/a8 through a15) selector s y 1 0 selector a d8 through d15/ a 8 through a15 1 0 selector 1 0 ebif function control (in units of bits) p1fc internal data bus syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-4 port 1 register 7 6 5 4 3 2 1 0 p1 bit symbol p17 p16 p15 p14 p13 p12 p11 p10 (0xffff_f001) read/write r/w after reset input mode (output latch register is cleared to "0.") port 1 control register 7 6 5 4 3 2 1 0 p1cr bit symbol p17c p16c p15c p14c p13c p12c p11c p10c (0xffff_f004) read/write r/w after reset 0 0 0 0 0 0 0 0 function << see p1fc >> port 1 function register 7 6 5 4 3 2 1 0 p1fc bit symbol p17f p16f p15f p14f p13f p12f p11f p10f (0xffff_f005) read/write r/w after reset 0 0 0 0 0 0 0 0 function p1fc/p1cr = 00: input, 01: output, 10: d15 through 8 or ad15 through 8, 11: a15 through 8 function corresponding bit of p1fc corresponding bit of p1cr port to be used por1 input setting 0 0 port1 por1 output setting 0 1 port1 data bus (d15 through d8) input/output setting 1 0 separate bus mode (busmd="0") address bus (a15 through a8) output setting 1 1 port1 address data bus (ad15 through ad8) input/output setting 1 0 multiplexed bus mode (busmd="1") address bus (a15 through a8) output setting 1 1 port1 fig. 7.2.2 port 1 registers tmp19a64c1d tmp19a64 (rev1.1) 7-5 7.3 port 2 (p20 through p27) the port 2 is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register p2cr and the function register p2fc. a reset allows all bits of the output latch p2 to be set to "1," all bits of p2cr and p2fc to be cleared to "0," and the port 2 to be put in input mode. besides the general-purpose input/output port function, the port 2 performs another function: a0 through a7 function as one address bus and a16 through a23 function as the other address bus. to access external memory, registers p2cr and p2fc must be provisioned to allow the port 2 to function as an address bus. if the busmd pin is set to "l" level during a reset, the port 2 is put in separate mode (a16 to a23). if it is set to "h" level during a reset, the port 2 is put in multiplexed mode (a0 through a7 or a16 through a23). during external access p2fc function control (in units of bits) ? direction control (in units of bits) p2cr output latch p2 p2 read port 2 p20 through p27 (a16 through a23) (a0 through a7/a16 through a23) reset y 0 1 selector selector a 16 through a23/ selector 1 0 a 0 through a7 s 1 0 internal data bus syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-6 port 2 register 7 6 5 4 3 2 1 0 p2 bit symbol p27 p26 p25 p24 p23 p22 p21 p20 (0xffff_f012) read/write r/w after reset input mode (output latch register is cleared to "1.") port 2 control register 7 6 5 4 3 2 1 0 p2cr bit symbol p27c p26c p25c p24c p23c p22c p21c p20c (0xffff_f014) read/write r/w after reset 0 0 0 0 0 0 0 0 function < tmp19a64c1d tmp19a64 (rev1.1) 7-7 7.4 port 3 (p30 through p37) the port 3 is a general-purpose, 8-bit input/output port (p30 and p31 are used exclusively for output). for this port, inputs and outputs can be specified in units of bits by using the control register p3cr and the function register p3fc. a reset allows the output latches p30 and 31 to be set to "1." if the busmd pin is at the "l" level when a reset is performed, p37 goes into separate bus mode, and the output latch is set to "1." if the busmd pin is at the "h" level when a reset is performed, p37 goes into multiplexed bus mode, and the output latch is cleared to "0." bit 2 through bit 6 of p3cr (bits 0 and 1 are unused) are cleared to "0." bit 7 of p3cr is cleared to "0" in separate bus mode and set to "1" in multiplexed bus mode. all bits of p3fc are cleared to "0," p30 and p31 generate "h," and p32 through p36 go into the input mode with a pull-up resistor after reset is cleared. if the port 3 goes into separate bus mode, p37 is put into input mode. if the port 3 goes into multiplexed bus mode, p37 is put into output mode. besides the general-purpose input/output port function, the port 3 inputs and outputs cpu control/status signals. if the p30 pin is set to rd signal output mode ( tmp19a64c1d tmp19a64 (rev1.1) 7-8 function control (in units of bits) p3fc direction control (in units of bits) p3cr internal data bus selector s 0 1 output latch p3 selector 1 0 hwr selector 0 1 during external access stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-9 fig. 7.4.3 port 3 (p33) output buffer direction control (in units of bits) p3cr stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-10 direction control (in units of bits) p3cr stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-11 direction control (in units of bits) p3cr output latch p3 function control (in units of bits) p3fc selector 1 0 busak selector 1 0 selector 1 0 internal data bus stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-12 during external access fig. 7.4.6 port 3 (p36) direction control (in units of bits) p3cr internal data bus stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-13 stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-14 port 3 register 7 6 5 4 3 2 1 0 p3 bit symbol p37 p36 p35 p34 p33 p32 p31 p30 (0xffff_f018) read/write r/w output mode after reset to be determined according to the bus mode (*1) 1 1 1 1 1 1 1 port 3 control register 7 6 5 4 3 2 1 0 p3cr bit symbol p37c p36c p35c p34c p33c p32c ? ? (0xffff_f01a) read/write r/w r after reset 0 0 0 0 0 0 0 function to be determined according to the bus mode (*1) 0: input 1: output output port 3 function register 7 6 5 4 3 2 1 0 p3fc bit symbol p37f p36f p35f p34f p33f p32f p31f p30f (0xffff_f01b) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 0: port 0: port 0: port 0: port/ wait 0: port 0: port 0: port 1: ale 1: r/w 1: busak 1: busrq 1: port/ rdy 1: hwr 1: wr 1: rd function corresponding bit of p3fc corresponding bit of p3cr port to be used rd output setting 1(*2) ? p30 wr output setting 1(*2) ? p31 hwr output setting 1 1 p32 wait input setting rdy input setting 0 1 0 0 p33 busrq input setting 1 0 p34 busak output setting 1 1 p35 r/w output setting 1 1 p36 ale output setting (busmd = "1") 1(*1) 1 p37 (*1) in separate bus mode (busmd="0"), ale is not output. the port 3 functions as an input/output port based on the bit setting of the control register p3cr tmp19a64c1d tmp19a64 (rev1.1) 7-15 7.5 port 4 (p40 through p47) the port 4 is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register p4cr and the function register p4fc. a reset allows all bits of the output latch p4 to be set to "1" and all bits of p4cr to be reset to "0." bits of p40fc through p46fc are reset to "0." p40 through p45 goes into the input mode with a pull-up resistor, and p46 and p47 are put into input mode. besides the general-purpose input/output port function, the ports 40 through 45 outputs chip select signals ( cs0 through cs5 ), and the port 46 functions as a scout output pin for outputting external clocks. during external access fig. 7.5.1 port 4 (p40 to p45) cs0, cs1 cs2, cs3 cs4, cs5 p40 (cs0) p41 (cs1) p42 (cs2) p43 (cs3) p44 (cs4) p45 (cs5) direction control (in units of bits) p4cr internal data bus output latch p4 function control (in units of bits) p4fc programmable pull-up p4 read selector 1 0 selector 1 0 selector 1 0 stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-16 0 1 p46 (scout) reset stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-17 direction control (in units of bits) p4cr p4 read p47 selector 1 0 output latch p4 reset internal data bus stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-18 port 4 register 7 6 5 4 3 2 1 0 p4 bit symbol p47 p46 p45 p44 p43 p42 p41 p40 (0xffff_f01e) read/write r/w after reset input mode 1 1 1 (pull-up) 1 (pull-up) 1 (pull-up) 1 (pull-up) 1 (pull-up) 1 (pull-up) port 4 control register 7 6 5 4 3 2 1 0 p4cr bit symbol p47c p46c p45c p44c p43c p42c p41c p40c (0xffff_f020) read/write r/w after reset 0 0 0 0 0 0 0 0 0: input 1: output port 4 function register 7 6 5 4 3 2 1 0 p4fc bit symbol p47f p46f p45f p44f p43f p42f p41f p40f (0xffff_f021) read/write r r/w after reset 0 0 0 0 0 0 0 0 function 0: port 0: port 1: scout 0: port 1: cs5 0: port 1: cs4 0: port 1: cs3 0: port 1: cs2 0: port 1: cs1 0: port 1: cs0 function corresponding bit of p4fc corresponding bit of p4cr port to be used cs0 output setting 1 1 p40 cs1 output setting 1 1 p41 cs2 output setting 1 1 p42 cs3 output setting 1 1 p43 cs4 output setting 1 1 p44 cs5 output setting 1 1 p45 scout output setting 1 1 p46 fig. 7.5.4 port 4 registers tmp19a64c1d tmp19a64 (rev1.1) 7-19 7.6 port 5 (p50 through p57) the port 5 is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register p5cr and the function register p5fc. a reset allows all bits of the output latch p5 to be set to "1," all bits of p5cr and p5fc to be cleared to "0," and the port 5 to be put in input mode. the port 5 also functions as an address bus (a0 thro ugh a7). to access external memory, p5cr and p5fc must be provisioned to allow the port 5 to function as an address bus. this address bus function can be used only in separate bus mode. (to put the port 5 in separate bus mode, the busmd pin must be set to "l" level during a reset.) direction control (in units of bits) p5cr port 5 (p50 to p57/a0 through a7) a0 through a7 internal data bus selector 1 0 output latch p5 function control (in units of bits) p5fc selector p5 read 1 0 stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-20 port 5 register 7 6 5 4 3 2 1 0 p5 bit symbol p57 p56 p55 p54 p53 p52 p51 p50 (0xffff_f028) read/write r/w after reset input mode (output latch register is set to "1.") port 5 control register 7 6 5 4 3 2 1 0 p5cr bit symbol p57c p56c p55c p54c p53c p52c p51c p50c (0xffff_f02c) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port 5 function register 7 6 5 4 3 2 1 0 p5fc bit symbol p57f p56f p55f p54f p53f p52f p51f p50f (0xffff_f02d) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 1: a7 0: port 1: a6 0: port 1: a5 0: port 1: a4 0: port 1: a3 0: port 1: a2 0: port 1: a1 0: port 1: a0 function corresponding bit of p5fc corresponding bit of p5cr port to be used por5 input setting 0 0 port5 por5 output setting 0 1 port5 address bus (a7 to a0) output setting (*1) 1 1 port5 (*1) the same address bus (a7 through a0) output setting is used in both the separate bus mode and multiplexed bus mode (busmd="0," "1"). fig. 7.6.2 port 5 registers tmp19a64c1d tmp19a64 (rev1.1) 7-21 7.7 port 6 (p60 through p67) the port 6 is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register p6cr and the function register p6fc. a reset allows all bits of the output latch p6 to be set to "1," all bits of p6cr and p6fc to be cleared to "0," and the port 6 to be put in input mode. besides the input/output port function, the port 6 performs other functions: p60 and p63 output sio data, p61 and p64 input sio data, p62 and p65 input and output sio clk or input cts, p61 and p64 input external interrupts, and p66 and p67 output a 16-bit timer. the port 6 also functions as an address bus (a8 thr ough a15). to access external memory, p6cr and p6fc must be provisioned to allow the port 6 to function as an address bus. the address bus function can be used only in separate bus mode. (to put the port 6 in separate bus mode, the busmd pin must be set to "l" level during a reset.) direction control (in units of bits) p6cr port 6 (p60 to p67/a8 through a15 ) a 8 through a15 selector 1 0 output latch p6 function control (in units of bits) p6fc selector 1 selector 0 1 internal data bus during external access stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-22 port 6 register 7 6 5 4 3 2 1 0 p6 bit symbol p67 p66 p65 p64 p63 p62 p61 p60 (0xffff_f029) read/write r/w after reset input mode (output latch register is set to "1.") port 6 control register 7 6 5 4 3 2 1 0 p6cr bit symbol p67c p66c p65c p64c p63c p62c p61c p60c (0xffff_f02e) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port 6 function register 7 6 5 4 3 2 1 0 p6fc bit symbol p67f p66f p65f p64f p63f p62f p61f p60f (0xffff_f02f) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 1: a15 0: port 1: a14 0: port 1: a13 0: port 1: a12 0: port 1: a11 0: port 1: a10 0: port 1: a9 0: port 1: a8 function corresponding bit of p6f corresponding bit of p6cr port to be used por6 input setting 0 0 port6 por6 output setting 0 1 port6 address bus (a15 to a8) output setting (*1) 1 1 port6 (*1) the same address bus (a15 through a8) output setting is used in both the separate bus mode and multiplexed bus mode (busmd="0," "1"). fig. 7.7.2 port 6 registers tmp19a64c1d tmp19a64 (rev1.1) 7-23 7.8 port 7 (p70 through p77), port 8 (p 80 through p87) and port 9 (p90 through p97) the ports 7, 8 and 9 are 8-bit ports and used exclusively for input. they are also used as analog input ports for the a/d converter. inputs can be specified by using the func tion register pnfc. a reset allows all bits of pnfc to be cleared to "0" and the ports 7, 8 and 9 to be put in input mode. fig. 7.8.1 port 7 to 9 (p70 through p 77, p80 through p87 and p90 through p97) ad read port 7 (p7 through p9) read port 7 to 9 p70 through p97 (an0 through an23) internal data bus a/d converter reset function control (p7fc, p8fc, p9fc) (in units of bits) reset tmp19a64c1d tmp19a64 (rev1.1) 7-24 port 7 register 7 6 5 4 3 2 1 0 p7 bit symbol p77 p76 p75 p74 p73 p72 p71 p70 (0xffff_f040) read/write r after reset input mode port 7 function register 7 6 5 4 3 2 1 0 p7fc bit symbol p77f p76f p75f p74f p73f p72f p71f p70f (0xffff_f048) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 1: an7 0: port 1: an6 0: port 1: an5 0: port 1: an4 0: port 1: an3 0: port 1: an2 0: port 1: an1 0: port 1: an0 port 8 register 7 6 5 4 3 2 1 0 p8 bit symbol p87 p86 p85 p84 p83 p82 p81 p80 (0xffff_f041) read/write r after reset input mode port 8 function register 7 6 5 4 3 2 1 0 p8fc bit symbol p87f p86f p85f p84f p83f p82f p81f p80f (0xffff_f049) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 1: an15 0: port 1: an14 0: port 1: an13 0: port 1: an12 0: port 1: an11 0: port 1: an10 0: port 1: an9 0: port 1: an8 port 9 register 7 6 5 4 3 2 1 0 p9 bit symbol p97 p96 p95 p94 p93 p92 p91 p90 (0xffff_f042) read/write r after reset input mode port 9 function register 7 6 5 4 3 2 1 0 p9fc bit symbol p97f p96f p95f p94f p93f p92f p91f p90f (0xffff_f04a) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 1: an23 0: port 1: an22 0: port 1: an21 0: port 1: an20 0: port 1: an19 0: port 1: an18 0: port 1: an17 0: port 1: an16 function corresponding bits of p7fc, p8fc and p9fc input setting for the ports 7, 8 and 9 0 input setting for an23 through an0 1 fig. 7.8.2 registers of the ports 7, 8 and 9 tmp19a64c1d tmp19a64 (rev1.1) 7-25 7.9 port a (pa0 through pa7) the port a is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register pacr. a reset allows pacr to be reset to "0" and the port a to function as an input port. besides the input/output port function, the port a performs other functions: pa2, pa5, pa6 and pa7 output a 16-bit timer, and pa0, pa1, pa3 and pa4 input a 16-bit timer and external interrupts. these functions are enabled by setting corresponding bits of pafc to "1." a reset allows pacr and pafc to be cleared to "0" and the port a to be put in input mode. fig. 7.9.1 port a (pa0, pa1, pa3, pa4) function control (pafc) (in units of bits) direction control (pacr) (in units of bits) output latch (pa) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-26 fig. 7.9.2 port a (pa2, pa5, pa6, pa7) function control (pafc) (in units of bits) direction control (pacr) (in units of bits) output latch (pa) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-27 port a register 7 6 5 4 3 2 1 0 pa bit symbol pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 (0xffff_f043) read/write r/w after reset input mode (output latch register is set to "1.") port a control register 7 6 5 4 3 2 1 0 pacr bit symbol pa7c pa6c pa5c pa4c pa3c pa2c pa1c pa0c (0xffff_f047) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port a function register 7 6 5 4 3 2 1 0 pafc bit symbol pa7f pa6f pa5f pa4f pa3f pa2f pa1f pa0f (0xffff_f04b) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 1: tb3out 0: port 1: tb2out 0: port 1: tb1out 0: port 1: tb1in1 / int8 0: port 1: tb1in0 / int7 0: port 1: tb0out 0: port 1: tb0in1 / int6 0: port 1: tb0in0 / int5 function corresponding bit of pafc corresponding bit of pacr port to be used tb0in0 input setting 1 0 int5 input setting 1(*1) 0 pa0 tb0in1 input setting 1 0 int6 input setting 1(*1) 0 pa1 tb0out output setting 1 1 pa2 tb1in0 input setting 1 0 int7 input setting 1(*1) 0 pa3 tb1in1 input setting 1 0 int8 input setting 1(*1) 0 pa4 tb1out output setting 1 1 pa5 tb2out output setting 1 1 pa6 tb3out output setting 1 1 pa7 (*1) this bit setting is used only if an interrupt must be generated to clear the stop status and if syscr tmp19a64c1d tmp19a64 (rev1.1) 7-28 7.10 port b (pb0 through pb7) port b is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register pbcr. a reset allows p bcr to be reset to "0" and the port b to function as an input port. besides the input/output port function, the port b performs other functions: pb0 through pb5 output a 16-bit timer, and pb6 and pb7 input a 16-bit timer. these functions are enabled by setting corresponding bits of pbfc to "1." a rest allows pbcr and pbfc to be clea red to "0" and the port b to function as an input port. fig. 7.10.1 port b (pb0 through pb5) function control (pbfc) (in units of bits) direction control (pbcr) (in units of bits) output latch (pb) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-29 fig. 7.10.2 port b (pb6, pb7) function control (pbfc) (in units of bits) direction control (pbcr) (in units of bits) output latch (pb) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-30 port b register 7 6 5 4 3 2 1 0 pb bit symbol pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 (0xffff_f050) read/write r/w after reset input mode (output latch register is set to "1.") port b control register 7 6 5 4 3 2 1 0 pbcr bit symbol pb7c pb6c pb5c pb4c pb3c pb2c pb1c pb0c (0xffff_f054) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port b function register 7 6 5 4 3 2 1 0 pbfc bit symbol pb7f pb6f pb5f pb4f pb3f pb2f pb1f pb0f (0xffff_f058) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 1: tbain1 0: port 1: tbain0 0: port 1: tb9out 0: port 1: tb8out 0: port 1: tb7out 0: port 1: tb6out 0: port 1: tb5out 0: port 1: tb4out function corresponding bit of pbfc corresponding bit of pbcr port to be used tb4out output setting 1 1 pb0 tb5out output setting 1 1 pb1 tb6out output setting 1 1 pb2 tb7out output setting 1 1 pb3 tb8out output setting 1 1 pb4 tb9out output setting 1 1 pb5 tbain0 input setting 1 0 pb6 tbain1 input setting 1 0 pb7 fig. 7.10.3 port b registers tmp19a64c1d tmp19a64 (rev1.1) 7-31 7.11 port c (pc0 to pc7) port c is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register pccr. a reset allows p ccr to be reset to "0" and the port c to function as an input port. besides the input/output port function, the port c performs other functions: pc0, pc3 and pc6 output sio data, pc1, pc4 and pc7 input sio data, and pc2 and pc5 input and output sio clk or input cts. these functions are enabled by setting corresponding bits of pcfc to "1." a reset allows pccr and pcfc to be cleared to "0" and the port c to function as an input port. fig. 7.11.1 port c (pc0, pc3, pc6) function control (pcfc) (in units of bits) direction control (pccr) (in units of bits) output latch (pc) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-32 fig. 7.11.2 port c (pc1, pc4, pc7) function control (pcfc) (in units of bits) direction control (pccr) (in units of bits) output latch (pc) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-33 fig. 7.11.3 port c (pc2, pc5) function control (pcfc) (in units of bits) direction control (pccr) (in units of bits) output latch (pc) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-34 port c register 7 6 5 4 3 2 1 0 pc bit symbol pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (0xffff_f051) read/write r/w after reset input mode (output latch register is set to "1.") port c control register 7 6 5 4 3 2 1 0 pccr bit symbol pc7c pc6c pc5c pc4c pc3c pc2c pc1c pc0c (0xffff_f055) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port c function register 7 6 5 4 3 2 1 0 pcfc bit symbol pc7f pc6f pc5f pc4f pc3f pc2f pc1f pc0f (0xffff_f059) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 1: rxd2 0: port 1: txd2 0: port 1: sclk1 / cts1 0: port 1: rxd1 0: port 1: txd1 0: port 1: sclk0 / cts0 0: port 1: rxd0 0: port 1: txd0 port c open drain control register 7 6 5 4 3 2 1 0 pcode bit symbol pc6ode pc5ode pc3ode pc2ode pc0ode (0xffff_f05d) read/write r r/w r r/w r r/w after reset 0 0 0 0 0 0 0 0 function 0: cmos 0: cmos 1: open drain 0: cmos 1: open drain 0: cmos 0: cmos 1: open drain 0: cmos 1: open drain 0: cmos 0: cmos 1: open drain function corresponding bit of pcfc corresponding bit of pccr port to be used txd0 output setting 1 1 pc0 rxd0 input setting 1 0 pc1 sclk0 output setting sclk0 input setting cts0 input setting 1 1 1 1 0 0 pc2 txd1 output setting 1 1 pc3 rxd1 output setting 1 1 pc4 sclk1 output setting sclk1 input setting cts1 input setting 1 1 1 1 0 0 pc5 txd2 output setting 1 0 pc6 rxd2 input setting 1 0 pc7 fig. 7.11.4 port c registers tmp19a64c1d tmp19a64 (rev1.1) 7-35 7.12 port d (pd0 to pd7) the port d is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register pdcr. a rese t allows pdcr to be reset to "0" and the port d to function as an input port. besides the input/output port function, the port d performs other functions: pd0, pd3 and pd6 input and output sio clk or input cts, pd1 and pd4 output sio data, pd2 and pd5 input sio data, and pd7 inputs external interrupts. these functions are enabled by setting corresponding bits of pdfc to "1." a reset allows pdcr and pdfc to be cleared to "0" and the port d to function as an input port. fig. 7.12.1 port d (pd0, pd3, pd6) sclk2 output sclk3 output sclk4 output open drain setting possible pdode tmp19a64c1d tmp19a64 (rev1.1) 7-36 fig. 7.12.2 port d (pd1, pd4) txd3 output txd4 output pd1 (txd3) pd4 (txd4) open drain setting possible pdode tmp19a64c1d tmp19a64 (rev1.1) 7-37 fig. 7.12.3 port d (pd2, pd5) pd2 (rxd3) pd5 (rxd4) rxd3 input rxd4 input function control (pdfc) (in units of bits) direction control (pdcr) (in units of bits) output latch (pd) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-38 fig. 7.12.4 port d (pd7) int9 function control (pdfc) (in units of bits) direction control (pdcr) (in units of bits) output latch (pd) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-39 port d register 7 6 5 4 3 2 1 0 pd bit symbol pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 (0xffff_f052) read/write r/w after reset input mode (output latch register is set to "1.") port d control register 7 6 5 4 3 2 1 0 pdcr bit symbol pd7c pd6c pd5c pd4c pd3c pd2c pd1c pd0c (0xffff_f056) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port d function register 7 6 5 4 3 2 1 0 pdfc bit symbol pd7f pd6f pd5f pd4f pd3f pd2f pd1f pd0f (0xffff_f05a) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 1: int9 0: port 1: sclk4 / cts4 0: port 1: rxd4 0: port 1: txd4 0: port 1: sclk3 / cts3 0: port 1: rxd3 0: port 1: txd3 0: port 1: sclk2 / cts2 port d open drain control register 7 6 5 4 3 2 1 0 pdode bit symbol pd6ode pd4ode pd3ode pd1ode pd0ode (0xffff_f05e) read/write r r/w r r/w r r/w after reset 0 0 0 0 0 0 0 0 function 0: cmos 0: cmos 1: open drain 0: cmos 0: cmos 1: open drain 0: cmos 1: open drain 0: cmos 0: cmos 1: open drain 0: cmos 1: open drain function corresponding bit of pdfc corresponding bit of pdcr port to be used sclk2 output setting sclk2 input setting cts2 input setting 1 1 1 1 0 0 pd0 txd3 output setting 1 1 pd1 rxd3 input setting 1 0 pc2 sclk3 output setting sclk3 input setting cts3 input setting 1 1 1 1 0 0 pd3 txd4 output setting 1 1 pd4 rxd4 output setting 1 1 pd5 sclk4 output setting sclk4 input setting cts4 input setting 1 1 1 1 0 0 pd6 int9 input setting 1(*1) 0 pd7 (*1) this bit setting is used only if an interrupt must be generated to clear the stop status and if syscr tmp19a64c1d tmp19a64 (rev1.1) 7-40 7.13 port e (pe0 through pe7) the port e is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register pecr. a reset allows pecr to be reset to "0" and the port e to function as an input port. besides the input/output port function, th e port e performs other functions: pe0 outputs sio data, pe1 inputs sio data, pe2 inputs and outputs sio clk or inputs cts, and pe6 and pe7 input external interrupts. these functions are enable d by setting corresponding bits of pe fc to "1." a reset allows pecr and pefc to be cleared to "0" and the port e to function as an input port. fig. 7.13.1 port e (pe0) txd5 output pe0 (txd5) open drain setting possible peode tmp19a64c1d tmp19a64 (rev1.1) 7-41 fig. 7.13.2 port e (pe1) pe1 (rxd5) rxd5 input function control (pefc) (in units of bits) direction control (pecr) (in units of bits) output latch (pe) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-42 fig. 7.13.3 port e (pe2) sclk5 output open drain setting possible peode tmp19a64c1d tmp19a64 (rev1.1) 7-43 fig. 7.13.4 port e (pe3, pe4, pe5) pe3 pe4 pe5 direction control (pecr) (in units of bits) output latch (pe) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-44 fig. 7.13.5 port e (pe6, pe7) function control (pefc) (in units of bits) direction control (pecr) (in units of bits) output latch (pe) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-45 port e register 7 6 5 4 3 2 1 0 pe bit symbol pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 (0xffff_f053) read/write r/w after reset input mode (output latch register is set to "1.") port e control register 7 6 5 4 3 2 1 0 pecr bit symbol pe7c pe6c pe5c pe4c pe3c pe2c pe1c pe0c (0xffff_f057) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port e function register 7 6 5 4 3 2 1 0 pefc bit symbol pe7f pe6f pe5f pe4f pe3f pe2f pe1f pe0f (0xffff_f05b) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 1: intb 0: port 1: inta 0: port 0: port 0: port 0: port 1: sclk5 / cts5 0: port 1: rxd5 0: port 1: txd5 port e open drain control register 7 6 5 4 3 2 1 0 peode bit symbol pe2ode pe0ode (0xffff_f05f) read/write r r/w r r/w after reset 0 0 0 0 0 0 0 0 function 0: cmos 0: cmos 0: cmos 0: cm os 0: cmos 0: cmos 1: open drain 0: cmos 0: cmos 1: open drain function corresponding bit of pefc corresponding bit of pecr port to be used txd5 output setting 1 1 pe0 rxd3 output setting 1 0 pe1 sclk5 output setting sclk5 input setting cts5 input setting 1 1 1 1 0 0 pe2 inta input setting 1(*1) 0 pe6 intb input setting 1(*1) 0 pe7 (*1) this bit setting is used only if an interrupt must be generated to clear the stop status and if syscr tmp19a64c1d tmp19a64 (rev1.1) 7-46 7.14 port f (pf0 through pf7) the port f is a general-purpose, 8-bit input/output port. fo r this port, inputs and outputs can be specified in units of bits by using the control register pfcr. a reset allows pfcr to be reset to "0" and the port f to function as an input port. besides the input/output port function, the port f performs other functions: pf0 through pf2 input and output sb1, pe3 and pe5 input the dma request signal, pf4 and pf6 output the dma acknowledge signal, and pf7 inputs external clock sources of a 32-bit time base timer. these functions are enabled by setting corresponding bits of pffc to "1." a reset allows pfcr and pffc to be cleared to "0" and the port f to function as an input port. the dmac function is shared by pf3 through pf6 and pj0 through pj3. to give pf0 through pf3 the precedence in using the dmac function, the corresponding bit of pffc must be set to "1." fig. 7.14.1 port f (pf0) function control (pffc) (in units of bits) direction control (pfcr) (in units of bits) output latch (pf) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-47 fig. 7.14.2 port f (pf1) function control (pffc) (in units of bits) direction control (pfcr) (in units of bits) output latch (pf) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-48 fig. 7.14.3 port f (pf2) function control (pffc) (in units of bits) direction control (pfcr) (in units of bits) output latch (pf) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-49 fig. 7.14.4 port f (pf3, pf5) function control (pffc) (in units of bits) direction control (pfcr) (in units of bits) output latch (pf) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-50 fig. 7.14.5 port f (pf4, pf6) pf4 (dack2) pf6 (dack3) dack2 output dack3 output function control (pffc) (in units of bits) direction control (pfcr) (in units of bits) output latch (pf) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-51 fig. 7.14.6 port f (pf7) pf7 (tbtin) tbtin function control (pffc) (in units of bits) direction control (pfcr) (in units of bits) output latch (pf) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-52 port f register 7 6 5 4 3 2 1 0 pf bit symbol pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 (0xffff_f060) read/write r/w after reset input mode (output latch register is set to "1.") port f control register 7 6 5 4 3 2 1 0 pfcr bit symbol pf7c pf6c pf5c pf4c pf3c pf2c pf1c pf0c (0xffff_f064) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port f function register 7 6 5 4 3 2 1 0 pffc bit symbol pf7f pf6f pf5f pf4f pf3f pf2f pf1f pf0f (0xffff_f068) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 1: tbtin 0: port 1: dack3 0: port 1: dreq3 0: port 1: dack2 0: port 1: dreq2 0: port 1: sck 0: port 1: si / scl 0: port 1: so / sda port f open drain control register 7 6 5 4 3 2 1 0 pfode bit symbol pf1ode pf0ode (0xffff_f06c) read/write r r/w after reset 0 0 0 0 0 0 0 0 function 0: cmos 0: cmos 0: cmos 0: cmos 0: cmos 0: cmos 0: cmos 1: open drain 0: cmos 1: open drain function corresponding bit of pffc corresponding bit of pfcr port to be used so output setting sda output setting sda input setting 1 1 1 1 1 0 pf0 si input setting scl output setting scl input setting 1 1 1 0 1 0 pf1 sclk5 output setting sclk5 input setting 1 1 1 0 pf2 dreq2 input setting 1 0 pf3 dack2 output setting 1 1 pf4 dreq3 input setting 1 0 pf5 dack3 output setting 1 1 pf6 tbtin input setting 1 0 pf7 (note) the dmac function is shared by the port f and the port j. if both ports are set to use the dmac function, the port f is given priority in using the dmac function. fig. 7.14.7 port f registers tmp19a64c1d tmp19a64 (rev1.1) 7-53 7.15 port g (pg0 through pg7) the port g is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register pgcr. a rese t allows pgcr to be reset to "0" and the port g to function as an input port. besides the input/output port function, the port g performs other functions: pg0 through pg3 input a 32-bit input capture trigger, and pg4 through pg7 output a 32-bit output compare. these functions are enabled by setting corresponding bits of pgfc to "1." a reset allows pgcr and pgfc to be cleared to "0" and the port g to function as an input port. fig. 7.15.1 port g (pg0 through pg3) pg0 (tc0in) pg1 (tc1in) pg2 (tc2in) pg3 (tc3in) tc0in, tc1in tc2in, tc3in function control (pgfc) (in units of bits) direction control (pgcr) (in units of bits) output latch (pg) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-54 fig. 7.15.2 port g (pg4 through pg7) timer f/f out pg4 (tcout0) pg5 (tcout1) pg6 (tcout2) pg7 (tcout3) tcout0 tcout1 tcout2 tcout3 function control (pgfc) (in units of bits) direction control (pgcr) (in units of bits) output latch (pg) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-55 port g register 7 6 5 4 3 2 1 0 pg bit symbol pg7 pg6 pg5 pg4 pg3 pg2 pg1 pg0 (0xffff_f061) read/write r/w after reset input mode (output latch register is set to "1.") port g control register 7 6 5 4 3 2 1 0 pgcr bit symbol pg7c pg6c pg5c pg4c pg3c pg2c pg1c pg0c (0xffff_f065) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port g function register 7 6 5 4 3 2 1 0 pgfc bit symbol pg7f pg6f pg5f pg4f pg3f pg2f pg1f pg0f (0xffff_f069) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 1: tcout3 0: port 1: tcout2 0: port 1: tcout1 0: port 1: tcout0 0: port 1: tc3in 0: port 1: tc2in 0: port 1: tc1in 0: port 1: tc0in function corresponding bit of pgfc corresponding bit of pgcr port to be used tc0in input setting 1 0 pg0 tc1in input setting 1 0 pg1 tc2in input setting 1 0 pg2 tc3in input setting 1 0 pg3 tcout0 output setting 1 1 pg4 tcout1 output setting 1 1 pg5 tcout2 output setting 1 1 pg6 tcout3 output setting 1 1 pg7 fig. 7.15.2 port g registers tmp19a64c1d tmp19a64 (rev1.1) 7-56 7.16 port h (ph0 through ph7) the port h is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register phcr. a rese t allows phcr to be reset to "0" and the port h to function as an input port. besides the input/output port function, the port h performs another function: ph0 through ph5 output the 32-bit output compare. this f unction is enabled by setting the corresponding bit of phfc to "1." a reset allows phcr and phfc to be cleare d to "0" and the port h to function as an input port. fig. 7.16.1 port h (ph0 through ph5) ph0 (tcout4) ph1 (tcout5) ph2 (tcout6) ph3 (tcout7) ph4 (tcout8) ph5 (tcout9) tcout4, tcout5 tcout6, tcout7 tcout8, tcout9 timer f/f out function control (phfc) (in units of bits) direction control (phcr) (in units of bits) output latch (ph) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-57 fig. 7.16.2 port h (ph6, ph7) ph6 ph7 direction control (phcr) (in units of bits) output latch (ph) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-58 port h register 7 6 5 4 3 2 1 0 ph bit symbol ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 (0xffff_f062) read/write r/w after reset input mode (output latch register is set to "1.") port h control register 7 6 5 4 3 2 1 0 phcr bit symbol ph7c ph6c ph5c ph4c ph3c ph2c ph1c ph0c (0xffff_f066) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port h function register 7 6 5 4 3 2 1 0 phfc bit symbol ph5f ph 4f ph3f ph2f ph1f ph0f (0xffff_f06a) read/write r r/w after reset 0 0 0 0 0 0 0 0 function 0: port 0: port 0: port 1: tcout9 0: port 1: tcout8 0: port 1: tcout7 0: port 1: tcout6 0: port 1: tcout5 0: port 1: tcout4 function corresponding bit of phfc corresponding bit of phcr port to be used tcout4 output setting 1 1 ph0 tcout5 output setting 1 1 ph1 tcout6 output setting 1 1 ph2 tcout7 output setting 1 1 ph3 tcout8 output setting 1 1 ph4 tcout9 output setting 1 1 ph5 fig. 7.16.3 port h registers tmp19a64c1d tmp19a64 (rev1.1) 7-59 7.17 port i (pi0 through pi4) the port i is a general-purpose, 5-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register picr. a reset allows picr to be reset to "0" and the port i to function as an input port. besides the input/output port function, the port i performs another function: pi0 through pi4 input external interrupts. this function is enabled by setting th e corresponding bit of pifc to "1." a reset allows picr and pifc to be cleared to "0" and the port i to function as an input port. the external interrupt function is shared by pi0 through pi4 and po0 through po4. to give po0 through po4 the precedence in using the external interrupt function, the corresponding bit of pofc must be set to the interrupt function. fig. 7.17.1 port i (pi0 through pi4) pi0 (int0) pi1 (int1) pi2 (int2) pi3 (int3) pi4 (int4) function control (pifc) (in units of bits) direction control (picr) (in units of bits) output latch (pi) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-60 port i register 7 6 5 4 3 2 1 0 pi bit symbol pi4 pi3 pi2 pi1 pi0 (0xffff_f063) read/write r r/w after reset input mode (output latch register is set to "1.") port i control register 7 6 5 4 3 2 1 0 picr bit symbol pi4c pi3c pi2c pi1c pi0c (0xffff_f063) read/write r r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port i function register 7 6 5 4 3 2 1 0 pifc bit symbol pi4f pi3f pi2f pi1f pi0f (0xffff_f06b) read/write r r/w after reset 0 0 0 0 0 0 0 0 function 0: port 1: int4 0: port 1: int3 0: port 1: int2 0: port 1: int1 0: port 1: int0 function corresponding bit of pifc corresponding bit of picr port to be used int0 input setting 1 (*1) 0 pi0 int1 input setting 1 (*1) 0 pi1 int2 input setting 1 (*1) 0 pi2 int3 input setting 1 (*1) 0 pi3 int4 input setting 1 (*1) 0 pi4 (note*1) this bit setting is used only if an interrupt must be generated to clear the stop status and if syscr tmp19a64c1d tmp19a64 (rev1.1) 7-61 7.18 port j (pj0 through pj3) the port j is a general-purpose, 4-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register pjcr. a reset allows pjcr to be reset to "0" and the port j to function as an input port. besides the input/output port function, the port j performs other functions: pj0 and pj2 input the dma request signal, and pj1 and pj3 output the dma acknowledge signal. these functions are enabled by setting the corresponding bits of pjfc to "1." a reset allows pjcr and pjfc to be cleared to "0" and the port j to function as an input port. the dmac function is shared by pj0 through pj3 and pf3 through pf6. to give pf0 through pf3 the precedence in using the dmac function over pj0 through pj3, the corresponding bit of pffc must be set to "1." fig. 7.18.1 port j (pj0, pj2) function control (pjfc) (in units of bits) direction control (pjcr) (in units of bits) output latch (pj) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-62 fig. 7.18.2 port j (pj1, pj3) function control (pjfc) (in units of bits) direction control (pjcr) (in units of bits) output latch (pj) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-63 port j register 7 6 5 4 3 2 1 0 pj bit symbol pj3 pj2 pj1 pj0 (0xffff_f070) read/write r r/w after reset input mode (output latch register is set to "1.") port j control register 7 6 5 4 3 2 1 0 pjcr bit symbol pj3c pj2c pj1c pj0c (0xffff_f074) read/write r r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port j function register 7 6 5 4 3 2 1 0 pjfc bit symbol pj3f pj2f pj1f pj0f (0xffff_f078) read/write r r/w after reset 0 0 0 0 0 0 0 0 function 0: port 1: dack3 0: port 1: dreq3 0: port 1: dack2 0: port 1: dreq2 function corresponding bit of pjfc corresponding bit of pjcr port to be used dreq2 input setting 1 0 pj0 dack2 output setting 1 1 pj1 dreq3 input setting 1 0 pj2 dack3 output setting 1 1 pj3 (note) the dmac function is shared by the port f and the port j. if both ports are set to use the dmac function, the port f is given priority in using the dmac function. fig. 7.18.3 port j registers tmp19a64c1d tmp19a64 (rev1.1) 7-64 7.19 port k (pk0 through pk7) the port k is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register pkcr. a rese t allows pkcr to be reset to "0" and the port k to function as an input port. besides the input/output port function, pk0 through pk7 perform the key input function. this function is enabled by setting the corresponding bit of pkfc to "1." a reset allows pkcr and pkfc to be cleared to "0" and the port k to function as an input port. the ports k0 through k7 have a pull-up resistor function. this function is enabled only if kuppup tmp19a64c1d tmp19a64 (rev1.1) 7-65 port k register 7 6 5 4 3 2 1 0 pk bit symbol pk7 pk6 pk5 pk4 pk3 pk2 pk1 pk0 (0xffff_f071) read/write r/w after reset input mode (output latch register is set to "1.") port k control register 7 6 5 4 3 2 1 0 pkcr bit symbol pk7c pk6c pk5c pk4c pk3c pk2c pk1c pk0c (0xffff_f075) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port k function register 7 6 5 4 3 2 1 0 pkfc bit symbol pk7f pk6f pk5f pk4f pk3f pk2f pk1f pk0f (0xffff_f079) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 1: key7 0: port 1: key6 0: port 1: key5 0: port 1: key4 0: port 1: key3 0: port 1: key2 0: port 1: key1 0: port 1: key0 function corresponding bit of pkfc corresponding bit of pkcr port to be used key0 input setting 1 0 pk0 key1 input setting 1 0 pk1 key2 input setting 1 0 pk2 key3 input setting 1 0 pk3 key4 input setting 1 0 pk4 key5 input setting 1 0 pk5 key6 input setting 1 0 pk6 key7 input setting 1 0 pk7 (*1) this bit setting is used only if an interrupt must be generated to clear the stop status and if syscr tmp19a64c1d tmp19a64 (rev1.1) 7-66 7.20 port l (pl0 through pl7) the port l is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register plcr. a reset allows plcr to be reset to "0" and the port l to function as an input port. fig. 7.20.1 port l (pl0 through pl7) pl0 pl1 pl2 pl3 pl4 pl5 pl6 pl7 direction control (plcr) (in units of bits) output latch (pl) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-67 port l register 7 6 5 4 3 2 1 0 pl bit symbol pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 (0xffff_f0c0) read/write r/w after reset input mode (output latch register is set to "1.") port l control register 7 6 5 4 3 2 1 0 plcr bit symbol pl7c pl6c pl5c pl4c pl3c pl2c pl1c pl0c (0xffff_f0c4) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output ?` l ???? (``?_) 7 6 5 4 3 2 1 0 plfc bit symbol pl7f pl6f pl5f pl4f pl3f pl2f pl1f pl0f (0xffff_f0c8 ) read/write r/w ?? 0 0 0 0 0 0 0 0 C 0: port 1: db7 0: port 1: db6 0: port 1: db5 0: port 1: db4 0: port 1: db3 0: port 1: db2 0: port 1: db1 0: port 1: db0 7.20.2 ?` l vS? tmp19a64c1d tmp19a64 (rev1.1) 7-68 7.21 port m (pm0 through pm7) the port m is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register pmcr. a rese t allows pmcr to be reset to "0" and the port m to function as an input port. fig. 7.21.1 port m (pm0 through pm7) pm0 pm1 pm2 pm3 pm4 pm5 pm6 pm7 direction control (pmcr) (in units of bits) output latch (pm) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-69 port m register 7 6 5 4 3 2 1 0 pm bit symbol pm7 pm6 pm5 pm4 pm3 pm2 pm1 pm0 (0xffff_f0c1) read/write r/w after reset input mode (output latch register is set to "1.") port m control register 7 6 5 4 3 2 1 0 pmcr bit symbol pm7c pm6c pm5c pm4c pm3c pm2c pm1c pm0c (0xffff_f0c5) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output ?` m ???? (``?_) 7 6 5 4 3 2 1 0 pmfc bit symbol pm5f pm4f pm3f pm2f pm1f pm0f (0xffff_f0c9 ) read/write r r/w ?? 0 0 0 0 0 0 0 0 C 0:port 0:port 0: port 1: db13 0: port 1: db12 0: port 1: db11 0: port 1: db10 0: port 1: db9 0: port 1: db8 7.21.2 ?` m vS? tmp19a64c1d tmp19a64 (rev1.1) 7-70 7.22 port n (pn0 through pn7) the port n is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register pncr. a rese t allows pncr to be reset to "0" and the port n to function as an input port. fig. 7.22.1 port n (pn0 through pn7) pn0 pn1 pn2 pn3 pn4 pn5 pn6 pn7 direction control (pncr) (in units of bits) output latch (pn) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-71 port n register 7 6 5 4 3 2 1 0 pn bit symbol pn7 pn6 pn5 pn4 pn3 pn2 pn1 pn0 (0xffff_f0c2) read/write r/w after reset input mode (output latch register is set to "1.") port n control register 7 6 5 4 3 2 1 0 pncr bit symbol pn7c pn6c pn5c pn4c pn3c pn2c pn1c pn0c (0xffff_f0c6) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output ?` n ???? (``?_) 7 6 5 4 3 2 1 0 pnfc bit symbol pn3f pn2f pn1f pn0f (0xffff_f0c a) read/write r r/w ?? 0 0 0 0 0 0 0 0 C 0:port 0:port 0:port 0:port 0: port 1:status1 0: port 1:status0 0: port 1: fclk 0: port 1: busy 7.22.2 ?` n vS? tmp19a64c1d tmp19a64 (rev1.1) 7-72 7.23 port o (po0 through po7) the port o is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register pocr. besides the input/output port function, the port o performs another function: po0 through po4 input external in terrupts. this function is enabled by setting the corresponding bit of pofc to "1." a rest allows pocr and pofc to be clear ed to "0" and the port o to function as an input port. the external interr upt function is shared by po0 through po4 and pi0 through pi4. to give po0 through po4 the precedence in using the external interrupt function, the corresponding bit of pofc must be set to the interrupt function. fig. 7.23.1 port o (po0 through po4) po0 (int0) po1 (int1) po2 (int2) po3 (int3) po4 (int4) function control (pofc) (in units of bits) direction control (pocr) (in units of bits) output latch (po) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-73 fig. 7.23.2 port o (po5) txd6 output po5 (txd6) open drain setting possible poode tmp19a64c1d tmp19a64 (rev1.1) 7-74 fig. 7.23.3 port o (po6) po6 (rxd6) rxd6 input function control (pofc) (in units of bits) direction control (pocr) (in units of bits) output latch (po) stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-75 fig. 7.23.4 port o (po7) sclk6 output open drain setting possible poode tmp19a64c1d tmp19a64 (rev1.1) 7-76 port o register 7 6 5 4 3 2 1 0 po bit symbol po7 po6 po5 po4 po3 po2 po1 po0 (0xffff_f0c3) read/write r/w after reset input mode (output latch register is set to "1.") port o control register 7 6 5 4 3 2 1 0 pocr bit symbol po7c po6c po5c po4c po3c po2c po1c po0c (0xffff_f0c7) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port o function register 7 6 5 4 3 2 1 0 pofc bit symbol po4f po3f po2f po1f po0f (0xffff_f0cb) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 1: sclk6 cts6 0: port 1: rxd6 0: port 1: txd6 0: port 1: int4 0: port 1: int3 0: port 1: int2 0: port 1: int1 0: port 1: int0 port o open drain control register 7 6 5 4 3 2 1 0 poode bit symbol po7ode po5ode (0xffff_f0cf) read/write r/w r r/w r r r r r after reset 0 0 0 0 0 0 0 0 function 0: cmos 1: open drain 0: cmos 0: cmos 1: open drain 0: cmos 0: cmos 0: cmos 0: cmos 0: cmos function corresponding bit of pofc corresponding bit of pocr port to be used int0 input setting 1(*1) 0 po0 int1 input setting 1(*1) 0 po1 int2 input setting 1(*1) 0 po2 int3 input setting 1(*1) 0 po3 int4 input setting 1(*1) 0 po4 txd6 output setting 1 1 po5 rtd6 input setting 1 0 po6 sclk6 output setting sclk6 input setting cts6 input setting 1 1 1 1 0 0 po7 (*1) this bit setting is used only if an interrupt must be generated to clear the stop status and if syscr tmp19a64c1d tmp19a64 (rev1.1) 7-77 7.24 port p (pp0 through pp7) the port p is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register ppcr. besides the input/output port function, the port p performs another function: pp0 through pp7 output the signal for ejtag. this function is enabled by a combination of the ejtag debug level and the corresponding bit of ppfc. a reset allows ppcr and ppfc to be cleared to "0" and the port p to function as an input port. if dsu-ice is used for debugging, the port p outputs the signal for ejtag. therefore, it is recommended not to use the port p as an input/output port. fig. 7.24.1 port p (pp0 through pp7) (note) the above system diagram does not show the debug function. direction control (ppcr) (in units of bits) output buffer internal data bus selector s y 1 0 output latch (pp) function control (ppfc) (in units of bits) tpd reset selector pp read s y 1 0 stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-78 port p register 7 6 5 4 3 2 1 0 pp bit symbol pp7 pp6 pp5 pp4 pp3 pp2 pp1 pp0 (0xffff_f0d0) read/write r/w after reset input mode (output latch register is set to "1.") port p control register 7 6 5 4 3 2 1 0 ppcr bit symbol pp7c pp6c pp5c pp4c pp3c pp2c pp1c pp0c (0xffff_f0d4) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output port p function register 7 6 5 4 3 2 1 0 ppfc bit symbol pp7f pp6f pp5f pp4f pp3f pp2f pp1f pp0f (0xffff_f0d8) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: port 1: tpd7/tpc7 0: port 1: tpd6/tpc6 0: port 1: tpd5/tpc5 0: port 1: tpd4/tpc4 0: port 1: tpd3/tpc3 0: port 1: tpd2/tpc2 0: port 1: tpd1/tpc1 0: port 1: tpd0/tpc0 fig. 7.24.2 port p registers note) if the port p or the port q is used to generate the output signal for ejtag, a necessary port p or q setting must be made using a tool. the ppfc register setting must be made in units of bites. level 2 level 0 level 1 ppfc=#ff ppfc #ff level 3 port p port port tpd port tpd port q port tpc port tpd tpc fig. 7.24.3 ports p and q function relative to debug levels note) for information on debug levels and other details, refer to the dsu probe handling manual. tmp19a64c1d tmp19a64 (rev1.1) 7-79 7.25 port q (pq0 through pq7) the port q is a general-purpose, 8-bit input/output port. for this port, inputs and outputs can be specified in units of bits by using the control register pqcr. besides the input/output port function, pq0 through pq7 output the signal for ejtag. this function is enabled by a combination of a debug level and the corresponding bit of ppfc. a reset allows pqcr and ppfc to be cleared to "0" and the port q to function as an input port. if dsu-ice is used for debugging, the port q outputs the signal for ejtag. therefore, it is recommended not to use the port q as an input/output port. fig. 7.25.1 port q (pq0 through pq7) (note) the above system diagram does not show the debug function. direction control (pqcr) (in units of bits) output buffer internal data bus selector s y 1 0 output latch (pq) function control (ppfc) (in units of bits) tpd/tpc reset selector pp read s y 1 0 stop mode syscr2 tmp19a64c1d tmp19a64 (rev1.1) 7-80 port q register 7 6 5 4 3 2 1 0 pq bit symbol pq7 pq6 pq5 pq4 pq3 pq2 pq1 pq0 (0xffff_f0d1) read/write r/w after reset input mode (output latch register is set to "1.") port q control register 7 6 5 4 3 2 1 0 pqcr bit symbol pq7c pq6c pq5c pq4c pq3c pq2c pq1c pq0c (0xffff_f0d5) read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: input 1: output fig. 7.25.2 port q registers tmp19a64c1d tmp19a64 (rev1.1) 8-1 8. external bus interface the tmp19a64 has a built-in external bu s interface function to connect to ex ternal memory, i/os, etc. this interface consists of an external bus interface circu it (ebif), a chip selector (cs) and a wait controller. the chip selector and wait controller designate mapping addresses in a 6-block address space and also control wait states and data bus widths (8- or 16-bit) in these and other external address spaces. the external bus interface circ uit (ebif) controls the timing of external buses based on the chip selector and wait controller settings. the ebif also controls the dynami c bus sizing and the bus arbi tration with the external bus master. z external bus mode selectable address, data separator bus mode and multiplex mode z wait function this function can be enabled for each block. ? a wait of up to 7 clocks can be automatically inserted. ? a wait can be inserted via the wait / rdy pin. z data bus width either an 8- or 16-bit width can be set for each block. z recovery cycle (read/write) if an external bus cycle is in progress, a dummy cycl e of up to 2 clocks can be inserted and this dummy cycle can be specified for each block. z recovery cycle (chip selector) when an external bus is selected, a dummy cycle of up to 1 clock can be inserted and this dummy cycle can be specified for each block. z bus arbitration function tmp19a64c1d tmp19a64 (rev1.1) 8-2 8.1 address and data pins (1) address and data pin settings the tmp19a64 can be set to either separate bus or multiplexed bus mode. setting the busmd pin to the "l" level at a reset activates the separate bus mode , and setting the pin to the "h" level activates the multiplexed bus mode. port pins 0, 1, 2, 5 and 6, which are to be connected to external devices (memory), are used as address buses, data buses and address/data buses. table 8.1.1 shows these. table 8.1.1 bus mode, address and data pins separate multiplex busmd="l" busmd="h" port 0 (p00 to p07) d0-d7 ad0-ad7 port 1 (p10 to p17) d8-d15 ad8-ad15/a8-a15 port 2 (p20 to p27) a16-a23 a0-a7/a16-a23 port 5 (p50 to p57) a0-a7 general-purpose port port 6 (p60 to p67) a8-a15 general-purpose port port 37 (p37) general-purpose port ale each port is put into input mode af ter a reset. to access an external device, set the address and data bus functions by using the port control register (pncr) and the port function register (pnfc). in the multiplex mode, the four types of functions can be selected, as shown in table 8.1.2, by setting the port registers (pncr and pnfc). table 8.1.2 address and data pins in the multiplex mode c d e f number of address buses max.24 (-16 mb) ma x.24 (-16 mb) max.16 (-64 kb) max.8 (-256 b) number of data buses 8 16 8 16 number of address/data multiplexed buses 8 16 0 0 port 0 ad0 to ad7 ad0 to ad7 ad0 to ad7 ad0 to ad7 port 1 a8 to a15 ad8 to ad15 a8 to a15 ad8 to ad15 port function port 2 a16 to a23 a16 to a23 a0 to a7 a0 to a7 timing diagram (note 1) even in cases of e and f , address outputs are available as the data bus pins are also used for address buses. (note 2) ports 0 to 2 are put into input modes after a reset, and they do not serve as address or data bus pins. (note 3) any of c to f can be selected by setting the p1cr, p1fc, p2cr and p2fc registers. (note 1) a7-0 a23-8 a23-8 a7-0 d7-0 ad7-0 ale rd a15 -0 a23-16 a23-16 d15 -0 ad15-0 ale rd a7-0 a15-0 a15-0 d7-0 ad7-0 ale rd a15 -0 a7-0 d15 -0 ad15-0 ale rd (note1) tmp19a64c1d tmp19a64 (rev1.1) 8-3 (2) address hold when an internal area is accessed when an internal area is being accessed, the address bus maintains the address ou tput of the previously accessed external area and doesn't change it. also, the data bus is in a state of high impedance. 8.2 data format internal registers and external bus interfaces of the tmp19a64 are configured as described below. (1) big-endian mode c word access ? 16-bit bus width internal registers external buses ? 8-bit bus width internal registers external buses d half word access ? 16-bit bus width internal registers external buses address d31 aa x0 bb x1 aabb ccdd cc x2 d00 dd x3 a1=0 a1=1 ms ls address d31 aa x0 bb x1 cc x2 d00 dd x3 aa bb cc dd x0 x1 x2 x3 address d31 aabb aa x0 d00 bb x1 ms ls address d31 ccdd cc x2 d00 dd x3 ms ls tmp19a64c1d tmp19a64 (rev1.1) 8-4 ? 8-bit bus width internal registers external buses internal registers external buses e byte access ? 16-bit bus width internal registers external buses address d31 aa x0 d00 bb x1 a b x0 x1 address d31 cc x2 d00 dd x3 cd x2 x3 address d31 aa d00 aa x0 address d31 bb d00 bb x1 address d31 cc d00 cc x2 address d31 dd d00 dd x3 ms ls ms ls ms ls ms ls tmp19a64c1d tmp19a64 (rev1.1) 8-5 ? 8-bit bus width internal registers external buses address d31 aa d00 aa x0 address d31 bb d00 bb x1 address d31 cc d00 cc x2 address d31 dd d00 dd x3 tmp19a64c1d tmp19a64 (rev1.1) 8-6 (2) little-endian mode c word access ? 16-bit bus width internal registers external buses ? 8-bit bus width internal registers external buses d half word access ? 16-bit bus width internal registers external buses address d31 dd x3 cc x2 aabb ccdd bb x1 d00 aa x0 a1=0 a1=1 ls ms address d31 dd x3 cc x2 bb x1 d00 aa x0 aa bb cc dd x0 x1 x2 x3 address d31 aabb bb x1 d00 aa x0 ls ms address d31 ccdd dd x3 d00 cc x2 lsb msb tmp19a64c1d tmp19a64 (rev1.1) 8-7 ? 8-bit bus width internal registers external buses internal registers external buses e byte access ? 16-bit bus width internal registers external buses address d31 bb x1 d00 aa x0 aa bb x0 x1 address d31 dd x3 d00 cc x2 cc dd x2 x3 address d31 aa d00 aa x0 address d31 bb d00 bb x1 address d31 cc d00 cc x2 address d31 dd d00 dd x3 lsb msb lsb msb lsb msb lsb msb tmp19a64c1d tmp19a64 (rev1.1) 8-8 ? 8-bit bus width internal registers external buses address d31 aa d00 aa x0 address d31 bb d00 bb x1 address d31 cc d00 cc x2 address d31 dd d00 dd x3 tmp19a64c1d tmp19a64 (rev1.1) 8-9 8.3 external bus operations (separate bus mode) this section describes various bus timing values. the timing diagram shown below assumes that the address buses are a23 through a0 and that the data buses are d15 through d0. (1) basic bus operation the external bus cycle of the tmp19a 64 basically consists of three clock pulses and a wait can be inserted as mentioned later. the basic clock of an external bu s cycle is the same as the internal system clock. fig. 8.3.1 shows read bus timing and fig. 8.3.2 shows write bus timing. if internal areas are accessed, address buses remain unchanged as shown in these figu res. additionally, data buses are in a state of high impedance and control signals such as rd and wr do not become active. fig. 8.3.1 read operation timing diagram fig. 8.3.2 write operation timing diagram no output of wr external access internal access d [15:0] output high ? z data tsys rd no output of rd a [23:0] address hold csn external access internal access d [15:0] output high ? z data tsys a [23:0] address hold csn wr tmp19a64c1d tmp19a64 (rev1.1) 8-10 (2) wait timing a wait cycle can be inserted for each block by usin g the chip selector (cs) and wait controller. the following three types of wait can be inserted: c a wait of up to 7 clocks can be automatically inserted. d a wait can be inserted via the wait pin (2+2n, 3+2n, 4+2n, 5+2n, 6+2n, 7+2n). note: 2n is the number of external waits that can be inserted. e a wait can be inserted via the rdy pin (2+2n, 3+2n, 4+2n, 5+2n, 6+2n, 7+2n). note: 2n is the number of external waits that can be inserted. the setting of the number of waits to be automatically inserted and the setting of the external wait input can be made using the chip selector and wait controller registers, bmncs tmp19a64c1d tmp19a64 (rev1.1) 8-11 fig. 8.3.5 shows the read operation timing when 0 wait, waits automatically inserted, and waits automatically inserted + external waits are inserted in the separate bus mode. fig. 8.3.5 read operation timing diagram tsys fsys 0 wait 2 waits automatically inserted 2 waits automatically inserted 2 waits automatically inserted + 2n (n=1) 2n_wait 3 waits automatically inserted + 2n (n=1) 2n_wait 2 waits automatically inserted + 2n (n=2) 2n_wait a [23:0] d[15:0] /rd /rd /wait a [23:0] d[15:0] /rd a [23:0] d[15:0] a [23:0] d[15:0] /rd /wait /wait /wait a [23:0] d[15:0] /rd /wait z --- external wait sampling point external wait sampling points take place before a cycle of waits automatically inserted is finished and before a 2n_wait cycle is finished as shown above. the same a pp lies to combinations of other numbers of waits. 2 waits automatically inserted 3 waits automatically inserted 2 waits automatically inserted tmp19a64c1d tmp19a64 (rev1.1) 8-12 fig. 8.3.6 shows the write operation timing when 0 wait, waits automatically inserted, and waits automatically inserted + external waits are inserted in the separate bus mode. tsys fs y s 0 wait 2 waits automatically inserted 2 waits automatically inserted 2 waits automatically inserted + 2n (n=1) 2 waits automatically inserted 2n_wait 3 waits automatically inserted + 2n (n=1) 3 waits automatically inserted 2n_wait 2 waits automatically inserted + 2n (n=2) 2 waits automatically inserted 2n_wait /wait a [23:0] d [ 15:0 ] a[ 23:0 ] d[15:0] /wr /wait /wait /wr a[ 23:0 ] d[15:0] /wr /wr /wait a[ 23:0 ] d[15:0] a [23:0] d[15:0] /wr /wait z --- external wait sampling point external wait sampling points take place before a cycle of waits automatically inserted is finished and before a 2n_wait cycle is finished as shown above. the same applies to combinations of other numbers of waits. fig. 8.3.6 write operation timing diagram tmp19a64c1d tmp19a64 (rev1.1) 8-13 by setting the bit 3 tmp19a64c1d tmp19a64 (rev1.1) 8-14 (3) time that it takes before ale is asserted when the external bu s of the tmp19a64 is used as a multiplexed bus, the ale width (assert time) can be specified by using the system control register syscr3 tmp19a64c1d tmp19a64 (rev1.1) 8-15 (4) recovery time if access to external areas occurs consecutively, a dummy cycle can be inserted for recovery time. a dummy cycle can be inserted in both a read and a write cycle. the dummy cycle insertion setting can be made in the chip selector and wait controller regi sters, bmncs tmp19a64c1d tmp19a64 (rev1.1) 8-16 (5) chip selector recovery time if access to external areas occurs consecutively, a dummy cycle can be inserted for recovery time. the dummy cycle insertion setting ca n be made in the chip selector and wait controller registers, bmncs tmp19a64c1d tmp19a64 (rev1.1) 8-17 8.4 external bus operations (multiplexed bus mode) this section describes various bus timing values. th e timing diagram shown below assumes that the address buses are a23 through a16 and that the address/data buses are ad15 through ad0. (1) basic bus operation the external bus cycle of the tmp19a 64 basically consists of three clock pulses and a wait can be inserted as mentioned later. the basic clock of an external bu s cycle is the same as the internal system clock. fig. 8.4.1 shows read bus timing and fig. 8.4.2 shows write bus timing. if internal areas are accessed, address buses remain unchanged and the ale does not output latch pulse as shown in these figures. additionally, address/data buses are in a state of high impedance and control signals such as rd and wr do not become active. a [23:16] a d [15:0] a le rd external access internal access output hi ? z no output of ale no output of rd higher-order address hold adr data tsys csn fig. 8.4.1 read operation timing diagram a [23:16] a d [15:0] a le wr external area output hi ? z no output of ale no output of wr higher-order address adr data tsys csn internal area fig. 8.4.2 write operation timing diagram tmp19a64c1d tmp19a64 (rev1.1) 8-18 (2) wait timing a wait cycle can be inserted for each block by usin g the chip selector (cs) and wait controller. the following three types of wait can be inserted: c a wait of up to 7 clocks can be automatically inserted. d a wait can be inserted via the wait pin (2+2n, 3+2n, 4+2n, 5+2n, 6+2n, 7+2n). note: 2n is the number of extern al waits that can be inserted. e a wait can be inserted via the rdy pin (2+2n, 3+2n, 4+2n, 5+2n, 6+2n, 7+2n). note: 2n is the number of extern al waits that can be inserted. the setting of the number of waits to be automatically in serted and the setting of the external wait input can be made using the chip selector and wait controller registers, bmncs tmp19a64c1d tmp19a64 (rev1.1) 8-19 fig. 8.4.3 shows the read operation timing when 0 wait, waits automatically inserted, and waits automatically inserted + external waits are inserted in the multiplexed bus mode. fig. 8.4.3 read operation timing diagram tsys fsys 0 wait 2 waits automatically inserted 2 waits automatically inserted 2 waits automatically inserted + 2n (n=1) 2n_wait 3 waits automatically inserted + 2n (n=1) 2n_wait 2 waits automatically inserted + 2n (n=2) 2n_wait a d[15:0] a le /wait /wait /rd a [23:16] /rd a [23:16] a d[15:0] /rd /wait a d[15:0] a le a [23:16] a d[15:0] a le /wait /wait /rd a le a [23:16] a [23:16] a d[15:0] a le /rd data z --- external wait sampling point external wait sampling points take place before a cycle of waits automatically inserted is finished and before a 2n_wait cycle is finished as shown above. the same applies to combinations of other numbers of waits. higher-order address lower-order address higher-order address lower-order address data higher-order address lower-order address data higher-order address lower-order address data data higher-order address lower-order address 2 waits automatically inserted 3 waits automatically inserted 2 waits automatically inserted tmp19a64c1d tmp19a64 (rev1.1) 8-20 fig. 8.4.4 shows the write operation timing when 0 wait, waits automatically inserted, and waits automatically inserted + external waits are inserted in the multiplexed bus mode. fig. 8.4.4 write operation timing diagram tsys fsys 0 wait 2 waits automatically inserted 2 waits automatically inserted 2 waits automatically inserted + 2n (n=1 ) 2 waits automatically inserted 2n_wait 3 waits automatically inserted + 2n (n=1) 2 waits automatically inserted 2n_wait 2 waits automatically inserted + 2n (n=2) 2 waits automatically inserted 2n_wait /wait /wr a le a le a [23:16] /wr a [23:16] a d[15:0] a [23:16] a d[15:0] /wr /wait a d[15:0] a le /wait /wait /wr a [23:16] a d[15:0] a le a [23:16] a d[15:0] a le /wr /wait higher-order address lowe r -order address data lowe r -order address data z --- external wait sampling point external wait sampling points take place before a cycle of waits automatically inserted is finished and before a 2n_wait cycle is finished as shown above. the same applies to combinations of other numbers of waits. lower-order address data lower-order address data higher-order address higher-order address higher-order address higher-order address lowe r -order address data tmp19a64c1d tmp19a64 (rev1.1) 8-21 (3) time that it takes before ale is asserted either 1 clock or 2 clocks can be se lected as the time that it takes before ale is asserted. the setting bit is located in the system clock control register. the default is 2 clocks. this assert setting cannot be established for each block in an external area and the same setting is commonly used in an external address space. a le (alesel = 0) a d [15:0] (alesel = 1) a d [15:0] 1 clock tsys 2 clocks fig. 8.4.12 time that it takes before ale is asserted fig. 8.4.13 shows the timing when the ale is 1 clock or 2 clocks. fig. 8.4.13 read operation timing diagram (when the ale is 1 clock or 2 clocks) when the ale is 1 clock or 2 clocks tsys fsys a [23:16] a d[15:0] a le /rd data higher-order address lower-order address data higher-order address tmp19a64c1d tmp19a64 (rev1.1) 8-22 (4) read and write recovery time if access to external areas occurs consecutively, a dummy cycle can be inserted for recovery time. a dummy cycle can be inserted in both a read and a write cycle. the dummy cycle insertion setting can be made in the chip selector and wait controller regi sters, bmncs tmp19a64c1d tmp19a64 (rev1.1) 8-23 (5) chip selector recovery time if access to external areas occurs consecutively, a dummy cycle can be inserted for recovery time. the dummy cycle insertion setting ca n be made in the chip selector and wait controller registers, bmncs tmp19a64c1d tmp19a64 (rev1.1) 8-24 8.5 bus arbitration the tmp19a64 can be connected to an external bus mast er. the arbitration of bus control authority with the external bus master is execut ed by using the two signals, busrq and busak . the external bus master can acquire control authority for tmp19a64 external buses on ly, and cannot acquire cont rol authority for internal buses. (1) accessible range of external bus master the external bus master can acquir e control authority for tmp19a64 external buses only, and cannot acquire control authority for internal buses (g-bus). therefore, the external bus master cannot access the internal memories or the internal i/o. the arbitration of bus control authority for exte rnal buses is executed by the external bus in terface circuit (ebif), and th is is independent of the cp u and the internal dmac. even when the external bus master holds the external bus control au thority, the cpu and the internal dmac can access the internal rom, ram and registers. on the other hand, if the cpu or the internal dmac tries to access an external memory when the ex ternal bus master holds the external bus control authority, the cpu or the internal dmac has to wait until the external bus ma ster releases the bus. for this reason, if the busrq remains active, the tmp19a64 can lock. (2) acquisition of bus control authority the external bus master requests the tmp19a64 for bus control author ity by asserting the busrq signal. the tmp19a64 samples the busrq signal at the break of external bus cycles on the internal buses (g- bus) and determines whether or not to give the bus control authority to the external bus master. when it gives the bus control authority to th e external bus master, it asserts the busak signal. at the same time, it makes address buses, data buses and bus control signals ( rd and wr ) in a state of high impedance. (the internal pull-up is enabled for the w r/ , hwr and csx .) depending on the relationship between the size of data to be loaded or stored and the external memory bus width, two or more bus cycles can occur in response to a single data transfer (bus si zing). in this case, the end of the last bus cycle is th e break of external bus cycles. if access to external areas occurs consecutively on th e tmp19a64, a dummy cycle can be inserted. again, requests for buses are accepted at the break of external bus cycles on the internal buses (g-bus). during a dummy cycle, the next external bus cy cle is already started on the internal buses. therefore, even if the busrq signal is asserted during a dummy cycle, the bus is not released until the next external bus cycle is completed. keep asserting the busrq signal until the bus cont rol authority is released. fig. 8.5.1 shows the timing of acquiring bus control authority by the external bus master. tmp19a64c1d tmp19a64 (rev1.1) 8-25 c d e internal address external address tmp19a64 external access tmp19a64 external access external bus master cycle tmp19a64 external access tsys busrq busak tmp19a64 external access c busrq is at the "h" level. d the tmp19a64 recognizes that the busrq is at the "l" level, and releas es the bus at the end of the bus cycle. e when the bus is completed, the tmp19a64 asserts busak . the external bus master recognizes that the busak is at the "l" level, and acquires the bus control authority to start bus operations. fig. 8.5.1 bus control authority acquisition timing (3) release of bus control authority the external bus master releases the bus control authority when it becomes unnecessary. if the external bus master no longer needs the bus control authority that it has held, it deasserts the busrq signal and returns the bus cont rol authority to the tmp19a64. fig. 8.5.2 shows the timing of releasing unnecessary bus control authority. internal address external address tmp19a64 external access tmp19a64 external access tmp19a64 external access external bus master cycle tmp19a64 external access c d e tsys busrq busak c the external bus master has the bus control authority. d the external bus master deasserts the busrq , as it no longer requires the bus contro l authority. e the tmp19a64 rec ognizes that the busrq is at the "h" level, and deasserts the busak . fig. 8.5.2 timing of releasing bus control authority tmp19a64c1d tmp19a64 (rev1.1) 9-1 9. the chip selector and wait controller the tmp19a64 can be connected to external devices (i/o devices, rom and sram). 6-block address spaces (cs0 through cs 5) can be established in the tmp19a64 and three parameters can be specified for each 4-block address and other address spaces : data bus width, the number of waits and the number of dummy cycles. cs0 through cs5 (also used as p40 through p45) are the outp ut pins corresponding to spaces cs0 through cs5. these pins generate chip selector signals (f or rom and sram) to each sp ace when the cpu designates an address in which spaces cs0 through cs5 are selected. for chip selector signals to be generated, however, the port 4 controller register (p4cr) and the port 4 fu nction register (p4fc) must be set appropriately. the specification of the spaces cs0 through cs5 is to be performed with a combination of base addresses (ban, n = 0 to 5) and mask addresses (man, n = 0 to 5) using the base and mask address setting registers (bma0 through bma5). meanwhile, master enable, data bus width, the number of waits and the number of dummy cycles for each address space are specified in the chip selector and wait controller registers (b01cs, b23cs, b45cs and bexcs). a bus wait request pin ( wait ) is provided as an input pin to co ntrol the status of these settings. 9.1 specifying address spaces spaces cs0 through cs5 are specified using the base and mask addre ss setting registers (bma0 through bma5). in each bus cycle, a comparison is made to see if each address on the bu s is located in th e space cs0 through cs5. if the result of a comparison is a match, it is considered that the designated cs space has been accessed and chip selector signals are output from pins cs0 through cs5 and the operations specified by the chip selector and wait controller registers (b01cs, b23cs an d b45cs) are executed. (refer to "9.2 the chip selector and wait controller.") 9.1.1 base and mask address setting registers figures 9.1.1 to 3 show base and mask address setting re gisters. for base addresses (ba0 through ba5), a start address in the space cs0 through cs5 is specified. in each bus cycle, the chip selector and wait controller compare values in their registers with addresses and th ose addresses with address bits masked by the mask address (ma0 through ma5) are not comp ared. the size of an address space is determined by the mask address setting. (1) base addresses base address ban specifies the higher-ord er 16 bits (a31 through a16) of the start address. the lower-order 16 bits (a15 to a0) of the start address are always set to "0." therefore, the start address begins with 0x0000_0000h and increases in 64 kilobyte units. fig. 9.1.4 shows the relationship between the start address and the ban value. (2) mask addresses mask address (man) specifies which address bit valu e is to be compared. th e address on the bus that corresponds to the bit for which "0" is written on th e address mask man is to be in cluded in address comparison to determine if the address is in th e area of the cs0 to cs5 spaces. th e bit for which "1" is written is not included in address comparison. tmp19a64c1d tmp19a64 (rev1.1) 9-2 cs0 to cs5 spaces have different address bi ts that can be masked by ma0 to ma5. cs0 space and cs1 space: a29 through a14 cs2 space and cs3 space: a30 through a15 cs4 space and cs5 space: a30 through a15 (note) address settings must be made using physical addresses. tmp19a64c1d tmp19a64 (rev1.1) 9-3 base and mask address setting registers bma0 (0xffff_ e400h)-bma5 (0 xffff_e414h) 31 30 29 28 27 26 25 24 bma0 bit symbol ba0 (0xffff_e400h) read/write r/w after reset 0 0 0 0 0 0 0 0 function a31 to a24 to be set as a start address 23 22 21 20 19 18 17 16 bit symbol ba0 read/write r/w after reset 0 0 0 0 0 0 0 0 function a23 to a16 to be set as a start address 15 14 13 12 11 10 9 8 bit symbol ma0 read/write r/w after reset 0 0 0 0 0 0 1 1 function make sure that you write "0." 7 6 5 4 3 2 1 0 bit symbol ma0 read/write r/w after reset 1 1 1 1 1 1 1 1 function cs0 space size setting 0: address for comparison 31 30 29 28 27 26 25 24 bma1 bit symbol ba1 (0xffff_e404h) read/write r/w after reset 0 0 0 0 0 0 0 0 function a31 to a24 to be set as a start address 23 22 21 20 19 18 17 16 bit symbol ba1 read/write r/w after reset 0 0 0 0 0 0 0 0 function a23 to a16 to be set as a start address 15 14 13 12 11 10 9 8 bit symbol ma1 read/write r/w after reset 0 0 0 0 0 0 1 1 function make sure that you write "0." 7 6 5 4 3 2 1 0 bit symbol ma1 read/write r/w after reset 1 1 1 1 1 1 1 1 function cs1 space size setting 0: address for comparison (note) make sure that you write "0" for bits 10 through 15 for bma0 and bma1. the size of both the cs0 and cs1 spaces can be a minimum of 16 kb to a maximum of 1 gb. the external address space of the tmp19a64 is 16 mb and so bits 10 through 15 must be set to "0" as addresses a24 through a29 are not masked. fig. 9.1.1 base and mask addres s setting registers (bma0, bma1) tmp19a64c1d tmp19a64 (rev1.1) 9-4 31 30 29 28 27 26 25 24 bma2 bit symbol ba2 (0xffff_e408h) read/write r/w after reset 0 0 0 0 0 0 0 0 function a31 to a24 to be set as a start address 23 22 21 20 19 18 17 16 bit symbol ba2 read/write r/w after reset 0 0 0 0 0 0 0 0 function a23 to a16 to be set as a start address 15 14 13 12 11 10 9 8 bit symbol ma2 read/write r/w after reset 0 0 0 0 0 0 0 1 function make sure that you write "0." 7 6 5 4 3 2 1 0 bit symbol ma2 read/write r/w after reset 1 1 1 1 1 1 1 1 function cs2 space size setting 0: address for comparison 31 30 29 28 27 26 25 24 bma3 bit symbol ba3 (0xffff_e40ch) read/write r/w after reset 0 0 0 0 0 0 0 0 function a31 to a24 to be set as a start address 23 22 21 20 19 18 17 16 bit symbol ba3 read/write r/w after reset 0 0 0 0 0 0 0 0 function a23 to a16 to be set as a start address 15 14 13 12 11 10 9 8 bit symbol ma3 read/write r/w after reset 0 0 0 0 0 0 0 1 function make sure that you write "0." 7 6 5 4 3 2 1 0 bit symbol ma3 read/write r/w after reset 1 1 1 1 1 1 1 1 function cs3 space size setting 0: address for comparison (note) make sure that you write "0" for bits 9 through 15 for bma2 and bma3. the size of both the cs2 and cs3 spaces can be a minimum of 32 kb to a maximum of 2 gb. the external address space of the tmp19a64 is 16 mb and so bits 9 through 15 must be set to "0" as addresses a24 through a30 are not masked. fig. 9.1.2 base and mask addres s setting registers (bma2, bma3) tmp19a64c1d tmp19a64 (rev1.1) 9-5 31 30 29 28 27 26 25 24 bma4 bit symbol ba4 (0xffff_e410h) read/write r/w after reset 0 0 0 0 0 0 0 0 function a31 to a24 to be set as a start address 23 22 21 20 19 18 17 16 bit symbol ba4 read/write r/w after reset 0 0 0 0 0 0 0 0 function a23 to a16 to be set as a start address 15 14 13 12 11 10 9 8 bit symbol ma4 read/write r/w after reset 0 0 0 0 0 0 0 1 function make sure that you write "0." 7 6 5 4 3 2 1 0 bit symbol ma4 read/write r/w after reset 1 1 1 1 1 1 1 1 function cs4 space size setting 0: address for comparison 31 30 29 28 27 26 25 24 bma5 bit symbol ba5 (0xffff_e414h) read/write r/w after reset 0 0 0 0 0 0 0 0 function a31 to a24 to be set as a start address 23 22 21 20 19 18 17 16 bit symbol ba5 read/write r/w after reset 0 0 0 0 0 0 0 0 function a23 to a16 to be set as a start address 15 14 13 12 11 10 9 8 bit symbol ma5 read/write r/w after reset 0 0 0 0 0 0 0 1 function make sure that you write "0." 7 6 5 4 3 2 1 0 bit symbol ma5 read/write r/w after reset 1 1 1 1 1 1 1 1 function cs5 space size setting 0: address for comparison (note) make sure that you write "0" for bits 9 through 15 for bma4 and bma5. the size of both the cs4 and cs5 spaces can be a minimum of 32 kb to a maximum of 2 gb. the external address space of the tmp19a64 is 16 mb and so bits 9 through 15 must be set to "0" as addresses a24 through a30 are not masked. fig. 9.1.3 base and mask addres s setting registers (bma4, bma5) tmp19a64c1d tmp19a64 (rev1.1) 9-6 start address base address value (ban) 0xffff_0000h 0xffff_ffffh ffffh address 0x0000_0000h 64 kb 0x0006_0000h 0006h 0x0005_0000h 0005h 0x0004_0000h 0004h 0x0003_0000h 0003h 0x0002_0000h 0002h 0x0001_0000h 0001h 0x0000_0000h 0000h fig. 9.1.4 start and base address register values 9.1.2 how to define start addresses and address spaces ? to specify a space of 64 kb star ting at 0xc000_0000 in the cs0 space, the base and mask address registers must be programmed as shown below. 31 1615 0 ba0 ma0 1 1 0 00 0 0 0 0 0000000000000000 0 0 0 0 0 1 1 c 0 0 0 0 0 0 3 values to be set in the base and mask address registers (bma0) in the base address (ba0), specify "0xc000" that corresp onds to higher 16 bits of a start address, while in the mask address (ma0), specify whet her a comparison of addresses in the space a29 through a16 is to be made or not. to ensure a comparison of a29 through a16, set bits 15 to 2 of the mask address (ma0) to "0." a comparison of addresses of a31 and a30 will definitely be made. this setting allows a31 through a16 to be compared w ith the value specified as a start addres s. as a15 through a0 are masked, a space of 64 kb from 0xc000_0000 to 0xc000_ffff is desi gnated as a cs0 space and the cso signal is asserted if there is a match with an address on the bus. tmp19a64c1d tmp19a64 (rev1.1) 9-7 ? to specify a space of 1 mb star ting at 0x1fd0_0000 in the cs2 sp ace, the base and mask address registers must be programmed as shown below. 31 1615 0 ba2 ma2 0 0 0 11 1 1 1 1 1010000000000000 0 0 1 1 1 1 1 1 f d 0 0 0 1 f values to be set in the base and mask address registers (bma2) in the base address (ba2), specify "0x1fd0" that corresponds to higher 16 bits of a start address, while in the mask address (ma2), specify whet her a comparison of addresses in the space a30 through a15 is to be made or not. to ensure a comparison of a30 through a20, set bits 15 to 5 of the mask address (ma2) to "0." a comparison of a3 1 will definitely be made. this setting allows a31 through a20 to be compared w ith the value specified as a start addres s. as a19 through a0 are masked, a space of 1 mb from 0x1 fd0_0000 to 0x1f df_ffff is designated as a cs2 space. note: the csn signal is not asserted to the following address spaces in the tmp19a64: 0x1fc0_0000 to 0x1fcf_ffff 0x4000_0000 to 0x400f_ffff 0xfffd_6000 to 0xfffd_ffff, 0xffff_6000 to 0xffff_dfff after a reset, the cs0, cs1, and cs3 through cs5 spaces are disabled , while the whole cs2 space (4 gb) is enabled as an address space. tmp19a64c1d tmp19a64 (rev1.1) 9-8 table 9.1.1 shows the relationship between cs space and space sizes. if two or more address spaces are specified simultaneously, a space or spaces with a smaller space number will be given priority in space selection. example: 0xc000_0000 as a start address of the cs0 space with a space size of 16 kb 0xc000_0000 as a start address of the cs1 space with a space size of 64 kb table 9.1.1 cs space and space sizes size (bytes) cs space 16 k 32 k 64 k 128 k 256 k 512 k 1 m 2 m 4 m 8 m 16 m cs0 { { { { { { { { { { { cs1 { { { { { { { { { { { cs2 { { { { { { { { { { cs3 { { { { { { { { { { cs4 { { { { { { { { { { cs5 { { { { { { { { { { 0xc000_0000 0xc000_3fff 0xc000_0000 0xc000_3fff 0xc000_ffff cs1 space cs0 space if a space of 0xc000_0000 to 0xc000_3fff is accessed, the cs0 space is selected. tmp19a64c1d tmp19a64 (rev1.1) 9-9 9.2 the chip selector and wait controller fig. 9.2.1 to fig. 9.2.4 show the chip selector and wait controller registers. for each address space (spaces cs0 through cs5 and other address spaces), each chip selector and wait controller register (b01cs through b45cs, bexcs) can be programmed to set master enable or disable, to select data bus width, to specify the number of waits and to insert dummy cycles. if two or more address spaces are specified simultane ously, a space or spaces with a smaller space number will be given priority in space selection (order of priority: cs0>cs1>cs2>cs3>cs4>cs5>excs). tmp19a64c1d tmp19a64 (rev1.1) 9-10 7 6 5 4 3 2 1 0 b01cs bit symbol b0om b0bus b0w (ffffe480h) read/write r/w r r/w r/w after reset 0 0 0 0 0 1 0 1 function select the chip selector output waveform. 00: rom/ram do not make any other settings. select data bus width. 0: 16bit 1: 8bit specify the number of waits. (automatic wait insertion) 0000: 0wait 0001: 1wait 0010: 2wait 0011: 3wait 0100: 4wait 0101: 5wait 0110: 6wait 0111: 7wait (external wait input) 1010: (2 + 2n) wait 1011: (3 + 2n) wait 1100: (4 + 2n) wait 1101: (5 + 2n) wait 1110: (6 + 2n) wait 1111: (7 + 2n) wait 1000,1001: reserved 15 14 13 12 11 10 9 8 bit symbol b0cscv b0wcv b0e b0rcv read/write r r/w r/w r/w r r/w after reset 0 0 0 0 0 0 0 0 function specify the number of dummy cycles to be inserted. (cs0 recovery time) 1: 1 cycle 0: none specify the number of dummy cycles to be inserted. (write, recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting prohibited enable or disable cs0. 0: disable 1: enable specify the number of dummy cycles to be inserted. (read, recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting prohibited 23 22 21 20 19 18 17 16 bit symbol b1om b1bus b1w read/write r/w r r/w r/w after reset 0 0 0 0 0 1 0 1 function select the chip selector output waveform. 00: rom/ram do not make any other settings. select data bus width. 0: 16bit 1: 8bit specify the number of waits. (automatic wait insertion) 0000: 0wait 0001: 1wait 0010: 2wait 0011: 3wait 0100: 4wait 0101: 5wait 0110: 6wait 0111: 7wait (external wait input) 1010: (2 + 2n) wait 1011: (3 + 2n) wait 1100: (4 + 2n) wait 1101: (5 + 2n) wait 1110: (6 + 2n) wait 1111: (7 + 2n) wait 1000,1001: reserved 31 30 29 28 27 26 25 24 bit symbol b1cscv b1wcv b1e b1rcv read/write r r/w r/w r/w r r/w after reset 0 0 0 0 0 0 0 0 function specify the number of dummy cycles to be inserted. (cs1 recovery time) 1: 1 cycle 0: none specify the number of dummy cycles to be inserted. (write, recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting prohibited enable or disable cs1. 0: disable 1: enable specify the number of dummy cycles to be inserted. (read, recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting prohibited fig. 9.2.1 chip selector and wait controller registers tmp19a64c1d tmp19a64 (rev1.1) 9-11 7 6 5 4 3 2 1 0 b23cs bit symbol b2om b2bus b2w (0xffff_e484h) read/write r/w r r/w r/w after reset 0 0 0 0 0 1 0 1 function select the chip selector output waveform. 00: rom/ram do not make any other settings. select data bus width. 0: 16bit 1: 8bit specify the number of waits. (automatic wait insertion) 0000: 0wait 0001: 1wait 0010: 2wait 0011: 3wait 0100: 4wait 0101: 5wait 0110: 6wait 0111: 7wait (external wait input) 1010: (2 + 2n) wait 1011: (3 + 2n) wait 1100: (4 + 2n) wait 1101: (5 + 2n) wait 1110: (6 + 2n) wait 1111: (7 + 2n) wait 1000,1001: reserved 15 14 13 12 11 10 9 8 bit symbol b2cscv b2wcv b2e b2m b2rcv read/write r r/w r/w r/w after reset 0 0 0 0 1 0 0 0 function specify the number of dummy cycles to be inserted. (cs2 recovery time) 1: 1 cycle 0: none specify the number of dummy cycles to be inserted. (write, recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting prohibited enable or disable cs2. 0: disable 1: enable select cs2 space. 0: 4g space 1: cs space specify the number of dummy cycles to be inserted. (read, recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting prohibited 23 22 21 20 19 18 17 16 bit symbol b3om b3bus b3w read/write r/w r r/w r/w after reset 0 0 0 0 0 1 0 1 function select the chip select output waveform. 00: rom/ram do not make any other settings. select data bus width. 0: 16bit 1: 8bit specify the number of waits. (automatic wait insertion) 0000: 0wait 0001: 1wait 0010: 2wait 0011: 3wait 0100: 4wait 0101: 5wait 0110: 6wait 0111: 7wait (external wait input) 1010: (2 + 2n) wait 1011: (3 + 2n) wait 1100: (4 + 2n) wait 1101: (5 + 2n) wait 1110: (6 + 2n) wait 1111: (7 + 2n) wait 1000,1001: reserved 31 30 29 28 27 26 25 24 bit symbol b3cscv b3wcv b3e b3rcv read/write r r/w r/w r/w r r/w after reset 0 0 0 0 0 0 0 0 function specify the number of dummy cycles to be inserted. (cs3 recovery time) 1: 1 cycle 0: none specify the number of dummy cycles to be inserted. (write, recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting prohibited enable or disable cs3. 0: disable 1: enable specify the number of dummy cycles to be inserted. (read, recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting prohibited fig. 9.2.2 chip selector an d wait controller registers tmp19a64c1d tmp19a64 (rev1.1) 9-12 7 6 5 4 3 2 1 0 b45cs bit symbol b4om b4bus b4w (0xffff_e488h) read/write r/w r r/w r/w after reset 0 0 0 0 0 1 0 1 function select the chip selector output waveform. 00: rom/ram do not make any other settings. select data bus width. 0: 16bit 1: 8bit specify the number of waits. (automatic wait insertion) 0000: 0wait 0001: 1wait 0010: 2wait 0011: 3wait 0100: 4wait 0101: 5wait 0110: 6wait 0111: 7wait (external wait input) 1010: (2 + 2n) wait 1011: (3 + 2n) wait 1100: (4 + 2n) wait 1101: (5 + 2n) wait 1110: (6 + 2n) wait 1111: (7 + 2n) wait 1000,1001: reserved 15 14 13 12 11 10 9 8 bit symbol b4cscv b4wcv b4e b4rcv read/write r r/w r/w r/w r r/w after reset 0 0 0 0 1 0 0 0 function specify the number of dummy cycles to be inserted. (cs4 recovery time) 1: 1 cycle 0: none specify the number of dummy cycles to be inserted. (write, recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting prohibited enable or disable cs4. 0: disable 1: enable specify the number of dummy cycles to be inserted. (read, recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting prohibited 23 22 21 20 19 18 17 16 bit symbol b5om b5bus b5w read/write r/w r r/w r/w after reset 0 0 0 0 0 1 0 1 function select the chip select output waveform. 00: rom/ram do not make any other settings. select data bus width. 0: 16bit 1: 8bit specify the number of waits. (automatic wait insertion) 0000: 0wait 0001: 1wait 0010: 2wait 0011: 3wait 0100: 4wait 0101: 5wait 0110: 6wait 0111: 7wait (external wait input) 1010: (2 + 2n) wait 1011: (3 + 2n) wait 1100: (4 + 2n) wait 1101: (5 + 2n) wait 1110: (6 + 2n) wait 1111: (7 + 2n) wait 1000,1001: reserved 31 30 29 28 27 26 25 24 bit symbol b5cscv b5wcv b5e b5rcv read/write r r/w r/w r/w r r/w after reset 0 0 0 0 0 0 0 0 function specify the number of dummy cycles to be inserted. (cs5 recovery time) 1: 1 cycle 0: none specify the number of dummy cycles to be inserted. (write, recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting prohibited enable or disable cs5. 0: disable 1: enable specify the number of dummy cycles to be inserted. (read, recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting prohibited fig. 9.2.3 chip selector and wait controller registers tmp19a64c1d tmp19a64 (rev1.1) 9-13 7 6 5 4 3 2 1 0 bexcs bit symbol bexom bexbus bexw (0xffff_e48ch) read/write r/w r r/w r/w after reset 0 0 0 0 0 1 0 1 function select the chip selector output waveform. 00: rom/ram do not make any other settings. select data bus width. 0: 16bit 1: 8bit specify the number of waits. (automatic wait insertion) 0000: 0wait 0001: 1wait 0010: 2wait 0011: 3wait 0100: 4wait 0101: 5wait 0110: 6wait 0111: 7wait (external wait input) 1010: (2 + 2n) wait 1011: (3 + 2n) wait 1100: (4 + 2n) wait 1101: (5 + 2n) wait 1110: (6 + 2n) wait 1111: (7 + 2n) wait 1000,1001: reserved 15 14 13 12 11 10 9 8 bit symbol becscv bexwcv bexrcv read/write r r/w r/w r/w r r/w after reset 0 0 0 0 0 0 0 0 function specify the number of dummy cycles to be inserted. 1: 1 cycle 0: none specify the number of dummy cycles to be inserted. (write, recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting prohibited specify the number of dummy cycles to be inserted. (read, recovery time) 00: 2 cycles 01: 1 cycle 10: none 11: setting prohibited 23 22 21 20 19 18 bit symbol read/write r after reset 0 0 0 0 0 0 0 0 function 31 30 29 28 27 26 25 24 bit symbol read/write r r/w r after reset 0 0 0 0 0 0 0 0 function fig. 9.2.4 chip selector and wait controller registers a reset of the tmp19a64 allows the port 4 controller register (p4cr) and the port 4 function register (p4fc) to be cleared to "0," and the cs signal output is disabled. to output the cs signals, set the corresponding bits to "1" at the p4fc and the p4cr in that order. the cs recovery time can be configured in any other areas than th e cs setting areas, but cs si gnals will not be output. tmp19a64c1d tmp19a64(rev1.1)-10-1 10. dma controller (dmac) the tmp19a64 has a built-in 8-channel dma controller (dmac). 10.1 features the dmac of the tmp19a64 has the following features: (1) dma with 8 independent channels (2) two types of requests for bus control authority: with and without snoop requests (3) transfer requests: internal requ ests (software initiated)/external requests (external interrupts, interrupt requests given by internal peripheral i/os, and requests given by the dreq pin) requests given by the dreq pin (ch2, 3): level mode (memory memory) edge mode (memory i/o, i/o to memory) (4) transfer mode: dual address mode (5) transfer devices: memory-to-memory, memory-to-i/o, i/o-to-memory (6) device size: 32-bit memory (8 or 16 bits can be specified using the cs/wait controller); i/o of 8, 16 or 32 bits (7) address changes: increase, decrease, fi xed, irregular increase, irregular decrease (8) channel priority: fixed (in ascending order of channel numbers) (9) endian switchover function tmp19a64c1d tmp19a64(rev1.1)-10-2 10.2 configuration 10.2.1 internal connections of the tmp19a64 fig. 10.2.1 shows the internal connections with the dmac in the tmp19a64. (note) in fig. 10.1, signals indi cated by * are internal signals. fig. 10.2.1 dmac connections in the tmp19a64 the dmac has eight dma channels. each of these ch annels handles the data transfer request signal (intdreqn) from the interrupt controller and the acknowledgment signal (dackn) generated in response to intdreqn, where "n" is a channel number from 0 to 7. external pins (dreq2 and dreq3) are internally wired to allow them to function as pins of the port f and j. to use them as pins of the port f and j, they must be selected by setting the function control register pffc and pjfc to an appropriate setting. if both ports are set to use the dmac function, the port f is given priority in using the dmac function. pins, dack2 and dack3, handle the data transfer request and acknowledge signal output supplied through external pins, dreq2 and dreq3. channel 0 is given higher priority than channel 1, channel 1 higher priority than channel 2 and channel 2 higher priority than channel 3. subsequent channels are given priority in the same manner. the tx19a processor core has a snoop function. using the snoop function, the tx19a processor core opens the core's data bus to the dmac, thus allowing the dmac to access the internal rom and ram linked to the core. the dmac is capable of determining whether or not to use this snoop function. for further information on the snoop function, refer to 10.2.3 "snoop function." two types of bus control authority (sreq and greq ) are available to the dmac and which type of control right to use depends on the use or nonuse of the snoop function. greq is a request for bus control authority if the dmac does not use the snoop function, while sreq is a request for bus control authority if the dmac uses the snoop function. sreq is given higher priority than greq. tx19a processor core address data notification to release bus control authority control request for bus control authority request to release bus control authority busgnt * busrel * intdreq [7 : 0]* dack [7 : 0]* dmac notification of bus control authority ownership haveit * interrupt controller (external request) internal i/o interrupt request external interrupt request busreq * dreq [3 : 2] dack [3 : 2] port f and j function control tmp19a64c1d tmp19a64(rev1.1)-10-3 10.2.2 dmac internal blocks fig. 10.2.2 shows the internal blocks of the dmac. channel 3 channel 2 destination address register (darx) source address register (sarx) byte count register (bsrx) channel control register (ccrx) 31 0 channel 0 dma control register (dcr) data holding register (dhr) channel status register (csrx) dma transfer control register (dtcrx) request select register (rsr) (x 0 through 7) channel 4 channel 5 channel 6 channel 7 channel 1 fig. 10.2.2 dmac internal blocks 10.2.3 snoop function the tx19a processor core has a snoop function. if the snoop function is activated, the tx19a processor core opens the core's data bus to the dmac and su spends its own operation until the dmac withdraws a request for bus control authority. if the snoop functio n is enabled, the dmac can access the internal ram and rom and therefore desi gnate the ram or rom as a source or destination. if the snoop function is not used, the dmac cannot acce ss the internal ram or ro m. however, the g-bus is opened to the dmac. if the tx19a processor core attempts to access memory or the i/o by way of the g-bus and if the dmac does not accept a bus control release request, bus operations cannot be executed and, as a result, the pipeline stalls. (note) if the snoop function is not used, the tx19a processor core does not open the data bus to the dmac. if the data bus is closed and the internal ram or rom is designated as a dmac source or destination, an acknowledgment signal will not be returned in response to a dmac transfer bus cycle and, as a result, the bus will lock. tmp19a64c1d tmp19a64(rev1.1)-10-4 10.3 registers the dmac has fifty-one 32-bit registers. table 10.3.1 shows the register map of the dmac. table 10.3.1 dmac registers address register symbol register name 0xffff_e200 ccr0 channel cont rol register (ch. 0) 0xffff_e204 csr0 channel st atus register (ch. 0) 0xffff_e208 sar0 source address register (ch. 0) 0xffff_e20c dar0 destination address register (ch. 0) 0xffff_e210 bcr0 byte count register (ch. 0) 0xffff_e218 dtcr0 dma transfer control register (ch. 0) 0xffff_e220 ccr1 channel cont rol register (ch. 1) 0xffff_e224 csr1 channel st atus register (ch. 1) 0xffff_e228 sar1 source address register (ch. 1) 0xffff_e22c dar1 destination address register (ch. 1) 0xffff_e230 bcr1 byte count register (ch. 1) 0xffff_e238 dtcr1 dma transfer control register (ch. 1) 0xffff_e240 ccr2 channel cont rol register (ch. 2) 0xffff_e244 csr2 channel st atus register (ch. 2) 0xffff_e248 sar2 source address register (ch. 2) 0xffff_e24c dar2 destination address register (ch. 2) 0xffff_e250 bcr2 byte count register (ch. 2) 0xffff_e258 dtcr2 dma transfer control register (ch. 2) 0xffff_e260 ccr3 channel cont rol register (ch. 3) 0xffff_e264 csr3 channel st atus register (ch. 3) 0xffff_e268 sar3 source address register (ch. 3) 0xffff_e26c dar3 destination address register (ch. 3) 0xffff_e270 bcr3 byte count register (ch. 3) 0xffff_e278 dtcr3 dma transfer control register (ch. 3) 0xffff_e280 ccr4 channel cont rol register (ch. 4) 0xffff_e284 csr4 channel st atus register (ch. 4) 0xffff_e288 sar4 source address register (ch. 4) 0xffff_e28c dar4 destination address register (ch. 4) 0xffff_e290 bcr4 byte count register (ch. 4) 0xffff_e298 dtcr4 dma transfer control register (ch. 4) 0xffff_e2a0 ccr5 channel c ontrol register (ch. 5) 0xffff_e2a4 csr5 channel st atus register (ch. 5) 0xffff_e2a8 sar5 source address register (ch. 5) 0xffff_e2ac dar5 destination address register (ch. 5) 0xffff_e2b0 bcr5 byte count register (ch. 5) 0xffff_e2b8 dtcr5 dma transfer control register (ch. 5) 0xffff_e2c0 ccr6 channel control register (ch. 6) 0xffff_e2c4 csr6 channel status register (ch. 6) 0xffff_e2c8 sar6 source address register (ch. 6) 0xffff_e2cc dar6 destination a ddress register (ch. 6) 0xffff_e2d0 bcr6 byte count register (ch. 6) 0xffff_e2d8 dtcr6 dma transfer control register (ch. 6) tmp19a64c1d tmp19a64(rev1.1)-10-5 table 10.3.1 dmac registers (2) 0xffff_e2e0 ccr7 channel control register (ch. 7) 0xffff_e2e4 csr7 channel status register (ch. 7) 0xffff_e2e8 sar7 source address register (ch. 7) 0xffff_e2ec dar7 destination address register (ch. 7) 0xffff_e2f0 bcr7 byte count register (ch. 7) 0xffff_e2f8 dtcr7 dma transfer control register (ch. 7) 0xffff_e300 dcr dma control register (dmac) 0xffff_e304 rsr request se lect register (dmac) 0xffff_e30c dhr data holding register (dmac) tmp19a64c1d tmp19a64(rev1.1)-10-6 10.3.1 dma control register (dcr) 7 6 5 4 3 2 1 0 dcr bit symbol rst7 rst6 rst5 rst4 rst3 rst2 rst1 rst0 (0xffff_e300h) read/write w after reset 0 0 0 0 0 0 0 0 function see detailed description. 15 14 13 12 11 10 9 8 bit symbol read/write r after reset 0 function 23 22 21 20 19 18 17 16 bit symbol read/write r after reset 0 function 31 30 29 28 27 26 25 24 bit symbol rstall read/write w r after reset 0 0 function see detailed description. bit mnemonic field name description 31 rstall reset all performs a software reset of the dmac. if the rstall bit is set to 1, the values of all the internal registers of the dmac are reset to their initial values. all transfer requests are canceled and all eight channels go into an idle state. 0: don't care 1: initializes the dmac 7 rst7 reset 7 performs a software reset of th e dmac channel 7. if the rst7 bit is set to 1, internal registers of the dmac channel 7 and a corresponding bit of the channel 7 of the rsr register are reset to their initial values. the transfer request of the channel 7 is canceled and the channel 7 goes into an idle state. 0: don't care 1: initializes the dmac channel 7 6 rst6 reset 6 performs a software reset of th e dmac channel 6. if the rst6 bit is set to 1, internal registers of the dmac channel 6 and a corresponding bit of the channel 6 of the rsr register are reset to their initial values. the transfer request of the channel 6 is canceled and the channel 6 goes into an idle state. 0: don't care 1: initializes the dmac channel 6 5 rst5 reset 5 performs a software reset of th e dmac channel 5. if the rst5 bit is set to 1, internal registers of the dmac channel 5 and a corresponding bit of the channel 5 of the rsr register are reset to their initial values. the transfer request of the channel 5 is canceled and the channel 5 goes into an idle state. 0: don't care 1: initializes the dmac channel 5 fig. 10.3.1 dma control register (dcr) (1 of 2) tmp19a64c1d tmp19a64(rev1.1)-10-7 bit mnemonic field name description 4 rst4 reset 4 performs a software reset of th e dmac channel 4. if the rst4 bit is set to 1, internal registers of the dmac channel 4 and a corresponding bit of the channel 4 of the rsr register are reset to their initial values. the transfer request of the channel 4 is canceled and the channel 4 goes into an idle state. 0: don't care 1: initializes the dmac channel 4 3 rst3 reset 3 performs a software reset of th e dmac channel 3. if the rst3 bit is set to 1, internal registers of the dmac channel 3 and a corresponding bit of the channel 3 of the rsr register are reset to their initial values. the transfer request of the channel 3 is canceled and the channel 3 goes into an idle state. 0: don't care 1: initializes the dmac channel 3 2 rst2 reset 2 performs a software reset of th e dmac channel 2. if the rst2 bit is set to 1, internal registers of the dmac channel 2 and a corresponding bit of the channel 2 of the rsr register are reset to their initial values. the transfer request of the channel 2 is canceled and the channel 2 goes into an idle state. 0: don't care 1: initializes the dmac channel 2 1 rst1 reset 1 performs a software reset of th e dmac channel 1. if the rst1 bit is set to 1, internal registers of the dmac channel 1 and a corresponding bit of the channel 1 of the rsr register are reset to their initial values. the transfer request of the channel 1 is canceled and the channel 1 goes into an idle state. 0: don't care 1: initializes the dmac channel 1 0 rst0 reset 0 performs a software reset of th e dmac channel 0. if the rst0 bit is set to 1, internal registers of the dmac channel 0 and a corresponding bit of the channel 0 of the rsr register are reset to their initial values. the transfer request of the channel 0 is canceled and the channel 0 goes into an idle state. 0: don't care 1: initializes the dmac channel 0 fig. 10.3.1 dma control register (dcr) (2 of 2) (note 1) if a write to the dcr register occurs duri ng a software reset right after the last round of dma transfer is completed, the interrupt to stop dma transfer is not canceled although the channel register is initialized. (note 2) an attempt to execute a write (software reset) to the dcr register by dma transfer must be strictly avoided. tmp19a64c1d tmp19a64(rev1.1)-10-8 10.3.2 channel control registers (ccrn) (n=0 through 7) 7 6 5 4 3 2 1 0 ccrn bit symbol sac dio dac trsiz dps (0xffff_e200h) read/write r/w r/w r/w r/w r/w (0xffff_e220h) after reset 0 0 0 0 0 0 0 0 (0xffff_e240h) function see detailed description. (0xffff_e260h) 15 14 13 12 11 10 9 8 (0xffff_e280h) bit symbol exr pose lev sreq relen sio sac (0xffff_e2a0h) read/write w r/w r/w r/w r/w r/w r/w r/w (0xffff_e2c0h) after reset 0 0 0 0 0 0 0 0 (0xffff_e2e0h) function always set this bit to "0." see detailed description. 23 22 21 20 19 18 17 16 bit symbol nien ablen big read/write r/w r/w r/w r/w r/w r/w r/w w after reset 1 1 1 0 0 0 1 0 function see detailed description. always set this bit to "0." see detailed description. always set this bit to "0." 31 30 29 28 27 26 25 24 bit symbol str read/write w w after reset 0 0 0 0 0 0 0 0 function see detailed description. always set this bit to "0." bit mnemonic field name description 31 str channel start start (initial value: 0) starts channel operation. if this bit is set to 1, the channel goes into a standby mode and starts to transfer data in response to a transfer request. only a write of 1 is valid to the str bit and a write of 0 is ignored. a read always returns a 0. 1: starts channel operation 24 ? (reserved) this is a reserved bi t. always set this bit to "0." 23 nien normal completion interrupt enable normal completion interrupt enable (initial value: 1) 1: normal completion interrupt enable 0: normal completion interrupt disable 22 abien abnormal completion interrupt enable abnormal completion interrupt enable (initial value: 1) 1: abnormal completion interrupt enable 0: abnormal completion interrupt disable 21 ? (reserved) this is a reserved bit. alth ough its initial value is "1," always set this bit to "0." 20 ? (reserved) this is a reserved bi t. always set this bit to "0." 19 ? (reserved) this is a reserved bi t. always set this bit to "0." 18 ? (reserved) this is a reserved bi t. always set this bit to "0." fig. 10.3.2 channel control r egister (ccrn) (1 of 3) tmp19a64c1d tmp19a64(rev1.1)-10-9 bit mnemonic field name description 17 big big-endian big endian (initial value: 1) 1: a channel operates by big-endian 0: a channel operates by little-endian 16 ? (reserved) this is a reserved bi t. always set this bit to "0." 15 ? (reserved) this is a reserved bi t. always set this bit to "0." 14 exr external request mode external request mode (initial value: 0) selects a transfer request mode. 1: external transfer request (interr upt request or external dreqn request) 0: internal transfer request (software initiated) 13 pose positive edge positive edge (initial value: 0) the effective level of the transfer request signal intdreqn or dreqn is specified. this function is valid only if the transfer request is an external transfer request (if the exr bit is 1). if it is an internal transfer request (if the exr bit is 0), the pose value is ignored. because the intdreqn and dreqn signals are active at "l" level, ma ke sure that this pose bit is set to "0." 1: setting prohibited 0: the falling edge of the intdreqn or dreqn signal or the "l" level is effective. the dackn is active at "l" level. 12 lev level mode level m ode (initial value: 0) specifies which is used to recognize the external transfer request, signal level or signal change. this setting is valid only if a transfer request is the external transfer request (if the exr bit is 1). if the internal transfer request is specified as a transfer request (if the exr bit is 0), the value of the lev bit is ignored. because th e intdreqn signal is active at "l" level, make sure that you set the lev bit to "1." the state of active dreqn is determined by the lev bit setting. 1: level mode the level of the dreqn signal is recogn ized as a data transfer request. (the "l" level is recognized if the pose bit is 0. 0: edge mode a change in the dreqn signal is recognized as a data transfer request. (a falling edge is recognized if the pose bit is 0.) 11 sreq snoop request snoop reque st (initial value: 0) the use of the snoop function is specified by asserting the bus control request mode. if the snoop function is used, the snoop function of the tx19a processor core is enabled and the dmac can use the data bus of the tx19a processor core. if the snoop function is not used, the snoop function of the tx19a processor core does not work. 1: use snoop function (sreq) 0: do not use snoop function (greq) 10 relen bus control release request enable release request enable (initial value: 0) acknowledgment of the bus control re lease request made by the tx19a processor core is specified. this function is valid only if greq is generated. if sreq is generated, th e tx19a processor core cannot make a bus control release request and, ther efore, this function cannot be used. 1: the bus control release request is acknowledged if the dmac has control of the bus. if the tx19a processor core issues a bus control release request, the dmac relinqui shes control of the bus to the tx19a processor core during a pause in bus operation. 0: the bus control release request is not acknowledged. 9 sio source i/o source type: i/o (initial value: 0) specifies the source device. 1: i/o device 0: memory fig. 10.3.2 channel contro l register (ccrn) (2/3) tmp19a64c1d tmp19a64(rev1.1)-10-10 bit mnemonic field name description 8 : 7 sac source address count source a ddress count (initial value: 00) source address count (i nitial value: 00) specifies the manner of change in a source address. 1x: address fixed 01: address decrease 00: address increase 6 dio destination i/o destination type: i/o (initial value: 0) specifies a destination device. 1: i/o device 0: memory 5 : 4 dac destination address count destination address count (initial value: 00) specifies the manner of change in a destination address. 1x: address fixed 01: address decrease 00: address increase 3 : 2 trsiz transfer unit transfer size (initial value: 00) specifies the amount of data to be tr ansferred in response to one transfer request. 11: 8 bits (1 byte) 10: 16 bits (2 bytes) 0x: 32 bits (4 bytes) 1 : 0 dps device port size device port size (initial value: 00) specifies the bus width of an i/o device designated as a source or destination device. 11: 8 bits (1 byte) 10: 16 bits (2 bytes) 0x: 32 bits (4 bytes) fig. 10.3.2 channel contro l register (ccrn) (3/3) (note 1) the ccrn register setting must be completed before the dmac is put into a standby mode. (note 2) when accessing the internal i/o or transferring data by dma in response to the dreq pin request, make sure that you set the transfer unit tmp19a64c1d tmp19a64(rev1.1)-10-11 10.3.3 request select register (rsr) 7 6 5 4 3 2 1 0 rsr bit symbol reqs3 reqs2 (0xffff_e304h) read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function always set this bit to "0." see detailed description. always set this bit to "0." 15 14 13 12 11 10 9 8 bit symbol read/write r after reset 0 function 23 22 21 20 19 18 17 16 bit symbol read/write r after reset 0 function 31 30 29 28 27 26 25 24 bit symbol read/write r after reset 0 function bit mnemonic field name description 3 reqs3 request select (ch.3) request select (initial value: 0) selects a source of the external transfer request for the dma channel 3. 1: request made by dreq3 0: request made by the interrupt controller (intc) 2 reqs2 request select (ch.2) request select (initial value: 0) selects a source of the external transfer request for the dma channel 2. 1: request made by dreq2 0: request made by the interrupt controller (intc) fig. 10.3.3 dma control register (rsr) (note) make sure that you write "0" to bits 0, 1 and 4 through 7 of the rsr register. tmp19a64c1d tmp19a64(rev1.1)-10-12 10.3.4 channel status registers (csrn) (n=0 through 7) 7 6 5 4 3 2 1 0 csrn bit symbol (0xffff_e204h) read/write r r/w r/w r/w (0xffff_e224h) after reset 0 0 0 0 (0xffff_e244h) function always set this bit to "0." (0xffff_e264h) 15 14 13 12 11 10 9 8 (0xffff_e284h) bit symbol (0xffff_e2a4h) read/write r (0xffff_e2c4h) after reset 0 (0xffff_e2e4h) function 23 22 21 20 19 18 17 16 bit symbol nc abc bes bed conf read/write r/w r/w r/w r r r r after reset 0 0 0 0 0 0 0 function see detailed description. always set this bit to "0." see detailed description. 31 30 29 28 27 26 25 24 bit symbol act read/write r r after reset 0 0 function see detailed description. bit mnemonic field name description 31 act channel active channel active (initial value: 0) indicates whether the channel is in a standby mode: 1: in a standby mode 0: not in a standby mode 23 nc normal completion normal completion (initial value: 0) indicates normal completion of cha nnel operation. if an interrupt at normal completion is permitted by the ccr register, the dmac requests an interrupt when the nc bit becomes 1. this setting can be cleared by writing 0 to the nc bit. if a request for an interrupt at normal completion was previously issued, the request is canceled if the nc bit becomes 0. if an attempt is made to set the str bit to 1 when the nc bit is 1, an error occurs. to start the next transfer, the nc bit must be cleared to 0. a write of 1 will be ignored. 1: channel operation has been completed normally. 0: channel operation has not been completed normally fig. 10.3.4 channel status registers (csrn) (1/2) tmp19a64c1d tmp19a64(rev1.1)-10-13 bit mnemonic field name description 22 abc abnormal completion abnormal completion (initial value: 0) indicates abnormal completion of channel operation. if an interrupt at abnormal completion is permitted by the ccr register, the dmac requests an interrupt when the abc bit becomes 1. this setting can be cleared by writing 0 to the abc bit. if a request for an interrupt at abnormal completion was previously issued, the request is canceled if the abc bit becomes 0. additionally, if the abc bit is cleared to 0, each of the bes, bed and conf bits are cleared to 0. if an attempt is made to set the str bit to 1 when the abc bit is 1, an error occurs. to start the next transfer, the abc bit must be cleared to 0. a write of 1 will be ignored. 1: channel operation has been completed abnormally. 0: channel operation has not been completed abnormally. 21 ? (reserved) this is a reserved bi t. always set this bit to "0." 20 bes source bus error source bu s error (initial value: 0) 1: a bus error has occurred when the source was accessed. 0: a bus error has not occurred when the source was accessed. 19 bed destination bus error destination bus error (initial value: 0) 1: a bus error has occurred when the destination was accessed. 0: a bus error has not occurred when the destination was accessed. 18 conf configuration error confi guration error (initial value: 0) 1: a configuration error has occurred. 0: a configuration error has not occurred. 2 : 0 ? (reserved) these three bits are reserved bits. always set them to "0." fig. 10.3.4 channel status registers (csrn) (2/2) tmp19a64c1d tmp19a64(rev1.1)-10-14 10.3.5 source address registers (sarn) (n=0 through 7) 7 6 5 4 3 2 1 0 sarn bit symbol saddr7 saddr6 saddr 5 saddr4 saddr3 saddr2 saddr1 saddr0 (0xffff_e208h) read/write r/w (0xffff_e228h) after reset 0 (0xffff_e248h) function see detailed description. (0xffff_e268h) 15 14 13 12 11 10 9 8 (0xffff_e288h) bit symbol saddr15 saddr 14 saddr13 saddr12 saddr11 saddr10 saddr9 saddr8 (0xffff_e2a8h) read/write r/w (0xffff_e2c8h) after reset 0 (0xffff_e2e8h) function see detailed description. 23 22 21 20 19 18 17 16 bit symbol saddr23 saddr22 saddr21 saddr20 saddr19 saddr18 saddr17 saddr16 read/write r/w after reset 0 function see detailed description. 31 30 29 28 27 26 25 24 bit symbol saddr31 saddr30 saddr29 saddr28 saddr27 saddr26 saddr25 saddr24 read/write r/w after reset 0 function see detailed description. bit mnemonic field name description 31 : 0 saddr source address source address (initial value: 0) specifies the address of the source from which data is transferred using a physical address. this address changes according to the sac and trsiz settings of ccrn and the sacm setting of dtcrn. fig. 10.3.5 source address register (sarn) tmp19a64c1d tmp19a64(rev1.1)-10-15 10.3.6 destination address register (darn) (n=0 through 7) 7 6 5 4 3 2 1 0 darn bit symbol daddr7 daddr6 daddr 5 daddr4 daddr3 daddr2 daddr1 daddr0 (0xffff_e20ch) read/write r/w (0xffff_e22ch) after reset 0 (0xffff_e24ch) function see detailed description. (0xffff_e26ch) 15 14 13 12 11 10 9 8 (0xffff_e28ch) bit symbol daddr15 daddr 14 daddr13 daddr12 daddr11 daddr10 daddr9 daddr8 (0xffff_e2ach) read/write r/w (0xffff_e2cch) after reset 0 (0xffff_e2ech) function see detailed description. 23 22 21 20 19 18 17 16 bit symbol daddr23 daddr22 daddr21 daddr20 daddr19 daddr18 daddr17 daddr16 read/write r/w after reset 0 function see detailed description. 31 30 29 28 27 26 25 24 bit symbol daddr31 daddr30 daddr29 daddr28 daddr27 daddr26 daddr25 daddr24 read/write r/w after reset 0 function see detailed description. bit mnemonic field name description 31 : 0 daddr destination address destin ation address (initial value: 0) specifies the address of the destination to which data is transferred using a physical address. this address changes according to the dac and trsiz settings of ccrn and the dacm setting of dtcrn. fig. 10.3.6 destination address register (darn) tmp19a64c1d tmp19a64(rev1.1)-10-16 10.3.7 byte count registers (bcrn) (n=0 through 7) 7 6 5 4 3 2 1 0 bcrn bit symbol bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 (0xffff_e210h) read/write r/w (0xffff_e230h) after reset 0 (0xffff_e250h) function see detailed description. (0xffff_e270h) 15 14 13 12 11 10 9 8 (0xffff_e290h) bit symbol bc15 bc14 bc13 bc12 bc11 bc10 bc9 bc8 (0xffff_e2b0h) read/write r/w (0xffff_e2d0h) after reset 0 (0xffff_e2f0h) function see detailed description. 23 22 21 20 19 18 17 16 bit symbol bc23 bc22 bc21 bc20 bc19 bc18 bc17 bc16 read/write r/w after reset 0 function see detailed description. 31 30 29 28 27 26 25 24 bit symbol read/write r after reset 0 function bit mnemonic field name description 23 : 0 bc byte count byte count (initial value: 0) specifies the number of bytes of data to be transferred. the address decreases by the number of pieces of data transferred (a value specified by trsiz of ccrn). fig. 10.3.7 byte count register (bcrn) tmp19a64c1d tmp19a64(rev1.1)-10-17 10.3.8 dma transfer control register (dtcrn) (n=0 through 7) 7 6 5 4 3 2 1 0 dtcrn bit symbol dacm sacm (0xffff_e218h) read/write r r/w r/w (0xffff_e238h) after reset 0 0 0 0 0 0 0 (0xffff_e258h) function see detailed description. see detailed description. (0xffff_e278h) 15 14 13 12 11 10 9 8 (0xffff_e298h) bit symbol (0xffff_e2b8h) read/write r (0xffff_e2d8h) after reset 0 (0xffff_e2f8h) function 23 22 21 20 19 18 17 16 bit symbol read/write r after reset 0 function 31 30 29 28 27 26 25 24 bit symbol read/write r after reset 0 function bit mnemonic field name description 5 : 3 dacm destination address count mode destination address count mode specifies the count mode of the destination address. 000: counting begins from bit 0 001: counting begins from bit 4 010: counting begins from bit 8 011: counting begins from bit 12 100: counting begins from bit 16 101: setting prohibited 110: setting prohibited 111: setting prohibited 2 : 0 sacm source address count mode source address count mode specifies the count mode of the source address. 000: counting begins from bit 0 001: counting begins from bit 4 010: counting begins from bit 8 011: counting begins from bit 12 100: counting begins from bit 16 101: setting prohibited 110: setting prohibited 111: setting prohibited fig. 10.3.8 dma transfer control register (dtcrn) tmp19a64c1d tmp19a64(rev1.1)-10-18 10.3.9 data holding register (dhr) 7 6 5 4 3 2 1 0 dhr bit symbol dot7 dot6 dot5 dot4 dot3 dot2 dot1 dot0 (0xffff_e30ch) read/write r/w after reset 0 function see detailed description. 15 14 13 12 11 10 9 8 bit symbol dot15 dot14 dot13 dot12 dot11 dot10 dot9 dot8 read/write r/w after reset 0 function see detailed description. 23 22 21 20 19 18 17 16 bit symbol dot23 dot22 dot21 dot20 dot19 dot18 dot17 dot16 read/write r/w after reset 0 function see detailed description. 31 30 29 28 27 26 25 24 bit symbol dot31 dot30 dot29 d ot28 dot27 dot26 dot25 dot24 read/write r/w after reset 0 function see detailed description. bit mnemonic field name description 31 : 0 dot data on transfer data on transfer (initial value: 0) data that is read from the source in a dual-address data transfer mode. fig. 10.3.9 data holding register (dhr) tmp19a64c1d tmp19a64(rev1.1)-10-19 10.4 functions 10.4.1 overview the dmac is a 32-bit dma controller capable of transferring data in a system using the tx19a processor core at high speeds without routing data via the core. (1) source and destination the dmac handles data transfers from memory to memory and between memory and an i/o device. a device from which data is transferred is called a source device and a device to which data is transferred is called a destination device. both memory and i/o devices can be designated as a source or destination device. the dmac supports data transfers from memory to i/o devices, from i/o devices to memory, and from memory to memory, but not between i/o devices. the differences between memory and i/o devi ces are in the way they are accessed. when accessing an i/o device, the dmac asserts a dack n signal. because there is only one line per channel that carries a dackn signal, the number of i/o devices accessible during data transfer is limited to one. therefore, data cannot be transferred between i/o devices. an interrupt factor can be attached to a transfer request to be sent to the dmac. if an interrupt factor is generated, the interrupt controller (intc) issues a request to the dmac (the tx19a processor core is not notified of the interrupt re quest. for details, see description on interrupts.). the request issued by the intc is cleared by th e dackn signal. therefore, if an i/o device is designated as a device to which data is to be tr ansferred, a request made to the dmac is cleared after completion of the data transfer (transfer of the amount of data specified by trsiz). on the other hand, during memory-to-memory transfers, the dackn signal is asserted only when the number of bytes transferred (value set in the bcrn register) becomes "0." therefore, one transfer request allows data to be transferred successively without a pause. for example, if data is transferre d between a internal i/o and the internal (external) memory of the tmp19a64, a request made by the internal i/o to the dmac is cleared after completion of each data transfer and the transfer operation is always put in a standby mode for the next transfer request if the number of bytes transferred (value set in the bcrn register) does not become "0." therefore, the dma transfer operation continues until the value of the bcrn register becomes "0." (2) bus control arbitration (bus arbitration) in response to a transfer request made inside the dmac, the dmac reques ts the tx19a processor core to arbitrate bus control au thority. when a response signal is returned from the core, the dmac acquires bus control authority and executes a data transfer bus cycle. in acquiring bus control for the dmac, use or nonuse of the data bus of the tx19a processor core can be specified; specifically either snoop mode or non-snoop mode can be specified for each channel by using bit 11 (sreq) of the ccrn register. there are cases in which the tx19a processor core requests the release of bus control authority. whether or not to respond to this request can be specified for each channel by using the bit 10 (relen) of the ccrn register. however, this function can only be used in non-snoop mode (greq). in snoop mode (sreq), the tx19a processor core cannot request the release of bus control and, therefore, this function cannot be used. when there are no more transfer requests , the dmac releases control of the bus. tmp19a64c1d tmp19a64(rev1.1)-10-20 (note 1) when the dmac is acquiring bus control authority, nmi is put on hold. (note 2) do not bring the tx19a to a halt when the dmac is in operation. (note 3) to put the tx19a into idle (doze) mode when the snoop function is being used, you must first stop the dmac. tmp19a64c1d tmp19a64(rev1.1)-10-21 (3) transfer request modes two transfer request modes are used for the dmac : an internal transfer request mode and an external transfer request mode. in the internal transfer reques t mode, a transfer request is generated inside the dmac. setting a start bit (str bit of the channel control register ccrn) in the internal register of the dmac to "1" generates a transfer request, and th e dmac starts to transfer data. in the external transfer request mode, after a start bit is set to "1," a transfer request is generated when a transfer request signal intdreqn output by the intc is input, or when a transfer request signal dreqn output by an external device is input. for the dmac, two modes are provided: the level mode in which a transfer request is generate d when the "l" level of the intdreqn signal is detected and a mode in which a transfer request is generated when the falling edge or "l" level of the dreqn signal is detected. (4) address mode for the dmac of the tmp19a64, only one address mode is provided: a dual address mode. a single address mode is not available. in the dual address mode, data can be transferred from memory to memory and between memory and an i/o device. source and destination device addresses are output by the dmac. to access an i/o device, the dmac asserts the dackn signal. in the dual address mode, two bus operations, a read and a write, are executed. data that is read from a source devi ce for transfer is first put into the data holding register (dhr) inside the dmac and then written to a destination device. (5) channel operation the dmac has eight channels (channels 0 through 7). a channel is activated and put into a standby mode by setting a start (str) bit in the channel control register (ccrn) to "1." if a transfer request is generated when a channel is in a standby mode, the dmac acquires bus control authority and transfers data . if there is no transfer reques t, the dmac releases bus control authority and goes into a standby mode. if data transfer has been completed, a channel is put in an idle state. data transfer is completed either norm ally or abnormally (e.g. occurrence of errors). an interrupt signal can be generated upon completion of data transfer. fig. 10.4.1 shows the state tran sitions of channel operation. fig. 10.4.1 channel operation state transition start transfer completed idle wait transfer bus control authority acquired bus control authority not acquired bus control authority not acquired bus control authority acquired tmp19a64c1d tmp19a64(rev1.1)-10-22 (6) combinations of transfer modes the dmac can transfer data by comb ining each transfer mode as follows: transfer request edge/level address mode transfer devices internal ? memory memory memory memory memory i/o external "l" level (intdreqn) i/o memory "l" level (dreqn) memory memory memory i/o external falling edge (dreqn) dual i/o memory (7) address changes address changes are broadly classified into three ty pes: increases, decreases and fixed. the type of address change can be specified for each source an d destination address by using sac and dac in the ccrn register. for a memory device, an increase, decrease or fixed can be specified. for an i/o device, however, only "fixed" can be specified. if an i/o device is selected as a source or destination device, sac or dac in the ccr n register must be set to "fixed." if address increase or decrease is selected, the bit position for counting can be specified using sacm or dacm in the dtcrn register. to speci fy the bit position for counting a source address, sacm must be used, while dacm must be used to specify the bit position for a destination address. any of the bits 0, 4, 8, 12 and 16 can be specified as the bit position for address counting. if 0 is selected, an address normally increases or decreases. by selecting bits 4, 8, 12 or 16, it is possible to increase or decrease an address irregularly. examples of address changes are shown below. example 1: monotonic increase for a source devi ce and irregular increase for a destination device sac: address increase dac: address increase trsiz: transfer unit 32 bits source address: 0xa000_1000 destination address: 0xb000_0000 sacm: 000 counting to begin from bit 0 of the address counter dacm: 001 counting to begin from bit 4 of the address counter source destination 1st 0xa000_1000 0xb000_0000 2nd 0xa000_1001 0xb000_0010 3rd 0xa000_1002 0xb000_0020 4th 0xa000_1003 0xb000_0030 ? ? tmp19a64c1d tmp19a64(rev1.1)-10-23 example 2: irregular decrease fo r a source device and monotonic d ecrease for a destination device sac: address decrease dac: address decrease trsiz: transfer unit 16 bits source address: initial value 0xa000_1000 destination address: 0xb000_0000 sacm: 010 counting to begin from bit 8 of the address counter dacm: 000 counting to begin from bit 0 of the address counter source destination 1st 0xa000_1000 0xb000_0000 2nd 0x9fff_ff00 0xafff_fffe 3rd 0x9fff_fe00 0xafff_fffc 4th 0x9fff_fd00 0xafff_fffa ? ? 10.4.2 transfer request for the dmac to transfer data, a transfer request mu st be issued to the dmac. there are two types of transfer request: an in ternal transfer request and an external tr ansfer request. either of these transfer requests can be selected and specified for each channel. whichever is selected, the dmac acquires bus contro l authority and starts to transfer data if the transfer request is generated after the start of channel operation. ? internal transfer request if the str bit of ccr is set to "1" when the exr bit of ccrn is "0," a transfer request is generated immediately. this transfer request is called an internal transfer request. the internal transfer request is valid until the chan nel operation is completed. therefore, data can be transferred continuously if either of two events shown below does not occur: * a transition to a channel of higher priority * a shift of bus control authority to another bus master of higher priority in the case of the internal transfer request, data can only be transferred from memory to memory. ? external transfer request if the exr bit of ccrn is "1," setting the str bit of ccr to "1" allows a channel to go into a standby mode. the intc or an external device then generates the intdreqn or dreqn signal for this channel to notify the dmac of a transfer request, and a transfer request is generated. this transfer request is called an exte rnal transfer request. in the case of the external transfer request, data can be transferred from memory to memory and between memory and an i/o device. the tmp19a64 recognizes the tr ansfer request signal by detecting the "l" level of the intdreqn signal or by detecting the falling edge or "l" level of the dreqn signal. the unit of data to be transferred in response to one transfer request is specified in the trsiz field of ccrn, and 32, 16 or 8 bits can be selected. transfer requests using intdreqn and dreqn are described in detail on the next page. tmp19a64c1d tmp19a64(rev1.1)-10-24 c a transfer request made by the interrupt controller (intc) a transfer request made by the interrupt cont roller is cleared using the dackn signal. this dackn signal is asserted only if a bus cycle for an i/o device or the number of bytes (value set in the bcrn register) transferred from memory to memory becomes "0." therefore, if data is transferred between memory and an i/o device, the amount of data specified by trsiz is transferred only once because intdreqn is clear ed upon completion of one data transfer from one transfer request. on the other hand, if data is transferred from memory to memory, it can be transferred successively in response to a transfer request because intdreqn is not cleared until the number of bytes transferred (value set in the bcrn register) becomes "0." note that if the dmac acknowle dges an interrupt set in intdreqn and if this interrupt is cleared by the intc before dma transfer begi ns, there is a possibility that dma transfer might be executed once after the interrupt is cleared, depending on the timing. d a transfer request made by an external device external pins (dreq2 and dreq3) are internally wired to allow them to function as pins of the port f and port j. these pins can be sel ected by setting the function control registers pffc and pjfc to an appropriate setting. if both po rts are set to use the dmac function, the port f is given priority in using the dmac function. in the edge mode, the dreqn signal must be d easserted and then asserted for each transfer request to create an effective edge. in the le vel mode, however, successive transfer requests can be recognized by maintaining an effective le vel. in memory-to-memory transfer, only the "l" level mode can be used. in i/o-to-memory transfer, only the falling edge mode can be used. ? level mode in the level mode, the dmac detects the "l" level of the dreqn signal upon the rising of the internal system clock. if it detects the "l" level of the dreqn signal when a channel is in a standby mode, it goes into transfer mode and st arts to transfer data. to use the dreqn signal at an active level, the pose bit (bit 13) of the ccrn register must be set to "0." the dackn signal is active at the "l" level, as in the case of the dreqn signal. if an external circuit asserts the dreqn signal , the dreqn signal must be maintained at the "l" level until the dackn signal is asserted. if the dreqn signal is deasserted before the dackn signal is asserted, a transf er request may not be recognized. if the dreqn signal is not at the "l" level, the dmac judges that there is no transfer request, and starts a transfer operation for other channels or releases bus control authority and goes into a standby mode. the unit of a transfer request is specified in the trsiz field ( tmp19a64c1d tmp19a64(rev1.1)-10-25 dreqn a [31:1] dackn transfer data fig. 10.4.2.1 transfer request timing (level mode) ? edge mode in the edge mode, the dmac detects the falling edge of the dreqn signal. if it detects the falling edge of the dreqn signal upon the rising of the internal system clock (the case in which the "l" level is detected upon the rising of the system clock although it was not detected upon the rising of the previous system clock) when a channel is in a standby mode, it judges that there is a transfer re quest, goes into transfer mode, and starts a transfer operation. to detect the falling edge of the dreqn signal, the pose bit (bit 13) of the ccrn register must be set to "0," and the lev bit (bit 12) must also be set to "0." the dackn signal is active at the "l" level. if the falling edge of the dreqn signal is detected after the dackn signal is asserted, the next data is transferred without a pause. if there is no falling edge of the dreqn signal after the dackn signal is asserted, the dmac judges that there is no transfer reque st, and starts a transfer operation for other channels or goes into a standby mode after releasing bus control authority. the unit of a transfer request is specified in the trsiz field ( tmp19a64c1d tmp19a64(rev1.1)-10-26 10.4.3 address mode in the address mode, whether the dmac executes data transfers by outputting ad dresses to both source and destination devices or it does by outputting addresses to either a source device or a destination device is specified. the former is called the dual addr ess mode, and the latter is called the single address mode. for tmp19a64, only the dual address mode is available. in the dual address mode, the dmac first performs a read of the source device by storing the data output by the source device in one of its registers (d hr). it then executes a write on the destination device by writing the stored data to the de vice, thereby completing the data transfer. fig. 10.4.3.1 basic concept of data transfer in the dual address mode the unit of data to be transferred by the dmac is the amount of data (32, 16 or 8 bits) specified in the trsiz field of the ccrn. one unit of data is transfer red each time a transfer request is acknowledged. in the dual address mode, the unit of data is read from the source device, put into the dhr and written to the destination device. access to memory takes place when the specified unit of data is transferred. if access to external memory takes place, 16-bit access takes place twice if the unit of data is set to 32 bits and if the bus width set in the cs wait controller is 16 bits. likewise, if the unit of data is set to 32 bits and if the bus width set in the cs wait controller is 8 bits, 8-bit access takes place four times. if data is to be transferred from memory to an i/o device or from an i/o device to memory, the unit of data to be transferred must be specified and, at the same time, the bus width of an i/o device (device port size) must be specified in the dps field of the ccrn (32, 16 or 8 bits). dmac destination device data data bus c address d d c address bus source device tmp19a64c1d tmp19a64(rev1.1)-10-27 if the unit of data to be transferred is equal to a de vice port size, a read or write is executed once for an i/o device. if a device port size is smaller than the unit of data to be transferred, the dmac performs a read or write for an i/o device more than once. for example, if the unit of data to be transferred is 32 bits and if data is transferred from an i/o device whose device port size is 8 bits to memory, 8 bits of data are read from an i/o device four consecutive times and stored in the dhr. this 32-bit data is then written to memory all at once (twice if the data is written to external memory and if the bus width is 16 bits). an address change occurs by the amount defined as the unit of data to be transferred. the bcrn value also changes by the same amount. a device port size must not be larger than the unit of data to be transferred. the relationships between units of data to be transferred and device port sizes are summarized in table 10.4.3.2. table 10.4.3.2 units of data to be transferred and device port sizes (dual address mode) trsiz dps bus operations performed on i/o device 0x (32 bits) 0x (32 bits) once 0x (32 bits) 10 (16 bits) twice 0x (32 bits) 11 (8 bits) 4 times 10 (16 bits) 0x (32 bi ts) setting prohibited 10 (16 bits) 10 (16 bits) once 10 (16 bits) 11 (8 bits) twice 11 (8 bits) 0x (32 bi ts) setting prohibited 11 (8 bits) 10 (16 bi ts) setting prohibited 11 (8 bits) 11 (8 bits) once tmp19a64c1d tmp19a64(rev1.1)-10-28 10.4.4 channel operation a channel is activated if the str bit of the ccrn of a channel is set to "1." if a channel is activated, an activation check is conducted and if no error is detected, the channel is put into a standby mode. if a transfer request is generated when a channel is in a standby mode, the dmac acquires bus control authority and starts to transfer data. channel operation is completed either normally or a bnormally (forced termination or occurrence of an error). either normal comple tion or abnormal completion is indicated to the csrn. start of channel operation a channel is activated if the str bit of the ccrn is set to "1." when a channel is activated, a conf iguration error check is conducted and if no error is detected, the channel is put into a standby mode. if an error is detected, the channel is deactivated and this state of completion is considered to be abnormal completion. when a cha nnel goes into a standby mode, the act bit of the csrn of that channel becomes "1." if a channel is programmed to start operation in response to an intern al transfer request, a transfer request is generated immediately and the dmac acquires bus control authority and starts to transfer data. if a channel is programmed to start operation in response to an external transfer request, the dmac acquires bus control authority after intdreqn or dreqn is asserted, and starts to transfer data. completion of channel operation a channel completes operation either normally or abnormally and either one of these states is indicated to the csrn. if an attempt is made to set the str bit of the ccrn register to "1" when the nc or abc bit of the csrn register is "1," channel operation does not start and the completion of operation is considered to be abnormal completion. normal completion channel operation is considered to have been completed normally in the case shown below. for channel operation to be considered to have been completed normally, the transfer of a unit of data (value specified in the trsiz field of ccrn) must be completed successfully. ? when the contents of bcrn become 0 and data transfer is completed abnormal completion cases of abnormal completion of dmac operation are as follows: ? completion due to a configuration error a configuration error occurs if there is a mi stake in the dma transfer setting. because a configuration error occurs before data transfer begins, values specified in sarn, darn and bcrn remain the same as when they were initially specified. if channel operation is completed abnormally due to a configuration error, the abc bit of the csrn is set to "1," along with the conf bit. causes of a configuration error are as follows: ? both sio and dio were set to "1." ? the str bit of ccrn was set to "1" when the nc bit or abc bit of csrn was "1." ? a value that is not an integer multiple of the unit of data was set for bcrn. ? a value that is not an integer multiple of the unit of data was set for sarn or darn. ? a prohibited combination of a device port size and a unit of data to be transferred was set. ? the str bit of ccrn was set to "1" when the bcrn value was "0." tmp19a64c1d tmp19a64(rev1.1)-10-29 ? completion due to a bus error if the dmac operation has been completed abnormally due to a bus error, the abc bit of csrn is set to "1" and the bes or bed bit of csrn is set to "1." ? a bus error was detected during data transfer. (note) if the dmac operation has been completed abnormally due to a bus error, bcr, sar and dar values cannot be guaranteed. if a bus error persists, refer to 21. "list of functional registers" which appear later in this document. 10.4.5 order of priority of channels concerning the eight channels of the dmac, the smaller the channel number assigned to each channel, the higher the priority. if a transfer request is gene rated to channels 0 and 1 simultaneously, a transfer request for channel 0 is processed with higher pr iority and the transfer operation is performed accordingly. when the transfer request for channel 0 is cleared, the transfer operation for channel 1 is performed if the transfer re quest still exists (an internal transfer reque st is retained if it is not cleared. the interrupt controller retains an external transfer request if the active state for an interrupt request assigned to dma requests in the interrupt controller is set to edge mode. however, the interrupt controller does not retain an external transfer request if the active state is set to level mode. if the active state for an interrupt request assigned to dma requests in the interrupt controller is set to level mode, it is necessary to continue assert ing the interrupt request signal). if a transfer request is generated when data is being transferred through channel 1, a channel transition occurs at channel 0, that is, data transfer through channel 1 is temporarily suspended and data transfer through channel 0 is started. when the transfer request for channel 0 is cleared, data transfer through channel 1 resumes. channel transitions occur upon the completion of data transfers (when the writin g of all data in the dhr has been completed). interrupts upon completion of a channel operation, the dmac can generate interrupt requests (intdman: dma transfer completion interrupt) to the tx19a processor core with two types of interrupts available: a normal completion interrupt and an abnormal completion interrupt. ? normal completion interrupt if a channel operation is completed normally, the nc bit of csrn is set to "1." if a normal completion interrupt is authorized for the ni en bit of the ccrn, the dmac requests the tx19a processor core to authorize an interrupt. ? abnormal completion interrupt if a channel operation is completed abnormally, the abc bit of csrn is set to "1." if an abnormal completion interrupt is authorized for the abien bit of the ccrn, the dmac requests the tx19a processor core to authorize an interrupt. tmp19a64c1d tmp19a64(rev1.1)-10-30 10.5 timing diagrams dmac operations are synchronous to the rising edges of the internal system clock. 10.5.1 dual address mode ? memory-to-memory transfer fig. 10.5.1.1 shows an example of the timing with which 16-bit data is transferred from one external memory (16-bit width) to another (16-bit width). data is actually transferred successively until bcrn becomes "0." tsys /rd /cs0 a[23:0] d[15:0] /cs1 /wr,/hwr ` data data fig. 10.5.1.1 dual address mode (memory-to-memory) ? memory-to-i/o device transfer fig. 10.5.1.2 shows an example of the timing w ith which data is transferred from memory to an i/o device if the unit of data to be transferred is set to 16 bits and if the device port size is set to 8 bits. tsys data a[23:0] /cs0 /cs1 /rd /wr d[15:0] data data ` fig. 10.5.1.2 dual address mode (memory-to-i/o device) read write read write write tmp19a64c1d tmp19a64(rev1.1)-10-31 ? i/o device-to-memory transfer fig. 10.5.1.3 shows an example of the timing with which data is transferred from an i/o device to memory if the unit of data to be transferred is set to 16 bits and if the device port size is set to 8 bits. tsys data ` ` data d[15:0] data /wr /cs1 /rd /cs0 a[23:0] fig. 10.5.1.3 dual address mode (i/o device-to-memory) read read write tmp19a64c1d tmp19a64(rev1.1)-10-32 10.5.2 dreqn-initiated transfer mode ? data transfer from internal ra m to external memory (multiplexed bus, 5-wait insertion, level mode) fig. 10.5.2.1 shows two timing cycles in which 16-bit data is transferred twice from internal ram to external memory (16-bit width). (7+)? 5 ???? add ad[15:0] /rd add /dreqn /dackn a[23:16] /csn ale /wr /hwr r/w_ add data data fig. 10.5.2.1 level mode (from inte rnal ram to external memory) ? data transfer from external memory to intern al ram (multiplexed bus, 5-wait insertion, level mode) fig. 10.5.2.2 shows two timing cycles in which 16-bit data is transferred twice from external memory (16-bit width) to internal ram. (7+)? 5 ???? /csn r/w_ /dreqn /dackn ale a[23:16] /rd /wr ad[15:0] add /hwr add data add data fig. 10.5.2.2 level mode (from exte rnal memory to internal ram) internal system clock (7+ ) clock 5 waits internal system clock (7+ ) clock 5 waits tmp19a64c1d tmp19a64(rev1.1)-10-33 ? data transfer from internal ram to external memory (separate bus, 5-wait insertion, level mode) fig. 10.5.2.3 shows two timing cycles in which 16-bit data is transferred twice from internal ram to external memory (16-bit width). (7+)? 5 ???? /dreqn /dackn /hwr r/w_ /wr a[23:0] d[15:0] /rd /csn fig. 10.5.2.3 level mode (inter nal ram to external memory) ? data transfer from external memory to inte rnal ram (separate bus, 5-wait insertion, level mode) fig. 10.5.2.4 shows two timing cycles in which 16-bit data is transferred twice from external memory (16-bid width) to internal ram. (7+)? 5 ???? /dreqn /dackn a[23:0] d[15:0] /rd /wr /hwr /csn r/w_ fig. 10.5.2.4 level mode (from exte rnal memory to internal ram) internal system clock (7+ ) clock 5 waits internal system clock (7+ ) clock 5 waits tmp19a64c1d tmp19a64(rev1.1)-10-34 ? data transfer from internal ra m to external memory (multiplexed bus, 5-wait insertion, edge mode) fig. 10.5.2.5 shows one timing cycle in which 16-bit data is transferred once from internal ram to external memory (16-bit width). (7+)? 5 ???? ad[15:0] /csn r/w_ /rd /wr /hwr a[23:16] /dreqn /dackn ale add add data fig. 10.5.2.5 edge mode (from inte rnal ram to external memory) ? data transfer from external memory to intern al ram (multiplexed bus, 5-wait insertion, edge mode) fig. 10.5.2.6 shows one timing cycle in which 16-bit data is transferred once from external memory (16-bit width) to internal ram. (7+)? 5 ???? /dreqn /dackn ale a[23:16] ad[15:0] /csn r/w_ /rd /wr /hwr add add data fig. 10.5.2.6 edge mode (from exte rnal memory to internal ram) internal system clock (7+ ) clock 5 waits internal system clock ( 7+ ) clock 5 waits tmp19a64c1d tmp19a64(rev1.1)-10-35 ? data transfer from internal ra m to external memory (separat e bus, 5-wait insertion, edge mode) fig. 10.5.2.7 shows one timing cycle in which 16-bit data is transferred once from internal ram to external memory (16-bit width). (7+)? 5 ???? /dreqn /dackn a[23:0] d[15:0] /rd /wr /hwr /csn r/w_ fig. 10.5.2.7 edge mode (from inte rnal ram to external memory) ? data transfer from external memory to intern al ram (separate bus, 5-wait insertion, edge mode) fig. 10.5.2.8 shows one timing cycle in which 16-bit data is transferred once from external memory (16-bit width) to internal ram. (7+)? 5 ???? /dreqn /dackn a[23:0] d[15:0] /rd /wr /hwr /csn r/w_ fig. 10.5.2.8 edge mode (from exte rnal memory to internal ram) internal system clock ( 7+ ) clock 5 waits internal system clock ( 7+ ) clock 5 waits tmp19a64c1d tmp19a64(rev1.1)-10-36 10.6 case of data transfer the settings described below relate to a case in which serial data received (scnbu f) is transferred to the internal ram by dma transfer. dma (ch.0) is used to transfer data. the dma0 is activated by a receive inte rrupt generated by sio1. tmp19a64c1d tmp19a64(rev1.1)-11-1 11. 16-bit timer/event counters (tmrbs) each of the eleven channels (tmrb0 through tmrba) has a multi-functional, 16-bit timer/event counter. tmrbs operate in the followi ng four operation modes: ? 16-bit interval timer mode ? 16-bit event counter mode ? 16-bit programmable square-wave output (ppg) mode ? two-phase pulse input counter mode (quad-speed and tmrba) the use of the capture function allows tmrbs to operate in three other modes: ? frequency measurement mode ? pulse width measurement mode ? time difference measurement mode each channel consists of a 16-bit up-counter, two 16-bit timer registers (one of which is double-buffered), two 16-bit capture registers, two comparators, a capture inpu t control, a timer flip-flop and its associated control circuit. each channel (tmrb0 through tmrba) functions independently and while the channels operate in the same way, there are differences in their specifications as show n in table 11.1 and the two-phase pulse count function. therefore, the operational descriptions here are for tmrb0 only and for the two-phase pulse count function tmrba only. tmp19a64c1d tmp19a64(rev1.1)-11-2 table 11.1 differences in the s pecifications of tmrb modules channel specification tmrb0 tmrb1 tmrb2 tmrb3 tmrb4 tmrb5 external clock/ capture trigger input pins tb0in0 (shared with pa0) tb0in1 (shared with pa1) tb1in0 (shared with pa3) tb1in1 (shared with pa4) ? ? ? ? external pins timer flip-flop output pin tb0out (shared with pa2) tb1out (shared with pa5) tb2out (shared with pa6) tb3out (shared with pa7) tb4out (shared with pb0) tb5out (shared with pb1) internal signals timer for capture triggers tb9out tb9out tb9out tb9out tb9out tb3out timer run register tb0run tb1run tb2run tb3run tb4run tb5run timer control register tb0cr tb1cr tb2cr tb3 cr tb4cr tb5cr timer mode register tb0mod tb 1mod tb2mod tb3mod tb4mod tb5mod timer flip-flop control register tb0ffcr tb1ffcr tb2ffcr tb3 ffcr tb4ffcr tb5ffcr timer status register tb0st tb1st tb2st tb3st tb4st tb5st timer uc preset register tb0ucl tb0uch tb1ucl tb1uch tb2ucl tb2uch tb3ucl tb3uch tb4ucl tb4uch tb5ucl tb5uch timer register tb0rg0l tb0rg0h tb0rg1l tb0rg1h tb1rg0l tb1rg0h tb1rg1l tb1rg1h tb2rg0l tb2rg0h tb2rg1l tb2rg1h tb3rg0l tb3rg0h tb3rg1l tb3rg1h tb0rg0l tb4rg0h tb4rg1l tb4rg1h tb5rg0l tb5rg0h tb5rg1l tb5rg1h register names capture register tb0cp0l tb0cp0h tb0cp1l tb0cp1h tb1cp0l tb1cp0h tb1cp1l tb1cp1h tb2cp0l tb2cp0h tb2cp1l tb2cp1h tb3cp0l tb3cp0h tb3cp1l tb3cp1h tb4cp0l tb4cp0h tb4cp1l tb4cp1h tb5cp0l tb5cp0h tb5cp1l tb5cp1h channel specification tmrb6 tmrb7 tmrb8 tmrb9 tmrba external clock/ capture trigger input pins ? ? ? ? tbain0 (shared with pb6) tbain1 (shared with pb7) external pins timer flip-flop output pin tb6out (shared with pb2) tb7out (shared with pb3) tb8out (shared with pb4) tb9out (shared with pb5) ? internal signals timer for capture triggers tb3out tb3out tb3out tb3out tb3out timer run register tb6run tb7run tb8run tb9run tbarun timer control register tb6 cr tb7cr tb8cr tb9cr tbacr timer mode register tb6m od tb7mod tb8mod tb9mod tbamod timer flip-flop control register tb6 ffcr tb7ffcr tb8ffcr tb9ffcr tbaffcr timer status register tb6st tb7st tb8st tb9st tbast timer uc preset register tb6ucl tb6uch tb7ucl tb7uch tb8ucl tb8uch tb9ucl tb9uch tbaucl tbauch timer register tb6rg0l tb6rg0h tb6rg1l tb6rg1h tb7rg0l tb7rg0h tb7rg1l tb7rg1h tb8rg0l tb8rg0h tb8rg1l tb8rg1h tb9rg0l tb9rg0h tb9rg1l tb9rg1h tbarg0l tbarg0h tbarg1l tbarg1h register names capture register tb6cp0l tb6cp0h tb6cp1l tb6cp1h tb7cp0l tb7cp0h tb7cp1l tb7cp1h tb8cp0l tb8cp0h tb8cp1l tb8cp1h tb9cp0l tb9cp0h tb9cp1l tb9cp1h tbacp0l tbacp0h tbacp1l tbacp1h tmp19a64c1d tmp19a64(rev1.1)-11-3 11.1 block diagram of each channel internal data bus internal data bus run/ clear match detection 16-bit comparator (cp0) 16-bit timer register tb0rg0h/l 16-bit comparator (cp1) register buffer 0 16-bit timer register tb0rg1h/l match detection count clock tb0mod tmp19a64c1d tmp19a64(rev1.1)-11-4 internal data bus internal data bus run/ clear match detection 16-bit comparaotr (cp0) 16-bit timer register tbarg0h/l 16-bit comparator (cp1) register buffer 0 16-bit timer register tbarg1h/l match detection count clock tbamod tmp19a64c1d tmp19a64(rev1.1)-11-6 table 11.2.1 prescaler output clock resolutions @fc = 54mhz prescaler output clock resolutions release peripheral clock tmp19a64c1d tmp19a64(rev1.1)-11-8 11.2.4 capture registers (tb0cp0h/l, tb0cp1h/l) to read data from the capture register, use 1-byte data transfer instruction twice and make sure that reading is performed in the order of lo w-order bits followed by high-order bits . (don?t use 2-byte transfer instruction for data reading.) 11.2.5 capture this is a circuit that controls the timing of latching values from the uc0 up-counter into the tb0cp0 and tb0cp1 capture registers. the timing with which to latch data is specified by tb0mod tmp19a64c1d tmp19a64(rev1.1)-11-9 11.3 register description tmrbn run register (n=0 through 9) 7 6 5 4 3 2 1 0 bit symbol tbnrde i2tbn tbnpru n tbnrun read/write r/w r/w r/w r/w r/w r/w r r/w after reset 0 0 0 function double buffering 0: disable 1: enable write "0." write "0." write "0." idle 0: stop 1: operate timer run/stop control 0: stop & clear 1: count * the first bit can be read as "0." |