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data sheet (v6.3) 2006 aug 16 to improve design and/or performance, avant electronics may make changes to its products. please contact avant electronics for the latest versions of its products d a t a sh eet sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 dot-matrix stn lcd driver with 32-row x 80-column display data memory
2006 aug 16 2 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 1general 1.1 description the sbn1661g_x is a series of stn lcd segment/c ommon drivers. the series has four members: ? the sbn1661g_m18, ? the sbn1661g_m02, ? the sbn0080g_s18, and ? the sbn0080g_s02. both the sbn1661g_m18 and the sbn1661g_m02 can dr ive 16 commons and 61 segments and can be used as master in a master-slave connection. they both have 32-ro w x 80-column display data memory. functionally, their only difference is that the sbn1661g_m18 has an on-chip rc-t ype oscillator and can provide clock to slave, while the sbn1661g_m02 does not have an on-chip oscill ator and needs external clock source. both the sbn0080g_s18 and the sbn0080g_s02 are purely segm ent drivers. they do not have common outputs and are used for segment expansion in a master-slave connect ion. both devices need either a master or an external clock source to provide clock. the only difference bet ween these two chips is their operating frequency. the sbn0080g_s18?s operating frequency is 18 khz, whil e the sbn0080g_s02?s operating frequency is 2khz. all four devices have on-chip display data memory of 32-rows x 80-columns, for storing di splay data. dot-matrix mapping method is used to drive the lcd panel. therefore, a bit of the display data memory corresponds to a pixel on the lcd panel. segment drivers provide displa y data to the lcd panel and common drivers provide row-scanning signal. all four devices have a set of internal registers. these inte rnal registers must be properly programmed to ensure proper operation of the devices. display on the lcd panel is controlled by a host microc ontroller. all four devices communicate with the host microcontroller via data bus and control bus. the data bus is 8-bit wide. the contro l bus are read, write, and chip select. the host microcontroller can perform read/write operations to the internal registers and display data ram of all four devices. a wide variety of microcontrollers can easily interface with the devices, as the devices can accept both 80-type interface timing and 68-type interface timing. t he selection of interface ti ming is via the dual-function reset/if pin.
2006 aug 16 3 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 1.2 features ? four members of the sbn1661g_x series: ? the sbn1661g_m18, ? the sbn1661g_m02, ? the sbn0080g_s18, and ? the sbn0080g_s02 ? 16 common, 61 segment stn lcd driv er (the sbn1661g_m18 and the sbn1661g_m02). ? 80 segment stn lcd driver for expanding segm ent number (the sbn0080g_s18 and the sbn0080g_s02). ? on-chip display data memory: 32-ro w x 80-column (totally 2560 bits). ? dot matrix mapping between the display data memory bit and lcd pixel. ? a ?0? stored in the display data memory bit corresponds to an off-pixel on the lcd panel; a ?1? stored in the display data memory bit corresponds to an on-pixel on the lcd panel. ? 5-level external lcd bias. ? display duty cycle: 1/16, 1/32 for all four devices. ? two types of interface timing with a host microcontroller: the 80-type microcontroller an d the 68-type microcontroller. ? dual function reset/if input for chip reset a nd selection of microcontroller interface timing. ? 8-bit parrallel data bus; read, write, chip select control bus. ? a set of internal registers: display on/off, display star t line, static drive on/off, memory page address, memory column address, duty selection, memo ry column/segment mapping, and status. ? display data read/write commands and software reset command. ? read-modify-write command for block data transfer from the host microcontroller to the display data memory. ? power-saving mode. ? on-chip rc-type oscillator, requiring onl y an external resistor (the sbn1661g_m18). ? operating voltage range (v dd ): 2.7 ~ 5.5 volts. ? lcd bias voltage (v lcd =v5-v dd ): -13 volts (max.). ? operating frequency range: 2 khz, 18 khz. ? operating temperature range: -20 to +75 c. ? storage temperature range: -55 to +125 c.
2006 aug 16 4 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 1.3 ordering information table 1 product types table 2 ordering information product name clock frequency number of segment driver number of common driver duty cycle on-chip external sbn1661g_m18 18 khz 18 khz 61 16 1/16, 1/32 sbn1661g_m02 2 khz sbn0080g_s18 18 khz 80 0 sbn0080g_s02 2 khz product type description sbn1661g_m18-lqfpg lqfp100 pb-free package. sbn1661g_m18-qfpg qfp100 pb-free package. sbn1661g_m18-lqfp lqfp100 general package. sbn1661g_m18-qfp qfp100 general package. sbn1661g_m18-d tested die. sbn1661g_m02-lqfpg lqfp100 pb-free package. sbn1661g_m02-qfpg qfp 100 pb-free package. sbn1661g_m02-lqfp lqfp100 general package. sbn1661g_m02-qfp qfp100 general package. sbn1661g_m02-d tested die. sbn0080g_s18-lqfpg lqfp100 pb-free package. sbn0080g_s18-qfpg qfp100 pb-free package. sbn0080g_s18-lqfp lqfp100 general package. sbn0080g_s18-qfp qfp100 general package. sbn0080g_s18-d tested die. sbn0080g_s02-lqfpg lqfp100 pb-free package. sbn0080g_s02-qfpg qfp100 pb-free package. sbn0080g_s02-lqfp lqfp100 general package. sbn0080g_s02-qfp qfp100 general package. sbn0080g_s02-d tested die.
2006 aug 16 5 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 2 functional block diagram and description 2.1 funtional blo ck diagram (sbn1661g _m18, sbn1661g_m02) fig.1 functional block diagram level shifter mux common counter display data ram buffer 32 row x 80 column (2560 bits) display data ram column address decoder line address decoder display data ram access control display display data read/write control control mapping circuit microcontroller interface db0~db7 c /d e/rd r/w (wr ) osc and command decoder reset/if osc1(cs ) osc2(cl) display on/off register display start line register page address register status register duty select register static drive on/off column address register register timing gen. m/s v5 v4 v3 v2 seg0 v1 seg1 seg59 seg60 com0 com1 com15 fr display control time gen. c/s mappig register output driver high voltage circuit
2006 aug 16 6 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 3 pin(pad) assignment, pad coordinates, signal description 3.1 the sbn1661g_m18 and sbn1661g _m02 pinning diagram (lqfp100) fig.2 the sbn1661g_m18 , the sbn1661g _m02 pin assignment of lqfp100 package. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 32 33 31 com6 com7 com9 com11 com13 com14 seg60 seg59 seg57 seg54 seg53 seg52 seg51 seg50 com8 com10 com12 com15 seg58 seg55 seg56 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 com5 db0 v ss e/rd osc1(cs ) seg0 seg1 seg3 seg4 seg6 seg9 seg10 seg11 seg12 seg13 r/w (wr ) osc2(cl) c /d seg2 seg5 seg8 seg7 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 db1 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 db2 db3 db6 db4 fr v5 v3 reset/if db7 db5 v dd v2 m/s v4 v1 com0 com2 com3 com4 com1 sbn1661g_m18 sbn1661g_m02 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 note: (1) for the sbn1661g_m18, pin 74 is osc1 and pin 75 is osc2. (2) for the sbn1661g_m02, pin 74 is cs and pin 75 is cl. (3) all other pins of both devices have the same pin(pad) assignment. (4) both devices can be used as master or slave, by setting their m/s pin. (master/slave driver)
2006 aug 16 7 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 3.2 the sbn0080g_s18, the sbn 0080g_s02 pinning diagram (lqfp100) fig.3 the sbn0080g_s18, t he sbn0080g_s02 pin assignm ent of lqfp100 package. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 32 33 31 seg70 seg69 seg67 seg65 seg63 seg62 seg60 seg59 seg57 seg54 seg53 seg52 seg51 seg50 seg68 seg66 seg64 seg61 seg58 seg55 seg56 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 seg71 db0 v ss e/rd cs seg0 seg1 seg3 seg4 seg6 seg9 seg10 seg11 seg12 seg13 r/w (wr ) cl c /d seg2 seg5 seg8 seg7 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 db1 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 db2 db3 db6 db4 fr v5 v3 reset/if db7 db5 v dd v2 seg79 seg78 seg77 seg76 seg74 seg73 seg72 seg75 sbn0080g_s18 sbn0080g_s02 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 note: (1) both devices have the same pin(pad) assignment. (2) both devices can be used only as slave segment driver. (slave segment driver)
2006 aug 16 8 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 3.3 the sbn1661g_m18 , sbn1661g_m02 pad placement 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 com7 com3 com2 com1 com0 v1 v4 m/s v2 v3 v5 fr reset/if vdd db7 db6 db5 db4 db3 db2 db1 db0 vss 31 32 33 34 35 36 37 38 39 40 41 42 43 44 seg43 29 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 46 47 48 49 45 50 27 26 25 24 23 22 21 20 19 18 17 16 14 13 12 11 10 9 8 7 6 5 4 3 15 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg55 seg54 seg56 seg57 seg58 seg59 com15 seg60 com14 com13 com12 com11 com10 com9 com8 53 54 55 56 57 58 59 60 61 62 63 64 66 67 68 69 70 71 72 73 74 75 76 77 65 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg8 seg9 seg7 seg6 seg5 seg4 seg2 seg3 seg1 seg0 c /d osc1(cs ) osc2(cl) e/rd r/w (wr ) 78 79 52 51 28 30 (0,0) x y chip size : 4162 m x 3000 m. pad size: 90 m x 90 m. 1 com5 com4 100 com6 2 chip id fig.4 the sbn1661g_m18, sbn1661g_m02 pad placement note: (1) the sbn1661g_m18 and the sbn1661g_m02 have the same pad placement. (2) the chip id of the sbn1661g_m18 is at18001-01. (3) the chip id of the sbn1661g_m02 is at18001-02. (4) the die origin is at the center of the chip. (5) for chip_on_board_bonding, chip carrier should be connected to vdd or left open. chip carrier is the metal pad to which the die is attached.
2006 aug 16 9 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 3.4 the sbn0080g_s18 , sbn0080g_s02 pad placement 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 seg69 seg73 seg74 seg75 seg76 seg77 seg78 seg79 v2 v3 v5 fr reset/if vdd db7 db6 db5 db4 db3 db2 db1 db0 vss 31 32 33 34 35 36 37 38 39 40 41 42 43 44 seg43 29 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 46 47 48 49 45 50 27 26 25 24 23 22 21 20 19 18 17 16 14 13 12 11 10 9 8 7 6 5 4 3 15 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg55 seg54 seg56 seg57 seg58 seg59 seg61 seg60 seg62 seg63 seg64 seg65 seg66 seg67 seg68 53 54 55 56 57 58 59 60 61 62 63 64 66 67 68 69 70 71 72 73 74 75 76 77 65 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg8 seg9 seg7 seg6 seg5 seg4 seg2 seg3 seg1 seg0 c /d cs cl e/rd r/w (wr ) 78 79 52 51 28 30 (0,0) x y chip size : 4162 m x 3000 m. pad size: 90 m x 90 m. 1 seg71 seg72 100 seg70 2 chip id fig.5 the sbn0080g_s18, sbn0080g_s02 pad placement note: (1) the sbn0080g_s18 and the sbn0080g_s02 have the same pad placement. (2) the chip id of the sbn0080g_s18 is at18001-03 (3) the chip id of the sbn0080g_s02 is at18001-04. (4) the die origin is at the center of the chip. (5) for chip_on_board_bonding, chip carrier should be connected to vdd or left open. chip carrier is the metal pad to which th e die is attached.
2006 aug 16 10 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 3.5 the sbn1661g_m18, sb n1661g_m02 pad coordinates table 3 the sbn1661g_m18, sbn1661g_m02 p ad coordinates (unit: m) pad no. pad name xy pad no. pad name xy pad no. pad name xy 1 com5 -1824 -1430 35 seg37 2011 -732 69 seg3 -498 1430 2 com6 -1694 -1430 36 seg36 2011 -597 70 seg2 -628 1430 3 com7 -1569 -1430 37 seg35 2011 -462 71 seg1 -758 1430 4 com8 -1444 -1430 38 seg34 2011 -327 72 seg0 -888 1430 5 com9 -1319 -1430 39 seg33 2011 -192 73 c /d -1062 1430 6 com10 -1186 -1430 40 seg32 2011 -57 74 osc1 -1194 1430 7 com11 -1053 -1430 41 seg31 2011 78 75 osc2 -1326 1430 8 com12 -920 -1430 42 seg30 2011 213 76 e/rd -1458 1430 9 com13 -787 -1430 43 seg29 2011 348 77 r/w (wr ) -1590 1430 10 com14 -654 -1430 44 seg28 2011 483 78 vss -1722 1430 11 com15 -521 -1430 45 seg27 2011 618 79 db0 -1854 1430 12 seg60 -388 -1430 46 seg26 2011 753 80 db1 -2011 1358 13 seg59 -255 -1430 47 seg25 2011 883 81 db2 -2011 1176 14 seg58 -122 -1430 48 seg24 2011 1013 82 db3 -2011 1044 15 seg57 11 -1430 49 seg23 2011 1143 83 db4 -2011 909 16 seg56 144 -1430 50 seg22 2011 1273 84 db5 -2011 771 17 seg55 277 -1430 51 seg21 1842 1430 85 db6 -2011 635 18 seg54 410 -1430 52 seg20 1712 1430 86 db7 -2011 497 19 seg53 543 -1430 53 seg19 1582 1430 87 vdd -2011 358 20 seg52 676 -1430 54 seg18 1452 1430 88 reset/if -2011 212 21 seg51 809 -1430 55 seg17 1322 1430 89 fr -2011 81 22 seg50 942 -1430 56 seg16 1192 1430 90 v5 -2011 -50 23 seg49 1075 -1430 57 seg15 1062 1430 91 v3 -2011 -180 24 seg48 1208 -1430 58 seg14 932 1430 92 v2 -2011 -326 25 seg47 1341 -1430 59 seg13 802 1430 93 m/s -2011 -456 26 seg46 1474 -1430 60 seg12 672 1430 94 v4 -2011 -586 27 seg45 1607 -1430 61 seg11 542 1430 95 v1 -2011 -716 28 seg44 1740 -1430 62 seg10 412 1430 96 com0 -2011 -846 29 seg43 1873 -1430 63 seg9 282 1430 97 com1 -2011 -976 30 seg42 2006 -1430 64 seg8 152 1430 98 com2 -2011 -1106 31 seg41 2011 -1272 65 seg7 22 1430 99 com3 -2011 -1236 32 seg40 2011 -1137 66 seg6 -108 1430 100 com4 -2011 -1388 33 seg39 2011 -1002 67 seg5 -238 1430 34 seg38 2011 -867 68 seg4 -368 1430
2006 aug 16 11 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 3.6 the sbn0080g_s18, sb n0080g_s02 pad coordinates table 4 the sbn0080g_s18, sbn0080g_s02 pad coordinates ( unit: m ) pad no. pad name xy pad no. pad name xy pad no. pad name x y 1 seg71 -1824 -1430 35 seg37 2011 -732 69 seg3 -498 1430 2 seg70 -1694 -1430 36 seg36 2011 -597 70 seg2 -628 1430 3 seg69 -1569 -1430 37 seg35 2011 -462 71 seg1 -758 1430 4 seg68 -1444 -1430 38 seg34 2011 -327 72 seg0 -888 1430 5 seg67 -1319 -1430 39 seg33 2011 -192 73 c /d -1062 1430 6 seg66 -1186 -1430 40 seg32 2011 -57 74 cs -1194 1430 7 seg65 -1053 -1430 41 seg31 2011 78 75 cl -1326 1430 8 seg64 -920 -1430 42 seg30 2011 213 76 e/rd -1458 1430 9 seg63 -787 -1430 43 seg29 2011 348 77 r/w (wr ) -1590 1430 10 seg62 -654 -1430 44 seg28 2011 483 78 vss -1722 1430 11 seg61 -521 -1430 45 seg27 2011 618 79 db0 -1854 1430 12 seg60 -388 -1430 46 seg26 2011 753 80 db1 -2011 1358 13 seg59 -255 -1430 47 seg25 2011 883 81 db2 -2011 1176 14 seg58 -122 -1430 48 seg24 2011 1013 82 db3 -2011 1044 15 seg57 11 -1430 49 seg23 2011 1143 83 db4 -2011 909 16 seg56 144 -1430 50 seg22 2011 1273 84 db5 -2011 771 17 seg55 277 -1430 51 seg21 1842 1430 85 db6 -2011 635 18 seg54 410 -1430 52 seg20 1712 1430 86 db7 -2011 497 19 seg53 543 -1430 53 seg19 1582 1430 87 vdd -2011 358 20 seg52 676 -1430 54 seg18 1452 1430 88 reset/if -2011 212 21 seg51 809 -1430 55 seg17 1322 1430 89 fr -2011 81 22 seg50 942 -1430 56 seg16 1192 1430 90 v5 -2011 -50 23 seg49 1075 -1430 57 seg15 1062 1430 91 v3 -2011 -180 24 seg48 1208 -1430 58 seg14 932 1430 92 v2 -2011 -326 25 seg47 1341 -1430 59 seg13 802 1430 93 seg79 -2011 -456 26 seg46 1474 -1430 60 seg12 672 1430 94 seg78 -2011 -586 27 seg45 1607 -1430 61 seg11 542 1430 95 seg77 -2011 -716 28 seg44 1740 -1430 62 seg10 412 1430 96 seg76 -2011 -846 29 seg43 1873 -1430 63 seg9 282 1430 97 seg75 -2011 -976 30 seg42 2006 -1430 64 seg8 152 1430 98 seg74 -2011 -1106 31 seg41 2011 -1272 65 seg7 22 1430 99 seg73 -2011 -1236 32 seg40 2011 -1137 66 seg6 -108 1430 100 seg72 -2011 -1388 33 seg39 2011 -1002 67 seg5 -238 1430 34 seg38 2011 -867 68 seg4 -368 1430
2006 aug 16 12 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 3.7 pin(pad) signal difference among the four members of the sbn1661g_x all four members of the sbn1661g_x series have the same pad sequence and placement. however, some pins(pads) have different signals for different types . a comparison is given in table 5. table 5 comparison of pin(pad) signals 3.8 pin (pad) states after hardware reset table 6 pin(pad) states after reset type pin(pad) 1~11 pin(pad) 74 pin(pad) 75 pin(pad) 93 pin(pad) 94 pin(pad) 95 pin(pad) 96~100 sbn1661g_m18 com5~15 osc1 osc2 m/s v4 v1 com0~4 sbn1661g_m02 com5~15 cs cl m/s v4 v1 com0~4 sbn0080g_s18 seg71~61 cs cl seg79 seg78 seg77 seg76~72 sbn0080g_s02 sbn1661g_m18, sbn1661g_m02 sbn0080g_s18, sbn0080g_s02 signal states after reset signal states after reset db0~db7 tri-state db0~db7 tri-state com0~com15 v dd seg0~seg61 v dd seg0~seg79 v dd fr(sbn1661g_m18) tri-state osc2 (sbn1661g_m18) tri-state
2006 aug 16 13 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 3.9 the sbn1661g_m18 and the sbn1661g_m02 signal description table 7 pin (pad) signal description to avoid a latch-up effect at power-on: v ss ? 0.5 v < voltage at any pin at any time < v dd +0.5v. pin number symbol i/o description 1~11, 96~100 com5~15, com0~4 output common driver outputs. the output voltage level of common out puts are decided by the combination of the alternating frame signal (fr) and t he internal common counter, which generates raster-scanning common signals. depending on the value of the frame signal and the common counter output, a single voltage level is selected from vdd, v1, v4, or v5 for common driver , as shown in fig. 6. 12~72 seg60~0 output segnent driver outputs. the output voltage level of segment outpu ts are decided by the combination of the alternating frame signal (fr) and di splay data. depending on the value of the frame signal and the display data, a sinlge voltage level is selected from vdd, v2, v3, or v5 for segment driver, as shown in fig. 7. 73 c /d input selection of command or data. when c /d=0, the data on the 8-bit data bus (db0~db7) are either commamd, data to be written to an internal register , or data read from the internal status register. when c /d=1, the data on the 8-bit data bus (db0~db7) are related to the display data memory. they are the data to be written to or read from the display data memory. 0 1 0 1 0 1 0 1 0 1 0 1 0 v4 v5 v1 vdd v4 v5 v1 vdd fig.6 common driver output voltage level fr common output counter common output 0 1 0 1 0 1 0 1 0 1 0 1 0 v3 vdd v2 v5 v3 vdd v2 v5 fig.7 segment driver output voltage level fr display data bit seg output
2006 aug 16 14 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 74 osc1 input for the sbn1661g_m18, pin 74 is the osc1 pi n of the on-chip rc oscillator. it is the input pin to the oscillator. an exte rnal resistor should be connected across the osc1 and the osc2. cs for the sbn1661g_m02, pin 74 is the cs pin. usually, a signal decoded from the host microcontroller address lines or a por t line (c51) is connected to this pin. 75 osc2 output for the sbn1661g_m18, pin 75 is the osc2 pi n. it is the output pin of the on-chip rc oscillator. cl input for the sbn1661g_m02, pin 75 is the cl pi n. clock from master or an external clock source should be added to this pin. 76 e/(rd ) input enable signal (e) for the 68-type mi crocontroller, or read (rd ) signal for the 80-type microcontroller. if a 68-type microcotroller is selected as the host microcontroller, this pin should be connected to the enable output of the mi crocontroller. a high level on this pin indicates that the microcontroller in tends to select the sbn1661g_x series. if a 80-type microcontroller is selected as the host microcontroller, this pin should be connected to the rd output of the microcontroller. a low level on this pin indicates that the microcontroller intends to read from the sbn1661g_x series.. 77 r/w (wr ) input read/write (r/w ) signal for the 68-type microcontroller, or write(wr ) signal for the 80-type microcontroller. if a 68-type microcotroller is selected as the host microcontroller, this pin should be connected to the r/w output of the microcontroller . a high level on this pin indicates that the microcontroller intends to read from the sbn1661g_x series. a low level on this pin indicates that the microcontroller intends to write to the sbn1661g_x series. if a 80-type microcontroller is selected as the host microcontroller, this pin should be connected to the wr output of the microcontroller. a low level on this pin indicates that the microcontroller int ends to write to the sbn1661g_x series. 78 v ss ground pin. 79~86 db0~db7 i/o bi-direction, tri-state 8-bit parallel data bus for interface with a host microcontroller. this data bus is for data transfer between the host microcontroller and the sbn1661g_x. 87 v dd input power supply for logic part of the chip. the v dd should be in the range from 2.7 volts to 5.5 volts. pin number symbol i/o description
2006 aug 16 15 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 88 reset/if input hardware reset and interface type selection. this pin is a dual function pin. it can be used to reset the sbn1661g_x and select the type of interface timing. the hardware reset is edge-sensitive. it is not level-sensitive. that is, either a falling edge or a rising edge on this pin can reset the chip. the voltage level after the reset pulse selects the type of interface timing. if the voltage level after the reset pulse stays at high, interface timing for t he 68-type microcontroller is selected. if the voltage level after the reset pulse stays at low, then interface timing for the 80-type microcontroller is selected. therefore, a positive reset pulse select s the 80-type microcontroller for interface and a negative reset pulse selects the 68 -type microcontroller for interface. the following diagram illustrates the reset pulse and the selected type of microcontroller. 89 fr i/o frame output or input. the frame signal is the ac siganl for generat ing alternating bias voltage of reverse polarities for lcd cell. when the chip is used as master in a master-slave connection, this pin is an output pin and s ends frame signal to the slave. when the chip is used as slave, this pin is an input pin and accepts frame signal from the master. 90, 91, 92, 94, 95 v5, v3, v2, v4, v1 input external lcd bias voltage. the condition vdd v1 v2 v3 v4 v5 must always be met. in addition, v lcd (v5-v dd ) should not exceed -13 volts. 93 m/s input selection for master or slave in a master-slave conneciton. when this pin is connected to v dd (hardwired-connection), the chip is used as master. when this pin is connected to v ss , the chip is used as slave. * the common scanning order for the slave dr iver is reverse to that for master. pin number symbol i/o description positive reset pulse negative reset pulse interface timing for the 80-type microcontroller is selected. interface timing for the 68-type microcontroller is selected. fig.8 reset pulse interface timing selection m/s fr com0-com15 output osc1 osc2 vdd output com0-com15 input output vss input com31-com16 nc input
2006 aug 16 16 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 4 a sbn1661g_x-based display system a sbn1661g_x-based display system is shown in fig. 9. the sbn1661g_x , on the one side, interfaces with a host microcontroller via address bus , data bus, and control bus. the address bus from the microcontroller needs to be fu rther decoded to generate chip select signal. the host microcontroller can perform read/write operation to the on-chip display data memory, can send commands to the sbn1661g_x, and can program the internal registers to congi fure the sbn1661g_x. how data is to be displayed on the lcd panel is completely controlled by the host microcontroller. on the other side, the sb n1661g_x provides 15 common drivers and 61 se gment drivers to drive the lcd panel. to expand the common number and segment number, bot h the sbn1661g_m18 and sbn1661g_m02 can be used either as a master or as a slave in a master-slave c onnection. the synchronization betw een the master and the slave is via the fr (frame) signal and the cl (clock) signal supplied from the master to the slave. if only segment number needs to be expanded, then t he sbn0080g_s18 or the sbn0080g_s02 can be used as slave. host 68-series 80-seris c51-series address bus data bus control bus (master) sbn1661g_x sbn1661g_x (slave) lcd panel com0 com15 seg1 seg61 com0 com15 seg1 seg61 fig.9 a sbn1661g_x se ries-based display system microcontroller reset decoder display data memory display data memory registers registers lcd bias power supply
2006 aug 16 17 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 5 interface with a host microcontroller 5.1 selection of interface type by use of the r eset/if pin(pad) the sbn1661g_x series can accept two types of interface timing for two types of microconftroller: the 68-type micrcontrollers and the 80-type microcontro llers. selection of interface type is by use of the dual-function reset/if pin(pad). if the voltage at the reset/if pin(pad) stays at high after reset pul se, then the 68-type interface timing is selected. if the voltage at the reset/if pin(pad) stays at low after reset pul se, then the 80-type interface timing is selected. the reset of the sbn 1661g_x is edge-sensitive, instead of level-sens itive. that is, a pulse on the reset/if input triggers reset only on the rising edge and falling edge of the pul se. the voltage level after the reset pulse is used to select interface type. 5.2 interface signal and operation the interface signal between the host microcontroller and the sbn1661g_x are data bus and control bus. the data bus is an 8-bit (db0~db7) bi-directional bus. the cont rol bus is composed of the following siganls: c /d, e/(rd ), and r/w (wr ). by means of data bus and control bus, the host microcontrolle r can write data to the on-chip display data memory, can read data from the display data memory, can program the in ternal registers, can send commands, and can read status of the chip. it is the host microcontroller?s responsibility to put pr oper data and timing on the data bus and control bus to ensure proper communication. table 8 lists the setting for control bus and the types of interface operation. table 8 interface signal and microcontroller operation 5.3 interface timing please refer to fig. 22 and fig. 24 for interface timing di agram and table 42 , table 43, table 44, and table 45 for ac characteristics of interface timing. 5.4 interface circuit please refer to fig. 24, fig. 25, and fi g. 26 for interface circuit examples. comman /data 68-type interface 80-type interface operation c /d r/w rd wr 1101 the host microcontroller reads data from the display data memory. 1010 the host microcontroller writes data to the display data memory 0 1 0 1 the host microcontroller reads the status register. 0010 the host microcontroller issues a command or writes data to an internal register.
2006 aug 16 18 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 6 display data memory and lcd display the display data memory is a static me mory bit(cell) array of 32-row x 80-column . so, the total bit number of the display data memory is 32 x 80 = 2560 bits. each bit of the memo ry is mapped to a single pixel (dot) on the lcd panel. a ?1? stored in the display data memory bit corresponds to an on pixel (black dot in normal display) of the lcd panel. a ?0? stored in the display data memory bit corresponds to an o ff pixel (background dot in normal display) of the lcd panel. column outputs(column 0~79) of the display data memo ry is mapped to seg 0~79 out puts of the sbn1661g_x. the mapping can be normal mapping or inverse mapping. normal mapping means that column0 is mapped to seg0, column1 to seg1, column2 to seg2, and so on. inverse m apping means that column0 is mapped to seg79, column1 to seg78, column2 to seg77, and so on. the mapping re lation is decided by the colu mn/segment mapping register. any row (80 bits) of the display data memory can be select ed as the first row (com0) to be displayed on the lcd panel. this is decided by the display start line register. the display start line register poi nts at the first row of a block of the display data memory, which will be mapped to com0 of the lc d display. the length of the block of the memory can be 32 rows or 16 rows, which is decided by the duty select register. fig.10 memory cell array and lcd pixel array row 0 row 1 row 2 row 3 row 31 row 30 row 29 row 28 column 0 column 1 column 2 column 79 column 78 column 77 com 0 com 1 com 2 com 3 com 15 seg 0 seg 1 seg 2 seg 79 seg 78 seg 77 display data memory cell array lcd panel pixel array
2006 aug 16 19 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 7 display control instructions and registers 7.1 registers and their states after hardware reset the sbn1661g_x has a set of registers. to ensure pr oper operation of the devices, these registers must be programmed with proper val ues after hardware reset. the registers and their states af ter reset is given in table 9. table 9 registers and their states after reset 7.2 display on/off and the display on/off register the display on/off register is a 1- bit register. when this bit is progammed to high, the display is turned on. when this bit is programmed to low, the display is turned off. when display is turned o ff, seg0~seg60 will stay at either v2 or v3, and com0~com15 will stay at their previous value bef ore the display off command is issued. to program this register, the setting of control bus is given in table 10 and the setting of the data bus is given in table 11. table 10 setting of the control bus for pr ogramming the displa y on/off register table 11 setting of the data bus for progr amming the displa y on/off register when d0=1, the code is af(hex) and the display is turned on . when d0=0, the code is ae(hex) and the display is turned off. register name description states after reset display on/off register the display on/off register is a 1-bit register. after reset, its value is low and, therefore, the lcd display is turned off. 0 display start line register the display start line register is a 6-bit register. after reset, its value is 0 0000 and row0 of the display data memory is mapped to com0. 00 0000 page addres register the page address register is a 2- bit register. af ter reset, its value is 11 and, therefore, it poi nts to page 3 of the display data memory. 11 column address register the column address register is a 7-bit register. after reset, its value is 000 0000 and, therefore, it points to column 0 of the display data memory. 000 0000 static drive on/off register the static drive on/off regist er is a 1-bit register. after reset, its value is low and st atic display is turned off. 0 duty select register the duty select register is a 1-bit register. after reset, its value is high and 1/32 display duty is selected. 1 column/segment mapping register the column/segment mapping regi ster is a 1-bit register. after reset, its value is lo w and normal mapping is selected. 0 status register the status register shows the current state of the sbn1661g_x. it is a 4-bit regist er, with each bit showing the status of a programmed function. 0000 0000 c /d e/(rd )r/w (wr ) 010 d7(msb)d6d5d4d3d2d1d0(lsb) 1010111d0
2006 aug 16 20 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 7.3 display start line and the display start line register the display start line register is a 5-bi t register. it points at the first row of a block of the display data memory, which will be mapped to com0. the length of t he block of the memory can be 32 rows or 16 rows, which is decided by the duty select register. for example, if the display start line register is programm ed with 00010 ( decimal 2) and display duty is 1/32, then row2 of the display data memory will be mapped to com0 of lcd panel, row3 to com1, row4 to com2, row30 to com28, row31 to com29, row0 to com30, and finally row1 to com31, as illustrated in fig. 11. however, in this case, only row2~row17 can be displayed on com0~c om15, as com16~com31 are not availabe from the chip. to program this register, the setting of the control bus is given in table 12 and the setting of the data bus is given in table 13. table 12 the setting of the control bus for pr ogramming the display start line register table 13 the setting of the data bus for progr amming the display start line register a4, a3, a2, a1, and a0 are start line address bits and they can be programmed with a value in the range from 0 to 31. therefore, the code can be from 1100 0000 (c0 hex) to 1101 1111 (df hex). c /d e/(rd )r/w (wr ) 010 d7(msb)d6d5d4d3d2d1d0(lsb) 1 1 0 a4 a3 a2 a1 a0 fig.11 display start line register row 0 row 1 row 2 row 3 row 31 row 30 row 29 row 28 column 0 column 1 column 2 column 79 column 78 column 77 com 0 com 1 com 2 com 3 com 31 com 30 com 29 com 28 seg 0 seg 1 seg 2 seg 79 seg 78 seg 77 0 1 0 0 0 display start line register a0 a1 a2 a3 a4 display data memory lcd panel
2006 aug 16 21 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 7.4 display data memory page and the page address register the on-chip display data memory is divided into 4 pages: page 0, page 1, page 2, and page 3, with each page having 80 bytes in horizontal direction. page 0 is from row 0 to ro w 7, page 1 from row 8 to row 15, page 2 from row 16 to row 23, and page 3 from row 24 to row 31, as shown in fig 12. when the host microtroller intends to perform a read/write operation to the display data memory, it has to program the page adrress register to indicate which page it intends to access. to program this register, the setting of the control bus is gi ven in table 14 and the setting of the data bus is given in table 15. table 14 the setting of the control bus for programming the page address register table 15 the setting of the data bus for programming the page address register a1and a0 are page address bits and can be programmed with a value in the range from 0 to 3. a1a0=00 selects page 0, a1a0=01 selects page 1, a1a0=10 selects page 2, and a1a0 =11 selects page 3. therefore, the code can be from 1011 1000 (b8 hex) to 1011 1011 (bb hex). c /d e/(rd )r/w (wr ) 010 d7(msb)d6d5d4d3d2d1d0(lsb) 101110a1a0 row0 row1 row2 row3 row4 row5 row6 row7 fig.12 page/column allocation of the display data memory page 0 page 1 page 2 page 3 row8 row9 row10 row11 row12 row13 row14 row15 row16 row17 row18 row19 row20 row21 row22 row23 row24 row25 row26 row27 row28 row29 row30 row31 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 column 77(byte77) column 78(byte78) column 79(byte79) column 3(byte3) column 2(byte2) column 1(byte1) column 0(byte0)
2006 aug 16 22 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 7.5 column address and the column address register the column address register points at a column of the di splay data memory which the host microcontroller intends to perform a read/write oper ation. the column address register automatic ally increments by 1 af ter a read or write operation is finished. when the column address register reaches 79, it overflows to 0. please refer to fig.12 for the column sequence in a page of the display data memory. to program this register, the setting of the control bus is gi ven in table 16 and the setting of the data bus is given in table 17. table 16 the setting of the control bus for programming the column address register table 17 the setting of the data bus for programming the column address register a6~a0 are column address bits and can be programmed with a value in the range from 0 to 79. therefore, the code can be from 0000 0000 (00 hex) to 0100 1111 (4f hex). c /d e/(rd )r/w (wr ) 010 d7(msb)d6d5d4d3d2d1d0(lsb) 0 a6a5a4a3a2a1a0
2006 aug 16 23 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 7.6 mapping between memory cloumns and segmen ts and the column/segment mapping register the column/segment mapping register is a 1-bit register and selects the m apping relation between the column outputs of the display data memory and the segment outputs seg0~seg79. if this register is programm ed with high, then the data from column 79 of the display data memory will be output from seg0. this type of mapping is called inverted mapping . if this register is programmed with lo w, then data from column 0 of the displa y data memory will be output from seg0. this type of mapping is called normal mapping . by use of this register, the fl exibility of component placement and routing on a pcb can be increased. to program this register, the setting of the control bus is given in table 18 and the setting of the data bus is given in table 19. table 18 the setting of the control bus for progr amming the column/segment mapping register table 19 the setting of the data bus for progra mming the memory/segment mapping register the least significant bit d c an be programmed with either 0 or 1. ther efore, the codes are a0 hex or a1 hex. c /d e/(rd )r/w (wr ) 010 d7(msb)d6d5d4d3d2d1d0(lsb) 1010000d fig.13 column/segment mapping register. row 0 row 1 row 2 row 3 row 31 row 30 row 29 row 28 seg 0 seg 1 seg 2 seg 79 seg 78 seg 77 display data memory segment driver column 0 column 1 column 2 column 77 column 78 column 79 row 0 row 1 row 2 row 3 row 31 row 30 row 29 row 28 seg 0 seg 1 seg 2 seg 79 seg 78 seg 77 display data memory segment driver column 0 column 1 column 2 column 77 column 78 column 79 inverted mapping normal mapping (d=1) (d=0)
2006 aug 16 24 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 7.7 static drive on/off and the static drive on/off register the static drive on/off regist er is a 1-bit register. it is used to turn on or off the static drive mode of the sbn1661g_x. when this register is programmed with high, static drive mode is turned on and the device enters into static drive mode , in which the internal clock circuitry is disabled and the switching of the internal logic is suspended. when this register is programmed with low, static drive mode is turned off and the chip returns to normal operation. this register is used in combination with the display on /off register to make the cu rrent consumption of the lcd module reduced to almost static level. by turning off the display and turning on the static drive mode,the chip is configured into the following state: ? all common and segment outputs are set to v dd , ? on-chip oscillator or external clock is i nhibited and internal logi c circuit stays idle, ? osc2 is in floating state (please refer to section 11 , on-chip rc oscillator), and ? the state of registers and the data of t he display data memory are kept unchanged. in addition to turning on the static drive mode and turning off the display, to really reduce the power consumption of the lcd module, the host microcontroller should also send out a power-save signal to turn off the pnp transistor in the bias circuit, such that the current flow from v dd to v ee can be cut off, as shown in fig. 14. to program this register, the setting of the control bus is given in table 20 and the setting of the data bus is given in table 21. table 20 the setting of the control bus for progr amming the static drive on/off register table 21 the setting of the data bus for progra mming the static driv e on/off register the least significant bit d0 can be pr ogrammed with either 0 or 1. theref ore, the code is a4 hex or a5 hex. c /d e/(rd )r/w (wr ) 010 d7(msb)d6d5d4d3d2d1d0(lsb) 1010010d v0 v2 v3 v5 v ss v dd v0 v1 v2 v3 v4 v5 v dd v dd v ee seg0~seg60 c c c c c fig.14 power save mode com0~com15 v1 v4 microcontroller power save signal
2006 aug 16 25 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 7.8 select duty and the select duty register the select duty register is a 1-bit r egister. if it is programm ed with high, 1/32 display dut y is selected. if it is programmed with low, 1/16 display duty is selected. to program this register, the setting of the control bus is given in table 22 and the setting of the data bus is given in table 23. table 22 the setting of the control bus for programming the select duty register table 23 the setting of the data bus for programming the select duty register the least significant bit d can be pr ogrammed with either 0 or 1. theref ore, the code is a8 hex or a9 hex. in a master-slave connection using the sbn1661g_m18 or the sbn1661g_m02 as the ma ster, com0~com15 will be from the master and com16~com 31 will be from the slave. the select duty register of both the master and the slave should be programmed with high to select 1/32 duty. fig.15 shows the common sequence of this connection. this register is not available in the sbn0080g_s18 and the sbn0080g_s02, because both the devices are purely segment drivers and their duty cycle is decided by the fr and the cl from the master. c /d e/(rd )r/w (wr ) 010 d7(msb)d6d5d4d3d2d1d0(lsb) 1010100d fig.15 common sequence of master-slave connection 0 1 2 13 14 15 29 30 31 16 17 18 0 1 2 16 17 18 13 14 15 29 30 31 frame signal com0~com15 (from master) com16~com31 (from slave) (from master)
2006 aug 16 26 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 7.9 status read and status register the status register shows t he current state of the sbn1661g _x. it can be read by the host microcontroller. bit 7~4 shows the status and bit 3~0 are always fixed at 0. to read the status register, the setting of the control bus is given in table 24, t he bit allocation is given in table 25 and the description for each bit is given in table 26. table 24 the setting of the control bus for reading the status register table 25 the status register bit allocation table 26 the status register bit description c /d e/(rd )r/w (wr ) 001 d7(msb)d6d5d4d3d2d1d0(lsb) busy mapping on/off reset 0000 bit description busy busy=1 indicates that the sbn 1661g_x is currently busy and can not accept new command or data. the sbn1661g_x is executing a command or is in the process of reset. busy=0 indicates that the sbn1661g _x is not busy and is ready to accept new command or data. mapping mapping=1 indicates that the column/segment mappi ng register has been programmed with a value of ?1? and the seg0 is mapped to column 79 of the display data memory (inverted mapping). mapping=0 indicates that the column/segment mapping register has been programmed with a value of ?0? and the seg0 is mapped to column 0 of the display data memory (normal mapping). on/off the on/off bit indicates the current of status of display. if on/off=0, then the display has been turned on. if on/off=1, then the display has been turned off. note that the polarity of this bit is inve rse to that of the di splay on/off register. reset reset=1 indicates that the sbn1661g_x is currently in the process of being reset. reset=0 indicates that the sbn1661g_x is currently in normal operation.
2006 aug 16 27 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 8 commands the host microcontroller can issue commands to the sbn 1661g_x. table 27 lists all the commands. when issuing a command, the host microcontroller should put the command co de on the data bus. the host microcontroller should also give the control bus c /d, e(rd ), and r/w (wr ) proper value and timing. table 27 commands 8.1 write display data the write display data command writes a byte (8 bits) of dat a to the display data memory. data is put on the data bus by the host microcontroller. the location which accepts this byte of data is pointed to by the page address register and the column address register. at the end of the command operation, the content of the column address register is automatically incremented by 1. for page address and column address of the display data memory, please refer to fig. 12. table 28 gives the control bus setting for this command. table 28 the setting of the control bus for issuing write display data command command command code function d7 d6 d5 d4 d3 d2 d1 d0 write display data data to be written into the display data memory. write a byte of data to the display data memory. read display data data read from the display data memory. read a byte of data from the display data memory. read-modify-writ e11100000start r ead-modify-write operation. end 1 1 1 0 1 1 1 0 stop read-modify-write operation. software reset 11100010software reset. c /d e/(rd )r/w (wr ) 110
2006 aug 16 28 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 8.2 read display data the read display data command starts a 3-step operation. 1. first, the current data of the internal 8-bit output latch of the display data me mory is read by the microcontroller, via the 8-bit data bus db0~db7. 2. then, a byte of data of the display data memory is trans ferred to the 8-bit output latch from a location specified by the page address register and t he column address register, 3. finally, the content of the column address register is automatically incremented by one. fig. 16 shows the internal 8-bit ouptut latch located between the 8-bit i/o data bus and the display data memory cell array. because of this internal 8-bit output latch, a du mmy read is needed to obtain correct data from the display data memory. for display data write operation, a dummy write is not needed, because data can be directly written from the data bus to internal memory cells. table 29 gives the control bus setting for this command. table 29 the setting of the control bus fo r issuing read display data command c /d e/(rd )r/w (wr ) 101 fig.16 read display data memory 8-bit output latch ( 32 row x 80 column ) display data memory cell array column address decoder row address decoder db0 db1 db2 db3 db4 db5 db6 db7 (8-bit bi-directional data bus) read display data write display data
2006 aug 16 29 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 8.3 read-modify-write when the read-modify-write command is issued, t he sbn1661g_x enters into read-modify-write mode. in normal operation, when a read display data command or a wr ite display data command is issued, the content of the column address register is automatically incremented by one after the command operation is finished. however, during read-modify-write mode, the content of the column address register is not incremented by one after a read display data command is finished; only the write display data comm and can make the content of the column address register automatically incremented by one af ter the command operation is finished. during read-modify-write mode, any other registers, except the column addr ess register, can be modified. this command is useful when a block of the display data memory needs to be repeatedly read and updated. fig. 17 gives the change sequence of the column address r egister during read-modify-wri te mode. figure 18 gives the flow chart for read-modify-write command. fig.17 column address change during read-modify-write n n+1 n+2 n+3 n+m n read-modify-write duration column address internal buffer register re-load column address by issuing the end command read-modify-write command issued. end command issued.
2006 aug 16 30 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics table 30 gives the setting for the control bus and the setting of the data bus is given in table 31. table 30 the setting of the control bus for the read-modify-write command table 31 the setting of the data bus for the read-modify-write command the command code is e0 hex. 8.4 the end command the end command releases the read-modi fy-write mode and re-loads the column address register with the value previously stored in the internal buffer (refer to fig. 17) when the read-modify-write command was issued. table 32 gives the setting for the control bus and the setting of the data bus is given in table 33. c /d e/(rd )r/w (wr ) 010 d7(msb)d6d5d4d3d2d1d0(lsb) 11100000 fig.18 the flowchart for read-modify-write set page address register set column address register read-modify-write command dummy read read display data memory write display data memory finish modifying ? end no yes
2006 aug 16 31 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics table 32 the setting of the control bus for the end command table 33 the setting of the data bus for the end command the command code is ee hex. 8.5 software reset command the software reset command is different from the hardw are reset and can not be used to replace hardware reset. when software reset is issued by the host microcontroller, ? the content of the display start line r egister is cleared to zero(a4~a0=00000), ? the page address register is set to 3 (a1 a0 = 11), ? the content of the display data memory remains unchanged, and ? the content of all othe r registers remains unchanged. table 34 gives the setting for the control bus and the setting of the data bus is given in table 35. table 34 the setting of the control bus for software reset table 35 the setting of the data bus for software reset the command code is e2 hex. c /d e/(rd )r/w (wr ) 010 d7(msb)d6d5d4d3d2d1d0(lsb) 11101110 c /d e/(rd )r/w (wr ) 010 d7(msb)d6d5d4d3d2d1d0(lsb) 11100010
2006 aug 16 32 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 9 lcd bias circuit a typical lcd bias circuit is s hownin fig. 19. the condition vdd v1 v2 v3 v4 v5 must always be met. the maximum allowed voltage for lcd bias (v lcd =v dd -v 5 ) should not exceed 13 volts. v2 v3 v5 v ss v dd v1 v2 v3 v4 v5 v dd v dd v ee seg0~seg60 c c c c c com0~com15 v1 v4 microcontroller power save signal fig.19 lcd bias circuit c omponent r ecommended v alue c 0.1 f, electrolytic r1 2.2k r2 7.5k r3 10k tr1 pnp r1 r1 r1 r1 r2 r3 tr1 v dd v dd
2006 aug 16 33 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 10 common, segment output voltage the output voltage level of common driver and segment driver is given in table 36. the output voltage level of common driver is decided by the combination of fram e signal, internal common counter output, and the di splay on/off register. the output voltage level of seg ment driver is decided by the combinati on of frame signal, display data, and the display on/off register. table 36 common/segment ouptut voltage level note that, in the above table, ?data? for the com0~com15 is actually the output of t he internal common counter, which generates horizontal raster scanning signal. during reset, both segment and common outputs are at v dd . fr data display on/off seg0~seg60 (seg0~seg79) com0~com15 l l on v3 v4 l h on v5 v dd h l on v2 v1 h h on v dd v5 x(don?t care) x(don?t care) off v2 or v3 previous voltage
2006 aug 16 34 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 11 on-chip rc oscillator the sbn1661g_m18 has an on-chip rc-type oscillator. all other three members of the family do not have on-chip oscillator and need external clock source. th e output clk of the oscillator is the bas ic timing clock of the internal control logic, display pixel rate, and is also used to generate frame signal. the capacitor of the rc-oscillator is f abricated on-chip. only an external resistor rf needs to be connected across osc1 and osc2. the recommended value of rf is in the range from 1000k ohm to 1200k ohm. during pcb layout, this resistor should be placed as close to the sbn1661g_m 18 as possible, such that stray capacitance, inductance, and resistance can be minimized. the characteristics of the osci llator is given is table. 37. table 37 on-chip rc oscillator characteristics, t amb = ?2 0to+75 c oscillation min. typ. max. unit oscillation frequency at v dd =5v, r f =1.0m ? 20% 17.6 21.5 25.9 khz oscillation frequency at v dd =3v, r f =1.0m ? 20% 15.7 19.1 22.8 khz fig.20 on-chip rc oscillator osc1 osc2 disable disable disable vss vdd vss vdd clk r f 1.0 m (typical)
2006 aug 16 35 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 12 electrical characteristics 12.1 absolute maximum rating table 38 absolute maximum rating notes 1. the following applies to the absolute maximum rating: a) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. b) the sbn1661g_x series includes circuitry specifically designed for the protecti on of its internal devices from the damaging effect of excessive static charge (esd). however, it is sugges ted that conventional precautions be taken to avoid applying greater than the rated maxima. c) parameters are valid over operating te mperature range unless otherwise specified. d) all voltages are with respect to v ss, unless otherwise noted. 2. the condition vdd v1 v2 v3 v4 v5 must always be met. 3. qfp-type packages are sensitive to moisture of the enviroment, please check the drypack indicator on the tray package before soldering. exposure to moisture longer t han the rated drypack level may lead to cracking of the plastic package or broken bonding wiring inside the chip. symbol parameter min. max. unit v dd voltage on the v dd pin(pad) ? 0.3 +7.0 volts v lcd (note 2) lcd bias voltage, v lcd =v dd -v5 13 volts v i input voltage on any pin with respect to v ss ? 0.3 v dd +0.3 volts p d power dissipation 250 mw t stg storage temperature range ? 55 +125 c t amb operating ambient temperature range -40 + 85 c tsol (note 3) soldering temperature/time at pin 260 c, 10 second
2006 aug 16 36 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 13 dc characteristics table 39 dc characteristics v dd =5v 10%; v ss = 0 v; all voltages with respect to v ss, unless otherwise specified; t amb = ?2 0to+75 c. notes: 1. conditions for the measurement: os c1=osc2=vdd, measured at the v dd pin. 2. these values are measured when the microcontroller does not perform any read/write operation to the chip. 3. these meaurements are for diff erent members of the series: a) i dd(1) are measured for the sbn 1661g_m02 and the sbn0080g_s02, b) i dd(2) are measured for the sbn1661g_m18, and c) i dd(3) are measured for the sbn0080g_s18. 4. these values are measured when t he microcontroller continuously performs read/write operation to the chip. 5. this measurement is for the trans mission high-voltage pmos or nmos of com0~15 and seg0~60(79). please refer to section 18 for these driver ci rcuit. the meaurement is for the case when the voltage differential between the source and the drain of the high vo ltage pmos or nmos is 0.1 volts. 6. the value is relative to the reset pulse edge. that is, 1.0 s after the last reset edge, the device is completely reset. symbol parameter conditions min. typ. max. unit v dd supply voltage for logic 4.5 5.0 5.5 v v lcd lcd bias voltage v lcd = v dd -v5 13 v v il low level input voltage for all inputs 0 0.8 v v ih high level input voltage for all inputs v dd -1.2 v dd v v ol low level output voltage for all outputs 0.0 0.3 v v oh high level output voltage for all outputs v dd - 0.3 v dd v i stby standby current at v 5 =-5 volts note 1 3.0 a i dd(1) operating current at v 5 =-5 volts and f cl =2khz, v lcd =10 volts note 2 & note 3 2.7 5.6 a i dd(2) operating current at v 5 =-5 volts and rf=1 m , v lcd =10 volts 12.3 15.6 a i dd(3) operating current at v 5 =-5 volts and f cl =21.8 khz, v lcd =10 volts 5.3 10.8 a i dd( 4 ) operating current at v 5 =-5 volts and t cyc =100 khz, v lcd =10 volts note 4 21.7 26.2 a f osc(vdd=5v), f osc(vdd=3v) please refer to table 37, on-chip rc oscillator characteristics. c in input capacitance of all input pins 5.0 8.0 pf r on lcd driver on resistance note 5 5.0 7.5 k t r reset time note 6 1.0 s
2006 aug 16 37 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 14 ac timing characteristics 14.1 cl and fr timing table 40 cl and fr timing characteristics at v dd =5 volts v dd =5v 10%; v ss = 0 v; all voltages with respect to v ss unless otherwise specified; t amb = ?2 0to+75 c. table 41 cl and fr timing characteristics at v dd =3 volts v dd =3v 10%; v ss = 0 v; all voltages with respect to v ss unless otherwise specified; t amb = ?2 0to+75 c. symbol parameter conditions min. typ. max. unit t whcl cl clock high pulse width 33 s t wlcl cl cock low pulse width 33 s t r cl clock rise time 28 120 ns t f cl clock fall time 28 120 ns t dfr(input) fr delay time (input) when used as input in slave mode application -2.0 0.2 1.6 s t dfr(output) fr delay time (output) when used as output in master mode application, with cl= 100 pf. 0.2 0.36 s symbol parameter conditions min. typ. max. unit t whcl cl clock high pulse width 65 s t wlcl cl cock low pulse width 65 s t r cl clock rise time 50 220 ns t f cl clock fall time 50 220 ns t dfr(input) fr delay time (input) when used as input in slave mode application -3.6 0.36 3.6 s t dfr(output) fr delay time (output) when used as output in master mode application, with cl= 100 pf. 0.32 0.6 s fig.21 display control signal timing t wlcl t whcl t r t f t dfr cl fr 0.9 x vdd 0.1 x vdd 0.1 x vdd 0.1 x vdd 0.1 x vdd 0.1 x vdd 0.9 x vdd 0.9 x vdd
2006 aug 16 38 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 14.2 ac timing for interface with an 80-type microcontroller table 42 ac timing for interface with a 80-type microcontorller at v dd =5 volts v dd =5v 10%; v ss =0v; t amb =-20 cto+75 c. table 43 ac timing for interface with an 80-type microcontorller at v dd =3 volts v dd =3v 10%; v ss =0v; t amb =-20 cto+75 c. symbol parameter min. m ax. test conditons unit t as address set-up time 20 ns t ah address hold time 10 ns t f , t r read/write pulse falling/rising time 15 ns t rwpw read/write pulse width 200 ns t cyc system cycle time 1000 ns t ds data setup time 80 ns t dh data hold time 10 ns t acc data read access time 90 cl= 100 pf. refer to fig. 23. ns t oh data read output hold time 10 60 ns symbol parameter min. m ax. test conditons unit t as address set-up time 40 ns t ah address hold time 20 ns t f , t r read/write pulse falling/rising time 15 ns t rwpw read/write pulse width 400 ns t cyc system cycle time 2000 ns t ds data setup time 160 ns c /d, cs rd , wr d0 to d7 t rwpw t ds t dh t oh d0 to d7 (write) (read) 0.9 x vdd 0.1 x vdd 0.1 x vdd 0.1 x vdd 0.1 x vdd 0.1 x vdd 0.1 x vdd 0.1 x vdd 0.1 x vdd 0.9 x vdd 0.9 x vdd 0.9 x vdd 0.9 x vdd 0.9 x vdd 0.9 x vdd t as fig.22 ac timing for interfac e with a 80-type microcontroller t acc hi-z hi-z hi-z hi-z 0.9 x vdd t ah t f t r t cyc
2006 aug 16 39 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics note: the measurement is with the load circuit conne cted. the load circuit is shown in fig. 23. t dh data hold time 20 ns t acc data read access time 180 cl= 100 pf, refer to 23. ns t oh data read output hold time 20 120 ns symbol parameter min. m ax. test conditons unit fig.23 load circuit. vss c l c l = 100 pf (including wiring and probe capacitance). pin
2006 aug 16 40 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 14.3 ac timing for interface wi th a 68-type microcontroller table 44 ac timing for interface with a 68-type microcontroller at v dd =5 volts v dd =5v 10%; v ss =0v; t amb =-20 cto+75 c. symbol parameter min. m ax. test conditons unit t as1 address set-up time with respect to r/w 20 ns t as2 address set-up time with respect to c /d, cs 20 ns t ah1 address hold time with respect to r/w 10 ns t ah2 address hold time respect with to c /d, cs 10 ns t f , t r enable (e) pulse falling/rising time 15 ns t cyc system cycle time 1000 note 1 ns t ewr enable pulse width for read 100 ns t eww enable pulse width for write 80 ns t ds data setup time 80 ns t dh data hold time 10 ns t acc data access time 90 cl= 100 pf. refer to fig. 23. ns t oh data output hold time 10 60 ns fig.24 ac timing for interfac e with a 68-type microcontroller r/w d0 to d7 t ds t dh t oh d0 to d7 (write) (read) 0.9 x vdd 0.1 x vdd 0.1 x vdd 0.1 x vdd 0.1 x vdd 0.1 x vdd 0.1 x vdd 0.9 x vdd 0.9 x vdd 0.9 x vdd 0.9 x vdd 0.9 x vdd t acc hi-z hi-z hi-z hi-z c /d, cs 0.1 x vdd 0.1 x vdd 0.9 x vdd 0.9 x vdd e 0.1 x vdd 0.1 x vdd 0.9 x vdd t as1 t as2 t ah1 t ah2 0.9 x vdd 0.1 x vdd t r t f t cyc t ew
2006 aug 16 41 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics table 45 ac timing for interface with a 68-type microcontroller at v dd =3 volts v dd =3v 10%; v ss =0v; t amb =-20 cto+75 c. note: 1. the system cycle time(t cyc ) is the time duration from the time when ch ip enable is enabled to the time when chip select is released. symbol parameter min. max. test conditons unit t as1 address set-up time with respect to r/w 40 ns t as2 address set-up time with respect to c /d, cs 40 ns t ah1 address hold time with respect to r/w 20 ns t ah2 address hold time respect with to c /d, cs 20 ns t f , t r enable (e) pulse falling/rising time 15 ns t cyc system cycle time 2000 note 1 ns t ewr enable pulse width for read 200 ns t eww enable pulse width for write 160 ns t ds data setup time 160 ns t dh data hold time 20 ns t acc data access time 180 cl= 100 pf. refer to fig. 23. ns t oh data output hold time 20 120 ns
2006 aug 16 42 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 15 microcontroller interface circuit 15.1 example for inte rface with a 80-family microcontroller 15.2 example for inte rface with a 68-family microcontroller a0 a1~a7 iorq d0~d7 rd wr res vss vdd c /d cs db0~db7 rd wr reset/if vdd v5 gnd reset decoder 80-family microcontroller sbn1661g_m02 vdd negative lcd bias voltage note: this example is applicable to the sbn1661g_m02. fig.25 interface example with an 80-family microcontroller a0 a1~a15 vma d0~d7 e r/w res vss vdd c /d cs db0~db7 e r/w reset/if vdd v5 gnd reset decoder 68-family microcontroller sbn1661g_m02 vdd negative lcd bias voltage note: this example is applicable to the sbn1661g_m02. the cs selection for the sbn0080g_s18 and the sbn0080g_s02 can be decoded from the address lines in the same way. for application with the sbn1661g_m18, which does not have a cs input, the cs output from the decoder must be ored with c /d, e, and r/w . fig.26 interface example with a 68-family microcontroller
2006 aug 16 43 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 15.3 example for in terface with other types of 8-bit microcontroller c /d address d0~d7 e r/w res vss vdd c /d db0~db7 rd (e) wr (r/w) reset/if vdd v5 gnd reset 8-bit microcontroller sbn1661g_m18 vdd negative lcd bias voltage note: this example is applicable only to the sbn1661g_m18, which does not have a cs input and the cs output from the address or i/o space decoding circut must be ored with c /d, rd (e), and (wr )r/w . fig.27 interface example with an 8-bit microcontroller (indicating commad/data) address or i/o space decoding
2006 aug 16 44 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 16 synchronization of clock and frame in master/slave connections to expand common/segment number, both the sbn1661g_m18 and the sbn1661g_m02 can be used master. they can also be used as slave. however, if the sbn1661g_m 02 is used as master, external clock source is needed, as it has no on-chip oscillator. in master/slave connections, clock and frame between t he master and its slaves must be in synchronization. the sbn0080g_s18 and the sbn0080g_s02 can be us ed only as slave for segment expansion. 16.1 sbn1661g_m18 connected with a sbn1661g_m18 16.2 sbn1661g_m18 connected with more than two sbn0080g_s18 sbn1661g_m18 osc1 osc2 m/s fr master sbn1661g_m18 osc1 osc2 m/s fr slave v dd v ss r f to lcd segment to lcd segment to lcd common to lcd common fig.28 sbn1661g_m18 connec ted with a sbn1661g_m18. sbn1661g_m18 osc1 osc2 m/s fr master sbn0080g_s18 cl fr slave v dd r f to lcd segment to lcd segment to lcd common fig.29 sbn1661g_m18 connected with more than two sbn0080g_s18 sbn0080g_s18 cl fr slave to lcd segment note: when more than two slaves are connected, a cmos clock buffer is needed to drive all the slaves. the duty and phase of the clock to all the slav es must be the same as that for the master. cmos buffer
2006 aug 16 45 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 16.3 sbn1661g_m02 connected with a sbn1661g_m02 16.4 sbn1661g_m02 connected with a sbn0080g_s02 sbn1661g_m02 cl m/s fr master sbn1661g_m02 cl m/s fr slave v dd v ss to lcd segment to lcd segment to lcd common to lcd common fig.30 sbn1661g_m02 connec ted with a sbn1661g_m02. external clock source sbn1661g_m02 cl m/s fr master sbn0080g_s02 cl fr slave v dd to lcd segment to lcd segment to lcd common fig.31 sbn1661g_m02 connec ted with a sbn0080g_s02. external clock source
2006 aug 16 46 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 17 typical applications 17.1 1/16 duty, 10 characters x 2 lines 17.2 1/16 duty, 23 characters x 2 rows 17.3 1/32 duty, 33 characters x 4 lines fig.32 1/16 duty, 10 characters x 2 lines com15 com0 seg0 seg60 com15 com0 sbn1661g_m18 16 x 61 lcd panel in this application, 10-characters x 2-lines can be displayed, if the format of character font is 6 x 8 pixels. seg0 seg60 fig.33 1/16 duty, 23 characters x 2 lines com15 com0 seg0 seg60 com15 com0 sbn1661g_m18 16 x 141 lcd panel fr cl seg0 seg79 sbn0080g_s18 seg0 seg60 seg61 seg140 in this application, 23-characters x 2-lines can be displayed, if the format of character font is 6 x 8 pixels. (master) (slave) fig.34 1/32 duty, 33 characters x 4 lines com15 com0 seg0 seg60 com15 com0 sbn1661g_m18 32 x 202 lcd panel fr cl seg0 seg79 sbn0080g_s18 seg0 seg60 seg61 seg140 in this application, 33-characters x 4-lines can be displayed, if the format of character font is 6 x 8 pixels. (master) (slave) fr cl seg0 seg60 sbn1661g_m18 seg141 seg201 (slave) com0 com15 com16 com31
2006 aug 16 47 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 18 pin circuits table 46 mos-level schematics of al l input, output, and i/o pins. symbol input/ output circuit notes c /d, r/w (wr ), e/rd , reset/if inputs m/s input osc1, osc2 the circuit encircled inside the red dashed frame is the oscillator circut. d0~d7, fr i/o vss vdd vss vdd osc1 osc2 disable disable disable vss vdd vss vdd clk vss vdd vss vdd data out output enable data in enable
2006 aug 16 48 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics seg0~79 com0~15 symbol input/ output circuit notes vdd v2 v3 v5 v5 vdd en1 en2 en3 en4 vdd vdd vdd v5 v5 v5 seg0~79 vdd v5 com0~15 vdd v1 v4 v5 v5 vdd en1 en2 en3 en4 vdd vdd vdd v5 v5 v5 v5 vdd
2006 aug 16 49 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 19 application notes 1. it is recommended that the following power-up sequence be followed to ensure reliable operation of your display system. as the ics are fabricated in cmos and there is intrinsic latch-up problem associated with any cmos devices, proper power-up sequence can reduce the danger of triggering latch-up. w hen powering up the system, control logic power must be powered on first. when powering down the system, c ontrol logic must be shut off later than or at the same time with the lcd bias (v ee ). 2. the metal frame of the lcd panel should be grounded. 3. a 0.1 f ceramic capacitor should be connected between v dd and v ss . 4. a 0.1 mf ceramic capacitor should be connected between v dd (or v ss ) and each of v1, v2, v3, v4, and v5. 5. if the length of the cable connecting the host microcont roller and the lcd module is longer than 45 cm, a ceramic capacitor of 20p~150p should be connected between v dd (or v ss ) and each of the r/wr (wr ), the e/rd , and the cs . vdd signal vee 5v 0v -30v 0~50 ms 1 second (minimum) 0 second 0 second (minimum) (minimum) 0~50 ms 1 second (minimum) fig.35 recommended power up/down sequence
2006 aug 16 50 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 20 package information pakage information is provided in another document. please contact avant electronics for package information.
2006 aug 16 51 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 21 soldering 21.1 introduction there is no soldering method that is i deal for all ic packages. wave solderi ng is often preferred when through-hole and surface mounted components are mixed on one printed-circuit boar d. however, wave soldering is not always suitable for surface mounted ics, or for printed-circui ts with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. for more in-depth account of so ldering ics, please refer to dedicated reference materials. 21.2 reflow soldering reflow soldering techniques ar e suitable for all qfp packages. the choice of heating method may be influenced by larger plasti c qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutel y dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can c ause cracking of the plastic body. for more information, please contact avant for drypack information. reflow soldering requires solder paste (a suspension of fine solder particles, flux and bind ing agent) to be applied to the printed-circuit board by screen printi ng, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, t hermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typica l reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating dur ation: 45 minutes at 45 c. 21.3 wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of inco mplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, th e following conditions must be observed: ? a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. ? the footprint must be at an angle of 45 to the board direction and mu st incorporate solder thieves downstream and at the side corners. during placement and before so ldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of pack age immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 21.4 repairing so ldered joints fix the component by first soldering two diagonally- opposit e end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2006 aug 16 52 of 52 data sheet (v6.3) dot-matrix stn lcd driver with 32-row x 80-column sbn1661g_m18, sbn1661g_m02, sbn0080g_s18, sbn0080g_s02 avant electronics 22 life support applications avant?s products, unless specifically specified, are not des igned for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. avant customers using or selling avant?s products for use in such applications do so at their own risk and agree to fully indemnify avant for any damages resulting from such improper use or sale.

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