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1 standard products qcots tm ut8q512k32 16megabit sram mcm data sheet march, 2009 features ? 25ns maximum (3.3 volt supply) address access time ? mcm contains four (4) 512k x 8 industry-standard asynchronous srams; the control architecture allows operation as 8, 16, 24, or 32-bit data width ? ttl compatible inputs and output levels, three-state bidirectional data bus ? typical radiation performance - total dose: 50krads - sel immune >80 mev-cm 2 /mg - let th (0.25) = >10 mev-cm 2 /mg - saturated cross section cm 2 per bit, 5.0e-9 - < 1e-8 errors/bit-day, adams 90% geosynchronous heavy ion ? packaging options: - 68-lead dual cavity ceramic quad flatpack (cqfp) - (weight 7.37 grams) ? standard microcircuit drawing 5962-01533 - qml t and q compliant part introduction the qcots tm ut8q512k32 quantified commercial off-the- shelf product is a high-perfor mance 2m byte (16mbit) cmos static ram multi-chip module (mcm), organized as four individual 524,288 x 8 bit srams with a common output enable. memory expansion is provided by an active low chip enable (e n), an active low output enable (g ), and three-state drivers. this device has a power-down feature that reduces power consumption by more than 90% when deselected . writing to each memory is accomplished by taking the chip enable (e n) input low and write enable (w n) inputs low. data on the i/o pins is then wr itten into the location specified on the address pins (a 0 through a 18 ). reading from the device is accomplished by taking the chip enable (e n) and output enable (g ) low while forcing write enable (w n) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the input/output pins are placed in a high impedance state when the device is deselected (e n high), the outputs are disabled (g high), or during a write operation (e n low and w n low). perform 8, 16, 24 or 32 bit accesses by making w n along with e n a common input to any combination of the discrete memory die. figure 1. ut8q512k32 sram block diagram 512k x 8 512k x 8 512k x 8 512k x 8 dq(31:24) or dq3(7:0) dq(23:16) or dq2(7:0) dq(15:3) or dq1(7:0) dq(7:0) or dq0(7:0) g a(18:0) w 3 e 3 e 2 e 1 e 0 w 2 w 1 w 0
2 pin names device operation each die in the ut8q512k32 has three control inputs called enable (e n), write enable (w n), and output enable (g ); 19 address inputs, a(18:0); and eight bidirectional data lines, dq(7:0). the device enable (e n) controls device selection, active, and standby modes. asserting e n enables the device, causes i dd to rise to its active value, and decodes the 19 address inputs to each memory die by selecting the 2,048,000 byte of memory. w n controls read and write operations. during a read cycle, g must be asserted to enable the outputs. table 1. device operation truth table notes: 1. ?x? is defined as a ?don?t care? condition. 2. device active; outputs disabled. read cycle a combination of w n greater than v ih (min) with e n and g less than v il (max) defines a read cycle. read access time is measured from the latter of devi ce enable, output enable, or valid address to valid data output. sram read cycle 1, the address access is initiated by a change in address inputs while the chip is enabled with g asserted and w n deasserted. valid data appears on data outputs dqn(7:0) after the specified t av q v is satisfied. outputs remain active throughout the entire cycle. as lo ng as device enable and output enable are active, the address inpu ts may change at a rate equal to the minimum read cycle time (t avav ). sram read cycle 2, the chip enable-controlled access is initiated by e n going active while g remains asserted, w n remains deasserted, and the addr esses remain stable for the entire cycle. after the specified t etqv is satisfied, the eight-bit word addressed by a(18:0) is accessed and appears at the data outputs dqn(7:0). sram read cycle 3, the output enable-controlled access is initiated by g going active while e n is asserted, w n is deasserted, and the addresses ar e stable. read access time is t glqv unless t av q v or t etqv have not been satisfied. a(18:0) address w n writeenable dq(7:0) data input/output g output enable e n device enable v dd power v ss ground 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 top view dq0(0) dq1(0) dq2(0) dq3(0) dq4(0) dq5(0) dq6(0) dq7(0) v ss dq0(1) dq1(1) dq2(1) dq3(1) dq4(1) dq5(1) dq6(1) dq7(1) dq0(2) dq1(2) dq2(2) dq3(2) dq4(2) dq5(2) dq6(2) dq7(2) v ss dq0(3) dq1(3) dq2(3) dq3(3) dq4(3) dq5(3) dq6(3) dq7(3) nc a0 a1 a2 a3 a4 a5 e 2 v ss e 3 w 0 a6 a7 a8 a9 a10 v dd v dd a11 a12 a13 a14 a15 a16 e 0 g e 1 a17 w 1 w 2 w 3 a18 nc nc figure 2. 25ns sram pinout (68) g w n e n i/o mode mode x 1 x 1 3-state standby x 0 0 data in write 1 1 0 3-state read 2 0 1 0 data out read
3 write cycle a combination of w n less than v il (max) and e n less than v il (max) defines a write cycle. the state of g is a ?don?t care? for a write cycle. the outputs are placed in the high-impedance state when either g is greater than v ih (min), or when w n is less than v il (max). write cycle 1, the write enable-controlled access is defined by a write terminated by w n going high, with e n still active. the write pulse width is defined by t wlwh when the write is initiated by w n, and by t etwh when the write is initiated by e n. unless the outputs have been previous ly placed in the high-impedance state by g , the user must wait t wlqz before applying data to the eight bidirectional pins dqn(7:0) to avoid bus contention. write cycle 2, the chip enable-controlled access is defined by a write terminated by the former of e n or w n going inactive. the write pulse width is defined by t wlef when the write is initiated by w n, and by t etef when the write is initiated by the e n going active. for the w n initiated write, unless the outputs have been previously placed in the high-impedance state by g , the user must wait t wlqz before applying data to the eight bidirectional pins dqn(7:0) to avoid bus contention. typical radiation hardness the ut8q512k32 sram incorpor ates features which allow operation in a limited radiation environment. table 2. typical radiation hardness design specifications 1 notes: 1. the sram will not latchup during radiation exposure under recommended operating conditions. 2. 90% worst case particle environmen t, geosynchronous orbit, 100 mils of aluminum. total dose 50 krad(si) nominal heavy ion error rate 2 <1e-8 errors/bit-day
4 absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond lim its indicated in the operatio nal sections of this specif ication is not recommended. exposure to absolute maximum rating conditions for extend ed periods may affect device reliability and performance. 2. maximum junction temperatur e may be increased to +175 c during burn-in and steady-static life. 3. test per mil-std-883, method 1012. recommended operating conditions symbol parameter limits v dd dc supply voltage -0.5 to 4.6v v i/o voltage on any pin -0.5 to 4.6v t stg storage temperature -65 to +150 c p d maximum power dissipation 1.0w (per byte) t j maximum junction temperature 2 +150 c jc thermal resistance, junction-to-case 3 10 c/w i i dc input current 10 ma symbol parameter limits v dd positive supply voltage 3.0 to 3.6v t c case temperature range -40 to +125 c v in dc input voltage 0v to v dd
5 dc electrical characteristics (pre/post-radiation)* (-40 c to +125 c) (v dd = 3.3v + 0.3) notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. measured only for initial qua lification and after process or design changes that could affect input/output capacitance. 2. supplied as a design limit but not guaranteed or tested. 3. not more than one output may be shorted at a time for maximum duration of one second. symbol parameter condition min max unit v ih high-level input voltage (ttl) 2.0 v v il low-level input voltage (ttl) 0.8 v v ol1 low-level output voltage i ol = 8ma, v dd =3.0v (ttl) 0.4 v v ol2 low-level output voltage i ol = 200 a,v dd =3.0v (cmos) 0.08 v v oh1 high-level output voltage i oh = -4ma,v dd =3.0v (ttl) 2.4 v v oh2 high-level output voltage i oh = -200 a,v dd =3.0v (cmos) v dd -0.10 v c in 1 input capacitance ? = 1mhz @ 0v 32 pf c io 1 bidirectional i/o capacitance ? = 1mhz @ 0v 16 pf i in input leakage current v ss < v in < v dd, v dd = v dd (max) -2 2 a i oz three-state output leakage current 0v < v o < v dd v dd = v dd (max) g = v dd (max) -2 2 a i os 2, 3 short-circuit output current 0v < v o < v dd -90 90 ma i dd (op) supply current operating @ 1mhz (per byte ) inputs: v il = 0.8v, v ih = 2.0v i out = 0ma v dd = v dd (max) 125 ma i dd1 (op) supply current operating @40mhz (per byte) inputs: v il = 0.8v, v ih = 2.0v i out = 0ma v dd = v dd (max) 180 ma i dd2 (sb) nominal standby supply current @0mhz (per byte) inputs: v il = v ss i out = 0ma e n = v dd - 0.5, v dd = v dd (max) v ih = v dd - 0.5v 6 40 ma ma -40 c and 25 c +125 c
6 ac characteristics read cycle (pre/post-radiation)* (-40 c to +125 c) (v dd = 3.3v + 0.3) notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. functional test. 2. three-state is defined as a 300mv change from steady-state output voltage. 3. the et (enable true) notation refers to the falling edge of e n. seu immunity does not af fect the read parameters. 4. the ef (enable false) notation refers to the rising edge of e n. seu immunity does not af fect the read parameters. symbol parameter min max unit t avav 1 read cycle time 25 ns t avqv read access time 25 ns t axqx 2 output hold time 3 ns t glqx 2 g -controlled output enable time 3 ns t glqv g -controlled output enable time (read cycle 3) 10 ns t ghqz 2 g -controlled output three-state time 10 ns t etqx 2,3 e n-controlled output enable time 3 ns t etqv 3 e n-controlled access time 25 ns t efqz 1,2,4 e n-controlled output three-state time 10 ns { { } } v load + 300mv v load - 300mv v load v h - 300mv v l + 300mv active to high z levels high z to active levels figure 3. 3-volt sram loading
7 assumptions: 1. e n and g < v il (max) and w n > v ih (min) a(18:0) dqn(7:0) figure 4a. sram read cycle 1: address access t avav t avqv t axqx previous valid data valid data assumptions: 1. g < v il (max) and w n > v ih (min) a(18:0) figure 4b. sram read cycle 2: chip enable-controlled access e n data valid t efqz t etqx t etqv dqn(7:0) figure 4c. sram read cycle 3: output enable-controlled access a(18:0) dqn(7:0) g t ghqz assumptions: 1. e n < v il (max) and w n > v ih (min) t glqv t glqx t avqv data valid
8 ac characteristics write cycl e (pre/post-radiation)* (-40 c to +125 c) (v dd = 3.3v + 0.3) notes : * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. functional test performed with outputs disabled (g high). 2. three-state is defined as 300mv change from steady-state output voltage. symbol parameter min max unit t avav 1 write cycle time 25 ns t etwh device enable to end of write 20 ns t av e t address setup time for write (e n - controlled) 1 ns t av w l address setup time for write (w n - controlled) 0 ns t wlwh write pulse width 20 ns t whax address hold time for write (w n - controlled) 2 ns t efax address hold time for device enable (e n - controlled) 2 ns t wlqz 2 w n- controlled three-state time 10 ns t whqx 2 w n - controlled output enable time 5 ns t etef device enable pulse width (e n - controlled) 20 ns t dvwh data setup time 15 ns t whdx 2 data hold time 2 ns t wlef device enable controlled write pulse width 20 ns t dvef 2 data setup time 15 ns t efdx data hold time 2 ns t av w h address valid to end of write 20 ns t whwl 1 write disable time 5 ns
9 assumptions: 1. g < v il (max). if g > v ih (min) then qn(8:0) will be in three-state for the entire cycle. 2. g high for t avav cycle. w n t av w l figure 5a. sram write cycle 1: write enable - controlled access a(18:0) qn(7:0) e n t avav 2 dn(7:0) applied data t dvwh t whdx t etwh t wlwh t whax t whqx t wlqz t av w h t whwl
10 t efdx assumptions & notes: 1. g < v il (max). if g > v ih (min) then qn(7:0) will be in three-state for the entire cycle. 2. either e n scenario above can occur. 3. g high for t avav cycle. a(18:0) figure 5b. sram write cycle 2: chip enable - controlled access w n e n dn(7:0) applied data e n qn(7:0) t wlqz t etef t wlef t dvef t avav 3 t av e t t av e t t etef t efax t efax or notes: 1. 50pf including scope prob e and test socket capacitance. 2. measurement of data output occurs at the lo w to high or high to lo w transition mid-point (i.e., cmos input = v dd /2). 90% figure 6. ac test lo ads and input waveforms input pulses 10% < 5ns < 5ns v load = 1.55 300 ohms 50pf cmos 0.5v 90% v dd -0.05v 10%
11 data retention characteristics (pre/post-irradiation) (1 second data rentention test) notes: 1. e n = v dd - .2v, all other inputs = v dr or v ss . 2. data retention current (i ddr ) tc = 25 o c. 3. not guaranteed or tested. 4. v dr = t=-40 o c and 125 o c. data retention characteristics (pre/post-irradiation) (10 second data retention test, t c =-40 o c and +125 o c) notes: 1. performed at v dd (min) and v dd (max). 2. e n = v ss , all other inputs = v dr or v ss . 3. not guaranteed or tested. symbol parameter minimum maximum unit v dr v dd for data retention 2.0 -- v i ddr 1,2 data retention current (per byte) -- 2.0 ma t efr 1,3 chip select to data retention time 0 ns t r 1,3 operation recovery time t avav ns symbol parameter minimum maximum unit v dd 1 v dd for data retention 3.0 3.6 v t efr 2, 3 chip select to data retention time 0 ns t r 2, 3 operation recovery time t avav ns v dd data retention mode t r 50% 50% v dr > 2.0v figure 7. low v dd data retention waveform t efr e n
12 packaging notes: . package shipped with non-conductive strip (ncs). leads are not trimmed. 2. total weight approx. 7.37g. figure 8. 68-pin ceramic flatpack
13 ordering information 512k32 16megabit sram mcm: notes: 1. prototype flow per aeroflex colorado spring s manufacturing flows document. tested at 25 c only. lead finish is gold only. 2. extended industrial temperature range flow per aeroflex colora do springs manufacturing flows document. devices are tested at -40 o c to +125 o c. radiation neither tested nor guaranteed. gold lead finish only. device type: - = 25ns access, 3.3v operation package type: (s) = 68-lead dual cavity cqfp screening: (p) = prototype flow (w) = extended industrial temperature range flow (-40 o c to +125 o c) lead finish: (c) = gold ut8q512k32 -* * * * aeroflex core part number
14 512k32 16megabit sram mcm: smd 5962 - 01533 ** ** * notes: 1. total dose radiation must be specified when ordering. gold lead finish only. 2. only extended indu strial temperature -40c to +125c. no military temp. test available. federal stock class designator: no options total dose (-) = none (d) = 1e4 (10krad(si)) (l) = 5e4 (50krad(si)) (contact factory) (p) = 3e4 (30krad(si)) (contact factory) drawing number: 01533 device type 01 = 25ns access time, 3.3v oper ation, extended in dustrial temp (-40 o c to +125 o c) class designator: (t) = qml class t (q) = qml class q case outline: (x) = 68-lead dual cavity cqfp lead finish: (c) = gold
15 colorado toll free: 800-645-8862 fax: 719-594-8468 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex utmc microelectronic systems inc. (aeroflex) reserves the right to make changes to any products and services herein at any time without notice. consult aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a product or service from aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties. aeroflex colordo springs - datasheet definition advanced datasheet - product in development preliminary datasheet - shipping prototype datasheet - shipping qml & reduced hi-rel

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