78k0/kb2 mos integ r ated circuit preliminary product information 8-bit single-chip microcontroller ? n ec electron ics corpor atio n 2004 t he 78k0/kb2 prod ucts are 8- bit singl e-ch i p microcontro ller s of the 78k0 s e ries. t hese microcontrollers fe atur e sing le-vo l tag e self -pro gram ming f l ash me mor y a nd ma n y per ip hera l s. fe a t ures ? 78k0 cpu co re, 8-bit cisc architectur e ? flash eepr om and ram sizes item product name program mem o r y (fl a s h rom ) data memory (ram) pd78 f0503 32k b y tes (flash) 1k b y tes pd78 f0502 24k b y tes (flash) 1k b y tes pd78 f0501 16k b y tes ( f lash) 768 b y tes pd78 f0500 8k b y tes ( f lash) 512 b y te minim u m i n str u ctio n c y cle 0.1 s (2 0mhz@ 4 .0v to 5.5v) 0.2 s (10mhz @2.7v to 5.5v ) 0.4 s ( 5mhz @1.8v to 5.5v ) clock ? main cl ock - intern al high-speed-o scillator 8mhz (ty p .) - cer a mic/cry s tal o scillator / ex ter nal clk ( 1 mhz to 20mhz) (instruction exec ution ti me = 100ns(min.) @20mh z ) ? wdt clo c k - internal lo w-speed-o scillator 240khz (ty p .) peripherals . ? on -chip po w e r - on -clear (poc) circuit ? low - voltage d e tector (lvi ) circ uit ? ti mer - 16bit timer 1ch - 8bit timer 4ch - watchdog time r ( o perable w i th 240khz internal- l o w -speed -os c i ll ator) ? serial interface - uart/ c si 1ch - uart ( w ith lin - bus) 1ch - iic 1ch ? ad co nverter - 10-bit resolutio n a/d converter 4 ch ? i/o p o r t total : 23 cmos i/ o : 21 n-ch o. d i/o: 2 ? other - self progra mming - on -chip debug function ( pd7 8 f0503d onl y ) interrupt - internal 16ch - external 6ch o p e r at i o n v o lt ag e 1.8v to 5.5v package 30-pin ssop (7. 62mm(300 )) this in for m ati o n con t ai ned in t h is doc um ent i s being iss u ed in ad v a nce of t h e pro duc tion c y c l e for th e pro duct . t h e p a ram e ters for t h e prod uct m a y change b e fore final pro d u c tio n or nec electronics corp orati o n, at it s o w n dis c retio n , , ma y w i thdra w t h e pro duc t prio r to it s pro duc ti on. no t all pr o d u ct s a nd/ or t y p es are a v aila ble in e v er y c oun tr y . pleas e check w i th an n e c electro nics sales represe nt ati v e for a v aila b ilit y an d ad diti o n al in form ati on. z ud-cc-04- 01 25-e dat a pub lish e d oct 2004 n cp(k)
78k0/kb2 1. block diagram fig. 78k0/kb2 ani0 - ani3 a vss av r e f 10bit ad converter sck10 si10 so10 3w i r e serial i/f (csi10) ex ternal interru p t int p 0 - int p 5 ex l v i lo w volt a ge indicator ( lv i ) scl0 sda0 multi master iic (iic0) tx d 0 rxd0 uar t (uar t 0 ) t i 51 t o 51 8bit t i mer (t m51) t i 50 t o 50 8bit t i mer (t m50) reset reset ct l s y stem control fl md0 regc vdd vss internal h i gh-s pee d -oscill ator ( 8mhz t yp . ) po w e r on clear (poc) high-s p e ed s ystem clock osc x1 w a tchdo g t i mer 16bit t i mer (t m00) t o 00 t i 000 t i 010 8bit t i mer (t mh0) to h 0 8bit t i mer (t mh1) to h 1 78k0 cpu core ram f l ash eeprom port12 port6 port3 port2 port1 port0 tx d 6 rxd6 uar t -lin (uar t 6 ) p00 -p01 p10 -p17 p20 -p23 p30 -p33 p60 -p61 p120 -p1 2 2 x2/ e x c l k internal l o w - s pee d -oscill ator ( 240khz t yp . ) ? n ec electron ics corpor atio n 2004 z ud-ca-05- 00 60 dat a pub lish e d oct 2004 n cp(k)
78k0/kb2 2. pin lay out 78k0/k b 2 30-pin plastic ssop (7.62mm(300)) pd 78f05 0 0 mc-5a 4 , pd78f050 1 m c-5a4 pd 78f05 0 2 mc-5a 4 , pd78f050 3 m c-5a4 q j o 4 4 0 1 1 " / * 1 " / * 1 5 * 5 0 1 5 * 1 * / 5 1 & 9 - 7 * 3 & 4 & 5 * $ ' - . % 1 9 & 9 $ - , 1 9 3 & ( $ 7 4 4 7 4 4 7 % % 7 % % 1 4 $ - 1 4 % " 1 5 * 5 0 * / 5 1 1 * / 5 1 1 * / 5 1 1 * / 5 1 1 5 * 5 0 1 5 0 ) * / 5 1 1 5 0 ) 1 3 9 % 1 5 9 % 1 4 0 1 4 * 3 9 % 1 4 $ , 5 9 % " 7 3 & ' " 7 4 4 1 " / * 1 " / * q j o 4 4 0 1 1 " / * 1 " / * 1 5 * 5 0 1 5 * 1 * / 5 1 & 9 - 7 * 3 & 4 & 5 * $ ' - . % 1 9 & 9 $ - , 1 9 3 & ( $ 7 4 4 7 4 4 7 % % 7 % % 1 4 $ - 1 4 % " 1 5 * 5 0 * / 5 1 1 * / 5 1 1 * / 5 1 1 * / 5 1 1 5 * 5 0 1 5 0 ) * / 5 1 1 5 0 ) 1 3 9 % 1 5 9 % 1 4 0 1 4 * 3 9 % 1 4 $ , 5 9 % " 7 3 & ' " 7 4 4 1 " / * 1 " / * ? n ec electron ics corpor atio n 2004 z ud-ca-05- 00 60 dat a pub lish e d oct 2004 n cp(k)
78k0/kb2 3. pin function table (1/2 ) pin name function vdd positive p o w e r suppl y e x cept for ports (e xcep t p20-p23) an d ad converter vss ground p o tenti a l e x ce pt for ports (ex c e p t p2 0-p23) a nd ad converter reset s y stem res e t input flmd0 flash eepro m programmi n g mode settin g regc conn ectin g reg u lator o u tput stabil i zation capacitor. co n nect to gnd via a capacit or (0.47 f) a v ref a/d converter anal og p o w e r s uppl y and p o w e r supp l y for p 20-p2 3 a vss ground p o tenti a l for a/d conv erter and p2 0 - p23. i/o port p00 /t i000 extern al co unt clock inp u t to 16-bit timer/eve n t counter 00 captur e trigger input to captur e registers (cr 000, cr 010) of 16-bit timer/event co unter 00 (t m00) i/o port captur e trigger input to captur e register (cr 0 00) of 16-b i t timer/event counter 0 0 (t m00) p01 /t i010 /t o00 16-bit timer/ev ent counter 0 0 output (t m00) i/o port clock in put/ ou tput for serial i n terface (csi1 0 ) p10 /sck10 /t xd0 serial d a ta out put from as ync h ron ous seri al i n terface (uar t 0 ) i/o port se ri a l da ta i npu t to serial inte rface (csi10) p1 1 /si10 /rx d 0 serial d a ta in p u t to as y n c h ro nous ser i al i n te rface (uart 0 ) i/o port p12 /so10 serial d a ta out put form serial interface (csi1 0 ) i/o port p13 /t xd6 serial d a ta out put from as ync h ron ous seri al i n terface (uar t 6 ) i/o port p14 /rx d 6 serial d a ta in p u t to as y n c h ro nous ser i al i n te rface (uart 6 ) i/o port p15 /t oh0 8-bit timer h0 output (t mh0) i/o port 8-bit timer h1 output (t mh1) p16 /t oh1 /in t p 5 extern al i n terru pt request in pu t w i th sp ecifia bl e valid edg es i/o port extern al co unt clock inp u t to 8- bit timer/event counter 50 (t m50) p17 /t i50 /t o50 8-bit timer/eve n t counter 50 o u tput (t m50) ? n ec electron ics corpor atio n 2004 z ud-ca-05- 00 60 dat a pub lish e d oct 2004 n cp(k)
78k0/kb2 t a ble ( 2/2) pin name function p20- p23 / ani0- ani3 i/o ports a/d converter anal og i nput p30/int p 1 p31/int p 2 p32/int p 3 i/o port extern al i n terru pt request in pu t w i th sp ecifia bl e valid edg es i/o port extern al co unt clock inp u t to 8- bit timer/event counter 51(t m 51) 8-bit timer/eve n t counter 51 o u tput (t m51) p33 /t i51 /t o51 /in t p 4 extern al i n terru pt request in pu t w i th sp ecifia bl e valid edg es i/o port (n-ch open drain) p60 /scl0 clock in put/ ou tput for serial i n terface (iic0) i/o port (n-ch open drain) p61 /sda0 serial data input/ output fo r serial i n terface ( iic0) i/o port extern al i n terru pt request in pu t w i th sp ecifia bl e valid edg es p120 /in t p 0 /ex l vi refere nce voltage i nput for l o w v o lt ag e indi cator i/o port (an ex ternal oscillat ion circuit is not used) p121 /x 1 conn ectin g res onator for mai n s y stem clock oscill ation i/o port (an ex ternal oscillat ion circuit is not used) conn ectin g res onator for mai n s y stem clock oscill ation p122 /x 2 /ex c lk extern al cl ock i nput fo r main s y stem clock ? n ec electron ics corpor atio n 2004 z ud-ca-05- 00 60 dat a pub lish e d oct 2004 n cp(k)
78k0/kb2 4. memory sp ace 78k0/kb2 ha ve 64kb line a r add re ss a r e a . common ro m b an k rom p r o d u c t s r o m si z e addr e s s a d d r e s s num b er o f ban k pd78f050 3 32kb 0000 h-7fff h (32kb) - - pd78f050 2 24kb 0000 h-5fff h (24kb) - - pd78f050 1 16kb 0000 h-3fff h (16kb) - - pd78f050 0 8kb 0000 h-1fff h (8kb) - - 5. clock 78k0/kb2 have 2 type intern al oscilla tor and 2 ty pe external re so nator o s cillati on ci rcuit. 78k0/kb2 ca n be op erate d internal hi gh-sp eed o s cilla to r only. internal l o w-spe ed o scill a t or ca n con n e c t to watch do g time r and 8 b it timer (tm h 1 ) on ly for high se cu re. fig. clo ck co nne cting blo c k imag e internal high-s p e ed oscillator ( 8mhz t yp ) high-s p e ed s y stem clock oscill ation circ u i t (1-20mhz) w a tchdo g time r cpu periph era l internal lo w - sp ee d oscill ator (240khz t y p) 8bit timer (tmh 1 ) mpx mpx external r e sonat or or ex ter nal clock ? n ec electron ics corpor atio n 2004 z ud-ca-05- 00 60 dat a pub lish e d oct 2004 n cp(k)
78k0/kb2 6. outline of functions of kb2 p d 78 f0 50 0 p d 78 f0 50 1 p d 78 f0 50 2 p d 78 f0 50 3 flash memor y 8 k 16k 24k 32 k b a n k - - - - internal memory (b y t e ) high speed ra m 5 1 2 7 6 8 1 k extend ram - c e r a m i c / c r y s tal - 1 to 20 m h z: v dd = 4.0 to 5.5 v - 1 to 10 m h z: v dd = 2.7 to 5.5 v - 1 to 5 mhz: v dd = 1.8 to 5.5 v main s y stem clock inter nal oscillator - 8 mhz( ty p.) s u b s y s t e m c l o c k - inter nal low speed oscillator (for tmh1, w d t ) - 240 khz(t y p. ) minimum instruction c y cle - 0.1 s (cera m ic/ cr y s tal operation f xh = 20 mhz v dd = 4.0 to 5.5 v) i / o total :23 - c m o s i / o : 2 1 - n - c h o . d . : 2 timer - 16 bit timer/ev ent counte r :1ch - 8 bit timer/eve n t counter :2ch - 8 bit timer:2ch - watch dog tim e r:1ch t i m e r o u t p u t -5(pw m : 3 ) p c l o u t p u t - b u z z e r o u t p u t - a/d converte r - 10bit x 4ch serial interface - uart ( w ith lin - bus):1ch - csi/ uar t :1ch - i 2 c:1ch multiplier / div i der - internal 16 interrup t e x t e r n a l 6 k e y r e t u r n - on chip de bug function product name un decided voltage range v dd = 1.8 to 5.5 v oper ation tempe r ature ta = -40 c to +8 5 c package - 30pin ssop ( 7. 62mm(300 )) ? n ec electron ics corpor atio n 2004 z ud-ca-05- 00 60 dat a pub lish e d oct 2004 n cp(k)
78k0/kb2 1 2 3 4 v o l t a ge applica tion w a veform a t input pin w a v e f o r m distor tion due to input noise or a reflected w a v e ma y cause malfunction. if the input of the cmos de vice sta ys in the area betw een v il (max) and v ih (min) due to noise , etc., the de vice ma y malfunction. t a k e care to pre v ent chatter ing noise from enter ing the de vice when the input le v el is fix ed, and also in the tr ansition per iod when the input le v el passes through the area betw een v il (max) and v ih (min). handling of unused input pins unconnected cmos de vice inputs can be cause of malfunction. if an input pin is unconnected, it is possib le that an inter nal input le v el ma y be gener ated due to noise , etc., causing malfunction. cmos de vices beha v e diff erently than bipolar or nmos de vices . input le v els of cmos de vices m ust be fix ed high or lo w b y using pull-up or pull-do wn circuitr y . each un used pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to un used pins m ust be judged separ ately f or each de vice and according to related specifications go v e r ning the de vice . preca ution a gainst esd a strong electr ic field, when e xposed to a mos de vice , can cause destr uction of the gate o xide and ultimately deg r ade the de vice oper ation. steps m ust be tak en to stop gener ation of static electr icity as m uch as possib le , and quic kly dissipate it when it has occurred. en vironmental control m ust be adequate . when it is dr y , a humidifier should be used. it is recommended to a v oid using insulators that easily b uild up static electr icity . semiconductor de vices m ust be stored and tr anspor ted in an anti-static container , static shielding bag or conductiv e mater ial. all test and measurement tools including w o r k benches and floors should be g rounded. the oper ator should be g rounded using a wr ist str ap . semiconductor de vices m ust not be touched with bare hands . similar precautions need to be tak en f or pw boards with mounted semiconductor de vices . st a tus before initializa tion p o w er-on does not necessar ily define the initial status of a mos de vice . immediately after the po w er source is tur ned on, de vices with reset functions ha v e not y et been initializ ed. hence , po w er-on does not guar antee output pin le v els , i/o settings or contents of registers . a de vice is not initializ ed until the reset signal is receiv ed. a reset oper ation m ust be e x ecuted immediately after po w er-on f or de vices with reset functions . po wer on/off seq uence in the case of a de vice that uses diff erent po w er supplies f or the inter nal oper ation and e xter nal interf ace , as a r ule , s witch on the e xter nal po w er supply after s witching on the inter nal po w er supply . when s witching the po w er supply off , as a r ule , s witch off the e xter nal po w er supply and then the inter nal po w er supply . use of the re v erse po w er on/off sequences ma y result in the application of an o v er v oltage to the inter nal elements of the de vice , causing malfunction and deg r adation of inter nal elements due to the passage of an abnor mal current. the correct po w er on/off sequence m ust be judged separ ately f or each de vice and according to related specifications go v e r ning the de vice . input of signal during po wer off st a t e do not input signals or an i/o pull-up po w er supply while the de vice is not po w ered. the current injection that results from input of such a signal or i/o pull-up po w er supply ma y cause malfunction and the abnor mal current that passes in the de vice at this time ma y cause deg r adation of inter nal elements . input of signals dur ing the po w er off state m ust be judged separ ately f or each de vice and according to related specifications go v e r ning the de vice . notes for cmos devices 5 6 wind o w s an d wind o w s nt are eith er r e g i stered t r ad em a r ks or tra d ema r ks of mic r os of t corpora t ion i n the unite d s t a t e s a nd/or oth e r c ountrie s . pc/ a t is a tra d emar k o f in tern atio n a l busin ess mach i n es co rp o r atio n . hp90 00 se ries 700 an d hp-u x are trad e m a r ks o f he w l ett-pack ard co m p an y . sp a r cst a tio n is a trad emar k o f sp a rc in tern atio n a l, inc. so laris an d su n o s are trad emar ks o f su n micro syste m s, in c. supe rfla s h ? is a registered tradem ark of silicon s t orage t echnology , inc. in several countries includin g the united s t ate s and ja p an . ? n ec electron ics corpor atio n 2004 z ud-ca-05- 00 60 dat a pub lish e d oct 2004 n cp(k)
78k0/kb2 cautio n: t h is p roduct uses su p erf l ash ? technol o gy l i cen s ed from silico n s t ora g e t ech nolo gy , inc. the information contained in this document is being issued in advance of the production cycle for the product. the parameters for the product may change before final production or nec electronics corporation, at its own discretion, may withdraw the product prior to its production. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special", and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics products before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. i f customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m 5 0 2 . 11-1 (1) (2) "nec electronics" a s used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": ? n ec electron ics corpor atio n 2004 z ud-ca-05- 00 60 dat a pub lish e d oct 2004 n cp(k)
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