,. analog w devices low cost general purpose analog- to-digital converter preliminary technical data features 12 bit resolution and accuracy very high performance/cost ratio monotonic from ooc to +50c 40j,ls conversion time low profile module parallel and serial outputs ttl/dtl logic levels user selected input ranges input buffer option available general description the adc-12qz is a 12-bit successive approximation type general purpose analog-to-digital converter that offers mod- erate speed and good performance at very low cost. analog devices' proprietary monolithic quad switches and a unique combination of thin film and hybrid technology have been incorporated in the adc-12qz, resulting in a converter that has the basic performance of a much higher priced unit. it is monotonic (no missing codes) from ooc to +50c, and has a maximum error of :tvzlsb relative to full scale. the adc- 12qz is packaged in a convenient, small, low profile module, and all of its logic inputs and outputs are fully ttl/dtl compatible. easy to use the adc-12qz was designed specifically to make it easy to use. it contains its own temperature-compensated precision voltage reference, and any of four input ranges (0 to +10v, :tl0v, 0 to +5v, :t5v) can be selected with jumpers and con- nections at the module terminals. if a high input impedance is required, the adc-12qz can be special ordered with an in- put buffer. binary output coding is used for unipolar operation, but for operation in the bipolar mode, the parallel output data can be either two's complement or offset binary at the user's option. the two codes differ only in that the msb output (pin 72) is used for offset binary coding, while its complement, msb (pin 70) is used for two's complement coding. status, which in- dicates when the parallel output data is valid, and its comple- ment, status, are both available. a latched serial output having a nonreturn-to-zero (nrz) for- mat is taken from the output of a ttl flip-flop. the serial data is transmitted msb first in binary code for unipolar r-' information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implica- tion or otherwise under any patent or patent rights of analog devices. ---1 i ~ j i i """ -~-- operation and in offset binary code for bipolar operation. the strobe output is used to synchronize the serial data with a receiving shift register. timing as shown in figure 1, the leading edge ("0" to "1" transition) of the convert command pulse sets the status and msb out- puts to the "1" state, and the outputs of bits 2-12 to "0". the conversion program begins on the trailing edge of the convert command pulse with the starting of the internal clock. the bit decisions are made on successive "1" to "0" clock pulse transi- tions, with the msb decision occurring first. the 200ns wide strobe pulses are used to synchronize the transmission of serial data. serial data bits are valid on successive leading edges ("0" to "1" transitions) of the strobe pulses. at the completion of the conversion, the status output returns to zero, signaling that the parallel output data is valid. cg~~er:..n previous word, 0011 .. 0 new word. 010111101000 status ..j l clock strobe bit 1 imsbi bit 2 : i n i i i i i hl i i i i '---' bit 3 , i ,', i i i i i i l j l i i i un bit 4 i i i i i :-+--t l...jr1lj', bit 12 ilsbi serial out figure 1. adc-12qz timing diagram route 1 industrial park; p.o. box 280; norwood, mass. 02062 tel: 617/329-4700 twx: 710/394-6577 -- obsolete
.. high performance general purpose aid converters adc-qm, adc-qu general description these converters are characterized primarily by hig!! performance and general utility. the use of j..i.dadb> mono- lithic quad switches with j..i.dac monolithic thin film resistance networks provide these converters with the best stability and linearity generally available. prices are kept at moderate levels by large volume manufacturing. adc-qm the adc-qm is a high performance, general purpose aid con- verter packaged in a low profile 2" x 4" module. it offers ex- cellent stability over both time and temperature at moderate cost. it is complete with an input buffer, and the desired input range is selected by the user with jumpers and connections at .the module terminals. the digital output code of the binary version is natural binary for a unipolar input, but is selected by the user to be either offset binary or two's complement with a bipolar input. the adc-qm is available in 8, 10, and 12 bit versions. adc-qu the adc-qu is a modular analog-to-digital converter that is very similar to the adc-qm, except that it offers an appre- ciably shorter conversion time. the 12 bit version performs a conversion in 15j..1.s maximum. the adc-qu's speed is the re- sult of the use of analog devices' ad55 1 j..i.dac8> high speed quad current switches in its internal dac. the adc-qu is pin-compatible with the adc-qm, and in most applications can serve as a direct plug-in replacement for it. when mounted on an ac445 1 mounting card, the adc-qu becomes a pin- compatible substitute for the older model adc-u. bwck diagram adc-qm & adc-qu 1 "5 3ok look ~ gain -15 i ',5v 3meg look ~ zero -15 .15v 211 0.- '5 29 1 00i't gro 3o~ )61 r. note: in the adc-8qm and adc-8qu, bit 8 is the lsb, and pins 48,50,52 and 54 are deleted. in the adc-i0qm and adc-ioqu, bit 10 is the lsb, and pins 48 and 50 are deleted. data acquisition applications an adc-qm or an adc-qu can be combined with a sha-ia or sha-2a sample-and-hold amplifier, and one or more mpx- 8a multiplexers to form a data acquisition subsystem. the table below shows the maximum throughput rates (conversions! sec) that can be achieved using various combinations of these products. the settling time of the mpx-8a does not affect the throughput rate because it can be settling on a new input signal at the same time the aid converter is converting the signal being held constant by the sample-and-hold amplifier. adc adc-12qm adc-12qm adc-12qu adc-12qu sha sha-ia sha-2a sha-ia sha-2a max. throughput rate 34khz 39khz 50khz 67khz ordering guide: adc-qm and adc-qu adc-xx xx /xxx no. of bits "'8 10 12 series om qu output code bin (binary) bcd (binary) coded decimal) 92 converters obsolete
~ specification summary (typical @ +25c unless otherwise noted) model adc-qm adc-qu resolution, bits s, 10, 12 linearity error :t1f2lsb analog input ranges! (volts) u.5, :t5, :tlo, +10,+5 * input impedance without buffer2 with buffer conversion time digital control inputs & outputs data outputs outpu t codes standard optional status or busy output serial data output temperature coefficient gain (of reading) offset (unipolar) (bipolar) power required package style package size price (1-9) 2.5k - 10k ohms 108 ohms lsps 22ps 25ps ttl/dtl compatible ttl positive true bin, obn, 2sc bcd "1" during conversion no * yes 5ppm/c 50pv/c 75pv/c +15v @ 25ma -15v@35ma +5v @ 200ma c-3 2" x 4" x 0.4" * * +15v @ 25ma -15v @ soma +5v @ 300ma * adc-sqm $250. adc-10qm $280. adc-12qm $305. adc-squ adc-10qu adc-12qu $260. $290. $315. i the desired input range is selected by the user with connections and jumpers at the module terminals. 2 input impedance without buffer is proportional to input voltage range. .specifications same as for adc-qm. timing diagram adc-qu --11-1o0n5 min convert command ~"i '0' i !: ti r if i i ~ i i r+-t '0' : i hl i i i i ~i i i i i ( lsb 1 ii h i j i ..;. i t1 co~~~~,~!or :ij,~iu - - - - - - - --lt~ ( return to zero ) serial output status clock msb 2sa 3sb 4sb 5sb prev code, 10110...1 new code, 01010...1 i -- converters 93 * 6.4ps bps 15ps * .. * timing diagram adc-qm --1 100nsec min convert j command ii l-status clock :vililllllllllllill ----- msb 'iiiiiii'iiii 11111111111 2sb 3sb 'i'i'ii'iii 4sb '0' ii i i i i ri i1ii1111 i i, ': i i i i i i i i i i : : i 5sb i ii i ii : i i i i i i i i i i i i i i ii i i i i i i i i i i i i i i i ii i i i i i i i i i i i i "7l ii1i i ii" iii r lsb '0' '1' r comparator 1 2 3 4 5 6 7 b 9 10 11 12 output obsolete
+15 .- v" gain -15 ~::.;)~,.,.~.~",.""",..,i,." ? +15v ~ 3meg > 4'vv' r zero ~ -15 block diagram adc-qm & adc-q u jok msb 61 58 56 54 52 50 48 status 43 3 4 5 6 ref precjsion dac . (pdac ic's plus thin film resistor network) 32 33 34 35 36 comp. out ~ -. status convert cmd clock in clock out inte rnal clock - 19 20 bip/uni co ii) ~ co ii) ..j 31 clock inhibit :: in the adc-8qm and adc-8qu, bit 8 is the lsb, pins 48,50, 52 and 54 are deleted. in the adc-10qm adc-10qu, bit 10 is the lsb, and pins 48 and 50 ieleted. 22 23 msb 25 +15v 271 0--. ttl logic & registers 29 1 ~ 30 ~ grd obsolete
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