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? xicor, inc. 2000 patents pending 9900-3003.5 5/4/00 ep characteristics subject to change without notice. 1 of 17 64k x40620 block diagram command decode and control logic hv generation timing and control x decoder y decoder data register write control wp scl sda v cc v2f ail (v cc ) control signal v2mon reset logic power on and generation v 2trip + - reset low voltage v trip + - reset & watchdog timebase watchdog timer reset eeprom array (64kbits) dual voltage cpu supervisor with 64k serial eeprom features dual voltage detection and reset assertion three standard reset threshold settings. (3.1v/ 2.6v, 3.1v/1.7v, 2.9v/2.3v) adjust low voltage reset threshold voltages using special programming sequence reset signal valid down to v cc =1v watchdog timer (150ms) power on reset (150ms) low power cmos 10? typical standby current, watchdog on 400? typical standby current, watchdog off 64kbit 2-wire serial eeprom 1mhz serial interface speed 64-byte page write mode self-timed write cycle 5ms write cycle time (typical) 2.5 to 3.7v power supply operation 8-lead tssop package description the x40620 combines several functions into one device. the ?st is a dual voltage monitoring, power-on reset control, watchdog timer and 64kbit serial eeprom memory in one package. this combination lowers system cost, reduces board space require- ments, and increases reliability. applying voltage to v cc activates the power on reset circuit which holds reset active for a period of time. this allows the power supply and system oscillator to stabilize before the processor can execute code. low v cc detection circuitry protects the users system from low voltage conditions, resetting the system when v cc falls below the set minimum vtrip point. reset is active until v cc returns to proper operating level and stabilizes. a second voltage monitor circuit (v2mon) tracks the unregulated supply to provide a power fail warning or monitors different power supply voltage. when the second monitored voltage drops below a preset v2 trip voltage. v2f ail is active until v2 returns to proper operating level and above the v2 trip voltage. five common low voltage combinations are available, however, xicors unique circuits allows the threshold for either voltage monitor to be reprogrammed to meet special needs or to ?e-tune the threshold for applica- tions requiring higher precision.
x40620 characteristics subject to change without notice. 2 of 17 package/pinouts pin names pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with other open drain or open col- lector outputs. an open drain requires the use of a pull-up resistor. write protect (wp) the wp pin should be tied high at all time. (this wp pin is reserved for internal factory testing only). reset output (reset ) reset is an active low, open drain output which goes active whenever v cc falls below the minimum vtrip sense level. it will remain active until v cc rises above the minimum vtrip sense level for 150ms. reset goes active if the watchdog timer is enabled and there is no start bit before the end of the select- able watchdog time-out period. a serial start bit will reset the watchdog timer. reset also goes active on power up at 1v and remains active for 150ms after the power supply stabilizes. v2 voltage fail output (v2fail ) v2f ail is an active low, open drain output which goes active whenever v2mon falls below the mini- mum v2trip sense level. it will remain active until v2mon rises above the minimum v2mon sense level. device operation power on reset application of power to the x40620 activates a power on reset circuit. this circuit goes active at 1v and pulls the reset pin active. this signal prevents the system microprocessor from starting to operate with insuf?ient voltage or prior to stabilization of the oscil- lator. when v cc exceeds the device v trip value for 200ms (nominal) the circuit releases reset allowing the processor to begin executing code. low voltage v cc (v1) monitoring during operation, the x40620 monitors the v cc level and asserts reset if supply voltage falls below a pre- set minimum v trip . the reset signal prevents the microprocessor from operating in a power fail or brownout condition. the reset signal remains active until the voltage drops below 1v. it also remains active until v cc returns and exceeds v trip for 200ms. when the internal low voltage detect circuitry senses that v cc is low, the following happens: the reset pin goes active. communication to the device is interrupted and any command is aborted. if a serial nonvolatile store is in progress when power fails, the circuitry does not stop the nonvolatile store operation, but attempts to complete the operation. the low v cc threshold is typically set to 3.1v for a 2.5 to 3.7v operating range. low voltage v2 monitoring the x40620 also monitors a second voltage level and asserts v2f ail if the voltage falls below a preset mini- mum v2 trip . the v2f ail signal is either ored with reset to prevent the microprocessor from operating in a power fail or brownout condition or used to inter- rupt the microprocessor with noti?ation of an impend- ing power failure. the v2f ail signal remains active until the v cc drops below 1v. it also remains active until v2mon returns and exceeds v2 trip by 0.2v v ss ground sda serial data v cc power scl serial clock wp write protect v2mon voltage monitor input reset low voltage detect output v2fail v2 voltage fail output wp v cc v2f ail scl v ss v2mon sda reset 3 2 4 1 6 7 5 8 8l tssop
x40620 characteristics subject to change without notice. 3 of 17 when the internal low voltage detect circuitry senses that v2mon is low, the v2f ail pin goes active. typi- cally this would be used by the processor as an inter- rupt to stop the execution of the code or to do housekeeping in preparation for an impending power failure. the reset and v2f ail signals remain active until v cc voltage drops below 1v. reset remains active until v cc returns and exceeds v trip for 200ms. v2f ail remains active until immediately after v2mon returns and exceeds its minimum voltage. watchdog timer the watchdog timer circuit monitors the microproces- sor activity by monitoring the start bit. the micropro- cessor must send a start bit periodically to prevent a reset signal. the start bit must occur prior to the expiration of the watchdog time-out period. the watch- dog timer period is set at 150msec. serial memory operation there are two primary modes of operation for the x40620; read and write of the memory arrays. the basic method of communication to the memory areas of the device is established by generating a start condition, then transmitting a command, followed by the address. the user must perform ack polling to determine the validity of the address, before starting a data transfer (see acknowledge polling.) data is transferred in 8-bit segments, with each trans- fer being followed by an ack, generated by the receiv- ing device. if the x40620 is in a nonvolatile write cycle a ?o ack (sda=high) response will be issued in response to loading of the command byte. if a stop is issued prior to the start of a nonvolatile write cycle the write opera- tion will be terminated and the part will reset and enter into a standby mode. the basic sequence is illustrated in figure 1. after each transaction is completed, the x40620 will reset and enter into a standby mode. figure 1. x40620 device operation v2f ail reset v ss v2mon scl wp sda v cc volt reg v cc scl sda intr reset ? otp mode enabled recommended connection pin 1 load command byte load 2 byte address read/write data bytes twc or data ack polling
x40620 characteristics subject to change without notice. 4 of 17 figure 2. set v trip level sequence (v cc v trip ) figure 3. set v2 trip level sequence (v cc v2 trip ) figure 4. reset v trip level sequence (v cc > 3v, wel is set.) sda d8h 00h reset v p = 15v 01h v trip v cc 01h sets v cc scl 01234567 01234567 01234567 01234567 00h sda d8h 00h reset v p = 15v 0dh v2 trip v2mon 0dh sets v2mon scl 01234567 01234567 01234567 01234567 00h sda d8h 00h reset v p = 15v v trip v cc 03h 03h resets v cc scl 01234567 01234567 01234567 01234567 00h
x40620 characteristics subject to change without notice. 5 of 17 figure 5. reset v2 trip level sequence (v cc > 3v, wel is set.) sda d8h 00h reset v p = 15v v trip v cc 03h 03h resets v cc scl 01234567 01234567 01234567 01234567 00h v cc and v2mon threshold reset procedure the x40620 is shipped with standard v trip and v2 trip voltages. these values will not change over normal operating and storage conditions. however, in applications where the standard thresholds are not exactly right, or if higher precision is needed in the threshold value, the x40620 trip points may be adjusted. the procedure is described below, and uses the application of a high voltage control signal. setting the v trip voltage this procedure is used to set the v trip ,v2 trip to a higher voltage value. for example, if the current v trip is 4.4v and the new v trip is 4.6v, this procedure will directly make the change. if the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value. to set the new voltages, apply the desired v trip thresh- old v oltage to the v cc pin, the v2 trip voltage to the v2mon pin, then tie the reset pin to the programming voltage v p . then, write data 01h or 0dh at address 00h to program v trip , v2 trip respectively. the stop bit following a valid write operation initiates the pro- gramming sequence. bring reset low to complete the operation. note: this operation also writes 01h or 0dh to address 00h. resetting the v trip voltage this procedure is used to set the v trip , the v2 trip to a ?ative voltage level. for example, if the current v trip is 4.4v and the new v trip must be 4.0v, then the v trip must be reset. when the threshold is reset, the new level is something less than 1.7v. this proce- dure must be used to set the voltage to a lower value. to reset the new v trip , v2 trip voltage, apply the desired v trip or v2 trip threshold voltage to the v cc or v2mon pin, respectively, and tie the reset pin to the programming voltage v p . then write 03h or 0fh to address 00h. the stop bit of a valid write opera- tion initiates the programming sequence. bring reset low to complete the operation. note: this operation also writes 03h or 0fh to address 00h of the eeprom array. figure 6. sample v trip reset circuit 5 4 7 1 8 2 6 3 x40620 v trip adj. v p reset 4.7k sda scl ? adjust run v2fail v2 trip adj.
x40620 characteristics subject to change without notice. 6 of 17 v trip /v2 trip programming apply 5v to v cc or v2mon decrement v cc reset goes active? measured v(2) trip - desired v(2) trip done execute sequence reset v trip /v2 trip set v cc = v cc applied = desired v trip or execute sequence set v trip, v2 trip new v cc or v2mon applied = old v cc v2mon applied + error (<50mv step) execute sequence reset v2 trip , v trip new v cc /v2mon applied = old v cc applied?rror error < 0 error = 0 yes no error > 0 set v2mon = v2mon applied = desired v2 trip, v cc >=v2trip or v2mon or v2fail pin recycle v cc power
x40620 characteristics subject to change without notice. 7 of 17 device protocol the x40620 supports a bidirectional bus oriented pro- tocol. the protocol de?es any device that sends data onto the bus as a transmitter and the receiving device as a receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initiate data transfers and pro- vide the clock for both transmit and receive operations. therefore, the x40620 will be considered a slave in all applications. after each byte written to or read from the x40620, the address pointer is incremented by 1. this allows the user to read from the entire device after sending only a single address. it also allows an entire page to be writ- ten in one operation. an exception to this address incrementation occurs during a read. after reading address 1fffh the device goes into an idle mode, so additional reads return all ?s? clock and data conventions data states on the sda line can change only during scl low. sda changes during scl high are reserved for indicating start and stop conditions. refer to figure 7 and figure 8. start condition all commands are preceeded by the start condition, which is a high to low transition of sda when scl is high. the x40620 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition is met. a start may be issued to terminate the input of a con- trol byte or the input data to be written. this will reset the device and leave it ready to begin a new read or write command. a start bit generated while the part is outputting data is accepted as a start as long as the device is not outputting a ?ero? stop condition all communications are be terminated by a stop condi- tion. the stop condition is a low to high transition of sda when scl is high. the stop condition is also used to reset the device during a command or data input sequence and will leave the device in the standby power mode. as with starts, stops are recog- nized while the device outputs data, as long as the data output is not a ?ero? figure 7. data validity figure 8. definition of start and stop conditions acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data. the x40620 will respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write condition have been selected, the x40620 will respond with an acknowledge after the receipt of each subsequent eight-bit word. scl sda data data change stable scl sda start condition stop condition table 1. x40620 instruction set notes: illegal command codes will be disregarded. the part will respond with a ?o-ack to the illegal byte and then return to the sta ndby mode. 1st byte after start 1st byte after command 2nd byte after command command description 1100 1000 high address low address memory array read 1101 1000 high address low address memory array write
x40620 characteristics subject to change without notice. 8 of 17 program operations memory array programming the memory array program mode requires issuing the 8-bit write command followed by the address and then the data bytes transferred as illustrated in figure 9. up to 64 b ytes (or more) may be transferred. sending more than 64 bytes results in data wrapping and over-writing previ- ous data. after the last byte to be transferred is acknowledged a stop condition is issued which starts the nonvolatile write cycle. figure 9. memory array programming start command ack s sda ack ack a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ack data 0 data 63 ack ack s wait t wc data ack stop ?? polling write ack polling once a stop condition is issued to indicate the end of the hosts write sequence, the x40620 initiates the internal nonvolatile write cycle. in order to take advan- tage of the typical 5ms write cycle, ack polling can begin immediately. this involves issuing the start con- dition followed by the new command code of 8 bits (1st byte of the protocol.) if the x40620 is still busy with the nonvolatile write operation, it will issue a ?o-ack in response. if the nonvolatile write operation has com- pleted, an ?ck will be returned and the host can then proceed with the rest of the protocol. data ack polling sequence ack returned ? issue new command code write sequence completed enter ack polling issue start no yes proceed
x40620 characteristics subject to change without notice. 9 of 17 figure 10. acknowledge polling 8th clk ?ck clk 8th clk ?ck clk ?ck start condition 8th bit ack or no ack scl sda memory read operations memory read operations are initiated in the same manner as write operations but with a different com- mand code. random read the master issues the start condition, then a read instruction, then issues the word address. once the ?st byte has been read, another start can be issued followed by a new 8-bit address. see figure 11. sequential read the host can read sequentially within the memory array after receiving the read command and an address within the address space. the data output is sequential, with the data from address n followed by the data from n+1. the address counter for read oper- ations increments all address bits, allowing the entire memory array contents to be serially read during one operation. at the end of the address space (address 1fffh) the device goes into an idle state and a new read sequence must be initiated to continue reading at another address. refer to figure 12 for the address, acknowledge and data transfer sequence. an acknowl- edge must follow each 8-bit data transfer. after the last bit has been read, the host sends a stop condition with or without a preceding acknowledge. figure 11. random read figure 12. sequential read s ack stop a7 a6 a5 a4 a3 a2 a1 a0 data 0 s start start command ack s sda ack ack a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 0 read data x ack s start command ack s sda ack ack a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ack data 0 stop read
x40620 characteristics subject to change without notice. 10 of 17 absolute maximum ratings temperature under bias ................... ?5? to +135? storage temperature ........................?5? to +150? voltage on any pin with respect to v ss ..... ?v to +7v d.c. output current ............................................... 5ma lead temperature (soldering, 10 seconds).........300? comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this speci?ation) is not implied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. recommended operating conditions temp min. max. commercial 0? +70? extended ?0? +85? device supply voltage limits x40620 2.5v to 3.7v d.c. operating characteristics (over the recommended operating conditions unless otherwise speci?d.) capacitance (t a = +25?, f = 1mhz, v cc = 3v) notes: (1) must perform a stop command after a read command prior to measurement (2) v il min. and v ih max. are for reference only and are not tested. (3) this parameter is periodically sampled and not 100% tested. symbol parameter limits units test conditions min. max. i cc1 v cc supply current (read) 1 ma f scl = 1mhz, reset = v2fail = v cc w/ pull up resistor v 2mon = v cc i cc2 (3) v cc supply current (write) 3 ma f scl = 1mhz, reset = v2fail = v cc w/ pull up resistor rst = v ss i sb1 (1) v cc supply current (standby) 50 ? v il = v cc x 0.1, v ih = v cc x 0.9 f scl = 1mhz, f sda = 400 khz i sb2 (1) v cc supply current (standby) 1 a v sda = v scl = v 2mon = v cc other = gnd or v cc ?.3v i li input leakage current 10 ? v in = v ss to v cc i lo output leakage current 10 ? v out = v ss to v cc v il1 (2) input low voltage ?.5 v cc x 0.3 v v cc = 3.0v v ih1 (2) input high voltage v cc x 0.7 v cc + 0.5 v v cc = 3.0v v il2 (2) input low voltage ?.5 v cc x 0.1 v v cc = 3.0v v ih2 (2) input high voltage v cc x 0.9 v cc + 0.5 v v cc = 3.0v v ol output low voltage 0.4 v i ol = 3ma symbol test max. units conditions c out (3) output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (wp, scl, v 2mon ) 6 pf v in = 0v
x40620 characteristics subject to change without notice. 11 of 17 equivalent a.c. load circuit a.c. test conditions 3v 1.3k ? output 100pf input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 output load 100pf ac characteristics ac specifications (over the recommended operating conditions) reset ac specifications nonvolatile write cycle timing notes: (1) t wc is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used. symbol parameter min. typ. (1) max. units f scl scl clock frequency 0 1000 khz t in pulse width of spikes which must be suppressed by the input filter 10 ns t aa scl low to sda data out valid 0.05 0.55 s t buf time the bus must be free before a new transmit can start 0.5 s t low clock low time 0.6 s t high clock high time 0.4 s t su:sta start condition setup time 0.25 s t hd:sta start condition hold time 0.25 s t su:dat data in setup time 100 ns t hd:dat data in hold time 0 s t su:sto stop condition setup time 0.25 s t dh data output hold time 0 100 ns t r sda and scl rise time (10% to 90% of v cc ) 10 100 ns t f sda and scl fall time 10 100 ns symbol parameter min. typ. (1) max. units t wc (1) write cycle time 5 10 ms
x40620 characteristics subject to change without notice. 12 of 17 timing diagrams bus timing write cycle timing guidelines for calculating typical values of bus pull up resistors t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t aa t r scl sda t wc 8th bit of last byte ack stop condition start condition 50 40 30 20 10 bus capacitance in pf pull up resistance in k ? rmin r pmax 2 4 6 8 10 for v ih = 0.9v cc r min v ccmax 0.4 i olmin ---------------------------------------- - 1100 ? = = v ih vcc 1 e t rmax r pmax c bus --------------------------------------- ?? ?? ?? ?? ?? ?? = r pmax t r 2.3 c bus () ------------------------------ - = t rmax = maximum allowable sda rise time 100ns max rise time
x40620 characteristics subject to change without notice. 13 of 17 power-up and power-down timing reset output timing v2fail output timing notes: (5) this parameter is periodically sampled and not 100% tested. (6) typical values not tested. symbol parameter min. typ. max. units v trip reset trip point voltage 2.4 3.5 v v 2trip v2fail trip point voltage 1.7 3.5 v v th v trip hysteresis (high to low vs. low to high v trip voltage) 40 mv v 2ta v 2trip hysteresis (high to low vs. low to high v trip voltage) 40 mv t purst power-up reset timeout 75 150 225 ms t dvc (5) detect v cc low voltage to reset output (v cc = 2.3v) 65 s t dvb (5) detect v 2mon low voltage to reset output (v cc = 2.5-3.7v) 100 s t fv (5) v cc fall time 100 s t rv (5) v cc rise time 100 s t fb (5) v 2mon fall time 500 n s t rb (5) v 2mon rise time 500 n s v rvalid reset valid v cc 1v v cc t purst t rv t fv t dvc reset 0 volts v vtrip v vtrip t purst v2mon v2fail t rb t fb t dvb 0 volts v 2trip v 2trip
x40620 characteristics subject to change without notice. 14 of 17 start bit vs. reset timing reset output timing symbol parameter min. typ. max. units t wdo watchdog timeout period 75 150 225 ms t wdr sda low duration (reset the watchdog) 400 ns t rst reset timeout 75 150 225 ms sda t wdr reset t wdo t rst scl t su:sta t su:sto t wdo t rst
x40620 characteristics subject to change without notice. 15 of 17 packaging information note: all dimensions in inches (in p arentheses in millimeters) 8-lead plastic, tssop, package type v see detail ? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0??8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) (4.16) (7.72) (1.78) (0.42) (0.65) all measurements are typical
x40620 characteristics subject to change without notice. 16 of 17 ordering information notes: tolerance for v trip and v 2trip are +/-5% v cc range v trip v 2trip package operating temperature range part number 2.5?.7v 3.1 2.6 8l tssop 0??0? x40620v8-3.1 -20??5? x40620v8e-3.1 2.5?.7v 3.1 1.7 8l tssop 0??0? x40620v8-3.1a -20??5? x40620v8e- 3.1a 2.5?.7v 2.9 2.3 8l tssop 0??0? x40620v8-2.9 -20??5? x40620v8e-2.9
x40620 characteristics subject to change without notice. 17 of 17 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devi ces from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue production and change s peci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xd cp are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. part mark convention 8-lead tssop eyww xxxx xx 4062 ar = v trip v 2trip temp 4062 as = 4062 at = 4062 au = 4062 av = 4062 aw = 2.6 2.6 1.7 1.7 2.3 2.3 0 to 70? -20 to 85? 0 to 70? -20 to 85? 0 to 70? -20 to 85? 3.1 3.1 3.1 3.1 2.9 2.9

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