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nt512d64s8hakw m 512mb : 64m x 64 pc210 0 / pc1600 un buffered ddr so-dimm 200pin tw o bank un buffered ddr so-dimm features ? 64mx64 doubl e unbuffer ed dd r so- d imm bas ed on 32m x8 ddr sdram. ? performance: p c 1 6 0 0 p c 2 1 0 0 speed sort - 8b - 75b - 7k dimm cas late n cy 2 2.5 2 unit f ck c l o c k frequenc y 1 0 0 1 3 3 1 3 3 mhz t ck c l o c k cy c l e 1 0 7 . 5 7 . 5 ns f dq dq bu rst freq ue ncy 200 266 266 mhz ? intended for 1 0 0 mhz and 133 mhz applications ? inputs and outp u ts are sstl- 2 compatible ? v dd = 2.5volt 0.2, v ddq = 2.5 v olt 0.2 ? sdrams have 4 internal banks for concurrent op eration ? module has tw o ph y s ical banks ? differential clock inputs ? data is read or written on both clock edges ? dram dll aligns dq and dqs transitions w i th clock transitions. ? address and control signals are fully s y nchronous to positive clock edge ? programmable oper ation: - dimm cas l a t enc y : 2, 2.5 - burst t y pe: se quential or interl eave - burst length: 2, 4, 8 - ope r ation: burs t read and w r ite ? auto-refresh ( c br) and self- r efresh modes ? automatic and controlled precha rge commands ? 13/10/2 addres sing (ro w / column /bank) ? 7.8 s max. average periodic r e fresh interval ? serial presence detect ? gold contacts ? sdrams in 60-ball csp packag e description nt512d 64s8ha k wm is an unbuffered 200 -pin do uble data rate ( ddr) sd ram s m all-outline memor y m odule (s odimm ) , orga nized as a two-bank hi gh-speed memo r y ar ra y. the 6 4 m x 64 m odule is a dual-bank dimm t hat uses sixteen 32mx8 ddr sdrams in 60-b a ll csp packages. the sod i mm achieves high-sp eed data tr ansfer rates of up to 2 6 6 mhz. the s o di mm is intended for use in applicatio ns operating fro m 100 mhz to 13 3 mhz clock spe eds w i th dat a rat e s of 200 to 266 mhz. prior to an y access operation, the device cas latency and bu rst t y pe / length/operatio n t y pe must be p r ogramme d into t he dimm b y address inputs a0-a12 and i/ o in puts ba0 and ba1 using the mode register set c y cle. the sodimm us es serial presence detects implemented via a serial eepro m using the t w o-pin ii c prot ocol. the first 1 28 b y tes of ser i al pd data are prog rammed and locked during modul e assembly . the last 128 b y tes ar e available to the customer. all nan y a 200pi n ddr s o dimm s provide a high- performa n ce, flexible 8-b y te interf ace in a 2.66? lon g space-saving footprint. ordering information part numbe r s p e e d o r g a nization leads pow e r 143mhz (7ns @ cl = 2.5) nt512d 64s8ha k wm-7k 133mhz (7.5ns @ cl= 2) pc2100 133mhz (7.5ns @ cl= 2.5) nt512d 64s8ha k wm-75b 100mhz (10ns @ cl = 2) pc2100 125mhz (8ns @ cl = 2.5) nt512d 64s8ha k wm-8b 100mhz (10ns @ cl = 2) pc1600 6 4 m x 6 4 g o l d 2 . 5 v rev 1.1 1 08/2002 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8hakw m 512mb : 64m x 64 pc210 0 / pc1600 un buffered ddr so-dimm pin description ck0, ck1, ck2, ck0 , ck1 , ck2 dif f erential clock input s. dq0 - d q 63 dat a input/outpu t cke0, cke1 clock enable ras r o w a d d r e s s s t r o b e dqs0- d qs7 , dqs9- d qs1 6 bidirectional dat a strobes cas c o l u m n a d d r e s s s t r o b e v dd p o w e r (2. 5 v ) we w r ite enable v ddq suppl y volt age fo r dqs (2.5v) s0 , s1 c h i p select s v ss g r o u n d a0-a9, a1 1, a12 address input s nc no connect a 1 0 / a p a d d r e s s input/au t o p r e c h a r g e s c l se rial presence detect clock input ba0, ba1 sdram bank address input s sda se rial presence detect dat a inpu t/output v ref ref. v o lt age for sstl_2 input s sa0-2 serial presence detect address input s v ddid v dd identification flag. v ddspd serial eeprom positive pow er s uppl y (2.5v ) pinout p i n f r o n t p i n b a c k p i n f r o n t pin b a c k pin f ront pin b ack p i n f r o n t pin b a c k 1 v ref 2 v ref 5 1 v ss 5 2 v ss 1 0 1 a 9 102 a 8 1 5 1 d q 4 2 152 dq46 3 v ss 4 v ss 5 3 d q 1 9 54 dq23 103 v ss 1 0 4 v ss 1 5 3 d q 4 3 154 dq47 5 d q 0 6 d q 4 5 5 d q 2 4 56 dq28 105 a 7 106 a 6 1 5 5 v dd 1 5 6 v dd 7 d q 1 8 d q 5 5 7 v dd 5 8 v dd 1 0 7 a 5 108 a 4 1 5 7 v dd 1 5 8 ck1 9 v dd 1 0 v dd 5 9 d q 2 5 60 dq29 109 a 3 1 1 0 a 2 1 5 9 v ss 1 6 0 c k 1 1 1 d q s 0 1 2 d m 0 6 1 d q s 3 62 d m 3 1 1 1 a 1 1 1 2 a 0 1 6 1 v ss 1 6 2 v ss 1 3 d q 2 1 4 d q 6 6 3 v ss 6 4 v ss 1 1 3 v dd 1 1 4 v dd 1 6 3 d q 4 8 164 dq52 1 5 v ss 1 6 v ss 6 5 d q 2 6 66 dq30 1 1 5 a 10/ap 1 1 6 ba1 1 6 5 d q 4 9 166 dq53 1 7 d q 3 1 8 d q 7 6 7 d q 2 7 68 dq31 1 1 7 b a 0 1 1 8 ras 1 6 7 v dd 1 6 8 v dd 1 9 d q 8 2 0 d q 1 2 6 9 v dd 7 0 v dd 1 1 9 we 120 cas 1 6 9 d q s 6 170 d m 6 2 1 v dd 2 2 v dd 7 1 n c 72 n c 121 s0 122 s1 1 7 1 d q 5 0 172 dq54 2 3 d q 9 2 4 d q 1 3 7 3 n c 74 n c 1 2 3 d u 1 2 4 d u 1 7 3 v ss 1 7 4 v ss 2 5 d q s 1 2 6 d m 1 7 5 v ss 7 6 v ss 1 2 5 v ss 1 2 6 v ss 1 7 5 d q 5 1 176 dq55 2 7 v ss 2 8 v ss 7 7 n c 78 n c 127 dq32 128 dq36 1 7 7 d q 5 6 178 dq60 2 9 d q 1 0 3 0 d q 1 4 7 9 n c 80 n c 129 dq33 130 dq37 1 7 9 v dd 1 8 0 v dd 3 1 d q 1 1 3 2 d q 1 5 8 1 v dd 8 2 v dd 1 3 1 v dd 1 3 2 v dd 1 8 1 d q 5 7 182 dq61 3 3 v dd 3 4 v dd 8 3 n c 84 n c 133 dqs4 134 dm4 1 8 3 d q s 7 184 d m 7 3 5 c k 0 3 6 v dd 8 5 d u 86 d u 135 dq34 136 dq38 1 8 5 v ss 1 8 6 v ss 37 ck0 3 8 v ss 8 7 v ss 8 8 v ss 1 3 7 v ss 1 3 8 v ss 1 8 7 d q 5 8 188 dq62 3 9 v ss 4 0 v ss 8 9 c k 2 90 v ss 1 3 9 dq35 140 dq39 1 8 9 d q 5 9 190 dq63 4 1 d q 1 6 4 2 d q 2 0 9 1 ck2 9 2 v dd 1 4 1 dq40 142 dq44 1 9 1 v dd 1 9 2 v dd 4 3 d q 1 7 4 4 d q 2 1 9 3 v dd 9 4 v dd 1 4 3 v dd 1 4 4 v dd 1 9 3 s d a 194 s a 0 4 5 v dd 4 6 v dd 9 5 c k e 1 96 cke0 145 dq41 146 dq45 1 9 5 s c l 196 s a 1 4 7 d q s 2 4 8 d m 2 9 7 d u 98 d u 147 dqs5 148 dm5 1 9 7 v ddspd 1 9 8 s a 2 4 9 d q 1 8 5 0 d q 2 2 9 9 a 1 2 100 a1 1 149 v ss 1 5 0 v ss 1 9 9 v ddid 2 0 0 d u note: all pin assignment s are con s istent for all 8-byte unbuf fe red v e rsions. rev 1.1 2 08/2002 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8hakw m 512mb : 64m x 64 pc210 0 / pc1600 un buffered ddr so-dimm input/output functional description s y mbol ty p e polarit y function ck0, ck1, ck2 (sstl) positive edge the positive line of the differential pair of sy st em clock inputs w h ich drives the input to the on-dimm pll. a ll the ddr sdram address and control inputs are sampled on the risin g edge of their ass o ciated clocks. ck0 , ck1 , ck2 ( s s t l ) negative edge the negative line of the differential pair of sy stem clock inputs w h ich drives the input to the on-dimm pll. cke0, cke1 (sstl) active high activates the sd ram ck signal w h en high and d eactivates the ck signal w hen lo w . b y deactivating the clocks, cke lo w initiates the power do wn mod e , or the self-r efresh mode. s0 , s1 (sstl) active lo w enables the associated sdram command dec ode r w hen lo w an d d i sables the com m and decoder w hen high. when the command decoder is disabled, new commands are ignore d but previous ope rations continue. ras , cas , we (sstl) active lo w when sampled at the positive rising edge of the clock, ras , cas , we define the op eration to be executed b y the sd ram. v ref s u p p l y reference voltag e for sstl - 2 inp u ts v ddq s u p p l y isolated po w e r supply for the ddr sd ram o u t put buffe rs to provide improv ed noise immunity ba0, ba1 (sstl) - select s w h ich sdram bank is to be active. a0 - a9 a10/ap a1 1, a12 (sstl) - during a ba nk activate command c y cle, a0 -a12 defines the ro w address (ra0 -ra12) w h en sampled at the rising clock edge. during a rea d or w r ite command c y cle, a0-a9 defines the column address (c a0-ca9) w h en sampled a t the rising clock edge. i n additio n to the column address, ap is u s ed to invoke autoprecharge ope ration at the end of the burst read o r w r ite cy cle. if a p is high , autoprechar ge is selected and b a 0/ba1 define the bank to be precharged. if ap is low , autoprechar ge is disabled. during a pr echarge command c ycle, ap is used in conjunction w i t h ba0/ba1 to control w h ich bank(s) to precharge. if a p is high al l 4 ba nks w ill be prech a rged rega rdless of the st ate of ba0/ba1 . if ap is low , the n ba0/ba1 are u s ed to define w h ich bank to pre-c harge. dq0 - d q 63, (sstl) - dat a and c heck bit input/output pins operate in the same man ner as on conventional drams. dq s0 - dq s7, dq s9 - dq s16 (sstl) active high data strobes: output w i th re ad data, input w i th write data. edge aligned w i th rea d data, centered on write data. used to ca pture write data. v dd, v ss s u p p l y pow e r and g r oun d for the d dr s dram input buff e rs and core logi c sa0 ? sa2 - address input s. connected to either v dd or v ss on the sy stem board to configure the serial presence detect eeprom address. sda - this bidirectional pin is used to t r ansfer data into or out of the sp d eeprom . a resisto r must be connected from the s d a bus line to v dd to act as a pullup. scl - this signal is used to clock data into and out of the spd eepr om. a resistor ma y b e connected from t he scl bus time to v dd to act as a pullup. v ddspd suppl y serial eeprom positive pow er s uppl y . rev 1.1 3 08/2002 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8hakw m 512mb : 64m x 64 pc210 0 / pc1600 un buffered ddr so-dimm functional block diagram (2 bank, 32mx8 ddr sdrams) se r i a l pd a0 a2 a1 sc l wp sd a sa0 sa2 sa1 ddr sdram : d0 , d1 , d8 , d9 ck ck pl l ddr sdram : d2 , d3 , d1 0 , d1 1 ddr sdram : d4 , d5 , d1 2 , d1 3 ddr sdram : d6 , d7 , d1 4 , d1 5 s0 dm 0 dq0 dq1 dq2 dq7 dq4 dq6 dq5 dq3 dq8 dq9 dq1 0 dq1 5 dq1 2 dq1 4 dq1 3 dq1 1 dq1 6 dq1 7 dq1 8 dq2 3 dq2 0 dq2 2 dq2 1 dq1 9 dq2 4 dq2 5 dq2 6 dq3 1 dq2 8 dq3 0 dq2 9 dq2 7 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d3 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d2 dqs0 dm 4 dq s 4 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d0 dm 1 dqs1 dqs dm 2 dqs2 dm 3 dqs3 dqs dq 32 dq 33 dq 34 dq 39 dq 36 dq 38 dq 37 dq 35 dq 40 dq 41 dq 42 dq 47 dq 44 dq 46 dq 45 dq 43 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d1 dqs dq s 5 dm 5 dq 48 dq 49 dq 50 dq 55 dq 52 dq 54 dq 53 dq 51 dq 56 dq 57 dq 58 dq 63 dq 60 dq 62 dq 61 dq 59 dq s 6 dm 6 dq s 7 dm 7 dqs s1 i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d8 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d9 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d1 0 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d1 1 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d7 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d6 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d4 dqs dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d5 dqs dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d12 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d13 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d14 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d15 dqs a0-a 12 ras ba 0 - ba1 ba 0 - ba1 : sdra m s d0 - d 1 5 a0 - a 1 2 : sdrams d0 - d 1 5 ra s : s dra m s d 0 -d15 cke0 we ca s c as : s dra m s d 0 -d15 ck e : sdram s d0 - d 7 ck e : sdram s d8 - d 1 5 we : s dra m s d 0 -d15 cke1 v ddspd v ss vr ef v ddid v dd /v ddq s t rap: s ee n o te 4 spd d0 - d 1 5 d0 - d 1 5 d0 - d 1 5 n o tes : 1. d q - t o-i/o w r i ng m a y be chang ed w i thi n a b y te. 2. d q / d qs /d m / c k e/s rel a ti onsh i ps are m a i n t a i ned as sho w n. 3. d q / d qs /d m / d q s resi stors ar e 22 ohm s . 4. v dd id strap conne cti ons (for m e m o ry devi c e v dd , v ddq ): s t r a p out (ope n): v dd = v ddq s t r a p in (v ss ): v dd i s not eq ual to v ddq . rev 1.1 4 08/2002 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8hakw m 512mb : 64m x 64 pc210 0 / pc1600 un buffered ddr so-dimm serial presence det ect -- part 1 of 2 spd entr y v a lue serial pd dat a e n tr y (he x adecimal) n ote by t e descr iption ddr266a -7k ddr266b -75b ddr200 -8b ddr266a -7k ddr266b -75b ddr200 -8b 0 number of se rial pd b y tes w r itte n during production 1 2 8 8 0 1 t o t a l numbe r of b y tes in serial pd device 256 08 2 fundament al memor y t y pe sdram ddr 07 3 number of ro w addresses on assembly 13 0d 4 number of colu mn addresses on assembly 10 0a 5 number of dimm bank 2 02 6 dat a wid t h of assembly x64 40 7 dat a wid t h of assembly (cont?) 00 8 v o lt age interface level of this assembl y sstl 2.5v 04 9 ddr sdram de vice cy cle t i me at cl=2.5 7ns 7.5ns 8ns 70 75 80 10 ddr sdram de vice access t i me from clock at cl=2.5 0 . 7 5 n s 0 . 7 5 n s 0 . 8 n s 7 5 7 5 8 0 1 1 d i m m configura t ion t y p e non-parit y 0 0 1 2 r e f r e s h rate/ t y p e sr/1x( 7 . 8 u s ) 8 2 13 primar y d dr sd ram wid t h x8 08 14 error checking ddr sdram devi ce wid t h n/a 00 15 ddr sdram de vice attr: min clk dela y , random col access 1 clock 01 16 ddr sdram de vice attributes: burst length su pported 2 , 4 , 8 0 e 17 ddr sdram de vice attributes: n u mber of device banks 4 0 4 18 ddr sdram de vice attributes: c as latencies supported 2 / 2 . 5 2 / 2 . 5 2 / 2 . 5 0 c 0 c 0 c 19 ddr sdram de vice attributes: c s latenc y 0 01 20 ddr sdram de vice attributes: we latenc y 1 02 2 1 d d r sdram de vice attribut e s : d i f f e r e n t i a l c l o c k 2 0 22 ddr sdram de vice attributes: general +/-0.2v v o lt age t o lerance 00 23 minimum clock c y cle at cl=2 7.5ns 10ns 10ns 75 a0 a0 24 max i mum dat a a ccess t i me from clock at cl=2 0 . 7 5 n s 0 . 7 5 n s 0 . 8 n s 7 5 7 5 8 0 25 minimum clock c y cle t i me at cl =1 n/a 00 26 max i mum dat a a ccess t i me from clock at cl=1 n / a 0 0 27 minimum row p r echarge t i me (t rp ) 2 0 n s 2 0 n s 2 0 n s 5 0 5 0 5 0 28 minimum row a c tive to row active dela y (t rrd ) 1 5 n s 1 5 n s 1 5 n s 3 c 3 c 3 c 29 minimum ras to cas dela y (t rcd ) 2 0 n s 2 0 n s 2 0 n s 5 0 5 0 5 0 30 minimum ras pulse wid t h (t ras ) 4 5 n s 4 5 n s 5 0 n s 2 d 2 d 3 2 31 module bank de nsity 256mb 40 32 address and co mmand setup t i me before clock 0 . 9 n s 0 . 9 n s 1 . 1 n s 9 0 9 0 b 0 33 address and co mmand hold t i m e af ter clock 0 . 9 n s 0 . 9 n s 1 . 1 n s 9 0 9 0 b 0 34 dat a input set u p t i me before clo ck 0.5ns 0.5ns 0.6ns 50 50 60 35 dat a input hold t i me af ter clock 0.5ns 0.5ns 0.6ns 50 50 60 3 6 - 6 1 r e s e r v e d u n d e f i n e d 0 0 6 2 spd r e v i s i o n i n i t i a l i n i t i a l i n i t i a l 0 0 0 0 0 0 6 3 c h e c k s u m dat a 9 0 c 0 4 6 rev 1.1 5 08/2002 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8hakw m 512mb : 64m x 64 pc210 0 / pc1600 un buffered ddr so-dimm serial presence det ect -- part 2 of 2 spd entr y v a lue serial pd dat a e n tr y (he x adecimal) by t e descr iption ddr266a -7k ddr266b -75b ddr200 -8b ddr266a -7k ddr266b -75b ddr200 -8b note 64-71 manufacturer ? s jedec id code nan y a 7f7f7 f 0b00000 000 72 module manufact u ring location n/a 00 73-90 module part num ber n/a n/a n/a 00 00 00 9 1 - 9 2 m o d u l e revision c o d e n / a 0 0 93-94 module manufact u ring dat a y ear/w eek code yy/ ww 1, 2 95-98 module serial number serial number 00 9 9 - 2 5 5 r e s e r v e d u n d e f i n e d 0 0 1. yy= binar y code d decimal y e a r c ode, 0-99 (decimal), 00-63 (he x ) 2. ww = bina r y code d decimal y e a r c ode, 01-52 (decimal), 01-34 (he x ) rev 1.1 6 08/2002 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8hakw m 512mb : 64m x 64 pc210 0 / pc1600 un buffered ddr so-dimm absolute maximum ratings s y mbol parameter rating unit s v in , v out v o lt age on i/o pi ns relative to vss -0.5 to v ddq +0. 5 v v in v o lt age on input relative to vss -0.5 to +3.6 v v dd v o lt age on vdd supply relative to vss -0.5 to +3.6 v v ddq v o lt age on vdd q suppl y relative to vss -0.5 to +3.6 v t a oper ating t e mpe r ature (ambient) 0 to+70 c t st g s t orage t e mpe r a t ure (plastic) -55 to +150 c p d p o w e r dissip a t i o n 1 6 w i out short circuit out put cur r ent 5 0 m a note : s t resses greater than thos e listed under ?a bsolute maximu m ratings? ma y cause permanen t dam age to the device. this is stress rating onl y , and functional operation of the d e vice at t hese or an y othe r conditions abov e those indicated in the operat ional sections of this specification is not im plied. exposure to absolute ma ximum rating co n d itions for extend ed periods ma y a f fect r eliability . capacitan ce parameter s y mbol max unit s notes input capacitance: ck0, ck0 , ck 1, ck1 , ck2, ck2 c i1 2 4 p f 1 input capacitance: a0-a12, ba0, ba1, we , ras , cas c i2 6 0 p f 1 input capacitance: cke0, cke1, s0 , s1 c i5 3 0 p f 1 input capacitance: sa0-sa2, sc l c i4 9 p f 1 input/ou t put cap a citance: dq0-6 3 ; dqs0 -7, dm0 - 7 c io1 1 4 p f 1 input/ou t put cap a citance: sda c io3 1 1 p f 1 , 2 1. v ddq = v dd = 2.5v 0.2v, f = 100 mhz, ta = 2 5 c, v out (dc) = vddq/2, v out (peak to peak) = 0.2v. 2. dq s inputs a r e grouped w i th i/ o pins reflecting the fact that the y are matched in lo ading to dq and dq s to facilitate trace m atching at the board level. rev 1.1 7 08/2002 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8hakw m 512mb : 64m x 64 pc210 0 / pc1600 un buffered ddr so-dimm dc electrical characteristics a nd operating conditions (t a = 0 c ~ 7 0 c; v ddq = 2.5v 0.2v; v dd = 2. 5v 0.2v, see a c characte ristics) s y m b o l p a r a m e t e r m i n m a x unit s n otes v dd suppl y voltage 2.3 2.7 v 1 v ddq i/o suppl y voltage 2.3 2.7 v 1 v ss , v ssq suppl y voltage, i / o suppl y v o ltage 0 0 v v ref /o refe rence vol t age 0.49 x v dd q 0 . 5 1 x v dd q v 1 , 2 v tt i/o t e rmination voltage (s y s tem) v ref ? 0.04 v ref + 0.04 v 1, 3 v ih (dc) input high (lo g ic1) voltage v ref + 0.15 v ddq + 0.3 v 1 v il (dc) input lo w (logic0) voltage -0.3 v ref - 0.15 v 1 v in (dc) input voltage le vel, ck and ck i nputs -0.3 v ddq + 0.3 v 1 v id (dc) input differential voltage, ck and ck inputs 0.30 v ddq + 0.6 v 1, 4 i i input leakage c u rrent an y input 0v v in v dd; (all other pins not under t e st = 0v) - 5 5 u a 1 i oz output l eakage curren t (dqs a r e disabled; 0v v out v dd q - 5 5 u a 1 i oh output high cur r ent (v out = v ddq -0. 373v, min v ref, min v tt ) - 1 6 . 8 - m a 1 i ol output l o w cu rr ent (v out = 0.373, max v ref , ma x v tt ) 1 6 . 8 - m a 1 1. inputs are no t recognized as valid until v ref stabilize s . 2. v ref is expect ed to be equal to 0.5 v ddq of the transmitting device, and to track variati ons in the dc level of the same. peak-to-pe a k noise on v ref m a y not e x ceed 2 % of the d c value. 3. v tt is not applied directly to the dimm. v tt is a sy stem suppl y fo r signal termination resistors, is expected to be set equal to v ref, and must track variations in the dc level of v ref . 4. v id is the mag n itude of the diffe rence bet w een th e input level on ck and the input level on ck . rev 1.1 8 08/2002 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8hakw m 512mb : 64m x 64 pc210 0 / pc1600 un buffered ddr so-dimm ac characteristics (notes 1-5 appl y to the follow i ng t ables; electrical c haracteristics and dc operating conditions, ac oper ating conditions, oper ating, standb y , a nd refresh c u rre nt s, and electrical charac teristics and ac timing.) 1. all voltages referenced to vss. 2. tests for ac ti ming, idd, and e l ectrical, ac and dc characte ristics, ma y be condu cted at nominal r e ference/suppl y voltage le vels, b u t the related specifications and device operation are guarantee d for th e full voltage range specified. 3. outpu t s measured w i th equivalent load. re fer to the ac output l oad circuit below. 4. ac timing and i dd tests ma y u s e a v il to v ih s w ing of up to 1.5 v in the test environmen t, but input timing is still re ferenced to v re f (or to th e crossing point for ck, c k ), and pa ramet e r specificati ons are gua ranteed f o r the specified ac input levels u nder no rm al use conditions. the minimum slew ra te for the i nput si gnals is 1v/ns in the range b e t w e en v il (ac) a nd v ih (ac) unless oth e r w ise specified. 5. the ac a nd d c input level specificat i ons are as defined in the s s tl_2 standa rd (i.e . the receiver effectively s w itches as a result of the signal crossing the ac input level, and remains in t hat state as long as the signal does not ring back above (belo w ) th e dc inp ut l o w ( h igh) level. ac output load circuits ti m i n g ref e renc e p o i n t v tt 5 0 ohm s 30 pf o u t put v out ac operating conditions (t a = 0 c ~ 7 0 c ; vdd q = 2.5v 0.2v; vdd = 2. 5v 0.2v, see a c characte ristics) s y mbol parameter/ condi tion min max unit notes v ih (ac) input high (lo g ic 1) voltage. v ref + 0.31 v 1, 2 v il (ac) input lo w (logic 0) voltage. v ref ?- 0. 31 v 1, 2 v id (ac) input differential voltage, ck and ck inputs 0.62 v ddq + 0.6 v 1, 2, 3 v ix (ac) input differential pair cross point voltage, ck and ck inputs (0.5*v ddq) - 0.2 (0.5*v ddq) + ? 0. 2 v 1, 2, 4 1. input slew rate = 1v/ ns. 2. inputs are no t recognized as valid until v ref stabilize s . 3. v id is the mag n itude of the diffe rence bet w een th e input level on ck and the input level on ck. 4. the value of v ix is expected to equal 0.5*v ddq of the transmittin g device and must track variations in the dc level of the same. rev 1.1 9 08/2002 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8hakw m 512mb : 64m x 64 pc210 0 / pc1600 un buffered ddr so-dimm operating, standby , and refresh currents (t a = 0 c ~ 70 c ; v ddq = 2.5v 0.2v; v dd = 2. 5v 0.2v, see a c characte ristics) s y mbol parameter/ condi tion pc1600 pc2100 unit notes i dd0 oper ating cur r e n t : one bank; act i ve / precharge; t rc = t rc ( m i n ) ; t ck = t ck ( m i n ) ; dq, dm, and d q s inputs changing tw ice per clock cy cle ; address and cont rol inputs changing once per clock cy cle 1 0 2 4 1 1 6 0 m a 1 , 2 i dd1 oper ating cur r e n t : one bank; act i ve / read / prech a rge; burst = 2; t rc = t rc ( m in) ; cl=2.5; t ck = t ck (m i n ) ; i out = 0ma; address and cont rol inputs changing once per clock cy cle 1 7 6 0 1 9 2 0 m a 1 , 2 i dd2p precharge po we r-do w n standb y curren t : all banks id le; pow e r-do w n mode; cke v il ( m a x ) ; t ck = t ck ( m in) 4 0 0 4 0 0 m a 1 , 2 i dd2n idle standb y c u r r ent : cs v ih (m in ) ; all banks idle; cke v ih( m i n ) ; t ck = t ck ( m in) ; a ddress and contr o l inputs changin g once per clock cy cle 4 8 0 5 6 0 m a 1 , 2 i dd3p active pow e r- do w n st andb y cur r ent : one bank ac tive; po w e r- do w n mod e ; cke v il ( m a x ) ; t ck = t c k ( m in ) 4 0 0 4 0 0 m a 1 , 2 i dd3n active standby c u rrent : one bank ; active / prechar ge; cs v ih ( m in ) ; cke v ih ( m in) ; t rc = t ras ( m a x ) ; t ck = t ck ( m i n ) ; dq, dm, an d dqs inputs changing tw ice per clock c y cle; address and cont rol inputs changing once per clock cy cle 8 0 0 9 6 0 m a 1 , 2 i dd4r oper ating cur r e n t : one bank; bu rst = 2; reads; co ntinuous burst; address and cont rol inputs changing once per clock cy cle; dq and dqs out puts changing twice per clock cy cle; cl = 2.5; t ck = t ck ( m in) ; i out = 0ma 1 4 1 8 1 8 0 0 m a 1 , 2 i dd4 w oper ating cur r e n t : one bank; bu rst = 2; w r ites; continuous burst; address and cont rol inputs changing once per clock cy cle; dq and dqs inp u ts changing tw ic e per clock cy cle; cl=2.5; t ck = t ck ( m in) 1 2 8 8 1 6 8 0 m a 1 , 2 t rc = t rfc ( m in) 2 2 5 6 2 4 0 0 m a 1 , 2 i dd5 auto-refr e sh cu rrent : t rc = 7.8 s 264 264 ma 1, 2, 4 i dd6 self-refresh cu r r ent : cke ?0. 2v 4 8 4 8 m a 1 - 3 i dd7 oper ating curre nt: four bank; four bank interleaving w i th bl = 4, address and control inpu ts randoml y cha nging; 50% of d a ta changing at ever y transfer; t rc = t rc (mi n ); i ou t = 0ma. 4 0 0 0 4 8 0 0 m a 1 1. i dd specifications are tested af ter t he device is properl y initialize d . 2. input slew rate = 1v/ ns. 3. enables on-chip refresh and ad dress counters. 4. curr ent at 7.8 s is time averag ed value of i dd5 at t rfc ( m i n ) and i dd2p over 7.8 s. rev 1.1 10 08/2002 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8hakw m 512mb : 64m x 64 pc210 0 / pc1600 un buffered ddr so-dimm ac timing specifications for d dr sdram devices used on module (t a = 0 c ~ 7 0 c; v ddq = 2.5v 0.2v; v dd = 2. 5v 0.2v, see a c characte ristics) (part 1 of 2) - 7 k - 7 5 b - 8 b s y mbol p a r a m e t e r m i n . m a x . m i n . m a x . m i n . max . unit notes t ac dq out put access time from ck/ ck - 0 . 7 5 + 0.75 -0.75 + 0.75 - 0 . 8 + 0 . 8 n s 1 - 4 t dqsck dqs outp u t access time from ck/ ck - 0 . 7 5 + 0.75 -0.75 + 0.75 - 0 . 8 + 0 . 8 n s 1 - 4 t ch ck high-level w i d t h 0 . 4 5 0 . 5 5 0 . 4 5 0 . 5 5 0 . 4 5 0 . 5 5 t ck 1-4 t cl ck low-level w i dt h 0 . 4 5 0 . 5 5 0 . 4 5 0 . 5 5 0 . 4 5 0 . 5 5 t ck 1-4 t ck c l = 2 . 5 7 1 2 7 . 5 1 2 8 1 2 n s 1 - 4 t ck clock cy cle time c l = 2 7 . 5 1 2 1 0 1 2 1 0 1 2 n s 1 - 4 t dh dq and dm inpu t hold time 0.5 0.5 0.6 ns 1-4, 15, 16 t ds dq and dm inpu t setup time 0.5 0.5 0.6 ns 1-4, 15, 16 t dip w dq and dm inpu t pulse w i dth ( e a c h input) 1 .75 1.75 2 ns 1-4 t hz data-out high -impedance time fro m ck/ ck -0.75 + 0.75 -0.75 + 0.75 - 0 . 8 + 0 . 8 n s 1 - 5 t lz data-out lo w-imp edance time fro m ck/ ck -0.75 + 0.75 -0.75 + 0.75 - 0 . 8 + 0 . 8 n s 1 - 5 t dqsq dq s-dq skew (dq s & associated dq signals) 0 . 5 0 . 5 0 . 6 n s 1 - 4 t dqsqa dqs- dq ske w ( d qs & all dq si g n a l s ) 0 . 5 0 . 5 0 . 6 n s 1 - 4 t hp minimum half clk period for a n y gi ven cy cle; defined b y clk high (t ch) or clk low ( t cl ) ti me t ch or t cl t ch or t cl t ch or t cl t ck 1-4 t qh data output h o ld time from d q s t hp - 0.75ns t hp - 0.75ns t hp - 1.0ns t ck 1-4 t dqss write command t o 1st dqs latching transition 0 . 7 5 1 . 2 5 0 . 7 5 1 . 2 5 0 . 7 5 1 . 2 5 t ck 1-4 t dqsl,h dqs input lo w (h igh) pulse w i dth (w rite c y cle) 0 . 3 5 0 . 3 5 0 . 3 5 t ck 1-4 t dss dqs falling edge to ck setup time (w rite c y cle) 0 . 2 0 . 2 0 . 2 t ck 1-4 t dsh dqs falling edge hold time from c k (w rite c y cle) 0 . 2 0 . 2 0 . 2 t ck 1-4 t mrd mode register se t command c y cle time 14 15 16 ns 1-4 t wp r e s write preamble s e tup time 0 0 0 ns 1-4, 7 t wp s t write p o s t a m b l e 0 . 4 0 0 . 6 0 0 . 4 0 0 . 6 0 0 . 4 0 0 . 6 0 t ck 1-4, 6 t wp r e write preamble 0 . 2 5 0 . 2 5 0 . 2 5 t ck 1-4 t ih address and control input hold time (fast slew rate) 0 . 9 1 . 1 1 . 1 n s 2-4, 9, 11, 12 t is address and control input setup time (fast slew rate) 0 . 9 1 . 1 1 . 1 n s 2-4, 9, 11, 12 t ih address and control input hold time (s l o w s l e w rat e ) 1 . 0 1 . 1 1 . 1 n s 2-4, 10-12, 14 rev 1.1 11 08/2002 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8hakw m 512mb : 64m x 64 pc210 0 / pc1600 un buffered ddr so-dimm ac timing specifications for d dr sdram devices used on module (t a = 0 c ~ 7 0 c; v ddq = 2.5v 0.2v; v dd = 2. 5v 0.2v, see a c characte ristics) (part 2 of 2) - 7 k - 7 5 b - 8 b s y mbol p a r a m e t e r m i n . max . m i n . max . m i n . m a x . unit notes t is address and control input setup time (s l o w s l e w rate ) 1 . 0 1 . 0 1 . 1 n s 2-4, 10-12, 14 t ip w input p u l s e w i d t h 2 . 2 2 . 2 - n s 2-4, 12 t rpre read pre a m b l e 0 . 9 1 . 1 0 . 9 1 . 1 0 . 9 1 . 1 t ck 1-4 t rpst read postamble 0 . 4 0 0 . 6 0 0 . 4 0 0 . 6 0 0 . 4 0 0 . 6 0 t ck 1-4 t ras active to precharge command 45 120,000 45 120,000 50 120,000 ns 1-4 t rc active to active/ a uto-ref r esh command period 6 5 6 5 7 0 n s 1-4 t rfc auto-ref r esh to a c tive/auto-refres h command period 7 5 7 5 8 0 n s 1 - 4 t rcd active to read or write dela y 20 20 20 ns 1-4 t rap active to read command w i th autoprecharge 2 0 2 0 2 0 n s 1-4 t rp precharge comm a n d p e r i o d 2 0 2 0 2 0 n s 1-4 t rrd active bank a to active bank b command 1 5 1 5 1 5 n s 1-4 t wr write recover y ti m e 1 5 1 5 1 5 n s 1-4 t dal auto precharg e write recover y + precharge time (t wr /t ck ) + (t rp /t ck ) (t wr /t ck ) + (t rp /t ck ) (t wr /t ck ) + (t rp /t ck ) t ck 1-4, 13 t wt r internal w r ite to r ead command d e la y 1 1 1 t ck 1-4 t xard pow e r do wn exit time 7.5 7.5 8 ns 1-4 t xsnr exit self-refresh t o non-r ead command 7 5 7 5 8 0 n s 1 - 4 t xsrd exit self-refresh t o read command 200 200 200 t ck 1-4 t refi average periodic refresh inte rval 7 . 8 7 . 8 7 . 8 s 1 - 4 , 8 rev 1.1 12 08/2002 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8hakw m 512mb : 64m x 64 pc210 0 / pc1600 un buffered ddr so-dimm ac timing specification notes 1. input slew rate = 1v/ns. 2. the ck/ ck inp u t refer ence level (for timing refe re nce to ck/ ck ) is the point at w h ich ck and ck cro ss: the input refe rence level for signals other than ck/ ck is v ref . 3. inputs are no t recognized as valid until v ref sta b ilize s . 4. the output ti ming reference l e vel, as measured at the timing re ference point indicated in ac char acteristics (note 3) is v tt. 5. t hz and t lz transitions occur in the same access time w i ndo w s as va lid data transitions. these parameters a r e not refer r ed to a specific voltage level, but specify w h en the device is no longer driving (hz ) , or begin s driving (lz). 6. the ma ximum limit for this parameter is not a de vice limi t. the device operates w i t h a greate r value for this paramet er, but sy s t e m performa n ce (bu s turnaround ) de grades according l y . 7. the specific requirement is that dqs be valid (hi gh, low , or some point on a valid transition) on or b e fore this ck ed ge. a valid transition is defin ed as monotonic and meeting the i nput slew rate sp ecification s of the device. when no w r ites w e re pr eviously in pr ogr ess on the bus, dq s w ill be tr ansitioning fr om hi- z to logic low. if a pr evious wr ite w a s in pr ogr e ss, dq s could be high, lo w, or transitioning fr om high to lo w at this time, depending on tdqss. 8. a maximum of eight auto refr esh commands can be posted to an y given ddr sdr a m device. 9. for comman d / address input slew rate >= 1.0 v/n s . slew rate is measured bet w e en v oh (ac) and v ol (ac). 10. for comma n d /address input slew r a te >= 0.5 v / ns and < 1.0 v/n s . slew rate is measured bet w e en v oh (ac) and v ol (ac). 11. ck/ ck sle w r a tes are >= 1.0 v / ns. 12. these pa ram e ters guaran tee device timing, bu t the y a r e not n e c essarily tested on each device, and the y ma y be guarantee d b y design or tester c haracterization. 13. for each of t he terms in pare n theses, if not alread y an inte g e r, round to th e ne xt highest integer. t ck is equal to the ac tual sy stem clock cy cle time. for e x ample, fo r pc2100 at cl= 2. 5, t dal = (1 5n s/7.5ns) +(20ns/ 7 .0ns) = 2 + 3 = 5. 14. an input setu p and hold time d e rating tabl e is used to increase t is and t ih in the case w h e r e the i nput slew rate is belo w 0 . 5 v/ns. input slew rate delta (tis ) d e l t a (tih ) u n i t n o t e 0.5 v/ns 0 0 ps 1, 2 0.4 v/ns +50 0 ps 1, 2 0.3 v/ns +100 0 ps 1, 2 1. input slew rate is based on the lesser of the slew rates determine d b y either v ih ( a c) to v il ( a c) or v ih (dc) to v i l ( dc), similar l y for rising transitions. 2. these der ating paramete r s ma y be gua rantee d b y design or te st er characterization and are n o t ne cessarily tested on each devi ce. 15. an input setu p and hold time d e rating table is used to increas e t ds and t dh in t he case w h e r e th e i/o sle w rat e is below 0.5 v/ns. input slew rate delta (tds ) d e l t a (tdh ) u n i t n o t e 0.5 v/ns 0 0 ps 1, 2 0.4 v/ns +75 +75 ps 1, 2 0.3 v/ns +150 +150 ps 1, 2 1. i/o sle w rat e is based on the lesser of the slew r a tes determined b y either v ih ( a c) to v il (ac) or v ih (dc) to v i l (dc) , s i mi l a rl y for rising transitions. 2. these der ating paramete r s ma y be gua rantee d b y design or te st er characterization and are n o t ne cessarily tested on each devi ce. 16. an i/o delta rise, fall derating table is used to increase t ds an d t dh in the cas e where dq, dm , and d q s slew r a tes diffe r. delta rise and f a ll rate delta (tds ) d e l t a (tdh ) u n i t n o t e 0.0 ns/v 0 0 ps 1-4 0.25 ns/v +50 +50 ps 1-4 0.5 ns/v +100 +100 ps 1-4 1. input slew rate is based on the lesser of the slew rates determine d b y either v ih ( a c) to v il ( a c) or v ih (dc) to v i l ( dc), similar l y for rising transitions. 2. input slew rate is based on the larger of ac to a c delta rise, fall rate and dc t o d c delta rise, fall rate. 3. the delta rise, fall rate is calcu l ated as : [1/(sle w rate 1)] - [1/ ( slew rate 2)] for e x ample: slew rate 1 = 0. 5 v/ ns; slew rate 2 = 0.4 v/ns. delta ri se, fall = (1/0.5) - (1/0.4) [ n s/v] = - 0 .5 ns/v using the table above, this w ould result in an increase in t ds and t dh of 100 ps. 4. these der ating paramete r s ma y be gua rantee d b y design or test er characterization and are n o t ne cessarily tested on each device. rev 1.1 13 08/2002 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8hakw m 512mb : 64m x 64 pc210 0 / pc1600 un buffered ddr so-dimm packag e dimensions 67.60 4.0 0 + / -0.10 1.00+ /- 0.1 fr o n t sid e 1.00+ /- 0.10 d e t a il a 2.55 0.60 d e t a il b 0.45 0.25 ma x 19 9 13 9 4 1 d e t a il a d e t a il b 4.00 20.00 31.75 6.00 2.1 5 11.4 0 4.20 1.80 47.40 3.80 m a x (2x) 1.8 0 2.45 bac k 63.60 not e : a l l di m ens i o ns are t y p i c a l w i t h t o l e ranc es o f +/ - 0. 15 u n l e s s ot her w i s e s t at ed . u n its: m illim e t e r s ( i n c h e s ) rev 1.1 14 08/2002 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d64s8hakwm 512mb : 64m x 64 pc2100 / pc1600 unbuffered ddr so-dimm rev 1.1 15 08/2002 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. revision log rev date modification 1.0 06/2002 official release fixed typo in ordering information added t xard (power down exit time) to ac timing table 1.1 08/2002 added tolerance specification of +/- 0.15 to package dimensions

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