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| tsi564a serial rapidio switch hardware manual formal may 2007 80b802a_ma002_04 titl
trademarks tundra is a registered trademark of tundra semiconductor corporation (canada, u.s., and u.k.). tundra, the tundra logo, tsi564a, and silicon behind the network, are trademarks of tundra semiconductor corporation. all other registered and unregistered mark s (including trademarks, servi ce marks and logos) are the property of their respective owners. the absence of a mark identifier is not a representation that a particular product name is not a mark. copyright copyright ? may 2007 tundra semiconductor corporation. all rights reserved. published in canada this document contains information th at is proprietary to tundra and may be used for non-commercial purposes within your organization in support of tundra products. no other use or transmission of all or any part of this document is permitted without written permission from tundra, and must include all copyright and other proprietary notices. use or transmission of all or any pa rt of this document in violation of any applicable canadian or other legislation is hereby expressly prohibited. user obtains no rights in the information or in any produc t, process, technology or tr ademark which it includes or describes, and is expressly prohibited from modifying the information or creating derivative works without the express written consent of tundra. disclaimer tundra assumes no responsibility for the accuracy or comple teness of the information presented, which is subject to change without notice. tundra products may contain de sign defects or errors known as errata which may cause the product to deviate from published specifications. curren t characterized errata are available on request. in no event will tundra be liable for any direct, indirect, speci al, incidental or consequential damages, including lost profits, lost business or lost data, resulting from the use of or reliance upon the in formation, whether or not tundra has been advised of the possibility of such damages. the information contained in this document does not affect or change tundra?s product warranties. mention of non-tundra products or services is for information purposes only and constitutes neither an endorsement nor a recommendation. as this information will change over time, please ensu re you have the most recen t version by contacting a member of the tundra technical support team, or by checking the support section of www.tundra.com. 228 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com ? corporate profile about tundra tundra semiconductor corporation is the global leader in system interconnect providing world-class support and leading edge semico nductor solutions to the world?s foremost communications, networking, storage system, and information te chnology vendors. consis tently delivering on system-level performance promises that reduce time to market, tundra system interconnect ensures market advantage in wireless infra structure, storage networking, network access, military, industrial automation, and information technology applicati ons. tundra headquarters ar e located in ottawa, ontario, canada. the company also has a design center in south portland, maine, and sales offices through out europe, across the us and in asia. tundr a sells its products worl dwide through a network of direct sales personnel, independent dist ributors, and manufacturer s' representatives. tundra system interconnect tundra uses the term system interconnect to refer to the technology used to connect all the components and sub-systems in almost any embe dded system. this concept applies to the interfacing of functional elements (cpu, memory, i/o complexes) within a single-board system, and the interconnection of multiple boards in a larger system. advanced communications networks need advanced system interconn ect. it is a vital enabling technology for the networked world. tundra system interconnect provides the latest interface and throughput features, which enable communications infrastructure vend ors to design and build more powerful, faster equipmen t in shorter timeframes. tundra system interconnect ? vital to building the communica tions systems of the future: ? tundra system interconnect products enable cu stomers to get the perform ance, scalability, and reliability from their systems to meet today's and tomorrow's bandwidth demands. ? tundra system interconnect products are standa rds-based, off-the-shel f products that help customers speed their time to market. ? tundra system interconnect products meet the growing customer demand for outsourced standards-based interconnect products. partnerships fundamental to the success of tundra is its partners hips with leading technology companies, including ibm, intel, and freescale. as a result of these alliances, tundra devices complement our partners? products, and greatly influence the design of cust omers? architecture. customers are changing their designs to incorporate tundra products. this is eviden ce of our commitment to be a significant part of its customers? success. corporate profile 229 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com customers tundra semiconductor products are used by the worl d?s leading communications infrastructure and storage vendors, including cisco sy stems, freescale, siemen s, nortel networks, lucent technologies, nokia, ericsson, alcatel, and hewlett-packard. the tundra design philosophy is one in which a nu mber of strategic customers are invited to participate in the defini tion, design, test, and ear ly silicon phases of pro duct development. close working relationships with custom ers and clear product roadmaps ensure that tundra can anticipate and meet the future directions and needs of communications systems de signers and manufacturers. support tundra is respected throughout the industry for it s outstanding commitment to customer support. tundra ensures that its customers can take immediat e advantage of the company?s products through its in-house applications engineerin g group, unmatched design suppor t tools, and full documentation accessible through the web. design. connect. go ? 230 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com ? contact information tundra is dedicated to providing s uperior technical documentation and design support to its customers. the following support options are available: web product information www.tundra.com/tsi5 64a contains the features, benefits, typical applications, and block diagram for the tsi564a. this webpage also provides links to other product information located on the tundra website. technical support resources www.t undra.com/support contains an extensive list of technical resources to assist with your design needs. some of the key support resources include: ? technical support faq ? user documentation ? schematic design checkli sts and debug guidelines you can also opt to receive ema il notification when a support resource is added or changed. technical support request to contact tundr a support personnel about a technical question, fill out the technica l support request form in the support section of the website. sales support www.tundra.com /sales contains information that will help you locate a tundra sales representative nearest you. email docfeedback@tundra.com can be used to provide feedback on a tsi564a customer document. mail tundra semiconductor corporation 603 march road ottawa, on, canada k2k 2m5 fax 613-592-1320 contact information 231 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 232 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com ? about this document this section discusses the following topics: ? ?scope? on page 232 ? ?document conventi ons? on page 232 ? ?revision history? on page 233 scope the tsi564a serial rapidio switch hardware manual discusses the features, capabilities, and configuration requirements for the tsi564a. it is intended for hardware and so ftware engineers who are designing system interconnect ap plications with the device. document conventions this document uses th e following conventions. non-differential signal notation non-differential signals are either ac tive-low or active-high. an active-l ow signal has an active state of logic 0 (or the lower voltage level) , and is denoted by a lowercase ?_b? . an active-high signal has an active state of logic 1 (o r the higher voltage level), and is not denoted by a special character. the following table illustrates the non-di fferential signal naming convention. differential signal notation differential signals consist of pairs of complement positive and negati ve signals that are measured at the same time to determine a signal?s active or inactive state (they are denoted by ?_p? and ?_n?, respectively). the following table illustrate s the differential signal naming convention. state single-line signal multi-line signal active low name_b name_b[3] active high name name[3] state single-line signal multi-line signal inactive name_p = 0 name_n = 1 name_p[3] = 0 name_n[3] =1 active name_p = 1 name_n = 0 name_p[3] is 1 name_n[3] is 0 about this document 233 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com object size notation ?a byte is an 8-bit object. ?a word is a 16-bit object. ?a doubleword (dword) is a 32-bit object. numeric notation ? hexadecimal numbers are denoted by the prefix 0x (for example, 0x04). ? binary numbers are denoted by the prefix 0b (for example, 0b010). ? registers that have multiple iterations ar e denoted by {x..y} in their names; where x is first register and address, and y is the last register and address. for example, reg{0..1} in dicates there are two versions of the register at diff erent addresses: reg0 and reg1. symbols document status information ? advance ? contains information that is subject to change, and is available once prototypes are released to customers. ? preliminary ? contains information about a product that is near production-r eady, and is revised as required. ? formal ? contains information about a final, cu stomer-ready product, and is available once the product is released to production. revision history 80b802a_ma002_04, formal, may 2007 this is the current release of the tsi564a serial rapidio switch hardware manual. the following information was updated: ? ?power distribution? on page 285 ? ?package characteristics? on page 250 ? ?heatsink attachment? on page 255 tip this symbol indicates a basic design conc ept or information considered helpful. this symbol indicates important conf iguration informatio n or suggestions. this symbol indicates procedures or operating levels that may re sult in misuse or damage to the device. about this document 234 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 80b802a_ma002_03, fi nal, february 2006 the following changes were made to this document: ? ?line rate support? on page 298 ? ?power sequencing? on page 259 . ? the t storage minimum value was changed to -55 c (see table 6 on page 256 ). ? ?heatsink requirement and analysis? on page 255 80b802a_ma001_02, final, march 2006 this was the production version of the tsi564a serial rapidio switch hardware manual. an error was corrected in the industrial part number (see ?ordering information? on page 33 ). no other information has been edited in this document. 80b802a_ma001_01, final, march 2006 this was the first release of the tsi564a serial rapidio switch hardware manual. about this document 235 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 11 ? contents corporate profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 contact information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 about this document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 document conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1. signals and packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.1 pinlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2.1 endian ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.2.2 signal groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.3 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.4.1 junction-to-ambient thermal characteristics (theta ja) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.4.2 heatsink requirement and analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2 electrical characteristics and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2.1 power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.2 lvttl i/o and open drain electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.3 serial interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.4 serial reference clock input electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.5 serial interface capability and implem entation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.2.6 i2c interface ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.2.7 boundary scan interface ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.3 ac timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.1 lvtll i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.2 serial interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3. layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2 impedance requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3 tracking topologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3.1 stripline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3.2 crosstalk considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.3.3 receiver dc blocking capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.3.4 escape routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.3.5 board stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.4 power distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 contents 12 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 3.5 decoupling requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.5.1 component selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.5.2 power plane impedance and resonance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.6 clocking and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.6.1 clock overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.6.2 clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.6.3 reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.7 modeling and simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.8 testing and debugging considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.8.1 logic analyzer connection pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.8.2 jtag connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.9 reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4. line rate support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 a. ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 a.1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 a.2 part numbering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 13 ? figures figure 1: tsi568a pinout list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 2: package diagram ? top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 3: package diagram ? side view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 4: package diagram ? bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 5: i2c interface signal timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 6: input timing measurement waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 7: output timing measurement waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 8: duty cycle definition waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 9: serial interface transmitter and receiver signal waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 10: serial reference clock waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 11: recommended edge coupled differential stripline (symmetric when h1=h2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 12: not recommended broadside coupled or dual stripline c onstruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 13: differential microstrip construction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 14: equation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 15: differential controlled impedance via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 16: via construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 17: signal across a via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 18: signal through a via. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 19: signal transitioning across a via simulation model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 20: signal transitioning through a via simulation model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 21: buried via example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 22: blind via example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 23: serpentine signal routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 24: receiver coupling capacitor positioning recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 25: escape routing for differential signal pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 26: differential skew matching serpentine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 27: recommended board stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 28: system power supply model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 29: pll filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 30: recommended decoupling capacitor pad designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 31: decoupling bypass frequency bands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 32: tsi568a clocking architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 33: tsi568a driven by lvpecl or cml clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 34: tsi568a driven by an lvds clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 35: analyzer probe pad tracking recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figures 14 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 15 ? tables table 1: signal types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 2: tsi568a signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 3: package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 4: thermal characteristics of tsi568a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 5: simulated junction to ambient characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 6: absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 7: power supply electrical characteristics and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 8: lvttl i/o and open drain electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 9: serial interface receiver input electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 10: serial interface transmitter output electrical speci fications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 11: serial reference clock input electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 12: rapidio specification requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 13: drive current register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 14: idr/inom ratios vs. dtx[3:0]swing into termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 15: vtt to output swing limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 16: ac specifications for i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 17: boundary scan test signal timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 18: decoupling capacitor quantities and values recommended for the tsi568a. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 19: clock input sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 20: tsi568a clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 21: 8-channel probe pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 22: tsi568a supported standard rapidio line rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 23: tsi568a supported non-standard line rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 24: ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 tables 16 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 242 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com ? 1. signals and packaging this chapter describes the packag ing (mechanical) features for the tsi564a. it includes the following information: ? ?pinlist? on page 242 ? ?signals? on page 242 ? ?package characteristics? on page 250 ? ?thermal characteri stics? on page 254 \ 1.1 pinlist please refer to the tsi564a user manual and the tundra website at www.tundra.com for information on the package pinlist and ballmap. 1.2 signals the following conventions are used in the pin description table: ? signals with the suffix ?_p? are the positive half of a differential pair. ? signals with the suffix ?_n? are the negative half of a differential pair. ? signals with the suffix ?_b? are active low. ? ddr signals are double data rate, data is tran sferred on both edges of the associated clock. signals are classified accord ing to the types defined in table 1 on page 242 . table 1: signal types pin type definition i input o output i/o input/output od open drain srio cml driver/receiver defined by rapidio interconnect specification (revision 1.2) pu pulled up internal to the tsi564a pd pulled down internal to the tsi564a 1. signals and packaging 243 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 1.2.1 endian ordering this document follows the bit- numbering convention adopted by rapidio interconnect specification (revision 1.2) , where [0:7] is used to represent an 8 bi t bus with bit 0 as the most-significant bit. 1.2.2 signal groupings figure 1 summarizes the tsi564a signals. hyst hysteresis core power core supply core ground ground for core logic i/o power i/o supply table 1: signal types (continued) pin type definition 1. signals and packaging 244 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com figure 1: tsi564a pinout list sp2 sp 3 sp 4 sp_io_speed[1:0] ports 0,1 ports 2 - 5 1 1 1 1 1 1 1 jtag tap i 2 c tck tdi tdo tms trst_b i2c_sclk i2c_sd 1 1 hard_rst_b sw_rst_b 1 int_b reset 2 2 ref clks s_clk_1_[p,n] s_clk_2_[p,n] 1 p_clk vss vd d logic pwr/gnd vss_io port config 2 interrupt vdd_io io pwr/gnd sp0, 2, 4 ?. 6 vd d 1 i2c_disable sp6_t[a,b,c,d]_[p,n] 8 ports 6,7 sp_vdd sp0_t[a,b,c,d]_[p,n] sp0_r[a,b,c,d]_[p,n] sp0_rref 8 8 sp0_modesel sp0_pwrdn 1 1 1 sp1_pwrdn 1 sp0_vtt 1 sp0 _ avd d 1 sp6_r[a,b,c,d]_[p,n] sp6_rref 8 sp6_modesel sp6_pwrdn 1 1 1 sp7_pwrdn 1 sp6_vtt 1 sp6_avdd 1 sp 5 1. signals and packaging 245 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com table 2 describes the tsi564a signals. table 2: tsi564a signal description pin name pin count type description port n - 1x/4x mode serial rapidio port (n+1) - 1x mode serial rapidio where n = 0, 2, 4, 6 serial port n/n+1 transmit where n = 0, 2, 4, 6, 8 sp{n}_ta_p 1 o, srio port n lane a differential non-inverting transmit data output (4x mode) port n differential non-inverting transmit data output (1x mode) sp{n}_ta_n 1 o, srio port n lane a differential inverting transmit data output (4x mode) port n differential inverting transmit data output (1x mode) sp{n}_tb_p 1 o, srio port n lane b differential non-inverting transmit data output (4x mode) port n+1 differential non-inverting transmit data output (1x mode) sp{n}_tb_n 1 o, srio port n lane b differential inverting transmit data output (4x mode) port n+1 differential inverting transmit data output (1x mode) sp{n}_tc_p 1 o, srio port n lane c differential non-inverting transmit data output (4x mode) sp{n}_tc_n 1 o, srio port n lane c differential inverting transmit data output (4x mode) sp{n}_td_p 1 o, srio port n lane d differential non-inverting transmit data output (4x mode) sp{n}_td_n 1 o, srio port n lane d differential inverting transmit data output (4x mode) serial port n/n+1 receive where n = 0, 2, 4, 6 sp{n}_ra_p 1 i, srio port n lane a differential non-inverting receive data input (4x node) port n differential non-inverting receive data input (1x mode) sp{n}_ra_n 1 i, srio port n lane a differential inverting receive data input (4x node) port n differential inverting receive data input (1x mode) sp{n}_rb_p 1 i, srio port n lane b differential non-inverting receive data input (4x mode) port n+1 differential non-inverting receive data input (1x mode) sp{n}_rb_n 1 i, srio port n lane b differential inverting receive data input (4x mode) port n+1 differential inverting receive data input (1x mode) sp{n}_rc_p 1 i, srio port n lane c differential non-inverting receive data input (4x mode) sp{n}_rc_n 1 i, srio port n lane c differential inverting receive data input (4x mode) sp{n}_rd_p 1 i, srio port n lane d differential non-inverting receive data input (4x mode) sp{n}_rd_n 1 i, srio port n lane d differential inverting receive data input (4x mode) serial port n/n+1 configurat ion where n = 0, 2, 4, 6 1. signals and packaging 246 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com sp{n}_rref 1 used to connect a 1k +/-1% resistor to sp{n}_avdd to provide a reference current for the driver and equalization circuits. sp{n}_modesel 1 i/o, cmos pd selects the serial port operating mode for ports n and n+1 0 - port n operating in 4x mode (port n+1 not available) 1 - ports n and n+1 operating in 1x mode must remain stable for 10 p_clk cycles after hw_rst_b is de-asserted in order to be sampled correctly. ignored after reset. sp{n}_pwrdn 1 i/o, cmos pu port n transmit and receive power down control this signal controls the state of port n and port n+1 the pwrdn controls the state of all four lanes (a/b/c/d) of serdes macro. 0 - port n powered up. port n+ 1 controlled by sp{n+1}_pwrdn. 1 - port n powered down. port n+1 powered down. override sp{n}_pwrdn using pwdn _x1 field in srio mac x clock selection register output capability of this pin is only used in test mode. must remain stable for 10 p_clk cycl es after hw_rst_b is de-asserted in order to be sampled correctly. ignored after reset. sp{n+1}_pwrdn 1 i/o, cmos pu port n+1 transmit and re ceive power do wn control this signal controls the state of port n+1. note that port n+1 is never used when 4x mode is selected for a serial rapid io mac, and it must be powered down. 0 - port n+1 powered up 1 - port n+1 powered down override sp{n+1}_pwrdn using pwdn _x4 field in srio mac x clock selection register. output capability of this pin is only used in test mode. must remain stable for 10 p_clk cycl es after hw_rst_b is de-asserted in order to be sampled correctly. ignored after reset. serial port speed select table 2: tsi564a signal description (continued) pin name pin count type description 1. signals and packaging 247 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com sp_io_speed[1] 1 i/o, cmos, pd serial port transmit and receive operating frequency select, bit 1 when combined with sp_io_speed[0], this pin selects the default serial port frequency for all ports. 00 - s_clk_2 reference divided by 2 01 - s_clk_2 reference (default) 10 - s_clk_1 reference 11 - reserved the output data rate per lane is 10 times the selected input clock. selects the speed at which the ports operates when reset is removed. this could be either due to hard_rst_b being de-asserted or by the completion of a self-reset. this signal must remain stable for 10 p_clk cycles after hw_rst_b is de-asserted in order to be sampled correctly. the signal is ignored after reset. the sp_io_speed[1:0] setting is equal to the sclk_sel field in the srio mac x clock selection register output capability of this pin is only used in test mode. sp_io_speed[0] 1 i/o, cmos, pu see sp_io_speed[1] clock and reset p_clk 1 i cmos this clock is used for the register bus clock the maximum frequency of this input clock is 100 mhz. s_clk_1_p 1 i cml differential non-inverting reference clock the clock is used for following purposes: serdes reference clock, serial port system clock, isf clock (equal to half of this clock) and test clock. the clock frequency is defined in the minimum clock frequency requirements section. the maximum frequency of this input clock is 312.5 mhz. if this clock input is not used, pull this signal up. s_clk_1_n 1 i cml differential inverting reference clock the clock is used for following purposes: serdes reference clock, serial port system clock, isf clock (equal to half of this clock) and test clock. the clock frequency is defined in the minimum clock frequency requirements section.the maximum frequency of this input clock is 312.5 mhz. if this clock input is not used, pull this signal down. table 2: tsi564a signal description (continued) pin name pin count type description 1. signals and packaging 248 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com s_clk_2_p 1 i cml differential non-inverting reference clock the clock is used for following purposes: serdes reference clock, serial port system clock, 125mhz clock (equal to hal f of this clock) and test clock. the clock frequency is defined in the minimum clock frequency requirements section. the maximum frequency of this input clock is 250 mhz. if this clock input is not used, pull this signal up. s_clk_2_n 1 i cml differential inverting reference clock the clock is used for following purposes: serdes reference clock, serial port system clock, 125mhz clock (equal to hal f of this clock) and test clock. the clock frequency is defined in the minimum clock frequency requirements section.the maximum frequency of this input clock is 250 mhz. if this clock input is not used, pull this signal down. hard_rst_b 1 i cmos, hyst, pu schmidt-triggered hard reset asynchronous active low reset for the entire device. interrupts int_b 1 o, od, cmos interrupt signal (open drain output) sw_rst_b 1 o, od, cmos software reset (open drain output) this signal is asserted when a rapidio port receives a valid reset request on a rapidio link. if self-reset is not selected, this pin remains asserted until the reset request is cleared from the status registers. if self-reset is selected, this pin remains asserted until the self reset is complete. if the tsi564a is reset from the hard_rst_b pin, this pin is de-asserted and remains de-asserted after hard_rst_b is released. i 2 c i2c_sclk 1 o, od, cmos, pu i 2 c clock, up to 100 khz although this clock is open drain, the i2c controller does not support multiple bus masters. this clock signal must be connected to the clock of the serial eeprom on the i2c bus. i2c_sd 1 i/o, od, cmos,p u i 2 c input and output data bus (bidirectional open drain) i2c_disable - i, cmos, pd disable i 2 c register loading after reset when asserted, the tsi564a will not attempt to load register values from i 2 c. 0 - enable i 2 c register loading 1- disable i 2 c register loading table 2: tsi564a signal description (continued) pin name pin count type description 1. signals and packaging 249 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com jtag / tap controller tck 1 i, cmos, pd ieee 1149.1 test access port - clock input tdi 1 i, cmos, pu ieee 1149.1 test access port - serial data input tdo 1 o, cmos ieee 1149.1 test access port - serial data output tms 1 i, cmos, pu ieee 1149.1 test access port - test mode select trst_b 1 i, cmos, pu ieee 1149.1 test access port - tap reset input this input should asserted during a power-up reset. power supplies port n/n+1 n = 0, 2, 4, 6 sp{n}_avdd 1 - port n & n+1: 1.2v supply for bias g enerator circuitry. this is required to be a low-noise supply. sp{n}_vtt 1 - port n & n+1: driver termination voltage - common to all lanes common supply vdd_io 12 - common 3.3v supply for cmos i/o vss_io 12 - common ground supply for i/os vss 188 - common ground supply for digital logic vdd 32 - common 1.2v supply for digital logic sp_vdd 30 - 1.2v supply for cdr, tx/rx, and digital logic for all rapidio ports total power and ground 274 table 2: tsi564a signal description (continued) pin name pin count type description 1. signals and packaging 250 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 1.3 package characteristics tsi564a?s package characteristics are summarized in the following table. figure 2 and figure 3 illustrates the top and side views of the tsi564a package. figure 4 presents the bottom view of the device. table 3: package characteristics feature description package type flip-chip ball grid array (fcbga) package body size 21 x 21 mm jedec specification 95-1 section 14 pitch 1.00 mm ball pad size 500 um soldermask opening 400 um moisture sensitivity level 4 1. signals and packaging 251 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com figure 2: package diagram ? top view 1. signals and packaging 252 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com figure 3: package diagram ? side view 1. signals and packaging 253 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com figure 4: package diagram ? bottom view 1. signals and packaging 254 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 1.4 thermal characteristics heat generated by the packaged ic has to be re moved from the package to ensure that the ic is maintained within its functional and maximum design temperature limits. if heat buildup becomes excessive, the ic temperature may ex ceed the temperature limits. a conseq uence of this is that the ic may fail to meet the performance specifications and the reliability objec tives may be affected. failure mechanisms and failure rate of a device ha ve an exponential dependence of the ic operating temperatures. thus, the control of the package temperature, and by extension the junction temperature, is essential to ensure product reliability. the tsi564a is specified safe for operation when the junction temperature is wi thin the recommended limits. table 4 shows the simulated theta jb and theta jc thermal characteristics of the tsi564a fcbga package. 1.4.1 junction-to-ambient thermal characteristics (theta ja) table 5 shows the simulated theta ja thermal characteristic of the tsi564a fcbga package.the results in table 5 are based on a jedec thermal test boar d configuration (jes d51-9) and do not factor in system level char acteristics. as such, these va lues are for reference only. table 4: thermal characteristics of tsi564a interface result theta jb (junction to board) 13.4 c/watt theta jc (junction to case) 0.09 c/watt the theta ja thermal resistance characteristics of a package depend on multiple system level variables. table 5: simulated junction to ambient characteristics package theta ja at specified airflow (no heat sink) 0m/s 1 m/s 2m/s tsi564a fcbga 17.4 c/watt 15.8 c/watt 15.0 c/watt 1. signals and packaging 255 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 1.4.1.1 system-level characteristics in an application, the following system-level characteristics and en vironmental issues must be taken into account: ? package mounting (vertical / horizontal) ? system airflow conditions (laminar / turbulent) ? heat sink design and thermal characteristics (see ?heatsink requirement and analysis? on page 255 ) ? heat sink attachme nt method (see ?heatsink requirement and analysis? on page 255 ) ? pwb size, layer count and conductor thickness ? influence of the heat dissipating componen ts assembled on the pwb (neighboring effects) example on thermal data usage based on the theta ja data and specified conditio ns, the following formula can be used to derive the junction temperature (tj) of the tsi564a with a 0m/s airflow: ?tj = ja * p + tamb where: tj is junction temperatur e, p is the power consumption, tamb is the ambient temperature assuming a power consumption (p) of 3 w a nd an ambient temperature (tamb) of 70 c, the resulting junction temperature (tj) would be 122.2 c. 1.4.2 heatsink requirement and analysis the tsi564a is packaged in a flip-chip ball grid array (fcbga). with this package technology, the silicon die is exposed and serves as the interface between package and heatsink. where a heatsink is required to maintain junction temper atures at or below sp ecified maximum values, it is important that attachment techniques and thermal re quirements be critical ly analyzed to ensure reliability of this interface. factors to be considered include: surf ace preparations, selection of thermal interface materials, curing process, shock and vibration requirements, and thermal expansion coefficients, among others. each design should be in dividually analyzed to ensure that a reliable thermal solution is achieved. 1.4.2.1 heatsink attachment both mechanical and adhesive techniques are available for he atsink attachment. for heatsink attachment methods th at induce a compressive load to the fcbga package, the maximum force that can be applied to the p ackage should be limited to 5 gm / bga ball (provided that the board is supported to prevent any flexing or bowing). the maximum force for the tsi564a package is 2.0 kg. both mechanical and adhesive techniques are available for heatsink attach ment. tundra makes no recommendations as to the reliabilit y or effectiveness of either approach. the designer must critically analy ze heatsink requirements, selection criteria, and attachment techniques. 256 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com ? 2. electrical characteristics this chapter provides the electrical characterist ics for the tsi564a. it includes the following information: ? ?absolute maximum ratings? on page 256 ? ?electrical characteristics and operating conditions? on page 257 ? ?ac timing waveforms? on page 268 2.1 absolute maximum ratings operating the device beyond the operating conditions is not recommended. stressing the tsi564a beyond the absolute maximum ra ting can cause permanent damage. table 6 lists the absolute maximum ratings. table 6: absolute maximum ratings symbol parameter min max unit t storage storage temperature -55 125 c t case (t j ) case temperature under bias -40 120 c v dd_33 3.3v dc supply voltage -0.5 4.6 v v dd , sp_v dd 1.2v dc supply voltage -0.5 1.7 v sp{n}_av dd 1.2v analogue supply voltage -0.5 1.7 v sp{n}_v tt driver termination voltage -0.5 2.5 v v i_sp{n}-r{a-d}_{p,n} serdes port cml receiver input voltage -0.3 3 v v o_sp{n}-t{a-d}_{p,n} serdes port cml transmitter output voltage -0.3 3 v v i_lvttl lvttl input voltage -0.5 v dd_33 +0.5 v v o_lvttl lvttl output or i/o voltage -0.5 v dd_33 +0.5 v 2. electrical characteristics 257 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 2.2 electrical characteristics and operating conditions table 7 lists the recommended operating conditions and electrical characteristic s for the power supply pins of the tsi564a. v esd_hbm maximum esd voltage discharge tolerance for human body model (hbm). [test conditions per jedec standard - jesd22-a114-b] 1000 v v esd_cdm maximum esd voltage discharge tolerance for charged device model (cdm). test conditions per jedec standard - jesd22-c101-a 300 v table 7: power supply electrical ch aracteristics and operating conditions symbol parameter min typ max unit notes t j junction temperature -40 120 c v dd_33 3.3v dc supply voltage 2.97 3.63 v maximum ac voltage ripple must be less than 2.5% measured at device pin sp_vdd, vdd, sp{n}_avdd 1.2v dc supply voltage 1.14 1.29 v maximum ac voltage ripple must be less than 2.5% measured at device pin sp{n}_vtt 1.2v driver termination voltage 1.14 1.26 v maximum ac voltage ripple must be less than 2.5% measured at device pin 1.5v driver termination voltage 1.42 1.58 v maximum ac voltage ripple must be less than 2.5% measured at device pin 1.8v driver termination voltage 1.71 1.89 v maximum ac voltage ripple must be less than 2.5% measured at device pin i vdd core supply current 2420 ma i vdd (in ma) = (i_vddc1 x n1)+(i_vddc4 x n4), where i_vddc1 is the active x1 port current, n1 is the number of active x1 ports, i_vddc4 is the active x4 port current, and n4 is the number of x4 ports active. i_vddc1(in ma) = 0.0361 x f + 38.4, where f is the serdes port frequency of operation in mhz i_vddc4(in ma) = 0.062 x f + 72.7, where f is the serdes port frequency of operation in mhz table 6: absolute maximum ratings symbol parameter min max unit 2. electrical characteristics 258 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com i vdd_33 3.3v io supply current 10 ma i sp _ vdd serdes digital supply current 2600 ma i sp_vdd (in ma)=0.026xcxnxf, where c is the number of active serdes channels, n is the number of active serdes ports, and f is the serdes port frequency of operation in mhz i sp _ avdd serdes analog supply current 80 ma i sp_avdd (in ma)=10xn, where n is the number of serdes ports active brent to get cpk of 2 number i sp_vtt serdes termination supply current 1140 ma i sp_vtt =inom x ridr/inom x c x n, where ridr/inom is the idr to inom ratio, c is the number of active serdes channels, and n is the number of serdes ports with termination active. pd_core core power dissipation 3050 mw pd_core(in mw)= vdd x rvdd/vdd_max x i_vddc, where rvdd/vdd_max is the ratio of vdd to vdd_max, and i_vddc is the core current calculated for the core supply current parameter pd_io io power dissipation 5570 mw pd_io(in mw)= (sp_vdd x rsp_vdd/sp_vddmax x isp_vdd) + (vdd33 x rvdd33/vdd33_max x i_vdd33) + (sp_avdd x rsp_avdd/sp_avddmax x isp_avdd) + (sp_vtt x isp_vtt), where rxxxx/xxxx is the ratio of the supply voltage to the supply voltage maximum, isp_vdd is the serdes digital supply current parameter, i_vdd33 is the 3.3v io supply current parameter, isp_avdd is the serdes analog supply current parameter, and isp_vtt is the se rdes termination supply current parameter pd_standby standby power dissipation 256 mw pd_standby (in mw) = 32 x n, where n is the number of disabled ports. the standby power of each disabled port must be included in the total power dissipation calculation. the value shown here is for eight ports in standby. pd total power dissipation 7890 mw this parameter is configuration dependent and can be calculated from the pd_core, pd_io, and pd_standby parameters for a given configuration. the number shown here is for the maximum power configuration of eight 4x mode ports operating at 3.125gb/s table 7: power supply electrical ch aracteristics and operating conditions symbol parameter min typ max unit notes 2. electrical characteristics 259 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 2.2.1 power sequencing the recommended power sequence for the tsi564a is in the following order: ? vdd (1.2v), sp_vdd, and sp{n}_vdda (1.2v) power-up together ? sp{n}_vtt ? vdd_io (3.3v) it is recommended that there not be more than 50m s between ramping of the 1.2v and 3.3v supplies. the power supply ramp rates must be kept between 10v/sec and 1x10 6 v/sec to minimize power current spikes during power up. for applications requ iring power sequencing that is different than the recommended sequence, please contact tundra applications engineering. 2.2.1.1 power-down power down is the reverse sequence of power up: ? vdd_io (3.3v) ? sp{n}_vtt ? vdd (1.2v), sp_vdd, and sp{n}_avdd (1.2 v) power-down at the same time. this section describes the dc signa l characteristics for the tsi564a. 2.2.2 lvttl i/o and open drai n electrical characteristics table 8 lists the electri cal characteristics for the lvttl interface pins on the tsi564a table 8: lvttl i/o and open drain electrical characteristics symbol parameter min typ max unit notes v il lvttl input low voltage 0.8 v all inputs and i/os of lvttl type v ih lvttl input high voltage 2.0 v all inputs and i/os of lvttl type i il lvttl input low current 10 ua all non-pu inputs and i/os of lvttl type i ih lvttl input high current -10 ua all non-pd inputs and i/os of lvttl type i ozl_pu, i il_pu lvttl input low/ output tristate current 5 100 ua all pu inputs and i/os of lvttl type for voltages from 0 to v dd_33 on the pin. i ozh_pd, i ih_pd lvttl input high/ output tristate current -5 -100 ua all pd inputs and i/os of lvttl type for voltages from 0 to v dd_33 on the pin. v ol lvttl output low voltage 0.4 v i ol =2ma for int_b, sw_rst_b, and tdo pins i ol =8ma for i2c_clk and i2c_sd pins 2. electrical characteristics 260 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com v oh lvttl output low voltage v dd_33 -0.5 vi oh =2ma for int_b, sw_rst_b, and tdo pins v hyst lvttl input hysteresis voltage 200 mv all hyst inputs and i/os of lvttl type c pad lvttl pad capacitance 10 pf all pads of lvttl type t cfgps configuration pin setup time 100 ns for all configuration pins (except sp{n}_modesel with respect to hard_rst_b rising edge (see figure 6 ) t cfgph configuration pin hold time 100 ns for all configuration pins (except sp{n}_modesel) with respect to hard_rst_b rising edge (see figure 6 t sp_modesels sp{n}_modesel setup time 5 ns with respect to rising edge of p_clk. sp{n}_modesel pins are sampled on every rising edge of p_clk. (see figure 6 ) t sp_modeseh sp{n}_modesel hold time 5 ns with respect to rising edge of p_clk. sp{n}_modesel pins are sampled on every rising edge of p_clk. (see figure 6 ) t isov1 int_b/sw_rst_b output valid delay from rising edge of p_clk 15 ns measured between 50% points on both signals. output valid delay is guaranteed by design.(see figure 7 ) t isof1 int_b/sw_rst_b output float delay from rising edge of p_clk 15 ns a float condition occurs when the output current becomes less than i lo , where i lo is 2 x i oz . float delay guaranteed by design . (see figure 7 ) f in_pclk p_clk input clock frequency range 100 - 100 ppm 100 + 100 ppm mhz f in_pclk_dc p_clk input clock duty cycle 40 50 60 % see figure 8 j pclk p_clk input jitter 300 ps t r_pclk , t f_pclk p_clk input rise/fall time 2.5 ns rpu internal pull-up resistor 82 170 260 kohm at vol=0.8 v rpd internal pull-down resistor 28 40 54 kohm at vih=2.0 v table 8: lvttl i/o and open drain electrical characteristics symbol parameter min typ max unit notes 2. electrical characteristics 261 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 2.2.3 serial interface el ectrical characteristics table 9 lists the electri cal characteristics for the serial receiver interface pins on the tsi564a table 9: serial interface receiver input electrical characteristics symbol parameter min typ max unit notes z di rx differential input impedance 80 120 ohm v diffi rx differential input voltage 170 2000 mv l cr rx common mode return loss 6 db over a range 100mhz to 0.8* baud frequency l dr rx differential return loss 10 db over a range 100mhz to 0.8* baud frequency v los rx loss of input differential level 85 mv port receiver input level below which low signal input is detected j rt1250 rx total jitter tolerance (peak-to-peak) 0.71 uipp for 1.25gb/s +/- 100ppm @ber=10e-12 j rr1250 rx deterministic + random jitter component 0.61 uipp for 1.25gb/s +/- 100ppm @ber=10e-12 j rd1250 rx deterministic jitter component 0.45 uipp for 1.25gb/s +/- 100ppm j rt2500 rx total jitter (peak-to-peak) 0.67 uipp for 2.5gb/s +/- 100ppm @ber=10e-12 j rr2500 rx deterministic + random jitter component 0.57 uipp for 2.5gb/s +/- 100ppm @ber=10e-12 j rd2500 rx deterministic jitter component 0.42 uipp for 2.5gb/s +/- 100ppm j rt3125 rx total jitter (peak-to-peak) 0.65 uipp for 3.125gb/s +/- 100ppm @ber=10e-12 j rr3125 rx deterministic + random jitter component 0.55 uipp for 3.125gb/s +/- 100ppm @ber=10e-12 j rd3125 rx deterministic jitter component 0.41 uipp for 3.125gb/s+/- 100ppm t rx_ch_skew rx channel to channel skew tolerance 24 ns between channels in a given x4 port r tr, r tf rx input rise/fall times 160 ps between 20% and 80% levels 2. electrical characteristics 262 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com table 10 lists the electrical characteris tics for the serial transmi tter interface pins on the tsi564a table 10: serial interface transmit ter output electric al specifications symbol parameter min typ max unit notes z seo tx single-ended output impedance 40 50 60 ohm z do tx differential output impedance 80 100 120 ohm v sw tx output voltage swing (single-ended) 350 750 mvp- p v sw (in mv) = z seo /2 x inom x ridr/inom, where ridr/inom is the idr to inom ratio. v diffo tx differential output voltage amplitude 2 x vsw_ min 2 x vsw_ max mvp- p p v ol tx output low-level voltage v tt -(1.5 x vsw) v v oh tx output high-level voltage v tt -(0.5 x vsw) v v tcm tx common-mode voltage v tt - vsw v l dr1 tx differential return loss -10 db for (baud frequency)/10 2. electrical characteristics 264 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 2.2.5 serial interface capability and implementation the configuration settings for drv_strength and dtx give tsi564a serial interface the flexibility to configure transmitter output voltage am plitudes to optimize both power and serial link performance. it is possible to select combinations of these setting that allow the transmitter to operate outside of the rapidio specified limits. care must be used to select appropriate values for both drv_strength and dtx to match the serial link performance requirements and meet the limits defined for the tsi568. his is also true for the deq settings whic h are covered in the srio mac x serdes configuration registers . table 12 lists the amplitudes as stated in the rapidio interconnect speci fication (revision 1.2) . the tsi564a uses the drv_strength and dt x bits in each port srio mac x serdes configuration registers to control the drive current fo r each port. all four lanes are set to the same drive currents. table 13 shows the programming options for drv_st rength and drive currents outputs from the programming options. the serdes has been tested to meet the rapidio specification, however operation beyond this range is possible. table 12: rapidio specification requirements ranges tx amplitude limits rx amplitude limits min mvpp max mvpp min mvpp max mvpp short range 500 1000 200 1600 long range 800 1600 200 1600 table 13: drive current register setting drv_strength inom ma 0 1 10 0 0 20 1 0 28 1 1 reserved 2. electrical characteristics 265 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com table 14 shows the idr/inom ratio options as a func tion of the dtx[3:0] selection codes. .. the single-ended voltage swing for the serial transmitter output (v sw ) is determined by the following equation: ( section 2.2.5 -eq1) v sw (in mv) = z seo /2 x inom x ridr/inom , where ridr/inom is the idr to inom ratio there are possible combinations of drv_strength and dtx that will violate allowable output swing limits. allowable output swing amplitudes are limited by the v tt range used in the system. table 15 shows the output swing limits as a function of v tt . table 14: idr/inom ratios vs. dtx[3:0]swing into termination dtx[3:0] idr/inom ratio dtx[3:0] idr/inom ratio 0000 1.00 1000 0.60 0001 1.05 1001 0.65 0010 1.10 1010 0.70 00111.1510110.75 0100 1.20 1100 0.80 0101 1.25 1101 0.85 0110 1.30 1110 0.90 0111 1.35 1111 0.95 for proper performance it is required that th e inom and ridr/inom parameters be selected such that vsw calcul ated using equation section 2.2.5 -eq1 meet the requ irement specified in table 15 . table 15: v tt to output swing limits v tt maximum vsw 1.2 350mv 1.5 500mv 1.8 750mv 2. electrical characteristics 266 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 2.2.6 i 2 c interface ac specifications the dc characteristics of the i 2 c interface are defined in table 8 on page 259 . table 16 lists the ac specifications for tsi564a?s i 2 c interface (s ee notes below) . notes: 1. see figure 5 , i 2 c interface signal timings 2. after this period, the fi rst clock pulse is generated figure 5 shows i 2 c interface signal timings figure 5: i 2 c interface signal timings table 16: ac specifications for i 2 c interface symbol parameter min max units notes f scl sd_i2c_clk/i2c_s clk clock frequency 0 100 khz 10us t buf bus free time between stop and start condition 4.7 - s1 t low sd_i2c_clk/i2c _sclk clock low time 4.7 - s1 t high sd_i2c_clk/i2c _sclk clock high time 4 - s1 t hdsta hold time (repeated) start condition 4 - s1,2 t susta setup time for a repeated start condition 4.7 - s1 t hddat data hold time 0 3.45 s1 t sudat data setup time 250 - ns 1 t sr sd_i2c_clk, sd_i 2c_sda, i2c_sclk, and i2c_sda rise time - 1000 ns 1 t sf sd_i2c_clk, sd_i 2c_sda, i2c_sclk, and i2c_sda fall time - 300 ns 1 t susto setup time for stop condition 4 - s1 sda scl t buf stop start t low t hdsta t high t sr t hddat t sf t sudat t susta repeated t hdsta t sp stop t susto start 2. electrical characteristics 267 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 2.2.7 boundary scan interface ac specifications table 17 lists the signal timings for the b oundary scan interface for tsi564a. notes: 1. outputs precharged to v dd . 2. see figure 7 , ?output timing measurement waveforms?. 3. see figure 6 , ?input timing measurement waveforms?. 4. a float condition occurs when the output current becomes less than i lo , where i lo is 2 x i oz , the output tri-state dc current. float delay guaranteed by design. see figure 7 , ?output timing measurement waveforms?. table 17: boundary scan test signal timings symbol parameter min max units notes t bsf tck frequency 0 10 mhz - t bsch tck high time 50 - ns measured at 1.5v, 1 t bscl tck low time 50 - ns measured at 1.5v, 1 t bscr tck rise time - 25 ns 0.8v to 2.0v, 1 t bscf tck fall time - 25 ns 2.0v to 0.8v, 1 t sis1 input setup to tck 10 - ns 2 t bsih1 input hold from tck 10 - ns 2 t bsov1 tdo output valid delay from falling edge of tck. -15ns1 t of1 tdo output float delay from falling edge of tck -15ns3, 4 2. electrical characteristics 268 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 2.3 ac timing waveforms this section shows the ac timing waveforms for timing specifications for the tsi564a. 2.3.1 lvtll i/o pins figure 6 shows the input timing relationships for all lvttl input signals to the corresponding clock input. the waveform is generalized for both inpu t and clk naming. the parameter tis represents the setup time and the tih parameter represents the hold time. figure 6: input timing measurement waveforms. figure 7 shows the generalized output timing relationships for all lvttl i/o pins. the tov parameter represents the output valid time or propagation delay of a given output signal with respect to the corresponding clock input. figure 7: output timing measurement waveforms clk input valid v test v test v test t is t ih v tl v th v th v tl v max v test clk output float vtrise output delay rise output delay fall v tfall t ov t ov t of v tl v th 2. electrical characteristics 269 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com figure 8 shows the relationship for the clk duty cycle. the duty cycle by is defined as twh/tcyc and twl/tcyc, where twh/tcyc + twl/tcyc = 100% figure 8: duty cycle definition waveforms 2.3.2 serial interface pins figure 9 shows the important voltage levels and timi ng relationships for the serial interface transmitter and receiver pins. figure 9: serial interface transmitter and receiver signal waveforms figure 10 shows the important voltage levels and timing relationships for the serial reference clock inputs. tcyc clk twh twl ui sp{n}_{t,r}{a-d}_p sp{n}_{t,r}{a-d}_n v oh v tcm v ol v sw tr,tf sp{n}_{t,r}{a-d}_p sp{n}_{t,r}{a-d}_n tch_skew 0.8vsw 0.2vsw tskew 2. electrical characteristics 270 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com figure 10: serial reference clock waveforms tr,tf s_clk_p s_clk_n v cm tskew 0.8vsw 0.2vsw v sw 2. electrical characteristics 271 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 3. layout guidelines 272 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 3. layout guidelines this chapter describes the layout guidelines for the tsi564a. it includes the following information: ? ?impedance requirements? on page 272 ? ?tracking topologies? on page 272 ? ?power distribution? on page 285 ? ?decoupling requirements? on page 285 ? ?clocking and reset? on page 289 ? ?modeling and simulation? on page 293 ? ?testing and debugging cons iderations? on page 294 ? ?reflow profile? on page 296 3.1 overview the successful implementation of a tsi564a in a board design is dependent on properly routing the serial rapidio signals and maintaining good signal integrity with a resultant low bit error rate. the sections that follow contain inform ation for the user on principals th at will maximize the signal quality of the links. since every situation is different, tundra urges the designer to model and simulate their board layout and verify that the layout topo logies chosen will provide the pe rformance required of the product. 3.2 impedance requirements the impedance requirements of th e serial rapidio interface are: ? 100 ohms differential ? 50 ohms single-ended 3.3 tracking topologies the tracking topologies required to maintain a cons istent differential impedance of 100 ohms to the signal placed on the transmission lin e are limited to stripline and micr ostrip types. th e designer must decide whether the signalling must be moved to an outer layer of the board using a microstrip topology, or if the signalling may be placed on an inner laye r as stripline where shielding by ground and power planes above and below is possible. 3. layout guidelines 273 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 3.3.1 stripline the rapidio buses should be routed in a symmetri cal edge-coupled striplin e structure in order to ensure a constant impedance environment. the symmetrical stripline construction is shown in figure 11 . this method also provides clean and equal return paths through vss and vdd from the i/o cell of the tsi564a to the adjacent rapidio device. the use of broadside coupled stripline construction as shown in figure 12 is discouraged because of its inabil ity to maintain a constant impedance throughout the entire board signal layer. the minimum recommended layer count of a board desi gn consists of 12 layers. the optimum design consists of 16 layers. the designer should consider both of these designs an d weigh their associated costs versus performance. figure 11: recommended edge coupled differ ential stripline (symmetric when h1=h2) equations for stripline and differen tial stripline impedance (in ohms): the broadside coupled stripline c onstruction is not recommended for use with rapidio because of the manufacturing variations in layer spacings. these variations will cau se impedance mismatch artifacts in the signal waveforms and will degrade the performance of the link. w s h1 h2 t power/ground plane power/ground plane ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? + ? 2 1 9 . 2 374 . 0 1 2 h h s e zo zdiff () () ? ? ? ? ? ? ? ? + + + = t w t h h zo r 8 . 0 67 . 0 ) 2 1 ( 2 9 . 1 ln 60 3. layout guidelines 274 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com figure 12: not recommended broadside c oupled or dual stripline construction 3.3.1.1 microstrip when it is necessary to place the differential si gnal pairs on the outer surfaces of the board, the differential microstrip construction is used. figure 13 shows the construction of the microstrip topology. below the figure are the design equations for calculating the imped ance of the trace pair. figure 13: differential microstrip construction equations for the differential microstrip construction: t b b c w h dielectric signal layer signal layer t b b c w h dielectric signal layer signal layer t w w s h d e r () ohms t w h r o z ? ? ? ? ? ? + + = 8 . 0 67 . 0 4 ln 67 . 0 475 . 0 60 ohms e z z h s o diff ? ? ? ? ? ? ? ? ? ? ? 96 . 0 48 . 0 1 2 3. layout guidelines 275 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 3.3.1.2 signal return paths the return path is the route that current takes to re turn to its source. it can take a path through ground planes, power planes, other signals, or integrated circuits. the return path is based on electro-magnetic field effects. the return path fo llows the path of least resistance nearest to the signal conductor. discontinuities in the return path of ten have signal integrity and timing effects that are similar to the discontinuities in the signal conductor. therefore, the return paths need to be given similar consideration. a simple way to evaluate return path parasitic inductance is to draw a loop that traces the current from the driver through the signal con ductor to the receiver, then back through the ground/power plane to the driver again. the smaller the area of the loop, the lower the parasitic inductance. if via densities are large and most of the signals swit ch at the same time (as would be the case when a whole data group switches layers), the layer to la yer bypass capacitors fail to provide an acceptably short signal return path to ma intain timing and noise margins. since the signals are routed using symmetric striplin e, return current is pr esent on both the vdd and vss planes. if a layer change must occur, then vcc and vss vias must be placed as close to the signal via as possible in order to provide the sh ortest possible path fo r the return current. the following return path rules apply to all designs: ? always trace out the return current path and provide as much care to the return path as the path of the signal conductor. ? do not route impedance cont rolled signals over splits in the reference planes. ? do not route signals on the reference planes in the vicinity of system bus signals. ? do not make signal layer changes that force the return path to make a reference plane change. ? decoupling capacitors do not adequa tely compensate for a plane split. ? do not route over via anti -pads or socket anti-pads. if reference plane chan ges must be made: ? change from a vss reference plane to another vs s reference plane and pla ce a via connecting the two planes as close as possible to the signal vi a. this also applies when making a reference plane change from one vcc plane to another vcc plane. ? for symmetric stri pline, provided return path vias for both vss and vcc. ? do not switch the reference plan e from vcc to vss or vice versa. 3.3.1.3 guard traces guard traces are used to minimize cr osstalk. guard traces are tracks that run parallel to a signal trace for the entire length and are conn ected to the reference plane to wh ich the signal(s) are associated. guard traces can lower the radiated cr osstalk by as much as 20db, but wi ll also lower the characteristic impedance of the signal trace due to their proximity. 3. layout guidelines 276 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com the use of guard tracks requires some planning and foresight. the guard tracks will consume board real estate. simulati on has shown that a 5 mil ground trace wi th 5 mil spaces between the aggressor and receptor traces offers as much is olation as a 20 mil space between aggressor and receptor traces. the aggressor trace is the trace with a driven waveform on it. the receptor trace is the trace onto which the crosstalk is coupled. guard tracks are required to be stitched or connected with vias to the refere nce plane associated with the aggressor signal. to ensure that there is no re sonance on the guard traces the stitching vias should be spaced at intervals that equal 1/20 of the 3 rd harmonic. figure 14: equation in the case of the 3.125 gbits/s data rate, the rise and fall times must be less th an 40 ps. this relates to an upper frequency of 25ghz and a corresponding wave length of 25 mm based on a permittivity of 4.3. therefore, the stitching vias must not be further apart than 8 mm. 3.3.1.4 via construction due to the high frequency content of the serial ra pidio signals, it is necessary to minimize the discontinuities im posed by crossing ground and power planes when it is necessary to transition to different signal layers. the use of a controlled impedance via is necessa ry. the construction of the vias is shown in figure 15 . tip detailed design information can be found in bibliography entry 15, ? designing controlled impedance vias ? by thomas neu, edn ma gazine october 2, 2003. r rd rd r f s m f c 3 8 3 20 / 10 3 20 1 = = 3. layout guidelines 277 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com figure 15: differential controlled impedance via 3.3.1.5 layer transitioning with vias the basic rule is to keep vias in the signal path down to a minimum. vias represent a significant impedance discontinuity and should be minimized. when routing vias, try to ensure that signals travel through the via rather than across the via. a via where the signal goes through the via, has a much different effect than a via where the signal travels across the via. these two cases are shown in figure 17 and in figure 18 . the ?in? and ?out? nodes of the via model are shown on the thei r corresponding locations in the figures. transitioning across a via that is not blind or bu ried leaves a stub which appears as a capacitive impedance discontinuity. the portion of the via that conducts current appears inductive while the stub that develops only an electri c field will appear capacitive. in order to minimize the effects of a via on a signal, the follow ing equations ma y be used to approximate the capacitance and inducta nce of the via design. it can be seen that the proximity of the pad and antipad have a direct rela tionship on the capacitance, and that the length of the barrel (h) has a direct effect on the inductance. reference ground plane r e f e r e n c e g r o u n d p l a n e reference ground plane r e f e r e n c e g r o u n d p l a n e signal via anti-pad which touches the ground vias 4 vias connected to ground planes differential signal l 5.08 h 4 h d ----- - ?? ?? 1 + ln = c 1.41 r td 1 d 2 d 1 ? -------------------------- = 3. layout guidelines 278 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com c is the capacitance in pf. t is the thickness of the circuit board or thickness of pre-preg. d 1 is the diameter of the via pad. d 2 is the diameter of the antipad. r is the dielectric constant of the circuit board material. l is the inductance in nh. h is the overall length of the via barrel. d is the diameter of the via barrel. figure 16: via construction figure 17: signal across a via d2 d1 d t t h signal signal "in" "out" stub via pwr & gnd planes 3. layout guidelines 279 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com figure 18: signal through a via because of the high frequencies pres ent in the rapidio signal, vias be come a significant contributor to signal degradation. most vias are formed by a cylinder going through the pcb board. because the via has some length, there is an indu ctance associated with the via. parasitic ca pacitance comes from the power and ground planes through which the via passes . from this structure we model the via in rlc lumps as shown in figure 19 and figure 20 . cvia is the total capacitance of the via to ground or power, rvia is the total resistance through the via, and lvia is the total inductance of the via. these parameters may be extracted using 3d parasitic extraction t ools. by distributing the r, l, and c, the model better represents the fact that the capacitance, resistance and inductance are distributed across the length of the via. for the via model to be accurate in simu lation, the propagation delay of each lc section should be less than 1/10 of the si gnal risetime. this is to ensure the frequency response of the via is modeled correctly up to the frequencies of interest. more information may be found in reference [16]. figure 19: signal transitioning across a via simulation model figure 20: signal transitioning through a via simulation model 3.3.1.6 buried vs. blind the use of buried and blind vias is recommended because in both cas es the signal travels through the via and not across it. exampl es of these two types of structures are shown in figure 21 and figure 22 . signal "in" "out" pwr & gnd planes via signal in rvia/3 rvia/3 rvia/3 lvia/3 lvia/3 lvia/3 cvia/4 cvia/4 cvia/4 cvia/4 out in rvia/3 rvia/3 rvia/3 lvia/3 lvia/3 lvia/3 cvia/4 cvia/4 cvia/4 cvia/4 out 3. layout guidelines 280 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com figure 21: buried via example figure 22: blind via example 3.3.1.7 serpentine traces during layout, it is necessary to adjust the lengths of tracks in or der to accommodate the requirements of equal track lengths for pairs of signals. in the ca se of the lvds/cml signals, this ensures that both the negative and positive halves of the signals arri ve at the receiver simultane ously, thus maximizing the data sampling window in the eye diagram. creating a serpentine track is a method of adjusting the track length. ensure that the wave front does not propagate along the trace and through the crosstalk path perpendicular to the parall el sections, as shown in figure 23 . the arrival of a wave front at the receiver ahead of the wave front travelling along the serpentin e route is caused by the self-coupling between the parallel sections of the transmission line (lp). signal "in" "out" pwr & gnd planes via signal signal "in" "out" pwr & gnd planes via signal 3. layout guidelines 281 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com figure 23: serpentine signal routing figure 26 describes the guidelines for length matching a di fferential pair.if it is necessary to serpentine a trace, follow these guidelines: ? make the minimum spacing between parallel s ections of the serpentine trace (see ?s? in figure 23 ) at least 3 to 4 times the distance between the sign al conductor and the reference ground plane. ? minimize the total length (see ?lp? in figure 23 ) of the serpentine section in order to minimize the amount of coupling. ? use an embedded microstrip or striplin e layout instead of a microstrip layout. 3.3.2 crosstalk considerations the serial rapidio signals easily capacitively couple to adjacent signals due to their high frequency. it is therefore recommended that adequate space be us ed between different differential pairs, and that channel transmit and receive be routed on different layers. cross coupling of di fferential signals results in an effect called inter-symbol interference (isi). this coupling causes pattern dependent errors on the receptor, and can substantially incr ease the bit error rate of the channel. to maximize the signal integrity, cl ock lines should not be serpentine. tip for a detailed discussion about serpentine layouts, refer to section 12.8.5 of ?high-speed signal propagation, advanced black magic? by howard johnson and martin graham. lp s driver reciever crosstalk path 3. layout guidelines 282 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 3.3.3 receiver dc bl ocking capacitors the serial rapidio interface require s that the port inputs be capacitor coupled in order to isolate the receiver from any common mode offset that may be present in the transmitte r outputs. dc blocking capacitors should be selected such that they have low dissipation factor and low series inductance. figure 24 shows the recommended tracking and capacitor pa d placement required. it will be necessary to model and simulate the effects of the changed tr ack spacing on the channel quality and determine if any changes are required to the topology. an often used method of correcting the decreased impedance caused by the larger capacito r mounting pads is to create a slot in the shield plane below the capacitor bodies and soldering pads. sin ce the impedance change caused by the slot is dependent on the capacitor geometry, core thickness, core material characteristics and layer spacings, the size and shape of the slot will have to be determined by simulation. figure 24: receiver coupling capaci tor positioning recommendation 3.3.4 escape routing all differential nets should maintain spacing throug hout a route. separation of differential pairs to go around objects should not be allowed. figure 25 illustrates several options for breaking out a differential pair from the tsi564a device. the order of preference is from a to d. case d below has a small serpentine section used to match the inter-pair skew of the differential pair. in this case each serpentine section should be grea ter than 3 x w (w=width), and the gap should not increase by more than 2x. figure 26 illustrates these requirements. do not place the capacitors along the signal trace at a /4 increment from the driver in order to avoid possible standing wave effects. 3. layout guidelines 283 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com figure 25: escape routing for differential signal pairs figure 26: differential skew matching serpentine 3.3.5 board stackup the recommended board stack up is shown in figure 27 . this design makes provi sion for four stripline layers and two outer microstrip laye rs. layers eight and nine are prov isioned as orthogonal low speed signal routing layers. 3. layout guidelines 284 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com figure 27: recommended board stackup 3. layout guidelines 285 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 3.4 power distribution the tsi564a is a high speed device with both digita l and analogue components in its design. the core logic has a high threshold of nois e sensitivity within its 1.2v opera ting range. however, the analogue portion of the switch is considerably more sensitive. the correct treatment of the power rails, plane assi gnments and decoupling is important to maximizing the performance the tsi564a can deliver. the larges t indicator of poor performance on the serial rapidio interfaces is the presence of jitter. the die, i/o and package designs ha ve all been optimized to provide jitter performance well below the limits required by the se rial rapidio specifications. the guidelines provided below wi ll assist the user in ac hieving a board layout that will provide the best performance possible. the required decoupli ng by each voltage rail can be found in table 18 on page 286 . the ripple specifications for each rail are ma ximums, and every effort should be made to target the layout to achieve lower values in the design. a solid, low impedance plane must be provided for th e vdd 1.2v core supply re ferenced to vss. it is strongly recommended that the v dd and vss planes be constructed with the intent of creating a buried capacitance. the connection to the power supply must also be low impedance in order to minimize noise conduction to the other supply planes. a solid, low impedance pl ane must be provided for the sp_vdd 1. 2 v serdes supply , referenced to the vss plane. this supply can be derived from the same power supply as vdd, as long as a kelvin connection is used. the preference however, is to use a separate power supply. the spn_avdd 1.2 v serdes analogue supply also needs to be sourced from a low impedance supply plane. this supply voltage powe rs the serdes plls. the sp_vdd plane may also be used for the spn_avdd supply. connect all of the spn_avdd pins to this plane through the filters shown in figure 29 and decouple the plane directly to vss. the vdd_io supply powers the 3.3v i/o cells on th e switch. this supply re quires no special filtering other than the decoupling to the vss_io plane. connect the vss_io plane to the vss plane using a kelvin connection. 3.5 decoupling requirements this section deals with the subj ect of decoupling capacitors requ ired by the tsi564a . to accomplish the goal of achieving maximum performance and re liability, the power su pply distribution system needs to be broken down into its individual pieces, and each designed carefully. the standard model for representing the components of a typical system are shown in figure 28 . this figure graphically represents the parasiti cs present in a power distribution system. 3. layout guidelines 286 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com figure 28: system power supply model 3.5.1 component selection the recommended decoupling capacitor usag e for the tsi564a is shown below in table 18 on page 286 . the capacitors should be select ed with the smallest surface mount body that the applied voltage permits in order to minimize the body inductance. the components should be distribu ted evenly around the device in order to provide filtering and bulk energy evenly to all of the ports. the serdes plls require extra care in order to minimize jitter on the transmitted signals. the circuit shown in figure 29 is recommended. one filter is required fo r each rapidio port. figure 29: pll filter use the tsi564a ball map (available at www.tu ndra.com) to aid in the distribution of the capacitors. table 18: decoupling capacitor quantities and values recommended for the tsi564a voltage usage acronym component requirements 1.2v logic core vdd 20 x 0.1uf 20 x 0.01uf 16 x 1nf 16 x 22uf 1.2v serdes core, serdes bias serial drivers sp_vdd 8 x 0.1uf 48 x 0.01uf 8 x 10uf 8 x 100uf 1.5v serdes termination supply vtt 8 x 0.1uf 8 x 0.01uf -- -- 3.3v single ended i/o ports vdd_io 12 x 0.1uf 12 x 0.01uf -- -- 1.2v pll spn_avdd 8 x 0.1uf 8 x 0.01uf 8 x ferrite bead 120 ohm @ 1.5amp + - vdd power rp lp cp rdc ldc cdc rsb lsb csb lpcb rpcb decoupling substrate tsi574 die power delivery system spn_avdd 0.01uf 0.1uf 120 @1.5a 1.2v 3. layout guidelines 287 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 3.5.1.1 effective pad design breakout vias for the decoupling ca pacitors should be kept as clos e together as possible. the trace connecting the pad to the via should also be kept as short as possible with a maximum length of 50mils. the width of the breakout traces shoul d be 20mils, or the width of the pad. figure 30: recommended decoupling capacitor pad designs 3.5.2 power plane impe dance and resonance the intent of adding decoupling to a board is to lo wer the impedance of the power supply to the devices on the board. it is necessary to pay attention to th e resonance of the combined bulk capacitance and to stagger the values in order to spread the imped ance valleys broadly acros s the operating frequency range. figure 31 demonstrates the concept of staggered ba nds of decoupling. calculate the impedance of each of the capacitor va lues at the knee frequency to de termine their impact on resonance. via sharing should not be used in board design with the tsi564a. f knee 0.5 t rise ----------- where t rise time from 10% to 90% = = 3. layout guidelines 288 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com figure 31: decoupling bypass frequency bands as the frequency changes, each part of the pd s responds proportionally; the low-impedance power supply responds to slow events, bulk capac itors to mid-frequency events, and so forth. 3. layout guidelines 289 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 3.6 clocking and reset this section discusses the requiremen ts of the clock and reset inputs. 3.6.1 clock overview the tsi564a has three input reference clocks that are used to produce the tsi564a internal clock domains. the following diagram illustrates the cl ocking architecture of the tsi564a. figure 32: tsi564a clocking architecture i 2 c_sclk pin pin pin pin p_clk s_clk_0 s_clk_1 i 2 c internal registers and bus ? : ? 2 serial port 0 clk gen serial port 6 clk gen serial port 0 logic serial port 1 logic serial port 0 serdes serial port 6 logic serial port 7 logic serial port 6 serdes internal switching fabric rxclka rxclkb rxclkc rxclkd txclk rxclka rxclkb rxclkc rxclkd txclk 3. layout guidelines 290 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com the three reference cloc ks are described in table 19 . each of the listed cloc k domains is described in detail in the following sub-section. for more information about special line rate support see ?line rate support? on page 298 . 3.6.1.1 frequencies required the clock signals should be shield ed from neighboring signal lines using ground traces on either side. this reduces jitter by minimizing crosstalk from the neighboring signal lines. since p_clk is single-ended, extra precaution should be taken so that noise does not get coupled onto it. in order to preserve the quality of the low jitter cl ock, the shielding requirement of the clock lines is critical. it is possible that lo w-frequency noise can interfere with the operation of plls, which can cause the plls to m odulate at the same frequenc y as the noise. the high-fre quency noise is generally beyond the pll bandwidth which is about 1/10th the refclk frequency. 3.6.1.2 stability, jitter and noise content the maximum input jitter on the s_clk_1 and s_clk_2 inputs is 7ps peak to peak from 1.8 to 32 mhz to avoid passing through the pll loop filter in the serdes and afftecting th e transmit data streams. the maximum input jitter allowable on the p_clk inpu t is 300 pspp. jitter on this input would be reflected outside of the chip on the i 2 c bus. jitter equation the following equation can be used to co nvert phase noise in dbc to rms jitter: rmsjitter ps(rms) = [((10 (dbc/10) ) 1/2 ) * 2] / [2 * pi * (frequency in hz)] using this equation, an example of 312.5 mhz an d a phase noise of -63dbc, would produce 0.72ps rms jitter. table 19: clock input sources clock input pin type maximum frequency clock domain s_clk_1_[p/n] differential 312.5 mhz serial transmit domain 2 (nominally 312.5mhz) internal switching fabric (isf) domain s_clk_2_[p/n] differential 250 mhz serial transmit domain 1 (nominally 250 mhz) serial transmit domain 0 (nominally 125 mhz) note: if the tsi564a never uses serial transmit domains 1 and 2, then this input reference clock is not required to be driven. p_clk single ended 100 mhz internal register domain and i 2 c domain 3. layout guidelines 291 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 3.6.2 clock domains 3.6.2.1 interfacing to the s_clk_x inputs the interface for a lvpecl or cml clock source to the converter cell is shown in figure 33 . note that an ac-coupled interface is required so that only the ac information of the clock source is transmitted table 20: tsi564a clock domains clock domain clock source description internal register domain p_clk this clock domain in cludes all of the internal registers and their interconnect bus. the domain uses the input p_clk directly. internal switching fabric domain s_clk_1_[p/n] divided by 2 this clock domain includes the switching matrix of the isf and the portion of each rapidio block that interfaces to the isf. i 2 c domain p_clk divided by 1000 this clock domain is responsible for driving the i 2 c output clock pin i2c_sclk. this clock domain is generated by dividing the p_clk input by 1000. the majority of the i 2 c logic runs in the internal register domain serial transmit domain 0 s_clk_2_[p/n] divided by 2 this clock domain is used to clock all of the serial rapidio transmit ports that have the sclk_sel field in the smacx_clk_sel register set to 00. the s_clk_2_p/n input is divided in half and used to clock the transmit logic. this clock is multiplied by 10 to produce the high-speed clock that is used to output the serial data on output pins sp{0..15}_t{a..d}_p/n. the maximum data rate available using this domain is 1.25 gb/s per lane. serial transmit domain 1 s_clk_2_[p/n] this clock domain is used to clock all of the serial rapidio transmit ports that have the sclk_sel field in the smacx_clk_sel register set to 01. the s_clk_2_p/n input is used directly to clock the transmit logic. this clock is multiplied by 10 to produce the high-speed clock that is used to output the serial data on output pins sp{0..15}_t{a..d}_p/n. the maximum data rate available using this domain is 2.5 gb/s per lane. serial transmit domain 2 s_clk_1_[p/n] this clock domain is used to clock all the serial rapidio transmit ports that have the sclk_sel field in the smacx_clk_sel register set to 10. the s_clk_1_p/n input is used directly to clock the transmit logic. this clock is multiplied by 10 to produce the high-speed clock that is used to output the serial data on output pins sp{0..15}_t{a..d}_p/n. the maximum data rate available using this domain is 3.125 gb/s per lane. 3. layout guidelines 292 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com to the clock inputs of the tsi564a. figure 33: tsi564a driven by lvpecl or cml clock source the interface for an lvds clock source to the converter cell is shown in figure 34 . since an lvds driver requires a dc termination path, a 2-k. resist or should be inserted be fore the capacitors. this resistor can be placed anywhere along the signal path between th e clock source and the ac-coupling capacitors, although tundra recommends placing it cl ose to the clock source. note that the effective termination resi stance seen by the clock source is about 95 . due to the parallel combination of this external resistor and the integrated termination resi stor of the converter cell. again, an ac-coupled interface is required so that only the ac information of the clock source is transmitted to the clock inputs of the tsi564a. figure 34: tsi564a driven by an lvds clock source 3.6.3 reset requirements the tsi564a requires only one reset input, hard_rst_b. the signal provided to the device must be a monotonic 3.3v swing that de-asserts a minimum of 1ms after supply rails are stable. the signal de-assertion is used to release synchronizers based on p_clk which control the release from reset of the internal logic. p_clk must therefore be op erating and stable befo re the 1ms hard_rst_b countdown begins. trst_b must be asserted while hard_rst_b is a sserted following a device power-up to ensure the correct setup of the tap controller. trst_b is no t required to be re-asserted for non power cycle assertions of hard_rst_b. tip the most versatile solution to this require ment is to and the hard_rst_b and trst_b signals together to form an output with which to drive the trst_b pin on the switch. tsi574 s_clk_p s_clk_n clock source lvpecl / cml pcb traces tsi574 s_clk_p s_clk_n clock source lvds pcb traces 2k 3. layout guidelines 293 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com power up option pins are double sampled at the releas e of hard_rst_b. as such, there is no set-up time requirement, but the signals must be stable at the releas e of hard_rst_b. there is a hold time requirement of 100ns or 10 p_clk cycles minimum. 3.7 modeling and simulation the need for verifying the signal integrity of the bo ard design is very important for designs using ghz signalling. tundra recommends that the designer invest in a simulation tool as an aid to a successful rapidio design. tools are availa ble from companies su ch as mentor graphics (hyperlynx ghz), ansoft (siwave) and sisoft (siauditor). this is by no means a complete list, only a sample of known suppliers. 3.7.0.1 ibis the use of ibis for signal integrity checking at the high frequencies of the serial rapidio link have been found to be too inaccurate to be useful. also, we have found that most tools do not yet support the ibis specification (revision 3.2) for the support of multi-staged slew rate controlled buffers. for this reason, tundra is not presently making av ailable an ibis file for the tsi564a. 3.7.0.2 encrypted hspice please contact the tundra applications en gineering through the web based form at www.tundra.com/supp ort to request the necessary non-disclosure agreement form required to acquire the encrypted model. 3. layout guidelines 294 tsi564a hardware manual 80b802a_ma002_04 tundra semiconductor corporation www.tundra.com 3.8 testing and debugging considerations it is prudent to make provision for debugging and te sting tools in order to sp eed board bring-up. this section provides information on the probing requi rements for monitoring the serial rapidio link between two devices. at ghz frequencies, standa rd probing techniques are intrusive and cause excessive signal degradation intr oducing additional errors in th e link stream. the recommended solution is an ultra low capacitance probe that ope rates in conjunction with a logic analyzer. the addition of the appropriate disass embler software to the analyzer makes it a very powerful tool for examining the traffic on a link a nd aiding in software debugging. please contact your local test equipment vendor for appropriate solutions for your requirements. 3.8.1 logic analyzer connection pads the pinout for a recommended srio 8-channel probe is given in table 21 . this pin/signal assignment has been adopted by several tool vendors includi ng tektronix, but is not an established standard. these notes are given here: footprint channel vs. lane/link designations ? channel = either an upst ream or downstream differen tial pair for a given lane ? c = the two signals of the differen tial pair. the signals with in a given pair may be assigned to either p or n regardless of polarity. 3.8.1.1 general rules for signal pa ir assignment of analyzer probe the differential pairs that make up the srio links mu st be assigned to specific pins of the footprint. however, there is some freedom in this pair assignm ent in order to minimize routing constraints on the platform. table 21: 8-channel probe pin assignment pin # signal name pin # signal name 2gnd1cap/tx0 4 cbp/rx0 3 can/tx0 6cbn/rx05 gnd 8 gnd 7 ccp/tx1 10 cdp/rx1 9 ccn/tx1 12 cdn/rx1 11 gnd 14 gnd 13 cep/tx2 16 cfp/rx2 15 cen/tx2 18 cfn/rx2 17 gnd
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