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sp574b/674b/1674b/774b 12Cbit sampling a/d converters ? copyright 2000 sipex corporation 1 n complete monolithic 12Cbit a/d converters with sampleChold, reference, clock and triC state outputs n full nyquist sampling at all sample rates n choice of sampling rates 40khz, 66khz, 100khz or 125khz n low power dissipation 110mw n 12Cbit linearity over temperature n commercial, industrial and military tempera- ture ranges n nextCgeneration replacement for 574a, 674a, 1674a, 774a devices 1 1413121110987654 3 2 28 1516171819202122232425 26 27 sts db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 dgnd v logic 12/8 cs a 0 r/c ce v cc ref out agnd ref in v ee bip off 10v in 20v in nibble a nibble b nibble c three?tate buffers and control n/c 7.5k 15k15k 7.5k 7.5k offset/gain trim 12?it capacitance dac comp ref control logic 12?it sar osc description the sp574b/674b/1674b/774b (spx74b) series are complete 12Cbit successiveCapproxi- mation a/d converters integrated on a single die with tri-state output latches, an internal reference, clock and a sampleChold. the new bCseries features true nyquist sampling while maintaining compatibility with prior versions. they are dropCin replacements for the older 574a/ 674a/1674a/774a type devices. ? sp574b/674b/1674b/774b 12Cbit sampling a/d converters obsolete - historical reference only
sp574b/674b/1674b/774b 12Cbit sampling a/d converters ? copyright 2000 sipex corporation 2 absolute maximum ratings v cc to digital common .................................................. 0 to +16.5v v logic to digital common ................................................... 0 to +7v analog common to digital common ......................................... 1v control inputs to digital common ................. C0.5v to v logic +0.5v (ce, cs, a 0 , 12/8, r/c) analog input voltage range ........................................... fs 30% analog inputs to analog common ...................................... 16.5v (ref in, bip off, 10v in ) 20v in to analog common ........................................................ 24v ref out ............................................... indefinite short to common ................................................................... momentary short to v cc power dissipation ............................................................. 1000mw lead temperature, soldering .................................. 300?c, 10sec j/c ..................................................................................... 45?c/w mtbfC25?c ground base ................................ 2.915 million hours mtbfC125?c missile launch ...................... 10.16 thousand hours ? inputs exceeding +30% or C30% of fs will cause erratic performance. caution: esd (electrostatic discharge) sensitive device. permanent damage may occur on unconnected devices subject to high energy electrostatic fields. unused devices must be stored in conductive foam or shunts. personnel should be properly grounded prior to handling this device. the protective foam should be discharged to the destination socket before devices are removed. specifications (typical @ 25 c with v cc = +15v, v ee = 0v, v logic = +5v unless otherwise noted.) parameter min. typ. max. unit conditions resolution all models 12 bits analog inputs input ranges bipolar 5, 10 v unipolar 0 to +10, 0 to +20 v input impedance sp574b/sp674b 10 volt input 3.75 6.25 k w 20 volt input 15 25 k w sp1674b/sp774b 10 volt input 1.875 3.125 k w 20 volt input 7.45 12.42 k w nyquist frequency sp574b 20 khz sp674b 33 khz sp1674b 50 khz sp774b 62.5 khz digital inputs logic inputs ce, cs r/c, a o , 12/8 logic 1 +2.4 +5.5 v logic 0 C0.3 +0.8 v current 0.1 50 m a C0.3v to +5.5v input 5 m a 0v to +5.5v input capacitance 5 pf 12/8 control input hardwire to v logic or digital common digital outputs logic outputs db 11 Cdb 0 , sts logic 1 +2.4 v i source 500 m a logic 0 +0.4 v i sink 1.6ma leakage (high z state) 40 m a data bits only capacitance 5 pf parallel data output codes unipolar positive true binary bipolar positive true offset binary internal reference output voltage 10.00 0.1 v output current 2 m a note 1 obsolete - historical reference only
sp574b/674b/1674b/774b 12Cbit sampling a/d converters ? copyright 2000 sipex corporation 3 specifications (continued) (typical @ 25 c with v cc = +15v, v ee = 0v, v logic = +5v unless otherwise noted.) parameter min. typ. max. unit conditions conversion time sp574b 12Cbit conversion 13 25 m s 8Cbit conversion 10 19 m s sp674b 12Cbit conversion 9 1 5 m s 8Cbit conversion 6 11.2 m s sp1674b 12Cbit conversion 5 1 0 m s 8Cbit conversion 4 7.6 m s sp774b 12Cbit conversion 4 8 m s 8Cbit conversion 3 6 m s accuracy linearity error Ca, Cj, Cs 1.0 lsb @ 25 c and t min to t max Cb, Ck, Ct 0.5 lsb @ 25 c and t min to t max differential linearity error note 2 Ca, Cj, Cs 11 bits @ 25 c 11 bits t min to t max Cb, Ck, Ct 12 bits @ 25 c 12 bits t min to t max offset note 3 unipolar 3 lsb bipolar Ca, Cj, Cs 10 lsb Cb, Ck, Ct 4 lsb full scale (gain) error % of full scale; t min to t max 0.3 %fs note 4 Ca 0.6 %fs no adjustment @ 25 c 0.3 %fs with adjustment @ 25 c Cb 0.45 %fs no adjustment @ 25 c 0.15 %fs with adjustment @ 25 c Cj 0.5 %fs no adjustment @ 25 c 0.22 %fs with adjustment @ 25 c Ck 0.4 %fs no adjustment @ 25 c 0.12 %fs with adjustment @ 25 c Cs 0.8 %fs no adjustment @ 25 c 0.5 %fs with adjustment @ 25 c Ct 0.6 %fs no adjustment @ 25 c 0.25 %fs with adjustment @ 25 c stability unipolar offset Cj 10 ppm/ ct min to t max Ck, Ca, Cs 5 ppm/ ct min to t max Cb, Ct 2.5 ppm/ ct min to t max bipolar offset Cj, Ca, Cs 10 ppm/ ct min to t max Ck, Cb, Ct 5 ppm/ ct min to t max gain (scale factor) Cj, Ca, Cs 50 ppm/ ct min to t max Ck, Cb, Ct 25 ppm/ ct min to t max obsolete - historical reference only
sp574b/674b/1674b/774b 12Cbit sampling a/d converters ? copyright 2000 sipex corporation 4 typical ac dynamics measurement/model sp574b sp674b sp1674b sp774b unit test conditions: sampling rate 40 67 100 125 khz input frequency (f in )19314961khz sfdr 90 85 80 77 db thd -80 -80 -77 -76 db sinad 72 72 71 71 db snr 72.5 72.5 72.5 72.5 db note: 1. refer to figure 10, for typical fft at nyquist sampling rate. specifications (continued) (typical @ 25 c with v cc = +15v, v ee = 0v, v logic = +5v unless otherwise noted.) parameter min. typ. max. unit conditions power requirements v logic +4.5 +5.5 v i logic sp574b 13 ma sp674b 13 ma sp1674b 13 ma sp774b 13 ma v cc +11.4 +16.5 v i cc sp574b 79 ma sp674b 79 ma sp1674b 10 12.5 ma sp774b 10 12.5 ma power dissipation sp574b 110 150 mw sp674b 110 150 mw sp1674b 155 200 mw sp774b 155 200 mw environmental operating temperature range Cj, Ck 0 +70 c Ca, Cb C40 +85 c Cs, Ct C55 +125 c storage temperature range Cj, Ck C40 +85 c Ca, Cb, Cs, Ct C65 +150 c notes: 1. available for external loads. external load should not change during conversion. when supplying an external load and operating on a +12v supply, a buffer amplifier must be provided for the reference output. 2. minimum resolution for which no missing codes are guaranteed. 3. externally adjustable to zero. see calibration information. 4. fixed 50 w resistor between ref out and ref in. 5. specifications are identical for all models unless otherwise noted. obsolete - historical reference only
sp574b/674b/1674b/774b 12Cbit sampling a/d converters ? copyright 2000 sipex corporation 5 circuit operation the spx74b are complete monolithic capacitor dacCbased 12Cbit analog-to-digital convert- ers with integral voltage reference, comparator, successiveCapproximation register (sar), sampleCandChold, clock, output buffers and control circuitry. the high level of integration of the spx74b series means they require few external components. when the control section of the spx74b initiates a conversion command, the clock is enabled and the successiveCapproximation register is reset to all zeros. once the conversion cycle begins, it can not be stopped or restarted and data is not available from the output buffers. the sar, timed by the clock, sequences through the conversion cycle and returns an endCofCconvert flag to the control sec- tion of the adc. the clock is then disabled by the control section, the output status goes low, and the control section is enabled to allow the data to be read by external command. the internal spx74b 12Cbit cdac is sequenced by the sar starting from the msb to the lsb at the beginning of the conversion cycle to provide an output voltage from the cdac that is equal to the input signal voltage (which is divided by the input voltage divider network). the com- parator determines whether the addition of each successivelyCweighted bit voltage causes the cdac output voltage summation to be greater or less than the input voltage; if the sum is less, the bit is left on; if more, the bit is turned off. after testing all the bits, the sar contains a 12C bit binary code which accurately represents the input signal to within 1 M 2 lsb. the internal reference provides the voltage refer- ence to the cdac with excellent stability over temperature and time. the reference is trimmed to 10.00 volts 1% and can supply up to 2ma to an external load in addition to that required to drive the reference input resistor (1ma) and offset resistor (1ma) when operating with 15v supplies. if the spx74b is used with 12v supplies, or if external current must be supplied over the full temperature range, an external buffer amplifier is recommended. any external load on the spx74b reference must remain constant during conversion. features the spx74b series feature standard bipolar and unipolar input ranges of 10v and 20v. input ranges are controlled by a bipolar offset pin and laser-trimmed for specified linearity, gain and offset accuracy. power requirements are +5v and +12v to +15v with a maximum dissipation of 150mw at the specified voltages. conversion times of 8 m s, 10 m s, 15 m s and 25 m s are available, as are units with 10, 25 or 50ppm/ c tempera- ture coefficients for flexible matching to spe- cific application requirements. the spx74b series are available in nine prod- uct grades for each conversion time. the Cj and Ck models are specified over 0?c to + 70?c commercial temperature range; the Ca and Cb models are specified over the C40?c to +85?c industrial temperature range; the Cs and Ct models are specified over the C55?c to +125?c military temperature range. package options include 28Cpin cdip, 28Cpin plastic dip (both narrow and wide), 28-pin plcc and 28Cpin soic. pin assignments pin function pin function 1v logic 28 sts 2 12/8 27 db 11 (msb) 3cs 26 db 10 4a 0 25 db 9 5 r/c 24 db 8 6ce 23 db 7 7v cc 22 db 6 8 ref out 21 db 5 9 ana gnd(ac) 20 db 4 10 ref in 19 db 3 11 n/c* 18 db 2 12 bip off 17 db 1 13 10v in 16 db 0 (lsb) 14 20v in 15 dig. gnd *this pin is not connected inside the device so it can be tied to C15v, ground, or left floating. obsolete - historical reference only
sp574b/674b/1674b/774b 12Cbit sampling a/d converters ? copyright 2000 sipex corporation 6 sampleCandChold function although there is no sampleCandChold circuit in the classical sense, the sampling nature of the capacitive dac makes the spx74b appear to have a builtCin sampleCandChold. the sampleCandC hold function of the cdac architecture is opti- mized to provide full nyquist sampling at any maximum sampling rate. because the s/h func- tion is included in the adc circuitry, the majority of the s/h specifications are included within the a/ d specifications. note that some system architectures may use an external sampleCandChold. the builtCin s/h func- tion of the spx74b will provide additional isola- tion. once the internal sample is taken by the cdac capacitance, the input of the spx74b is disconnected from the input. this prevents tran- sients occurring during conversion from being inflicted upon the attached buffer. all other 574/ 674Ctype circuits will cause a transient load cur- rent on the input which will upset the buffer output and may add error to the conversion itself. in addition, the isolation of the input after the acqui- sition time in the spx74b allows you the opportu- nity to release the hold on an external sampleC andChold and start it tracking the next sample. this will increase system throughput with your existing components. when using an external s/h, the spx74b acts as any other 574Ctype device because the internal s/ h is transparent. the sample/hold function in the spx74b is inherent to the capacitor dac struc- ture, and its timing characteristics are determined by the internally generated clock. however, for multiplexer operation, the internal s/h may elimi- nate the need for an external s/h. the operation of the s/h function is internal to the spx74b and is using the spx74b series typical interface circuit the spx74b is a complete a/d converter that is fully operational when powered up and issued a start convert signal. only a few external compo- nents are necessary. the spx74b series have four standard input ranges: 0v to +10v, 0v to +20v, 5v and 10v. figure 2 depicts a typical interface circuit for operating the spx74b in a unipolar input mode. figure 3 depicts a typical interface circuit for operating the spx74b in a bipolar input mode. further information is given in the follow- ing sections on these connections, but first a few considerations concerning board layout to achieve the best operation. for each application of this device, strict attention must be given to power supply decoupling, board layout (to reduce pickup between analog and digi- tal sections), and grounding. digital timing, cali- bration and the analog signal source must be considered for correct operation. to achieve specified accuracy, a doubleCsided printed circuit board with a copper ground plane on the component side is recommended. keep analog signal traces away from digital lines. it is best to lay the pc board out such that there is an analog section and a digital section with a single point ground connection between the two through an rf bead. if this is not possible, run analog controlled through the normal r/c control line (refer to figure 1 ). when the r/c line makes a negative transition, the spx74b starts the timing of the sampling and conversion. the first two clock cycles are allocated to signal acquisition of the input by the cdac (this time is defined as t acq ). following these two cycles, the input sample is taken and held. the a/d conversion follows this cycle with the duration controlled by the internal clock cycle, which is determined by the specific product model. note that because the sample is taken relative to the r/c transition, t acq is also the traditional aperture delay of this internal sample and hold. since t acq is measured in clock cycles, its duration will vary with the internal clock fre- quency. offset, gain and linearity errors of the s/h circuit, as well as the effects of its droop rate, are included in the overall specs for the spx74b . r/c ce wait for convert signal wait for bus read conversion v in cdac voltage 0 volts t (acq) acquisition time acquisition time = aperture delay time = 0.12 x t convert figure 1. sampleCandChold function obsolete - historical reference only
sp574b/674b/1674b/774b 12Cbit sampling a/d converters ? copyright 2000 sipex corporation 7 2 28 sts dgnd 12/8 cs a 0 r/c ce three?tate buffers and control nibble a nibble b nibble c 27 26 25 24 23 22 21 20 19 18 17 16 output bits msb lsb 3 4 5 6 control logic oscillator 12?its 12?its sample/hold cdac lsb msb offset/gain trim network ref ref amp 1 15 v logic +5v 711 v cc v ee 9 agnd +15v n.c. 8 10 v ref out v ref in r2 100 w r1 100k w 100k w -15v +15v 100 w 10v in 20v in bip off 13 14 12 analog inputs 0 to 10v 0 to 20v 12?it sar comp strobe 10? 0.1? 10? 0.1? + + figure 2. unipolar input connections signals between ground traces and cross digital lines at right angles only. grounding considerations any ground path from the analog and digital ground should be as low resistance as possible to accommodate the ground currents present with this device. the analog ground current is approximately 6ma dc while the digital ground is 3ma dc. the analog and digital common pins should be tied together as close to the package as possible to guarantee best performance. the codeCde- pendent currents flow through the v logic and v cc terminals and not through the analog and digital common pins. power supplies the supply voltages for the spx74b must be kept as quiet as possible from noise pickup and also regulated from transients or drops. because the part has 12Cbit accuracy, voltage spikes on the supply lines can cause several lsb deviations on the output. switching power supply noise can be a problem. careful filtering and shielding should be employed to prevent the noise from being picked up by the converter. capacitor bypass pairs are needed from each sup- ply pin to its respective ground to filter noise and counter the problems caused by the variations in supply current. a 10 m f tantalum and a 0.1 m f ceramic type in parallel between v logic (pin 1) and digital common (pin15), and v cc (pin 7) and analog common (pin 9) is sufficient. v ee is gener- ated internally so pin 11 may be grounded or connected to a negative supply if the spx74b is being used to upgrade an already existing design. calibration and connection procedures unipolar the calibration procedure consists of adjusting the converters most negative output to its ideal value for offset adjustment, and then adjusting the most positive output to its ideal value for gain adjustment. starting with offset adjustment and referring to figure 2 , the midpoint of the first lsb increment should be positioned at the origin to get an output code of all 0s. to do this, an input of + 1 M 2 lsb or +1.22mv for the 10v range and +2.44mv for the 20v range should be applied to the spx74b . adjust the offset potentiometer r 1 for code transi- tion flickers between 0000 0000 0000 and 0000 0000 0001. obsolete - historical reference only
sp574b/674b/1674b/774b 12Cbit sampling a/d converters ? copyright 2000 sipex corporation 8 +9.9927v for the 10v range. adjust the gain potentiometer r 2 for flicker between codes 1111 1110 and 1111 1111 1111. alternative the 100 w potentiometer r 2 provides gain adjust for 10v and 20v ranges. in some applications, a full scale of 10.24v (for and lsb of 2.5mv) or 20.48 (for an lsb of 5.0mv) is more convenient. for these, replace r 2 by a 50 w , 1% metal film resistor. then to provide gain adjust for the 10.24 range, add a 200 w potentiometer in series with pin 13. for the 20.48v range, add a 1000 w potentiom- eter in series with pin 14. the gain adjustment should be done at positive full scale. the ideal input corresponding to the last code change is applied. this is 1 1 M 2 lsb below the nominal full scale which is +9.9963v for the 10v range and +19.9927v for the 20v range. adjust the gain potentiometer r 2 for flicker between codes 1111 1111 1110 and 1111 1111 1111. if calibration is not necessary for the intended appli- cation, replace r 2 with a 50 w , 1% metal film resistor and remove the network analog input to pin 13 for the 0v to 10v range or to pin 14 for the 0v to 20v range. bipolar the gain and offset errors listed in the specifica- tions may be adjusted to zero using the potentiom- eters r 1 and r 2 (see figure 3 ). if adjustment is not needed, either or both pots may be replaced by a 50 w , 1% metal film resistor. to calibrate, connect the analog input signal to pin 13 for a 5v range or to pin 14 for a 10v range. first apply a dc input voltage 1 M 2 lsb above negative full scale which is C4.9988v for the 5v range or C9.9976v for the 10v range. adjust the offset potentiometer r 1 for flicker between output codes 0000 0000 0000 and 0000 0000 0001. next, apply a dc input voltage 1 1 M 2 lsb below positive full scale which is +4.9963v for the 5 range or controlling the spx74b the spx74b can be operated by most micropro- cessor systems due to the control input pins and onCchip logic. it may also be operated in the standCalone mode and enabled by the r/c input pin. full microprocessor control consists of selecting an 8C or 12Cbit conversion cycle, initiating the conversion, and reading the output data when ready. the output read has the options of choosing either 12Cbits at once or 8Cbits fol- lowed by 4Cbits in a leftCjustified format. all five control inputs are ttl/cmos compatible and include 12/8, cs, a 0 , r/c and ce. the use of these inputs in controlling the converters operation is figure 3. bipolar input connections 2 28 sts 12/8 cs a 0 r/c ce three?tate buffers and control nibble a nibble b nibble c 27 26 25 24 23 22 21 20 19 18 17 16 output bits msb lsb 3 4 5 6 control logic oscillator 12?its 12?its sample/hold cdac lsb msb offset/gain trim network ref ref amp 8 10 v ref out v ref in 100 w r1 10v in 20v in bip off 13 14 12 analog inputs 12?it sar comp strobe 100 w r2 ?v ?0v dgnd 1 15 v logic +5v 711 v cc v ee 9 agnd +15v n.c. 10? 0.1? 10? 0.1? + + obsolete - historical reference only
sp574b/674b/1674b/774b 12Cbit sampling a/d converters ? copyright 2000 sipex corporation 9 conversion length a conversion start transition latches the state of a 0 as shown in figure 4 and table 1 . the latched state determines if the conversion stops with 8Cbits (a 0 high) or continues for 12Cbits (a 0 low). if all 12C bits are read following an 8Cbit conversion, the three lsbs will be a logic 0 and db 3 will be a logic 1. a 0 is latched because it is also involved in enabling the output buffers as explained else- where. no other control inputs are latched. standCalone operation the simplest interface is a control line connected to r/c. the other controls must be tied to known states as follows: ce and 12/8 are wired high, a 0 and cs are wired low. the output data arrives in words of 12Cbits each. the limits on r/c duty cycle are shown in figures 8 and 9 . the duty cycle may be within and including the extremes shown in the specifications. in general, data may be read when r/c is high unless sts is also high, indicat- ing a conversion is in progress. reading output data the output data buffers remain in a high imped- ance state until the following four conditions are met: r/c is high, sts is low, ce is high and cs is low. the data lines become active in response to these four conditions, and output data according to the conditions of the control lines 12/8 and a 0 . the timing diagram for this process is shown in figure 7 . when 12/8 is high, all 12 data outputs become active simultaneously and the a 0 input is ignored. the 12/8 input is usually tied high or low; it is ttl/ cmos compatible. when 12/8 is low, the output is separated into two 8Cbit bytes as shown below: byte 1 byte2 xxxx xxxx xxxx 0000 msb lsb this configuration makes it easy to connect to an 8Cbit data bus as shown in figure 5 . the a 0 control can be connected to the least significant bit of the address bus in order to store the output data into two consecutive memory locations. when a 0 is pulled low, the 8 msbs are enabled only. when a 0 is high, the 8 msbs are disabled, bits 4 through 7 are forced to a zero and the four lsbs are enabled. the two byte format is left justified data as shown above and can be considered to have a decimal point or binary to the left of byte 1. shown in table 1 , and the internal control logic is shown in a simplified schematic in figure 4 . conversion start a conversion may be initiated by a logic transition on any of the three inputs: ce, cs r/c, as shown in table 1. the last of the three to reach the correct state starts the conversion, so one, two or all three may be dynamically controlled. the nominal de- lay from each is the same and all three may change state simultaneously. in order to assure that a particular input controls the start of conversion, the other two should be setup at least 50ns earlier. refer to the convert mode timing specifications. the convert start timing diagram is shown in figure 6 . the output signal sts is the status flag and goes high only when a conversion is in progress. while sts is high, the output buffers remain in a high impedance state so that data can not be read. also, when sts is high, an additional start convert will not reset the converter or reinitiate a conversion. note, if a 0 changes state after a conversion begins, an additional start convert command will latch the new state of a 0 and possibly cause a wrong cycle length for that conversion (8Cversus 12Cbits). table 1. spx74b control input truth table ce cs r/c 12/8 a 0 operation 0xxxx none x 1 x x x none 0 0 x 0 initiate 12Cbit conversion 0 0 x 1 initiate 8Cbit conversion 1 0 x 0 initiate 12Cbit conversion 1 0 x 1 initiate 8Cbit conversion 10 x 0 initiate 12Cbit conversion 10 x 1 initiate 8Cbit conversion 1 0 1 1 x enable 12Cbit output 10100 enable 8 msb's only 10101 enable 4 lsb's plus 4 trailing zeroes obsolete - historical reference only
sp574b/674b/1674b/774b 12Cbit sampling a/d converters ? copyright 2000 sipex corporation 10 a 0 may be toggled without damage to the con- verter at any time. breakCbeforeCmake action is guaranteed between the two data bytes. this as- sures that the outputs which are strapped together in figure 5 will never be enabled at the same time. in figure 7 , it can be seen that a read operation usually begins after the conversion is complete and sts is low. if earlier access is needed, the read can begin no later than the addition of times t dd and t hs before sts goes low. "nyquist" sampling each of the spx74b analog-to-digital convert- ers has been designed to provide nyquist sam- pling (highest input frequency is 1/2 of the sampling rate) data conversion with no degra- dation in dc performance. this is shown in figure 10 . note that the differential linearity and integral linearity min/max values are well within the 1/2 lsb limits of a k-version converter. also, the typical fft at nyquist rates shown on figure 10 reflect the values listed in the typical ac dynamics table. sts delay r ck q d h d ck q q eoc8 eoc12 ce r/c a 0 cs 12/8 read control a 0 latch input buffers nibble b zero override nibble a, b nibble c figure 4. spx74b control logic 28 27 26 25 24 23 22 21 20 19 18 17 16 15 sts db11 (msb) db0 (lsb) dig com spx74b 2 4 a 0 address bus a 0 12/8 data bus figure 5. interfacing spx74b to 8?it interface bus obsolete - historical reference only
sp574b/674b/1674b/774b 12Cbit sampling a/d converters ? copyright 2000 sipex corporation 11 ce cs r/c a 0 sts db 11 db 0 high impedance t dsc t c t hac t sac t hrc t hec t src t ssc convert mode timing characteristics typical @ 25?c, v cc = +15v or +10v, v logic = +5v, v ee = 0v, unless otherwise specified. parameter min. typ. max. units conditions t dsc sts delay from ce 200 ns t hec ce pulse width 50 ns t ssc cs to ce setup 50 ns t hsc cs low during ce high 50 ns t src r/c to ce setup 50 ns t hrc r/c low during ce high 50 ns t sac a 0 to ce setup 0 ns t hac a 0 valid during ce high 50 ns t c conversion time 1, 3, 4 see specifications notes: 1. parameters guaranteed by design and sample tested. 2. parameters 100% tested @ 25?c on special orders. 3. 100% tested. 4. t min to t max . figure 6. convert mode timing obsolete - historical reference only
sp574b/674b/1674b/774b 12Cbit sampling a/d converters ? copyright 2000 sipex corporation 12 characteristics typical @ 25?c, v cc = +15v or +12v, v logic = +5v, v ee = 0v, unless otherwise specified. parameter min. typ. max. units conditions t dd access time from ce 2 150 ns t hd data valid after ce low 2 25 ns t hl output float delay 2 150 ns t ssr cs to ce setup 50 0 ns t srr r/c to ce setup 0 0 ns t sar a 0 to ce setup 50 ns t hsr cs valid after ce low 0 0 ns t hrr r/c high after ce low 0 50 ns t har a 0 valid after ce low 50 ns t hs sts delay after data valid 300 1000 ns notes: 1. parameters guaranteed by design and sample tested. 2. parameters 100% tested @ 25?c on special orders. read mode timing ce cs r/c a 0 sts db11 db0 high impedance t ssr t hsr t hrr t srr t sar t har t hd data valid t hl t dd figure 7. read mode timing obsolete - historical reference only
sp574b/674b/1674b/774b 12Cbit sampling a/d converters ? copyright 2000 sipex corporation 13 standCalone mode timing characteristics typical @ 25?c, v cc = +15v or +12v, v logic = +5v, v ee =0v, unless otherwise specified. parameter min. typ . max. units conditions t hrl low r/c pulse width 2 50 ns t ds sts delay from r/c 2 200 ns t hdr data valid after r/c low 2 25 ns t hs sts delay after data valid 2 300 1000 ns t hrh high r/c pulse width 150 ns t ddr data access time 150 ns notes: 1. parameters guaranteed by design and sample tested. 2. parameters 100% tested @ 25?c on special orders. r/c sts db11?b0 t hrl data valid t ds data valid t c t hs t hdr figure 8. low pulse for r/c outputs enabled after conversion figure 9. high pulse for r/c outputs enabled while r/c is high, otherwise high impedance r/c sts db11?b0 data valid t ds t c t hrh high? high? t ddr t hdr obsolete - historical reference only
sp574b/674b/1674b/774b 12Cbit sampling a/d converters ? copyright 2000 sipex corporation 14 figure 10. typical fft at nyquist sampling rates ordering information model monotonicity linearity gain tc temperature range package types 25 m s conversion time sp574bj ............... 11 bits .............................. 1.0 lsb ...................... 50ppm/ c ....................... 0 c to +70 c ................................. l, n, p, s sp574bk .............. 12 bits .............................. 0.5 lsb ...................... 25ppm/ c ....................... 0 c to +70 c ................................. l, n, p, s sp574ba .............. 11 bits .............................. 1.0 lsb ...................... 50ppm/ c ....................... C40 c to +85 c ............................. l, n, p, s sp574bb .............. 12 bits .............................. 0.5 lsb ...................... 25ppm/ c ....................... C40 c to +85 c ............................. l, n, p, s sp574bs .............. 11 bits .............................. 1.0 lsb ...................... 50ppm/ c ....................... C55 c to +125 c ........................................ q sp574bt ............... 12 bits .............................. 0.5 lsb ...................... 25ppm/ c ....................... C55 c to +125 c ........................................ q 15 m s conversion time sp674bj ............... 11 bits .............................. 1.0 lsb ...................... 50ppm/ c ....................... 0 c to +70 c ................................. l, n, p, s sp674bk .............. 12 bits .............................. 0.5 lsb ...................... 25ppm/ c ....................... 0 c to +70 c ................................. l, n, p, s sp674ba .............. 11 bits .............................. 1.0 lsb ...................... 50ppm/ c ....................... C40 c to +85 c ............................. l, n, p, s sp674bb .............. 12 bits .............................. 0.5 lsb ...................... 25ppm/ c ....................... C40 c to +85 c ............................. l, n, p, s sp674bs .............. 11 bits .............................. 1.0 lsb ...................... 50ppm/ c ....................... C55 c to +125 c ........................................ q sp674bt ............... 12 bits .............................. 0.5 lsb ...................... 25ppm/ c ....................... C55 c to +125 c ........................................ q 10 m s conversion time sp1674bj ............. 11 bits .............................. 1.0 lsb ...................... 50ppm/ c ....................... 0 c to +70 c ................................. l, n, p, s sp1674bk ............ 12 bits .............................. 0.5 lsb ...................... 25ppm/ c ....................... 0 c to +70 c ................................. l, n, p, s sp1674ba ............ 11 bits .............................. 1.0 lsb ...................... 50ppm/ c ....................... C40 c to +85 c ............................. l, n, p, s sp1674bb ............ 12 bits .............................. 0.5 lsb ...................... 25ppm/ c ....................... C40 c to +85 c ............................. l, n, p, s sp1674bs ............ 11 bits .............................. 1.0 lsb ...................... 50ppm/ c ....................... C55 c to +125 c ........................................ q sp1674bt ............. 12 bits .............................. 0.5 lsb ...................... 25ppm/ c ....................... C55 c to +125 c ........................................ q 8 m s conversion time sp774bj ............... 11 bits .............................. 1.0 lsb ...................... 50ppm/ c ....................... 0 c to +70 c ................................. l, n, p, s sp774bk .............. 12 bits .............................. 0.5 lsb ...................... 25ppm/ c ....................... 0 c to +70 c ................................. l, n, p, s sp774ba .............. 11 bits .............................. 1.0 lsb ...................... 50ppm/ c ....................... C40 c to +85 c ............................. l, n, p, s sp774bb .............. 12 bits .............................. 0.5 lsb ...................... 25ppm/ c ....................... C40 c to +85 c ............................. l, n, p, s sp774bs .............. 11 bits .............................. 1.0 lsb ...................... 50ppm/ c ....................... C55 c to +125 c ........................................ q sp774bt ............... 12 bits .............................. 0.5 lsb ...................... 25ppm/ c ....................... C55 c to +125 c ........................................ q n 28Cpin, 0.3" wide plastic dip .................. l 28-pin, plcc ....... s 28Cpin, 0.3" soic p 28Cpin, 0.6" wide plastic dip ......................................................... q 28Cpin, 0.6" ceramic dip (consult factory) obsolete - historical reference only
sp574b/674b/1674b/774b 12Cbit sampling a/d converters ? copyright 2000 sipex corporation 15 corporation signal processing excellence sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. sipex corporation headquarters and sales office 22 linnell circle billerica, ma 01821 tel: (978) 667-8700 fax: (978) 670-9001 e-mail: sales@sipex.com sales office 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600 obsolete - historical reference only

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