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2003 pcibus solutions data manual sgls168
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2003, texas instruments incorporated
iii contents section title page 1 introduction 1?1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 description 1 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 features 1 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 related documents 1 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 trademarks 1 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 ordering information 1 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 PCI1520-EP data manual document history 1 ? 3 . . . . . . . . . . . . . . . . . . . . 2 terminal descriptions 2?1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 feature/protocol descriptions 3?1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 power supply sequencing 3 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 i/o characteristics 3 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 clamping voltages 3 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 peripheral component interconnect (pci) interface 3 ? 2 . . . . . . . . . . . . . . 3.4.1 pci grst signal 3 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 pci bus lock (lock )3 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 loading subsystem identification 3 ? 3 . . . . . . . . . . . . . . . . . . . . . 3.5 pc card applications 3 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 pc card insertion/removal and recognition 3 ? 4 . . . . . . . . . . . 3.5.2 p 2 c power-switch interface (tps222x) 3 ? 4 . . . . . . . . . . . . . . . 3.5.3 zoomed video support 3 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.4 standardized zoomed-video register model 3 ? 7 . . . . . . . . . . . 3.5.5 internal ring oscillator 3 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.6 integrated pullup resistors 3 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.7 spkrout and caudpwm usage 3 ? 9 . . . . . . . . . . . . . . . . . . . 3.5.8 led socket activity indicators 3 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . 3.5.9 cardbus socket registers 3 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 serial-bus interface 3 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 serial-bus interface implementation 3 ? 11 . . . . . . . . . . . . . . . . . . . 3.6.2 serial-bus interface protocol 3 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 serial-bus eeprom application 3 ? 13 . . . . . . . . . . . . . . . . . . . . . . 3.6.4 accessing serial-bus devices through software 3 ? 14 . . . . . . . 3.7 programmable interrupt subsystem 3 ? 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.1 pc card functional and card status change interrupts 3 ? 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.2 interrupt masks and flags 3 ? 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.3 using parallel irq interrupts 3 ? 17 . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.4 using parallel pci interrupts 3 ? 18 . . . . . . . . . . . . . . . . . . . . . . . . .
iv 3.7.5 using serialized irqser interrupts 3 ? 18 . . . . . . . . . . . . . . . . . . . 3.7.6 smi support in the pci1520 3 ? 18 . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 power management overview 3 ? 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 integrated low-dropout voltage regulator (ldo-vr) 3 ? 19 . . . . 3.8.2 clock run protocol 3 ? 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.3 cardbus pc card power management 3 ? 20 . . . . . . . . . . . . . . . . 3.8.4 16-bit pc card power management 3 ? 20 . . . . . . . . . . . . . . . . . . . 3.8.5 suspend mode 3 ? 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.6 requirements for suspend mode 3 ? 21 . . . . . . . . . . . . . . . . . . . . . 3.8.7 ring indicate 3 ? 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.8 pci power management 3 ? 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.9 cardbus bridge power management 3 ? 23 . . . . . . . . . . . . . . . . . . 3.8.10 acpi support 3 ? 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.11 master list of pme context bits and global reset-only bits 3 ? 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pc card controller programming model 4 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 pci configuration registers (functions 0 and 1) 4 ? 1 . . . . . . . . . . . . . . . . . 4.2 vendor id register 4 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 device id register 4 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 command register 4 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 status register 4 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 revision id register 4 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 pci class code register 4 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 cache line size register 4 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 latency timer register 4 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 header type register 4 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 bist register 4 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 cardbus socket/exca base-address register 4 ? 7 . . . . . . . . . . . . . . . . . . 4.13 capability pointer register 4 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 secondary status register 4 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.15 pci bus number register 4 ? 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16 cardbus bus number register 4 ? 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17 subordinate bus number register 4 ? 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.18 cardbus latency timer register 4 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19 memory base registers 0, 1 4 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.20 memory limit registers 0, 1 4 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.21 i/o base registers 0, 1 4 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.22 i/o limit registers 0, 1 4 ? 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23 interrupt line register 4 ? 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.24 interrupt pin register 4 ? 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.25 bridge control register 4 ? 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.26 subsystem vendor id register 4 ? 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.27 subsystem id register 4 ? 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.28 pc card 16-bit i/f legacy-mode base address register 4 ? 15 . . . . . . . . .
v 4.29 system control register 4 ? 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.30 multifunction routing register 4 ? 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.31 retry status register 4 ? 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.32 card control register 4 ? 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.33 device control register 4 ? 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.34 diagnostic register 4 ? 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.35 capability id register 4 ? 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.36 next-item pointer register 4 ? 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.37 power-management capabilities register 4 ? 26 . . . . . . . . . . . . . . . . . . . . . . 4.38 power-management control/status register 4 ? 27 . . . . . . . . . . . . . . . . . . . . 4.39 power-management control/status register bridge support extensions 4 ? 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.40 power-management data register 4 ? 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.41 general-purpose event status register 4 ? 29 . . . . . . . . . . . . . . . . . . . . . . . . 4.42 general-purpose event enable register 4 ? 30 . . . . . . . . . . . . . . . . . . . . . . . 4.43 general-purpose input register 4 ? 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.44 general-purpose output register 4 ? 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.45 serial-bus data register 4 ? 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.46 serial-bus index register 4 ? 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.47 serial-bus slave address register 4 ? 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.48 serial-bus control and status register 4 ? 34 . . . . . . . . . . . . . . . . . . . . . . . . . 5 exca compatibility registers (functions 0 and 1) 5 ? 1 . . . . . . . . . . . . . . . . . . 5.1 exca identification and revision register 5 ? 5 . . . . . . . . . . . . . . . . . . . . . . 5.2 exca interface status register 5 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 exca power control register 5 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 exca interrupt and general control register 5 ? 8 . . . . . . . . . . . . . . . . . . . 5.5 exca card status-change register 5 ? 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 exca card status-change interrupt configuration register 5 ? 10 . . . . . . . 5.7 exca address window enable register 5 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . 5.8 exca i/o window control register 5 ? 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 exca i/o windows 0 and 1 start-address low-byte registers 5 ? 13 . . . . 5.10 exca i/o windows 0 and 1 start-address high-byte registers 5 ? 13 . . . . 5.11 exca i/o windows 0 and 1 end-address low-byte registers 5 ? 14 . . . . . 5.12 exca i/o windows 0 and 1 end-address high-byte registers 5 ? 14 . . . . 5.13 exca memory windows 0 ? 4 start-address low-byte registers 5 ? 15 . . . 5.14 exca memory windows 0 ? 4 start-address high-byte registers 5 ? 16 . . . 5.15 exca memory windows 0 ? 4 end-address low-byte registers 5 ? 17 . . . . 5.16 exca memory windows 0 ? 4 end-address high-byte registers 5 ? 18 . . . 5.17 exca memory windows 0 ? 4 offset-address low-byte registers 5 ? 19 . . 5.18 exca memory windows 0 ? 4 offset-address high-byte registers 5 ? 20 . 5.19 exca card detect and general control register 5 ? 21 . . . . . . . . . . . . . . . . 5.20 exca global control register 5 ? 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.21 exca i/o windows 0 and 1 offset-address low-byte registers 5 ? 23 . . . 5.22 exca i/o windows 0 and 1 offset-address high-byte registers 5 ? 23 . . .
vi 5.23 exca memory windows 0 ? 4 page registers 5 ? 24 . . . . . . . . . . . . . . . . . . . 6 cardbus socket registers (functions 0 and 1) 6 ? 1 . . . . . . . . . . . . . . . . . . . . . . 6.1 socket event register 6 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 socket mask register 6 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 socket present-state register 6 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 socket force event register 6 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 socket control register 6 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 socket power-management register 6 ? 9 . . . . . . . . . . . . . . . . . . . . . . . . . . 7 electrical characteristics 7 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 absolute maximum ratings over operating temperature ranges 7 ? 1 . 7.2 recommended operating conditions 7 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 electrical characteristics over recommended operating conditions 7 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 pci clock/reset timing requirements over recommended ranges of supply voltage and operating free-air temperature 7 ? 3 . . . 7.5 pci timing requirements over recommended ranges of supply voltage and operating free-air temperature 7 ? 4 . . . . . . . . . . . . . 8 mechanical information 8 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii list of illustrations figure title page 2 ? 1 pci1520 ghk-package terminal diagram 2 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 1 pci1520 simplified block diagram 3 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 2 3-state bidirectional buffer 3 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 3 tps222x typical application 3 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 4 zoomed video implementation using the pci1520 3 ? 6 . . . . . . . . . . . . . . . . . . . . 3 ? 5 zoomed video switching application 3 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 6 sample application of spkrout and caudpwm 3 ? 10 . . . . . . . . . . . . . . . . . . . . 3 ? 7 two sample led circuits 3 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 8 serial eeprom application 3 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 9 serial-bus start/stop conditions and bit transfers 3 ? 12 . . . . . . . . . . . . . . . . . . . . 3 ? 10 serial-bus protocol acknowledge 3 ? 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 11 serial-bus protocol ? byte write 3 ? 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 12 serial-bus protocol ? byte read 3 ? 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 13 eeprom interface doubleword data collection 3 ? 13 . . . . . . . . . . . . . . . . . . . . . 3 ? 14 irq implementation 3 ? 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 15 signal diagram of suspend function 3 ? 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 16 ri_out functional diagram 3 ? 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 17 block diagram of a status/enable cell 3 ? 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 1 exca register access through i/o 5 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 2 exca register access through memory 5 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 1 accessing cardbus socket registers through pci memory 6 ? 1 . . . . . . . . . . . .
viii list of tables table title page 2 ? 1 signal names by ghk terminal number 2 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 2 cardbus pc card signal names sorted alphabetically 2 ? 4 . . . . . . . . . . . . . . . . 2 ? 3 16-bit pc card signal names sorted alphabetically 2 ? 9 . . . . . . . . . . . . . . . . . . . 2 ? 4 power supply terminals 2 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 5 pc card power switch terminals 2 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 6 pci system terminals 2 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 7 pci address and data terminals 2 ? 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 8 pci interface control terminals 2 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 9 multifunction and miscellaneous terminals 2 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 10 16-bit pc card address and data terminals (slots a and b) 2 ? 12 . . . . . . . . . . 2 ? 11 16-bit pc card interface control terminals (slots a and b) 2 ? 13 . . . . . . . . . . . . 2 ? 12 cardbus pc card interface system terminals (slots a and b) 2 ? 14 . . . . . . . . . 2 ? 13 cardbus pc card address and data terminals (slots a and b) 2 ? 15 . . . . . . . . 2 ? 14 cardbus pc card interface control terminals (slots a and b) 2 ? 16 . . . . . . . . . 3 ? 1 pc card card-detect and voltage-sense connections 3 ? 4 . . . . . . . . . . . . . . . . 3 ? 2 power switch options 3 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 3 functionality of the zv output signals 3 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 4 zoomed-video card interrogation 3 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 5 integrated pullup resistors 3 ? 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 6 cardbus socket registers 3 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 7 register- and bit-loading map 3 ? 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 8 pci1520 registers used to program serial-bus devices 3 ? 15 . . . . . . . . . . . . . . . 3 ? 9 interrupt mask and flag registers 3 ? 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 10 pc card interrupt events and description 3 ? 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 11 interrupt pin register cross reference 3 ? 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 12 smi control 3 ? 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 13 requirements for internal/external 2.5-v core power supply 3 ? 19 . . . . . . . . . . 3 ? 14 power-management registers 3 ? 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 1 pci configuration registers (functions 0 and 1) 4 ? 1 . . . . . . . . . . . . . . . . . . . . . . 4 ? 2 bit field access tag descriptions 4 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 3 command register description 4 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 4 status register description 4 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 5 secondary status register description 4 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 6 interrupt pin register cross reference 4 ? 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 7 bridge control register description 4 ? 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 8 system control register description 4 ? 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 9 multifunction routing register description 4 ? 19 . . . . . . . . . . . . . . . . . . . . . . . . . . .
ix 4 ? 10 retry status register description 4 ? 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 11 card control register description 4 ? 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 12 device control register description 4 ? 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 13 diagnostic register description 4 ? 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 14 power-management capabilities register description 4 ? 26 . . . . . . . . . . . . . . . . 4 ? 15 power-management control/status register description 4 ? 27 . . . . . . . . . . . . . . 4 ? 16 power-management control/status register bridge support extensions description 4 ? 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 17 general-purpose event status register description 4 ? 29 . . . . . . . . . . . . . . . . . . 4 ? 18 general-purpose event enable register description 4 ? 30 . . . . . . . . . . . . . . . . . 4 ? 19 general-purpose input register description 4 ? 31 . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 20 general-purpose output register description 4 ? 32 . . . . . . . . . . . . . . . . . . . . . . . 4 ? 21 serial-bus data register description 4 ? 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 22 serial-bus index register description 4 ? 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 23 serial-bus slave address register description 4 ? 33 . . . . . . . . . . . . . . . . . . . . . . 4 ? 24 serial-bus control and status register description 4 ? 34 . . . . . . . . . . . . . . . . . . . 5 ? 1 exca registers and offsets 5 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 2 exca identification and revision register description 5 ? 5 . . . . . . . . . . . . . . . . . 5 ? 3 exca interface status register description 5 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 4 exca power control register description ? 82365sl support 5 ? 7 . . . . . . . . . . 5 ? 5 exca power control register description ? 82365sl-df support 5 ? 7 . . . . . . . 5 ? 6 exca interrupt and general control register description 5 ? 8 . . . . . . . . . . . . . . 5 ? 7 exca card status-change register description 5 ? 9 . . . . . . . . . . . . . . . . . . . . . . 5 ? 8 exca card status-change interrupt configuration register description 5 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 9 exca address window enable register description 5 ? 11 . . . . . . . . . . . . . . . . . . . 5 ? 10 exca i/o window control register description 5 ? 12 . . . . . . . . . . . . . . . . . . . . . . 5 ? 11 exca memory windows 0 ? 4 start-address high-byte registers description 5 ? 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 12 exca memory windows 0 ? 4 end-address high-byte registers description 5 ? 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 13 exca memory windows 0 ? 4 offset-address high-byte registers description 5 ? 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 14 exca card detect and general control register description 5 ? 21 . . . . . . . . . . 5 ? 15 exca global control register description 5 ? 22 . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 1 cardbus socket registers 6 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 2 socket event register description 6 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 3 socket mask register description 6 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 4 socket present-state register description 6 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 5 socket force event register description 6 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 6 socket control register description 6 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 7 socket power-management register description 6 ? 9 . . . . . . . . . . . . . . . . . . . . .
1 ? 1 1 introduction 1.1 description the texas instruments pci1520, a 208-terminal dual-slot cardbus controller designed to meet the pci bus power management interface specification for pci to cardbus bridges , is an ultralow-power high-performance pci-to-cardbus controller that supports two independent card sockets compliant with the pc card standard (rev. 7.1). the pci1520 provides features that make it the best choice for bridging between pci and pc cards in both notebook and desktop computers. the 1997 pc card standard retains the 16-bit pc card specification defined in pci local bus specification and defines the new 32-bit pc card, cardbus, capable of full 32-bit data transfers at 33 mhz. the pci1520 supports any combination of 16-bit and cardbus pc cards in the two sockets, powered at 5 v or 3.3 v, as required. the pci1520 is compliant with the pci local bus specification , and its pci interface can act as either a pci master device or a pci slave device. the pci bus mastering is initiated during cardbus pc card bridging transactions. the pci1520 is also compliant with pci bus power management interface specification (rev. 1.1). all card signals are internally buffered to allow hot insertion and removal without external buffering. the pci1520 is register-compatible with the intel 82365sl-df and 82365sl exca controllers. the pci1520 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit pci cycles for maximum performance. independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. the pci1520 can also be programmed to accept fast posted writes to improve system-bus utilization. multiple system-interrupt signaling options are provided, including parallel pci, parallel isa, serialized isa, and serialized pci. furthermore, general-purpose inputs and outputs are provided for the board designer to implement sideband functions. many other features designed into the pci1520, such as socket activity light-emitting diode (led) outputs, are discussed in detail throughout the design specification. an advanced complementary metal-oxide semiconductor (cmos) process achieves low system power consumption while operating at pci clock rates up to 33 mhz. several low-power modes enable the host power management system to further reduce power consumption. 1.2 features the PCI1520-EP supports the following features: ? controlled baseline ? one assembly/test site, one fabrication site ? extended temperature performance of ? 40 c to 85 c ? enhanced diminishing manufacturing sources (dms) support ? enhanced product-change notification ? qualification pedigree ? ? a 209-terminal microstar bga ? ball-grid array (ghk) package ? 2.5-v core logic and 3.3-v i/o with universal pci interfaces compatible with 3.3-v and 5-v pci signaling environments ? integrated low-dropout voltage regulator (ldo-vr) eliminates the need for an external 2.5-v power supply ? component qualification in accordance with jedec and industry standards to ensure reliable operation over an extended temperatu re range. this includes, but is not limited to, highly accelerated stress test (hast) or biased 85/85, temperature cycle, autoclave or un biased hast, electromigration, bond intermetallic life, and mold compound life. such qualification testing should not be viewed as justifyin g use of this component beyond specified performance and environmental limits.
1 ? 2 ? mix-and-match 5-v/3.3-v 16-bit pc cards and 3.3-v cardbus cards ? two pc card or cardbus slots with hot insertion and removal ? serial interface to ti ? tps222x dual-slot pc card power switch ? burst transfers to maximize data throughput with cardbus cards ? interrupt configurations: parallel pci, serialized pci, parallel isa, and serialized isa ? serial eeprom interface for loading subsystem id and subsystem vendor id ? pipelined architecture for greater than 130-mbps throughput from cardbus-to-pci and from pci-to-cardbus ? up to five general-purpose i/os ? programmable output select for clkrun ? multifunction pci device with separate configuration space for each socket ? five pci memory windows and two i/o windows available for each 16-bit interface ? two i/o windows and two memory windows available to each cardbus socket ? exchangeable-card-architecture- (exca-) compatible registers are mapped in memory and i/o space ? intel ? 82365sl-df and 82365sl register compatible ? ring indicate, suspend , pci clkrun, and cardbus cclkrun ? socket activity led terminals ? pci bus lock (lock ) ? advanced quarter-micron, ultralow-power cmos technology ? internal ring oscillator 1.3 related documents ? advanced configuration and power interface (acpi) specification (revision 1.1) ? pci bus power management interface specification (revision 1.1) ? pci bus power management interface specification for pci to cardbus bridges (revision 0.6) ? pci to pcmcia cardbus bridge register description (yenta) (revision 2.1) ? pci local bus specification (revision 2.2) ? pci mobile design guide (revision 1.0) ? pc card standard (revision 7.1) ? pc 2001 ? serialized irq support for pci systems (revision 6) 1.4 trademarks intel is a trademark of intel corporation. ti and microstar bga are trademarks of texas instruments. other trademarks are the property of their respective owners. 1.5 ordering information temperature package ordering number top-side marking ? 40 c to 85 c 209-ball pbga pci1520ighkep pci1520iep
1 ? 3 1.6 PCI1520-EP data manual document history date page number revision 05/2003 original draft
2 ? 1 2 terminal descriptions the pci1520 is available in a 209-terminal microstar bga ? package (ghk). the terminal layout for the ghk package is shown in figure 2 ? 1. ghk plastic ball grid array (pbga) package bottom view 19 17 16 13 14 15 11 12 9 810 v u w r n p l m k t 7 56 34 h f g e c d 1 a b 2 j 18 figure 2 ? 1. pci1520 ghk-package terminal diagram table 2 ? 1 lists the terminal assignments arranged in terminal-number order, with corresponding signal names for both cardbus and 16-bit pc cards; table 2 ? 1 is for terminals on the ghk package. table 2 ? 2 and table 2 ? 3 list the terminal assignments arranged in alphanumerical order by signal name, with corresponding terminal numbers for ghk package; table 2 ? 2 is for cardbus signal names and table 2 ? 3 is for 16-bit pc card signal names. terminal e5 on the ghk package is an identification ball used for device orientation; it has no internal connection within the device.
2 ? 2 table 2 ? 1. signal names by ghk terminal number term signal name term signal name term signal name term. no. cardbus pc card 16-bit pc card term. no. cardbus pc card 16-bit pc card term. no. cardbus pc card 16-bit pc card a04 ad12 ad12 e07 perr perr h06 ad2 ad2 a05 par par e08 frame frame h14 a_cstschg a_bvd1(stschg /ri ) a06 gnd gnd e09 ad19 ad19 h15 a_cclkrun a_wp(iois16 ) a07 v cc v cc e10 idsel idsel h17 a_caudio a_bvd2(spkr ) a08 ad18 ad18 e11 ad27 ad27 h18 a_cserr a_wait a09 gnd gnd e12 ad31 ad31 h19 a_cint a_ready(ireq ) a10 v ccp v ccp e13 ri_out /pme ri_out /pme j01 b_cad4 b_d12 a11 ad29 ad29 e14 mfunc2 mfunc2 j02 b_cad3 b_d5 a12 v cc v cc e17 data data j03 b_cad6 b_d13 a13 req req e18 latch latch j05 b_cad5 b_d6 a14 gnd gnd e19 a_cad31 a_d10 j06 b_rsvd b_d14 a15 mfunc5 mfunc5 f01 ad3 ad3 j14 a_cad26 a_a0 a16 mfunc1 mfunc1 f02 ad5 ad5 j15 a_cvs1 a_vs1 b05 ad15 ad15 f03 ad6 ad6 j17 a_cad25 a_a1 b06 stop stop f05 ad8 ad8 j18 a_cad24 a_a2 b07 irdy irdy f06 c/be1 c/be1 j19 v cc v cc b08 ad17 ad17 f07 devsel devsel k01 gnd gnd b09 ad22 ad22 f08 c/be2 c/be2 k02 b_cad7 b_d7 b10 ad24 ad24 f09 ad20 ad20 k03 b_cad8 b_d15 b11 ad28 ad28 f10 ad23 ad23 k05 b_cc/be0 b_ce1 b12 ad11 ad11 f11 ad26 ad26 k06 b_cad9 b_a10 b13 gnt gnt f12 ad25 ad25 k14 a_cc/be3 a_reg b14 c/be3 c/be3 f13 mfunc3/irqser mfunc3/irqser k15 a_cad23 a_a3 b15 mfunc4 mfunc4 f14 spkrout spkrout k17 a_creq a_inpack c05 ad13 ad13 f15 clock clock k18 a_cad22 a_a4 c06 serr serr f17 a_rsvd a_d2 k19 vr_port vr_port c07 trdy trdy f18 a_cad29 a_d1 l01 vr_en vr_en c08 ad16 ad16 f19 gnd gnd l02 b_cad10 b_ce2 c09 ad21 ad21 g01 v cc v cc l03 b_cad11 b_oe c10 pclk pclk g02 ad0 ad0 l05 b_cad13 b_iord c11 grst grst g03 ad1 ad1 l06 b_cad12 b_a11 c12 ad30 ad30 g05 ad4 ad4 l14 a_cad21 a_a5 c13 prst prst g06 c/be0 c/be0 l15 a_crst a_reset c14 mfunc6/ clkrun mfunc6/ clkrun g14 a_cad28 a_d8 l17 a_cad20 a_a6 c15 suspend suspend g15 a_cad30 a_d9 l18 a_cvs2 a_vs2 d01 ad10 ad10 g17 a_cad27 a_d0 l19 a_cad19 a_a25 d19 mfunc0 mfunc0 g18 a_ccd2 a_cd2 m01 b_cad15 b_iowr e01 gnd gnd g19 v cc v cc m02 b_cad14 b_a9 e02 ad7 ad7 h01 b_cad1 b_d4 m03 b_cad16 b_a17 e03 ad9 ad9 h02 b_cad2 b_d11 m05 b_rsvd b_a18 e05 nc nc h03 b_cad0 b_d3 m06 b_cc/be1 b_a8 e06 ad14 ad14 h05 b_ccd1 b_cd1 m14 a_cclk a_a16
2 ? 3 table 2 ? 1. signal names by ghk terminal number (continued) term signal name term signal name term signal name term. no. cardbus pc card 16-bit pc card term. no. cardbus pc card 16-bit pc card term. no. cardbus pc card 16-bit pc card m15 a_cframe a_a23 p17 a_cstop a_a20 u13 a_cad7 a_d7 m17 a_cc/be2 a_a12 p18 a_cgnt a_we u14 a_cad10 a_ce2 m18 a_cad17 a_a24 p19 v cca v cca u15 a_cad14 a_a9 m19 a_cad18 a_a7 r01 v ccb v ccb v05 b_cad20 b_a6 n01 v cc v cc r02 b_ctrdy b_a22 v06 b_cad22 b_a4 n02 b_cpar b_a13 r03 b_cframe b_a23 v07 b_cad24 b_a2 n03 b_cblock b_a19 r06 b_cad19 b_a25 v08 b_cint b_ready(ireq ) n05 b_cgnt b_we r07 b_creq b_inpack v09 b_caudio b_bvd2(spkr ) n06 b_cperr b_a14 r08 b_cad26 b_a0 v10 b_cad28 b_d8 n14 a_cblock a_a19 r09 b_cclkrun b_wp(iois16 ) v11 b_cad31 b_d10 n15 a_cdevsel a_a21 r10 b_cad30 b_d9 v12 a_cad4 a_d12 n17 a_ctrdy a_a22 r11 a_cad2 a_d11 v13 a_rsvd a_d14 n18 a_cirdy a_a15 r12 a_cad5 a_d6 v14 a_cc/be0 a_ce1 n19 v cc v cc r13 a_cad9 a_a10 v15 a_cad13 a_iord p01 gnd gnd r14 a_cad15 a_iowr w04 b_cad17 b_a24 p02 b_cstop b_a20 r17 a_rsvd a_a18 w05 b_crst b_reset p03 b_cdevsel b_a21 r18 a_cperr a_a14 w06 gnd gnd p05 b_cirdy b_a15 r19 gnd gnd w07 b_cad25 b_a1 p06 b_cclk b_a16 t01 b_cc/be2 b_a12 w08 v cc v cc p07 b_cvs2 b_vs2 t19 a_cc/be1 a_a8 w09 b_cserr b_wait p08 b_cad23 b_a3 u05 b_cad18 b_a7 w10 b_cad27 b_d0 p09 b_ccd2 b_cd2 u06 b_cad21 b_a5 w11 nc ? nc ? p10 b_rsvd b_d2 u07 b_cc/be3 b_reg w12 a_cad1 a_d4 p11 a_cad0 a_d3 u08 b_cvs1 b_vs1 w13 v cc v cc p12 a_cad6 a_d13 u09 b_cstschg b_bvd1(stschg /ri ) w14 gnd gnd p13 a_cad8 a_d15 u10 b_cad29 b_d1 w15 a_cad11 a_oe p14 a_cad12 a_a11 u11 a_ccd1 a_cd1 w16 a_cad16 a_a17 p15 a_cpar a_a13 u12 a_cad3 a_d5 ? terminal w11 is an nc on the pci1520 to allow for terminal compatibility with the next generation of devices.
2 ? 4 table 2 ? 2. cardbus pc card signal names sorted alphabetically signal name term no. signal name term. no. signal name term. no. signal name ghk signal name ghk signal name ghk a_cad0 p11 a_cdevsel n15 ad24 b10 a_cad1 w12 a_cframe m15 ad25 f12 a_cad2 r11 a_cgnt p18 ad26 f11 a_cad3 u12 a_cint h19 ad27 e11 a_cad4 v12 a_cirdy n18 ad28 b11 a_cad5 r12 a_cpar p15 ad29 a11 a_cad6 p12 a_cperr r18 ad30 c12 a_cad7 u13 a_creq k17 ad31 e12 a_cad8 p13 a_crst l15 b_cad0 h03 a_cad9 r13 a_cserr h18 b_cad1 h01 a_cad10 u14 a_cstop p17 b_cad2 h02 a_cad11 w15 a_cstschg h14 b_cad3 j02 a_cad12 p14 a_ctrdy n17 b_cad4 j01 a_cad13 v15 a_cvs1 j15 b_cad5 j05 a_cad14 u15 a_cvs2 l18 b_cad6 j03 a_cad15 r14 a_rsvd r17 b_cad7 k02 a_cad16 w16 a_rsvd v13 b_cad8 k03 a_cad17 m18 a_rsvd f17 b_cad9 k06 a_cad18 m19 ad0 g02 b_cad10 l02 a_cad19 l19 ad1 g03 b_cad11 l03 a_cad20 l17 ad2 h06 b_cad12 l06 a_cad21 l14 ad3 f01 b_cad13 l05 a_cad22 k18 ad4 g05 b_cad14 m02 a_cad23 k15 ad5 f02 b_cad15 m01 a_cad24 j18 ad6 f03 b_cad16 m03 a_cad25 j17 ad7 e02 b_cad17 w04 a_cad26 j14 ad8 f05 b_cad18 u05 a_cad27 g17 ad9 e03 b_cad19 r06 a_cad28 g14 ad10 d01 b_cad20 v05 a_cad29 f18 ad11 b12 b_cad21 u06 a_cad30 g15 ad12 a04 b_cad22 v06 a_cad31 e19 ad13 c05 b_cad23 p08 a_caudio h17 ad14 e06 b_cad24 v07 a_cblock n14 ad15 b05 b_cad25 w07 a_cc/be0 v14 ad16 c08 b_cad26 r08 a_cc/be1 t19 ad17 b08 b_cad27 w10 a_cc/be2 m17 ad18 a08 b_cad28 v10 a_cc/be3 k14 ad19 e09 b_cad29 u10 a_ccd1 u11 ad20 f09 b_cad30 r10 a_ccd2 g18 ad21 c09 b_cad31 v11 a_cclk m14 ad22 b09 b_caudio v09 a_cclkrun h15 ad23 f10 b_cblock n03
2 ? 5 table 2 ? 2. cardbus pc card signal names sorted alphabetically (continued) signal name term no. signal name term no. signal name term no. signal name ghk signal name ghk signal name ghk b_cc/be0 k05 c/be2 f08 nc e05 b_cc/be1 m06 c/be3 b14 nc ? w11 b_cc/be2 t01 clock f15 par a05 b_cc/be3 u07 data e17 pclk c10 b_ccd1 h05 devsel f07 perr e07 b_ccd2 p09 frame e08 prst c13 b_cclk p06 gnd a06 req a13 b_cclkrun r09 gnd a09 ri_out /pme e13 b_cdevsel p03 gnd a14 serr c06 b_cframe r03 gnd e01 spkrout f14 b_cgnt n05 gnd k01 stop b06 b_cint v08 gnd p01 suspend c15 b_cirdy p05 gnd r19 trdy c07 b_cpar n02 gnd w06 v cc a07 b_cperr n06 gnd f19 v cc a12 b_creq r07 gnd w14 v cc g01 b_crst w05 gnt b13 v cc g19 b_cserr w09 grst c11 v cc j19 b_cstop p02 idsel e10 v cc n01 b_cstschg u09 irdy b07 v cc n19 b_ctrdy r02 latch e18 v cc w08 b_cvs1 u08 mfunc0 d19 v cc w13 b_cvs2 p07 mfunc1 a16 v cca p19 b_rsvd j06 mfunc2 e14 v ccb r01 b_rsvd m05 mfunc3/irqser f13 v ccp a10 b_rsvd p10 mfunc4 b15 vr_en l01 c/be0 g06 mfunc5 a15 vr_port k19 c/be1 f06 mfunc6/clkrun c14 ? terminals 81 and w11 are nc on the pci1520 to allow for terminal compatibility with the next generation of devices.
2 ? 6 table 2 ? 3. 16-bit pc card signal names sorted alphabetically signal name term. no. signal name term. no. signal name term no. signal name ghk signal name ghk signal name ghk a_a0 j14 a_d10 e19 ad24 b10 a_a1 j17 a_d11 r11 ad25 f12 a_a2 j18 a_d12 v12 ad26 f11 a_a3 k15 a_d13 p12 ad27 e11 a_a4 k18 a_d14 v13 ad28 b11 a_a5 l14 a_d15 p13 ad29 a11 a_a6 l17 a_inpack k17 ad30 c12 a_a7 m19 a_iord v15 ad31 e12 a_a8 t19 a_iowr r14 b_a0 r08 a_a9 u15 a_oe w15 b_a1 w07 a_a10 r13 a_ready(ireq ) h19 b_a2 v07 a_a11 p14 a_reg k14 b_a3 p08 a_a12 m17 a_reset l15 b_a4 v06 a_a13 p15 a_vs1 j15 b_a5 u06 a_a14 r18 a_vs2 l18 b_a6 v05 a_a15 n18 a_wait h18 b_a7 u05 a_a16 m14 a_we p18 b_a8 m06 a_a17 w16 a_wp(iois16 ) h15 b_a9 m02 a_a18 r17 ad0 g02 b_a10 k06 a_a19 n14 ad1 g03 b_a11 l06 a_a20 p17 ad2 h06 b_a12 t01 a_a21 n15 ad3 f01 b_a13 n02 a_a22 n17 ad4 g05 b_a14 n06 a_a23 m15 ad5 f02 b_a15 p05 a_a24 m18 ad6 f03 b_a16 p06 a_a25 l19 ad7 e02 b_a17 m03 a_bvd1(stschg /ri ) h14 ad8 f05 b_a18 m05 a_bvd2(spkr ) h17 ad9 e03 b_a19 n03 a_cd1 u11 ad10 d01 b_a20 p02 a_cd2 g18 ad11 b12 b_a21 p03 a_ce1 v14 ad12 a04 b_a22 r02 a_ce2 u14 ad13 c05 b_a23 r03 a_d0 g17 ad14 e06 b_a24 w04 a_d1 f18 ad15 b05 b_a25 r06 a_d2 f17 ad16 c08 b_bvd1(stschg /ri ) u09 a_d3 p11 ad17 b08 b_bvd2(spkr ) v09 a_d4 w12 ad18 a08 b_cd1 h05 a_d5 u12 ad19 e09 b_cd2 p09 a_d6 r12 ad20 f09 b_ce1 k05 a_d7 u13 ad21 c09 b_ce2 l02 a_d8 g14 ad22 b09 b_d0 w10 a_d9 g15 ad23 f10 b_d1 u10
2 ? 7 table 2 ? 3. 16-bit pc card signal names sorted alphabetically (continued) signal name term no. signal name term no. signal name term no. signal name ghk signal name ghk signal name ghk b_d2 p10 c/be2 f08 nc e05 b_d3 h03 c/be3 b14 nc ? w11 b_d4 h01 clock f15 par a05 b_d5 j02 data e17 pclk c10 b_d6 j05 devsel f07 perr e07 b_d7 k02 frame e08 prst c13 b_d8 v10 gnd a06 req a13 b_d9 r10 gnd a09 ri_out /pme e13 b_d10 v11 gnd a14 serr c06 b_d11 h02 gnd e01 spkrout f14 b_d12 j01 gnd k01 stop b06 b_d13 j03 gnd p01 suspend c15 b_d14 j06 gnd r19 trdy c07 b_d15 k03 gnd w06 v cc a07 b_inpack r07 gnd f19 v cc a12 b_iord l05 gnd w14 v cc g01 b_iowr m01 gnt b13 v cc g19 b_oe l03 grst c11 v cc j19 b_ready(ireq ) v08 idsel e10 v cc n01 b_reg u07 irdy b07 v cc n19 b_reset w05 latch e18 v cc w08 b_vs1 u08 mfunc0 d19 v cc w13 b_vs2 p07 mfunc1 a16 v cca p19 b_wait w09 mfunc2 e14 v ccb r01 b_we n05 mfunc3/irqser f13 v ccp a10 b_wp(iois16 ) r09 mfunc4 b15 vr_en l01 c/be0 g06 mfunc5 a15 vr_port k19 c/be1 f06 mfunc6/clkrun c14 ? terminals 81 and w11 are nc on the pci1520 to allow for terminal compatibility with the next generation of devices.
2 ? 8 the terminals are grouped in tables by functionality, such as pci system function, power-supply function, etc. the terminal numbers are also listed for convenient reference. table 2 ? 4. power supply terminals terminal name no. i/o description name ghk i/o description gnd a06, a09, a14, e01, f19, k01, p01, r19, w06, w14 ? device ground terminals v cc a07, a12, g01, g19, j19, n01, n19, w08, w13 ? power supply terminal for i/o and internal voltage regulator v cca p19 ? clamp voltage for pc card a interface. matches card a signaling environment, 5 v or 3.3 v v ccb r01 ? clamp voltage for pc card b interface. matches card b signaling environment, 5 v or 3.3 v v ccp a10 ? clamp voltage for pci and miscellaneous i/o, 5 v or 3.3 v vr_en l01 i internal voltage regulator enable. active-low vr_port k19 i/o internal voltage regulator input/output. when vr_en is low, the regulator is enabled and this terminal is an output. an external bypass capacitor is required on this terminal. when vr_en is high, the regu- lator is disabled and this terminal is an input for an external 2.5-v core power source. table 2 ? 5. pc card power switch terminals terminal name no. i/o description name ghk i/o description clock f15 i/o power switch clock. information on the data line is sampled at the rising edge of clock. clock defaults to an input, but can be changed to a pci1520 output by using bit 27 (p2cclk) in the system control register (offset 80h, see section 4.29). the tps222x defines the maximum frequency of this signal to be 2 mhz. however, pci1520 requires a 16-khz to 100-khz frequency range. if a system design defines this terminal as an output, then this terminal requires an external pulldown resistor. the frequency of the pci1520 output clock is derived from the internal ring oscillator (16 khz typical). data e17 o power switch data. data is used to communicate socket power control information serially to the power switch. latch e18 i/o power switch latch. latch is asserted by the pci1520 to indicate to the power switch that the data on the data line is valid. when a pulldown resistor is implemented on this terminal, the mfunc1 and mfunc4 terminals provide the serial eeprom sda and scl interface. table 2 ? 6. pci system terminals terminal name no. i/o description name ghk i/o description grst c11 i global reset. when the global reset is asserted, the grst signal causes the pci1520 to place all output buffers in a high-impedance state and reset all internal registers. when grst is asserted, the device is completely in its default state. for systems that require wake-up from d3, grst normally is asserted only during initial boot. prst should be asserted following initial boot so that pme context is retained during the transition from d3 to d0. for systems that do not require wake-up from d3, grst should be tied to prst . when the suspend mode is enabled, the device is protected from grst , and the internal registers are preserved. all outputs are placed in a high-impedance state. pclk c10 i pci bus clock. pclk provides timing for all transactions on the pci bus. all pci signals are sampled at the rising edge of pclk. prst c13 i pci reset. when the pci bus reset is asserted, prst causes the pci1520 to place all output buffers in a high-impedance state and reset internal registers. when prst is asserted, the device can generate the pme signal only if it is enabled. after prst is deasserted, the pci1520 is in a default state. when the suspend mode is enabled, the device is protected from prst , and the internal registers are preserved. all outputs are placed in a high-impedance state.
2 ? 9 table 2 ? 7. pci address and data terminals terminal name no. i/o description name ghk i/o description ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 e12 c12 a11 b11 e11 f11 f12 b10 f10 b09 c09 f09 e09 a08 b08 c08 b05 e06 c05 a04 b12 d01 e03 f05 e02 f03 f02 g05 f01 h06 g03 g02 i/o pci address/data bus. these signals make up the multiplexed pci address and data bus on the primary interface. during the address phase of a primary-bus pci cycle, ad31 ? ad0 contain a 32-bit address or other destination information. during the data phase, ad31 ? ad0 contain data. c/be3 c/be2 c/be1 c/be0 b14 f08 f06 g06 i/o pci-bus commands and byte enables. these signals are multiplexed on the same pci terminals. during the address phase of a primary-bus pci cycle, c/be3 ? c/be0 define the bus command. during the data phase, this 4-bit bus is used as byte enables. the byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. c/be0 applies to byte 0 (ad7 ? ad0), c/be1 applies to byte 1 (ad15 ? ad8), c/be2 applies to byte 2 (ad23 ? ad16), and c/be3 applies to byte 3 (ad31 ? ad24). par a05 i/o pci-bus parity. in all pci-bus read and write cycles, the pci1520 calculates even parity across the ad31 ? ad0 and c/be3 ? c/be0 buses. as an initiator during pci cycles, the pci1520 outputs this parity indicator with a one-pclk delay. as a target during pci cycles, the pci1520 compares its calculated parity to the parity indicator of the initiator. a compare error results in the assertion of a parity error (perr ).
2 ? 10 table 2 ? 8. pci interface control terminals terminal name no. i/o description name ghk i/o description devsel f07 i/o pci device select. the pci1520 asserts devsel to claim a pci cycle as the target device. as a pci initiator on the bus, the pci1520 monitors devsel until a target responds. if no target responds before timeout occurs, then the pci1520 terminates the cycle with an initiator abort. frame e08 i/o pci cycle frame. frame is driven by the initiator of a bus cycle. frame is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. when frame is deasserted, the pci bus transaction is in the final data phase. gnt b13 i pci bus grant. gnt is driven by the pci bus arbiter to grant the pci1520 access to the pci bus after the current data transaction has completed. gnt may or may not follow a pci bus request, depending on the pci bus parking algorithm. idsel e10 i initialization device select. idsel selects the pci1520 during configuration space accesses. idsel can be connected to one of the upper 24 pci address lines on the pci bus. irdy b07 i/o pci initiator ready. irdy indicates the ability of the pci bus initiator to complete the current data phase of the transaction. a data phase is completed on a rising edge of pclk where both irdy and trdy are asserted. until irdy and trdy are both sampled asserted, wait states are inserted. perr e07 i/o pci parity error indicator. perr is driven by a pci device to indicate that calculated parity does not match par when perr is enabled through bit 6 of the command register (pci offset 04h, see section 4.4). req a13 o pci bus request. req is asserted by the pci1520 to request access to the pci bus as an initiator. serr c06 o pci system error. serr is an output that is pulsed from the pci1520 when enabled through bit 8 of the command register (pci offset 04h, see section 4.4) indicating a system error has occurred. the pci1520 need not be the target of the pci cycle to assert this signal. when serr is enabled in the command register, this signal also pulses, indicating that an address parity error has occurred on a cardbus interface. stop b06 i/o pci cycle stop signal. stop is driven by a pci target to request the initiator to stop the current pci bus transaction. stop is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers. trdy c07 i/o pci target ready. trdy indicates the ability of the primary bus target to complete the current data phase of the transaction. a data phase is completed on a rising edge of pclk when both irdy and trdy are asserted. until both irdy and trdy are asserted, wait states are inserted.
2 ? 11 table 2 ? 9. multifunction and miscellaneous terminals terminal name no. i/o description name ghk i/o description mfunc0 d19 i/o multifunction terminal 0. mfunc0 can be configured as parallel pci interrupt inta , gpi0, gpo0, socket activity led output, zv switching output, cardbus audio pwm, gpe , or a parallel irq. see section 4.30, multifunction routing register , for configuration details. mfunc1 a16 i/o multifunction terminal 1. mfunc1 can be configured as parallel pci interrupt intb , gpi1, gpo1, socket activity led output, zv switching output, cardbus audio pwm, gpe , or a parallel irq. see section 4.30, multifunction routing register , for configuration details. serial data (sda). when latch is detected low after the deassertion of grst , the mfunc1 terminal provides the sda signaling for the serial bus interface. the two-terminal serial interface loads the subsystem identification and other register defaults from an eeprom after a pci reset. see section 3.6.1, serial bus interface implementation , for details on other serial bus applications. mfunc2 e14 i/o multifunction terminal 2. mfunc2 can be configured as gpi2, gpo2, socket activity led output, zv switching output, cardbus audio pwm, gpe , ri_out , d3_stat , or a parallel irq. see section 4.30, multifunction routing register , for configuration details. mfunc3/ irqser f13 i/o multifunction terminal 3. mfunc3 can be configured as a parallel irq or the serialized interrupt signal irqser. this terminal is irqser by default. see section 4.30, multifunction routing register , for configuration details. mfunc4 b15 i/o multifunction terminal 4. mfunc4 can be configured as pci lock , gpi3, gpo3, socket activity led output, zv switching output, cardbus audio pwm, gpe , d3_stat , ri_out , or a parallel irq. see section 4.30, multifunction routing register , for configuration details. serial clock (scl). when latch is detected low after the deassertion of grst , the mfunc4 terminal provides the scl signaling for the serial bus interface. the two-terminal serial interface loads the subsystem identification and other register defaults from an eeprom after a pci reset. see section 3.6.1, serial bus interface implementation , for details on other serial bus applications. mfunc5 a15 i/o multifunction terminal 5. mfunc5 can be configured as gpi4, gpo4, socket activity led output, zv switching output, cardbus audio pwm, d3_stat , gpe , or a parallel irq. see section 4.30, multifunction routing register , for configuration details. mfunc6/ clkrun c14 i/o multifunction terminal 6. mfunc6 can be configured as a pci clkrun or a parallel irq. see section 4.30, multifunction routing register , for configuration details. nc e05 w11 no connect. these terminals have no connection anywhere within the package. terminal e05 on the ghk package is used as a key to indicate the location of the a1 corner of the bga package. terminals w11 on the ghk package and 81 on the pdv package will be used as a 48-mhz clock input on future-generation devices. ri_out /pme e13 o ring indicate out and power management event output. this terminal provides an output for ring-indicate or pme signals. spkrout f14 o speaker output. spkrout is the output to the host system that can carry spkr or caudio through the pci1520 from the pc card interface. spkrout is driven as the exclusive-or combination of card spkr //caudio inputs. suspend c15 i suspend. suspend protects the internal registers from clearing when the grst or prst signal is asserted. see section 3.8.5, suspend mode , for details.
2 ? 12 table 2 ? 10. 16-bit pc card address and data terminals (slots a and b) terminal number name slot a ? slot b ? i/o description ghk ghk a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 l19 m18 m15 n17 n15 p17 n14 r17 w16 m14 n18 r18 p15 m17 p14 r13 u15 t19 m19 l17 l14 k18 k15 j18 j17 j14 r06 w04 r03 r02 p03 p02 n03 m05 m03 p06 p05 n06 n02 t01 l06 k06 m02 m06 u05 v05 u06 v06 p08 v07 w07 r08 o pc card address. 16-bit pc card address lines. a25 is the most significant bit. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 p13 v13 p12 v12 r11 e19 g15 g14 u13 r12 u12 w12 p11 f17 f18 g17 k03 j06 j03 j01 h02 v11 r10 v10 k02 j05 j02 h01 h03 p10 u10 w10 i/o pc card data. 16-bit pc card data lines. d15 is the most significant bit. ? terminal name for slot a is preceded with a_. for example, the full name for terminals 123 and l19 is a_a25. ? terminal name for slot b is preceded with b_. for example, the full name for terminals 55 and r06 is b_a25.
2 ? 13 table 2 ? 11. 16-bit pc card interface control terminals (slots a and b) terminal number name slot a ? slot b ? i/o description ghk ghk bvd1 (stschg /ri ) h14 u09 i battery voltage detect 1. bvd1 is generated by 16-bit memory pc cards that include batteries. bvd1 is used with bvd2 as an indication of the condition of the batteries on a memory pc card. both bvd1 and bvd2 are high when the battery is good. when bvd2 is low and bvd1 is high, the battery is weak and should be replaced. when bvd1 is low, the battery is no longer serviceable and the data in the memory pc card is lost. see section 5.6, exca card status-change interrupt configuration register , for enable bits. see section 5.5, exca card status-change register , and section 5.2, exca interface status register , for the status bits for this signal. status change. stschg is used to alert the system to a change in the ready, write protect, or battery voltage dead condition of a 16-bit i/o pc card. ring indicate. ri is used by 16-bit modem cards to indicate a ring detection. bvd2 (spkr ) h17 v09 i battery voltage detect 2. bvd2 is generated by 16-bit memory pc cards that include batteries. bvd2 is used with bvd1 as an indication of the condition of the batteries on a memory pc card. both bvd1 and bvd2 are high when the battery is good. when bvd2 is low and bvd1 is high, the battery is weak and should be replaced. when bvd1 is low, the battery is no longer serviceable and the data in the memory pc card is lost. see section 5.6, exca card status-change interrupt configuration register , for enable bits. see section 5.5, exca card status-change register , and section 5.2, exca interface status register , for the status bits for this signal. speaker. spkr is an optional binary audio signal available only when the card and socket have been configured for the 16-bit i/o interface. the audio signals from cards a and b are combined by the pci1520 and are output on spkrout. cd1 cd2 u11 g18 h05 p09 i card detect 1 and card detect 2. cd1 and cd2 are internally connected to ground on the pc card. when a pc card is inserted into a socket, cd1 and cd2 are pulled low. for signal status, see section 5.2, exca interface status register . ce1 ce2 v14 u14 k05 l02 o card enable 1 and card enable 2. ce1 and ce2 enable even- and odd-numbered address bytes. ce1 enables even-numbered address bytes, and ce2 enables odd-numbered address bytes. inpack k17 r07 i input acknowledge. inpack is asserted by the pc card when it can respond to an i/o read cycle at the current address. iord v15 l05 o i/o read. iord is asserted by the pci1520 to enable 16-bit i/o pc card data output during host i/o read cycles. iowr r14 m01 o i/o write. iowr is driven low by the pci1520 to strobe write data into 16-bit i/o pc cards during host i/o write cycles. ? terminal name for slot a is preceded with a_. for example, the full name for terminals 130 and k17 is a_inpack . ? terminal name for slot b is preceded with b_. for example, the full name for terminals 61 and r07 is b_inpack .
2 ? 14 table 2 ? 11. 16-bit pc card interface control terminals (slots a and b) (continued) terminal number name slot a ? slot b ? i/o description ghk ghk oe w15 l03 o output enable. oe is driven low by the pci1520 to enable 16-bit memory pc card data output during host memory read cycles. ready (ireq ) h19 v08 i ready. the ready function is provided by ready when the 16-bit pc card and the host socket are configured for the memory-only interface. ready is driven low by 16-bit memory pc cards to indicate that the memory card circuits are busy processing a previous write command. ready is driven high when the 16-bit memory pc card is ready to accept a new data transfer command. interrupt request. ireq is asserted by a 16-bit i/o pc card to indicate to the host that a device on the 16-bit i/o pc card requires service by the host software. ireq is high (deasserted) when no interrupt is requested. reg k14 u07 o attribute memory select. reg remains high for all common memory accesses. when reg is asserted, access is limited to attribute memory (oe or we active) and to the i/o space (iord or iowr active). attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information. reset l15 w05 o pc card reset. reset forces a hard reset to a 16-bit pc card. vs1 vs2 j15 l18 u08 p07 i/o voltage sense 1 and voltage sense 2. vs1 and vs2 , when used in conjunction with each other, determine the operating voltage of the pc card. wait h18 w09 i bus cycle wait. wait is driven by a 16-bit pc card to extend the completion of the memory or i/o cycle in progress. we p18 n05 o write enable. we is used to strobe memory write data into 16-bit memory pc cards. we is also used for memory pc cards that employ programmable memory technologies. wp (iois16 ) h15 r09 i write protect. wp applies to 16-bit memory pc cards. wp reflects the status of the write-protect switch on 16-bit memory pc cards. for 16-bit i/o cards, wp is used for the 16-bit port (iois16 ) function. i/o is 16 bits. iois16 applies to 16-bit i/o pc cards. iois16 is asserted by the 16-bit pc card when the address on the bus corresponds to an address to which the 16-bit pc card responds, and the i/o port that is addressed is capable of 16-bit accesses. ? terminal name for slot a is preceded with a_. for example, the full name for terminals 112 and p18 is a_we . ? terminal name for slot b is preceded with b_. for example, the full name for terminals 45 and n05 is b_we . table 2 ? 12. cardbus pc card interface system terminals (slots a and b) terminal number name slot a ? slot b ? i/o description ghk ghk cclk m14 p06 o cardbus clock. cclk provides synchronous timing for all transactions on the cardbus interface. all signals except crst , cclkrun , cint , cstschg, caudio, ccd2 , ccd1 , cvs2, and cvs1 are sampled on the rising edge of cclk, and all timing parameters are defined with the rising edge of this signal. cclk operates at the pci bus clock frequency, but it can be stopped in the low state or slowed down for power savings. cclkrun h15 r09 i/o cardbus clock run. cclkrun is used by a cardbus pc card to request an increase in the cclk frequency, and by the pci1520 to indicate that the cclk frequency is going to be decreased. crst l15 w05 o cardbus reset. crst brings cardbus pc card-specific registers, sequencers, and signals to a known state. when crst is asserted, all cardbus pc card signals are placed in a high-impedance state, and the pci1520 drives these signals to a valid logic level. assertion can be asynchronous to cclk, but deassertion must be synchronous to cclk. ? terminal name for slot a is preceded with a_. for example, the full name for terminals 115 and m14 is a_cclk. ? terminal name for slot b is preceded with b_. for example, the full name for terminals 48 and p06 is b_cclk.
2 ? 15 table 2 ? 13. cardbus pc card address and data terminals (slots a and b) terminal number name slot a ? slot b ? i/o description ghk ghk cad31 cad30 cad29 cad28 cad27 cad26 cad25 cad24 cad23 cad22 cad21 cad20 cad19 cad18 cad17 cad16 cad15 cad14 cad13 cad12 cad11 cad10 cad9 cad8 cad7 cad6 cad5 cad4 cad3 cad2 cad1 cad0 e19 g15 f18 g14 g17 j14 j17 j18 k15 k18 l14 l17 l19 m19 m18 w16 r14 u15 v15 p14 w15 u14 r13 p13 u13 p12 r12 v12 u12 r11 w12 p11 v11 r10 u10 v10 w10 r08 w07 v07 p08 v06 u06 v05 r06 u05 w04 m03 m01 m02 l05 l06 l03 l02 k06 k03 k02 j03 j05 j01 j02 h02 h01 h03 i/o cardbus address and data. these signals make up the multiplexed cardbus address and data bus on the cardbus interface. during the address phase of a cardbus cycle, cad31 ? cad0 contain a 32-bit address. during the data phase of a cardbus cycle, cad31 ? cad0 contain data. cad31 is the most significant bit. cc/be3 cc/be2 cc/be1 cc/be0 k14 m17 t19 v14 u07 t01 m06 k05 i/o cardbus bus commands and byte enables. cc/be3 ? cc/be0 are multiplexed on the same cardbus terminals. during the address phase of a cardbus cycle, cc/be3 ? cc/be0 define the bus command. during the data phase, this 4-bit bus is used as byte enables. the byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. cc/be0 applies to byte 0 (cad7 ? cad0), cc/be1 applies to byte 1 (cad15 ? cad8), cc/be2 applies to byte 2 (cad23 ? cad16), and cc/be3 applies to byte 3 (cad31 ? cad24). cpar p15 n02 i/o cardbus parity. in all cardbus read and write cycles, the pci1520 calculates even parity across the cad and cc/be buses. as an initiator during cardbus cycles, the pci1520 outputs cpar with a one-cclk delay. as a target during cardbus cycles, the pci1520 compares its calculated parity to the parity indicator of the initiator; a compare error results in a parity error assertion. ? terminal name for slot a is preceded with a_. for example, the full name for terminals 107 and p15 is a_cpar. ? terminal name for slot b is preceded with b_. for example, the full name for terminals 40 and n02 is b_cpar.
2 ? 16 table 2 ? 14. cardbus pc card interface control terminals (slots a and b) terminal number name slot a ? slot b ? i/o description ghk ghk caudio h17 v09 i cardbus audio. caudio is a digital input signal from a pc card to the system speaker. the pci1520 supports the binary audio mode and outputs a binary signal from the card to spkrout. cblock n14 n03 i/o cardbus lock. cblock is used to gain exclusive access to a target. ccd1 u11 h05 i cardbus detect 1 and cardbus detect 2. ccd1 and ccd2 are used in con j unction with cvs1 and ccd1 ccd2 u11 g18 h05 p09 i cardbus detect 1 and cardbus detect 2 . ccd1 and ccd2 are used in conjunction with cvs1 and cvs2 to identify card insertion and interrogate cards to determine the operating voltage and card type. cdevsel n15 p03 i/o cardbus device select. the pci1520 asserts cdevsel to claim a cardbus cycle as the target device. as a cardbus initiator on the bus, the pci1520 monitors cdevsel until a target responds. if no target responds before timeout occurs, then the pci1520 terminates the cycle with an initiator abort. cframe m15 r03 i/o cardbus cycle frame. cframe is driven by the initiator of a cardbus bus cycle. cframe is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. when cframe is deasserted, the cardbus bus transaction is in the final data phase. cgnt p18 n05 o cardbus bus grant. cgnt is driven by the pci1520 to grant a cardbus pc card access to the cardbus bus after the current data transaction has been completed. cint h19 v08 i cardbus interrupt. cint is asserted low by a cardbus pc card to request interrupt servicing from the host. cirdy n18 p05 i/o cardbus initiator ready. cirdy indicates the ability of the cardbus initiator to complete the current data phase of the transaction. a data phase is completed on a rising edge of cclk when both cirdy and ctrdy are asserted. until cirdy and ctrdy are both sampled asserted, wait states are inserted. cperr r18 n06 i/o cardbus parity error. cperr reports parity errors during cardbus transactions, except during special cycles. it is driven low by a target two clocks following the data cycle during which a parity error is detected. creq k17 r07 i cardbus request. creq indicates to the arbiter that the cardbus pc card desires use of the cardbus bus as an initiator. cserr h18 w09 i cardbus system error. cserr reports address parity errors and other system errors that could lead to catastrophic results. cserr is driven by the card synchronous to cclk, but deasserted by a weak pullup; deassertion may take several cclk periods. the pci1520 can report cserr to the system by assertion of serr on the pci interface. cstop p17 p02 i/o cardbus stop. cstop is driven by a cardbus target to request the initiator to stop the current cardbus transaction. cstop is used for target disconnects, and is commonly asserted by target devices that do not support burst data transfers. cstschg h14 u09 i cardbus status change. cstschg alerts the system to a change in the card status, and is used as a wake-up mechanism. ctrdy n17 r02 i/o cardbus target ready. ctrdy indicates the ability of the cardbus target to complete the current data phase of the transaction. a data phase is completed on a rising edge of cclk, when both cirdy and ctrdy are asserted; until this time, wait states are inserted. cvs1 cvs2 j15 l18 u08 p07 i/o cardbus voltage sense 1 and cardbus voltage sense 2. cvs1 and cvs2 are used in conjunction with ccd1 and ccd2 to identify card insertion and interrogate cards to determine the operating voltage and card type. ? terminal name for slot a is preceded with a_. for example, the full name for terminals 140 and h18 is a_caudio. ? terminal name for slot b is preceded with b_. for example, the full name for terminals 72 and v09 is b_caudio.
3 ? 1 3 feature/protocol descriptions the following sections give an overview of the pci1520. figure 3 ? 1 shows a simplified block diagram of the pci1520. the pci interface includes all address/data and control signals for pci protocol. the interrupt interface includes terminals for parallel pci, parallel isa, and serialized pci and isa signaling. miscellaneous system interface terminals include multifunction terminals: suspend , ri_out /pme (power management control signal), and spkrout. pci bus pci1520 activity leds pci950 irqser deserializer irqser 3 interrupt controller inta intb irq2 ? 15 multiplexer 23 23 pc card socket a tps222x power switch 3 pc card socket b external zv port vga controller audio subsystem zoomed video 19 4 zoomed video note: the pc card interface is 68 terminals for cardbus and 16-bit pc cards. in zoomed video mode 23 terminals are used for rout ing the zoomed video signals to the vga controller and audio subsystem. 68 68 68 68 23 figure 3 ? 1. pci1520 simplified block diagram 3.1 power supply sequencing the pci1520 contains 3.3-v i/o buffers with 5-v tolerance requiring an i/o power supply and an ldo-vr power supply for core logic. the core power supply, which is always 2.5 v, can be supplied through the vr_port terminal (when vr_en is high) or from the integrated ldo-vr. the ldo-vr needs a 3.3-v power supply via the v cc terminals. the clamping voltages (v cca , v ccb , and v ccp ) can be either 3.3 v or 5 v, depending on the interface. the following power-up and power-down sequences are recommended. the power-up sequence is: 1. assert grst to the device to disable the outputs during power up. output drivers must be powered up in the high-impedance state to prevent high current levels through the clamp diodes to the 5-v clamping rails (v cca , v ccb , and v ccp ). 2. apply 3.3-v power to v cc . 3. apply the clamp voltage.
3 ? 2 the power-down sequence is: 1. assert grst to the device to disable the outputs during power down. output drivers must be powered down in the high-impedance state to prevent high current levels through the clamp diodes to the 5-v clamping rails (v cca , v ccb , and v ccp ). 2. remove the clamp voltage. 3. remove the 3.3-v power from v cc . note: the clamp voltage can be ramped up or ramped down along with the 3.3-v power. the voltage difference between v cc and the clamp voltage must remain within 3.6 v. 3.2 i/o characteristics figure 3 ? 2 shows a 3-state bidirectional buffer. section 7.2, recommended operating conditions , provides the electrical characteristics of the inputs and outputs. note: the pci1520 meets the ac specifications of the 1997 pc card standard and pci local bus specification. tied for open drain oe pad v ccp figure 3 ? 2. 3-state bidirectional buffer note: unused terminals (input or i/o) must be held high or low to prevent them from floating. 3.3 clamping voltages the clamping voltages are set to match whatever external environment the pci1520 is interfaced with, 3.3 v or 5 v. the i/o sites can be pulled through a clamping diode to a voltage rail that protects the core from external signals. the core power supply is always 3.3 v and is independent of the clamping voltages. for example, pci signaling can be either 3.3 v or 5 v, and the pci1520 must reliably accommodate both voltage levels. this is accomplished by using a 3.3-v i/o buffer that is 5-v tolerant, with the applicable clamping voltage applied. if a system designer desires a 5-v pci bus, then v ccp can be connected to a 5-v power supply. the pci1520 requires three separate clamping voltages because it supports a wide range of features. the three voltages are listed and defined in section 7.2, recommended operating conditions . grst , suspend , pme , and cstschg are not clamped to any of them. 3.4 peripheral component interconnect (pci) interface the pci1520 is fully compliant with the pci local bus specification . the pci1520 provides all required signals for pci master or slave operation, and may operate in either a 5-v or 3.3-v signaling environment by connecting the v ccp terminal to the desired voltage level. in addition to the mandatory pci signals, the pci1520 provides the optional interrupt signals inta and intb . 3.4.1 pci grst signal during the power-up sequence, grst and prst must be asserted. grst can only be deasserted 100 s after pclk is stable. prst can be deasserted at the same time as grst or any time thereafter.
3 ? 3 3.4.2 pci bus lock (lock ) the bus-locking protocol defined in the pci local bus specification is not highly recommended, but is provided on the pci1520 as an additional compatibility feature. the pci lock signal can be routed to the mfunc4 terminal by setting the appropriate values in bits 19 ? 16 of the multifunction routing register. see section 4.30, multifunction routing register , for details. note that the use of lock is only supported by pci-to-cardbus bridges in the downstream direction (away from the processor). pci lock indicates an atomic operation that may require multiple transactions to complete. when lock is asserted, nonexclusive transactions can proceed to an address that is not currently locked. a grant to start a transaction on the pci bus does not guarantee control of lock ; control of lock is obtained under its own protocol. it is possible for different initiators to use the pci bus while a single master retains ownership of lock . note that the cardbus signal for this protocol is cblock to avoid confusion with the bus clock. an agent may need to do an exclusive operation because a critical access to memory might be broken into several transactions, but the master wants exclusive rights to a region of memory. the granularity of the lock is defined by pci to be 16 bytes, aligned. the lock protocol defined by the pci local bus specification allows a resource lock without interfering with nonexclusive real-time data transfer, such as video. the pci bus arbiter may be designed to support only complete bus locks using the lock protocol. in this scenario, the arbiter will not grant the bus to any other agent (other than the lock master) while lock is asserted. a complete bus lock may have a significant impact on the performance of the video. the arbiter that supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation is in progress. the pci1520 supports all lock protocol associated with pci-to-pci bridges, as also defined for pci-to-cardbus bridges. this includes disabling write posting while a locked operation is in progress, which can solve a potential deadlock when using devices such as pci-to-pci bridges. the potential deadlock can occur if a cardbus target supports delayed transactions and blocks access to the target until it completes a delayed read. this target characteristic is prohibited by the pci local bus specification , and the issue is resolved by the pci master using lock . 3.4.3 loading subsystem identification the subsystem vendor id register (pci offset 40h, see section 4.26) and subsystem id register (pci offset 42h, see section 4.27) make up a doubleword of pci configuration space for functions 0 and 1. this doubleword register is used for system and option card (mobile dock) identification purposes and is required by some operating systems. implementation of this unique identifier register is a pc 99/pc 2001 requirement. the pci1520 offers two mechanisms to load a read-only value into the subsystem registers. the first mechanism relies upon the system bios providing the subsystem id value. the default access mode to the subsystem registers is read-only, but can be made read/write by clearing bit 5 (subsysrw) in the system control register (pci offset 80h, see section 4.29). once this bit is cleared, the bios can write a subsystem identification value into the registers at pci offset 40h. the bios must set the subsysrw bit such that the subsystem vendor id register and subsystem id register is limited to read-only access. this approach saves the added cost of implementing the serial electrically erasable programmable rom (eeprom). in some conditions, such as in a docking environment, the subsystem vendor id register and subsystem id register must be loaded with a unique identifier via a serial eeprom. the pci1520 loads the data from the serial eeprom after a reset of the primary bus. note that the suspend input gates the pci reset from the entire pci1520 core, including the serial-bus state machine (see section 3.8.5, suspend mode , for details on using suspend ). the pci1520 provides a two-line serial-bus host controller that can interface to a serial eeprom. see section 3.6, serial-bus interface , for details on the two-wire serial-bus controller and applications.
3 ? 4 3.5 pc card applications this section describes the pc card interfaces of the pci1520. ? card insertion/removal and recognition ? p 2 c power-switch interface ? zoomed video support ? speaker and audio applications ? led socket activity indicators ? cardbus socket registers 3.5.1 pc card insertion/removal and recognition the pc card standard (release 7.1) addresses the card-detection and recognition process through an interrogation procedure that the socket must initiate on card insertion into a cold, nonpowered socket. through this interrogation, card voltage requirements and interface (16-bit versus cardbus) are determined. the scheme uses the card-detect and voltage-sense signals. the configuration of these four terminals identifies the card type and voltage requirements of the pc card interface. the encoding scheme is defined in the pc card standard (release 7.1) and in table 3 ? 1. table 3 ? 1. pc card card-detect and voltage-sense connections cd2 //ccd2 cd1 //ccd1 vs2 //cvs2 vs1 //cvs1 key interface voltage ground ground open open 5 v 16-bit pc card 5 v ground ground open ground 5 v 16-bit pc card 5 v and 3.3 v ground ground ground ground 5 v 16-bit pc card 5 v, 3.3 v, and x.x v ground ground open ground lv 16-bit pc card 3.3 v ground connect to cvs1 open connect to ccd1 lv cardbus pc card 3.3 v ground ground ground ground lv 16-bit pc card 3.3 v and x.x v connect to cvs2 ground connect to ccd2 ground lv cardbus pc card 3.3 v and x.x v connect to cvs1 ground ground connect to ccd2 lv cardbus pc card 3.3 v, x.x v, and y.y v ground ground ground open lv 16-bit pc card x.x v connect to cvs2 ground connect to ccd2 open lv cardbus pc card x.x v ground connect to cvs2 connect to ccd1 open lv cardbus pc card x.x v and y.y v connect to cvs1 ground open connect to ccd2 lv cardbus pc card y.y v ground connect to cvs1 ground connect to ccd1 reserved ground connect to cvs2 connect to ccd1 ground reserved 3.5.2 p 2 c power-switch interface (tps222x) the pci1520 provides a pcmcia peripheral control (p 2 c) interface for control of the pc card power switch. the clock, data, and latch terminals interface with the ti tps222x dual-slot pc card power interface switches to provide power switch support. figure 3 ? 3 illustrates a typical application where the pci1520 represents the pcmcia controller. table 3 ? 2 shows the available power switch options compatible with the pci1520.
3 ? 5 pci1520 (pcmcia controller) 12 v power supply v pp1 v pp2 v cc v cc pc card a tps222x 5 v 3.3 v clock v pp1 v pp2 v cc v cc pc card b 12 v 5 v 3.3 v avpp avcc avcc bvpp bvcc bvcc bvcc avcc supervisor reset reset data latch figure 3 ? 3. tps222x typical application table 3 ? 2. power switch options device pin-compatible replacement(s) tps2206 tps2226idb ? ? 30-pin ssop tps2216adap ? 32-pin tssop tps2214(a) tps2224idb ? ? 24-pin ssop tps2216(a) tps2226idb ? ? 30 pin ssop tps2223 ?? n/a ? check for newer device tps2224 ? n/a ? check for newer device tps2226 ? n/a ? check for newer device ? recommended for new designs ? for applications not requiring 12 volts the clock terminal on the pci1520 can be an input or an output. the pci1520 defaults the clock terminal as an input to control the serial interface and the internal state machine. bit 27 (p2cclk) in the system control register (offset 80h, see section 4.29) can be set by the platform bios or the serial eeprom to enable the pci1520 to generate and drive clock internally from the pci clock. when the system design implements clock as an output from the pci1520, an external pulldown resistor is required. 3.5.3 zoomed video support the pci1520 allows for the implementation of zoomed video (zv) for pc cards. zoomed video is supported by setting bit 6 (zvenable) in the card control register (pci offset 91h, see section 4.32) on a per-socket function basis. setting this bit puts 16-bit pc card address lines a25 ? a4 of the pc card interface in the high-impedance state. these lines can then transfer video and audio data directly to the appropriate controller. card address lines a3 ? a0 can still access pc card cis registers for pc card configuration. figure 3 ? 4 illustrates a pci1520 zv implementation.
3 ? 6 crt vga controller audio codec pci1520 19 4 zoomed video port pcm audio input pci bus pc card interface video audio 19 4 pc card motherboard speakers figure 3 ? 4. zoomed video implementation using the pci1520 not shown in figure 3 ? 4 is the multiplexing scheme used to route either socket 0 or socket 1 zv source to the graphics controller. the pci1520 provides zvstat, zvsel0 , and zvsel1 signals on the multifunction terminals to switch external bus drivers. figure 3 ? 5 shows an implementation for switching between three zv streams using external logic. zvstat zvsel0 zvsel1 pci1520 2 0 1 figure 3 ? 5. zoomed video switching application figure 3 ? 5 illustrates an implementation using standard three-state bus drivers with active-low output enables. zvsel0 is an active-low output indicating that the socket 0 zv mode is enabled, and zvsel1 is an active-low output indicating that socket 1 zv is enabled. when both sockets have zv mode enabled, the pci1520 by defaults indicates socket 0 enabled through zvsel0 ; however, bit 5 (port_sel) in the card control register (see section 4.32) allows software to select the socket zv source priority. table 3 ? 3 illustrates the functionality of the zv output signals.
3 ? 7 table 3 ? 3. functionality of the zv output signals inputs outputs portsel socket 0 enable socket 1 enable zvsel0 zvsel1 zvstat x 0 0 1 1 0 0 1 x 0 1 1 0 0 1 1 0 1 1 x 1 1 0 1 1 1 0 0 1 1 also shown in figure 3 ? 5 is a third zv input that can be provided from a source such as a high-speed serial bus like ieee 1394. the zvstat signal provides a mechanism to switch the third zv source. zvstat is an active-high output indicating that one of the pci1520 sockets is enabled for zv mode. the implementation shown in figure 3 ? 5 can be used if pc card zv is prioritized over other sources. 3.5.4 standardized zoomed-video register model the standardized zoomed-video register model is defined for the purpose of standardizing the zv port control for pc card controllers across the industry. the following list summarizes the standardized zoomed-video register model changes to the existing pc card register set. ? socket present state register (cardbus socket address + 08h, see section 6.3) bit 27 (zvsupport) has been added. the platform bios can set this bit via the socket force event register (cardbus socket address + 0ch, see section 6.4) to define whether zoomed video is supported on that socket by the platform. ? socket force event register (cardbus socket address + 0ch, see section 6.4) bit 27 (fzvsupport) has been added. the platform bios can use this bit to set the zvsupport bit in the socket present state register (cardbus socket address + 08h, see section 6.3) to define whether zoomed video is supported on that socket by the platform. ? socket control register (cardbus socket address +10h, see section 6.5) bit 11 (zv_activity) has been added. this bit is set when zoomed video is enabled for either of the pc card sockets. bit 10 (stdzvreg) has been added. this bit defines whether the pc card controller supports the standardized zoomed-video register model. bit 9 (zven) is provided for software to enable or disable zoomed video, per socket. if the stdzven bit (bit 0) in the diagnostic register (pci offset 93h, see section 4.34) is 1, then the standardized zoomed video register model is disabled. for backward compatibility, even if the stdzven bit is 0 (enabled), the pci1520 allows software to access zoomed video through the legacy address in the card control register (pci offset 91h, see section 4.32), or through the new register model in the socket control register (cardbus socket address + 10h, see section 6.5). 3.5.4.1 zoomed-video card insertion and configuration procedure 1. a zoomed-video pc card is inserted into an empty slot. 2. the card is detected and interrogated appropriately.
3 ? 8 there are two types of pc card controllers to consider. ? legacy controller not using the standardized zv register model software reads bit 10 (stdzvreg) of the socket control register (cardbus socket address + 10h) to determine if the standardized zoomed-video register model is supported. if the bit returns 0, then software must use legacy code to enable zoomed video. ? newer controller that uses the standardized zv register model software reads bit 10 (stdzvreg) of the socket control register (cardbus socket address + 10h) to determine if the standardized zoomed-video register model is supported. if the bit returns 1, then software can use the process/register model detailed in table 3 ? 4 to enable zoomed video. table 3 ? 4. zoomed-video card interrogation zvsupport (this socket) zvsupport (other socket) zv_activity action 1 x 0 set zven to enable zoomed video. 1 x 1 display a user message such as, ? the zoomed video protocol required by this pc card application is already in use by another card. ? 0 0 x display a user message such as, ? this platform does not support the zoomed-video protocol required by this pc card application. ? 0 1 x display a user message such as, ? this platform does not support the zoomed-video protocol required by this pc card application in this pc card socket. please remove the card and re-insert in the other pc card socket. ? 3.5.5 internal ring oscillator the internal ring oscillator provides an internal clock source for the pci1520 so that neither the pci clock nor an external clock is required in order for the pci1520 to power down a socket or interrogate a pc card. this internal oscillator, operating nominally at 16 khz, can be enabled by setting bit 27 (p2cclk) of the system control register (pci offset 80h, see section 4.29) to 1. this function is disabled by default. 3.5.6 integrated pullup resistors the pc card standard (release 7.1) requires pullup resistors on various terminals to support both cardbus and 16-bit card configurations. unlike the pci12xx, pci1450, and pci4450 which required external pullup resistors, the pci1520 has integrated all of these pullup resistors. the i/o buffer on the bvd1(stschg )/cstschg terminal has the capability to switch either pullup or pulldown. the pullup resistor is turned on when a 16-bit pc card is inserted, and the pulldown resistor is turned on when a cardbus pc card is inserted. this prevents unexpected cstschg signal assertion. the integrated pullup resistors are listed in table 3 ? 5.
3 ? 9 table 3 ? 5. integrated pullup resistors signal name term. number socket a term. number socket b signal name pdv ghk pdv ghk a14/cperr 109 r18 42 n06 a15/cirdy 117 n18 50 p05 a19/cblock 108 n14 41 n03 a20/cstop 111 p17 44 p02 a21/cdevsel 113 n15 46 p03 a22/ctrdy 116 n17 49 r02 bvd1(stschg )/cstschg 141 h14 73 u09 bvd2(spkr )/caudio 140 h17 72 v09 cd1 /ccd1 83 u11 15 h05 cd2 /ccd2 144 g18 75 p09 inpack /creq 130 k17 61 r07 ready/cint 138 h19 69 v08 reset/crst 126 l15 58 w05 vs1 /cvs1 137 j15 68 u08 vs2 /cvs2 124 l18 56 p07 wait /cserr 139 h18 71 w09 wp(iois16 )/cclkrun 142 h15 74 r09 3.5.7 spkrout and caudpwm usage spkrout carries the digital audio signal from the pc card to the system. when a 16-bit pc card is configured for i/o mode, the bvd2 terminal becomes spkr . this terminal is also used in cardbus binary audio applications, and is referred to as caudio. spkr passes a ttl-level digital audio signal to the pci1520. the cardbus caudio signal also can pass a single-amplitude binary waveform. the binary audio signals from the two pc card sockets are xored in the pci1520 to produce spkrout. this output is enabled by bit 1 (spkrouten) in the card control register (pci offset 91h, see section 4.32). older controllers support caudio in binary or pwm mode but use the same terminal (spkrout). some audio chips may not support both modes on one terminal and may have a separate terminal for binary and pwm. the pci1520 implementation includes a signal for pwm, caudpwm, which can be routed to an mfunc terminal. bit 2 (aud2mux), located in the card control register, is programmed on a per-socket function basis to route a cardbus caudio pwm terminal to caudpwm. if both cardbus functions enable caudio pwm routing to caudpwm, then socket 0 audio takes precedence. see section 4.30, multifunction routing register , for details on configuring the mfunc terminals. figure 3 ? 6 provides an illustration of a sample application using spkrout and caudpwm.
3 ? 10 speaker subsystem binary_spkr system core logic pci1520 caudpwm spkrout pwm_spkr figure 3 ? 6. sample application of spkrout and caudpwm 3.5.8 led socket activity indicators the socket activity leds are provided to indicate when a pc card is being accessed. the leda1 and leda2 signals can be routed to the multifunction terminals. when configured for led outputs, these terminals output an active high signal to indicate socket activity. leda1 indicates socket 0 (card a) activity, and leda2 indicates socket 1 (card b) activity. the led_skt output indicates socket activity to either socket 0 or socket 1. see section 4.30, multifunction routing register , for details on configuring the multifunction terminals. the active-high led signal is driven for 64-ms. when the led is not being driven high, it is driven to a low state. either of the two circuits shown in figure 3 ? 7 can be implemented to provide led signaling, and the board designer must implement the circuit that best fits the application. the led activity signals are valid when a card is inserted, powered, and not in reset. for pc card-16, the led activity signals are pulsed when ready/ireq is low. for cardbus cards, the led activity signals are pulsed if cframe , irdy , or creq are active. pci1520 application- specific delay current limiting r 500 ? pci1520 current limiting r 500 ? led led figure 3 ? 7. two sample led circuits as indicated, the led signals are driven for a period of 64 ms by a counter circuit. to avoid the possibility of the leds appearing to be stuck when the pci clock is stopped, the led signaling is cut off when the suspend signal is asserted, when the pci clock is to be stopped during the clock run protocol, or when in the d2 or d1 power state. if any additional socket activity occurs during this counter cycle, then the counter is reset and the led signal remains driven. if socket activity is frequent (at least once every 64 ms), then the led signals remain driven. 3.5.9 cardbus socket registers the pci1520 contains all registers for compatibility with the 1997 pc card standard . these registers exist as the cardbus socket registers and are listed in table 3 ? 6.
3 ? 11 table 3 ? 6. cardbus socket registers register name offset socket event 00h socket mask 04h socket present state 08h socket force event 0ch socket control 10h reserved 14h ? 1ch socket power management 20h 3.6 serial-bus interface the pci1520 provides a serial-bus interface to load subsystem identification information and selected register defaults from a serial eeprom, and to provide a pc card power-switch interface alternative to p 2 c. see section 3.5.2, p 2 c power-switch interface (tps222x) , for details. the pci1520 serial-bus interface is compatible with various i 2 c and smbus components. 3.6.1 serial-bus interface implementation the pci1520 defaults to serial bus interface are disabled. to enable the serial interface, a pulldown resistor must be implemented on the latch terminal and the appropriate pullup resistor must be implemented on the sda and scl signals, that is, the mfunc1 and mfunc4 terminals. when the interface is detected, bit 3 (sbdetect) in the serial bus control and status register (see section 4.48) is set. the sbdetect bit is cleared by a writeback of 1. the pci1520 implements a two-terminal serial interface with one clock signal (scl) and one data signal (sda). when a pulldown resistor is provided on the latch terminal, the scl signal is mapped to the mfunc4 terminal and the sda signal is mapped to the mfunc1 terminal. the pci1520 drives scl at nearly 100 khz during data transfers, which is the maximum specified frequency for standard mode i 2 c. the serial eeprom must be located at address a0h. figure 3 ? 8 illustrates an example application implementing the two-wire serial bus. serial eeprom pci1520 mfunc4 mfunc1 latch scl sda v cc a1 a0 a2 figure 3 ? 8. serial eeprom application some serial device applications may include pc card power switches, zv source switches, card ejectors, or other devices that may enhance the user ? s pc card experience. the serial eeprom device and pc card power switches are discussed in the sections that follow. 3.6.2 serial-bus interface protocol the scl and sda signals are bidirectional, open-drain signals and require pullup resistors as shown in figure 3 ? 8. the pci1520, which supports up to 100-kb/s data-transfer rate, is compatible with standard mode i 2 c using 7-bit addressing. all data transfers are initiated by the serial bus master. the beginning of a data transfer is indicated by a start condition, which is signaled when the sda line transitions to low state while scl is in the high state, as illustrated
3 ? 12 in figure 3 ? 9. the end of a requested data transfer is indicated by a stop condition, which is signaled by a low-to-high transition of sda while scl is in the high state, as shown in figure 3 ? 9. data on sda must remain stable during the high state of the scl signal, as changes on the sda signal during the high state of scl are interpreted as control signals, that is, a start or a stop condition. sda scl start condition stop condition change of data allowed data line stable, data valid figure 3 ? 9. serial-bus start/stop conditions and bit transfers data is transferred serially in 8-bit bytes. the number of bytes that may be transmitted during a data transfer is unlimited; however, each byte must be completed with an acknowledge bit. an acknowledge (ack) is indicated by the receiver pulling the sda signal low, so that it remains low during the high state of the scl signal. figure 3 ? 10 illustrates the acknowledge protocol. scl from master 123 78 9 sda output by transmitter sda output by receiver figure 3 ? 10. serial-bus protocol acknowledge the pci1520 is a serial bus master; all other devices connected to the serial bus external to the pci1520 are slave devices. as the bus master, the pci1520 drives the scl clock at nearly 100 khz during bus cycles and places scl in a high-impedance state (zero frequency) during idle states. typically, the pci1520 masters byte reads and byte writes under software control. doubleword reads are performed by the serial eeprom initialization circuitry upon a pci reset and may not be generated under software control. see section 3.6.3, serial-bus eeprom application , for details on how the pci1520 automatically loads the subsystem identification and other register defaults through a serial-bus eeprom. figure 3 ? 11 illustrates a byte write. the pci1520 issues a start condition and sends the 7-bit slave device address and the command bit zero. a 0 in the r/w command bit indicates that the data transfer is a write. the slave device acknowledges if it recognizes the address. if no acknowledgment is received by the pci1520, then an appropriate status bit is set in the serial-bus control and status register (pci offset b3h, see section 4.48). the word address byte is then sent by the pci1520, and another slave acknowledgment is expected. then the pci1520 delivers the data byte msb first and expects a final acknowledgment before issuing the stop condition.
3 ? 13 sb6 b4 b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0 aa slave address word address r/w s/p = start/stop condition a = slave acknowledgement b7 b6 b4 b5 b3 b2 b1 b0 a p data byte figure 3 ? 11. serial-bus protocol ? byte write figure 3 ? 12 illustrates a byte read. the read protocol is very similar to the write protocol, except the r/w command bit must be set to 1 to indicate a read-data transfer. in addition, the pci1520 master must acknowledge reception of the read bytes from the slave transmitter. the slave transmitter drives the sda signal during read data transfers. the scl signal remains driven by the pci1520 master. sb6 b4 b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0 aa slave address word address r/w sb6 b4 b5 b3 b2 b1 b0 1 a slave address s/p = start/stop condition m = master acknowledgement b7 b6 b4 b5 b3 b2 b1 b0 m p data byte start restart r/w a = slave acknowledgement stop figure 3 ? 12. serial-bus protocol ? byte read figure 3 ? 13 illustrates eeprom interface doubleword data collection protocol. s1 1 0 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 aa slave address word address r/w data byte 2 data byte 1 data byte 0 m p m m m = master acknowledgement s/p = start/stop condition a = slave acknowledgement data byte 3 m s1 1 000001a restart r/w slave address start figure 3 ? 13. eeprom interface doubleword data collection 3.6.3 serial-bus eeprom application when the pci bus is reset and the serial-bus interface is detected, the pci1520 attempts to read the subsystem identification and other register defaults from a serial eeprom. the registers and corresponding bits that can be loaded with defaults through the eeprom are provided in table 3 ? 7.
3 ? 14 table 3 ? 7. register- and bit-loading map eeprom offset register offset register bits loaded from eeprom 00h flag 01h: load / ffh: do not load 01h pci 04h command register, bits 8, 6 ? 5, 2 ? 0 note: bits loaded per following: b8 b7 b6 b6 b5 b5 b2 b2 b1 b1 b0 b0 02h pci 40h subsystem vendor id bits 7 ? 0 bits 7 ? 0 03h pci 40h subsystem vendor id bits 15 ? 8 bit 7 ? 0 04h pci 42h subsystem id bits 7 ? 0 bits 7 ? 0 05h pci 42h subsystem id bits 15 ? 8 bits 7 ? 0 06h pci 44h pc card 16-bit i/f legacy-mode base address bits 7 ? 1 bits 7 ? 1 07h pci 44h pc card 16-bit i/f legacy-mode base address bits 15 ? 8 bits 7 ? 0 08h pci 44h pc card 16-bit i/f legacy-mode base address bit 23:16 bit 7:0 09h pci 44h pc card 16-bit i/f legacy-mode base address bits 31 ? 24 bits 7 ? 0 0ah pci 80h system control bits 7 ? 0 bits 7 ? 0 0bh pci 80h system control bits 15 ? 8 bits 7 ? 0 0ch pci 80h system control byte bits 31 ? 24 bits 7 ? 0 0dh pci 8ch multifunction routing bits 7 ? 0 bits 7 ? 0 0eh pci 8ch multifunction routing bits 15 ? 8 bits 7 ? 0 0fh pci 8ch multifunction routing bits 23 ? 16 bits 7 ? 0 10h pci 8ch multifunction routing bits 27 ? 24 bits 3 ? 0 11h pci 90h retry status bits 7, 6 bits 7, 6 12h pci 91h card control bits 7, 5 bits 7, 6 13h pci 92h device control bits 6, 3 ? 0 bits 6, 3 ? 0 14h pci 93h diagnostic bits 7, 4 ? 0 bits 7, 4 ? 0 15h pci a2h power management capabilities bit 15 bit 7 16h exca 00h exca identification and revision bits 7 ? 0 bits 7 ? 0 17h cb socket + 0ch (function 0) function 0 socket force event, bit 27 bit 3 18h cb socket + 0ch (function 1) function 1 socket force event, bit 27 bit 3 this format must be followed for the pci1520 to load initializations from a serial eeprom. all bit fields must be considered when programming the eeprom. the serial eeprom is addressed at slave address 1010 000b by the pci1520. all hardware address bits for the eeprom should be tied to the appropriate level to achieve this address. the serial eeprom chip in the sample application circuit (figure 3 ? 8) assumes the 1010b high-address nibble. the lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to gnd. 3.6.4 accessing serial-bus devices through software the pci1520 provides a programming mechanism to control serial bus devices through software. the programming is accomplished through a doubleword of pci configuration space at offset b0h. table 3 ? 8 lists the registers used to program a serial-bus device through software.
3 ? 15 table 3 ? 8. pci1520 registers used to program serial-bus devices pci offset register name description b0h serial-bus data contains the data byte to send on write commands or the received data byte on read commands. b1h serial-bus index the content of this register is sent as the word address on byte writes or reads. this register is not used in the quick command protocol. b2h serial-bus slave address write transactions to this register initiate a serial-bus transaction. the slave device address and the r/w command selector are programmed through this register. b3h serial-bus control and status read data valid, general busy, and general error status are communicated through this register. in addition, the protocol-select bit is programmed through this register. 3.7 programmable interrupt subsystem interrupts provide a way for i/o devices to let the microprocessor know that they require servicing. the dynamic nature of pc cards and the abundance of pc card i/o applications require substantial interrupt support from the pci1520. the pci1520 provides several interrupt signaling schemes to accommodate the needs of a variety of platforms. the different mechanisms for dealing with interrupts in this device are based on various specifications and industry standards. the exca register set provides interrupt control for some 16-bit pc card functions, and the cardbus socket register set provides interrupt control for the cardbus pc card functions. the pci1520 is, therefore, backward compatible with existing interrupt control register definitions, and new registers have been defined where required. the pci1520 detects pc card interrupts and events at the pc card interface and notifies the host controller using one of several interrupt signaling protocols. to simplify the discussion of interrupts in the pci1520, pc card interrupts are classified either as card status change (csc) or as functional interrupts. the method by which any type of pci1520 interrupt is communicated to the host interrupt controller varies from system to system. the pci1520 offers system designers the choice of using parallel pci interrupt signaling, parallel isa-type irq interrupt signaling, or the irqser serialized isa and/or pci interrupt protocol. it is possible to use the parallel pci interrupts in combination with either parallel irqs or serialized irqs, as detailed in the sections that follow. all interrupt signaling is provided through the seven multifunction terminals, mfunc0 ? mfunc6. 3.7.1 pc card functional and card status change interrupts pc card functional interrupts are defined as requests from a pc card application for interrupt service and are indicated by asserting specially-defined signals on the pc card interface. functional interrupts are generated by 16-bit i/o pc cards and by cardbus pc cards. card status change (csc)-type interrupts are defined as events at the pc card interface that are detected by the pci1520 and may warrant notification of host card and socket services software for service. csc events include both card insertion and removal from pc card sockets, as well as transitions of certain pc card signals. table 3 ? 9 summarizes the sources of pc card interrupts and the type of card associated with them. csc and functional interrupt sources are dependent on the type of card inserted in the pc card socket. the three types of cards that can be inserted into any pc card socket are: ? 16-bit memory card ? 16-bit i/o card ? cardbus cards
3 ? 16 table 3 ? 9. interrupt mask and flag registers card type event mask flag 16 bit memory battery conditions (bvd1, bvd2) exca offset 05h/45h/805h bits 1 and 0 exca offset 04h/44h/804h bits 1 and 0 16-bit memory wait states (ready) exca offset 05h/45h/805h bit 2 exca offset 04h/44h/804h bit 2 16 bit i/o change in card status (stschg ) exca offset 05h/45h/805h bit 0 exca offset 04h/44h/804h bit 0 16-bit i/o interrupt request (ireq ) always enabled pci configuration offset 91h bit 0 all 16-bit pc cards power cycle complete exca offset 05h/45h/805h bit 3 exca offset 04h/44h/804h bit 3 change in card status (cstschg) socket mask bit 0 socket event bit 0 cardbus interrupt request (cint ) always enabled pci configuration offset 91h bit 0 cardbus power cycle complete socket mask bit 3 socket event bit 3 card insertion or removal socket mask bits 2 and 1 socket event bits 2 and 1 functional interrupt events are valid only for 16-bit i/o and cardbus cards; that is, the functional interrupts are not valid for 16-bit memory cards. furthermore, card insertion and removal-type csc interrupts are independent of the card type. table 3 ? 10. pc card interrupt events and description card type event type signal description batter y conditions csc bvd1(stschg )//cstschg a transition on bvd1 indicates a change in the pc card battery conditions. 16-bit memory battery conditions (bvd1, bvd2) csc bvd2(spkr )//caudio a transition on bvd2 indicates a change in the pc card battery conditions. memory wait states (ready) csc ready(ireq )//cint a transition on ready indicates a change in the ability of the memory pc card to accept or provide data. 16 bit i/o change in card status (stschg ) csc bvd1(stschg )//cstschg the assertion of stschg indicates a status change on the pc card. 16-bit i/o interrupt request (ireq ) functional ready(ireq )//cint the assertion of ireq indicates an interrupt request from the pc card. cardbus change in card status (cstschg) csc bvd1(stschg )//cstschg the assertion of cstschg indicates a status change on the pc card. cardbus interrupt request (cint ) functional ready(ireq )//cint the assertion of cint indicates an interrupt request from the pc card. all pc cards card insertion or removal csc cd1 //ccd1 , cd2 //ccd2 a transition on either cd1 //ccd1 or cd2 //ccd2 indicates an insertion or removal of a 16-bit or cardbus pc card. all pc cards power cycle complete csc n/a an interrupt is generated when a pc card power-up cycle has completed. the naming convention for pc card signals describes the function for 16-bit memory, i/o cards, and cardbus. for example, ready(ireq )//cint includes ready for 16-bit memory cards, ireq for 16-bit i/o cards, and cint for cardbus cards. the 16-bit memory card signal name is first, with the i/o card signal name second, enclosed in parentheses. the cardbus signal name follows after a double slash (//). the 1997 pc card standard describes the power-up sequence that must be followed by the pci1520 when an insertion event occurs and the host requests that the socket v cc and v pp be powered. upon completion of this power-up sequence, the pci1520 interrupt scheme can be used to notify the host system (see table 3 ? 10), denoted by the power cycle complete event. this interrupt source is considered a pci1520 internal event, because it depends on the completion of applying power to the socket rather than on a signal change at the pc card interface.
3 ? 17 3.7.2 interrupt masks and flags host software may individually mask (or disable) most of the potential interrupt sources listed in table 3 ? 10 by setting the appropriate bits in the pci1520. by individually masking the interrupt sources listed, software can control those events that cause a pci1520 interrupt. host software has some control over the system interrupt the pci1520 asserts by programming the appropriate routing registers. the pci1520 allows host software to route pc card csc and pc card functional interrupts to separate system interrupts. interrupt routing somewhat specific to the interrupt signaling method used is discussed in more detail in the following sections. when an interrupt is signaled by the pci1520, the interrupt service routine must determine which of the events listed in table 3 ? 9 caused the interrupt. internal registers in the pci1520 provide flags that report the source of an interrupt. by reading these status bits, the interrupt service routine can determine the action to be taken. table 3 ? 9 details the registers and bits associated with masking and reporting potential interrupts. all interrupts can be masked except the functional pc card interrupts, and an interrupt status flag is available for all types of interrupts. notice that there is not a mask bit to stop the pci1520 from passing pc card functional interrupts through to the appropriate interrupt scheme. these interrupts are not valid until the card is properly powered, and there should never be a card interrupt that does not require service after proper initialization. table 3 ? 9 lists the various methods of clearing the interrupt flag bits. the flag bits in the exca registers (16-bit pc card-related interrupt flags) can be cleared using two different methods. one method is an explicit write of 1 to the flag bit to clear and the other is by reading the flag bit register. the selection of flag bit clearing methods is made by bit 2 (ifcmode) in the exca global control register (exca offset 1eh/5eh/81eh, see section 5.20), and defaults to the flag-cleared-on-read method. the cardbus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket event register (see section 6.1). although some of the functionality is shared between the cardbus registers and the exca registers, software should not program the chip through both register sets when a cardbus card is functioning. 3.7.3 using parallel irq interrupts the seven multifunction terminals, mfunc6 ? mfunc0, implemented in the pci1520 can be routed to obtain a subset of the isa irqs. the irq choices provide ultimate flexibility in pc card host interruptions. to use the parallel isa-type irq interrupt signaling, software must program the device control register (pci offset 92h, see section 4.33), to select the parallel irq signaling scheme. see section 4.30, multifunction routing register , for details on configuring the multifunction terminals. a system using parallel irqs requires (at a minimum) one pci terminal, inta , to signal csc events. this requirement is dictated by certain card and socket-services software. the inta requirement calls for routing the mfunc0 terminal for inta signaling. the intrtie bit is used, in this case, to route socket b interrupt events to inta . this leaves (at a maximum) six different irqs to support legacy 16-bit pc card functions. as an example, suppose the six irqs used by legacy pc card applications are irq3, irq4, irq5, irq10, irq11, and irq15. the multifunction routing register must be programmed to a value of 0fba 5432h. this value routes the mfunc0 terminal to inta signaling and routes the remaining terminals as illustrated in figure 3 ? 14. not shown is that inta must also be routed to the programmable interrupt controller (pic), or to some circuitry that provides parallel pci interrupts to the host.
3 ? 18 pci1520 pic mfunc1 mfunc2 mfunc3 mfunc4 mfunc5 mfunc6 irq3 irq4 irq5 irq10 irq11 irq15 figure 3 ? 14. irq implementation power-on software is responsible for programming the multifunction routing register to reflect the irq configuration of a system implementing the pci1520. the multifunction routing register is shared between the two pci1520 functions, and only one write to function 0 or 1 is necessary to configure the mfunc6 ? mfunc0 signals. writing to function 0 only is recommended. see section 4.30, multifunction routing register , for details on configuring the multifunction terminals. the parallel isa-type irq signaling from the mfunc6 ? mfunc0 terminals is compatible with the input signal requirements of the 8259 pic. the parallel irq option is provided for system designs that require legacy isa irqs. design constraints may demand more mfunc6 ? mfunc0 irq terminals than the pci1520 makes available. 3.7.4 using parallel pci interrupts parallel pci interrupts are available when exclusively in parallel pci interrupt/parallel isa irq signaling mode, and when only irqs are serialized with the irqser protocol. both inta and intb can be routed to mfunc terminals (mfunc0 and mfunc1). however, interrupts of both socket functions can be routed to inta (mfunc0) if bit 29 (intrtie) is set in the system control register (pci offset 80h, see section 4.29). the intrtie bit affects the read-only value provided through accesses to the interrupt pin register (pci offset 3dh, see section 4.24). when the intrtie bit is set, both functions return a value of 01h on reads from the interrupt pin register for both parallel and serial pci interrupts. table 3 ? 11 summarizes the interrupt signaling modes. table 3 ? 11. interrupt pin register cross reference intrtie bit intpin intrtie bit function 0 function 1 0 01h 02h 1 01h 01h 3.7.5 using serialized irqser interrupts the serialized interrupt protocol implemented in the pci1520 uses a single terminal to communicate all interrupt status information to the host controller. the protocol defines a serial packet consisting of a start cycle, multiple interrupt indication cycles, and a stop cycle. all data in the packet is synchronous with the pci clock. the packet data describes 16 parallel isa irq signals and the optional 4 pci interrupts inta , intb , intc , and intd . for details on the irqser protocol, refer to the document serialized irq support for pci systems . 3.7.6 smi support in the pci1520 the pci1520 provides a mechanism for interrupting the system when power changes have been made to the pc card socket interfaces. the interrupt mechanism is designed to fit into a system maintenance interrupt (smi) scheme. smi interrupts are generated by the pci1520, when enabled, after a write cycle to either the socket control register (cb offset 10h, see section 6.5) of the cardbus register set, or the exca power control register (exca offset 02h/42h/802h, see section 5.3) causes a power cycle change sequence to be sent on the power switch interface. the smi control is programmed through three bits in the system control register (pci offset 80h, see section 4.29). these bits are smiroute (bit 26), smistatus (bit 25), and smienb (bit 24). table 3 ? 12 describes the smi control bits function.
3 ? 19 table 3 ? 12. smi control bit name function smiroute this shared bit controls whether the smi interrupts are sent as a csc interrupt or as irq2. smistat this socket dependent bit is set when an smi interrupt is pending. this status flag is cleared by writing back a 1. smienb when set, smi interrupt generation is enabled. this bit is shared by functions 0 and 1. if csc smi interrupts are selected, then the smi interrupt is sent as the csc on a per-socket basis. the csc interrupt can be either level or edge mode, depending upon the cscmode bit in the exca global control register (exca offset 1eh/5eh/81eh, see section 5.20). if irq2 is selected by smiroute, then the irqser signaling protocol supports smi signaling in the irq2 irq/data slot. in a parallel isa irq system, the support for an active low irq2 is provided only if irq2 is routed to either mfunc3 or mfunc6 through the multifunction routing register (pci offset 8ch, see section 4.30). 3.8 power management overview in addition to the low-power cmos technology process used for the pci1520, various features are designed into the device to allow implementation of popular power-saving techniques. these features and techniques are discussed in this section. 3.8.1 integrated low-dropout voltage regulator (ldo-vr) the pci1520 requires 2.5-v core voltage. the core power can be supplied by the pci1520 itself using the internal ldo-vr . the core power can alternatively be supplied by an external power supply through the vr_port terminal. table 3 ? 13 lists the requirements for both the internal core power supply and the external core power supply. table 3 ? 13. requirements for internal/external 2.5-v core power supply supply v cc vr_en vr_port note internal 3.3 v gnd 2.5-v output internal 2.5-v ldo-vr is enabled. a 1.0 f bypass capacitor is required on the vr_port terminal for decoupling. this output is not for external use. external 3.3 v v cc 2.5-v input internal 2.5-v ldo-vr is disabled. an external 2.5-v power supply, of minimum 50-ma capacity, is required. a 0.1 f bypass capacitor on the vr_port terminal is required. 3.8.2 clock run protocol the pci clkrun feature is the primary method of power management on the pci interface of the pci1520. clkrun signaling is provided through the mfunc6 terminal. since some chip sets do not implement clkrun , this is not always available to the system designer, and alternate power-saving features are provided. for details on the clkrun protocol see the pci mobile design guide . the pci1520 does not permit the central resource to stop the pci clock under any of the following conditions: ? bit 1 (keepclk) in the system control register (pci offset 80h, see section 4.29) is set. ? the 16-bit pc card- resource manager is busy. ? the pci1520 cardbus master state machine is busy. a cycle may be in progress on cardbus. ? the pci1520 master is busy. there may be posted data from cardbus to pci in the pci1520. ? interrupts are pending. ? the cardbus cclk for either socket has not been stopped by the pci1520 cclkrun manager.
3 ? 20 the pci1520 restarts the pci clock using the clkrun protocol under any of the following conditions: ? a 16-bit pc card ireq or a cardbus cint has been asserted by either card. ? a cardbus cbwake (cstschg) or 16-bit pc card stschg /ri event occurs in either socket. ? a cardbus attempts to start the cclk using cclkrun . ? a cardbus card arbitrates for the cardbus bus using creq . 3.8.3 cardbus pc card power management the pci1520 implements its own card power-management engine that can turn off the cclk to a socket when there is no activity to the cardbus pc card. the pci clock-run protocol is followed on the cardbus cclkrun interface to control this clock management. 3.8.4 16-bit pc card power management the coe bit (bit 7) of the exca power control register (exca offset 02h/42h/802h, see section 5.3) and pwrdwn bit (bit 0) of the exca global control register (exca offset 1eh/5eh/81eh, see section 5.20) bits are provided for 16-bit pc card power management. the coe bit places the card interface in a high-impedance state to save power. the power savings when using this feature are minimal. the coe bit resets the pc card when used, and the pwrdwn bit does not. furthermore, the pwrdwn bit is an automatic coe, that is, the pwrdwn performs the coe function when there is no card activity. note: the 16-bit pc card must implement the proper pullup resistors for the coe and pwrdwn modes. 3.8.5 suspend mode the suspend signal, provided for backward compatibility, gates the prst (pci reset) signal and the grst (global reset) signal from the pci1520. besides gating prst and grst , suspend also gates pclk inside the pci1520 in order to minimize power consumption. gating pclk does not create any issues with respect to the power switch interface in the pci1520. this is because the pci1520 does not depend on the pci clock to clock the power switch interface. there are two methods to clock the power switch interface in the pci1520: ? use an external clock to the pci1520 clock terminal ? use the internal oscillator it should also be noted that asynchronous signals, such as card status change interrupts and ri_out , can be passed to the host system without a pci clock. however, if card status change interrupts are routed over the serial interrupt stream, then the pci clock must be restarted in order to pass the interrupt, because neither the internal oscillator nor an external clock is routed to the serial-interrupt state machine. figure 3 ? 15 is a signal diagram of the suspend function.
3 ? 21 reset gnt suspend pclk resetin suspendin pclkin external terminals internal signals figure 3 ? 15. signal diagram of suspend function 3.8.6 requirements for suspend mode the suspend mode prevents the clearing of all register contents on the assertion of reset (prst or grst ) which would require the reconfiguration of the pci1520 by software. asserting the suspend signal places the pci outputs of the controller in a high-impedance state and gates the pclk signal internally to the controller unless a pci transaction is currently in process (gnt is asserted). it is important that the pci bus not be parked on the pci1520 when suspend is asserted because the outputs are in a high-impedance state. the gpios, mfunc signals, and ri_out signal are all active during suspend , unless they are disabled in the appropriate pci1520 registers. 3.8.7 ring indicate the ri_out output is an important feature in power management, allowing a system to go into a suspended mode and wake up on modem rings and other card events. ti-designed flexibility permits this signal to fit wide platform requirements. ri_out on the pci1520 can be asserted under any of the following conditions: ? a 16-bit pc card modem in a powered socket asserts ri to indicate to the system the presence of an incoming call. ? a powered down cardbus card asserts cstschg (cbwake) requesting system and interface wake up. ? a powered cardbus card asserts cstschg from the insertion/removal of cards or change in battery voltage levels. figure 3 ? 16 shows various enable bits for the pci1520 ri_out function; however, it does not show the masking of csc events. see table 3 ? 9 for a detailed description of csc interrupt masks and flags.
3 ? 22 card i/f pc card socket 0 csc cstsmask rienb ri_out ri_out function ringen cdresume csc ri card i/f pc card socket 1 csc cstsmask ringen cdresume csc ri figure 3 ? 16. ri_out functional diagram ri from the 16-bit pc card interface is masked by bit 7 (ringen) in the exca interrupt and general control register (exca offset 03h/43h/803h, see section 5.4). this is programmed on a per-socket basis and is only applicable when a 16-bit card is powered in the socket. the cbwake signaling to ri_out is enabled through the same mask as the csc event for cstschg. the mask bit (bit 0, cstsmask) is programmed through the socket mask register (cb offset 04h, see section 6.2) in the cardbus socket registers. ri_out can be routed through any of three different pins, ri_out /pme , mfunc2, or mfunc4. the ri_out function is enabled by setting rienb in the card control register (pci offset 91h, see section 4.32). the pme function is enabled by setting pmeen in the power management control/status register (pci offset a4h, see section 4.38). when rimux in the system control register (pci offset 80h, see section 4.29) is set to 0, both the ri_out function and the pme function are routed to the ri_out /pme terminal. if both functions are enabled and rimux is set to 0, the ri_out /pme terminal becomes ri_out only and pme assertions will never be seen. therefore, in a system using both the ri_out function and the pme function, rimux must be set to 1 and ri_out must be routed to either mfunc2 or mfunc4. 3.8.8 pci power management the pci bus power management interface specification for pci to cardbus bridges establishes the infrastructure required to let the operating system control the power of pci functions. this is done by defining a standard pci interface and operations to manage the power of pci functions on the bus. the pci bus and the pci functions can be assigned one of seven power-management states, resulting in varying levels of power savings. the seven power-management states of pci functions are: ? d0-uninitialized ? before device configuration, device not fully functional ? d0-active ? fully functional state ? d1 ? low-power state ? d2 ? low-power state ? d3 hot ? low-power state. transition state before d3 cold ? d3 cold ? pme signal-generation capable. main power is removed and vaux is available. ? d3 off ? no power and completely nonfunctional
3 ? 23 note 1: in the d0-uninitialized state, the pci1520 does not generate pme and/or interrupts. when the io_en and mem_en bits (bits 0 and 1) of the command register (pci offset 04h, see section 4.4) are both set, the pci1520 switches the state to d0-active. transit ion from d3 cold to the d0-uninitialized state happens at the deassertion of prst . the assertion of grst forces the controller to the d0-uninitialized state immediately. note 2: the pwr_state bits (bits 0 ? 1) of the power-management control/status register (pci offset a4h, see section 4.38) only code for four power states, d0, d1, d2, and d3 hot . the differences between the three d3 states is invisible to the software because the controller is not accessible in the d3 cold or d3 off state. similarly, bus power states of the pci bus are b0 ? b3. the bus power states b0 ? b3 are derived from the device power state of the originating bridge device. for the operating system (os) to manage the device power states on the pci bus, the pci function should support four power-management operations. these operations are: ? capabilities reporting ? power status reporting ? setting the power state ? system wake up the os identifies the capabilities of the pci function by traversing the new capabilities list. the presence of capabilities in addition to the standard pci capabilities is indicated by a 1 in bit 4 (caplist) of the status register (pci offset 06h, see section 4.5). the capabilities pointer provides access to the first item in the linked list of capabilities. for the pci1520, a cardbus bridge with pci configuration space header type 2, the capabilities pointer is mapped to an offset of 14h. the first byte of each capability register block is required to be a unique id of that capability. pci power management has been assigned an id of 01h. the next byte is a pointer to the next pointer item in the list of capabilities. if there are no more items in the list, then the next item pointer must be set to 0. the registers following the next item pointer are specific to the capability of the function. the pci power-management capability implements the register block outlined in table 3 ? 14. table 3 ? 14. power-management registers register name offset power-management capabilities next item pointer capability id a0h data power-management control/ status register bridge support extensions power-management control/status (csr) a4h the power management capabilities register (pci offset a2h, see section 4.37) provides information on the capabilities of the function related to power management. the power-management control/status register (pci offset a4h, see section 4.38) enables control of power-management states and enables/monitors power-management events. the data register is an optional register that can provide dynamic data. for more information on pci power management, see the pci bus power management interface specification for pci to cardbus bridges . 3.8.9 cardbus bridge power management the pci bus power management interface specification for pci to cardbus bridges was approved by pcmcia in december of 1997. this specification follows the device and bus state definitions provided in the pci bus power management interface specification published by the pci special interest group (sig). the main issue addressed in the pci bus power management interface specification for pci to cardbus bridges is wake-up from d3 hot or d3 cold without losing wake-up context (also called pme context).
3 ? 24 the specific issues addressed by the pci bus power management interface specification for pci to cardbus bridges for d3 wake up are as follows: ? preservation of device context. the specification states that a reset must occur during the transition from d3 to d0. some method to preserve wake-up context must be implemented so that the reset does not clear the pme context registers. ? power source in d3 cold if wake-up support is required from this state. the texas instruments pci1520 addresses these d3 wake-up issues in the following manner: ? two resets are provided to handle preservation of pme context bits: ? global reset (grst ) is used only on the initial boot up of the system after power up. it places the pci1520 in its default state and requires bios to configure the device before becoming fully functional. ? pci reset (prst ) has dual functionality based on whether pme is enabled or not. if pme is enabled, then pme context is preserved. if pme is not enabled, then prst acts the same as a normal pci reset. please see the master list of pme context bits in section 3.8.11. ? power source in d3 cold if wake-up support is required from this state. since v cc is removed in d3 cold , an auxiliary power source must be supplied to the pci1520 v cc terminals. consult the pci14xx implementation guide for d3 wake-up or the pci power management interface specification for pci to cardbus bridges for further information. 3.8.10 acpi support the advanced configuration and power interface (acpi) specification provides a mechanism that allows unique pieces of hardware to be described to the acpi driver. the pci1520 offers a generic interface that is compliant with acpi design rules. two doublewords of general-purpose acpi programming bits reside in pci1520 pci configuration space at offset a8h. the programming model is broken into status and control functions. in compliance with acpi, the top level event status and enable bits reside in the general-purpose event status register (pci offset a8h, see section 4.41) and general-purpose event enable register (pci offset aah, see section 4.42). the status and enable bits are implemented as defined by acpi and illustrated in figure 3 ? 17. event output event input enable bit status bit figure 3 ? 17. block diagram of a status/enable cell the status and enable bits generate an event that allows the acpi driver to call a control method associated with the pending status bit. the control method can then control the hardware by manipulating the hardware control bits or by investigating child status bits and calling their respective control methods. a hierarchical implementation would be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report events. for more information of acpi, see the advanced configuration and power interface (acpi) specification.
3 ? 25 3.8.11 master list of pme context bits and global reset-only bits if the pme enable bit (bit 8) of the power-management control/status register (pci offset a4h, see section 4.38) is asserted, then the assertion of prst will not clear the following pme context bits. if the pme enable bit is not asserted, then the pme context bits are cleared with prst . the pme context bits are: ? bridge control register (pci offset 3eh): bit 6 ? system control register (pci offset 80h): bits 10, 9, 8 ? power-management control/status register (pci offset a4h): bits 15, 8 ? exca power control register (exca offset 802h): bits 7, 5 ? , 4 ? 3, 1 ? 0 ( ? 82365sl mode only) ? exca interrupt and general control register (exca offset 803h): bits 6 ? 5 ? exca card status change register (exca offset 804h): bits 11 ? 8, 3 ? 0 ? exca card status-change-interrupt configuration register (exca offset 805h): bits 3 ? 0 ? cardbus socket event register (cardbus offset 00h): bits 3 ? 0 ? cardbus socket mask register (cardbus offset 04h): bits 3 ? 0 ? cardbus socket present state register (cardbus offset 08h): bits 13 ? 7, 5 ? 1 ? cardbus socket control register (cardbus offset 10h): bits 6 ? 4, 2 ? 0 global reset places all registers in their default state regardless of the state of the pme enable bit. the grst signal is gated only by the suspend signal. this means that assertion of suspend blocks the grst signal internally, thus preserving all register contents. the registers cleared only by grst are: ? status register (pci offset 06h): bits 15 ? 11, 8 ? secondary status register (pci offset 16h): bits 15 ? 11, 8 ? interrupt pin register (pci offset 3dh): bits 1,0 (function 1 only) ? subsystem vendor id register (pci offset 40h): bits 15 ? 0 ? subsystem id register (pci offset 42h): bits 15 ? 0 ? pc card 16-bit legacy mode base address register (pci offset 44h): bits 31 ? 1 ? system control register (pci offset 80h): bits 31 ? 29, 27 ? 13, 11, 6 ? 0 ? multifunction routing register (pci offset 8ch): bits 27 ? 0 ? retry status register (pci offset 90h): bits 7 ? 5, 3, 1 ? card control register (pci offset 91h): bits 7 ? 5, 2 ? 0 ? device control register (pci offset 92h): bits 7 ? 5, 3 ? 0 ? diagnostic register (pci offset 93h): bits 7 ? 0 ? power management capabilities register (pci offset a2h): bit 15 ? general-purpose event status register (pci offset a8h): bits 15 ? 14 ? general-purpose event enable register (pci offset aah): bits 15 ? 14, 11, 8, 4 ? 0 ? general-purpose output (pci offset aeh): bits 4 ? 0 ? serial bus data (pci offset b0h): bits 7 ? 0 ? serial bus index (pci offset b1h): bits 7 ? 0 ? serial bus slave address register (pci offset b2h): bits 7 ? 0 ? serial bus control and status register (pci offset b3h): bits 7, 5 ? 0 ? exca identification and revision register (exca offset 00h): bits 7 ? 0 ? exca global control register (exca offset 1eh): bits 2 ? 0 ? socket present state register (cardbus offset 08h): bit 29 ? socket power management register (cardbus offset 20h): bits 25 ? 24
4 ? 1 4 pc card controller programming model this section describes the pci1520 pci configuration registers that make up the 256-byte pci configuration header for each pci1520 function. as noted, some bits are global in nature and are accessed only through function 0. 4.1 pci configuration registers (functions 0 and 1) the pci1520 is a multifunction pci device, and the pc card controller is integrated as pci functions 0 and 1. the configuration header is compliant with the pci local bus specification as a cardbus bridge header and is pc 99 compliant as well. table 4 ? 1 shows the pci configuration header, which includes both the predefined portion of the configuration space and the user-definable registers. table 4 ? 1. pci configuration registers (functions 0 and 1) register name offset device id vendor id 00h status command 04h class code revision id 08h bist header type latency timer cache line size 0ch cardbus socket/exca base address 10h secondary status reserved capability pointer 14h cardbus latency timer subordinate bus number cardbus bus number pci bus number 18h cardbus memory base register 0 1ch cardbus memory limit register 0 20h cardbus memory base register 1 24h cardbus memory limit register 1 28h cardbus i/o base register 0 2ch cardbus i/o limit register 0 30h cardbus i/o base register 1 34h cardbus i/o limit register 1 38h bridge control interrupt pin interrupt line 3ch subsystem id subsystem vendor id 40h pc card 16-bit i/f legacy-mode base address 44h reserved 48h ? 7ch system control 80h reserved 84h ? 88h multifunction routing 8ch diagnostic device control card control retry status 90h reserved 94h ? 9ch power-management capabilities next-item pointer capability id a0h power-management data power-management control/status bridge support extensions power-management control/status a4h general-purpose event enable general-purpose event status a8h general-purpose output general-purpose input ach serial bus control/status serial bus slave address serial bus index serial bus data b0h reserved b4h ? fch
4 ? 2 a bit description table, typically included when a register contains bits of more than one type or purpose, indicates bit field names, which appear in the signal column; a detailed field description, which appears in the function column; and field access tags, which appear in the type column of the bit description table. table 4 ? 2 describes the field access tags. table 4 ? 2. bit field access tag descriptions access tag name meaning r read field may be read by software. w write field may be written by software to any value. s set field may be set by a write of 1. writes of 0 have no effect. c clear field may be cleared by a write of 1. writes of 0 have no effect. u update field may be autonomously updated by the pci1520. 4.2 vendor id register this 16-bit register contains a value allocated by the pci special interest group (sig) and identifies the manufacturer of the pci device. the vendor id assigned to ti is 104ch. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vendor id type r r r r r r r r r r r r r r r r default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 register: vendor id offset: 00h (functions 0, 1) type: read-only default: 104ch 4.3 device id register this 16-bit register contains a value assigned to the pci1520 by ti. the device identification for the pci1520 is ac55h. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name device id type r r r r r r r r r r r r r r r r default 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 1 register: device id offset: 02h (functions 0, 1) type: read-only default: ac55h
4 ? 3 4.4 command register the command register provides control over the pci1520 interface to the pci bus. all bit functions adhere to the definitions in pci local bus specification . none of the bit functions in this register is shared between the two pci1520 pci functions. two command registers exist in the pci1520, one for each function. software must manipulate the two pci1520 functions as separate entities when enabling functionality through the command register. the serr_en and perr_en enable bits in this register are internally wired-or between the two functions, and these control bits appear separately according to their software function. see table 4 ? 3 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name command type r r r r r r r rw r rw rw r r rw rw rw default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: command offset: 04h type: read-only, read/write default: 0000h table 4 ? 3. command register description bit signal type function 15 ? 10 rsvd r reserved. bits 15 ? 10 return 0s when read. 9 fbb_en r fast back-to-back enable. the pci1520 does not generate fast back-to-back transactions; therefore, bit 9 returns 0 when read. 8 serr_en rw system error (serr ) enable. bit 8 controls the enable for the serr driver on the pci interface. serr can be asserted after detecting an address parity error on the pci bus. both bits 8 and 6 must be set for the pci1520 to report address parity errors. 0 = disable serr output driver (default) 1 = enable serr output driver 7 step_en r address/data stepping control. the pci1520 does not support address/data stepping; therefore, bit 7 is hardwired to 0. 6 perr_en rw parity error response enable. bit 6 controls the pci1520 response to parity errors through perr . data parity errors are indicated by asserting perr , whereas address parity errors are indicated by asserting serr . 0 = pci1520 ignores detected parity error (default) 1 = pci1520 responds to detected parity errors 5 vga_en rw vga palette snoop. bit 5 controls how pci devices handle accesses to video graphics array (vga) palette registers. 4 mwi_en r memory write-and-invalidate enable. bit 4 controls whether a pci initiator device can generate memory write-and-invalidate commands. the pci1520 controller does not support memory write-and-invalidate commands, but uses memory write commands instead; therefore, this bit is hardwired to 0. 3 special r special cycles. bit 3 controls whether or not a pci device ignores pci special cycles. the pci1520 does not respond to special cycle operations; therefore, this bit is hardwired to 0. 2 mast_en rw bus master control. bit 2 controls whether or not the pci1520 can act as a pci bus initiator (master). the pci1520 can take control of the pci bus only when this bit is set. 0 = disables the pci1520 from generating pci bus accesses (default) 1 = enables the pci1520 to generate pci bus accesses 1 mem_en rw memory space enable. bit 1 controls whether or not the pci1520 can claim cycles in pci memory space. 0 = disables the pci1520 from responding to memory space accesses (default) 1 = enables the pci1520 to respond to memory space accesses 0 io_en rw i/o space control. bit 0 controls whether or not the pci1520 can claim cycles in pci i/o space. 0 = disables the pci1520 from responding to i/o space accesses (default) 1 = enables the pci1520 to respond to i/o space accesses
4 ? 4 4.5 status register the status register provides device information to the host system. bits in this register can be read normally. a bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. all bit functions adhere to the definitions in the pci local bus specification . pci bus status is shown through each function. see table 4 ? 4 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name status type rc rc rc rc rc r r rc r r r r r r r r default 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 register: status offset: 06h (functions 0, 1) type: read-only, read/clear default: 0210h table 4 ? 4. status register description bit signal type function 15 par_err rc detected parity error. bit 15 is set when a parity error is detected (either address or data). 14 sys_err rc signaled system error. bit 14 is set when serr is enabled and the pci1520 signals a system error to the host. 13 mabort rc received master abort. bit 13 is set when a cycle initiated by the pci1520 on the pci bus is terminated by a master abort. 12 tabt_rec rc received target abort. bit 12 is set when a cycle initiated by the pci1520 on the pci bus is terminated by a target abort. 11 tabt_sig rc signaled target abort. bit 11 is set by the pci1520 when it terminates a transaction on the pci bus with a target abort. 10 ? 9 pci_speed r devsel timing. these bits encode the timing of devsel and are hardwired 01b, indicating that the pci1520 asserts pci_speed at a medium speed on nonconfiguration cycle accesses. 8 datapar rc data parity error detected. 0 = the conditions for setting bit 8 have not been met. 1 = a data parity error occurred, and the following conditions were met: a. perr was asserted by any pci device including the pci1520. b. the pci1520 was the bus master during the data parity error. c. the parity error response bit is set in the command register (pci offset 04h, see section 4.4). 7 fbb_cap r fast back-to-back capable. the pci1520 cannot accept fast back-to-back transactions; therefore, bit 7 is hardwired to 0. 6 udf r user-definable feature support. the pci1520 does not support the user-definable features; therefore, bit 6 is hardwired to 0. 5 66mhz r 66-mhz capable. the pci1520 operates at a maximum pclk frequency of 33 mhz; therefore, bit 5 is hardwired to 0. 4 caplist r capabilities list. bit 4 returns 1 when read. this bit indicates that capabilities in addition to standard pci capabilities are implemented. the linked list of pci power-management capabilities is implemented in this function. 3 ? 0 rsvd r reserved. bits 3 ? 0 return 0s when read.
4 ? 5 4.6 revision id register the revision id register indicates the silicon revision of the pci1520. bit 7 6 5 4 3 2 1 0 name revision id type r r r r r r r r default 0 0 0 0 0 0 0 1 register: revision id offset: 08h (functions 0, 1) type: read-only default: 01h 4.7 pci class code register the class code register recognizes pci1520 functions 0 and 1 as a bridge device (06h) and a cardbus bridge device (07h), with a 00h programming interface. bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pci class code base class subclass programming interface type r r r r r r r r r r r r r r r r r r r r r r r r default 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 register: pci class code offset: 09h (functions 0, 1) type: read-only default: 06 0700h 4.8 cache line size register the cache line size register is programmed by host software to indicate the system cache line size. bit 7 6 5 4 3 2 1 0 name cache line size type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: cache line size offset: 0ch (functions 0, 1) type: read/write default: 00h
4 ? 6 4.9 latency timer register the latency timer register specifies the latency time for the pci1520 in units of pci clock cycles. when the pci1520 is a pci bus initiator and asserts frame , the latency timer begins counting from zero. if the latency timer expires before the pci1520 transaction has terminated, then the pci1520 terminates the transaction when its gnt is deasserted. this register is separate for each of the two pci1520 functions. this allows platforms to prioritize use of the pci bus by the two pci1520 functions. bit 7 6 5 4 3 2 1 0 name latency timer type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: latency timer offset: 0dh type: read/write default: 00h 4.10 header type register this register returns 82h when read, indicating that the pci1520 function 0 and 1 configuration spaces adhere to the cardbus bridge pci header. the cardbus bridge pci header ranges from pci register 000h to 7fh, and 80h to ffh is user-definable extension registers. bit 7 6 5 4 3 2 1 0 name header type type r r r r r r r r default 1 0 0 0 0 0 1 0 register: header type offset: 0eh (functions 0, 1) type: read/write default: 82h 4.11 bist register because the pci1520 does not support a built-in self-test (bist), this register returns the value of 00h when read. bit 7 6 5 4 3 2 1 0 name bist type r r r r r r r r default 0 0 0 0 0 0 0 0 register: bist offset: 0fh (functions 0, 1) type: read-only default: 00h
4 ? 7 4.12 cardbus socket/exca base-address register the cardbus socket/exca base-address register is programmed with a base address referencing the cardbus socket registers and the memory-mapped exca register set. bits 31 ? 12 are read/write and allow the base address to be located anywhere in the 32-bit pci memory address space on a 4-kbyte boundary. bits 11 ? 0 are read-only, returning 0s when read. when software writes all 1s to this register, the value read back is ffff f000h, indicating that at least 4 kbytes of memory address space are required. the cardbus registers start at offset 000h, and the memory-mapped exca registers begin at offset 800h. because this register is not shared by functions 0 and 1, mapping of each socket control is performed separately. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cardbus socket/exca base-address type rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cardbus socket/exca base-address type rw rw rw rw r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: cardbus socket/exca base-address offset: 10h type: read-only, read/write default: 0000 0000h 4.13 capability pointer register the capability pointer register provides a pointer into the pci configuration header where the pci power-management register block resides. pci header doublewords at a0h and a4h provide the power-management (pm) registers. each socket has its own capability pointer register. this register returns a0h when read. bit 7 6 5 4 3 2 1 0 name capability pointer type r r r r r r r r default 1 0 1 0 0 0 0 0 register: capability pointer offset: 14h type: read-only default: a0h
4 ? 8 4.14 secondary status register the secondary status register is compatible with the pci-to-pci bridge secondary status register and indicates cardbus-related device information to the host system. this register is very similar to the status register (offset 06h, see section 4.5); status bits are cleared by writing a 1. see table 4 ? 5 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name secondary status type rc rc rc rc rc r r rc r r r r r r r r default 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 register: secondary status offset: 16h type: read-only, read/clear default: 0200h table 4 ? 5. secondary status register description bit signal type function 15 cbparity rc detected parity error. bit 15 is set when a cardbus parity error is detected (either address or data). 14 cbserr rc signaled system error. bit 14 is set when cserr is signaled by a cardbus card. the pci1520 does not assert cserr . 13 cbmabort rc received master abort. bit 13 is set when a cycle initiated by the pci1520 on the cardbus bus has been terminated by a master abort. 12 rec_cbta rc received target abort. bit 12 is set when a cycle initiated by the pci1520 on the cardbus bus is terminated by a target abort. 11 sig_cbta rc signaled target abort. bit 11 is set by the pci1520 when it terminates a transaction on the cardbus bus with a target abort. 10 ? 9 cb_speed r cdevsel timing. these bits encode the timing of cdevsel and are hardwired 01b, indicating that the pci1520 asserts cb_speed at a medium speed. 8 cb_dpar rc cardbus data parity error detected. 0 = the conditions for setting bit 8 have not been met. 1 = a data parity error occurred and the following conditions were met: a. cperr was asserted on the cardbus interface. b. the pci1520 was the bus master during the data parity error. c. the parity error response bit is set in the bridge control. 7 cbfbb_cap r fast back-to-back capable. the pci1520 cannot accept fast back-to-back transactions; therefore, bit 7 is hardwired to 0. 6 cb_udf r user-definable feature support. the pci1520 does not support user-definable features; therefore, bit 6 is hardwired to 0. 5 cb66mhz r 66-mhz capable. the pci1520 cardbus interface operates at a maximum cclk frequency of 33 mhz; therefore, bit 5 is hardwired to 0. 4 ? 0 rsvd r reserved. bits 4 ? 0 return 0s when read.
4 ? 9 4.15 pci bus number register this register is programmed by the host system to indicate the bus number of the pci bus to which the pci1520 is connected. the pci1520 uses this register in conjunction with the cardbus bus number and subordinate bus number registers to determine when to forward pci configuration cycles to its secondary buses. bit 7 6 5 4 3 2 1 0 name pci bus number type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: pci bus number offset: 18h (functions 0, 1) type: read/write default: 00h 4.16 cardbus bus number register this register is programmed by the host system to indicate the bus number of the cardbus bus to which the pci1520 is connected. the pci1520 uses this register in conjunction with the pci bus number and subordinate bus number registers to determine when to forward pci configuration cycles to its secondary buses. this register is separate for each pci1520 controller function. bit 7 6 5 4 3 2 1 0 name cardbus bus number type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: cardbus bus number offset: 19h type: read/write default: 00h 4.17 subordinate bus number register this register is programmed by the host system to indicate the highest-numbered bus below the cardbus bus. the pci1520 uses this register in conjunction with the pci bus number and cardbus bus number registers to determine when to forward pci configuration cycles to its secondary buses. this register is separate for each cardbus controller function. bit 7 6 5 4 3 2 1 0 name subordinate bus number type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: subordinate bus number offset: 1ah type: read/write default: 00h
4 ? 10 4.18 cardbus latency timer register this register is programmed by the host system to specify the latency timer for the pci1520 cardbus interface in units of cclk cycles. when the pci1520 is a cardbus initiator and asserts cframe , the cardbus latency timer begins counting. if the latency timer expires before the pci1520 transaction has terminated, then the pci1520 terminates the transaction at the end of the next data phase. a recommended minimum value for this register is 40h, which allows most transactions to be completed. bit 7 6 5 4 3 2 1 0 name cardbus latency timer type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: cardbus latency timer offset: 1bh (functions 0, 1) type: read/write default: 00h 4.19 memory base registers 0, 1 the memory base registers indicate the lower address of a pci memory address range. these registers are used by the pci1520 to determine when to forward a memory transaction to the cardbus bus and when to forward a cardbus cycle to pci. bits 31 ? 12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit pci memory space on 4-kbyte boundaries. bits 11 ? 0 are read-only and always return 0s. write transactions to these bits have no effect. bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. the memory base register or the memory limit register must be nonzero for the pci1520 to claim any memory transactions through cardbus memory windows (that is, these windows are not enabled by default to pass the first 4 kbytes of memory to cardbus). bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name memory base registers 0, 1 type rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name memory base registers 0, 1 type rw rw rw rw r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: memory base registers 0, 1 offset: 1ch, 24h type: read-only, read/write default: 0000 0000h
4 ? 11 4.20 memory limit registers 0, 1 the memory limit registers indicate the upper address of a pci memory address range. these registers are used by the pci1520 to determine when to forward a memory transaction to the cardbus bus and when to forward a cardbus cycle to pci. bits 31 ? 12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit pci memory space on 4-kbyte boundaries. bits 11 ? 0 are read-only and always return 0s. write transactions to these bits have no effect. bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. the memory base register or the memory limit register must be nonzero for the pci1520 to claim any memory transactions through cardbus memory windows; that is, these windows are not enabled by default to pass the first 4 kbytes of memory to cardbus. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name memory limit registers 0, 1 type rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name memory limit registers 0, 1 type rw rw rw rw r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: memory limit registers 0, 1 offset: 20h, 28h type: read-only, read/write default: 0000 0000h 4.21 i/o base registers 0, 1 the i/o base registers indicate the lower address of a pci i/o address range. these registers are used by the pci1520 to determine when to forward an i/o transaction to the cardbus bus and when to forward a cardbus cycle to the pci bus. the lower 16 bits of this register locate the bottom of the i/o window within a 64-kbyte page, and the upper 16 bits (31 ? 16) are a page register which locates this 64-kbyte page in 32-bit pci i/o address space. bits 31 ? 2 are read/write. bits 1 and 0 are read-only and always return 0s, forcing i/o windows to be aligned on a natural doubleword boundary. note: either the i/o base register or the i/o limit register must be nonzero to enable any i/o transactions. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name i/o base registers 0, 1 type rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name i/o base registers 0, 1 type rw rw rw rw rw rw rw rw rw rw rw rw rw rw r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: i/o base registers 0, 1 offset: 2ch, 34h type: read-only, read/write default: 0000 0000h
4 ? 12 4.22 i/o limit registers 0, 1 the i/o limit registers indicate the upper address of a pci i/o address range. these registers are used by the pci1520 to determine when to forward an i/o transaction to the cardbus bus and when to forward a cardbus cycle to pci. the lower 16 bits of this register locate the top of the i/o window within a 64-kbyte page, and the upper 16 bits are a page register that locates this 64-kbyte page in 32-bit pci i/o address space. bits 15 ? 2 are read/write and allow the i/o limit address to be located anywhere in the 64-kbyte page (indicated by bits 31 ? 16 of the appropriate i/o base) on doubleword boundaries. bits 31 ? 16 are read-only and always return 0s when read. the page is set in the i/o base register. bits 1 and 0 are read-only and always return 0s, forcing i/o windows to be aligned on a natural doubleword boundary. write transactions to read-only bits have no effect. the pci1520 assumes that the lower 2 bits of the limit address are 1s. note: the i/o base or the i/o limit register must be nonzero to enable an i/o transaction. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name i/o limit registers 0, 1 type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name i/o limit registers 0, 1 type rw rw rw rw rw rw rw rw rw rw rw rw rw rw r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: i/o limit registers 0, 1 offset: 30h, 38h type: read-only, read/write default: 0000 0000h 4.23 interrupt line register the interrupt line register communicates interrupt line routing information. each pci1520 function has an interrupt line register. bit 7 6 5 4 3 2 1 0 name interrupt line type rw rw rw rw rw rw rw rw default 1 1 1 1 1 1 1 1 register: interrupt line offset: 3ch type: read/write default: ffh
4 ? 13 4.24 interrupt pin register the value read from the interrupt pin register is function dependent and depends on the interrupt signaling mode, selected through bits 2 ? 1 (intmode field) of the device control register (pci offset 92h, see section 4.33) and the state of bit 29 (intrtie) in the system control register (pci offset 80h, see section 4.29). when the intrtie bit is set, this register reads 01h (inta ) for both functions. see table 4 ? 6 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name interrupt pin type r r r r r r r r default 0 0 0 0 0 0 x x register: interrupt pin offset: 3dh type: read-only default: 0xh table 4 ? 6. interrupt pin register cross reference intrtie bit intpin intrtie bit function 0 function 1 0 01h 02h 1 01h 01h
4 ? 14 4.25 bridge control register the bridge control register provides control over various pci1520 bridging functions. some bits in this register are global and are accessed only through function 0. see table 4 ? 7 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name bridge control type r r r r r rw rw rw rw rw rw r rw rw rw rw default 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 register: bridge control offset: 3eh (functions 0, 1) type: read-only, read/write default: 0340h table 4 ? 7. bridge control register description bit signal type function 15 ? 11 rsvd r reserved. bits 15 ? 11 return 0s when read. 10 posten rw write posting enable. enables write posting to and from the cardbus sockets. write posting enables posting of write data on burst cycles. operating with write posting disabled inhibits performance on burst cycles. note that burst write data can be posted, but various write transactions may not. bit 10 is socket dependent and is not shared between functions 0 and 1. 9 prefetch1 rw memory window 1 type. bit 9 specifies whether or not memory window 1 is prefetchable. this bit is socket dependent. bit 9 is encoded as: 0 = memory window 1 is nonprefetchable. 1 = memory window 1 is prefetchable (default). 8 prefetch0 rw memory window 0 type. bit 8 specifies whether or not memory window 0 is prefetchable. this bit is encoded as: 0 = memory window 0 is nonprefetchable. 1 = memory window 0 is prefetchable (default). 7 intr rw pci interrupt ? ireq routing enable. bit 7 selects whether pc card functional interrupts are routed to pci interrupts or the irq specified in the exca registers. 0 = functional interrupts routed to pci interrupts (default) 1 = functional interrupts routed by excas 6 crst rw cardbus reset. when bit 6 is set, crst is asserted on the cardbus interface. crst can also be asserted by passing a prst assertion to cardbus. 0 = crst deasserted 1 = crst asserted (default) 5 ? mabtmode rw master abort mode. bit 5 controls how the pci1520 responds to a master abort when the pci1520 is an initiator on the cardbus interface. this bit is common between each socket. 0 = master aborts not reported (default) 1 = signal target abort on pci and serr (if enabled) 4 rsvd r reserved. bit 4 returns 0 when read. 3 vgaen rw vga enable. bit 3 affects how the pci1520 responds to vga addresses. when this bit is set, accesses to vga addresses are forwarded. 2 isaen rw isa mode enable. bit 2 affects how the pci1520 passes i/o cycles within the 64-kbyte isa range. this bit is not common between sockets. when this bit is set, the pci1520 does not forward the last 768 bytes of each 1k i/o range to cardbus. 1 ? cserren rw cserr enable. bit 1 controls the response of the pci1520 to cserr signals on the cardbus bus. this bit is common between the two sockets. 0 = cserr is not forwarded to pci serr . 1 = cserr is forwarded to pci serr . 0 ? cperren rw cardbus parity error response enable. bit 0 controls the response of the pci1520 to cardbus parity errors. this bit is common between the two sockets. 0 = cardbus parity errors are ignored. 1 = cardbus parity errors are reported using cperr . ? this bit is global and is accessed only through function 0.
4 ? 15 4.26 subsystem vendor id register the subsystem vendor id register is used for system and option-card identification purposes and may be required for certain operating systems. this register is read-only or read/write, depending on the setting of bit 5 (subsysrw) in the system control register (pci offset 80h, see section 4.29). bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name subsystem vendor id type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: subsystem vendor id offset: 40h (functions 0, 1) type: read-only (read/write if enabled by subsysrw) default: 0000h 4.27 subsystem id register the subsystem id register is used for system and option-card identification purposes and may be required for certain operating systems. this register is read-only or read/write, depending on the setting of bit 5 (subsysrw) in the system control register (pci offset 80h, see section 4.29). bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name subsystem id type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: subsystem id offset: 42h (functions 0, 1) type: read-only (read/write if enabled by subsysrw) default: 0000h 4.28 pc card 16-bit i/f legacy-mode base address register the pci1520 supports the index/data scheme of accessing the exca registers, which are mapped by this register. an address written to this register is the address for the index register and the address + 1 is the data address. using this access method, applications requiring index/data exca access can be supported. the base address can be mapped anywhere in 32-bit i/o space on a word boundary; hence, bit 0 is read-only, returning 1 when read. as specified in the pci to pcmcia cardbus bridge register description (yenta), this register is shared by functions 0 and 1. see section 5, exca compatibility registers , for register offsets. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name pc card 16-bit i/f legacy-mode base address type rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pc card 16-bit i/f legacy-mode base address type rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 register: pc card 16-bit i/f legacy-mode base address offset: 44h (functions 0, 1) type: read-only, read/write default: 0000 0001h
4 ? 16 4.29 system control register system-level initializations are performed by programming this doubleword register. some of the bits are global and are written only through function 0. see table 4 ? 8 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name system control type rw rw rw r rw rw rc rw r rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name system control type rw rw r r r r r r r rw rw rw rw rw rw rw default 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 register: system control offset: 80h (functions 0, 1) type: read-only, read/write, read/clear default: 0044 9060h
4 ? 17 table 4 ? 8. system control register description bit signal type function 31 ? 30 ? ser_step rw serialized pci interrupt routing step. bits 31 and 30 configure the serialized pci interrupt stream signaling and accomplish an even distribution of interrupts signaled on the four pci interrupt slots. bits 31 and 30 are global to all pci1520 functions. 00 = inta /intb signal in inta /intb irqser slots 01 = inta /intb signal in intb /intc irqser slots 10 = inta /intb signal in intc /intd irqser slots 11 = inta /intb signal in intd /inta irqser slots 29 ? intrtie rw tie internal pci interrupts. when this bit is set, the inta and intb signals are tied together internally and are signaled as inta . inta can then be shifted by using bits 31 ? 30 (ser_step). this bit is global to all pci1520 functions. when configuring the pci1520 functions to share pci interrupts, multifunction terminal mfunc3 must be configured as irqser prior to setting the intrtie bit. 28 rsvd r reserved. bit 28 returns 0 when read. 27 ? p2cclk rw p2c power switch clock. the pci1520 clock signal is used to clock the serial interface power switch and the internal state machine. the default state for bit 27 is 0, requiring an external clock source provided to the clock terminal (terminal number f15 for the ghk package or terminal number 154 for the pdv package). bit 27 can be set to 1, allowing the internal oscillator to provide the clock signal. 0 = clock provided externally, input to pci1520 (default) 1 = clock generated by internal oscillator and driven by pci1520. 26 smiroute rw smi interrupt routing. bit 26 is shared between functions 0 and 1, and selects whether irq2 or csc is signaled when a write occurs to power a pc card socket. 0 = pc card power change interrupts routed to irq2 (default) 1 = a csc interrupt is generated on pc card power changes. 25 smistatus rc smi interrupt status. this socket-dependent bit is set when bit 24 (smienb) is set and a write occurs to set the socket power. writing a 1 to bit 25 clears the status. 0 = smi interrupt signaled (default) 1 = smi interrupt not signaled 24 ? smienb rw smi interrupt mode enable. when bit 24 is set and a write to the socket power control occurs, the smi interrupt signaling is enabled and generates an interrupt. this bit is shared and defaults to 0 (disabled). 23 rsvd r reserved. bit 23 returns 0 when read. 22 cbrsvd rw cardbus reserved terminals signaling. when a cardbus card is inserted and bit 22 is set, the rsvd cardbus terminals are driven low. when this bit is 0, these terminals are placed in a high-impedance state. 0 = place cardbus rsvd terminals in a high-impedance state. 1 = drive cardbus rsvd terminals low (default). 21 vccprot rw v cc protection enable. bit 21 is socket dependent. 0 = v cc protection enabled for 16-bit cards (default) 1 = v cc protection disabled for 16-bit cards 20 reducezv rw reduced zoomed video enable. when this bit is enabled, terminals a25 ? a22 of the card interface for pc card-16 cards are placed in the high-impedance state. this bit should not be set for normal zv operation. this bit is encoded as: 0 = reduced zoomed video disabled (default) 1 = reduced zoomed video enabled 19 ? 16 rsvd rw reserved. do not change the default value. 15 ? mrburstd n rw memory read burst enable downstream. when bit 15 is set, memory read transactions are allowed to burst downstream. 0 = downstream memory read burst is disabled. 1 = downstream memory read burst is enabled (default). 14 ? mrburstu p rw memory read burst enable upstream. when bit 14 is set, the pci1520 allows memory read transactions to burst upstream. 0 = upstream memory read burst is disabled (default). 1 = upstream memory read burst is enabled. 13 socactiv e r socket activity status. when set, bit 13 indicates access has been performed to or from a pc card and is cleared upon read of this status bit. this bit is socket-dependent. 0 = no socket activity (default) 1 = socket activity 12 rsvd r reserved. bit 12 returns 1 when read. ? this bit is global and is accessed only through function 0.
4 ? 18 table 4 ? 8. system control register description (continued) bit signal type function 11 ? pwrstream r power stream in progress status bit. when set, bit 11 indicates that a power stream to the power switch is in progress and a powering change has been requested. this bit is cleared when the power stream is complete. 0 = power stream is complete and delay has expired. 1 = power stream is in progress. 10 ? delayup r power-up delay in progress status. when set, bit 10 indicates that a power-up stream has been sent to the power switch and proper power may not yet be stable. this bit is cleared when the power-up delay has expired. 9 ? delaydown r power-down delay in progress status. when set, bit 9 indicates that a power-down stream has been sent to the power switch and proper power may not yet be stable. this bit is cleared when the power-down delay has expired. 8 interrogate r interrogation in progress. when set, bit 8 indicates an interrogation is in progress and clears when interrogation completes. this bit is socket dependent. 0 = interrogation not in progress (default) 1 = interrogation in progress 7 rsvd r reserved. bit 7 returns 0 when read. 6 pwrsavings rw power savings mode enable. when this bit is set, if a cb card is inserted, idle, and without a cb clock, then the applicable cb state machine will not be clocked. 5 ? subsysrw rw subsystem id (pci offset 42h, see section 4.27), subsystem vendor id (pci offset 40h, see section 4.26), exca identification and revision (exca offset 00h/40h/800h, see section 5.1) registers read/write enable. bit 5 is shared by functions 0 and 1. 0 = subsystem id, subsystem vendor id, exca identification and revision registers are read/write. 1 = subsystem id, subsystem vendor id, exca identification and revision registers are read-only (default). 4 ? cb_dpar rw cardbus data parity serr signaling enable 0 = cardbus data parity not signaled on pci serr 1 = cardbus data parity signaled on pci serr 3 rsvd rw reserved. do not change the default value. 2 excapower rw exca power-control bit. 0 = enables 3.3 v 1 = enables 5 v 1 ? keepclk rw keep clock. this bit works with pci and cb clkrun protocols. 0 = allows normal functioning of both clkrun protocols (default) 1 = does not allow cb clock or pci clock to be stopped using the clkrun protocols 0 rimux rw ri_out /pme multiplex enable. 0 = ri_out and pme are both routed to the ri_out /pme terminal. if both functions are are enabled at the same time, the terminal becomes ri_out only and pme assertions are not seen. 1 = only pme is routed to the ri_out /pme terminal. ? this bit is global and is accessed only through function 0.
4 ? 19 4.30 multifunction routing register the multifunction routing register is used to configure the mfunc0 ? mfunc6 terminals. these terminals may be configured for various functions. all multifunction terminals default to the general-purpose input configuration. this register is intended to be programmed once at power-on initialization. the default value for this register can also be loaded through a serial bus eeprom. see table 4 ? 9 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name multifunction routing type r r r r rw rw rw rw rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name multifunction routing type rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw default 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 register: multifunction routing offset: 8ch (functions 0, 1) type: read-only, read/write default: 0000 1000h table 4 ? 9. multifunction routing register description bit signal type function 31 ? 28 rsvd r bits 31 ? 28 return 0s when read. 27 ? 24 mfunc6 rw multifunction terminal 6 configuration. these bits control the internal signal mapped to the mfunc6 terminal as follows: 0000 = rsvd ? 0100 = irq4 1000 = irq8 1100 = irq12 0001 = clkrun 0101 = irq5 1001 = irq9 1101 = irq13 0010 = irq2 0110 = irq6 1010 = irq10 1110 = irq14 0011 = irq3 0111 = irq7 1011 = irq11 1111 = irq15 23 ? 20 mfunc5 rw multifunction terminal 5 configuration. these bits control the internal signal mapped to the mfunc5 terminal as follows: 0000 = gpi4 ? 0100 = irq4 1000 = caudpwm 1100 = leda1 0001 = gpo4 0101 = irq5 1001 = d3_stat 1101 = led_skt 0010 = pcgnt 0110 = zvstat 1010 = irq10 1110 = gpe 0011 = irq3 0111 = zvsel1 1011 = irq11 1111 = irq15 19 ? 16 mfunc4 rw multifunction terminal 4 configuration. these bits control the internal signal mapped to the mfunc4 terminal as follows: note: when the serial bus mode is implemented by pulling down the latch terminal, the mfunc4 terminal provides the scl signaling. 0000 = gpi3 ? 0100 = irq4 1000 = caudpwm 1100 = ri_out 0001 = gpo3 0101 = irq5 1001 = irq9 1101 = led_skt 0010 = lock pci 0110 = zvstat 1010 = irq10 1110 = gpe 0011 = irq3 0111 = zvsel1 1011 = irq11 1111 = d3_stat 15 ? 12 mfunc3 rw multifunction terminal 3 configuration. these bits control the internal signal mapped to the mfunc3 terminal as follows: 0000 = rsvd 0100 = irq4 1000 = irq8 1100 = irq12 0001 = irqser ? 0101 = irq5 1001 = irq9 1101 = irq13 0010 = irq2 0110 = irq6 1010 = irq10 1110 = irq14 0011 = irq3 0111 = irq7 1011 = irq11 1111 = irq15 11 ? 8 mfunc2 rw multifunction terminal 2 configuration. these bits control the internal signal mapped to the mfunc2 terminal as follows: 0000 = gpi2 ? 0100 = irq4 1000 = caudpwm 1100 = ri_out 0001 = gpo2 0101 = irq5 1001 = irq9 1101 = leda2 0010 = pcreq 0110 = zvstat 1010 = irq10 1110 = gpe 0011 = irq3 0111 = zvsel0 1011 = d3_stat 1111 = irq7
4 ? 20 table 4 ? 9. multifunction routing register description (continued) bit signal type function 7 ? 4 mfunc1 rw multifunction terminal 1 configuration. these bits control the internal signal mapped to the mfunc1 terminal as follows: note: when the serial bus mode is implemented by pulling down the latch terminal, the mfunc1 terminal provides the sda signaling. 0000 = gpi1 ? 0100 = irq4 1000 = caudpwm 1100 = leda1 0001 = gpo1 0101 = irq5 1001 = irq9 1101 = leda2 0010 = intb 0110 = zvstat 1010 = irq10 1110 = gpe 0011 = irq3 0111 = zvsel0 1011 = irq11 1111 = irq15 3 ? 0 mfunc0 rw multifunction terminal 0 configuration. these bits control the internal signal mapped to the mfunc0 terminal as follows: 0000 = gpi0 ? 0100 = irq4 1000 = caudpwm 1100 = leda1 0001 = gpo0 0101 = irq5 1001 = irq9 1101 = leda2 0010 = inta 0110 = zvstat 1010 = irq10 1110 = gpe 0011 = irq3 0111 = zvsel0 1011 = irq11 1111 = irq15 ? default value
4 ? 21 4.31 retry status register the retry status register enables the retry timeout counters and displays the retry expiration status. the flags are set when the pci1520 retries a pci or cardbus master request and the master does not return within 2 15 pci clock cycles. the flags are cleared by writing a 1 to the bit. these bits are expected to be incorporated into the pci command, pci status, and bridge control registers by the pci sig. access this register only through function 0. see table 4 ? 10 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name retry status type rw rw rc r rc r rc r default 1 1 0 0 0 0 0 0 register: retry status offset: 90h (functions 0, 1) type: read-only, read/write, read/clear default: c0h table 4 ? 10. retry status register description bit signal type function 7 pciretry rw pci retry timeout counter enable. bit 7 is encoded: 0 = pci retry counter disabled 1 = pci retry counter enabled (default) 6 ? cbretry rw cardbus retry timeout counter enable. bit 6 is encoded: 0 = cardbus retry counter disabled 1 = cardbus retry counter enabled (default) 5 texp_cbb rc cardbus target b retry expired. write a 1 to clear bit 5. 0 = inactive (default) 1 = retry has expired 4 rsvd r reserved. bit 4 returns 0 when read. 3 ? texp_cba rc cardbus target a retry expired. write a 1 to clear bit 3. 0 = inactive (default) 1 = retry has expired. 2 rsvd r reserved. bit 2 returns 0 when read. 1 texp_pci rc pci target retry expired. write a 1 to clear bit 1. 0 = inactive (default) 1 = retry has expired. 0 rsvd r reserved. bit 0 returns 0 when read. ? this bit is global and is accessed only through function 0.
4 ? 22 4.32 card control register the card control register is provided for pci1130 compatibility. ri_out is enabled through this register, and the enable bit is shared between functions 0 and 1. see table 4 ? 11 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name card control type rw rw rw r r rw rw rc default 0 0 0 0 0 0 0 0 register: card control offset: 91h type: read-only, read/write, read/clear default: 00h table 4 ? 11. card control register description bit signal type function 7 ? rienb rw ring indicate output enable. 0 = disables any routing of ri_out signal (default) 1 = enables ri_out signal for routing to the ri_out /pme terminal, when rimux is set to 0, and for routing to mfunc2 or mfunc4 6 zvenable rw compatibility zv mode enable. when set, the corresponding pc card socket interface zv terminals enter a high-impedance state. this bit defaults to 0. 5 port_sel rw port select. this bit controls the priority for the zvsel0 and zvsel1 signaling if bit 6 (zvenable) is set in both functions. 0 = socket 0 takes priority, as signaled through zvsel0 , when both sockets are in zv mode. 1 = socket 1 takes priority, as signaled through zvsel1 , when both sockets are in zv mode. 4 ? 3 rsvd r reserved. bits 4 and 3 return 0 when read. 2 aud2mux rw cardbus audio-to-irqmux. when set, the caudio cardbus signal is routed to the corresponding multifunction terminal which may be configured for caudpwm. when both socket 0 and 1 functions have aud2mux set, socket 0 takes precedence. 1 spkrouten rw speaker out enable. when bit 1 is set, spkr on the pc card is enabled and is routed to spkrout. the spkr signal from socket 0 is xored with the spkr signal from socket 1 and sent to spkrout. the spkrout terminal drives data only when the spkrouten bit of either function is set. this bit is encoded as: 0 = spkr to spkrout not enabled 1 = spkr to spkrout enabled 0 ifg rc interrupt flag. bit 0 is the interrupt flag for 16-bit i/o pc cards and for cardbus cards. bit 0 is set when a functional interrupt is signaled from a pc card interface and is socket dependent (that is, not global). write back a 1 to clear this bit. 0 = no pc card functional interrupt detected (default). 1 = pc card functional interrupt detected. ? this bit is global and is accessed only through function 0.
4 ? 23 4.33 device control register the device control register is provided for pci1130 compatibility and contains bits that are shared between functions 0 and 1. the interrupt mode select is programmed through this register which is composed of pci1520 global bits. the socket-capable force bits are also programmed through this register. see table 4 ? 12 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name device control type rw rw rw r rw rw rw rw default 0 1 1 0 0 1 1 0 register: device control offset: 92h (functions 0, 1) type: read-only, read/write default: 66h table 4 ? 12. device control register description bit signal type function 7 sktpwr_lock rw socket power lock bit. when this bit is set to 1, software cannot power down the pc card socket while in d3. this may be necessary to support wake on lan or ring if the operating system is programmed to power down a socket when the cardbus controller is placed in the d3 state. 6 ? 3vcapable rw 3-v socket capable force 0 = not 3-v capable 1 = 3-v capable (default) 5 io16v2 rw diagnostic bit. this bit defaults to 1. 4 rsvd r reserved. bit 4 returns 0 when read. 3 ? test rw ti test. only a 0 should be written to bit 3. 2 ? 1 intmode rw interrupt signaling mode. bits 2 and 1 select the interrupt signaling mode. the interrupt signaling mode bits are encoded: 00 = parallel pci interrupts only 01 = parallel irq and parallel pci interrupts 10 = irq serialized interrupts and parallel pci interrupt 11 = irq and pci serialized interrupts (default) 0 ? rsvd rw reserved. bit 0 is reserved for test purposes. only 0 should be written to this bit. ? this bit is global and is accessed only through function 0.
4 ? 24 4.34 diagnostic register the diagnostic register is provided for internal ti test purposes. it is a read/write register, but only 0s should be written to it. see table 4 ? 13 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name diagnostic type rw r rw rw rw rw rw rw default 0 1 1 0 0 0 0 0 register: diagnostic offset: 93h (functions 0, 1) type: read/write default: 60h table 4 ? 13. diagnostic register description bit signal type function 7 ? true_val rw this bit defaults to 0. this bit is encoded as: 0 = reads true values in pci vendor id and pci device id registers (default) 1 = reads all 1s in reads from the pci vendor id and pci device id registers 6 rsvd r reserved. bit 6 returns 1 when read. 5 csc rw csc interrupt routing control 0 = csc interrupts routed to pci if exca 803 bit 4 = 1 1 = csc interrupts routed to pci if exca 805 bits 7 ? 4 = 0000b (default) in this case, the setting of exca 803 bit 4 is a don ? t care. 4 ? diag4 rw diagnostic retry_dis. delayed transaction disable. 3 ? diag3 rw diagnostic retry_ext. extends the latency from 16 to 64. 2 ? diag2 rw diagnostic discard_tim_sel_cb. set = 2 10 , reset = 2 15 . 1 ? diag1 rw diagnostic discard_tim_sel_pci. set = 2 10 , reset = 2 15 . 0 stdzven rw standardized zoomed video register model enable. 0 = enable the standardized zoomed video register model (default). 1 = disable the standardized zoomed video register model. ? this bit is global and is accessed only through function 0.
4 ? 25 4.35 capability id register the capability id register identifies the linked list item as the register for pci power management. the register returns 01h when read, which is the unique id assigned by the pci sig for the pci location of the capabilities pointer and the value. bit 7 6 5 4 3 2 1 0 name capability id type r r r r r r r r default 0 0 0 0 0 0 0 1 register: capability id offset: a0h type: read-only default: 01h 4.36 next-item pointer register the next-item pointer register indicates the next item in the linked list of the pci power-management capabilities. because the pci1520 functions include only one capabilities item, this register returns 0s when read. bit 7 6 5 4 3 2 1 0 name next-item pointer type r r r r r r r r default 0 0 0 0 0 0 0 0 register: next-item pointer offset: a1h type: read-only default: 00h
4 ? 26 4.37 power-management capabilities register this register contains information on the capabilities of the pc card function related to power management. both pci1520 cardbus bridge functions support d0, d1, d2, and d3 power states. see table 4 ? 14 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name power-management capabilities type rw r r r r r r r r r r r r r r r default 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 0 register: power-management capabilities offset: a2h type: read/write, read-only default: fe12h table 4 ? 14. power-management capabilities register description bit signal type function pme support. this 5-bit field indicates the power states from which the pci1520 device functions may assert pme . a 0 (zero) for any bit indicates that the function cannot assert the pme signal while in that power state. these five bits return 1 1111b when read. each of these bits is described below: 15 pme_support rw bit 15 defaults to the value 1 indicating the pme signal can be asserted from the d3 cold state. this bit is r/w because wake-up support from d3 cold is contingent on the system providing an auxiliary power source to the v cc terminals. if the system designer chooses not to provide an auxiliary power source to the v cc terminals for d3 cold wake-up support, then bios should write a 0 to this bit. 14 ? 11 pme_support r bit 14 contains the value 1, indicating that the pme signal can be asserted from d3 hot state. bit 13 contains the value 1, indicating that the pme signal can be asserted from d2 state. bit 12 contains the value 1, indicating that the pme signal can be asserted from d1 state. bit 11 contains the value 1, indicating that the pme signal can be asserted from the d0 state. 10 d2_support r d2 support. bit 10 returns a 1 when read, indicating that the cardbus function supports the d2 device power state. 9 d1_support r d1 support. bit 9 returns a 1 when read, indicating that the cardbus function supports the d1 device power state. 8 ? 6 rsvd r reserved. bits 8 ? 6 return 0s when read. 5 dsi r device-specific initialization. bit 5 returns 1 when read, indicating that the cardbus controller function requires special initialization (beyond the standard pci configuration header) before the generic-class device driver is able to use it. 4 aux_pwr r auxiliary power source. bit 4 is meaningful only if bit 15 (pme_support, d3 cold ) is set. when bit 4 is set, it indicates that support for pme in d3 cold requires auxiliary power supplied by the system by way of a proprietary delivery vehicle. when bit 4 is 0, it indicates that the function supplies its own auxiliary power source. 3 pmeclk r pme clock. bit 3 returns 0 when read, indicating that no host bus clock is required for the pci1520 to generate pme . 2 ? 0 version r version. bits 2 ? 0 return 010b when read, indicating that the power-management registers (pci offsets a4h ? a7h, see sections 4.38 ? 4.40) are defined in the pci bus power management interface specification version 1.1.
4 ? 27 4.38 power-management control/status register the power-management control/status register determines and changes the current power state of the pci1520 cardbus function. the contents of this register are not affected by the internally-generated reset caused by the transition from d3 hot to d0 state. all pci, exca, and cardbus registers are reset as a result of a d3 hot to d0 state transition. ti-specific registers, pci power-management registers, and the pc card 16-bit legacy-mode base address register (pci offset 44h, see section 4.28) are not reset. see table 4 ? 15 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name power-management control/status type rc r r r r r r rw r r r r r r rw rw default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: power-management control/status offset: a4h (functions 0, 1) type: read-only, read/write, read/clear default: 0000h table 4 ? 15. power-management control/status register description bit signal type function 15 pmestat rc pme status. bit 15 is set when the cardbus function would normally assert pme , independent of the state of bit 8 (pme_en). bit 15 is cleared by a writeback of 1, and this also clears the pme signal if pme was asserted by this function. writing a 0 to this bit has no effect. 14 ? 13 datascale r data scale. this 2-bit field returns 0s when read. the cardbus function does not return any dynamic data. 12 ? 9 datasel r data select. this 4-bit field returns 0s when read. the cardbus function does not return any dynamic data. 8 pme_en rw pme enable. bit 8 enables the function to assert pme . if this bit is cleared, then assertion of pme is disabled. 7 ? 2 rsvd r reserved. bits 7 ? 2 return 0s when read. 1 ? 0 pwr_state rw power state. this 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. this field is encoded as: 00 = d0 01 = d1 10 = d2 11 = d3 hot
4 ? 28 4.39 power-management control/status register bridge support extensions the power-management control/status register bridge support extensions support pci bridge specific functionality. see table 4 ? 16 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name power-management control/status register bridge support extensions type r r r r r r r r default 1 1 0 0 0 0 0 0 register: power-management control/status register bridge support extensions offset: a6h (functions 0, 1) type: read-only default: c0h table 4 ? 16. power-management control/status register bridge support extensions description bit signal type function 7 bpcc_en r bpcc_enable. bus power/clock control enable. this bit returns 1 when read. this bit is encoded as: 0 = bus power/clock control is disabled. 1 = bus power/clock control is enabled (default). a 0 indicates that the bus power/clock control policies defined in the pci bus power management interface specification are disabled. when the bus power/clock control enable mechanism is disabled, the bridge power-management control/status register power state field (see section 4.38, bits 1 ? 0) cannot be used by the system software to control the power or the clock of the bridge secondary bus. a 1 indicates that the bus power/clock control mechanism is enabled. 6 b2_b3 r b2/b3 support for d3 hot . the state of this bit determines the action that is to occur as a direct result of programming the function to d3 hot . this bit is only meaningful if bit 7 (bpcc_en) is a 1. this bit is encoded as: 0 = when the bridge is programmed to d3 hot , its secondary bus has its power removed (b3). 1 = when the bridge function is programmed to d3 hot , its secondary bus pci clock is stopped (b2) (default). 5 ? 0 rsvd r reserved. bits 5 ? 0 return 0s when read. 4.40 power-management data register the power-management data register returns 0s when read, because the cardbus functions do not report dynamic data. bit 7 6 5 4 3 2 1 0 name power-management data type r r r r r r r r default 0 0 0 0 0 0 0 0 register: power-management data offset: a7h (functions 0, 1) type: read-only default: 00h
4 ? 29 4.41 general-purpose event status register the general-purpose event status register contains status bits that are set when events occur that are controlled by the general-purpose control register. the bits in this register and the corresponding gpe are cleared by writing a 1 to the corresponding bit location. the status bits in this register do not depend upon the states of corresponding bits in the general-purpose enable register. access this register only through function 0. see table 4 ? 17 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name general-purpose event status type rc rc r r rc r r rc r r r rc rc rc rc rc default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: general-purpose event status offset: a8h (function 0) type: read-only, read/clear default: 0000h table 4 ? 17. general-purpose event status register description bit signal type function 15 zv0_sts rc pc card socket 0 zv status. bit 15 is set on a change in status of bit 6 (zvenable) in the function 0 card control register (pci offset 91h, see section 4.32). 14 zv1_sts rc pc card socket 1 zv status. bit 14 is set on a change in status of bit 6 (zvenable) in the function 1 card control register (pci offset 91h, see section 4.32). 13 ? 12 rsvd r reserved. bits 13 and 12 return 0s when read. 11 pwr_sts rc power-change status. bit 11 is set when software has changed the power state of either socket. a change in either v cc or v pp for either socket causes this bit to be set. 10 ? 9 rsvd r reserved. bits 10 and 9 return 0s when read. 8 vpp12_sts rc 12-v v pp request status. bit 8 is set when software has changed the requested v pp level to or from 12 v for either of the two pc card sockets. 7 ? 5 rsvd r reserved. bits 7 ? 5 return 0s when read. 4 gp4_sts rc gpi4 status. bit 4 is set on a change in status of the mfunc5 terminal input level. 3 gp3_sts rc gpi3 status. bit 3 is set on a change in status of the mfunc4 terminal input level . 2 gp2_sts rc gpi2 status. bit 2 is set on a change in status of the mfunc2 terminal input level. 1 gp1_sts rc gpi1 status. bit 1 is set on a change in status of the mfunc1 terminal input level. 0 gp0_sts rc gpi0 status. bit 0 is set on a change in status of the mfunc0 terminal input level.
4 ? 30 4.42 general-purpose event enable register the general-purpose event enable register contains bits that are set to enable a gpe signal. the gpe signal is driven until the corresponding status bit is cleared and the event is serviced. the gpe can only be signaled if one of the multifunction terminals, mfunc6 ? mfunc0, is configured for gpe signaling. access this register only through function 0. see table 4 ? 18 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name general-purpose event enable type rw rw r r rw r r rw r r r rw rw rw rw rw default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: general-purpose event enable offset: aah (function 0) type: read-only, read/write default: 0000h table 4 ? 18. general-purpose event enable register description bit signal type function 15 zv0_en rw pc card socket 0 zv enable. when bit 15 is set, a gpe is signaled on a change in status of bit 6 (zvenable) in the function 0 card control register (pci offset 91h, see section 4.32). 14 zv1_en rw pc card socket 1 zv enable. when bit 14 is set, a gpe is signaled on a change in status of bit 6 (zvenable) in the function 1 card control register (pci offset 91h, see section 4.32). 13 ? 12 rsvd r reserved. bits 13 and 12 return 0s when read. 11 pwr_en rw power change enable. when bit 11 is set, a gpe is signaled on when software has changed the power state of either socket. 10 ? 9 rsvd r reserved. bits 10 and 9 return 0s when read. 8 vpp12_en rw 12-v v pp request enable. when bit 8 is set, a gpe is signaled when software has changed the requested v pp level to or from 12 v for either card socket. 7 ? 5 rsvd r reserved. bits 7 ? 5 return 0s when read. 4 gp4_en rw gpi4 enable. when bit 4 is set, a gpe is signaled when there has been a change in status of the mfunc5 terminal input level if configured as gpi4. 3 gp3_en rw gpi3 enable. when bit 3 is set, a gpe is signaled when there has been a change in status of the mfunc4 terminal input level if configured as gpi3. 2 gp2_en rw gpi2 enable. when bit 2 is set, a gpe is signaled when there has been a change in status of the mfunc2 terminal input if configured as gpi2. 1 gp1_en rw gpi1 enable. when bit 1 is set, a gpe is signaled when there has been a change in status of the mfunc1 terminal input if configured as gpi1. 0 gp0_en rw gpi0 enable. when bit 0 is set, a gpe is signaled when there has been a change in status of the mfunc0 terminal input if configured as gpi0.
4 ? 31 4.43 general-purpose input register the general-purpose input register provides the logical value of the data input from the gpi terminals, mfunc5, mfunc4, and mfunc2 ? mfunc0. access this register only through function 0. see table 4 ? 19 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name general-purpose input type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 x x x x x register: general-purpose input offset: ach (function 0) type: read-only default: 00xxh table 4 ? 19. general-purpose input register description bit signal type function 15 ? 5 rsvd r reserved. bits 15 ? 5 return 0s when read. 4 gpi4_data r gpi4 data bit. the value read from bit 4 represents the logical value of the data input from the mfunc5 terminal. 3 gpi3_data r gpi3 data bit. the value read from bit 3 represents the logical value of the data input from the mfunc4 terminal. 2 gpi2_data r gpi2 data bit. the value read from bit 2 represents the logical value of the data input from the mfunc2 terminal. 1 gpi1_data r gpi1 data bit. the value read from bit 1 represents the logical value of the data input from the mfunc1 terminal. 0 gpi0_data r gpi0 data bit. the value read from bit 0 represents the logical value of the data input from the mfunc0 terminal.
4 ? 32 4.44 general-purpose output register the general-purpose output register is used for control of the general-purpose outputs. access this register only through function 0. see table 4 ? 20 for a complete description of the register contents. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name general-purpose output type r r r r r r r r r r r rw rw rw rw rw default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: general-purpose output offset: aeh (function 0) type: read-only, read/write default: 0000h table 4 ? 20. general-purpose output register description bit signal type function 15 ? 5 rsvd r reserved. bits 15 ? 5 return 0s when read. 4 gpo4_data rw gpo4 data bit. the value written to bit 4 represents the logical value of the data driven to the mfunc5 terminal if configured as gpo4. read transactions return the last data value written. 3 gpo3_data rw gpio3 data bit. the value written to bit 3 represents the logical value of the data driven to the mfunc4 terminal if configured as gpo3. read transactions return the last data value written. 2 gpo2_data rw gpo2 data bit. the value written to bit 2 represents the logical value of the data driven to the mfunc2 terminal if configured as gpo2. read transactions return the last data value written. 1 gpo1_data rw gpo1 data bit. the value written to bit 1 represents the logical value of the data driven to the mfunc1 terminal if configured as gpo1. read transactions return the last data value written. 0 gpo0_data rw gpo0 data bit. the value written to bit 0 represents the logical value of the data driven to the mfunc0 terminal if configured as gpo0. read transactions return the last data value written. 4.45 serial-bus data register the serial-bus data register is for programmable serial-bus byte reads and writes. this register represents the data when generating cycles on the serial bus interface. to write a byte, this register must be programmed with the data, the serial bus index register must be programmed with the byte address, the serial-bus slave address must be programmed with the 7-bit slave address, and the read/write indicator bit must be reset. on byte reads, the byte address is programmed into the serial-bus index register , the serial bus slave address register must be programmed with both the 7-bit slave address and the read/write indicator bit, and bit 5 (reqbusy) in the serial bus control and status register (pci offset b3h, see section 4.48) must be polled until clear. then the contents of this register are valid read data from the serial bus interface. see table 4 ? 21 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name serial-bus data type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: serial-bus data offset: b0h (function 0) type: read/write default: 00h table 4 ? 21. serial-bus data register description bit signal type function 7 ? 0 sbdata rw serial-bus data. this bit field represents the data byte in a read or write transaction on the serial interface. on reads, the reqbusy bit must be polled to verify that the contents of this register are valid.
4 ? 33 4.46 serial-bus index register the serial-bus index register is for programmable serial-bus byte reads and writes. this register represents the byte address when generating cycles on the serial-bus interface. to write a byte, the serial-bus data register must be programmed with the data, this register must be programmed with the byte address, and the serial-bus slave address register must be programmed with both the 7-bit slave address and the read/write indicator bit. on byte reads, the word address is programmed into this register , the serial-bus slave address must be programmed with both the 7-bit slave address and the read/write indicator bit, and bit 5 (reqbusy) in the serial-bus control and status register (see section 4.48) must be polled until clear. then the contents of the serial-bus data register are valid read data from the serial-bus interface. see table 4 ? 22 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name serial-bus index type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: serial-bus index offset: b1h (function 0) type: read/write default: 00h table 4 ? 22. serial-bus index register description bit signal type function 7 ? 0 sbindex rw serial-bus index. this bit field represents the byte address in a read or write transaction on the serial interface. 4.47 serial-bus slave address register the serial-bus slave address register is for programmable serial-bus byte read and write transactions. to write a byte, the serial-bus data register must be programmed with the data, the serial-bus index register must be programmed with the byte address, and this register must be programmed with both the 7-bit slave address and the read/write indicator bit. on byte reads, the byte address is programmed into the serial bus index register , this register must be programmed with both the 7-bit slave address and the read/write indicator bit, and bit 5 (reqbusy) in the serial-bus control and status register (pci offset b3h, see section 4.48) must be polled until clear. then the contents of the serial-bus data register are valid read data from the serial-bus interface. see table 4 ? 23 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name serial-bus slave address type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: serial-bus slave address offset: b2h (function 0) type: read/write default: 00h table 4 ? 23. serial-bus slave address register description bit signal type function 7 ? 1 slavaddr rw serial-bus slave address. this bit field represents the slave address of a read or write transaction on the serial interface. 0 rwcmd rw read/write command. bit 0 indicates the read/write command bit presented to the serial bus on byte read and write accesses. 0 = a byte write access is requested to the serial bus interface. 1 = a byte read access is requested to the serial bus interface.
4 ? 34 4.48 serial-bus control and status register the serial-bus control and status register communicates serial-bus status information and selects the quick command protocol. bit 5 (reqbusy) in this register must be polled during serial-bus byte reads to indicate when data is valid in the serial-bus data register. see table 4 ? 24 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name serial-bus control and status type rw r r r rc rw rc rc default 0 0 0 0 0 0 0 0 register: serial-bus control and status offset: b3h (function 0) type: read-only, read/write, read/clear default: 00h table 4 ? 24. serial-bus control and status register description bit signal type function 7 prot_sel rw protocol select. when bit 7 is set, the send-byte protocol is used on write requests and the receive-byte protocol is used on read commands. the word-address byte in the serial-bus index register (pci offset b1h, see section 4.46) is not output by the pci1520 when bit 7 is set. 6 rsvd r reserved. bit 6 returns 0 when read. 5 reqbusy r requested serial-bus access busy. bit 5 indicates that a requested serial-bus access (byte read or write) is in progress. a request is made, and bit 5 is set, by writing to the serial-bus slave address register (pci offset b2h, see section 4.47). bit 5 must be polled on reads from the serial interface. after the byte read access has been requested, the read data is valid in the serial-bus data register. 4 rombusy r serial eeprom busy status. bit 4 indicates the status of the pci1520 serial eeprom circuitry. bit 4 is set during the loading of the subsystem id and other default values from the serial-bus eeprom. 0 = serial eeprom circuitry is not busy 1 = serial eeprom circuitry is busy 3 sbdetect rc serial-bus detect. when bit 3 is set, it indicates that the serial-bus interface is detected. a pulldown resistor must be implemented on the latch terminal for bit 3 to be set. if bit 3 is reset, then the mfunc4 and mfunc1 terminals can be used for alternate functions such as general-purpose inputs and outputs. 0 = serial-bus interface not detected 1 = serial-bus interface detected 2 sbtest rw serial-bus test. when bit 2 is set, the serial-bus clock frequency is increased for test purposes. 0 = serial-bus clock at normal operating frequency, 100 khz (default) 1 = serial-bus clock frequency increased for test purposes 1 req_err rc requested serial-bus access error. bit 1 indicates when a data error occurs on the serial interface during a requested cycle, and can be set due to a missing acknowledge. bit 1 is cleared by a writeback of 1. 0 = no error detected during user-requested byte read or write cycle 1 = data error detected during user-requested byte read or write cycle 0 rom_err rc eeprom data-error status. bit 0 indicates when a data error occurs on the serial interface during the auto-load from the serial-bus eeprom, and can be set due to a missing acknowledge. bit 0 is also set on invalid eeprom data formats. see section 3.6.1, serial bus interface implementation , for details on eeprom data format. bit 0 is cleared by a writeback of 1. 0 = no error detected during auto-load from serial-bus eeprom 1 = data error detected during auto-load from serial-bus eeprom
5 ? 1 5 exca compatibility registers (functions 0 and 1) the exca registers implemented in the pci1520 are register-compatible with the intel 82365sl ? df pcmcia controller. exca registers are identified by an offset value that is compatible with the legacy i/o index/data scheme used on the intel 82365 isa controller. the exca registers are accessed through this scheme by writing the register offset value into the index register (i/o base) and reading or writing the data register (i/o base + 1). the i/o base address used in the index/data scheme is programmed in the pc card 16-bit i/f legacy-mode base address register (pci offset 44h, see section 4.28), which is shared by both card sockets. the offsets from this base address run contiguously from 00h to 3fh for socket a, and from 40h to 7fh for socket b. see figure 5 ? 1 for an exca i/o mapping illustration. cardbus socket/exca base address 16-bit legacy-mode base address 10h 44h 00h 3fh offset index host i/o space data pc card a exca registers pc card b exca registers 40h 7fh note: the 16-bit legacy mode base address register is shared by functions 0 and 1 as indicated by the shading. pci1520 configuration registers offset figure 5 ? 1. exca register access through i/o the ti pci1520 also provides a memory-mapped alias of the exca registers by directly mapping them into pci memory space. they are located through the cardbus socket/exca base-address register (pci offset 10h, see section 4.12) at memory offset 800h. each socket has a separate base address programmable by function. see figure 5 ? 2 for an exca memory mapping illustration. note that memory offsets are 800h ? 844h for both functions 0 and 1. this illustration also identifies the cardbus socket register mapping, which is mapped into the same 4-k window at memory offset 00h.
5 ? 2 cardbus socket/exca base address 16-bit legacy-mode base address 10h 44h note: the cardbus socket/exca base address mode register is separate for functions 0 and 1. pci1520 configuration registers cardbus socket a registers host memory space 00h exca registers card a 20h 800h 844h offset cardbus socket b registers host memory space 00h exca registers card b 20h 800h 844h offset offset figure 5 ? 2. exca register access through memory the interrupt registers in the exca register set, as defined by the 82365sl ? dl specification, control such card functions as reset, type, interrupt routing, and interrupt enables. special attention must be paid to the interrupt routing registers and the host interrupt signaling method selected for the pci1520 to ensure that all possible pci1520 interrupts can potentially be routed to the programmable interrupt controller. the exca registers that are critical to the interrupt signaling are the exca interrupt and general control register (exca offset 03h/43h/803h, see section 5.4) and the exca card status-change interrupt configuration register (05h/45h/805h, see section 5.6). access to i/o mapped 16-bit pc cards is available to the host system via two exca i/o windows. these are regions of host i/o address space into which the card i/o space is mapped. these windows are defined by start, end, and offset addresses programmed in the exca registers described in this section. i/o windows have byte granularity. access to memory mapped 16-bit pc cards is available to the host system via five exca memory windows. these are regions of host memory space into which the card memory space is mapped. these windows are defined by start, end, and offset addresses programmed in the exca registers described in this section. table 5 ? 1 identifies each exca register and its respective exca offset. memory windows have 4-kbyte granularity.
5 ? 3 table 5 ? 1. exca registers and offsets e x ca register name pci memory address exca offset (hex) e x ca register name pci memory address offset (hex) card a card b identification and revision 800 00 40 interface status 801 01 41 power control 802 02 42 interrupt and general control 803 03 43 card status change 804 04 44 card status-change interrupt configuration 805 05 45 address window enable 806 06 46 i / o window control 807 07 47 i / o window 0 start-address low byte 808 08 48 i / o window 0 start-address high byte 809 09 49 i / o window 0 end-address low byte 80a 0a 4a i / o window 0 end-address high byte 80b 0b 4b i / o window 1 start-address low byte 80c 0c 4c i / o window 1 start-address high byte 80d 0d 4d i / o window 1 end-address low byte 80e 0e 4e i / o window 1 end-address high byte 80f 0f 4f memory window 0 start-address low byte 810 10 50 memory window 0 start-address high byte 811 11 51 memory window 0 end-address low byte 812 12 52 memory window 0 end-address high byte 813 13 53 memory window 0 offset-address low byte 814 14 54 memory window 0 offset-address high byte 815 15 55 card detect and general control 816 16 56 reserved 817 17 57 memory window 1 start-address low byte 818 18 58 memory window 1 start-address high byte 819 19 59 memory window 1 end-address low byte 81a 1a 5a memory window 1 end-address high byte 81b 1b 5b memory window 1 offset-address low byte 81c 1c 5c memory window 1 offset-address high byte 81d 1d 5d global control 81e 1e 5e reserved 81f 1f 5f memory window 2 start-address low byte 820 20 60 memory window 2 start-address high byte 821 21 61 memory window 2 end-address low byte 822 22 62 memory window 2 end-address high byte 823 23 63 memory window 2 offset-address low byte 824 24 64 memory window 2 offset-address high byte 825 25 65 reserved 826 26 66 reserved 827 27 67 memory window 3 start-address low byte 828 28 68 memory window 3 start-address high byte 829 29 69 memory window 3 end-address low byte 82a 2a 6a
5 ? 4 table 5 ? 1. exca registers and offsets (continued) e x ca register name pci memory address exca offset (hex) e x ca register name pci memory address offset (hex) card a card b memory window 3 end-address high byte 82b 2b 6b memory window 3 offset-address low byte 82c 2c 6c memory window 3 offset-address high byte 82d 2d 6d reserved 82e 2e 6e reserved 82f 2f 6f memory window 4 start-address low byte 830 30 70 memory window 4 start-address high byte 831 31 71 memory window 4 end-address low byte 832 32 72 memory window 4 end-address high byte 833 33 73 memory window 4 offset-address low byte 834 34 74 memory window 4 offset-address high byte 835 35 75 i/o window 0 offset-address low byte 836 36 76 i/o window 0 offset-address high byte 837 37 77 i/o window 1 offset-address low byte 838 38 78 i/o window 1 offset-address high byte 839 39 79 reserved 83a 3a 7a reserved 83b 3b 7b reserved 83c 3c 7c reserved 83d 3d 7d reserved 83e 3e 7e reserved 83f 3f 7f memory window page 0 840 ? ? memory window page 1 841 ? ? memory window page 2 842 ? ? memory window page 3 843 ? ? memory window page 4 844 ? ? a bit description table, typically included when a register contains bits of more than one type or purpose, indicates bit field names, which appear in the signal column; a detailed field description, which appears in the function column; and field access tags, which appear in the type column of the bit description table. table 4 ? 2 describes the field access tags.
5 ? 5 5.1 exca identification and revision register the exca identification and revision register provides host software with information on 16-bit pc card support and intel 82365sl-df compatibility. this register is read-only or read/write, depending on the setting of bit 5 (subsysrw) in the system control register (pci offset 80h, see section 4.29). see table 5 ? 2 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca identification and revision type r r rw rw rw rw rw rw default 1 0 0 0 0 1 0 0 register: exca identification and revision offset: cardbus socket address + 800h; card a exca offset 00h card b exca offset 40h type: read-only, read/write default: 84h table 5 ? 2. exca identification and revision register description bit signal type function 7 ? 6 iftype r interface type. these bits, which are hardwired as 10b, identify the 16-bit pc card support provided by the pci1520. the pci1520 supports both i/o and memory 16-bit pc cards. 5 ? 4 rsvd rw reserved. bits 5 and 4 can be used for intel 82365sl-df emulation. 3 ? 0 365rev rw intel 82365sl-df revision. this field stores the intel 82365sl-df revision supported by the pci1520. host software can read this field to determine compatibility to the intel 82365sl-df register set. writing 0010b to this field puts the controller in 82365sl mode.
5 ? 6 5.2 exca interface status register the exca interface status register provides information on the current status of the pc card interface. an x in the default bit value indicates that the value of the bit after reset depends on the state of the pc card interface. see table 5 ? 3 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca interface status type r r r r r r r r default 0 0 x x x x x x register: exca interface status offset: cardbus socket address + 801h; card a exca offset 01h card b exca offset 41h type: read-only default: 00xx xxxxb table 5 ? 3. exca interface status register description bit signal type function 7 rsvd r reserved. bit 7 returns 0 when read. 6 cardpwr r card power. bit 6 indicates the current power status of the pc card socket. this bit reflects how the exca power control register (exca offset 02h/42h/802h, see section 5.3) is programmed. bit 6 is encoded as: 0 = v cc and v pp to the socket turned off (default) 1 = v cc and v pp to the socket turned on 5 ready r ready. bit 5 indicates the current status of the ready signal at the pc card interface. 0 = pc card not ready for data transfer 1 = pc card ready for data transfer 4 cardwp r card write protect (wp). bit 4 indicates the current status of wp at the pc card interface. this signal reports to the pci1520 whether or not the memory card is write protected. furthermore, write protection for an entire pci1520 16-bit memory window is available by setting the appropriate bit in the memory window offset-address high-byte register. 0 = wp is 0. pc card is read/write. 1 = wp is 1. pc card is read-only. 3 cdetect2 r card detect 2. bit 3 indicates the status of cd2 at the pc card interface. software may use this and bit 2 (cdetect1) to determine if a pc card is fully seated in the socket. 0 = cd2 is 1. no pc card is inserted. 1 = cd2 is 0. pc card is at least partially inserted. 2 cdetect1 r card detect 1. bit 2 indicates the status of cd1 at the pc card interface. software may use this and bit 3 (cdetect2) to determine if a pc card is fully seated in the socket. 0 = cd1 is 1. no pc card is inserted. 1 = cd1 is 0. pc card is at least partially inserted. 1 ? 0 bvdstat r battery voltage detect. when a 16-bit memory card is inserted, the field indicates the status of the battery voltage detect signals (bvd1, bvd2) at the pc card interface, where bit 1 reflects the bvd2 status and bit 0 reflects bvd1. 00 = battery dead 01 = battery dead 10 = battery low; warning 11 = battery good when a 16-bit i/o card is inserted, this field indicates the status of spkr (bit 1) and stschg (bit 0) at the pc card interface. in this case, the two bits in this field directly reflect the current state of these card outputs.
5 ? 7 5.3 exca power control register the exca power control register provides pc card power control. bit 7 (coe) of this register controls the 16-bit output enables on the socket interface, and can be used for power management in 16-bit pc card applications. see table 5 ? 4 and table 5 ? 5 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca power control type rw r r rw rw r rw rw default 0 0 0 0 0 0 0 0 register: exca power control offset: cardbus socket address + 802h; card a exca offset 02h card b exca offset 42h type: read-only, read/write default: 00h table 5 ? 4. exca power control register description ? 82365sl support bit signal type function 7 coe rw card output enable. bit 7 controls the state of all of the 16-bit outputs on the pci1520. this bit is encoded as: 0 = 16-bit pc card outputs disabled (default) 1 = 16-bit pc card outputs enabled 6 rsvd r reserved. bit 6 returns 0 when read. 5 autopwrswen rw auto power switch enable. 0 = automatic socket power switching based on card detects is disabled. 1 = automatic socket power switching based on card detects is enabled. 4 capwren rw pc card power enable. 0 = v cc = no connection 1 = v cc is enabled and controlled by bit 2 (excapower) of the system control register (pci offset 80h, see section 4.29). 3 ? 2 rsvd r reserved. bits 3 and 2 return 0s when read. 1 ? 0 excavpp rw pc card v pp power control. bits 1 and 0 are used to request changes to card v pp . the pci1520 ignores this field unless v cc to the socket is enabled. this field is encoded as: 00 = no connection (default) 01 = v cc 10 = 12 v 11 = reserved table 5 ? 5. exca power control register description ? 82365sl-df support bit signal type function 7 coe rw card output enable. bit 7 controls the state of all of the 16-bit outputs on the pci1520. this bit is encoded as: 0 = 16-bit pc card outputs disabled (default) 1 = 16-bit pc card outputs enabled 6 ? 5 rsvd r reserved. bits 6 and 5 return 0s when read. 4 ? 3 excavcc rw v cc . bits 4 and 3 are used to request changes to card v cc . this field is encoded as: 00 = 0 v (default) 01 = 0 v reserved 10 = 5 v 11 = 3.3 v 2 rsvd r reserved. bit 2 returns 0 when read. 1 ? 0 excavpp rw v pp . bits 1 and 0 are used to request changes to card v pp . the pci1520 ignores this field unless v cc to the socket is enabled. this field is encoded as: 00 = no connection (default) 01 = v cc 10 = 12 v 11 = reserved
5 ? 8 5.4 exca interrupt and general control register the exca interrupt and general control register controls interrupt routing for i/o interrupts, as well as other critical 16-bit pc card functions. see table 5 ? 6 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca interrupt and general control type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: exca interrupt and general control offset: cardbus socket address + 803h; card a exca offset 03h card b exca offset 43h type: read/write default: 00h table 5 ? 6. exca interrupt and general control register description bit signal type function 7 ringen rw card ring indicate enable. bit 7 enables the ring indicate function of bvd1/ri . this bit is encoded as: 0 = ring indicate disabled (default) 1 = ring indicate enabled 6 reset rw card reset. bit 6 controls the 16-bit pc card reset, and allows host software to force a card reset. bit 6 affects 16-bit cards only. this bit is encoded as: 0 = reset signal asserted (default) 1 = reset signal deasserted 5 cardtype rw card type. bit 5 indicates the pc card type. this bit is encoded as: 0 = memory pc card installed (default) 1 = i/o pc card installed 4 cscroute rw pci interrupt csc routing enable bit. when bit 4 is set (high), the card status change interrupts are routed to pci interrupts. when low, the card status change interrupts are routed using bits 7 ? 4 (cscselect field) in the exca card status-change interrupt configuration register (exca offset 05h/45h/805h, see section 5.6). this bit is encoded as: 0 = csc interrupts are routed by exca registers (default). 1 = csc interrupts are routed to pci interrupts. 3 ? 0 intselect rw card interrupt select for i/o pc card functional interrupts. bits 3 ? 0 select the interrupt routing for i/o pc card functional interrupts. this field is encoded as: 0000 = no interrupt routing (default). csc interrupts are routed to pci interrupts. this bit setting is ored with bit 4 (cscroute) for backward compatibility. 0001 = irq1 enabled 0010 = smi enabled 0011 = irq3 enabled 0100 = irq4 enabled 0101 = irq5 enabled 0100 = irq6 enabled 0111 = irq7 enabled 1000 = irq8 enabled 1001 = irq9 enabled 1010 = irq10 enabled 1011 = irq11 enabled 1100 = irq12 enabled 1101 = irq13 enabled 1110 = irq14 enabled 1111 = irq15 enabled
5 ? 9 5.5 exca card status-change register the exca card status-change register controls interrupt routing for i/o interrupts as well as other critical 16-bit pc card functions. the register enables these interrupt sources to generate an interrupt to the host. when the interrupt source is disabled, the corresponding bit in this register always reads 0. when an interrupt source is enabled, the corresponding bit in this register is set to indicate that the interrupt source is active. after generating the interrupt to the host, the interrupt service routine must read this register to determine the source of the interrupt. the interrupt service routine is responsible for resetting the bits in this register as well. resetting a bit is accomplished by one of two methods: a read of this register or an explicit write back of 1 to the status bit. the choice of these two methods is based on bit 2 (interrupt flag clear mode select) in the exca global control register (exca offset 1e/5e/81e, see section 5.20). see table 5 ? 7 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca card status-change type r r r r r r r r default 0 0 0 0 0 0 0 0 register: exca card status-change offset: cardbus socket address + 804h; card a exca offset 04h card b exca offset 44h type: read-only default: 00h table 5 ? 7. exca card status-change register description bit signal type function 7 ? 4 rsvd r reserved. bits 7 ? 4 return 0s when read. 3 cdchange r card detect change. bit 3 indicates whether a change on cd1 or cd2 occurred at the pc card interface. this bit is encoded as: 0 = no change detected on either cd1 or cd2 1 = change detected on either cd1 or cd2 2 readychange r ready change. when a 16-bit memory is installed in the socket, bit 2 includes whether the source of a pci1520 interrupt was due to a change on ready at the pc card interface, indicating that the pc card is now ready to accept new data. this bit is encoded as: 0 = no low-to-high transition detected on ready (default) 1 = detected low-to-high transition on ready when a 16-bit i/o card is installed, bit 2 is always 0. 1 batwarn r battery warning change. when a 16-bit memory card is installed in the socket, bit 1 indicates whether the source of a pci1520 interrupt was due to a battery-low warning condition. this bit is encoded as: 0 = no battery warning condition (default) 1 = detected battery warning condition when a 16-bit i/o card is installed, bit 1 is always 0. 0 batdead r battery dead or status change. when a 16-bit memory card is installed in the socket, bit 0 indicates whether the source of a pci1520 interrupt was due to a battery dead condition. this bit is encoded as: 0 = stschg deasserted (default) 1 = stschg asserted ring indicate. when the pci1520 is configured for ring indicate operation, bit 0 indicates the status of ri .
5 ? 10 5.6 exca card status-change interrupt configuration register the exca card status-change interrupt configuration register controls interrupt routing for card status-change interrupts, as well as masking csc interrupt sources. see table 5 ? 8 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca status-change-interrupt configuration type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: exca card status-change interrupt configuration offset: cardbus socket address + 805h; card a exca offset 05h card b exca offset 45h type: read/write default: 00h table 5 ? 8. exca card status-change interrupt configuration register description bit signal type function 7 ? 4 cscselect rw interrupt select for card status change. bits 7 ? 4 select the interrupt routing for card status-change interrupts. 0000 = csc interrupts routed to pci interrupts if bit 5 (csc) of the diagnostic register (pci offset 93h, see section 4.34) is set to 1. in this case bit 4 (cscroute) of the exca interrupt and general control register (exca offset 03h/43h/803h, see section 5.4) is a don ? t care. this is the default setting. 0000 = no isa interrupt routing if bit 5 (csc) of the diagnostic register is set to 0 (see section 4.34). in this case, csc interrupts are routed to pci interrupts by setting bit 4 (cscroute) of the exca interrupt and general control register (exca offset 03h/43h/803h, see section 5.4) to 1. this field is encoded as: 0000 = no interrupt routing (default) 1000 = irq8 enabled 0001 = irq1 enabled 1001 = irq9 enabled 0010 = smi enabled 1010 = irq10 enabled 0011 = irq3 enabled 1011 = irq11 enabled 0100 = irq4 enabled 1100 = irq12 enabled 0101 = irq5 enabled 1101 = irq13 enabled 0110 = irq6 enabled 1110 = irq14 enabled 0111 = irq7 enabled 1111 = irq15 enabled 3 cden rw card detect enable. bit 3 enables interrupts on cd1 or cd2 changes. this bit is encoded as: 0 = disables interrupts on cd1 or cd2 line changes (default) 1 = enables interrupts on cd1 or cd2 line changes 2 readyen rw ready enable. bit 2 enables/disables a low-to-high transition on pc card ready to generate a host interrupt. this interrupt source is considered a card status change. this bit is encoded as: 0 = disables host interrupt generation (default) 1 = enables host interrupt generation 1 batwarnen rw battery warning enable. bit 1 enables/disables a battery warning condition to generate a csc interrupt. this bit is encoded as: 0 = disables host interrupt generation (default) 1 = enables host interrupt generation 0 batdeaden rw battery dead enable. bit 0 enables/disables a battery dead condition on a memory pc card or assertion of the stschg i/o pc card signal to generate a csc interrupt. 0 = disables host interrupt generation (default) 1 = enables host interrupt generation
5 ? 11 5.7 exca address window enable register the exca address window enable register enables/disables the memory and i/o windows to the 16-bit pc card. by default, all windows to the card are disabled. the pci1520 does not acknowledge pci memory or i/o cycles to the card if the corresponding enable bit in this register is 0, regardless of the programming of the memory or i/o window start/end/offset address registers. see table 5 ? 9 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca address window enable type rw rw r rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: exca address window enable offset: cardbus socket address + 806h; card a exca offset 06h card b exca offset 46h type: read-only, read/write default: 00h table 5 ? 9. exca address window enable register description bit signal type function 7 iowin1en rw i/o window 1 enable. bit 7 enables/disables i/o window 1 for the pc card. this bit is encoded as: 0 = i/o window 1 disabled (default) 1 = i/o window 1 enabled 6 iowin0en rw i/o window 0 enable. bit 6 enables/disables i/o window 0 for the pc card. this bit is encoded as: 0 = i/o window 0 disabled (default) 1 = i/o window 0 enabled 5 rsvd r reserved. bit 5 returns 0 when read. 4 memwin4en rw memory window 4 enable. bit 4 enables/disables memory window 4 for the pc card. this bit is encoded as: 0 = memory window 4 disabled (default) 1 = memory window 4 enabled 3 memwin3en rw memory window 3 enable. bit 3 enables/disables memory window 3 for the pc card. this bit is encoded as: 0 = memory window 3 disabled (default) 1 = memory window 3 enabled 2 memwin2en rw memory window 2 enable. bit 2 enables/disables memory window 2 for the pc card. this bit is encoded as: 0 = memory window 2 disabled (default) 1 = memory window 2 enabled 1 memwin1en rw memory window 1 enable. bit 1 enables/disables memory window 1 for the pc card. this bit is encoded as: 0 = memory window 1 disabled (default) 1 = memory window 1 enabled 0 memwin0en rw memory window 0 enable. bit 0 enables/disables memory window 0 for the pc card. this bit is encoded as: 0 = memory window 0 disabled (default) 1 = memory window 0 enabled
5 ? 12 5.8 exca i/o window control register the exca i/o window control register contains parameters related to i/o window sizing and cycle timing. see table 5 ? 10 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca i/o window control type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: exca i /o window control offset: cardbus socket address + 807h; card a exca offset 07h card b exca offset 47h type: read/write default: 00h table 5 ? 10. exca i /o window control register description bit signal type function 7 waitstate1 rw i/o window 1 wait state. bit 7 controls the i/o window 1 wait state for 16-bit i/o accesses. bit 7 has no effect on 8-bit accesses. this wait-state timing emulates the isa wait state used by the intel 82365sl-df. this bit is encoded as: 0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent isa wait state. 6 zerows1 rw i/o window 1 zero wait state. bit 6 controls the i/o window 1 wait state for 8-bit i/o accesses. bit 6 has no effect on 16-bit accesses. this wait-state timing emulates the isa wait state used by the intel 82365sl-df. this bit is encoded as: 0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three isa cycles. 5 iois16w1 rw i/o window 1 iois16 source. bit 5 controls the i/o window 1 automatic data sizing feature that uses iois16 from the pc card to determine the data width of the i/o data transfer. this bit is encoded as: 0 = window data width determined by datasize1, bit 4 (default). 1 = window data width determined by iois16 . 4 datasize1 rw i/o window 1 data size. bit 4 controls the i/o window 1 data size. bit 4 is ignored if bit 5 (iosis16w1) is set. this bit is encoded as: 0 = window data width is 8 bits (default). 1 = window data width is 16 bits. 3 waitstate0 rw i/o window 0 wait state. bit 3 controls the i/o window 0 wait state for 16-bit i/o accesses. bit 3 has no effect on 8-bit accesses. this wait-state timing emulates the isa wait state used by the intel 82365sl-df. this bit is encoded as: 0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent isa wait state. 2 zerows0 rw i/o window 0 zero wait state. bit 2 controls the i/o window 0 wait state for 8-bit i/o accesses. bit 2 has no effect on 16-bit accesses. this wait-state timing emulates the isa wait state used by the intel 82365sl-df. this bit is encoded as: 0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three isa cycles. 1 iois16w0 rw i/o window 0 iois16 source. bit 1 controls the i/o window 0 automatic data sizing feature that uses iois16 from the pc card to determine the data width of the i/o data transfer. this bit is encoded as: 0 = window data width is determined by datasize0, bit 0 (default). 1 = window data width is determined by iois16 . 0 datasize0 rw i/o window 0 data size. bit 0 controls the i/o window 0 data size. bit 0 is ignored if bit 1 (iosis16w0) is set. this bit is encoded as: 0 = window data width is 8 bits (default). 1 = window data width is 16 bits.
5 ? 13 5.9 exca i/o windows 0 and 1 start-address low-byte registers these registers contain the low byte of the 16-bit i/o window start address for i/o windows 0 and 1. the 8 bits of these registers correspond to the lower 8 bits of the start address. bit 7 6 5 4 3 2 1 0 name exca i/o windows 0 and 1 start-address low-byte type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: exca i/o window 0 start-address low-byte offset: cardbus socket address + 808h; card a exca offset 08h card b exca offset 48h register: exca i/o window 1 start-address low-byte offset: cardbus socket address + 80ch; card a exca offset 0ch card b exca offset 4ch type: read/write default: 00h 5.10 exca i/o windows 0 and 1 start-address high-byte registers these registers contain the high byte of the 16-bit i/o window start address for i/o windows 0 and 1. the 8 bits of these registers correspond to the upper 8 bits of the start address. bit 7 6 5 4 3 2 1 0 name exca i/o windows 0 and 1 start-address high-byte type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: exca i/o window 0 start-address high-byte offset: cardbus socket address + 809h; card a exca offset 09h card b exca offset 49h register: exca i/o window 1 start-address high-byte offset: cardbus socket address + 80dh; card a exca offset 0dh card b exca offset 4dh type: read/write default: 00h
5 ? 14 5.11 exca i/o windows 0 and 1 end-address low-byte registers these registers contain the low byte of the 16-bit i/o window end address for i/o windows 0 and 1. the 8 bits of these registers correspond to the lower 8 bits of the end address. bit 7 6 5 4 3 2 1 0 name exca i/o windows 0 and 1 end-address low-byte type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: exca i /o window 0 end-address low-byte offset: cardbus socket address + 80ah; card a exca offset 0ah card b exca offset 4ah register: exca i /o window 1 end-address low-byte offset: cardbus socket address + 80eh; card a exca offset 0eh card b exca offset 4eh type: read/write default: 00h 5.12 exca i/o windows 0 and 1 end-address high-byte registers these registers contain the high byte of the 16-bit i/o window end address for i/o windows 0 and 1. the 8 bits of these registers correspond to the upper 8 bits of the end address. bit 7 6 5 4 3 2 1 0 name exca i/o windows 0 and 1 end-address high-byte type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: exca i /o window 0 end-address high-byte offset: cardbus socket address + 80bh; card a exca offset 0bh card b exca offset 4bh register: exca i /o window 1 end-address high-byte offset: cardbus socket address + 80fh; card a exca offset 0fh card b exca offset 4fh type: read/write default: 00h
5 ? 15 5.13 exca memory windows 0 ? 4 start-address low-byte registers these registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. the 8 bits of these registers correspond to bits a19 ? a12 of the start address. bit 7 6 5 4 3 2 1 0 name exca memory windows 0 ? 4 start-address low-byte type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: exca memory window 0 start-address low-byte offset: cardbus socket address + 810h; card a exca offset 10h card b exca offset 50h register: exca memory window 1 start-address low-byte offset: cardbus socket address + 818h; card a exca offset 18h card b exca offset 58h register: exca memory window 2 start-address low-byte offset: cardbus socket address + 820h; card a exca offset 20h card b exca offset 60h register: exca memory window 3 start-address low-byte offset: cardbus socket address + 828h; card a exca offset 28h card b exca offset 68h register: exca memory window 4 start-address low-byte offset: cardbus socket address + 830h; card a exca offset 30h card b exca offset 70h type: read/write default: 00h
5 ? 16 5.14 exca memory windows 0 ? 4 start-address high-byte registers these registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. the lower 4 bits of these registers correspond to bits a23 ? a20 of the start address. in addition, the memory window data width and wait states are set in this register. see table 5 ? 11 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca memory windows 0 ? 4 start-address high-byte type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: exca memory window 0 start-address high-byte offset: cardbus socket address + 811h; card a exca offset 11h card b exca offset 51h register: exca memory window 1 start-address high-byte offset: cardbus socket address + 819h; card a exca offset 19h card b exca offset 59h register: exca memory window 2 start-address high-byte offset: cardbus socket address + 821h; card a exca offset 21h card b exca offset 61h register: exca memory window 3 start-address high-byte offset: cardbus socket address + 829h; card a exca offset 29h card b exca offset 69h register: exca memory window 4 start-address high-byte offset: cardbus socket address + 831h; card a exca offset 31h card b exca offset 71h type: read/write default: 00h table 5 ? 11. exca memory windows 0 ? 4 start-address high-byte registers description bit signal type function 7 datasize rw data size. bit 7 controls the memory window data width. this bit is encoded as: 0 = window data width is 8 bits (default). 1 = window data width is 16 bits. 6 zerowait rw zero wait state. bit 6 controls the memory window wait state for 8- and 16-bit accesses. this wait-state timing emulates the isa wait state used by the intel 82365sl-df. this bit is encoded as: 0 = 8- and 16-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three isa cycles. 16-bit cycles are reduced to equivalent of two isa cycles. 5 ? 4 scratch rw scratch pad bits. bits 5 and 4 have no effect on memory window operation. 3 ? 0 stahn rw start-address high nibble. bits 3 ? 0 represent the upper address bits a23 ? a20 of the memory window start address.
5 ? 17 5.15 exca memory windows 0 ? 4 end-address low-byte registers these registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. the 8 bits of these registers correspond to bits a19 ? a12 of the end address. bit 7 6 5 4 3 2 1 0 name exca memory windows 0 ? 4 end-address low-byte type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: exca memory window 0 end-address low-byte offset: cardbus socket address + 812h; card a exca offset 12h card b exca offset 52h register: exca memory window 1 end-address low-byte offset: cardbus socket address + 81ah; card a exca offset 1ah card b exca offset 5ah register: exca memory window 2 end-address low-byte offset: cardbus socket address + 822h; card a exca offset 22h card b exca offset 62h register: exca memory window 3 end-address low-byte offset: cardbus socket address + 82ah; card a exca offset 2ah card b exca offset 6ah register: exca memory window 4 end-address low-byte offset: cardbus socket address + 832h; card a exca offset 32h card b exca offset 72h type: read/write default: 00h
5 ? 18 5.16 exca memory windows 0 ? 4 end-address high-byte registers these registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. the lower 4 bits of these registers correspond to bits a23 ? a20 of the end address. in addition, the memory window wait states are set in this register. see table 5 ? 12 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca memory windows 0 ? 4 end-address high-byte type rw rw r r rw rw rw rw default 0 0 0 0 0 0 0 0 register: exca memory window 0 end-address high-byte offset: cardbus socket address + 813h; card a exca offset 13h card b exca offset 53h register: exca memory window 1 end-address high-byte offset: cardbus socket address + 81bh; card a exca offset 1bh card b exca offset 5bh register: exca memory window 2 end-address high-byte offset: cardbus socket address + 823h; card a exca offset 23h card b exca offset 63h register: exca memory window 3 end-address high-byte offset: cardbus socket address + 82bh; card a exca offset 2bh card b exca offset 6bh register: exca memory window 4 end-address high-byte offset: cardbus socket address + 833h; card a exca offset 33h card b exca offset 73h type: read-only, read/write default: 00h table 5 ? 12. exca memory windows 0 ? 4 end-address high-byte registers description bit signal type function 7 ? 6 memws rw wait state. bits 7 and 6 specify the number of equivalent isa wait states to be added to 16-bit memory accesses. the number of wait states added is equal to the binary value of these two bits. 5 ? 4 rsvd r reserved. bits 5 and 4 return 0s when read. 3 ? 0 endhn rw end-address high nibble. bits 3 ? 0 represent the upper address bits a23 ? a20 of the memory window end address.
5 ? 19 5.17 exca memory windows 0 ? 4 offset-address low-byte registers these registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. the 8 bits of these registers correspond to bits a19 ? a12 of the offset address. bit 7 6 5 4 3 2 1 0 name exca memory windows 0 ? 4 offset-address low-byte type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: exca memory window 0 offset-address low-byte offset: cardbus socket address + 814h; card a exca offset 14h card b exca offset 54h register: exca memory window 1 offset-address low-byte offset: cardbus socket address + 81ch; card a exca offset 1ch card b exca offset 5ch register: exca memory window 2 offset-address low-byte offset: cardbus socket address + 824h; card a exca offset 24h card b exca offset 64h register: exca memory window 3 offset-address low-byte offset: cardbus socket address + 82ch; card a exca offset 2ch card b exca offset 6ch register: exca memory window 4 offset-address low-byte offset: cardbus socket address + 834h; card a exca offset 34h card b exca offset 74h type: read/write default: 00h
5 ? 20 5.18 exca memory windows 0 ? 4 offset-address high-byte registers these registers contain the high 6 bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. the lower 6 bits of these registers correspond to bits a25 ? a20 of the offset address. in addition, the write protection and common/attribute memory configurations are set in this register. see table 5 ? 13 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca memory windows 0 ? 4 offset-address high-byte type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: exca memory window 0 offset-address high-byte offset: cardbus socket address + 815h; card a exca offset 15h card b exca offset 55h register: exca memory window 1 offset-address high-byte offset: cardbus socket address + 81dh; card a exca offset 1dh card b exca offset 5dh register: exca memory window 2 offset-address high-byte offset: cardbus socket address + 825h; card a exca offset 25h card b exca offset 65h register: exca memory window 3 offset-address high-byte offset: cardbus socket address + 82dh; card a exca offset 2dh card b exca offset 6dh register: exca memory window 4 offset-address high-byte offset: cardbus socket address + 835h; card a exca offset 35h card b exca offset 75h type: read/write default: 00h table 5 ? 13. exca memory windows 0 ? 4 offset-address high-byte registers description bit signal type function 7 winwp rw write protect. bit 7 specifies whether write operations to this memory window are enabled. this bit is encoded as: 0 = write operations are allowed (default). 1 = write operations are not allowed. 6 reg rw bit 6 specifies whether this memory window is mapped to card attribute or common memory. this bit is encoded as: 0 = memory window is mapped to common memory (default). 1 = memory window is mapped to attribute memory. 5 ? 0 offhb rw offset-address high byte. bits 5 ? 0 represent the upper address bits a25 ? a20 of the memory window offset address.
5 ? 21 5.19 exca card detect and general control register the exca card detect and general control register controls how the exca registers for the socket respond to card removal, as well as reports the status of vs1 and vs2 at the pc card interface. see table 5 ? 14 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca i/o card detect and general control type r r rw rw r r rw r default x x 0 0 0 0 0 0 register: exca card detect and general control offset: cardbus socket address + 816h; card a exca offset 16h card b exca offset 56h type: read-only, read/write default: xx00 0000b table 5 ? 14. exca card detect and general control register description bit signal type function 7 vs2stat r vs2 state. bit 7 reports the current state of vs2 at the pc card interface and, therefore, does not have a default value. 0 = vs2 low 1 = vs2 high 6 vs1stat r vs1 state. bit 6 reports the current state of vs1 at the pc card interface and, therefore, does not have a default value. 0 = vs1 low 1 = vs1 high 5 swcsc rw software card detect interrupt. if bit 3 (cden) in the exca card status-change interrupt configuration register (exca offset 05h/45h/805, see section 5.6) is set, then writing a 1 to bit 5 causes a card-detect card-status change interrupt for the associated card socket. if bit 3 (cden) in the exca card status-change-interrupt configuration register (exca offset 05h/45h/805, see section 5.6) is cleared to 0, then writing a 1 to bit 5 has no effect. a read operation of this bit always returns 0. 4 cdresume rw card detect resume enable. if bit 4 is set to 1, then once a card detect change has been detected on cd1 and cd2 inputs, ri_out goes from high to low. ri_out remains low until bit 0 (card status change) in the exca card status-change register is cleared (see section 5.5). if this bit is a 0, then the card detect resume functionality is disabled. 0 = card detect resume disabled (default) 1 = card detect resume enabled 3 ? 2 rsvd r reserved. bits 3 and 2 return 0s when read. 1 regconfig rw register configuration on card removal. bit 1 controls how the exca registers for the socket react to a card removal event. this bit is encoded as: 0 = no change to exca registers on card removal (default) 1 = reset exca registers on card removal 0 rsvd r reserved. bit 0 returns 0 when read.
5 ? 22 5.20 exca global control register the exca global control register controls both pc card sockets and is not duplicated for each socket. the host interrupt mode bits in this register are retained for intel 82365sl-df compatibility. see table 5 ? 15 for a complete description of the register contents. bit 7 6 5 4 3 2 1 0 name exca global control type r r r rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: exca global control offset: cardbus socket address + 81eh; card a exca offset 1eh card b exca offset 5eh type: read-only, read/write default: 00h table 5 ? 15. exca global control register description bit signal type function 7 ? 5 rsvd r reserved. bits 7 ? 5 return 0s when read. 4 intmodeb rw level/edge interrupt mode select ? card b. bit 4 selects the signaling mode for the pci1520 host interrupt for card b interrupts. this bit is encoded as: 0 = host interrupt is edge mode (default). 1 = host interrupt is level mode. 3 intmodea rw level/edge interrupt mode select ? card a. bit 3 selects the signaling mode for the pci1520 host interrupt for card a interrupts. this bit is encoded as: 0 = host interrupt is edge mode (default). 1 = host interrupt is level mode. 2 ifcmode rw interrupt flag clear mode select. bit 2 selects the interrupt flag clear mechanism for the flags in the exca card status change register (exca offset 04h/44h/804h, see section 5.5). this bit is encoded as: 0 = interrupt flags are cleared by read of csc register (default). 1 = interrupt flags are cleared by explicit writeback of 1. 1 cscmode rw card status change level/edge mode select. bit 1 selects the signaling mode for the pci1520 host interrupt for card status changes. this bit is encoded as: 0 = host interrupt is edge mode (default). 1 = host interrupt is level mode. 0 pwrdwn rw power-down mode select. when bit 0 is set to 1, the pci1520 is in power-down mode. in power-down mode, the pci1520 card outputs are high-impedance until an active cycle is executed on the card interface. following an active cycle, the outputs are again high-impedance. the pci1520 still receives functional interrupts and/or card status-change interrupts; however, an actual card access is required to wake up the interface. this bit is encoded as: 0 = power-down mode is disabled (default). 1 = power-down mode is enabled.
5 ? 23 5.21 exca i/o windows 0 and 1 offset-address low-byte registers these registers contain the low byte of the 16-bit i/o window offset address for i/o windows 0 and 1. the 8 bits of these registers correspond to the lower 8 bits of the offset address, and bit 0 is always 0. bit 7 6 5 4 3 2 1 0 name exca i/o windows 0 and 1 offset-address low-byte type rw rw rw rw rw rw rw r default 0 0 0 0 0 0 0 0 register: exca i/o window 0 offset-address low-byte offset: cardbus socket address + 836h; card a exca offset 36h card b exca offset 76h register: exca i/o window 1 offset-address low-byte offset: cardbus socket address + 838h; card a exca offset 38h card b exca offset 78h type: read-only, read/write default: 00h 5.22 exca i/o windows 0 and 1 offset-address high-byte registers these registers contain the high byte of the 16-bit i/o window offset address for i/o windows 0 and 1. the 8 bits of these registers correspond to the upper 8 bits of the offset address. bit 7 6 5 4 3 2 1 0 name exca i/o windows 0 and 1 offset-address high-byte type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: exca i/o window 0 offset-address high-byte offset: cardbus socket address + 837h; card a exca offset 37h card b exca offset 77h register: exca i/o window 1 offset-address high-byte offset: cardbus socket address + 839h; card a exca offset 39h card b exca offset 79h type: read/write default: 00h
5 ? 24 5.23 exca memory windows 0 ? 4 page registers the upper 8 bits of a 4-byte pci memory address are compared to the contents of this register when decoding addresses for 16-bit memory windows. each window has its own page register, all of which default to 00h. by programming this register to a nonzero value, host software can locate 16-bit memory windows in any 1 of 256 16-mbyte regions in the 4-gbyte pci address space. these registers are only accessible when the exca registers are memory-mapped; that is, these registers cannot be accessed using the index/data i/o scheme. bit 7 6 5 4 3 2 1 0 name exca memory windows 0 ? 4 page type rw rw rw rw rw rw rw rw default 0 0 0 0 0 0 0 0 register: exca memory windows 0 ? 4 page offset: cardbus socket address + 840h, 841h, 842h, 843h, 844h type: read/write default: 00h
6 ? 1 6 cardbus socket registers (functions 0 and 1) the 1997 pc card standard requires a cardbus socket controller to provide five 32-bit registers that report and control socket-specific functions. the pci1520 provides the cardbus socket/exca base-address register (pci offset 10h, see section 4.12) to locate these cardbus socket registers in pci memory address space. each socket has a separate base address register for accessing the cardbus socket registers (see figure 6 ? 1). table 6 ? 1 gives the location of the socket registers in relation to the cardbus socket/exca base address. the pci1520 implements an additional register at offset 20h that provides power management control for the socket. cardbus socket/exca base address 16-bit legacy-mode base address 10h 44h note: the cardbus socket/exca base address mode register is separate for functions 0 and 1. pci1520 configuration registers cardbus socket a registers host memory space 00h exca registers card a 20h 800h 844h offset cardbus socket b registers host memory space 00h exca registers card b 20h 800h 844h offset offset figure 6 ? 1. accessing cardbus socket registers through pci memory table 6 ? 1. cardbus socket registers register name offset socket event 00h socket mask 04h socket present-state 08h socket force event 0ch socket control 10h reserved 14h ? 1ch socket power-management 20h a bit description table, typically included when a register contains bits of more than one type or purpose, indicates bit field names, which appear in the signal column; a detailed field description, which appears in the function column; and field access tags, which appear in the type column of the bit description table. table 4 ? 2 describes the field access tags.
6 ? 2 6.1 socket event register the socket event register indicates a change in socket status has occurred. these bits do not indicate what the change is, only that one has occurred. software must read the socket present-state register (cb offset 08h, see section 6.3) for current status. each bit in this register can be cleared by writing a 1 to that bit. the bits in this register can be set to a 1 by software by writing a 1 to the corresponding bit in the socket force event register (cb offset 0ch, see section 6.4). all bits in this register are cleared by pci reset. they can be immediately set again, if, when coming out of pc card reset, the bridge finds the status unchanged (that is, cstschg reasserted or card detect is still true). software must clear this register before enabling interrupts. if it is not cleared when interrupts are enabled, then an interrupt is generated (but not masked) based on any bit set. see table 6 ? 2 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket event type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket event type r r r r r r r r r r r r r/c r/c r/c r/c default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: socket event offset: cardbus socket address + 00h type: read-only, read/write, read/clear default: 0000 0000h table 6 ? 2. socket event register description bit signal type function 31 ? 4 rsvd r reserved. bits 31 ? 4 return 0s when read. 3 pwrevent r/c power cycle. bit 3 is set when the pci1520 detects that bit 3 (pwrcycle) in the socket present-state register (cb offset 08h, see section 6.3) has changed state. this bit is cleared by writing a 1. 2 cd2event r/c ccd2 . bit 2 is set when the pci1520 detects that bit 2 (cdetect2) in the socket present-state register (cb offset 08h, see section 6.3) has changed state. this bit is cleared by writing a 1. 1 cd1event r/c ccd1 . bit 1 is set when the pci1520 detects that bit 1 (cdetect1) in the socket present-state register (cb offset 08h, see section 6.3) has changed state. this bit is cleared by writing a 1. 0 cstsevent r/c cstschg . bit 0 is set when bit 0 (cardsts) in the socket present-state register (cb offset 08h, see section 6.3) has changed state. for cardbus cards, bit 0 is set on the rising edge of cstschg . for 16-bit pc cards, bit 0 is set on both transitions of cstschg . this bit is reset by writing a 1.
6 ? 3 6.2 socket mask register the socket mask register allows software to control the cardbus card events that generate a status change interrupt. the state of these mask bits does not prevent the corresponding bits from reacting in the socket event register (cb offset 00h, see section 6.1). see table 6 ? 3 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket mask type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket mask type r r r r r r r r r r r r rw rw rw rw default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: socket mask offset: cardbus socket address + 04h type: read-only, read/write default: 0000 0000h table 6 ? 3. socket mask register description bit signal type function 31 ? 4 rsvd r reserved. bits 31 ? 4 return 0s when read. 3 pwrmask rw power cycle. bit 3 masks bit 3 (pwrcycle) in the socket present-state register (cb offset 08h, see section 6.3) from causing a status change interrupt. 0 = pwrcycle event does not cause csc interrupt (default). 1 = pwrcycle event causes csc interrupt. 2 ? 1 cdmask rw card detect mask. bits 2 and 1 mask bits 1 and 2 (cdetect1 and cdetect2) in the socket present-state register (cb offset 08h, see section 6.3) from causing a csc interrupt. 00 = insertion/removal does not cause csc interrupt (default). 01 = reserved (undefined) 10 = reserved (undefined) 11 = insertion/removal causes csc interrupt. 0 cstsmask rw cstschg mask. bit 0 masks bit 0 (cardsts) in the socket present-state register (cb offset 08h, see section 6.3) from causing a csc interrupt. 0 = cardsts event does not cause csc interrupt (default). 1 = cardsts event causes csc interrupt.
6 ? 4 6.3 socket present-state register the socket present-state register reports information about the socket interface. write transactions to the socket force event register (cb offset 0ch, see section 6.4) are reflected here, as well as general socket interface status. information about pc card v cc support and card type is only updated at each insertion. also note that the pci1520 uses ccd1 and ccd2 during card identification, and changes on these signals during this operation are not reflected in this register. see table 6 ? 4 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket present-state type r r r r r r r r r r r r r r r r default 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket present-state type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 x 0 0 0 x x x register: socket present-state offset: cardbus socket address + 08h type: read-only default: 3000 00xxh table 6 ? 4. socket present-state register description bit signal type function 31 yvsocket r yv socket. bit 31 indicates whether or not the socket can supply v cc = y.y v to pc cards. the pci1520 does not support y.y-v v cc ; therefore, this bit is always reset unless overridden by the socket force event register (cb offset 0ch, see section 6.4). this bit is hardwired to 0. 30 xvsocket r xv socket. bit 30 indicates whether or not the socket can supply v cc = x.x v to pc cards. the pci1520 does not support x.x-v v cc ; therefore, this bit is always reset unless overridden by the socket force event register (cb offset 0ch, see section 6.4). this bit is hardwired to 0. 29 3vsocket r 3-v socket. bit 29 indicates whether or not the socket can supply v cc = 3.3 v to pc cards. the pci1520 does support 3.3-v v cc ; therefore, this bit is always set unless overridden by the socket force event register (cb offset 0ch, see section 6.4). 28 5vsocket r 5-v socket. bit 28 indicates whether or not the socket can supply v cc = 5 v to pc cards. the pci1520 does support 5-v v cc ; therefore, this bit is always set unless overridden by the socket force event register (cb offset 0ch, see section 6.4). 27 zvsupport r zoomed-video support. this bit indicates whether or not the socket has support for zoomed video. 0 = zoomed video is not supported. 1 = zoomed video is supported. 26 ? 14 rsvd r reserved. bits 27 ? 14 return 0s when read. 13 yvcard r yv card. bit 13 indicates whether or not the pc card inserted in the socket supports v cc = y.y v. 0 = y.y-v v cc is not supported. 1 = y.y-v v cc is supported. 12 xvcard r xv card. bit 12 indicates whether or not the pc card inserted in the socket supports v cc = x.x v. 0 = x.x-v v cc is not supported. 1 = x.x-v v cc is supported. 11 3vcard r 3-v card. bit 11 indicates whether or not the pc card inserted in the socket supports v cc = 3.3 v. 0 = 3.3-v v cc is not supported. 1 = 3.3-v v cc is supported.
6 ? 5 table 6 ? 4. socket present-state register (continued) bit signal type function 10 5vcard r 5-v card. bit 10 indicates whether or not the pc card inserted in the socket supports v cc = 5 v. 0 = 5-v v cc is not supported. 1 = 5-v v cc is supported. 9 badvccreq r bad v cc request. bit 9 indicates that the host software has requested that the socket be powered at an invalid voltage. 0 = normal operation (default) 1 = invalid v cc request by host software 8 datalost r data lost. bit 8 indicates that a pc card removal event may have caused lost data because the cycle did not terminate properly or because write data still resides in the pci1520. 0 = normal operation (default) 1 = potential data loss due to card removal 7 notacard r not a card. bit 7 indicates that an unrecognizable pc card has been inserted in the socket. this bit is not updated until a valid pc card is inserted into the socket. 0 = normal operation (default) 1 = unrecognizable pc card detected 6 ireqcint r ready(ireq )//cint . bit 6 indicates the current status of ready(ireq )//cint at the pc card interface. 0 = ready(ireq )//cint low 1 = ready(ireq )//cint high 5 cbcard r cardbus card detected. bit 5 indicates that a cardbus pc card is inserted in the socket. this bit is not updated until another card interrogation sequence occurs (card insertion). 4 16bitcard r 16-bit card detected. bit 4 indicates that a 16-bit pc card is inserted in the socket. this bit is not updated until another card interrogation sequence occurs (card insertion). 3 pwrcycle r power cycle. bit 3 indicates the status of each card powering request. this bit is encoded as: 0 = socket powered down (default) 1 = socket powered up 2 cdetect2 r ccd2 . bit 2 reflects the current status of ccd2 at the pc card interface. changes to this signal during card interrogation are not reflected here. 0 = ccd2 low (pc card may be present) 1 = ccd2 high (pc card not present) 1 cdetect1 r ccd1 . bit 1 reflects the current status of ccd1 at the pc card interface. changes to this signal during card interrogation are not reflected here. 0 = ccd1 low (pc card may be present) 1 = ccd1 high (pc card not present) 0 cardsts r cstschg . bit 0 reflects the current status of cstschg at the pc card interface. 0 = cstschg low 1 = cstschg high
6 ? 6 6.4 socket force event register the socket force event register is used to force changes to the socket event register (cb offset 00h, see section 6.1) and the socket present-state register (see section 6.3). bit 14 (cvstest) in this register must be written when forcing changes that require card interrogation. see table 6 ? 5 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket force event type r r r r w r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket force event type r w w w w w w w w r w w w w w w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: socket force event offset: cardbus socket address + 0ch type: read-only, write-only default: 0000 0000h
6 ? 7 table 6 ? 5. socket force event register description bit signal type function 31 ? 28 rsvd r reserved. bits 31 ? 28 return 0s when read. 27 fzvsupport w zoomed-video support. this bit indicates whether or not the socket has support for zoomed video. 26 ? 15 rsvd r reserved. bits 26 ? 15 return 0s when read. 14 cvstest w card vs test. when bit 14 is set, the pci1520 re-interrogates the pc card, updates the socket present-state register (cb offset 08h, see section 6.3), and enables the socket control register (cb offset 10h, see section 6.5). 13 fyvcard w force yv card. write transactions to bit 13 cause bit 13 (yvcard) in the socket present-state register (cb offset 08h, see section 6.3) to be written. when set, this bit disables the socket control register (cb offset 10h, see section 6.5). 12 fxvcard w force xv card. write transactions to bit 12 cause bit 12 (xvcard) in the socket present-state register (cb offset 08h, see section 6.3) to be written. when set, this bit disables the socket control register (cb offset 10h, see section 6.5). 11 f3vcard w force 3-v card. write transactions to bit 11 cause bit 11 (3vcard) in the socket present-state register (cb offset 08h, see section 6.3) to be written. when set, this bit disables the socket control register (cb offset 10h, see section 6.5). 10 f5vcard w force 5-v card. write transactions to bit 10 cause bit 10 (5vcard) in the socket present-state register (cb offset 08h, see section 6.3) to be written. when set, this bit disables the socket control register (cb offset 10h, see section 6.5). 9 fbadvccreq w force bad v cc request. changes to bit 9 (badvccreq) in the socket present-state register (cb offset 08h, see section 6.3) can be made by writing to bit 9. 8 fdatalost w force data lost. write transactions to bit 8 cause bit 8 (datalost) in the socket present-state register (cb offset 08h, see section 6.3) to be written. 7 fnotacard w force not-a-card. write transactions to bit 7 cause bit 7 (notacard) in the socket present-state register (cb offset 08h, see section 6.3) to be written. 6 rsvd r reserved. bit 6 returns 0 when read. 5 fcbcard w force cardbus card. write transactions to bit 5 cause bit 5 (cbcard) in the socket present-state register (cb offset 08h, see section 6.3) to be written. 4 f16bitcard w force 16-bit card. write transactions to bit 4 cause bit 4 (16bitcard) in the socket present-state register (cb offset 08h, see section 6.3) to be written. 3 fpwrcycle w force power cycle. write transactions to bit 3 cause bit 3 (pwrevent) in the socket event register (cb offset 00h, see section 6.1) to be written, and bit 3 (pwrcycle) in the socket present-state register (cb offset 08h, see section 6.3) is unaffected. 2 fcdetect2 w force ccd2 . write transactions to bit 2 cause bit 2 (cd2event) in the socket event register (cb offset 00h, see section 6.1) to be written, and bit 2 (cdetect2) in the socket present-state register (cb offset 08h, see section 6.3) is unaffected. 1 fcdetect1 w force ccd1 . write transactions to bit 1 cause bit 1 (cd1event) in the socket event register (cb offset 00h, see section 6.1) to be written, and bit 1 (cdetect1) in the socket present-state register (cb offset 08h, see section 6.3) is unaffected. 0 fcardsts w force cstschg. write transactions to bit 0 cause bit 0 (cstsevent) in the socket event register (cb offset 00h, see section 6.1) to be written, and bit 0 (cardsts) in the socket present-state register (cb offset 08h, see section 6.3) is unaffected.
6 ? 8 6.5 socket control register the socket control register provides control of the voltages applied to the socket and instructions for the cb clkrun protocol. the pci1520 ensures that the socket is powered up only at acceptable voltages when a cardbus card is inserted. see table 6 ? 6 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket control type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket control type r r r r r r rw r rw rw rw rw r rw rw rw default 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 register: socket control offset: cardbus socket address + 10h type: read-only, read/write default: 0000 0400h table 6 ? 6. socket control register description bit signal type function 31 ? 12 rsvd r reserved. these bits return 0 when read. a write to these bits has no effect. 11 zv_activity r zoomed video activity. this bit returns 0 when the zven bits for both sockets are 0 (disabled). if either zven bit is set to 1, the zv_activity bit returns 1. 10 stdzvreg r standardized zoomed video register model support. this bit returns 1 by default when the stdzven bit (bit 0) in the diagnostic register is cleared (pci offset 93h, see section 4.34). 9 zven rw zoomed video enable. this bit enables zoomed video for this socket. 8 rsvd r reserved. this bit returns 0 when read. a write to this bit has no effect. 7 stopclk rw cb clkrun protocol instructions. 0 = cb clkrun protocol can only attempt to stop/slow the cb clock if the socket is idle and the pci clkrun protocol is preparing to stop/slow the pci bus clock. 1 = cb clkrun protocol can attempt to stop/slow the cb clock if the socket is idle. 6 ? 4 vccctrl rw v cc control. bits 6 ? 4 request card v cc changes. 000 = request power off (default) 100 = request v cc = x.x v 001 = reserved 101 = request v cc = y.y v 010 = request v cc = 5 v 110 = reserved 011 = request v cc = 3.3 v 111 = reserved 3 rsvd r reserved. bit 3 returns 0 when read. 2 ? 0 vppctrl rw v pp control. bits 2 ? 0 request card v pp changes. 000 = request power off (default) 100 = request v pp = x.x v 001 = request v pp = 12 v 101 = request v pp = y.y v 010 = request v pp = 5 v 110 = reserved 011 = request v pp = 3.3 v 111 = reserved
6 ? 9 6.6 socket power-management register this register provides power management control over the socket through a mechanism for slowing or stopping the clock on the card interface when the card is idle. see table 6 ? 7 for a complete description of the register contents. bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket power-management type r r r r r r r r r r r r r r r rw default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket power-management type r r r r r r r r r r r r r r r rw default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: socket power-management type: read-only, read/write offset: cardbus socket address + 20h default: 0000 0000h table 6 ? 7. socket power-management register description bit signal type function 31 ? 26 rsvd r reserved. bits 31 ? 26 return 0s when read. 25 sktacces r socket access status. this bit provides information on when a socket access has occurred. this bit is cleared by a read access. 0 = a pc card access has not occurred (default). 1 = a pc card access has occurred. 24 sktmode r socket mode status. this bit provides clock mode information. 0 = clock is operating normally. 1 = clock frequency has changed. 23 ? 17 rsvd r reserved. bits 23 ? 17 return 0s when read. 16 clkctrlen rw cardbus clock control enable. when bit 16 is set, bit 0 (clkctrl) is enabled. 0 = clock control is disabled (default). 1 = clock control is enabled. 15 ? 1 rsvd r reserved. bits 15 ? 1 return 0s when read. 0 clkctrl rw cardbus clock control. this bit determines whether the cb clkrun protocol stops or slows the cb clock during idle states. bit 16 (clkctrlen) enables this bit. 0 = allows cb clkrun protocol to stop the cb clock (default). 1 = allows cb clkrun protocol to slow the cb clock by a factor of 16.
7 ? 1 7 electrical characteristics 7.1 absolute maximum ratings over operating temperature ranges ? supply voltage range, v cc ? 0.5 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clamping voltage range, v ccp, v cca, v ccb ? 0.5 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i : pci, miscellaneous ? 0.5 v to v ccp + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . card a ? 0.5 to v cca + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . card b ? 0.5 to v ccb + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . fail safe ? 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o : pci, miscellaneous ? 0.5 v to v ccp + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . card a ? 0.5 to v cca + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . card b ? 0.5 to v ccb + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . fail safe ? 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0 or v i > v cc ) (see note 1) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc ) (see note 2) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditio ns is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. applies for external input and bidirectional buffers. v i > v cc does not apply to fail-safe terminals. pci terminals and miscellaneous terminals are measured with respect to v ccp instead of v cc . pc card terminals are measured with respect to v cca or v ccb . the limit specified applies for a dc condition. 2. applies for external output and bidirectional buffers. v o > v cc does not apply to fail-safe terminals. pci terminals and miscellaneous terminals are measured with respect to v ccp instead of v cc . pc card terminals are measured with respect to v cca or v ccb . the limit specified applies for a dc condition.
7 ? 2 7.2 recommended operating conditions (see note 3) operation min nom max unit v cc core voltage commercial 3.3 v 3 3.3 3.6 v v pci and miscellaneous i/o clamp commercial 3.3 v 3 3.3 3.6 v v ccp pci and miscellaneous i/o clam voltage commercial 5 v 4.75 5 5.25 v v cca pc c d i/o l lt commercial 3.3 v 3 3.3 3.6 v v cca v ccb pc card i/o clamp voltage commercial 5 v 4.75 5 5.25 v pci 3.3 v 0.5 v ccp v ccp pci 5 v 2 v ccp v ih ? high-level input voltage pc card 3.3 v 0.475 v cc(a/b) v cc(a/b) v v ih ? high level in ut voltage pc card 5 v 2.4 v cc(a/b) v miscellaneous ? 2 v cc pci 3.3 v 0 0.3 v ccp pci 5 v 0 0.8 v il ? low-level input voltage pc card 3.3 v 0 0.325 v cc(a/b) v v il ? low level in ut voltage pc card 5 v 0 0.8 v miscellaneous ? 0 0.8 pci 0 v ccp v i input voltage pc card 0 v cc(a/b) v v i in ut voltage miscellaneous ? 0 v cc v pci 0 v cc v o output voltage pc card 0 v cc v v o out ut voltage miscellaneous ? 0 v cc v t input transition time (t and t ) pci and pc card 1 4 ns t t input transition time (t r and t f ) miscellaneous ? 0 6 ns t a operating ambient temperature range pci1520i ? 40 25 85 c ? applies to external inputs and bidirectional buffers without hysteresis ? miscellaneous terminals are c11, c15, g18, h05, j15, l18, p07, p09, u08, and u11 for the ghk packaged device (suspend , grst , cdx , and vsx terminals). applies to external output buffers note 3: unused terminals (input or i/o) must be held high or low to prevent them from floating.
7 ? 3 7.3 electrical characteristics over recommended operating conditions (unless otherwise noted) parameter terminals operation test conditions min max unit pci 3.3 v i oh = ? 0.5 ma 0.9 v cc v pci 5 v i oh = ? 2 ma 2.4 v spkrout 3.3 v i oh = ? 0.5 ma 0.9 v cc v oh hi g h-level output volta g e spkrout 5 v i oh = ? 1 ma 2.4 v oh high-level out ut voltage pc card 3.3 v i oh = ? 0.15 ma 0.9 v cc pc card 5 v i oh = ? 0.15 ma 2.4 v miscellaneous i 4ma v 06 v miscellaneous i oh = ? 4 ma v cc ? 0.6 pci 3.3 v i ol = 1.5 ma 0.1 v cc pci 5 v i ol = 6 ma 0.55 pc card 3.3 v i ol = 0.7 ma 0.1 v cc v ol low-level output voltage pc card 5 v i ol = 0.7 ma 0.55 v ol g miscellaneous i ol = 4 ma 0.5 spkrout 3.3 v i ol = 1 ma 0.1 v cc spkrout 5 v i ol = 1 ma 0.55 i hi g h-impedance , low-level output output terminals 3.6 v v i = v cc ? 1 a i ozl high - im edance , low - level out ut current output terminals 5.25 v v i = v cc ? 1 a i hi g h-impedance , hi g h-level output output terminals 3.6 v v i = v cc ? 10 a i ozh high - im edance , high - level out ut current output terminals 5.25 v v i = v cc ? 25 a input terminals v i = gnd ? 1 i il low-level input current i/o terminals v i = gnd ? 10 a il low level in ut current pullup terminals v i = gnd ? 330 ? 10 i ih high level in p ut current input terminals 5.25 v v i = v cc ? 20 a i ih high-level input current i/o terminals 3.6 v v i = v cc ? 10 a i/o terminals 5.25 v v i = v cc ? 25 ? for pci and miscellaneous terminals, v i = v ccp . for pc card terminals, v i = v cc(a/b) . ? for i/o terminals, input leakage (i il and i ih ) includes i oz leakage of the disabled output. 7.4 pci clock/reset timing requirements over recommended ranges of supply voltage and operating free-air temperature parameter alternate symbol test conditions min max unit t c cycle time, pclk t cyc 30 ns t w(h) pulse duration (width), pclk high t high 11 ns t w(l) pulse duration (width), pclk low t low 11 ns t r , t f slew rate, pclk ? v/ ? t 1 4 v/ns t w pulse duration (width), prst t rst 1 ms t su setup time, pclk active at end of prst t rst-clk 100 s
7 ? 4 7.5 pci timing requirements over recommended ranges of supply voltage and operating free-air temperature this data manual uses the following conventions to describe time ( t ) intervals. the format is t a , where subscript a indicates the type of dynamic parameter being represented. one of the following is used: t pd = propagation delay time, t d (t en , t dis ) = delay time, t su = setup time, and t h = hold time. parameter alternate symbol test conditions min max unit t propagation delay time see note 4 pclk-to-shared signal valid delay time t val c l = 50 pf, 11 ns t pd propagation delay time, see note 4 pclk-to-shared signal invalid delay time t inv c l = 50 f , see note 4 2 ns t en enable time, high impedance-to-active delay time from pclk t on 2 ns t dis disable time, active-to-high impedance delay time from pclk t off 28 ns t su setup time before pclk valid t su 7 ns t h hold time after pclk high t h 0 ns note 4: pci shared signals are ad31 ? ad0, c/be3 ? c/be0 , frame , trdy , irdy , stop , idsel, devsel , and par.
8 ? 1 8 mechanical information the pci1520 is packaged in a 209-ball ghk bga package. the following shows the mechanical dimensions for the ghk package. ghk (s-pbga-n209) plastic ball grid array 19 14,40 typ 17 16 13 14 15 11 12 9 810 v u w r n p l m k t 7 5 6 3 4 h f g e c d 1 a b 2 j 18 seating plane 4145273 ? 2/b 12/98 sq 16,10 15,90 0,95 0,45 0,35 0,55 0,45 0,12 0,08 0,85 1,40 max 0,10 0,80 0,80 m 0,08 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. microstar bga ? configuration. microstar bga is a trademark of texas instruments.

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