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available si9185 vishay siliconix document number: 71765 s-50955?rev. e, 16-may-05 www.vishay.com 1 micropower 500-ma cmos ldo regulator with error flag/power-on-reset features input voltage 2 v to 6 v low 150-mv dropout at 500-ma load guaranteed 500-ma output current uses low esr ceramic output capacitor fast load and line transient response only 100- v(rms) noise with noise bypass capacitor 1- a maximum shutdown current built-in short circuit and thermal protection out-of-regulation error flag (power good or por) fixed 1.215-v, 1.5-v, 1.8-v, 2.5-v, 2.8-v, 3.0-v, 3.3-v, 5.0-v, or adjustable output voltage options other output voltages available by special order 1.1-w power dissipation thin, thermally enhanced mlp33 powerpak package applications laptop and palm computers desktop computers cellular phones pda, digital still cameras description the si9185 is a 500-ma cmos ldo (low dropout) voltage regulator. the device features ultra low ground current and dropout voltage to prolong battery life in portable electronics. the si9185 offers line/load transient response and ripple rejection superior to that of bipolar or bicmos ldo regulators, and is designed to drive lower cost ceramic, as well as tantalum, output capacitors. an external noise bypass capacitor connected to the device?s c noise pin will lower the ldo?s output noise for low noise applications. the si9185 also includes an out-of-regulation error flag. if a capacitor is connected to the device?s delay pin, the error flag output pin will generate a delayed power-on-reset signal. the device is guaranteed stable from maximum load current down to 0-ma load. the si9185 is available in both standard and lead (pb)-free mlp33 powerpak packages and is specified to operate over the industrial temperature range of ? 40 c to 85 c. mlp33 powerpak packaging allows enhanced heat transfer to the pc board. typical applications circuits figure 1. fixed output figure 2. adjustable output figure 3. low noise, full features application c noise sd 18 delay error 27 gnd sense/adj 36 v in v out 45 gnd v in 2.2 f 2.2 f v out si9185 c noise 18 delay error 27 gnd sense/adj 36 v in v out 45 gnd v in 2.2 f 2.2 f v out si9185 c noise 18 delay error 27 gnd sense/adj 36 v in v out 45 gnd v in 2.2 f 2.2 f v out si9185 por on/off 0.1 f 0.1 f 1 m sd sd
si9185 vishay siliconix www.vishay.com 2 document number: 71765 s-50955?rev. e, 16-may-05 absolute maximum ratings input v oltage, v in 6.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sd input voltage, v sd ? 0.3 v to v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output current, i out 500 ma continuous, short circuit protected . . . . . . . . output voltage, v out ? 0.3 v to v o(nom) + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . maximum junction temperature, t j(max) 150 c . . . . . . . . . . . . . . . . . . . . . . . storage temperature, t stg ? 55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . esd (human body model) 2 kv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation b 2.5 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . thermal impedance ( ja ) a (r ja )50 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (r jc )4 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes a. device mounted with all leads soldered or welded to pc board. (pc board?2? x 2?, 4-layer, fr4, 0.25 square inch spreading copper) b. derate 20 mw/ c above t a = 25 c stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratin gs only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating range input v oltage, v in 2 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage, v out (adjustable v ersion) 1.215 v to 5 v . . . . . . . . . . . . . . . r2 25 k to 150 k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating ambient temperature, t a ? 40 c to 85 c . . . . . . . . . . . . . . . . . . . . operating junction temperature, t j ? 40 c to 125 c . . . . . . . . . . . . . . . . . . . c in = 2.2 f, c out = 2.2 f (ceramic, x5r or x7r type) , c noise = 0.1 f (ceramic) c out range = 1 f to 10 f ( 10%, x5r or x7r type) c in c out specifications test conditions unless otherwise specified v v 1 v i 1 a limits ? 40 to 85 c parameter symbol v in = v out(nom) + 1 v, i out = 1 ma c in = 2.2 f, c out = 2.2 f, v sd = 1.5 v temp a min b typ c max b unit output voltage range adjustable v ersion full 1.215 5 v out p ut volta g e accurac y v out 1 ma i out 500 ma room ? 1.5 1.5 % v o( ) output voltage accuracy (fixed versions) out 1 ma i out 500 ma full ? 2.5 2.5 % v o(nom) feedback voltage (adj version) v adj room 1.191 1.215 1.239 v feedback voltage (adj version) v adj full 1.179 1.251 v line regulation (v adj v out 4 v) v out 100 v v from v in = v out + 1 v to v out + 2 v full ? 0.18 0.18 %/v line regulation (4 v v out 5 v) v in v out from v in = 5.5 v to 6 v full ? 0.18 0.18 %/v
si9185 vishay siliconix document number: 71765 s-50955?rev. e, 16-may-05 www.vishay.com 3 specifications limits ? 40 to 85 c test conditions unless otherwise specified v in = v out(nom) + 1 v, i out = 1 ma c in = 2.2 f, c out = 2.2 f, v sd = 1.5 v parameter unit max b typ c min b temp a test conditions unless otherwise specified v in = v out(nom) + 1 v, i out = 1 ma c in = 2.2 f, c out = 2.2 f, v sd = 1.5 v symbol i out = 10 ma room 5 20 dro p out volta g e d i out = 200 ma room 145 215 dropout voltage d (@v out(nom) 2 v) i out = 500 ma room 320 480 v in ? v out i out = 500 ma full 600 d in out i out = 200 ma room 115 175 dropout voltage d (@ v out(nom) 2.5 v ) i out = 500 ma room 250 400 (@v out(nom) 2 . 5 v) i out = 500 ma full 480 d i out = 200 ma room 90 135 mv dropout voltage d (@ v out(nom) 3.3 v ) v in ? v out i out = 500 ma room 200 300 mv (@v out(nom) 3 . 3 v) in out i out = 500 ma full 400 d i out = 200 ma room 60 100 dropout voltage d (@ v out(nom) 5 v ) v in ? v out i out = 500 ma room 150 210 (@v out(nom) 5 v) in out i out = 500 ma full 300 d i out = 200 ma room 170 250 dropout voltage d (@ v out(nom) 2 v , v in 2 v ) v in ? v out i out = 500 ma room 415 625 (@v out(nom) 2 v , v in 2 v) in out i out = 500 ma full 825 i out = 0 ma room 150 i out = 200 ma room 1000 ground pin current i gnd i out = 200 ma full 1500 a gnd i out = 500 ma room 2500 i out = 500 ma full 4000 shutdown supply current i in(off) v sd = 0 v room 0.1 1 a adj pin current i adj adj = 1.2 v room 5 100 na peak output current i o(peak) v out 0.95 x v out(nom) , t pw = 2 ms room 600 ma output noise voltage e n bw = 50 hz to 100 khz w/o c noise room 200 v (rms) output noise voltage e n bw = 50 hz to 100 khz i out = 150 ma c noise = 0.1 f room 100 v (rms) f = 1 khz room 60 ripple rejection v out / v in i out = 150 ma f = 10 khz room 60 db pp j out in out f = 100 khz room 40 dynamic line regulation v o(line) v in : v out(nom) + 1 v to v out(nom) + 2 v t r /t f = 5 s, i out = 500 ma room 10 mv dynamic load regulation v o(load) i out : 1 ma to 150 ma, t r /t f = 2 s room 30 mv v out turn on time t on v in = 4.3 v w/o c noise cap room 5 s v out turn-on-time t on v in = 4 . 3 v v out = 3.3 v c noise = 0.1 f room 2 ms thermal shutdown thermal shutdown junction temp t j(s/d) room 165 c thermal hysteresis t hyst room 20 c short circuit current i sc v out = 0 v room 800 ma shutdown input sd input voltage v ih high = regulator on (rising) full 1.5 v in v sd input voltage v il low = regulator off (falling) full 0.4 v
si9185 vishay siliconix www.vishay.com 4 document number: 71765 s-50955?rev. e, 16-may-05 specifications limits ? 40 to 85 c test conditions unless otherwise specified v in = v out(nom) + 1 v, i out = 1 ma c in = 2.2 f, c out = 2.2 f, v sd = 1.5 v parameter unit max b typ c min b temp a test conditions unless otherwise specified v in = v out(nom) + 1 v, i out = 1 ma c in = 2.2 f, c out = 2.2 f, v sd = 1.5 v symbol sd input current e i ih v sd = 0 v, regulator off room 0.01 a sd input current e i il v sd = 6 v, regulator on room 1.0 a shutdown hysteresis v hyst full 100 mv error output output high leakage i off error = v out(nom) full 0.01 2 a output low voltage g v ol i sink = 2 ma full 0.4 out-of-regulation error flag threshold voltage (rising) g v th full 0.93 x v out 0.95 x v out 0.97 x v out v hysteresis g v hyst room 2% x v out delay pin current source i delay room 1.2 2.2 3.0 a notes a. room = 25 c, full = ? 40 to 85 c. b. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum. c. typical values are for design aid only, not guaranteed nor subject to production testing. typical values for dropout voltage at v out 2 v are measured at v out = 3.3 v, while typical values for dropout voltage at v out < 2 v are measured at v out = 1.8 v. d. dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2% below the output voltage measured with a 1-v differential, provided that v in does not not drop below 2.0 v. when v out(nom) is less than 2.0 v, the output will be in regulation when 2.0 v ? v out(nom) is greater than the dropout voltage specified. e. the device?s shutdown pin includes a typical 6-m internal pull-down resistor connected to ground. f. v out is defined as the output voltage of the dut at 1 ma. g. the error output (low) function is guaranteed for v in 2.0 v. timing waveforms v in 0.95 v nom v out v out error v nom t delay figure 4. timing diagram for power-up t on
si9185 vishay siliconix document number: 71765 s-50955?rev. e, 16-may-05 www.vishay.com 5 pin configuration 2 3 4 8 7 6 5 c noise delay gnd v in sd error sense or adj v out top view 8 7 6 5 1 2 3 4 c noise delay gnd v in sd error sense or adj v out bottom view mlp33 powerpak 1 exposed pad mlp33 powerpak pin description pin number name function 1 c noise noise bypass pin. for low noise applications, a 0.01- f or larger ceramic capacitor should be connected from this pin to ground. 2 delay capacitor connected from this pin to ground will allow a delayed power-on-reset signal at the error (pin 7) output. refer to figure 4. 3 gnd ground pin. local ground for c noise and c out . 4 v in input supply pin. bypass this pin with a 2.2- f ceramic or tantalum capacitor to ground. 5 v out output voltage. connect c out between this pin and ground. 6 sense or adj for fixed output voltage versions, this pin should be connected to v out (pin 5). for adjustable output voltage version, this voltage feedback pin sets the output voltage via an external resistor divider. 7 error this open drain output is an error flag output which goes low when v out drops 5% below its nominal voltage. this pin also provides a power-on-reset signal if a capacitor is connected to the delay pin. 8 sd by applying less than 0.4 v to this pin, the device will be turned off. connect this pin to v in if unused. exposed pad the die substrate is attached to the exposed pad and must be electrically connected to gnd. ordering information standard part number lead (pb)-free part number marking voltage temperature package si9185dmp-12-t1 si9185dmp-12-t1?e3 8512 1.215 v si9185dmp-15-t1 si9185dmp-15-t1?e3 8515 1.50 v si9185dmp-18-t1 si9185dmp-18-t1?e3 8518 1.80 v si9185dmp-25-t1 si9185dmp-25-t1?e3 8525 2.50 v mlp33 si9185dmp-28-t1 si9185dmp-28-t1?e3 8528 2.80 v ? 40 to 85 c mlp33 powerpak si9185dmp-30-t1 si9185dmp-30-t1?e3 8530 3.00 v 40 to 85 c p ower pa k si9185dmp-33-t1 si9185dmp-33-t1?e3 8533 3.30 v si9185dmp-50-t1 si9185dmp-50-t1?e3 8550 5.00 v si9185dmp-ad-t1 si9185dmp-ad-t1?e3 85ad adjustable additional voltage options are available. eval kit temperature range board type si9185db ? 40 to 85 c surface mount
si9185 vishay siliconix www.vishay.com 6 document number: 71765 s-50955?rev. e, 16-may-05 typical characteristics (internally regulated, 25 c unless noted) 0 50 100 150 200 250 300 0 100 200 300 400 500 600 dropout v oltage vs. load current i load (ma) (mv) v drop 0 50 100 150 200 250 300 ? 50 ? 25 0 25 50 75 100 125 150 dropout voltage vs. t emperature 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0123456 dropout characteristic v in (v) (v) v out junction temperature ( c) 0 50 100 150 200 250 300 350 400 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 dropout voltage vs. v out dropout voltage (mv) v out r load = 16.5 (mv) v drop i out = 0 ma i out = 500 ma i out = 10 ma i out = 200 ma v out = 3.0 v v out = 3.0 v i out = 10 ma i out = 200 ma i out = 500 ma ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 ? 0.0 0.2 ? 40 ? 20 0 20 40 60 80 100 120 140 normalized v out vs. t emperature junction temperature ( c) (%) v out i out = 1 ma i out = 500 ma ? 0.75 ? 0.60 ? 0.45 ? 0.30 ? 0.15 0.00 0.15 0.30 0 50 100 150 200 250 300 350 400 450 500 normalized output voltage vs. load current output voltage (%) load current (ma) i out = 200 ma
si9185 vishay siliconix document number: 71765 s-50955?rev. e, 16-may-05 www.vishay.com 7 typical characteristics (internally regulated, 25 c unless noted) 0 50 100 150 200 250 300 01234567 no load gnd pin current vs. input voltage ( i gnd a) input voltage (v) ? 40 c 85 c ? 2.5 ? 2.0 ? 1.5 ? 1.0 ? 0.5 0.0 0 50 100 150 200 250 300 350 400 450 500 gnd current vs. load current load current (ma) 0 500 1000 1500 2000 2500 ? 40 ? 20 0 20 40 60 80 100 120 140 gnd pin current vs. temperature and load 25 c ( i gnd a) i out = 0 ma i out = 200 ma i out = 500 ma junctiontemperature ( c) 25 c ? 80 ? 60 ? 40 ? 20 0 10 100 1000 10000 100000 1000000 power supply rejection frequency (hz) gain (db) c in = 10 f c out = 2.2 f i load = 150 ma v out = 5 v v out = 5 v i gnd (ma)
si9185 vishay siliconix www.vishay.com 8 document number: 71765 s-50955?rev. e, 16-may-05 typical waveforms load t ransient response-1 i load 100 ma/div v out 10 mv/div v in = 4.3 v, c in = 2.2 f v out = 3.3 v, c out = 2.2 f i load = 1 to 150 ma t rise = 2 sec load t ransient response-2 5.00 s/div i load 100 ma/div v out 10 mv/div load transient response-3 i load 100 ma/div v out 10 mv/div load transient response-4 5.00 s/div i load 100 ma/div v out 10 mv/div load transient response-5 v in = 4.3 v, c in = 10 f v out = 3.3 v, c out = 10 f i load = 1 to 500 ma t rise = 2 sec 10 s/div load t ransient respons-6 5.00 s/div 5.00 s/div 10 s/div v out 20 mv/div i load 200 ma/div i load 200 ma/div v out 20 mv/div v in = 4.3 v, c in = 2.2 f v out = 3.3 v, c out = 2.2 f i load = 1 to 150 ma t rise = 2 sec v in = 4.3 v, c in = 2.2 f v out = 3.3 v, c out = 1.0 f i load = 1 to 150 ma t rise = 2 sec v in = 4.3 v, c in = 2.2 f v out = 3.3 v, c out = 1.0 f i load = 1 to 150 ma t rise = 2 sec v in = 4.3 v, c in = 10 f v out = 3.3 v, c out = 10 f i load = 1 to 500 ma t rise = 2 sec
si9185 vishay siliconix document number: 71765 s-50955?rev. e, 16-may-05 www.vishay.com 9 typical waveforms v in = 4.2 v v out = 3.3 v c delay = 0.1 f c noise = 0.1 f i load = 350 ma turn-on sequence 10.00 ms/div 5.00 s/div output noise v in = 4.2 v v out = 3.3 v i out = 150 ma c noise = 0.1 f bw = 10 hz to 1 mhz noise spectrum v in = 4.1 v v out = 3.3 v/10 ma c noise = 0.1 f 100 hz v in 2 v/div v out 2 v/div c delay 2 v/div error 2 v/div v in = 4.2 v v out = 3.3 v c delay = 0.1 f c noise = 0.1 f i load = 350 ma turn-off sequence v in ch-3 2 v/div v out ch-1 2 v/div c delay ch-4 2 v/div error ch-2 2 v/div 500 v/div 1 ms/div v hz 1 mhz 10.0 0.01 line transient response-1 v in 2 v/div v instep = 4.3 to 5.3 v v out = 3.3 v c out = 2.2 f c in = 10 f i load = 500 ma t rise = 5 sec 5.00 s/div v out 1 v/div line t ransient respons-2 v instep = 5.3 to 4.3 v v out = 3.3 v c out = 2.2 f c in = 10 f i load = 500 ma t fall = 5 sec v out 10 mv/div 5.00 s/div
si9185 vishay siliconix www.vishay.com 10 document number: 71765 s-50955?rev. e, 16-may-05 block diagram ? + v in 4 6 sd 8 3 gnd rfb2 rfb1 sense ? + + 1.215 v v ref ? 1 c noise ? + + 2 a to v in 5 2 7 v out error figure 5. 6 m 60 mv delay detailed description the si9185 is a low drop out, low quiescent current, and very linear regulator family with very fast transient response. it is primarily designed for battery powered applications where battery run time is at a premium. the low quiescent current allows extended standby time while low drop out voltage enables the system to fully utilize battery power before recharge. the si9185 is a very fast regulator with bandwidth exceeding 50 khz while maintaining low quiescent current at light load conditions. with this bandwidth, the si9185 is the fastest ldo available today. the si9185 is stable with any output capacitor type from 1 f to 10.0 f. however, x5r or x7r ceramic capacitors are recommended for best output noise and transient performance. v in v in is the input supply pin. the bypass capacitor for this pin is not critical as long as the input supply has low enough source impedance. for practical circuits, a 1.0- f or larger ceramic capacitor is recommended. when the source impedance is not low enough and/or the source is several inches from the si9185, then a larger input bypass capacitor is needed. it is required that the equivalent impedance (source impedance, wire, and trace impedance in parallel with input bypass capacitor impedance) must be smaller than the input impedance of the si9185 for stable operation. when the source impedance, wire, and trace impedance are unknown, it is recommended that an input bypass capacitor be used of a value that is equal to or greater than the output capacitor. v out v out is the output voltage of the regulator. connect a bypass capacitor from v out to ground. the output capacitor can be any value from 1.0 f to 10.0 f. a ceramic capacitor with x5r or x7r dielectric type is recommended for best output noise, line transient, and load transient performance. gnd ground is the common ground connection for v in and v out . it is also the local ground connection for c noise , delay, sense or adj, and sd .
si9185 vishay siliconix document number: 71765 s-50955?rev. e, 16-may-05 www.vishay.com 11 sense or adj sense is used to sense the output voltage. connect sense to v out for the fixed voltage version. for the adjustable output version, use a resistor divider r1 and r2, connect r1 from v out to adj and r2 from adj to ground. r2 should be in the 25-k to 150-k range for low power consumption, while maintaining adequate noise immunity. the formula below calculates the value of r1, given the desired output voltage and the r2 value, (1) r1 v out
v adj r2 v adj v adj is nominally 1.215 v. shutdown (sd ) sd controls the turning on and off of the si9185. v out is guaranteed to be on when the sd pin voltage equals or is greater than 1.5 v. v out is guaranteed to be off when thesd pin voltage equals or is less than 0.4 v. during shutdown mode, the si9185 will draw less than 2- a current from the source. to automatically turn on v out whenever the input is applied, tie the sd pin to v in . error error is an open drain output that goes low when v out is less than 5% of its normal value. as with any open drain output, an external pull up resistor is needed. when a capacitor is connected from delay to ground, the error signal transition from low to high is delayed (see delay section). this delayed error signal can be used as the power-on reset signal for the application system. (refer to figure 4.) the error pin is disconnected if not used. delay a capacitor from delay to ground sets the time delay for error going from low to high state. the time delay can be calculated using the following formula: (2) t delay v adj c delay i delay the delay pin should be an open circuit if not used. c noise for low noise application, connect a high frequency ceramic capacitor from c noise to ground. a 0.01- f or a 0.1- f x5r or x7r is recommended. safe operating area the ability of the si9185 to supply current is ultimately dependent on the junction temperature of the pass device. junction temperature is in turn dependent on power dissipation in the pass device, the thermal resistance of the package and the circuit board, and the ambient temperature. the power dissipation is defined as p d = (v in ? v out ) * i out . junction temperature is defined as t j = t a + ((p d * (r jc + r ca )). to calculate the limits of performance, these equations must be rewritten. allowable power dissipation is calculated using the equation p d = (t j ? t a )/ (r jc + r ca ) while allowable output current is calculated using the equation i out = (t j ? t a )/ (r jc + r ca ) * (v in ? v out ). ratings of the si9185 that must be observed are t jmax = 125 c, t amax = 85 c, (v in ? v out ) max = 5.3 v, r jc = 4 c/w. the value of r ca is dependent on the pc board used. the value of r ca for the board used in device characterization is approximately 46 c/w. figure 6 shows the performance limits graphically for the si9185 mounted on the circuit board used for thermal characterization. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 figure 6. (a) i out t a = 0 c v in ? v out (v) (v in ? v out ) max = 5.3 v t a = 25 c t a = 50 c t a = 85 c t a = 70 c
si9185 vishay siliconix www.vishay.com 12 document number: 71765 s-50955?rev. e, 16-may-05 pcb footprint and layout considerations the si9185 comes in the mlp33 powerpak package with an exposed pad on the bottom to provide a low thermal impedance path into the pc board. when the pc board layout is designed, a copper plane, referred to as spreading copper, is recommended to be placed under the package to which the exposed pad is soldered. this spreading copper is the path for the heat to move away from the package into the pc board. with the si9185 mounted on a four layer board measuring 2? 2?, a spreading copper area of 0.25 square inches will yield an r ja of 50 c/w. this allows for power dissipation in excess of 1 watt in an 80 c ambient environment. figure 7. mlp33 powerpak pad pattern 0.325 0.013 2.245 0.088 1.426 0.056 2.852 0.112 0.396 0.016 0.650 0.026 0.906 0.026 1.425 0.056 mm inches vishay siliconix maintains worldwide manufacturing c apability. pr oducts may be manufactured at on e of several qualified locati ons. reliability data for silicon technology and package reliability repr esent a composite of all qualified locations. for re lated documents such as package/tape drawings, par t marking, and reliability data, see http://www.vishay.com/ppg?71765 .

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