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| general features ? single-package fully-integrated avr 8-bit microcontroller with lin transceiver and 5v regulator ? very low current consumption in sleep mode ? 32kbytes flash memory for application program ? supply voltage up to 40v ? operating voltage: 5v to 27v ? temperature range: t case ?40c to +125c ? qfn48, 7 mm 7 mm package 1. description atmel ? ata6614 is a system-in-package (sip) product, which is particularly suited for complete lin-bus slave-node applications. it supports highly integrated solutions for in-vehicle lin networks. the first chip is the lin-system-basis-chip (lin-sbc) atmel ata6630, which has an integrated lin transceiver and a 5v regulator. the second chip is an automotive microc ontroller from atmel?s series of avr 8-bit microcontroller with advanced risc architecture. the atmel ata6614 consists of the lin-sbc atmel ata6630 and the atmel atmega328p with 32kbytes flash. all pins of the lin system basis chip as well as all pins of the avr microcontroller are bonded out to provide customers the same flexibil- ity for their applications as they have when using discrete parts. in section 2 you will find the pin configuration for the complete sip. in sections 3 to 5 the lin sbc is described, and in sect ion 7 the avr is described in detail. figure 1-1. application diagram mcu atmel atmeg a3 2 8 p lin- s bc atmel ata66 3 0 lin b us atmel ata6614 microcontroller with lin transceiver and 5v regulator atmel ata6614 preliminary 9159a?auto?09/10
2 9159a?auto?09/10 atmel ata6614 [preliminary] 2. pin configuration figure 2-1. pinning qfn48, 7 mm 7 mm pb5 mcuavdd adc6 aref gnd adc7 pc0 pc1 pc2 pc 3 pc4 pc5 mcuvdd1 pd4 pd 3 lin agnd wake en vbat v s vcc pvcc kl15 pb4 pb 3 pb2 pb1 pb0 pd7 pd6 pd5 pb7 pb6 mcuvdd2 gnd2 pc6 pd0 pd1 pd2 rxd div_on pv s p_mode inh txd pvcc_uv mode 4 8 47 46 45 44 4 3 42 41 40 3 9 38 3 7 1 3 14 15 16 17 1 8 19 20 21 22 2 3 24 1 2 3 4 5 6 7 8 9 10 11 12 3 6 3 5 3 4 33 3 2 3 1 3 0 29 2 8 27 26 25 table 2-1. pin description pin symbol function 1 pb5 port b 5 i/o line (sck / pcint5) 2 mcuavdd microcontroller adc-unit supply voltage 3 adc6 adc input channel 6 4 aref analog reference voltage input 5 gnd ground 6 adc7 adc input channel 7 7 pc0 port c 0 i/o line (adc0/pcint8) 8 pc1 port c 1 i/o line (adc1/pcint9) 9 pc2 port c 2 i/o line (adc2/pcint10) 10 pc3 port c 3 i/o line (adc3/pcint11) 11 pc4 port c 4 i/o line (adc4/sda/pcint12) 12 pc5 port c 5 i/o line (adc5/scl/pcint13) 13 pc6 port c 6 i/o line (reset/pcint14) 14 pd0 port d 0 i/o line (rxd/pcint16) 15 pd1 port d 1 i/o line (txd/pcint17) 16 pd2 port d 2 i/o line (int0/pcint18) 17 (1) rxd receive data output 18 (1) div_on input to switch internal vbat divider on, active high 19 (1) pv voltage divider output note: 1. this identifies the pi ns of the lin sbc ata6630 3 9159a?auto?09/10 atmel ata6614 [preliminary] 20 (1) sp_mode input to switch the transceiver in high-speed mode, active high 21 (1) inh battery related high-side switch 22 (1) txd transmit data input, active low output (strong pull down) 23 (1) pvcc_uv pvcc undervoltage 24 (1) mode connect to vcc 25 (1) kl15 ignition detection (edge sensitive) 26 (1) pvcc voltage regulator sense input 27 (1) vcc voltage regulator output 28 (1) vs battery supply voltage 29 (1) vbat battery connection for voltage divider 30 (1) en enables the device into normal mode 31 (1) wake high voltage input for local wake-up request 32 (1) agnd analog system ground (lin ground) 33 lin lin bus input/output 34 pd3 port d 3 i/o line (int1 oc2b/pcint19) 35 pd4 port d 4 i/o line (t0/xck/pcint20) 36 mcuvdd1 microcontroller supply voltage 37 gnd2 ground 38 mcuvdd2 microcontroller supply voltage 39 pb6 port b 6 i/o line (tosc1/xtal1/pcint6) 40 pb7 port b 7 i/o line (tosc2/xtal2/pcint7) 41 pd5 port d 5 i/o line (t1/oc0b/pcint21) 42 pd6 port d 6 i/o line (ain0/oc0a pcint22) 43 pd7 port d 7 i/o line (ain1/pcint23) 44 pb0 port b 0 i/o line (icp1/clko/pcint0) 45 pb1 port b 1 i/o line (oc1a/pcint1) 46 pb2 port b 2 i/o li ne (oc1b/ss/pcint2) 47 pb3 port b 3 i/o line (mosi/oc2a/pcint3) 48 pb4 port b 4 i/o line (miso/pcint4) backside heat slug is connected to gnd table 2-1. pin description (continued) pin symbol function note: 1. this identifies the pi ns of the lin sbc ata6630 4 9159a?auto?09/10 atmel ata6614 [preliminary] table 2-2. maximum ratings of the sip parameters symbol min. typ. max. unit hbm esd ansi/esd-stm5.1 jesd22-a114 aec-q100 (002) 2 kv cdm esd stm 5.3.1 750 v storage temperature t s ?55 +150 c operating temperature (1) t case ?40 +125 c thermal resistance junc tion to heat slug r thjc 5k/w thermal resistance junctiion to ambient, according to jedec r thja 25 k/w thermal shutdown of vcc regulator 150 165 170 c thermal shutdown of lin output 150 165 170 c thermal shutdown hysteresis 10 c note: 1. t case means the temperature of the heat slug (backside). it is mandatory that this backside temperature is 125c in the application. 5 9159a?auto?09/10 atmel ata6614 [preliminary] 3. lin system-basis-chip block 3.1 features ? master and slave operation possible ? supply voltage up to 40v ? operating voltage v s = 5v to 27v ? typically 10a supply cu rrent during sleep mode ? typically 40a supply cu rrent in silent mode ? linear low-drop voltage regulator: ? normal, fail-safe, and silent mode ?v cc = 5.0v 2% ? in sleep mode v cc is switched off ? vcc- undervoltage detection at open drain output pvcc_uv ? high-speed mode up to 115kbaud ? internal 1:6 voltage divider for v battery sensing ? boosting the voltage regulator possib le with an external npn transistor ? lin physical layer according to lin 2.0, 2.1 and saej2602-2 ? wake-up capability via lin-bu s, wake pin, or kl_15 pin ? inh output to control an external voltage regulator or to switch off the master pull up resistor ? bus pin is overtemperature and short-cir cuit protected versus gnd and battery ? advanced emc and esd performance ? fulfills the oem ?hardware requirements fo r lin in automotive applications rev.1.1? ? interference and damage protection according iso7637 ? package: qfn 5mm 5mm with 20 pins 3.2 description the atmel ? ata6630 is a fully integrated lin transceiver, which complies with the lin 2.0, 2.1 and saej2602-2 specifications. it has a low-drop voltage regulator for 5v/50ma output. the voltage regulator is able to source 50ma, but the output current can be boosted by using an external npn transistor. the ata6630 is designed to handle the low-speed data communica- tion in vehicles, e.g., in convenience electroni cs. improved slope control at the lin-driver ensures secure data communication up to 20kbaud. sleep mode and silent mode guarantee very low current consumption. 6 9159a?auto?09/10 atmel ata6614 [preliminary] figure 3-1. block diagram ata6630 high s peed mode s hort circ u it a nd overtemper a t u re protection txd time-o u t timer edge detection de b o u nce time intern a l te s ting unit control unit s lew r a te control w a ke- u p b us timer mode s elect norm a l/ s ilent/ f a il- sa fe mode 5v/50 ma/ 2 % rf filter rxd gnd pv pvcc pvcc mode en txd s p_mode kl15 wake receiver norm a l a nd f a il- sa fe mode lin pvcc vcc v s div_on vbatt 5k norm a l a nd f a il- sa fe mode inh undervolt a ge detection pvcc_uv 7 9159a?auto?09/10 atmel ata6614 [preliminary] 3.3 functional description 3.3.1 physical layer compatibility since the lin physical layer is independent from higher lin layers (e.g., the lin protocol layer), all nodes with a lin physical layer acco rding to revision 2.x can be mixed with lin physical layer nodes, which, according to older versions (i.e., lin 1.0, lin 1.1, lin 1.2, lin 1.3), are without any restrictions. 3.3.2 supply pin (vs) the lin operating voltage is v s = 5v to 27v. an undervoltage detection is implemented to dis- able data transmission if v s falls below vs th in order to avoid false bus messages. after switching on vs, the ic starts in fail-safe mode, and the voltage regulator is switched on (i.e., 3.3v/5v/50ma out put capability). the supply current is typically 10a in sleep mode and 40a in silent mode. 3.3.3 ground pin (gnd) the ic does not affect the lin bus in the event of gnd disconnection. it is able to handle a ground shift up to 11.5% of vs. the mandatory system ground is pin 5. 3.3.4 voltage regulator output pin (vcc) the internal 3.3v/5v voltage regulator is capable of driving loads up to 50ma. it is able to sup- ply the microcontroller and other ics on the pcb and is protected against overloads by means of current limitation and overtemperature shut-down. furthermore, the output voltage is moni- tored and will cause a reset signal at the pv cc_uv output pin if it drops below a defined threshold v thun . to boost up the maximum load current, an external npn transistor may be used, with its base connected to the vcc pin and its emitter connected to pvcc. 3.3.5 voltage regulator sense pin (pvcc) the pvcc is the sense input pin of the 3. 3v/5v voltage regulator. for normal applications (i.e., when only using the internal output transistor), this pin must be connected to the vcc pin. if an external boosting transistor is used, the pvcc pin must be connected to the output of this transistor, i.e., its emitter terminal. 3.3.6 bus pin (lin) a low-side driver with internal current limita tion and thermal shutdown and an internal pull-up resistor compliant with the lin 2.x specification are implemented. the allowed voltage range is between ?27v and +40v. reverse currents fr om the lin bus to vs are suppressed, even in the event of gnd shifts or battery disconnection. lin receiver thresholds are compatible with the lin protocol specification. the fall time from recessive to dominant bus state and the rise time from dominant to recessive bus state are slope controlled. 3.3.7 input/output pin (txd) in normal mode the txd pin is the microcontroller interface used to control the state of the lin output. txd must be pulled to ground in order to have a low lin-bus. if txd is high or not con- nected (internal pull-up resistor), the lin outpu t transistor is turned off, and the bus is in recessive state. during fail-safe mode, this pin is used as outp ut and is signalling the fail-safe source. it is current-limited to < 8ma. 8 9159a?auto?09/10 atmel ata6614 [preliminary] 3.3.8 txd dominant time-out function the txd input has an internal pull-up resistor . an internal timer prevents the bus line from being driven permanently in dominant state. if txd is forced to low for longer than t dom > 27ms, the lin-bus driver is switched to recessive state. nevertheless, when switching to sleep mode, the actual level at the txd pin is relevant. to reactivate the lin bus driver, switch txd to high (> 10s). 3.3.9 output pin (rxd) this output pin reports the state of the lin- bus to the microcontroller. lin high (recessive state) is reported by a high level at rxd; lin low (dominant state) is reported by a low level at rxd. the output has an internal pull-up resistor with typically 5 k to pvcc. the ac charac- teristics can be defined with an external load capacitor of 20pf. the output is short-circuit protected. rxd is switched off in unpowered mode (i.e., v s = 0v). during fail-safe mode it is si gnalling the fail- safe source. 3.3.10 enable input pin (en) the enable input pin controls the operation mode of the device. if en is high, the circuit is in normal mode, with transmission paths from txd to lin and from lin to rxd both active. the vcc voltage regulator operates with 3.3v/5v/50ma output capability. if en is switched to low while txd is still high , the device is forced to silent mode. no data transmission is then possible, and the current consumption is reduced to i vs typ. 40a. the vcc regulator has its full functionality. if en is switched to low while txd is low, the device is forced to sleep mode. no data trans- mission is possible, and the voltage regulator is switched off. 3.3.11 wake input pin (wake) the wake input pin is a high-voltage input used to wake up the devi ce from sleep mode or silent mode. it is usually connected to an external switch in the application to generate a local wake-up. a pull-up current source, typically 10a, is implemented. if a local wake-up is not needed in the applicati on, connect the wake pin directly to the vs pin. 3.3.12 mode input pin (mode) connect the mode pin directly to pvcc. 3.3.13 kl_15 pin the kl_15 pin is a high-voltage input used to wake up the device from sleep or silent mode. it is an edge-sensitive pin (low-to-high transitio n). it is usually connected to ignition to generate a local wake-up in the application when the ignition is switched on. although kl_15 pin is at high voltage (v batt ), it is possible to switch the ic into sleep or silent mode. connect the kl_15 pin directly to gnd if you do not need it. a debounce timer with a typical tdb kl_15 of 160 s is implemented. the input voltage threshold can be adjusted by varying the external resistor due to the input current i kl_15 . to protect this pin against voltage transients, a serial resistor of 47k and a ceramic capacitor of 100nf are recommended. with this rc combination you can increase the wake-up time tw kl_15 and, therefore, the sensitivity against transients on the ignition kl_15. 9 9159a?auto?09/10 atmel ata6614 [preliminary] you can also increase the wake-up time using external capacitors with higher values. 3.3.14 inh output pin the inh output pin is used to switch an external voltage regulator on during normal and fail-safe mode. the inh output is a high-side s witch, which is switched-o ff in sleep and silent mode. it is possible to switch off the external 1k master resistor via the inh pin for master node applications. 3.3.15 pvcc_uv output pin the pvcc_uv output pin, an open drain output, switches to low during pvcc undervoltage. 3.3.16 wake-up events from sleep or silent mode ?lin-bus ? wake pin ?en pin ? kl_15 3.3.17 div_on input pin the div_on pin is a low voltage input. it is used to switch on or off the internal voltage divider pv output directly with no time limitation (see table 3-1 on page 9 ). it is switched on if div_on is high or it is switched off if div_on is low. in sleep mode the div_on functionality is dis- abled and pv is off. an internal pull-down resistor is implemented. 3.3.18 vbatt input pin the vbatt is a high voltage input pin to supply the internal voltage divider. in an application with battery voltage monitoring, this pin is connected to v battery via a 47 resistor in series and a 10nf capacitor to gnd. the the divider ratio is 1:6. 3.3.19 pv output pin for applications with battery monitoring, this pi n is directly connected to the adc of a micro- controller. for buffering the adc input an external capacitor might be needed. this pin guarantees a voltage and temperature stable output of a v battery ratio. the pv output pin is controlled by the div_on input pin. 3.3.20 sp_mode input pin the sp_mode pin is a low-voltage input. high -speed mode of the transceiver can be acti- vated via a high level during normal mode. return to lin 2.x transceiver mode with slope control is possible if you s witch the sp_mode pin to low. table 3-1. table of voltage divider mode of operation input div_on voltage divider output pv fail-safe/normal/ high-speed/silent 0off 1on sleep 0off 1off 10 9159a?auto?09/10 atmel ata6614 [preliminary] 3.4 modes of operation figure 3-2. modes of operation unpowered mode a : v s > v s thf b : v s < v s thu c: b us w a ke- u p event d: w a ke u p from wake or kl_15 pin fail- s afe mode vcc : 5v/50ma with u ndervolt a ge monitoring communication : off s ilent mode vcc: 5v/50ma with u ndervolt a ge monitoring communication: off s leep mode vcc: s witched off communication: off go to s ilent comm a nd a txd = 0 en = 0 txd = 1 en = 0 en = 1 en = 1 en = 1 b b b c + d + e e c + d b normal mode vcc: 5v/50ma with u ndervolt a ge detection high level a t pin s p_mode: hi g h- s peed mode tr a n s ceiver 115 kb au d lin 2.1 tran s ceiver 20kb au d txd time-o u t timer on go to s leep comm a nd e: nre s s witche s to low go to norm a l comm a nd table 3-2. table of modes mode of operation transceiver pin lin v cc pin mode pin inh unpowered off recessive on gnd off fail-safe off recessive 3.3v/5v gnd on normal/ high-speed on txd depending 3.3v/5v gnd on silent off recessive 3.3v/5v gnd off sleep off recessive 0v gnd off 11 9159a?auto?09/10 atmel ata6614 [preliminary] 3.4.1 normal mode this is the normal transmitting and receiving mode. the voltage regulator is active and can source up to 50 ma. the undervoltage detection is activated. 3.4.2 silent mode a falling edge at en when txd is high switches the ic into silent mode. the txd signal has to be logic high during the mode select window (see figure 3-3 on page 11 ). the transmission path is disabled in silent mode. the inh ou tput is switched off and the voltage divider is enabled. the overall supply current from v batt is a combination of the i vssi = 40a plus the vcc regulator output current i vcc . the 3.3v/5v regulator with 2% tolerance can source up to 50ma. the internal slave termina- tion between the lin pin and the vs pin is dis abled in silent mode to minimize the current consumption in the event that the lin pin is short-circuited to gnd. only a weak pull-up cur- rent (typically 10a) between the lin pin and the vs pin is present. silent mode can be activated independen tly from the actual level on the lin, wake, or kl_15 pins. if a undervolt- age condition occurs, pvcc_uv is switched to low and the ic changes its state to fail-safe mode. a voltage less than the lin pre_wake detection vlinl at the lin pin activates the internal lin receiver and starts the wake-up detection timer. figure 3-3. switch to silent mode del a y time s ilent mode t d _ s ilent = m a xim u m 20 s mode s elect window lin s witche s directly to rece ss ive mode t d = 3 .2 s lin vcc txd en normal mode s ilent mode 12 9159a?auto?09/10 atmel ata6614 [preliminary] a falling edge at the lin pin followed by a dominant bus level maintained for a certain time period (t bus ) and the following rising edge at the lin pin (see figure 3-4 on page 12 ) result in a remote wake-up request which is only possible if txd is high. the device switches from silent mode to fail-safe mode. the internal lin slave termination resistor is switched on. the remote wake-up request is indicated by a low level at the rxd pin to interrupt the microcontroller (see figure 3-4 on page 12 ). en high can be used to switch directly to normal mode. figure 3-4. lin wake up from silent mode undervolt a ge detection a ctive s ilent mode 3 . 3 v/5v/50 ma f a il sa fe mode 3 . 3 v/5v/50 ma norm a l mode low fail- s afe mode normal mode en high node in s ilent mode high high pvcc_uv en vcc volt a ge reg u l a tor rxd lin bus b us w a ke- u p filtering time t bus txd don't c a re 13 9159a?auto?09/10 atmel ata6614 [preliminary] 3.4.3 sleep mode a falling edge at en when txd is low switches the ic into sleep mode. the txd signal has to be logic low during the mode select window ( figure 3-5 on page 13 ). in order to avoid any influence to the lin-pin during switching into slee p mode it is possible to switch the en up to 3.2 s earlier to low t han the txd. ther efore, the best an easiest way are two falling edges at txd and en at the same time. the transmissi on path is disabled in sleep mode. the supply current i vssleep from v batt is typically 10a. the inh output, the pv output and the vcc regulator are switched off. pvcc_uv is low. the internal slave termination between the lin pin and vs pin is disabled to minimize the current consumption in the event that the lin pin is short-circuited to gnd. only a weak pull-up cur- rent (typically 10a) between the lin pin and the vs pin is present. sleep mode can be activated independently from the current level on the lin, wake, or kl_15 pin. a voltage less than the lin pre_wake detection vlinl at the lin pin activates the internal lin receiver and starts the wake-up detection timer. figure 3-5. switch to sleep mode del a y time s leep mode t d_ s leep = m a xim u m 20 s lin s witche s directly to rece ss ive mode t d = 3 .2 s lin vcc pvcc_uv txd en s leep mode normal mode mode s elect window 14 9159a?auto?09/10 atmel ata6614 [preliminary] a falling edge at the lin pin followed by a dominant bus level maintained for a certain time period (t bus ) and a rising edge at pin lin result in a remote wake-up request. the device switches from sleep mode to fail-safe mode. the vcc regulator is activated, and the internal lin slave termination resistor is switched on. the remote wake-up request is indicated by a low level at the rxd pin to interrupt the micro- controller (see figure 3-6 on page 14 ). en high can be used to switch directly from sl eep/silent to fail-safe mode. if en is still high after vcc ramp up and undervoltage reset time, the ic switches to the normal mode. figure 3-6. lin wake up from sleep mode reg u l a tor w a ke- u p time off s t a te on s t a te low fail- s afe mode normal mode en high low or flo a ting en vcc volt a ge reg u l a tor rxd lin bus b us w a ke- u p filtering time t bus txd 15 9159a?auto?09/10 atmel ata6614 [preliminary] 3.4.4 sleep or silent mode: behavior at a fl oating lin-bus or a short circuited lin to gnd in sleep or in silent mode the device has a very low current consumption even during short-circuits or floating conditions on the bus. a floating bus can arise if the master pull-up resistor is missing, e.g., if it is switched off when the lin- master is in sleep mode or even if the power supply of the master node is switched off. in order to minimize the current consumption i vs in sleep or silent mode during voltage levels at the lin-pin below the lin pre-wake threshold, the receiver is activated only for a specific time tmon. if t mon elapses while the voltage at the bus is lower than pre-wake detection low (v linl ) and higher than the lin dominant level, the receiver is switched off again and the circuit changes back to sleep respective ly silent mode. the current consumption is then the result of i vssleep or i vssilent plus i linwake . if a dominant state is reached on the bus no wake-up will occur. even if the voltage rises above the pre-wake detection high (v linh ), the ic will stay in sleep respectively silent mode (see figure 3-7 ). this means the lin-bus must be above the pre-wake detection threshold v linh for a few microseconds before a new lin wake-up is possible. figure 3-7. floating lin-bus during sleep or silent mode if the atmel ? ata6630 is in sleep or silent mode and the voltage level at the lin-bus is in dominant state (v lin < v busdom ) for a time period exceeding t mon (during a short circuit at lin, for example), the ic switches back to sl eep mode respectively silent mode. the v s current consumption then consists of i vssleep or i vssilent plus i linwake . after a positive edge at pin lin the ic switches directly to fail-safe mode (see figure 3-8 on page 16 ). i v ss leep/ s ilent i v ss leep i v s f a il + i linw a ke i v ss leep v bu s dom v linl i v s t mon lin pre-w a ke lin domin a nt s t a te lin bu s mode of oper a tion int. p u ll- u p re s i s tor rlin w a ke- u p detection ph as e off (di sab led) s leep/ s ilent mode s leep/ s ilent mode 16 9159a?auto?09/10 atmel ata6614 [preliminary] figure 3-8. short circuit to gnd on the lin bus during sleep- or silent mode s leep/ s ilent mode i v ss leep/ s ilent i v s f a il + i linw a ke i v ss leep/ s ilent v bu s dom v linl lin pre-w a ke lin domin a nt s t a te lin bu s i v s mode of oper a tion int. p u ll- u p re s i s tor rlin off (di sab led) on (en ab led) w a ke- u p detection ph as e s leep/ s ilent mode f a il- sa fe mode t mon t mon 17 9159a?auto?09/10 atmel ata6614 [preliminary] 3.4.5 fail-safe mode the device automatically switches to fail-safe mode at system power-up. the voltage regula- tor is switched on (v cc = 3.3v/5v/2%/50ma) (see figure 3-9 on page 20 ). the nres output switches to low for t res = 4ms and gives a reset to the microcontroller. lin communication is switched off. the ic stays in this mode until en is switched to high. the ic then changes to normal mode. a power down of v batt (v s 19 9159a?auto?09/10 atmel ata6614 [preliminary] 3.5.5 fail-safe features ? during a short-circuit at lin to v battery , the output limits the output current to i bus_lim . due to the power dissipation, the chip temperature exceeds t linoff , and the lin output is switched off. the chip cools down and after a hysteresis of t hys , switches the output on again. rxd stays on high because lin is high. during lin overtemperature switch-off, the vcc regulator works independently. ? during a short-circuit from lin to gnd the ic can be switched into sleep or silent mode and even in this case the current consumption is lower than 45a in sleep mode and lower than 80a in silent mode. if the short-circuit disappears, the ic starts with a remote wake-up. ? sleep or silent mode: during a floating condition on the bus the ic switches back to sleep mode/silent mode automatically and thereby the current consumption is lower than 45a/80a. ? the reverse current is < 2a at the lin pin during loss of v batt . this is optimal behavior for bus systems where some slave nodes ar e supplied from battery or ignition. ? during a short circuit at vcc, the output limits the output current to i vcclim . because of undervoltage, pvcc_uv switches to low and the ic switches into fail-safe mode. if the chip temperature exceeds the value t vccoff , the vcc output switches off. the chip cools down and after a hysteresis of t hys , switches the output on again. because of the fail-safe mode, the vcc voltage will switch on again although en is switched off from the microcontroller. the microcontroller can start with its normal operation. ? en pin provides a pull-down resistor to force the transceiver into recessive mode if en is disconnected. ? rxd pin is set floating if v batt is disconnected. ? txd pin provides a pull-up resistor to force the transceiver into recessive mode if txd is disconnected. ? if txd is short-circuited to gnd, it is possible to switch to sleep mode via enable. 3.5.6 voltage regulator the voltage regulator needs an external capacitor for compensation and for smoothing the disturbances from the microcontroller. it is reco mmended to use an electrolythic capacitor with c > 1.8f and a ceramic capacitor with c = 100nf. the values of these capacitors can be var- ied by the customer, depending on the application. the main power dissipation of the ic is created from the vcc output current i vcc , which is needed for the application. in figure 3-10 on page 20 the safe operating area of the atmel ? ata6630 is shown. 20 9159a?auto?09/10 atmel ata6614 [preliminary] figure 3-9. vcc voltage regulator: ramp-up and undervoltage detection figure 3-10. power dissipation: safe operating area versus vcc output current and sup- ply voltage v s at different ambient temperatures due to r thja = 25k/w for programming purposes of the microcontroller it is potentially necessary to supply the v cc output via an external power supply while the v s pin of the system basis chip is disconnected. this behavior is no problem for the system basis chip. pvcc_uv 5v t t t v s 5v v th u n t re s _f t re s et t vcc 5.5v 12v vcc v s /v i vcc /ma 0 5 10 15 20 25 3 0 3 5 40 45 50 55 46 8 10 12 14 16 1 8 20 t a m b = 105c t a m b = 110c t a m b = 115c 21 9159a?auto?09/10 atmel ata6614 [preliminary] 4. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters symbol min. typ. max. unit supply voltage v s v s ?0.3 +40 v pulse time 500ms t a = 25c output current i vcc 50ma v s +40 v pulse time 2min t a = 25c output current i vcc 50ma v s 27 v wake (with 2.7k serial resistor) kl_15 (with 47k /100nf) vbatt (with 47 /10nf) dc voltage transient voltage due to iso7637 (coupling 1nf) ?1 ?150 +40 +100 v v inh - dc voltage ?0.3 v s + 0.3 v lin, vbatt - dc voltage ?27 +40 v logic pins (rxd, txd, en, pvcc_uv, mode, div_on, sp_mode, pv) ?0.3 vcc + 0.5v v output current pvcc_uv i pvcc_uv +2 ma pvcc dc voltage vcc dc voltage ?0.3 ?0.3 +5.5 +6.5 v v esd according to ibee lin emc test spec. 1.0 following iec 61000-4-2 - pin vs, lin to gnd - pin wake (2.7k , serial resistor) to gnd - pin vbatt (10nf) to gnd 6 kv hbm esd ansi/esd-stm5.1 jesd22-a114 aec-q100 (002) mil-std-883 (m3015.7) 3 kv cdm esd stm 5.3.1 750 v mm esd eia/jesd22-a115 esd stm5.2 aec-q100 (002) 200 v esd hbm following stm5.1 with 1.5k 100pf - pin vs, lin, wake to gnd 6 kv junction temperature t j ?40 +150 c storage temperature t s ?55 +150 c 22 9159a?auto?09/10 atmel ata6614 [preliminary] 5. electrical characteristics 5v < v s < 27v, ?40c < t j < 150c, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* 1 vs pin 1.1 nominal dc voltage range vs v s 527va 1.2 supply current in sleep mode sleep mode v lin > v s ? 0.5v v s < 14v vs i vssleep 31014aa sleep mode, v lin = 0v bus shorted to gnd v s < 14v vs i vssleep_short 61730aa 1.3 supply current in silent mode bus recessive v s < 14v (t j = 25c) without load at vcc vs i vssi 20 35 45 a a bus recessive v s < 14v (t j = 125c) without load at vcc vs i vssi 25 40 50 a a silent mode v s < 14v bus shorted to gnd without load at vcc vs i vssi_short 25 50 80 a a 1.4 supply current in normal mode bus recessive v s < 14v without load at vcc vs i vsrec 0.3 0.8 ma a 1.5 supply current in normal mode bus recessive v s < 14v v cc load current 50ma vs i vsdom 50 53 ma a 1.6 supply current in fail-safe mode bus recessive, rxd is low v s < 14v without load at vcc vs i vsfail 1.5 2.0 ma a 1.7 vs undervoltage threshold switch to unpowered mode vs v sthu 44.24.4va switch to fail-safe mode vs v sthf 4.3 4.5 4.9 v a 1.8 vs undervoltage threshold hysteresis vs v sth_hys 0.3 v a 2 rxd output pin 2.1 low-level output sink current normal mode v lin =0v v rxd =0.4v rxd i rxd 1.3 2.5 8 ma a 2.2 low-level output voltage i rxd = 1ma rxd v rxdl 0.4 v a 2.3 internal resistor to pvcc rxd r rxd 357k a 3 txd input/output pin 3.1 low-level voltage input txd v txdl ?0.3 +0.8 v a 3.2 high-level voltage input txd v txdh 2 v cc + 0.3v va 3.3 pull-up resistor v txd =0v txd r txd 125 250 400 k a 3.4 high-level leakage current v txd =v cc txd i txd ?3 +3 a a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 23 9159a?auto?09/10 atmel ata6614 [preliminary] 3.5 low-level output sink current fail-safe mode, wake up v lin = v s v wake = 0v v txd = 0.4v txd i txdwake 22.58maa 4 en input pin 4.1 low-level voltage input en v enl ?0.3 +0.8 v a 4.2 high-level voltage input en v enh 2 v cc + 0.3v va 4.3 pull-down resistor v en = v cc en r en 50 125 200 k a 4.4 low-level input current v en = 0v en i en ?3 +3 a a 5mode input pin 5.1 low-level voltage input mode v model ?0.3 +0.8 v a 5.2 high-level voltage input mode v modeh 2 v cc + 0.3v va 5.3 high-level leakage current v mode = v cc or v mode = 0v mode i mode ?3 +3 a a 6 inh output pin 6.1 high-level voltage i inh = ?15ma inh v inhh v s ? 0.75 v s va 6.2 switch-on resistance between vs and inh inh r inh 30 50 a 6.3 leakage current sleep mode v inh = 0v/27v, vs = 27v inh i inhl ?3 +3 a a 7 lin bus driver 7.1 driver recessive output voltage load1/load2 lin v busrec 0.9 v s v s va 7.2 driver dominant voltage v vs = 7v r load = 500 lin v _losup 1.2 v a 7.3 driver dominant voltage v vs = 18v r load = 500 lin v _hisup 2va 7.4 driver dominant voltage v vs = 7.0v r load = 1000 lin v _losup_1k 0.6 v a 7.5 driver dominant voltage v vs = 18v r load = 1000 lin v _hisup_1k 0.8 v a 7.6 pull-up resistor to vs the serial diode is mandatory lin r lin 20 30 47 k a 7.7 voltage drop at the serial diodes in pull-up path with r slave i serdiode =10ma lin v serdiode 0.4 1.0 v d 7.8 lin current limitation v bus = v batt_max lin i bus_lim 70 120 200 ma a 7.9 input leakage current at the receiver including pull-up resistor as specified input leakage current driver off v bus = 0v v batt = 12v lin i bus_pas_dom ?1 ?0.35 ma a 5. electrical characteristics (continued) 5v < v s < 27v, ?40c < t j < 150c, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 24 9159a?auto?09/10 atmel ata6614 [preliminary] 7.10 leakage current lin recessive driver off 8v < v batt < 18v 8v < v bus < 18v v bus v batt lin i bus_pas_rec 10 20 a a 7.11 leakage current at gnd loss, control unit disconnected from ground. loss of local ground must not affect communication in the residual network. gnd device = v s v batt = 12v 0v < v bus < 18v lin i bus_no_gnd ?10 +0.5 +10 a a 7.12 leakage current at loss of battery. node has to sustain the current that can flow under this condition. bus must remain operational under this condition. v batt disconnected v sup_device = gnd 0v < v bus < 18v lin i bus_no_bat 0.1 2 a a 7.13 capacitance on pin lin to gnd lin c lin 20 pf d 8 lin bus receiver 8.1 center of receiver threshold v bus_cnt = (v th_dom + v th _ rec )/2 lin v bus_cnt 0.475 v s 0.5 v s 0.525 v s va 8.2 receiver dominant state v en = v cc lin v busdom 0.4 v s va 8.3 receiver recessive state v en = v cc lin v busrec 0.6 v s va 8.4 receiver input hysteresis v hys = v th_rec ? v th_dom lin v bushys 0.028 v s 0.1 v s 0.175 v s va 8.5 pre_wake detection lin high-level input voltage lin v linh v s ? 2v v s + 0.3v v a 8.6 pre_wake detection lin low-level input voltage activates the lin receiver lin v linl ?27 v s ? 3.3v v a 9 internal timers 9.1 dominant time for wake-up via lin bus v lin = 0v lin t bus 30 90 150 s a 9.2 time delay for mode change from fail-safe into normal mode via en pin v en = v cc en t norm 51520sa 9.3 time delay for mode change from normal mode to sleep mode via en pin v en = 0v en t sleep 2712sa 9.4 txd dominant time-out time v txd = 0v txd t dom 27 55 70 ms a 9.5 time delay for mode change from silent mode into normal mode via en v en = v cc en t s_n 51540sa 9.6 monitoring time for wake-up over lin bus lin t mon 61015msa 5. electrical characteristics (continued) 5v < v s < 27v, ?40c < t j < 150c, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 25 9159a?auto?09/10 atmel ata6614 [preliminary] lin bus driver ac paramete r with different bus loads load 1 (small): 1nf, 1k ; load 2 (large): 10nf, 500 ; r rxd =5k ; c rxd = 20pf; load 3 (medium): 6.8nf, 660 characterized on samples; 10.7 and 10.8 specifie s the timing parameters for proper operation of 20kbit/s, 10.9 and 10.10 at 10.4kbit/s 9.7 duty cycle 1 th rec(max) = 0.744 v s th dom(max) = 0.581 v s v s = 7.0v to 18v t bit = 50s d1 = t bus_rec(min) /(2 t bit ) lin d1 0.396 a 9.8 duty cycle 2 th rec(min) = 0.422 v s th dom(min) = 0.284 v s v s = 7.6v to 18v t bit = 50s d2 = t bus_rec(max) /(2 t bit ) lin d2 0.581 a 9.9 duty cycle 3 th rec(max) = 0.778 v s th dom(max) = 0.616 v s v s = 7.0v to 18v t bit = 96s d3 = t bus_rec(min) /(2 t bit ) lin d3 0.417 a 9.10 duty cycle 4 th rec(min) = 0.389 v s th dom(min) = 0.251 v s v s = 7.6v to 18v t bit = 96s d4 = t bus_rec(max) /(2 t bit ) lin d4 0.590 a 9.11 slope time falling and rising edge at lin v s = 7.0v to 18v lin t slope_fall t slope_rise 3.5 22.5 s a 10 receiver electrical ac parameters of the lin physical layer lin receiver, rxd lo ad conditions (c rxd ): 20 pf 10.1 propagation delay of receiver ( figure 5-1 on page 28 ) v s = 7.0v to 18v t rx_pd = max(t rx_pdr , t rx_pdf ) rxd t rx_pd 6sa 10.2 symmetry of receiver propagation delay rising edge minus falling edge v s = 7.0v to 18v t rx_sym = t rx_pdr ? t rx_pdf rxd t rx_sym ?2 +2 s a 11 pvcc_uv open drain output pin 11.1 low-level output voltage v s 5.5v i nres = 1ma nres v nresl 0.14 v a 11.2 low-level output low 10k to 5v v cc = 0v nres v nresll 0.14 v a 11.3 undervoltage reset time v s 5.5v c nres = 20pf pvcc_uv t reset 246msa 11.4 reset debounce time for falling edge v s 5.5v c nres = 20pf pvcc_uv t res_f 1.5 10 s a 11.5 switch off leakage current v nres = 5.5v pvcc_uv ?3 +3 a a 5. electrical characteristics (continued) 5v < v s < 27v, ?40c < t j < 150c, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 26 9159a?auto?09/10 atmel ata6614 [preliminary] 12 kl_15 pin 12.1 high-level input voltage r v = 47k positive edge initializes a wake-up kl_15 v kl_15h 4v s + 0.3v v a 12.2 low-level input voltage r v = 47k kl_15 v kl_15l ?1 +2 v a 12.3 kl_15 pull-down current v s < 27v v kl_15 = 27v kl_15 i kl_15 50 60 a a 12.4 internal debounce time without external capacitor kl_15 tdb kl_15 80 160 250 s a 12.5 kl_15 wake-up time r v = 47k , c = 100nf kl_15 tw kl_15 0.424.5msc 13 wake pin 13.1 high-level input voltage wake v wakeh v s ? 1v v s + 0.3v v a 13.2 low-level input voltage initializes a wake-up signal wake v wakel ?1 v s ? 3.3v v a 13.3 wake pull-up current v s < 27v, v wake = 0v wake i wake ?30 ?10 a a 13.4 high-level leakage current v s = 27v, v wake = 27v wake i wakel ?5 +5 a a 13.5 time of low pulse for wake-up via wake pin v wake = 0v wake i wakel 30 70 150 s a 14 vcc voltage regulator in normal/fail-safe an d silent mode, vcc and pvcc short-circuited 14.1 output voltage vcc 5.5v < v s < 18v (0ma to 50ma) vcc vcc nor 4.9 5.1 v a 14.2 output voltage vcc at low vs 4v < v s < 5.5v vcc vcc low v s ? v d 5.1 v a 14.3 regulator drop voltage v s > 4v, i vcc = ?20ma vs, vcc v d1 250 mv a 14.4 regulator drop voltage v s > 4v, i vcc = ?50ma vs, vcc v d2 400 600 mv a 14.5 regulator drop voltage v s > 3.3v, i vcc = ?15ma vs, vcc v d3 200 mv a 14.6 line regulation 5.5v < v s < 18v vcc vcc line 0.1 0.2 % a 14.7 load regulation 5ma < i vcc < 50ma at 100khz vcc vcc load 0.1 0.5 % a 14.8 power supply ripple rejection 10hz to 100khz c vcc = 10f v s = 14v, i vcc = ?15ma vcc 50 db d 14.9 output current limitation vs > 5.5v vcc i vcclim ?240 ?130 ?85 ma a 14.10 load capacity 0.2 < esr < 5 at 100khz vcc v thunn 1.8 10 f d 14.11 vcc undervoltage threshold referred to vcc v s > 5.5v vcc v thunn 4.2 4.8 v a 14.12 hysteresis of undervoltage threshold referred to vcc v s > 5.5v vcc vhys thun 250 mv a 14.13 ramp-up time v s > 5.5v to v cc = 5v c vcc = 2.2f i load = ?5ma at vcc vcc t vcc 370 600 s a 5. electrical characteristics (continued) 5v < v s < 27v, ?40c < t j < 150c, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 27 9159a?auto?09/10 atmel ata6614 [preliminary] 15 div_on input pin 15.1 low-level voltage input div_on v div_on ?0.3 +0.8 v a 15.2 high-level voltage input div_on v div_on 2v cc + 0.3 v a 15.3 pull-down resistor v div_on = v cc div_on r div_on 125 250 400 k a 15.4 low-level input current v div_on = 0v div_on i div_on ?3 +3 a a 16 sp_mode input pin 16.1 low-level voltage input sp_mode v sp_mode ?0.3 +0.8 v a 16.2 high-level voltage input sp_mode v sp_mode 2v cc + 0.3 v a 16.3 pull-down resistor v sp_mode = v cc sp_mode r sp_mode 50 125 200 k a 16.4 low-level input current v sp_mode = 0v sp_mode i sp_mode ?3 +3 a a 17 lin driver in high-speed mode(vsp_mode = vcc) 17.1 transmission baud rate v s = 7v to 18v r lin = 500 , c lin = 600pf lin sp 115 kbaud c 17.2 slope time lin falling edge v s = 7v to 18v lin t sl_fall 12sa 17.3 slope time lin rising edge, depending on rc-load v s = 14v r lin = 500 , c lin = 600pf lin t sl_rise 23sa 18 voltage divider 18.1 divider ratio vs = 5v to 27v pv 1:6 a 18.2 divider ratio error ?2 +2 % a 18.3 divider temperature drift 3 ppm/c c 18.4 vbatt range of divider linearity vbatt 5 27 v a 18.5 vbatt input current vbatt = 14v vbatt 100 220 a a 18.6 maximum output voltage at pv vbatt 27v to 40v pv 4.4 4.8 5.2 v a 18.7 pin capacitance pv 2 pf 5. electrical characteristics (continued) 5v < v s < 27v, ?40c < t j < 150c, unless otherwise specified. all values refer to gnd pins no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 28 9159a?auto?09/10 atmel ata6614 [preliminary] figure 5-1. definition of bus timing characteristics txd (input to transmitting node) vs (transceiver supply of transmitting node) rxd (output of receiving node1) rxd (output of receiving node2) lin bus signal thresholds of receiving node1 thresholds of receiving node2 t bus_rec(max) t rx_pdr(1) t rx_pdf(2) t rx_pdr(2) t rx_pdf(1) t bus_dom(min) t bus_dom(max) th rec(max) th dom(max) th rec(min) th dom(min) t bus_rec(min) t bit t bit t bit 29 9159a?auto?09/10 atmel ata6614 [preliminary] 6. microcontroller block 6.1 features ? high performance, low power avr 8-bit microcontroller ? advanced risc architecture ? 131 powerful instructions ? mo st single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 20mips throughput at 20mhz ? on-chip 2-cycle multiplier ? high endurance non-volatile memory segments ? 4/8/16/32k bytes of in-system self-programmable flash progam memory (atmel atmega48pa/88pa/168pa/328p) ? 256/512/512/1k bytes eeprom (atm el atmega48pa/88pa/168pa/328p) ? 512/1k/1k/2k bytes internal sram (atmel atmega48pa/88pa/168pa/328p) ? write/erase cycles: 10,000 flash/100,000 eeprom ? data retention: 20 years at 85c/100 years at 25c ? optional boot code section with independent lock bits ? in-system programming by on-chip boot program ? true read-while-write operation ? programming lock for software security ? peripheral features ? two 8-bit timer/counters with se parate prescaler and compare mode ? one 16-bit timer/counter with separate prescaler, compare mode, and capture mode ? real time counter with separate oscillator ? six pwm channels ? 8-channel 10-bit adc in tqfp and qfn/mlf package ? temperature measurement ? 6-channel 10-bit adc in pdip package ? temperature measurement ? programmable serial usart ? master/slave spi serial interface ? byte-oriented 2-wire serial interface (philips i2c compatible) ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? interrupt and wake-up on pin change ? special microcontroller features ? power-on reset and programm able brown-out detection ? internal calibrated oscillator ? external and internal interrupt sources ? six sleep modes: idle, adc noise reductio n, power-save, power-down, standby, and extended standby ? i/o and packages ? 23 programmable i/o lines ? 28-pin pdip, 32-lead tqfp, 28-p ad qfn/mlf and 32-pad qfn/mlf ? operating voltage: ? 1.8 - 5.5v for atmel atmega48pa/88pa/168pa/328p ? temperature range: ? -40c to 85c 30 9159a?auto?09/10 atmel ata6614 [preliminary] ? speed grade: ? 0 - 20mhz at 1.8 - 5.5v ? low power consumption at 1mhz, 1.8v, 25 c for atmel atmega48pa/88pa/168pa/328p: ? active mode: 0.2ma ? power-down mode: 0.1a ? power-save mode: 0.75a (including 32khz rtc) 31 9159a?auto?09/10 atmel ata6614 [preliminary] 6.2 overview the atmel ? atmega48pa/88pa/168pa/328p is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the atmel atmega48pa/88pa/168pa/ 328p achieves thro ughputs approaching 1mips per mhz allowing the system designer to optimize power consumption versus process- ing speed. 6.2.1 block diagram figure 6-1. block diagram port c (7) port b (8) port d (8) usart 0 8bit t/c 2 16bit t/c 1 8bit t/c 0 a/d conv. internal bandgap analog comp. spi twi sram flash eeprom watchdog oscillator watchdog timer oscillator circuits / clock generation power supervision por / bod & reset vcc gnd program logic debugwire 2 gnd aref avcc data b u s adc[6..7] pc[0..6] pb[0..7] pd[0..7] 6 reset xtal[1..2] cpu 32 9159a?auto?09/10 atmel ata6614 [preliminary] the avr ? core combines a rich instruction set wit h 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two inde- pendent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. the atmel ? atmega48pa/88pa/168pa/328p provides th e following features: 4k/8k bytes of in-system programmable flash with read-while-write capabilities, 256/512/512/1k bytes eeprom, 512/1k/1k/2k bytes sram, 23 general purpose i/o lines, 32 general purpose working registers, three flexible timer/counters with compare modes, internal and external interrupts, a serial programmable usart, a byte-oriented 2-wire serial interface, an spi serial port, a 6-channel 10-bit adc (8 channels in tqfp and qfn/mlf packages), a program- mable watchdog timer with internal oscillator, and five software selectable power saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, usart, 2-wire serial interface, spi port, and inte rrupt system to continue functioning. the power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. in power-save mode, the asynchro- nous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. the adc noise reduction mode stops the cpu and all i/o modules except asynchronous timer and adc, to minimize switching noise during adc conversions. in standby mode, the cr ystal/resonator oscillator is running wh ile the rest of the device is sleep- ing. this allows very fast start-up combined with low power consumption. the device is manufactured using atmel?s high density non-volatile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system through an spi serial interface, by a conventional non-volatile memory programmer, or by an on-chip boot program running on the avr core. the boot program can use any interface to download the application program in the application flas h memory. software in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. by combining an 8-bit risc cpu with in-system self-program- mable flash on a monolithic chip, the atme l atmega48pa/88pa/168pa/328p is a powerful microcontroller that provides a highly flexib le and cost effective solution to many embedded control applications. the atmel atmega48pa/88pa/168pa/328p avr is supported with a full suite of program and system development tools including: c comp ilers, macro assemblers, program debug- ger/simulators, in-circuit emulators, and evaluation kits. 6.2.2 comparison between atmel atmega48pa, atmega88pa, atmega168pa and atmega328p the atmel atmega48pa, atmega88pa, atmega168pa and atmega328p differ only in memory sizes, boot loader support, and interrupt vector sizes. table 6-1 summarizes the dif- ferent memory and interrupt vector sizes for the three devices. table 6-1. memory size summary device flash eeprom ram in terrupt vector size atmega48pa 4k bytes 256 bytes 512 bytes 1 instruction word/vector atmega88pa 8k bytes 512 bytes 1k bytes 1 instruction word/vector atmega168pa 16k bytes 512 bytes 1k bytes 2 instruction words/vector atmega328p 32k bytes 1k bytes 2k bytes 2 instruction words/vector 33 9159a?auto?09/10 atmel ata6614 [preliminary] atmel atmega88pa, atmega168pa and atmega328p support a real read-while-write self-programming mechanism. there is a separate boot loader section, and the spm instruction can only execute from there. in atmega48pa, there is no read-while-write sup- port and no separate boot loader section. the spm instruction can execute from the entire flash. 6.3 resources a comprehensive set of development tools, application notes and datasheets are available for download on http:// www.atmel.com/avr. note: 1. 6.4 data retention reliability qualification re sults show that the projected data retention failure rate is much less than 1ppm over 20 years at 85c or 100 years at 25c. 6.5 about code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume th at the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c com- piler documentation for more details. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructions that allow access to extended i/o. typically ?lds? and ?sts? combined with ? sbrs?, ?sbrc?, ?sbr?, and ?cbr?. 34 9159a?auto?09/10 atmel ata6614 [preliminary] 6.6 atmel avr cpu core 6.6.1 overview this section discusses the avr core architecture in general. the main function of the cpu core is to ensure correct program execution. the cpu must therefore be able to access mem- ories, perform calculations, control peripherals, and handle interrupts. figure 6-2. block diagram of the avr architecture in order to maximize performance and parallelism, the atmel ? avr uses a harvard architec- ture ? with separate memories and buses for program and data. instructions in the program memory are executed with a single level pipeli ning. while one instruction is being executed, the next instruction is pre-fetched from the program memory. this concept enables instruc- tions to be executed in every clock cycle. the program memory is in-system reprogrammable flash memory. flash program memory instruction register instruction decoder program counter control lines 32 x 8 general purpose registrers alu status and control i/o lines eeprom data bus 8-bit data sram direct addressing indirect addressing interrupt unit spi unit watchdog timer analog comparator i/o module 2 i/o module1 i/o module n 35 9159a?auto?09/10 atmel ata6614 [preliminary] the fast-access register file contains 32 x 8-bit general purpose working registers with a sin- gle clock cycle access time. this allows single-cyc le arithmetic logic un it (alu) operation. in a typical alu operation, two operands are output from the register file, the operation is exe- cuted, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing ? enabling efficient address ca lculations. one of the these address pointers can also be used as an address pointer for l ook up tables in flash program memory. these added function registers are the 16-bit x-, y-, and z-register, described later in this section. the alu supports arithmetic and logic operations between registers or between a constant and a register. single register operations can also be executed in the alu. after an arithmetic operation, the status register is updated to reflect information about the result of the operation. program flow is provided by conditional and un conditional jump and call instructions, able to directly address the whole address space. most avr instructions have a single 16-bit word format. every program memory address contains a 16- or 32-bit instruction. program flash memory space is divided in two sections, the boot program section and the application program section. both sections have dedicated lock bits for write and read/write protection. the spm instruction that writes into the application flash memory section must reside in the boot program section. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram, and consequently the stack size is only limited by t he total sram size and the usage of the sram. all user pro- grams must initialize the sp in the reset routine (before subroutines or interrupts are executed). the stack pointer (sp) is read/writ e accessible in the i/o space. the data sram can easily be accessed through the five different addressing modes supported in the atmel avr architecture. the memory spaces in the atmel avr architecture are all linear and regular memory maps. a flexible interrupt module has its control registers in the i/o space with an additional global interrupt enable bit in the status register. all interrupts have a separate interrupt vector in the interrupt vector table. the interrupts have priority in accordance with their interrupt vector position. the lower the interrupt vector address, the higher the priority. the i/o memory space contains 64 addresses for cpu peripheral functions as control regis- ters, spi, and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5f. in addition, the atmel atmega48pa/88pa/168pa/328p has extended i/o spac e from 0x60 - 0xff in sram where only the st/sts/std and ld/lds/ldd instructions can be used. 6.6.2 alu ? arithmetic logic unit the high-performance atmel avr alu operates in direct connection with all the 32 general purpose working registers. within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. the alu operations are divided into three main categories ? arithmetic, logical, and bit-functions. some implemen- tations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. see the ?instruction set? section for a detailed description. 36 9159a?auto?09/10 atmel ata6614 [preliminary] 6.6.3 status register the status register contains information about the result of the most recently executed arith- metic instruction. this information can be used for altering program flow in order to perform conditional operations. note that the status register is updated after all alu operations, as specified in the instruction set reference. this will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. this must be handled by software. 6.6.3.1 sreg ? avr status register the avr status register ? sreg ? is defined as: ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set for the interrupts to be enabled. the individual interrupt enable control is then performed in separate control registers. if the global interrupt enable register is cleared, none of the in terrupts are enabled independent of the individual interrupt enable settings. the i-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupts. the i-bit can also be set and cleared by the application with the sei and cli in structions, as described in the instruction set reference. ? bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (bit store) use the t-bit as source or des- tination for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 ? h: half carry flag the half carry flag h indicates a half carry in some arithmetic operations. half carry is use- ful in bcd arithmetic. see the ?instruction set description? for detailed information. ? bit 4 ? s: sign bit, s = n v the s-bit is always an exclusive or between the negative flag n and the two?s complement overflow flag v. see the ?instruction set description? for detailed information. ? bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v supports two?s complement arithmetics. see the ?instruction set description? for detailed information. ? bit 2 ? n: negative flag the negative flag n indicates a negative result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. bit 76543210 0x3f (0x5f) i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 37 9159a?auto?09/10 atmel ata6614 [preliminary] ? bit 1 ? z: zero flag the zero flag z indicates a zero result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. ? bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see the ?instruction set description? for de tailed information. 6.6.4 general purpose register file the register file is optimized for the avr enhanc ed risc instruction set. in order to achieve the required performance and flexibility, the fo llowing input/output schemes are supported by the register file: ? one 8-bit output operand and one 8-bit result input ? two 8-bit output operands and one 8-bit result input ? two 8-bit output operands and one 16-bit result input ? one 16-bit output operand and one 16-bit result input figure 6-3 shows the structure of the 32 general purpose working registers in the cpu. figure 6-3. avr cpu general purpose working registers most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle instructions. as shown in figure 6-3 , each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. although not being physically imple- mented as sram locations, this me mory organization pr ovides great flexibility in access of the registers, as the x-, y- and z-pointer registers can be set to index any register in the file. 70addr. r0 0x00 r1 0x01 r2 0x02 ? r13 0x0d general r14 0x0e purpose r15 0x0f working r16 0x10 registers r17 0x11 ? r26 0x1a x-register low byte r27 0x1b x-register high byte r28 0x1c y-register low byte r29 0x1d y-register high byte r30 0x1e z-register low byte r31 0x1f z-register high byte 38 9159a?auto?09/10 atmel ata6614 [preliminary] 6.6.4.1 the x-register, y-register, and z-register the registers r26..r31 have some added func tions to their general purpose usage. these registers are 16-bit address pointers for indirect addressing of the data space. the three indi- rect address registers x, y, and z are defined as described in figure 6-4 . figure 6-4. the x-, y-, and z-registers in the different addressing modes these address registers have functions as fixed displace- ment, automatic increment, and automatic decrement (see the instruction set reference for details). 6.6.5 stack pointer the stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. note that the stack is implemented as growing from higher to lower me mory locations. the stack poin ter register always points to the top of the stack. the stack pointer points to the data sram stack area where the subrou- tine and interrupt stacks are located. a stack push command will decrease the stack pointer. the stack in the data sram must be defined by the program before any subroutine calls are executed or interrupts are enabled. initial stack pointer value equals the last address of the internal sram and the stack pointer must be set to point above start of the sram, see table 6-9 on page 44 . see table 6-2 for stack pointer details. the avr stack pointer is implemented as two 8-bit registers in the i/o space. the number of bits actually used is implementation dependent. note that the data space in some implementa- tions of the avr architecture is so small that only spl is needed. in this case, the sph register will not be present. 15 xh xl 0 x-register 707 0 r27 (0x1b) r26 (0x1a) 15 yh yl 0 y-register 707 0 r29 (0x1d) r28 (0x1c) 15 zh zl 0 z-register 70 7 0 r31 (0x1f) r30 (0x1e) table 6-2. stack pointer instructions instruction stack pointer description push decremented by 1 data is pushed onto the stack call icall rcall decremented by 2 return address is pushed onto the stack with a subroutine call or interrupt pop incremented by 1 data is popped from the stack ret reti incremented by 2 return address is popped from the stack with return from subroutine or return from interrupt 39 9159a?auto?09/10 atmel ata6614 [preliminary] 6.6.5.1 sph and spl ? stack pointer high and stack pointer low register 6.6.6 instruction execution timing this section describes the general access timing concepts for instruction execution. the avr cpu is driven by the cpu clock clk cpu , directly generated from the selected clock source for the chip. no internal cl ock division is used. figure 6-5 shows the parallel instruction fetches and instruction executions enabled by the harvard architecture and the fa st-access register file concept . this is the basic pipelining concept to obtain up to 1 mips per mhz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. figure 6-5. the parallel instruction fetches and instruction executions figure 6-6 shows the internal timing concept for t he register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destination register. figure 6-6. single cycle alu operation bit 151413121110 9 8 0x3e (0x5e) sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sph 0x3d (0x5d) sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value ramend ramend rame nd ramend ramend ra mend ramend ramend ramend ramend rame nd ramend ramend ra mend ramend ramend clk 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 cpu total execution time register operands fetch alu operation execute result write back t1 t2 t3 t4 clk cpu 40 9159a?auto?09/10 atmel ata6614 [preliminary] 6.6.7 reset and interrupt handling the avr provides several different interrupt sources. these interrupts and the separate reset vector each have a separate program vector in the program memory space. all interrupts are assigned individual enable bits which must be written logic one together with the global inter- rupt enable bit in the status register in order to enable the interrupt. depending on the program counter value, interrupts may be automatically disabled when boot lock bits blb02 or blb12 are programmed. this feature improves software security. see the section ?memory programming? on page 319 for details. the lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. the complete list of vectors is shown in ?interrupts? on page 81 . the list also determines the priority levels of the different interrupts. the lower the address the higher is the priority level. reset has the highest priority , and next is int0 ? the external interrupt request 0. the interrupt vectors can be moved to the start of the boot flash section by set- ting the ivsel bit in the mcu cont rol register (mcucr). refer to ?interrupts? on page 81 for more information. the reset vector can also be moved to the start of the boot flash section by programming the bootrst fuse, see ?boot loader support ? read-while-write self-programming, atmel atmega88pa, atmega168pa and atmega328p? on page 302 . when an interrupt occurs, the global interrupt enable i-bit is cleared and all interrupts are dis- abled. the user software can write logic one to the i-bit to enable nested interrupts. all enabled interrupts can then interrupt the current interrupt routine. the i-bit is automatically set when a return from interrupt instruction ? reti ? is executed. there are basically two types of interrupts. the first type is triggered by an event that sets the interrupt flag. for these interrupts, the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, and hardware clears the correspond- ing interrupt flag. interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. if an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the in terrupt flag will be set and reme mbered until the interrupt is enabled, or the flag is cleared by software. similarly, if one or more interrupt conditions occur while the global interrupt enable bit is cleared, the correspond ing interrupt flag(s) will be set and remembered until the global inte rrupt enable bit is set, and will then be executed by order of priority. the second type of interrupts will trigger as long as t he interrupt c ondition is present. these interrupts do not necessarily have interrupt flags. if the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. when the avr exits from an in terrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. note that the status register is not automat ically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. this must be handled by software. when using the cli instruction to disable interrupts, the interrupts will be immediately dis- abled. no interrupt will be executed after the cl i instruction, even if it occurs simultaneously with the cli instruction. the following example shows how this can be used to avoid interrupts during the timed eeprom write sequence. 41 9159a?auto?09/10 atmel ata6614 [preliminary] when using the sei instruction to enable interrupts, the instruction following sei will be exe- cuted before any pending interrupts, as shown in this example. 6.6.7.1 interrupt response time the interrupt execution response for all the ena bled avr interrupts is four clock cycles mini- mum. after four clock cycles the program vector address for the actual interrupt handling routine is executed. during th is four clock cycle period, the program counter is pushed onto the stack. the vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. if an interrupt occu rs during execution of a multi-cycl e instruction, this instruction is completed before the interrupt is served. if an interrupt occurs when the mcu is in sleep mode, the interrupt execution response time is increased by four clock cycles. this increase comes in addition to the start-up time from the selected sleep mode. a return from an interrupt handling routine takes four clock cycles. during these four clock cycles, the program counter (two bytes) is popped back from the stack, the stack pointer is incremented by two, and the i-bit in sreg is set. assembly code example in r16, sreg ; store sreg value cli ; disable interrupts during timed sequence sbi eecr, eempe ; start eeprom write sbi eecr, eepe out sreg, r16 ; restore sreg value (i-bit) c code example char csreg; csreg = sreg; /* store sreg value */ /* disable interrupts during timed sequence */ _cli(); eecr |= (1< 43 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-7. program memory map atmel ? atmega48pa figure 6-8. program memory map atmel atmega88pa, atmega168pa and atmega328p 0x0000 0x7ff program memory application flash section 0x0000 0x0fff/0x1fff/0x3fff program memory application flash section boot flash section 44 9159a?auto?09/10 atmel ata6614 [preliminary] 6.7.3 sram data memory figure 6-9 shows how the atmel atmega48pa/88pa/168pa/328p sram memory is organized. the atmel atmega48pa/88pa/168pa/328p is a complex microcontroller with more periph- eral units than can be supported within the 64 locations reserved in the opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. the lower 768/1280/1280/2303 data memory locations address both the register file, the i/o memory, extended i/o memory, and the internal data sram. the first 32 locations address the register file, the next 64 location the standard i/o memory, then 160 locations of extended i/o memory, and the next 512/1024/1024/2048 locations address the internal data sram. the five different addressing modes for the data memory cover: direct, indirect with displace- ment, indirect, indirect with pre-decrement, and indirect with post-increment. in the register file, registers r26 to r31 feature the indirect addressing pointer registers. the direct addressing reaches the entire data space. the indirect with displacement mode reaches 63 address locations from the base address given by the y- or z-register. when using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers x, y, and z are decremented or incremented. the 32 general purpose working registers, 64 i/o registers, 160 extended i/o registers, and the 512/1024/1024/2048 bytes of internal data sram in the atmega48pa/88pa/168pa/328p are all accessible through all these addressing modes. the register file is described in ?gen- eral purpose register file? on page 37 . figure 6-9. data memory map 32 registers 64 i/o registers internal sram (512/1024/1024/2048 x 8) 0x0000 - 0x001f 0x0020 - 0x005f 0x04ff/0x04ff/0x0ff/0x08ff 0x0060 - 0x00ff data memory 160 ext i/o reg. 0x0100 45 9159a?auto?09/10 atmel ata6614 [preliminary] 6.7.3.1 data memory access times this section describes the general access timi ng concepts for internal memory access. the internal data sram access is performed in two clk cpu cycles as described in figure 6-10 . figure 6-10. on-chip data sram access cycles 6.7.4 eeprom data memory the atmel ? atmega48pa/88pa/168pa/328p contains 256/512/512/1k bytes of data eeprom memory. it is organized as a separate data sp ace, in which single bytes can be read and written. the eeprom has an endurance of at least 100,000 write/erase cycles. the access between the eeprom and the cpu is de scribed in the following, specifying the eeprom address registers, the eeprom da ta register, and the eeprom control register. ?memory programming? on page 319 contains a detailed desc ription on eeprom program- ming in spi or para llel programming mode. 6.7.4.1 eeprom read/write access the eeprom access registers are accessible in the i/o space. the write access time for the eeprom is given in table 6-4 . a self-timing function, however, lets the user software detect when the next byte can be written. if the user code contains instructions that write the eeprom, some precautions must be taken. in heavily filtered power supplies, v cc is likely to rise or fall slowly on power-up/down. this causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. see ?preventing eeprom co rruption? on page 46 for details on how to avoid problems in these situations. in order to prevent unintenti onal eeprom writes, a specific wr ite procedure must be followed. refer to the description of the eeprom control regist er for details on this. when the eeprom is read, the cpu is halted for four clock cycl es before the ne xt instruction is executed. when the eeprom is written, the cpu is halted for two clock cycles before the next instruction is executed. clk wr rd data data address address valid t1 t2 t3 compute address read write cpu memory access instruction next instruction 46 9159a?auto?09/10 atmel ata6614 [preliminary] 6.7.4.2 preventing eeprom corruption during periods of low v cc, the eeprom data can be corrupted because the supply voltage is too low for the cpu and the eeprom to operate properly. these issues are the same as for board level systems using eepr om, and the same design so lutions should be applied. an eeprom data corruption can be caused by two situations when the voltage is too low. first, a regular write sequence to the eeprom requires a minimum voltage to operate cor- rectly. secondly, the cpu itself ca n execute instructions incorrectly, if the supply voltage is too low. eeprom data corruption can ea sily be avoided by followin g this design recommendation: keep the avr reset active (low) during periods of insufficient power supply voltage. this can be done by enabling the internal brown-out detector (bod). if the detection level of the internal bod does not match the needed detection level, an external low v cc reset protection circuit can be used. if a reset occurs while a writ e operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 6.7.5 i/o memory the i/o space definition of the atmel ? atmega48pa/88pa/168pa/328p is shown in ?register summary? on page 447 . all atmel ? atmega48pa/88pa/168pa/328p i/os and peripherals are placed in the i/o space. all i/o locations may be accessed by the ld/lds/ldd and st/sts/std instructions, transfer- ring data between the 32 general purpose workin g registers and the i/o space. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instruc- tions. in these registers, the value of singl e bits can be checked by using the sbis and sbic instructions. refer to the instruction set section for more details. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the atmel ? atmega48pa/88pa/168pa/328p is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. for compatibility with future devi ces, reserved bits should be wr itten to zero if accessed. reserved i/o memory addresses should never be written. some of the status flags are cleared by writing a logical one to them. note that, unlike most other avrs, the cbi and sbi inst ructions will only operate on th e specified bit, and can there- fore be used on registers containing such st atus flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. the i/o and peripherals control registers are explained in later sections. 6.7.5.1 general purpose i/o registers the atmel ? atmega48pa/88pa/168pa/328p contains th ree general purpose i/o registers. these registers can be used for storing any information, and they are particularly useful for storing global variables and status flags. ge neral purpose i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi, cbi, sbis, and sbic instructions. 47 9159a?auto?09/10 atmel ata6614 [preliminary] 6.7.6 register description 6.7.6.1 eearh and eearl ? the eeprom address register ? bits 15..9 ? res: reserved bits these bits are reserved bits in the atmel ? atmega48pa/88pa/168pa/328p and will always read as zero. ? bits 8..0 ? eear8..0: eeprom address the eeprom address registers ? eearh and eearl specify the eeprom address in the 256/512/512/1k bytes eeprom space. the eeprom data bytes are addressed linearly between 0 and 255/511/5 11/1023. the initial valu e of eear is undefined . a proper value must be written before the eepr om may be accessed. eear8 is an unused bit in atmega48pa and must always be written to zero. 6.7.6.2 eedr ? the eeprom data register ? bits 7..0 ? eedr7.0: eeprom data for the eeprom write oper ation, the eedr register contains the data to be written to the eeprom in the address given by the eear register. for the eeprom read op eration, the eedr contains the data read out from the eeprom at the add ress given by eear. 6.7.6.3 eecr ? the eeprom control register ? bits 7..6 ? res: reserved bits these bits are reserved bits in the atmel atmega48pa/88pa/168pa/328p and will always read as zero. bit 151413121110 9 8 0x22 (0x42) ???????eear8eearh 0x21 (0x41) eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 eearl 76543210 read/write rrrrrrrr/w r/w r/w r/w r/w r/w r/w r/w r/w initial value0000000x xxxxxxxx bit 76543210 0x20 (0x40) msb lsb eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x1f (0x3f) ? ? eepm1 eepm0 eerie eempe eepe eere eecr read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 x x 0 0 x 0 48 9159a?auto?09/10 atmel ata6614 [preliminary] ? bits 5, 4 ? eepm1 and eepm0: eeprom programming mode bits the eeprom programming mode bit setting def ines which programming action that will be triggered when writing eepe. it is possible to program data in one atomic operation (erase the old value and program the new value) or to split the erase and write operations in two differ- ent operations. the programming times for the different modes are shown in table 6-3 . while eepe is set, any write to eepmn will be ignored. during reset, the eepmn bits will be reset to 0b00 unless the eeprom is busy programming. ? bit 3 ? eerie: eeprom ready interrupt enable writing eerie to one enables the eeprom ready interrupt if the i bit in sreg is set. writing eerie to zero disables the interrupt. the eeprom ready interrupt generates a constant interrupt when eepe is cleared. the interrupt will not be generated during eeprom write or spm. ? bit 2 ? eempe: eeprom master write enable the eempe bit determines whether setting eepe to one causes the eeprom to be written. when eempe is set, setting eepe within four clock cycles will write data to the eeprom at the selected address if eempe is zero, se tting eepe will have no effect. when eempe has been written to one by software, hardware clears the bit to zero after four clock cycles. see the description of the eepe bit fo r an eeprom write procedure. ? bit 1 ? eepe: eeprom write enable the eeprom write enable signal eepe is t he write strobe to the eeprom. when address and data are correctly set up, th e eepe bit must be written to on e to write the value into the eeprom. the eempe bit must be wr itten to one be fore a logical one is written to eepe, oth- erwise no eeprom write takes place. the following procedure should be followed when writing the eeprom (the order of steps 3 and 4 is not essential): 1. wait until eepe becomes zero. 2. wait until selfprgen in spmcsr becomes zero. 3. write new eeprom address to eear (optional). 4. write new eeprom data to eedr (optional). 5. write a logical one to the eempe bit while writing a zero to eepe in eecr. 6. within four clock cycles after sett ing eempe, write a logical one to eepe. table 6-3. eeprom mode bits eepm1 eepm0 programming time operation 0 0 3.4ms erase and write in one operation (atomic operation) 01 1.8mserase only 1 0 1.8ms write only 1 1 ? reserved for future use 49 9159a?auto?09/10 atmel ata6614 [preliminary] the eeprom can not be programmed during a cpu write to the flash memory. the software must check that the flash programming is completed before initiating a new eeprom write. step 2 is only relevant if the software contains a boot loader allowing the cpu to program the flash. if the flash is never being updated by the cpu, step 2 can be omitted. see ?boot loader support ? read-while-write self-programming, atmel atmega88pa, atmega168pa and atmega328p? on page 302 for details about boot programming. caution: an interrupt between step 5 and step 6 will make the write cycle fail, since the eeprom master write enable will time-out. if an interrupt ro utine accessing the eeprom is interrupting another eeprom access, the eear or eedr register will be modified, causing the interrupte d eeprom access to fail. it is recommend ed to have the gl obal interrupt flag cleared during all the steps to avoid these problems. when the write access time has elapsed, the eepe bit is cleared by hard ware. the user soft- ware can poll this bit and wait for a zero before writing the next byte. when eepe has been set, the cpu is halted for two cycles be fore the next instruction is executed. ? bit 0 ? eere: eeprom read enable the eeprom read enable signal eere is the read strobe to the eeprom. when the cor- rect address is set up in the eear register, the eere bit must be written to a logic one to trigger the eeprom read. the eeprom read access takes one instruction, and the requested data is availa ble immediately. when the eeprom is read, the cpu is halted for four cycles before the next instruction is executed. the user should poll the eepe bit before starting the read operation. if a write operation is in progress, it is neither possi ble to read the eeprom, nor to change the eear register. the calibrated oscillator is used to time the eeprom accesses. table 6-4 lists the typical programming time for eeprom access from the cpu. the following code examples show one assemb ly and one c function for writing to the eeprom. the examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur duri ng execution of these functions. the examples also assume that no flash boot loader is present in the software. if such code is present, the eeprom write function must also wait fo r any ongoing spm command to finish. table 6-4. eeprom programming time symbol number of calibrated rc oscillator cycles typ programming time eeprom write (from cpu) 26,368 3.3ms 50 9159a?auto?09/10 atmel ata6614 [preliminary] assembly code example eeprom_write: ; wait for completion of previous write sbic eecr,eepe rjmp eeprom_write ; set up address (r18:r17) in address register out eearh, r18 out eearl, r17 ; write data (r16) to data register out eedr,r16 ; write logical one to eempe sbi eecr,eempe ; start eeprom write by setting eepe sbi eecr,eepe ret c code example void eeprom_write( unsigned int uiaddress, unsigned char ucdata) { /* wait for completion of previous write */ while(eecr & (1< 53 9159a?auto?09/10 atmel ata6614 [preliminary] 6.8.1.4 asynchronous timer clock ? clk asy the asynchronous timer clock allows the asynchronous timer/counter to be clocked directly from an external clock or an external 32khz clock crystal. the dedicated clock domain allows using this timer/counter as a real-time counter even when the device is in sleep mode. 6.8.1.5 adc clock ? clk adc the adc is provided with a dedicated clock domain. this allows halting the cpu and i/o clocks in order to reduce noise generated by digi tal circuitry. this gives more accurate adc conversion results. 6.8.2 clock sources the device has the following clock source options , selectable by flash fuse bits as shown below. the clock from the selected source is input to the avr clock generator, and routed to the appropriate modules. note: 1. for all fuses ?1? means unprogrammed while ?0? means programmed. 6.8.2.1 default clock source the device is shipped with internal rc oscill ator at 8.0mhz and with the fuse ckdiv8 pro- grammed, resulting in 1.0mhz system clock. the startup time is set to maximum and time-out period enabled. (cksel = "0010", sut = "10", ckdiv8 = "0"). the default setting ensures that all users can make their desired clock source setting using any available programming interface. 6.8.2.2 clock startup sequence any clock source needs a sufficient v cc to start oscillating and a minimum number of oscillat- ing cycles before it can be considered stable. to ensure sufficient v cc , the device issues an internal reset with a time-out delay (t tout ) after the device reset is released by all other reset sources. ?system control and reset? on page 71 describes the start conditions for the internal reset. the delay (t tout ) is timed from the watch- dog oscillator and the number of cycles in the delay is set by the sutx and ckselx fuse bits. the selectable delays are shown in table 6-6 . the frequency of the watchdog oscillator is voltage dependent as shown in ?typical characteristics? on page 350 . table 6-5. device clocking options select (1) device clocking option cksel3..0 low power crystal oscillator 1111 - 1000 full swing crystal oscillator 0111 - 0110 low frequency crystal oscillator 0101 - 0100 internal 128 khz rc oscillator 0011 calibrated internal rc oscillator 0010 external clock 0000 reserved 0001 54 9159a?auto?09/10 atmel ata6614 [preliminary] main purpose of the delay is to keep the atmel ? avr ? in reset until it is supplied with minimum v cc . the delay will not monitor the actual voltage and it will be r equired to select a delay lon- ger than the v cc rise time. if this is not possible, an internal or external brown-out detection circuit should be used. a bod circuit will ensure sufficient v cc before it releases the reset, and the time-out delay can be disabled. disabling the time-out delay without utilizing a brown-out detection circuit is not recommended. the oscillator is required to osc illate for a minimum num ber of cycles before the clock is con- sidered stable. an internal rippl e counter monitors the oscilla tor output clock, and keeps the internal reset active for a given number of clock cycles. the reset is then released and the device will start to execute. the recommended oscillator start-up time is dependent on the clock type, and varies fr om 6 cycles for an externally applie d clock to 32k cycles for a low fre- quency crystal. the start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts up from reset. when starting up from power-save or power-down mode, v cc is assumed to be at a sufficient level and only the start-up time is included. 6.8.3 low power crystal oscillator pins xtal1 and xtal2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on -chip oscillator, as shown in figure 6-12 on page 54 . either a quartz crystal or a ceramic resonator may be used. this crystal oscillator is a low power oscillato r, with reduced voltag e swing on the xtal2 out- put. it gives the lowest power consumption, but is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments. in these cases, refer to the ?full swing crystal oscillator? on page 56 . c1 and c2 should always be equal for both crystals and resonators. the optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. some initial guidelines for choosing capacitors for use with crystals are given in table 6-7 on page 55 . for ceramic resonators, the capacitor values given by the manufacturer should be used. figure 6-12. crystal oscillator connections table 6-6. number of watchdog oscillator cycles typ time-out (v cc = 5.0v) typ time-out (v cc = 3.0v) number of cycles 0ms 0ms 0 4.1ms 4.3ms 512 65ms 69ms 8k (8,192) xtal2 (tosc2) xtal1 (tosc1) gnd c2 c1 55 9159a?auto?09/10 atmel ata6614 [preliminary] the low power oscillator can operate in three different modes, each optimized for a specific frequency range. the operating mode is selected by the fuses cksel3..1 as shown in table 6-7 on page 55 . notes: 1. this is the recommanded cksel settings for the difference frenquency ranges. 2. this option should not be used with crystals, only with ceramic resonators. 3. if 8 mhz frequency exceeds the specification of the device (depends on v cc ), the ckdiv8 fuse can be programmed in order to divide the internal frequency by 8. it must be ensured that the resulting divided clock meets th e frequency specification of the device. the cksel0 fuse together with the sut1..0 fuses select the start-up times as shown in table 6-8 . notes: 1. these options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. these options are not suitable for crystals. 2. these options are intended for use with ce ramic resonators and will ensure frequency stabil- ity at start-up. they can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stab ility at start-up is not important for the application. table 6-7. low power crystal osc illator operating modes (3) frequency range (mhz) recommended range for capacitors c1 an d c2 (pf) cksel3..1 (1) 0.4 - 0.9 ? 100 (2) 0.9 - 3.0 12 - 22 101 3.0 - 8.0 12 - 22 110 8.0 - 16.0 12 - 22 111 table 6-8. start-up times for the low power cr ystal oscillator clock selection oscillator source / power conditions start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) cksel0 sut1..0 ceramic resonator, fast rising power 258 ck 14ck + 4.1ms (1) 000 ceramic resonator, slowly rising power 258 ck 14ck + 65ms (1) 001 ceramic resonator, bod enabled 1k ck 14ck (2) 010 ceramic resonator, fast rising power 1k ck 14ck + 4.1ms (2) 011 ceramic resonator, slowly rising power 1k ck 14ck + 65ms (2) 100 crystal oscillator, bod enabled 16k ck 14ck 1 01 crystal oscillator, fast rising power 16k ck 14ck + 4.1ms 1 10 crystal oscillator, slowly rising power 16k ck 14ck + 65ms 1 11 56 9159a?auto?09/10 atmel ata6614 [preliminary] 6.8.4 full swing crystal oscillator pins xtal1 and xtal2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on -chip oscillator, as shown in figure 6-12 on page 54 . either a quartz crystal or a ceramic resonator may be used. this crystal oscillator is a full swing oscillator, with rail-to-rail swing on the xtal2 output. this is useful for driving other clock inputs and in noisy environments. the current consumption is higher than the ?low power crystal oscillator? on page 54 . note that the full swing crystal oscillator will only operate for v cc = 2.7 - 5.5v. c1 and c2 should always be equal for both crystals and resonators. the optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. some initial guidelines for choosing capacitors for use with crystals are given in table 6-10 on page 57 . for ceramic resonators, the capacitor values given by the manufacturer should be used. the operating mode is selected by the fuses cksel3..1 as shown in table 6-9 . notes: 1. if 8mhz frequency exceeds the specification of the device (depends on v cc ), the ckdiv8 fuse can be programmed in order to divide the internal frequency by 8. it must be ensured that the resulting divided clock meets th e frequency specification of the device. figure 6-13. crystal oscillator connections table 6-9. full swing crystal osc illator operating modes frequency range (1) (mhz) recommended range for capacitors c1 and c2 (pf) cksel3..1 0.4 - 20 12 - 22 011 xtal2 (tosc2) xtal1 (tosc1) gnd c2 c1 57 9159a?auto?09/10 atmel ata6614 [preliminary] notes: 1. these options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. these options are not suitable for crystals. 2. these options are intended for use with ce ramic resonators and will ensure frequency stabil- ity at start-up. they can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stab ility at start-up is not important for the application. table 6-10. start-up times for the full swing crystal oscillator clock selection oscillator source / power conditions start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) cksel0 sut1..0 ceramic resonator, fast rising power 258ck 14ck + 4.1ms (1) 000 ceramic resonator, slowly rising power 258ck 14ck + 65ms (1) 001 ceramic resonator, bod enabled 1k ck 14ck (2) 010 ceramic resonator, fast rising power 1k ck 14ck + 4.1ms (2) 011 ceramic resonator, slowly rising power 1k ck 14ck + 65ms (2) 100 crystal oscillator, bod enabled 16k ck 14ck 1 01 crystal oscillator, fast rising power 16k ck 14ck + 4.1ms 1 10 crystal oscillator, slowly rising power 16k ck 14ck + 65ms 1 11 58 9159a?auto?09/10 atmel ata6614 [preliminary] 6.8.5 low frequency crystal oscillator the low-frequency crystal osc illator is optimized for use wi th a 32.768khz watch crystal. when selecting crystals, load capasitance and crystal?s equivalent series resistance, esr must be taken into consideration. both values are specified by the crystal vendor. atmel atmega48pa/88pa/168 pa/328p oscillator is optimized for very low power consumption, and thus when selecting crystals, see table 6-11 on page 58 for maximum esr recommendations on 6.5pf, 9.0pf and 12.5pf crystals table 6-11. maximum esr recommendation for 32.768khz crystal note: 1. maximum esr is typical value based on characterization the low-frequency crystal oscillator provides an internal load capacit ance of typical 6pf at each tosc pin. the external capacitance (c) needed at each tosc pin can be calculated by using: where cl is the load capacitance for a 32.768kh z crystal specified by the crystal vendor and c s is the total stray capacitance for one tosc pin. crystals specifying load capacitance (cl) higher than 6pf, require external capacitors applied as described in figure 6-12 on page 54 . the low-frequency crystal oscilla tor must be selected by sett ing the cksel fuses to ?0110? or ?0111?, as shown in table 6-13 . start-up times are determined by the sut fuses as shown in table 6-12 . note: 1. this option should only be used if frequen cy stability at start-up is not important for the application crystal cl (pf) max esr [k ] (1) 6.5 75 9.0 65 12.5 30 table 6-12. start-up times for the lo w-frequency crystal os cillator clock selection sut1..0 additional delay from reset (v cc = 5.0v) recommended usage 00 4ck fast rising power or bod enabled 01 4ck + 4.1ms slowly rising power 10 4ck + 65ms stable frequency at start-up 11 reserved table 6-13. start-up times for the lo w-frequency crystal os cillator clock selection cksel3..0 start-up time from power-down and power-save recommended usage 0100 (1) 1k ck 0101 32k ck stable frequency at start-up c 2 cl ? c s ? = 59 9159a?auto?09/10 atmel ata6614 [preliminary] 6.8.6 calibrated internal rc oscillator by default, the internal rc os cillator provides an approximat e 8.0mhz clock. though voltage and temperature dependent, this clock can be very accurately calibrated by the user. see table 6-139 on page 342 for more details. the device is shipped with the ckdiv8 fuse pro- grammed. see ?system clock prescaler? on page 61 for more details. this clock may be selected as the system cl ock by programming the cksel fuses as shown in table 6-14 . if selected, it will operate with no external components. during reset, hardware loads the pre-programmed calibration value into the osccal register and thereby automati- cally calibrates the rc oscillator. the accuracy of this calibration is shown as factory calibration in table 6-139 on page 342 . by changing the osccal register from sw, see ?osccal ? oscillator calibration register? on page 62 , it is possible to get a higher calibration accuracy than by using the factory calibra- tion. the accuracy of this calibration is shown as user calibration in table 6-139 on page 342 . when this oscillator is used as the chip cloc k, the watchdog oscillato r will still be used for the watchdog timer and for the reset time-out. for more information on the pre-programmed calibration value, see the section ?calibration byte? on page 324 . notes: 1. the device is shipped with this option selected. 2. if 8mhz frequency exceeds the specification of the device (depends on v cc ), the ckdiv8 fuse can be programmed in order to divide the internal frequency by 8. when this oscillator is selected, start-up times are determined by the sut fuses as shown in table 6-15 on page 59 . note: 1. if the rstdisbl fuse is programmed , this start-up time will be increased to 14ck + 4.1ms to ensure programming mode can be entered. 2. the device is shipped wit h this option selected. table 6-14. internal calibrated rc o scillator operating modes frequency range (2) (mhz) cksel3..0 7.3 - 8.1 0010 (1) table 6-15. start-up times for the internal calib rated rc oscillator clock selection power conditions start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) sut1..0 bod enabled 6ck 14ck (1) 00 fast rising power 6ck 14ck + 4.1ms 01 slowly rising power 6ck 14ck + 65ms (2) 10 reserved 11 60 9159a?auto?09/10 atmel ata6614 [preliminary] 6.8.7 128khz internal oscillator the 128khz internal osc illator is a low power oscillator pr oviding a clock of 128khz. the fre- quency is nominal at 3v and 25c. this clock may be select as the system clock by programming the c ksel fuses to ?11? as shown in table 6-16 . note: 1. note that the 128khz oscillator is a very low power clock source, and is not designed for high accuracy. when this clock source is sele cted, start-up times are determined by the sut fuses as shown in table 6-17 . note: 1. if the rstdisbl fuse is programmed , this start-up time will be increased to 14ck + 4.1ms to ensure programming mode can be entered. 6.8.8 external clock to drive the device from an external clock source, xtal1 should be driven as shown in figure 6-14 on page 60 . to run the device on an external clock, the cksel fuses must be pro- grammed to ?0000? (see table 6-18 ). figure 6-14. external clock drive configuration when this clock source is sele cted, start-up times are determined by the sut fuses as shown in table 6-19 . table 6-16. 128khz internal osc illator operating modes nominal frequency (1) cksel3..0 128khz 0011 table 6-17. start-up times for the 128k hz internal oscillator power conditions start-up time from power-down and power-save additional delay from reset sut1..0 bod enabled 6 ck 14ck (1) 00 fast rising power 6 ck 14ck + 4ms 01 slowly rising power 6 ck 14ck + 64ms 10 reserved 11 table 6-18. crystal oscillator clock frequency frequency cksel3..0 0 - 20mhz 0000 nc external clock signal xtal2 xtal1 gnd 61 9159a?auto?09/10 atmel ata6614 [preliminary] when applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the mcu. a variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. if changes of more than 2% is required, ensure that the mcu is kept in reset during the changes. note that the system clock prescaler can be used to implement run-time changes of the inter- nal clock frequency while still ensu ring stable operation. refer to ?system clock prescaler? on page 61 for details. 6.8.9 clock output buffer the device can output the system clock on the clko pin. to enable the output, the ckout fuse has to be programmed. this mode is suitable when the chip clock is used to drive other circuits on the system. the clock also will be outp ut during reset, and the normal operation of i/o pin will be overridden when the fuse is progr ammed. any clock source , including the inter- nal rc oscillator, can be selected when the clock is output on clko. if the system clock prescaler is used, it is the divided system clock that is output. 6.8.10 timer/counter oscillator atmel ? atmega48pa/88pa/168pa/328p uses the sa me crystal oscillator for low-frequency oscillator and timer/c ounter oscillator. see ?low frequency crystal oscillator? on page 58 for details on the oscillator and crystal requirements. atmel atmega48pa/88pa/ 168pa/328p share the timer/count er oscillator pins (tosc1 and tosc2) with xtal1 and xtal2. when using the timer/counter oscillator, the system clock needs to be four times the o scillator frequency. due to th is and the pin sharing, the timer/counter oscillator can only be used when the calibrated internal rc oscillator is selected as system clock source. applying an external clock source to tosc1 can be done if extclk in the assr register is written to logic one. see ?asynchronous operation of timer/counter2? on page 181 for further description on selecting external clock as input instead of a 32.768 khz watch crystal. 6.8.11 system clock prescaler the atmel atmega48pa/88pa/168pa/328p has a system clock prescaler, and the system clock can be divided by setting the ?clkpr ? clock prescale register? on page 63 7. this fea- ture can be used to decrease the system clock frequency and the power consumption when the requirement for processing power is low. this can be used with all clock source options, and it will affect the clock frequency of the cpu and all synchronous peripherals. clk i/o , clk adc , clk cpu , and clk flash are divided by a factor as shown in table 6-141 on page 343 . table 6-19. start-up times for the external clock selection power conditions start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) sut1..0 bod enabled 6ck 14ck 00 fast rising power 6ck 14ck + 4.1ms 01 slowly rising power 6ck 14ck + 65ms 10 reserved 11 62 9159a?auto?09/10 atmel ata6614 [preliminary] when switching between prescaler settings, the system clock presca ler ensures that no glitches occurs in the clock system. it also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. the ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the cpu's clock frequency. hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to the other cannot be exactly predicted. from the time the clkps values ar e written, it takes between t1 + t2 and t1 + 2 * t2 before the new clock frequency is active. in this interval, 2 active clock edges are produced. here, t1 is the previous clock period, and t2 is the pe riod corresponding to the new prescaler setting. to avoid unintentional changes of clock frequency, a special write procedure must befollowed to change the clkps bits: 1. write the clock prescaler change enable (clkpce) bit to one and all other bitsin clkpr to zero. 2. within four cycles, write the desired va lue to clkps while writing a zero to clkpce. interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. 6.8.12 register description 6.8.12.1 osccal ? oscillator calibration register ? bits 7..0 ? cal7..0: oscillator calibration value the oscillator calibration register is used to trim the calibrated internal rc oscillator to remove process variations from the oscillator frequency. a pre-programmed calibration value is automatically written to this register during chip reset, giving the factory calibrated fre- quency as specified in table 6-139 on page 342 . the application software can write this register to change the oscillator frequency. the oscillator can be calibrated to frequencies as specified in table 6-139 on page 342 . calibration outside that range is not guaranteed. note that this oscillator is used to time eeprom and flash write accesses, and these write times will be affected accordingly. if the eepr om or flash are writt en, do not calibrate to more than 8.8mhz. otherwise, t he eeprom or flash write may fail. the cal7 bit determines the range of operation for the oscillato r. setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. the two fre- quency ranges are overlapping, in other words a setting of osccal = 0x7f gives a higher frequency than osccal = 0x80. the cal6..0 bits are used to tune the frequency within the selected range. a setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7f gives the highest frequency in the range. bit 76543210 (0x66) cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value device specific calibration value 63 9159a?auto?09/10 atmel ata6614 [preliminary] 6.8.12.2 clkpr ? clock prescale register ? bit 7 ? clkpce: clock prescaler change enable the clkpce bit must be written to logic one to enable change of the clkps bits. the clk- pce bit is only updated when the other bits in clkpr are simultaneously written to zero. clkpce is cleared by hardware four cycles after it is written or when cl kps bits are written. rewriting the clkpce bit within this time-out period does neither extend the time-out period, nor clear the clkpce bit. ? bits 3..0 ? clkps3..0: clock prescaler select bits 3 - 0 these bits define the division factor between the selected clock source and the internal sys- tem clock. these bits can be written run-time to vary the clock frequency to suit the application requirements. as the divider divides the master clock input to the mcu, the speed of all syn- chronous peripherals is reduced when a division factor is used. the division factors are given in table 6-20 on page 63 . the ckdiv8 fuse determines the initial value of the clkps bits . if ckdiv8 is unprogrammed, the clkps bits will be reset to ?0000?. if ckdiv8 is program med, clkps bits are reset to ?0011?, giving a division factor of 8 at start up. this feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present oper- ating conditions. note that an y value can be written to th e clkps bits regardless of the ckdiv8 fuse setting. the application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. the device is shipped with the ckdiv8 fuse programmed. bit 7 6 5 4 3 2 1 0 (0x61) clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 clkpr read/write r/w r r r r/w r/w r/w r/w initial value 0 0 0 0 see bit description table 6-20. clock prescaler select clkps3 clkps2 clkps1 clkps0 clock division factor 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved 64 9159a?auto?09/10 atmel ata6614 [preliminary] 6.9 power management and sleep modes sleep modes enable the application to shut down unused modules in the mcu, thereby saving power. the avr provides various sleep modes allowing the user to tailor the power consump- tion to the application?s requirements. when enabled, the brown-out detector (bod) actively monitors the power supply voltage dur- ing the sleep periods. to further save power, it is possible to disable the bod in some sleep modes. see ?bod disable? on page 65 for more details. 6.9.1 sleep modes figure 6-11 on page 52 presents the different clock systems in the atmega48pa/88pa/168pa/328p, and their distribution. the figure is helpful in selecting an appropriate sleep mode. table 6-21 shows the different sleep modes, their wake up sources bod disable ability. notes: 1. only recommended with external crystal or resonator selected as clock source. 2. if timer/counter2 is running in asynchronous mode. 3. for int1 and int0, only level interrupt. to enter any of the six sleep modes, the se bi t in smcr must be written to logic one and a sleep instruction must be executed. the sm2, sm1, and sm0 bits in the smcr register select which sleep mode (idle, adc noise re duction, power-down, power-save, standby, or extended standby) will be activated by the sleep instruction. see table 6-22 on page 69 for a summary. if an enabled interrupt occurs while the mcu is in a sleep mo de, the mcu wakes up. the mcu is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction follow ing sleep. the contents of the register file and sram are unaltered when the device wakes up from sleep. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. table 6-21. active clock domains and wake-up sour ces in the different sleep modes. active clock domains osc illators wake-up sources software bod disable sleep mode clk cpu clk flash clk io clk adc clk asy main clock source enabled timer oscillator enabled int1, int0 and pin change twi address match timer2 spm/eeprom ready adc wdt other i/o idle xxx x x (2) x x x x xxx adc noise reduction xx x x (2) x (3) xx (2) xxx power-down x (3) xxx power-save x x (2) x (3) xx x x standby (1) xx (3) xxx extended standby x (2) xx (2) x (3) xx x x 65 9159a?auto?09/10 atmel ata6614 [preliminary] 6.9.2 bod disable when the brown-out detector (bod) is enabled by bodlevel fuses, table 6-126 on page 321 , the bod is actively monitoring the power supply voltage during a sleep period. to save power, it is possible to disable the bod by software for some of the sleep modes, see table 6-21 on page 64 . the sleep mode power consumption will then be at the same level as when bod is globally disabled by fuses. if bod is disabled in software, the bod function is turned off immediately after entering the sleep mode. upon wake-up from sleep, bod is automati- cally enabled again. this ensures safe operation in case the v cc level has dropped during the sleep period. when the bod has been disabl ed, the wake-up time from sl eep mode will be approximately 60 s to ensure that the bod is working correctly before the mcu continues executing code. bod disable is controlled by bit 6, bods (bod sleep) in the control register mcucr, see ?mcucr ? mcu control register? on page 69 . writing this bit to one turns off the bod in rel- evant sleep modes, while a zero in this bit keeps bod active. default setting keeps bod active, i.e. bods set to zero. writing to the bods bit is controll ed by a timed sequence and an enable bit, see ?mcucr ? mcu control register? on page 69 . 6.9.3 idle mode when the sm2..0 bits are written to 000, the sleep instruction makes the mcu enter idle mode, stopping the cpu but allowing the spi, usart, analog comparator, adc, 2-wire serial interface, timer/counters, watchdog, and the interrupt system to continue operating. this sleep mode basically halts clk cpu and clk flash , while allowing the other clocks to run. idle mode enables the mcu to wake up from external triggered interrupts as well as internal ones like the timer overflow and usart transmit complete interrupts. if wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the acd bit in the analog comparator control and status register ? acsr. this will reduce power consumption in idle mode. if the adc is enabled, a conversion starts automati- cally when this mode is entered. 6.9.4 adc noise reduction mode when the sm2..0 bits are written to 001, the sleep instruction makes the mcu enter adc noise reduction mode, stopping the cpu but allo wing the adc, the external interrupts, the 2-wire serial interface address watch, timer/counter2 (1) , and the watchdog to continue oper- ating (if enabled). this sleep mode basically halts clk i/o , clk cpu , and clk flash , while allowing the other clocks to run. this improves the noise environment for the adc, enabling higher resolution measurements. if the adc is enabled, a conversion starts automa tically when this mode is entered. apart from the adc conversion complete inte rrupt, only an external reset, a watchdog system reset, a watchdog interrupt, a brown-out reset, a 2-wire serial interface address match, a timer/counter2 interrupt, an spm /eeprom ready interrupt, an ex ternal level interrupt on int0 or int1 or a pin change interrupt can wake up the mcu from adc noise reduction mode. note: 1. timer/counter2 will only keep running in asynchronous mode, see ?8-bit timer/counter2 with pwm and asynchronous operation? on page 170 for details. 66 9159a?auto?09/10 atmel ata6614 [preliminary] 6.9.5 power-down mode when the sm2..0 bits are written to 010, the sleep instruction makes the mcu enter power-down mode. in this mode, the external os cillator is stopped, while the external inter- rupts, the 2-wire serial interface address watch, and the watchdog continue operating (if enabled). only an external reset, a watchd og system reset, a watchdog interrupt, a brown-out reset, a 2-wire serial interface address match, an external level interrupt on int0 or int1, or a pin change interrupt can wake up the mcu. this sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only. note that if a level triggered interrupt is used for wake-up from power-down mode, the changed level must be held for some time to wake up the mcu. refer to ?external interrupts? on page 95 for details. when waking up from power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. this allows the clock to restart and become stable after having been stopped. the wake-up period is defined by the same cksel fuses that define the reset time-out period, as described in ?clock sources? on page 53 . 6.9.6 power-save mode when the sm2..0 bits are written to 011, the sleep instruction makes the mcu enter power-save mode. this mode is identica l to power-down, wi th one exception: if timer/counter2 is enabled, it will keep runni ng during sleep. the device can wake up from either timer overflow or output compare event from timer/counter2 if the corresponding timer/counter2 interrupt enable bits are set in timsk2, and the global interrupt enable bit in sreg is set. if timer/counter2 is not running, power-down mode is recommended instead of power-save mode. the timer/counter2 can be clocked both synchronously and asynchronously in power-save mode. if timer/counter2 is not using the asynch ronous clock, the timer/counter oscillator is stopped during sleep. if timer/counter2 is not using the synchronous clock, the clock source is stopped during sleep. note that even if the synchronous clock is running in power-save, this clock is only available for timer/counter2. 6.9.7 standby mode when the sm2..0 bits are 110 and an external crystal/resonator clock option is selected, the sleep instruction makes the mcu enter standby mode. this mode is identical to power-down with the exception that the oscillator is kept running. from standby mode, the device wakes up in six clock cycles. 6.9.8 extended standby mode when the sm2..0 bits are 111 and an external crystal/resonator clock option is selected, the sleep instruction makes the mcu enter extended standb y mode. this mode is identical to power-save with the exception that the oscillator is kept running. from extended standby mode, the device wakes up in six clock cycles. 67 9159a?auto?09/10 atmel ata6614 [preliminary] 6.9.9 power reduction register the power reduction register (prr), see ?prr ? power reduction register? on page 70 , provides a method to stop the clock to individual peripherals to reduce power consumption. the current state of the peripheral is frozen and the i/o registers can not be read or written. resources used by the periphe ral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. waking up a module, which is done by clearing the bit in prr, puts the module in the same state as before shutdown. module shutdown can be used in idle mode and active mode to significantly reduce the overall power consumption. in all other sleep modes, the clock is already stopped. 6.9.10 minimizing power consumption there are several possibilities to consider w hen trying to minimize the power consumption in an avr controlled system. in general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as fe w as possible of the device?s functions are operating. all functions not needed should be disabled. in particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 6.9.10.1 analog to digital converter if enabled, the adc will be enabled in all sleep modes. to save power, the adc should be dis- abled before entering any sleep mode. when the adc is turned off and on again, the next conversion will be an extend ed conversion. refer to ?analog-to-digital converter? on page 275 for details on adc operation. 6.9.10.2 analog comparator when entering idle mode, the analog comparator should be disabled if not used. when enter- ing adc noise reduction mode, the analog comparator should be disabled. in other sleep modes, the analog comparator is automatically disabled. however, if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be dis- abled in all sleep modes. otherwise, the internal voltage re ference will be enabled, independent of sleep mode. refer to ?analog comparator? on page 271 for details on how to configure the analog comparator. 6.9.10.3 brown-out detector if the brown-out detector is not needed by the application, this module should be turned off. if the brown-out detector is enabled by the bo dlevel fuses, it will be enabled in all sleep modes, and hence, always cons ume power. in the de eper sleep modes, th is will contribute significantly to the total current consumption. refer to ?brown-out detection? on page 73 for details on how to configure the brown-out detector. 6.9.10.4 internal voltage reference the internal voltage re ference will be enabled wh en needed by the brow n-out detection, the analog comparator or the adc. if these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. when turned on again, the user must allow the reference to start up before the output is used. if the reference is kept on in sleep mode, the output can be used immediately. refer to ?inter- nal voltage reference? on page 74 for details on the start-up time. 68 9159a?auto?09/10 atmel ata6614 [preliminary] 6.9.10.5 watchdog timer if the watchdog timer is not needed in the application, the module should be turned off. if the watchdog timer is enabled, it will be enabled in all sleep modes and hence always consume power. in the deeper sleep modes, this will contribute significantly to the total current con- sumption. refer to ?watchdog timer? on page 75 for details on how to configure the watchdog timer. 6.9.10.6 port pins when entering a sleep mode, all port pins should be configured to use minimum power. the most important is then to ensure that no pins drive resistive loads. in sleep modes where both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buffers of the device will be disabled. this ensures that no power is consumed by the input logic when not needed. in some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. refer to the section ?digital input enable and sleep modes? on page 104 for details on which pins are enabled. if the input buffer is enabled and the input signal is left floating or have an analog signal level close to v cc /2, the input buffer will use excessive power. for analog input pins, the digital input buffer should be disabled at all times. an analog signal level close to v cc /2 on an input pin can caus e significant current even in active mode. digital input buffers can be disabled by writing to the digital input disable registers (didr1 and didr0). refer to ?didr1 ? digital input disable register 1? on page 274 and ?didr0 ? digital input disable register 0? on page 291 for details. 6.9.10.7 on-chip debug system if the on-chip debug system is enabled by the dwen fuse and the chip enters sleep mode, the main clock source is enabled and hence always consumes power. in the deeper sleep modes, this will contribute significantly to the total cu rrent consumption. 69 9159a?auto?09/10 atmel ata6614 [preliminary] 6.9.11 register description 6.9.11.1 smcr ? sleep mode control register the sleep mode control register contains control bits for power management. ? bits 7..4 res: reserved bits these bits are unused in the atmega48pa/88p a/168pa/328p, and will always be read as zero. ? bits 3..1 ? sm2..0: sleep mode select bits 2, 1, and 0 these bits select between the five available sleep modes as shown in table 6-22 . note: 1. standby mode is only recommended for use with external crystals or resonators. ? bit 0 ? se: sleep enable the se bit must be written to logic one to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid the mcu entering the slee p mode unless it is the pro- grammer?s purpose, it is recommended to write the sleep enable (se) bit to one just before the execution of the sleep inst ruction and to clear it im mediately after waking up. 6.9.11.2 mcucr ? mcu control register ? bit 6 ? bods: bod sleep the bods bit must be written to logic one in order to turn off bod during sleep, see table 6-21 on page 64 . writing to the bods bit is controlled by a timed sequence and an enable bit, bodse in mcucr. to disable bod in rele vant sleep modes, both bods and bodse must first be set to one. then, to set the bods bit, bods must be set to one and bodse must be set to zero within four clock cycles. bit 76543210 0x33 (0x53) ? ? ? ? sm2 sm1 sm0 se smcr read/write r r r r r/w r/w r/w r/w initial value00000000 table 6-22. sleep mode select sm2 sm1 sm0 sleep mode 000idle 0 0 1 adc noise reduction 0 1 0 power-down 011power-save 1 0 0 reserved 1 0 1 reserved 1 1 0 standby (1) 1 1 1 external standby (1) bit 7 6 5 4 3 2 1 0 0x35 (0x55) ? bods bodse pud ? ? ivsel ivce mcucr read/write r r r r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 70 9159a?auto?09/10 atmel ata6614 [preliminary] the bods bit is active three clock cycles after it is set. a sleep instruction must be executed while bods is active in order to turn off t he bod for the actual sleep mode. the bods bit is automatically cleared after three clock cycles. ? bit 5 ? bodse: bod sleep enable bodse enables setting of bods control bit, as explained in bods bit description. bod dis- able is controlled by a timed sequence. 6.9.11.3 prr ? power reduction register ? bit 7 - prtwi: power reduction twi writing a logic one to this bit shuts down t he twi by stopping the clock to the module. when waking up the twi again, the twi should be re initialized to ensure proper operation. ? bit 6 - prtim2: power reduction timer/counter2 writing a logic one to this bit shuts down the timer/counter2 module in synchronous mode (as2 is 0). when the timer/counter2 is enabled, operation will continue like before the shutdown. ? bit 5 - prtim0: power reduction timer/counter0 writing a logic one to this bit shuts down the timer/counter0 module. when the timer/counter0 is enabl ed, operation will continue like before the shutdown. ? bit 4 - res: reserved bit this bit is reserved in atmega48pa/88 pa/168pa/328p and will a lways read as zero. ? bit 3 - prtim1: power reduction timer/counter1 writing a logic one to this bit shuts down the timer/counter1 module. when the timer/counter1 is enabl ed, operation will continue like before the shutdown. ? bit 2 - prspi: power reduction serial peripheral interface if using debugwire on-chip debug system, this bit should not be written to one. writing a logic one to this bit sh uts down the serial peripheral interface by stopping the clock to the module. when waking up the spi again, the spi should be re initialized to ensure proper operation. ? bit 1 - prusart0: power reduction usart0 writing a logic one to this bit shuts down the usart by stopping the clock to the module. when waking up the usart again, the usart should be re initialized to ensure proper operation. ? bit 0 - pradc: power reduction adc writing a logic one to this bit shuts down t he adc. the adc must be disabled before shut down. the analog comparator cannot use the adc input mux when the adc is shut down. bit 765 432 1 0 (0x64) prtwi prtim2 prtim0 ? prtim1 prspi prusart0 pradc prr read/write r/w r/w r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 71 9159a?auto?09/10 atmel ata6614 [preliminary] 6.10 system control and reset 6.10.1 resetting the atmel avr during reset, all i/o registers are set to their initial values, and the program starts execution from the reset vector. for the atmel ? atmega168pa, the instruction placed at the reset vector must be a jmp ? absolute jump ? instruction to the reset handling routine. for the atmel atmega48pa and atmega88pa, the instruction placed at the reset vector must be an rjmp ? relative jump ? instruction to the reset handling routine. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the application sec- tion while the interrupt vectors are in the boot section or vice versa (atmel atmega88pa/168pa only). the circuit diagram in figure 6-15 on page 72 shows the reset logic. table 6-141 on page 343 defines the electrical parame ters of the reset circuitry. the i/o ports of the atmel avr ? are immediately reset to their initial state when a reset source goes active. this does not requir e any clock source to be running. after all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. this allows the power to reach a stable level before normal operation starts. the time-out period of the delay counter is defined by the us er through the sut and cksel fuses. the different selections for the delay period are presented in ?clock sources? on page 53 . 6.10.2 reset sources the atmel atmega48pa/88pa/168pa/328p has four sources of reset: ? power-on reset. the mcu is reset when the supply voltage is below the power-on reset threshold (v pot ). ? external reset. the mcu is reset when a low level is present on the reset pin for longer than the minimum pulse length. ? watchdog system reset. the mcu is reset when the watchdog timer period expires and the watchdog system reset mode is enabled. ? brown-out reset. the mcu is re set when the supply voltage v cc is below the brown-out reset threshold (v bot ) and the brown-out detector is enabled. 72 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-15. reset logic 6.10.3 power-on reset a power-on reset (por) pulse is generated by an on-chip detection circuit. the detection level is defined in ?system and reset characteristics? on page 343 . the por is activated whenever v cc is below the detection leve l. the por circuit can be used to trigger the start-up reset, as well as to detect a failure in supply voltage. a power-on reset (por) circuit ensures that the device is reset from power-on. reaching the power-on reset threshold voltage invokes the delay counter, which determines how long the device is kept in reset after v cc rise. the reset signal is activated again, without any delay, when v cc decreases below t he detection level. figure 6-16. mcu start-up, reset tied to v cc mcu status register (mcusr) brown-out reset circuit bodlevel [2..0] delay counters cksel[3:0] ck timeout wdrf borf extrf porf data b u s clock generator spike filter pull-up resistor watchdog oscillator sut[1:0] power-on reset circuit rstdisbl v reset time-out internal reset t tout v pot v rst cc 73 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-17. mcu start-up, reset extended externally 6.10.4 external reset an external reset is generate d by a low level on the reset pin. reset pulses longer than the minimum pulse width (see ?system and reset characteristics? on page 343 ) will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage ? v rst ? on its positive edge, the delay counter starts the mcu after the time-out period ? t tout ? has expired. the external reset can be disabled by the rstdisbl fuse, see table 6-126 on page 321 . figure 6-18. external reset during operation 6.10.5 brown-out detection atmel ? atmega48pa/88pa/168pa/328p has an on-chi p brown-out detection (bod) circuit for monitoring the v cc level during operation by comparing it to a fixed trigger level. the trigger level for the bod can be selected by the bodl evel fuses. the trigger level has a hysteresis to ensure spike free brown-out detection. the hysteresis on the detection level should be interpreted as v bot+ = v bot + v hyst /2 and v bot- = v bot - v hyst /2.when the bod is enabled, and v cc decreases to a value below the trigger level (v bot- in figure 6-19 on page 74 ), the brown-out reset is immediately activated. when v cc increases above the trigger level (v bot+ in figure 6-19 on page 74 ), the delay counter starts the mcu after the time-out period t tout has expired. the bod circuit will only detect a drop in v cc if the voltage stays belo w the trigger level for lon- ger than t bod given in ?system and reset characteristics? on page 343 . reset time-out internal reset t tout v pot v rst v cc cc 74 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-19. brown-out reset during operation 6.10.6 watchdog system reset when the watchdog times out, it will generate a short reset pulse of one ck cycle duration. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . refer to page 75 for details on operation of the watchdog timer. figure 6-20. watchdog system reset during operation 6.10.7 internal voltage reference atmel ? atmega48pa/88pa/168pa/328p features an internal bandgap reference. this refer- ence is used for brown-out detection, and it can be used as an input to the analog comparator or the adc. 6.10.7.1 voltage reference enable signals and start-up time the voltage reference has a start-up time that may influence the way it should be used. the start-up time is given in ?system and reset characteristics? on page 343 . to save power, the reference is not always turned on. the reference is on during the following situations: 1. when the bod is enabled (by prog ramming the bodlevel [2:0] fuses). 2. when the bandgap reference is connected to the analog comparator (by setting the acbg bit in acsr). 3. when the adc is enabled. v cc reset time-out internal reset v bot- v bot+ t tout ck cc 75 9159a?auto?09/10 atmel ata6614 [preliminary] thus, when the bod is not enabled, after setting the acbg bit or enabling the adc, the user must always allow the reference to start up before the output from the analog comparator or adc is used. to reduce power consumption in power-down mode, the user can avoid the three conditions above to ensure that the refe rence is turned off before entering power-down mode. 6.10.8 watchdog timer 6.10.8.1 features ? clocked from separat e on-chip oscillator ? 3 operating modes ?interrupt ? system reset ? interrupt and system reset ? selectable time-out period from 16ms to 8s ? possible hardware fuse watchdog always on (wdton) for fail-safe mode 6.10.8.2 overview atmel ? atmega48pa/88pa/168pa/328p has an enhanced watchdog timer (wdt). the wdt is a timer counting cycles of a separate on-chip 128khz oscillator. the wdt gives an interrupt or a system reset when the counter reaches a given time-out value. in normal opera- tion mode, it is required that the system uses the wdr - watchdog timer reset - instruction to restart the counter before the time-out value is reached. if the system doesn't restart the coun- ter, an interrupt or s ystem reset will be issued. figure 6-21. watchdog timer in interrupt mode, the wdt gives an interrupt when the timer expires. this interrupt can be used to wake the device from sleep-modes, and also as a general system timer. one example is to limit the maximum time allowed for certain operations, giving an interrupt when the opera- tion has run longer than expected. in system reset mode, the wdt gives a reset when the timer expires. this is typically used to prevent system hang-up in case of runaway code. the third mode, interrupt and system reset mode, combines the other two modes by first giving an interrupt and then switch to system reset mode. this mode will for instance allow a safe shutdown by saving critical parameters before a system reset. 128khz oscillator osc/2k osc/4k osc/8k osc/16k osc/32k osc/64k osc/128k osc/256k osc/512k osc/1024k wdp0 wdp1 wdp2 wdp3 watchdog reset wde wdif wdie mcu reset interrupt 76 9159a?auto?09/10 atmel ata6614 [preliminary] the watchdog always on (wdton) fuse, if pr ogrammed, will force the watchdog timer to system reset mode. with the fuse programmed the system reset mode bit (wde) and inter- rupt mode bit (wdie) are locked to 1 and 0 respectively. to further ensure program security, alterations to the watchdog set-up must follo w timed sequences. the sequence for clearing wde and changing time-out configuration is as follows: 1. in the same operation, write a logic one to the watchdog change enable bit (wdce) and wde. a logic one must be written to wde regardless of the previous value of the wde bit. 2. within the next four clock cycles, write the wde and watchdog prescaler bits (wdp) as desired, but with the wdce bit cleared. this must be done in one operation. the following code example shows one assemb ly and one c function for turning off the watchdog timer. the example assumes that interrupts are controlled (e.g. by disabling inter- rupts globally) so that no interrupts will o ccur during the executio n of these functions. 77 9159a?auto?09/10 atmel ata6614 [preliminary] note: 1. see ?about code examples? on page 33. note: if the watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the devic e will be reset and the watchdog timer will stay enabled. if the code is not set up to handle the watchdog, this might lead to an eternal loop of time-out resets. to avoid this situation, the application software should always clear the watchdog system reset flag (wdrf) and the wde control bit in the initialisation routine, even if the watchdog is not in use. assembly code example (1) wdt_off: ; turn off global interrupt cli ; reset watchdog timer wdr ; clear wdrf in mcusr in r16, mcusr andi r16, (0xff & (0< 80 9159a?auto?09/10 atmel ata6614 [preliminary] executing the corresponding inte rrupt vector will clear wdie a nd wdif automatically by hard- ware (the watchdog goes to system reset mode). this is useful for keeping the watchdog timer security while using the interrupt. to stay in interrupt and system reset mode, wdie must be set after each interrupt. this should however not be done within the interrupt service routine itself, as this might compromise th e safety-function of the watchdog system reset mode. if the interrupt is not executed before the nex t time-out, a system reset will be applied. note: 1. wdton fuse set to ?0? means programmed and ?1? means unprogrammed. ? bit 4 - wdce: watchdog change enable this bit is used in timed sequences for changing wde and prescaler bits. to clear the wde bit, and/or change the prescaler bits, wdce must be set. once written to one, ha rdware will clear wdce after four clock cycles. ? bit 3 - wde: watchdog system reset enable wde is overridden by wdrf in mcusr. this means that wde is always set when wdrf is set. to clear wde, wdrf must be cleared first. this feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure. ? bit 5, 2..0 - wdp3..0: watchdog timer prescaler 3, 2, 1 and 0 the wdp3..0 bits determine the watchdog timer prescaling when the watchdog timer is run- ning. the different prescaling values and t heir corresponding time-out periods are shown in table 6-24 on page 80 . table 6-23. watchdog timer configuration wdton (1) wde wdie mode action on time-out 1 0 0 stopped none 1 0 1 interrupt mode interrupt 1 1 0 system reset mode reset 111 interrupt and system reset mode interrupt, then go to system reset mode 0 x x system reset mode reset table 6-24. watchdog timer prescale select wdp3 wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 5.0v 0 0 0 0 2k (2048) cycles 16ms 0 0 0 1 4k (4096) cycles 32ms 0 0 1 0 8k (8192) cycles 64ms 0 0 1 1 16k (16384) cycles 0.125s 0 1 0 0 32k (32768) cycles 0.25s 0 1 0 1 64k (65536) cycles 0.5s 0 1 1 0 128k (131072) cycles 1.0s 0 1 1 1 256k (262144) cycles 2.0s 1 0 0 0 512k (524288) cycles 4.0s 81 9159a?auto?09/10 atmel ata6614 [preliminary] 6.11 interrupts this section describes the specifics of the interrupt handling as performed in atmel ? atmega48pa/88pa/168pa/328p. for a general explanation of the avr ? interrupt handling, refer to ?reset and interrupt handling? on page 40 . the interrupt vectors in atmel atmega48pa, atmega88pa, atmega168pa and atmega328p are generally the same, with the following differences: ? each interrupt vector occupies two instruction words in atmel atmega168pa and atmega328p, and one instruction word in atmel atmega48pa and atmega88pa. ? atmel atmega48pa does not have a separate boot loader section. in atmel atmega88pa, atmega168pa and atmega328p, the reset vector is affected by the bootrst fuse, and the interrupt vector star t address is affected by the ivsel bit in mcucr. 1 0 0 1 1024k (1048576) cycles 8.0s 1010 reserved 1011 1100 1101 1110 1111 table 6-24. watchdog timer prescale select (continued) wdp3 wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 5.0v 82 9159a?auto?09/10 atmel ata6614 [preliminary] 6.11.1 interrupt vectors in atmega48pa table 6-25. reset and interrupt vectors in atmega48pa vector no. program address source interrupt definition 1 0x000 reset external pin, power-on reset, brown-out reset and watchdog system reset 2 0x001 int0 external interrupt request 0 3 0x002 int1 external interrupt request 1 4 0x003 pcint0 pin change interrupt request 0 5 0x004 pcint1 pin change interrupt request 1 6 0x005 pcint2 pin change interrupt request 2 7 0x006 wdt watchdog time-out interrupt 8 0x007 timer2 compa timer/counter2 compare match a 9 0x008 timer2 compb timer/counter2 compare match b 10 0x009 timer2 ovf timer/counter2 overflow 11 0x00a timer1 capt timer/counter1 capture event 12 0x00b timer1 compa timer/counter1 compare match a 13 0x00c timer1 compb timer/coutner1 compare match b 14 0x00d timer1 ovf timer/counter1 overflow 15 0x00e timer0 compa timer/counter0 compare match a 16 0x00f timer0 compb timer/counter0 compare match b 17 0x010 timer0 ovf timer/counter0 overflow 18 0x011 spi, stc spi seri al transfer complete 19 0x012 usart, rx usart rx complete 20 0x013 usart, udre usart, data register empty 21 0x014 usart, tx usart, tx complete 22 0x015 adc adc conversion complete 23 0x016 ee ready eeprom ready 24 0x017 analog comp analog comparator 25 0x018 twi 2-wire serial interface 26 0x019 spm ready store program memory ready 83 9159a?auto?09/10 atmel ata6614 [preliminary] the most typical and general program setup for the reset and interrupt vector addresses in atmel ? atmega48pa is: address labels code comments 0x000 rjmp reset ; reset handler 0x001 rjmp ext_int0 ; irq0 handler 0x002 rjmp ext_int1 ; irq1 handler 0x003 rjmp pcint0 ; pcint0 handler 0x004 rjmp pcint1 ; pcint1 handler 0x005 rjmp pcint2 ; pcint2 handler 0x006 rjmp wdt ; watchdog timer handler 0x007 rjmp tim2_compa ; timer2 compare a handler 0x008 rjmp tim2_compb ; timer2 compare b handler 0x009 rjmp tim2_ovf ; timer2 overflow handler 0x00a rjmp tim1_capt ; timer1 capture handler 0x00b rjmp tim1_compa ; timer1 compare a handler 0x00c rjmp tim1_compb ; timer1 compare b handler 0x00d rjmp tim1_ovf ; timer1 overflow handler 0x00e rjmp tim0_compa ; timer0 compare a handler 0x00f rjmp tim0_compb ; timer0 compare b handler 0x010 rjmp tim0_ovf ; timer0 overflow handler 0x011 rjmp spi_stc ; spi transfer complete handler 0x012 rjmp usart_rxc ; usart, rx complete handler 0x013 rjmp usart_udre ; usart, udr empty handler 0x014 rjmp usart_txc ; usart, tx complete handler 0x015 rjmp adc ; adc conversion complete handler 0x016 rjmp ee_rdy ; eeprom ready handler 0x017 rjmp ana_comp ; analog comparator handler 0x018 rjmp twi ; 2-wire serial interface handler 0x019 rjmp spm_rdy ; store program memory ready handler ; 0x01areset: ldi r16, high(ramend); main program start 0x01b out sph,r16 ; set stack pointer to top of ram 0x01c ldi r16, low(ramend) 0x01d out spl,r16 0x01e sei ; enable interrupts 0x01f 84 9159a?auto?09/10 atmel ata6614 [preliminary] 6.11.2 interrupt vectors in atmel atmega88pa notes: 1. when the bootrst fuse is pr ogrammed, the device will jump to t he boot loader address at reset, see ?boot loader sup- port ? read-while-write self-pr ogramming, atmel atmega88pa, at mega168pa and atmega328p? on page 302 . 2. when the ivsel bit in mcucr is set, interrupt vectors will be moved to the start of the boot flash section. the address of each interrupt vector will then be the address in this table added to the start address of the boot flash section. table 6-27 on page 85 shows reset and interrupt vectors placement for the various combina- tions of bootrst and ivsel settings. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. table 6-26. reset and interrupt vectors in atmel ? atmega88pa vector no. program address (2) source interrup t definition 1 0x000 (1) reset external pin, power-on reset, brown-out reset and watchdog system reset 2 0x001 int0 external interrupt request 0 3 0x002 int1 external interrupt request 1 4 0x003 pcint0 pin change interrupt request 0 5 0x004 pcint1 pin change interrupt request 1 6 0x005 pcint2 pin change interrupt request 2 7 0x006 wdt watchdog time-out interrupt 8 0x007 timer2 compa timer /counter2 compare match a 9 0x008 timer2 compb timer /counter2 compare match b 10 0x009 timer2 ovf timer/counter2 overflow 11 0x00a timer1 capt timer/counter1 capture event 12 0x00b timer1 compa timer/counter1 compare match a 13 0x00c timer1 compb timer/coutner1 compare match b 14 0x00d timer1 ovf timer/counter1 overflow 15 0x00e timer0 compa timer/counter0 compare match a 16 0x00f timer0 compb timer /counter0 compare match b 17 0x010 timer0 ovf timer/counter0 overflow 18 0x011 spi, stc spi serial transfer complete 19 0x012 usart, rx usart rx complete 20 0x013 usart, udre usart, data register empty 21 0x014 usart, tx usart, tx complete 22 0x015 adc adc conversion complete 23 0x016 ee ready eeprom ready 24 0x017 analog comp analog comparator 25 0x018 twi 2-wire serial interface 26 0x019 spm ready store program memory ready 85 9159a?auto?09/10 atmel ata6614 [preliminary] note: 1. the boot reset address is shown in table 6-111 on page 314 . for the bootrst fuse ?1? means unprogrammed while ?0? means programmed. the most typical and general program setup for the reset and interrupt vector addresses in atmel atmega88pa is: address labels code comments 0x000 rjmp reset ; reset handler 0x001 rjmp ext_int0 ; irq0 handler 0x002 rjmp ext_int1 ; irq1 handler 0x003 rjmp pcint0 ; pcint0 handler 0x004 rjmp pcint1 ; pcint1 handler 0x005 rjmp pcint2 ; pcint2 handler 0x006 rjmp wdt ; watchdog timer handler 0x007 rjmp tim2_compa ; timer2 compare a handler 0x008 rjmp tim2_compb ; timer2 compare b handler 0x009 rjmp tim2_ovf ; timer2 overflow handler 0x00a rjmp tim1_capt ; timer1 capture handler 0x00b rjmp tim1_compa ; timer1 compare a handler 0x00c rjmp tim1_compb ; timer1 compare b handler 0x00d rjmp tim1_ovf ; timer1 overflow handler 0x00e rjmp tim0_compa ; timer0 compare a handler 0x00f rjmp tim0_compb ; timer0 compare b handler 0x010 rjmp tim0_ovf ; timer0 overflow handler 0x011 rjmp spi_stc ; spi transfer complete handler 0x012 rjmp usart_rxc ; usart, rx complete handler 0x013 rjmp usart_udre ; usart, udr empty handler 0x014 rjmp usart_txc ; usart, tx complete handler 0x015 rjmp adc ; adc conversion complete handler 0x016 rjmp ee_rdy ; eeprom ready handler 0x017 rjmp ana_comp ; analog comparator handler 0x018 rjmp twi ; 2-wire serial interface handler 0x019 rjmp spm_rdy ; store program memory ready handler ; 0x01areset: ldi r16, high(ramend); main program start 0x01b out sph,r16 ; set stack pointer to top of ram 0x01c ldi r16, low(ramend) 0x01d out spl,r16 0x01e sei ; enable interrupts 0x01f 86 9159a?auto?09/10 atmel ata6614 [preliminary] when the bootrst fuse is unprogrammed, the b oot section size set to 2k bytes and the ivsel bit in the mcucr register is set before any interrupts are enab led, the most typical and general program setup for the reset and interrupt vector addresses in atmel ? atmega88pa is: address labels code comments 0x000 reset: ldi r16,high(ramend); main program start 0x001 out sph,r16 ; set stack pointer to top of ram 0x002 ldi r16,low(ramend) 0x003 out spl,r16 0x004 sei ; enable interrupts 0x005 87 9159a?auto?09/10 atmel ata6614 [preliminary] ; 0xc1a reset: ldi r16,high(ramend); main program start 0xc1b out sph,r16 ; set stack pointer to top of ram 0xc1c ldi r16,low(ramend) 0xc1d out spl,r16 0xc1e sei ; enable interrupts 0xc1f 88 9159a?auto?09/10 atmel ata6614 [preliminary] table 6-29 on page 88 shows reset and interrupt vectors placement for the various combina- tions of bootrst and ivsel settings. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the application section while the interrupt vectors are in the boot sect ion or vice versa. note: 1. the boot reset address is shown in table 6-111 on page 314 . for the bootrst fuse ?1? means unprogrammed while ?0? means programmed. the most typical and general program setup for the reset and interrupt vector addresses in atmel ? atmega168pa is: address labels code comments 0x0000 jmp reset ; reset handler 0x0002 jmp ext_int0 ; irq0 handler 0x0004 jmp ext_int1 ; irq1 handler 0x0006 jmp pcint0 ; pcint0 handler 0x0008 jmp pcint1 ; pcint1 handler 0x000a jmp pcint2 ; pcint2 handler 0x000c jmp wdt ; watchdog timer handler 0x000e jmp tim2_compa ; timer2 compare a handler 0x0010 jmp tim2_compb ; timer2 compare b handler 0x0012 jmp tim2_ovf ; timer2 overflow handler 0x0014 jmp tim1_capt ; timer1 capture handler 0x0016 jmp tim1_compa ; timer1 compare a handler 0x0018 jmp tim1_compb ; timer1 compare b handler 0x001a jmp tim1_ovf ; timer1 overflow handler 0x001c jmp tim0_compa ; timer0 compare a handler 0x001e jmp tim0_compb ; timer0 compare b handler 0x0020 jmp tim0_ovf ; timer0 overflow handler 0x0022 jmp spi_stc ; spi transfer complete handler 0x0024 jmp usart_rxc ; usart, rx complete handler 0x0026 jmp usart_udre ; usart, udr empty handler 0x0028 jmp usart_txc ; usart, tx complete handler 0x002a jmp adc ; adc conversion complete handler 0x002c jmp ee_rdy ; eeprom ready handler 0x002e jmp ana_comp ; analog comparator handler 0x0030 jmp twi ; 2-wire serial interface handler 0x0032 jmp spm_rdy ; store program memory ready handler ; table 6-29. reset and interrupt vectors placement in atmel ? atmega168pa (1) bootrst ivsel reset address inter rupt vectors start address 1 0 0x000 0x002 1 1 0x000 boot reset address + 0x0002 0 0 boot reset address 0x002 0 1 boot reset address boot reset address + 0x0002 89 9159a?auto?09/10 atmel ata6614 [preliminary] 0x0033reset: ldi r16, high(ramend); main program start 0x0034 out sph,r16 ; set stack pointer to top of ram 0x0035 ldi r16, low(ramend) 0x0036 out spl,r16 0x0037 sei ; enable interrupts 0x0038 90 9159a?auto?09/10 atmel ata6614 [preliminary] address labels code comments ; .org 0x1c00 0x1c00 jmp reset ; reset handler 0x1c02 jmp ext_int0 ; irq0 handler 0x1c04 jmp ext_int1 ; irq1 handler ... ... ... ; 0x1c32 jmp spm_rdy ; store program memory ready handler ; 0x1c33 reset: ldi r16,high(ramend); main program start 0x1c34 out sph,r16 ; set stack pointer to top of ram 0x1c35 ldi r16,low(ramend) 0x1c36 out spl,r16 0x1c37 sei ; enable interrupts 0x1c38 91 9159a?auto?09/10 atmel ata6614 [preliminary] notes: 1. when the bootrst fuse is pr ogrammed, the device will jump to t he boot loader address at reset, see ?boot loader sup- port ? read-while-write self-pr ogramming, atmel atmega88pa, at mega168pa and atmega328p? on page 302 . 2. when the ivsel bit in mcucr is set, interrupt vectors will be moved to the start of the boot flash section. the address of each interrupt vector will then be the address in this table added to the start address of the boot flash section. table 6-31 on page 91 shows reset and interrupt vectors placement for the various combina- tions of bootrst and ivsel settings. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the application section while the interrupt vectors are in the boot sect ion or vice versa. note: 1. the boot reset address is shown in table 6-111 on page 314 . for the bootrst fuse ?1? means unprogrammed while ?0? means programmed. the most typical and general program setup for the reset and interrupt vector addresses in atmel atmega328p is: address labels code comments 0x0000 jmp reset ; reset handler 0x0002 jmp ext_int0 ; irq0 handler 0x0004 jmp ext_int1 ; irq1 handler 0x0006 jmp pcint0 ; pcint0 handler 0x0008 jmp pcint1 ; pcint1 handler 0x000a jmp pcint2 ; pcint2 handler 0x000c jmp wdt ; watchdog timer handler 0x000e jmp tim2_compa ; timer2 compare a handler 0x0010 jmp tim2_compb ; timer2 compare b handler 0x0012 jmp tim2_ovf ; timer2 overflow handler 0x0014 jmp tim1_capt ; timer1 capture handler 0x0016 jmp tim1_compa ; timer1 compare a handler 0x0018 jmp tim1_compb ; timer1 compare b handler 0x001a jmp tim1_ovf ; timer1 overflow handler 0x001c jmp tim0_compa ; timer0 compare a handler 0x001e jmp tim0_compb ; timer0 compare b handler 0x0020 jmp tim0_ovf ; timer0 overflow handler 0x0022 jmp spi_stc ; spi transfer complete handler 24 0x002e analog comp analog comparator 25 0x0030 twi 2-wire serial interface 26 0x0032 spm ready store program memory ready table 6-30. reset and interrupt vectors in atmel ? atmega328p (continued) vectorno. program address (2) source interrupt definition table 6-31. reset and interrupt vectors placement in atmega328p (1) bootrst ivsel reset address inter rupt vectors start address 1 0 0x000 0x002 1 1 0x000 boot reset address + 0x0002 0 0 boot reset address 0x002 0 1 boot reset address boot reset address + 0x0002 92 9159a?auto?09/10 atmel ata6614 [preliminary] 0x0024 jmp usart_rxc ; usart, rx complete handler 0x0026 jmp usart_udre ; usart, udr empty handler 0x0028 jmp usart_txc ; usart, tx complete handler 0x002a jmp adc ; adc conversion complete handler 0x002c jmp ee_rdy ; eeprom ready handler 0x002e jmp ana_comp ; analog comparator handler 0x0030 jmp twi ; 2-wire serial interface handler 0x0032 jmp spm_rdy ; store program memory ready handler ; 0x0033reset: ldi r16, high(ramend); main program start 0x0034 out sph,r16 ; set stack pointer to top of ram 0x0035 ldi r16, low(ramend) 0x0036 out spl,r16 0x0037 sei ; enable interrupts 0x0038 93 9159a?auto?09/10 atmel ata6614 [preliminary] 0x3c02 ldi r16,low(ramend) 0x3c03 out spl,r16 0x3c04 sei ; enable interrupts 0x3c05 94 9159a?auto?09/10 atmel ata6614 [preliminary] to avoid unintentional changes of interrupt vector tables, a special write procedure must be followed to change the ivsel bit: a. write the interrupt vector change enable (ivce) bit to one. b. within four cycles, write the desired valu e to ivsel while writing a zero to ivce. interrupts will automatically be disabled while this sequence is executed. interrupts are dis- abled in the cycle ivce is set, and they remain disabled until after the instruction following the write to ivsel. if ivsel is not written, interrupts remain disabl ed for four cycles. the i-bit in the status register is unaffected by the automatic disabling. note: if interrupt vectors are placed in the boot loader section and boot lock bit blb02 is pro- grammed, interrupts are disabled while executin g from the application section. if interrupt vectors are placed in the application section and boot lock bit blb12 is programed, interrupts are disabled while executing from the bo ot loader section. refer to the section ?boot loader support ? read-while-write self-progra mming, atmel atmega88pa, atmega168pa and atmega328p? on page 302 for details on boot lock bits. ? bit 0 ? ivce: interrupt vector change enable the ivce bit must be written to logic one to enable change of the ivsel bit. ivce is cleared by hardware four cycles af ter it is written or when ivsel is written. setting the ivce bit will dis- able interrupts, as explained in the ivsel description a bove. see code example below. assembly code example move_interrupts: ; enable change of interrupt vectors ldi r16, (1< 96 9159a?auto?09/10 atmel ata6614 [preliminary] 6.12.2 register description 6.12.2.1 eicra ? external interrupt control register a the external interrupt control register a contains control bits for interrupt sense control. ? bit 7..4 ? res: reserved bits these bits are unused bits in the atmel ? atmega48pa/88pa/168 pa/328p, and will always read as zero. ? bit 3, 2 ? isc11, isc10: interrupt sense control 1 bit 1 and bit 0 the external interrupt 1 is activated by the external pin int1 if the sreg i-flag and the corre- sponding interrupt mask are set. the level and edges on the external int1 pin that activate the interrupt are defined in table 6-32 . the value on the int1 pin is sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last longe r than one clock period will generate an interrupt. shorter pulses are not guaranteed to generate an interrupt. if low level interrupt is selected, th e low level must be held until the co mpletion of the currently executing instruction to generate an interrupt. ? bit 1, 0 ? isc01, isc00: interrupt sense control 0 bit 1 and bit 0 the external interrupt 0 is activated by the external pin int0 if the sreg i-flag and the corre- sponding interrupt mask are set. the level and edges on the external int0 pin that activate the interrupt are defined in table 6-33 . the value on the int0 pin is sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last longe r than one clock period will generate an interrupt. shorter pulses are not guaranteed to generate an interrupt. if low level interrupt is selected, th e low level must be held until the co mpletion of the currently executing instruction to generate an interrupt. bit 76543210 (0x69) ? ? ? ? isc11 isc10 isc01 isc00 eicra read/write r r r r r/w r/w r/w r/w initial value00000000 table 6-32. interrupt 1 sense control isc11 isc10 description 0 0 the low level of int1 generates an interrupt request. 0 1 any logical change on int1 generates an interrupt request. 1 0 the falling edge of int1 generates an interrupt request. 1 1 the rising edge of int1 generates an interrupt request. table 6-33. interrupt 0 sense control isc01 isc00 description 0 0 the low level of int0 generates an interrupt request. 0 1 any logical change on int0 generates an interrupt request. 1 0 the falling edge of int0 generates an interrupt request. 1 1 the rising edge of int0 generates an interrupt request. 97 9159a?auto?09/10 atmel ata6614 [preliminary] 6.12.2.2 eimsk ? external interrupt mask register ? bit 7..2 ? res: reserved bits these bits are unused bits in the atmel ? atmega48pa/88pa/168 pa/328p, and will always read as zero. ? bit 1 ? int1: external interrupt request 1 enable when the int1 bit is set (one) and the i-bit in the status register (sreg) is set (one), the external pin interrupt is enabled. the interrupt sense control1 bits 1/0 (isc11 and isc10) in the external interrupt control register a (eicra) define whether the external interrupt is acti- vated on rising and/or falling edge of the int1 pin or level sensed. activity on the pin will cause an interrupt request even if int1 is configured as an output. the corresponding interrupt of external interrupt request 1 is execut ed from the int1 interrupt vector. ? bit 0 ? int0: external interrupt request 0 enable when the int0 bit is set (one) and the i-bit in the status register (sreg) is set (one), the external pin interrupt is enabled. the interrupt sense control0 bits 1/0 (isc01 and isc00) in the external interrupt control register a (eicra) define whether the external interrupt is acti- vated on rising and/or falling edge of the int0 pin or level sensed. activity on the pin will cause an interrupt request even if int0 is configured as an output. the corresponding interrupt of external interrupt request 0 is execut ed from the int0 interrupt vector. 6.12.2.3 eifr ? external interrupt flag register ? bit 7..2 ? res: reserved bits these bits are unused bits in the atmel atmega48pa/88 pa/168pa/328p, and will always read as zero. ? bit 1 ? intf1: external interrupt flag 1 when an edge or logic change on the int1 pin triggers an interrupt request, intf1 becomes set (one). if th e i-bit in sreg and the int1 bit in eimsk are set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. this flag is always cleared when int1 is configured as a level interrupt. ? bit 0 ? intf0: external interrupt flag 0 when an edge or logic change on the int0 pin triggers an interrupt request, intf0 becomes set (one). if th e i-bit in sreg and the int0 bit in eimsk are set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. this flag is always cleared when int0 is configured as a level interrupt. bit 76543210 0x1d (0x3d) ??????int1int0eimsk read/write rrrrrrr/wr/w initial value00000000 bit 76543210 0x1c (0x3c) ??????intf1intf0eifr read/write rrrrrrr/wr/w initial value00000000 98 9159a?auto?09/10 atmel ata6614 [preliminary] 6.12.2.4 pcicr ? pin change interrupt control register ? bit 7..3 - res: reserved bits these bits are unused bits in the atmel ? atmega48pa/88pa/168 pa/328p, and will always read as zero. ? bit 2 - pcie2: pin change interrupt enable 2 when the pcie2 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 2 is enabled. any change on any enabled pcint23..16 pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci2 interrupt vector. pcint23..16 pins are ena bled individually by the pcmsk2 register. ? bit 1 - pcie1: pin change interrupt enable 1 when the pcie1 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 1 is enabled. any change on any enabled pcint14..8 pin will cause an inter- rupt. the corresponding interrupt of pin change interrupt request is executed from the pci1 interrupt vector. pcint14..8 pins are enabled individually by the pcmsk1 register. ? bit 0 - pcie0: pin change interrupt enable 0 when the pcie0 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 0 is enabled. any change on any enabled pcint7..0 pin will cause an inter- rupt. the corresponding interrupt of pin change interrupt request is executed from the pci0 interrupt vector. pcint7..0 pins are enabled individually by the pcmsk0 register. 6.12.2.5 pcifr ? pin change interrupt flag register ? bit 7..3 - res: reserved bits these bits are unused bits in the atmel atmega48pa/88 pa/168pa/328p, and will always read as zero. ? bit 2 - pcif2: pin change interrupt flag 2 when a logic change on any pcint23..16 pin triggers an interrupt request, pcif2 becomes set (one). if the i-bit in sreg and the pcie2 bit in pcicr ar e set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. ? bit 1 - pcif1: pin change interrupt flag 1 when a logic change on any pcint14..8 pin tri ggers an interrupt request, pcif1 becomes set (one). if the i-bit in sreg and the pcie1 bit in pcicr are set (one), the mcu will jump to the corresponding interrupt vector. the flag is cl eared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. bit 76543210 (0x68) ?????pcie2pcie1pcie0pcicr read/write rrrrrr/wr/wr/w initial value00000000 bit 76543210 0x1b (0x3b) ?????pcif2pcif1pcif0pcifr read/write rrrrrr/wr/wr/w initial value00000000 99 9159a?auto?09/10 atmel ata6614 [preliminary] ? bit 0 - pcif0: pin change interrupt flag 0 when a logic change on any pcint7..0 pin triggers an interrupt request, pcif0 becomes set (one). if the i-bit in sreg and the pcie0 bit in pcicr are set (one), the mcu will jump to the corresponding interrupt vector. the flag is cl eared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. 6.12.2.6 pcmsk2 ? pin change mask register 2 ? bit 7..0 ? pcint23..16: pin change enable mask 23..16 each pcint23..16-bit selects whether pin change interrupt is enabled on the corresponding i/o pin. if pcint23..16 is set and the pcie2 bit in pcicr is set, pin change interrupt is enabled on the corresponding i/o pin. if pcint23..16 is cleared, pin change interrupt on the corresponding i/o pin is disabled. 6.12.2.7 pcmsk1 ? pin change mask register 1 ? bit 7 ? res: reserved bit this bit is an unused bit in the atmel ? atmega48pa/88pa/168pa/328p, and will always read as zero. ? bit 6..0 ? pcint14..8: pin change enable mask 14..8 each pcint14..8-bit selects whether pin change interrupt is enabled on the corresponding i/o pin. if pcint14..8 is set and the pcie1 bit in pcicr is set, pin change interrupt is enabled on the corresponding i/o pin. if pcint14..8 is cleared, pin change interrupt on the corresponding i/o pin is disabled. 6.12.2.8 pcmsk0 ? pin change mask register 0 ? bit 7..0 ? pcint7..0: pin change enable mask 7..0 each pcint7..0 bit selects whether pin change interrupt is enabled on the corresponding i/o pin. if pcint7..0 is set and the pcie0 bit in pcicr is set, pin change interrupt is enabled on the corresponding i/o pin. if pcint7..0 is cl eared, pin change interrupt on the corresponding i/o pin is disabled. bit 76543210 (0x6d) pcint23 pcint22 pcint21 pcint20 pcint19 pcint18 pcint17 pcint16 pcmsk2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x6c) ? pcint14 pcint13 pcint12 pcint11 pcint10 pcint9 pcint8 pcmsk1 read/write r r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x6b) pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 pcmsk0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 100 9159a?auto?09/10 atmel ata6614 [preliminary] 6.13 i/o-ports 6.13.1 overview all avr ports have true read-modify-write functionality when used as general digital i/o ports. this means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the sbi and cbi instructions. the same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). each output buffer has symmetrical drive characteristics with both high sink and source capability. the pin driver is strong enough to drive led displays directly. all port pins have individually selectable pull-up resistors with a supply-voltage invariant resis- tance. all i/o pins have pr otection diodes to both v cc and ground as indicated in figure 6-23 . refer to ?electrical characteristics? on page 338 for a complete list of parameters. figure 6-23. i/o pin equivalent schematic all registers and bit references in this section are written in general form. a lower case ?x? rep- resents the numbering letter for the port, and a lower case ?n? represents the bit number. however, when using the register or bit defines in a program, the precise form must be used. for example, portb3 for bit no. 3 in port b, here documented generally as portxn. the physical i/o registers and bit locations are listed in ?register description? on page 117 . three i/o memory address locations are allocated for each port, one each for the data regis- ter ? portx, data direction register ? ddrx, and the port input pins ? pinx. the port input pins i/o location is read only, while the data register and the data direction register are read/write. however, writing a logic one to a bit in the pinx register, will result in a toggle in the corresponding bit in the data register. in addition, the pull-up disable ? pud bit in mcucr disables the pull-up function for all pins in all ports when set. using the i/o port as genera l digital i/o is described in ?ports as general digital i/o? on page 101 . most port pins are multiplexed with alternat e functions for the peripheral features on the device. how each alternate function interferes with the port pin is described in ?alternate port functions? on page 105 . refer to the individual module se ctions for a full description of the alternate functions. note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital i/o. c pin logic r pu see figure "general digital i/o" for details pxn 101 9159a?auto?09/10 atmel ata6614 [preliminary] 6.13.2 ports as general digital i/o the ports are bi-directional i/o ports with optional internal pull-ups. figure 6-24 shows a func- tional description of one i/o-port pin, here generically called pxn. figure 6-24. general digital i/o (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are co mmon to all pins within the same port. clk i/o , sleep, and pud are common to all ports. 6.13.2.1 configuring the pin each port pin consists of three register bi ts: ddxn, portxn, and pinxn. as shown in ?regis- ter description? on page 117 , the ddxn bits are accessed at the ddrx i/o address, the portxn bits at the portx i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register selects the direction of this pin. if ddxn is written logic one, pxn is configured as an output pin. if ddxn is wr itten logic zero, pxn is configured as an input pin. if portxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. to switch the pull-up resistor off, portxn has to be written logic zero or the pin has to be configured as an output pin. the port pins are tri-stated when reset condition becomes active, even if no clocks are running. if portxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). if portxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). clk rpx rrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q reset reset q q d q q d clr portxn q q d clr ddxn pinxn data b u s sleep sleep: sleep control pxn i/o wpx 0 1 wrx wpx: write pinx register 102 9159a?auto?09/10 atmel ata6614 [preliminary] 6.13.2.2 toggling the pin writing a logic one to pinxn toggles the value of portxn, independent on the value of ddrxn. note that the sbi instruction can be used to toggle one single bit in a port. 6.13.2.3 switching between input and output when switching between tri-state ({ddxn, portxn} = 0b00) and output high ({ddxn, portxn} = 0b11), an intermediate state with either pull-up enabled {ddxn, portxn} = 0b01) or output low ({ddxn, portxn} = 0b10) must occur. normally, the pull-up enabled state is fully acceptable, as a high-impedance environment will not notice th e difference between a strong high driver and a pull-up. if this is not the case, the pud bit in the mcucr register can be set to disable all pull-ups in all ports. switching between input with pull-up and output low generates the same problem. the user must use either the tri-state ({ddxn, portxn} = 0b00) or the output high state ({ddxn, portxn} = 0b11) as an intermediate step. table 6-34 summarizes the control signals for the pin value. 6.13.2.4 reading the pin value independent of the setting of data direction bit ddxn, the port pin can be read through the pinxn register bit. as shown in figure 6-24 , the pinxn register bit and the preceding latch constitute a synchronizer. this is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. figure 6-25 shows a timing diagram of the synchronization when re ading an externally applied pin value. the max- imum and minimum propagation delays are denoted t pd,max and t pd,min respectively. table 6-34. port pin configurations ddxn portxn pud (in mcucr) i/o pull-up comment 0 0 x input no tri-state (hi-z) 0 1 0 input yes pxn will source current if ext. pulled low. 0 1 1 input no tri-state (hi-z) 1 0 x output no output low (sink) 1 1 x output no output high (source) 103 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-25. synchronization when reading an externally applied pin value consider the clock period starting shortly after the first falling edge of the system clock. the latch is closed when the clock is low, and goes transparent when the cl ock is high, as indi- cated by the shaded region of the ?sync latch? signal. the signal value is latched when the system clock goes low. it is clocked into the pi nxn register at the succeeding positive clock edge. as indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ? and 1? system clock period depending upon the time of assertion. when reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in figure 6-26 . the out instruction sets the ?sync latch? signal at the positive edge of the clock. in this case, the delay tpd through the synchronizer is 1 system clock period. figure 6-26. synchronization when reading a software assigned pin value the following code example shows how to set port b pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. the result- ing pin values are read back again, but as pr eviously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. xxx in r17, pinx 0x00 0xff instructions sync latch pinxn r17 xxx system clk t pd, max t pd, min out portx, r16 nop in r17, pinx 0xff 0x00 0xff system clk r16 instructions sync latch pinxn r17 t pd 104 9159a?auto?09/10 atmel ata6614 [preliminary] note: 1. for the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. 6.13.2.5 digital input enable and sleep modes as shown in figure 6-24 , the digital input signal can be clamped to ground at the input of the schmitt trigger. the signal denoted sleep in the figure, is set by the mcu sleep controller in power-down mode, power-save mode, and standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to v cc /2. sleep is overridden for port pins enabled as ex ternal interrupt pins. if the external interrupt request is not enabled, sleep is active also fo r these pins. sleep is al so overridden by vari- ous other alternate functions as described in ?alternate port functions? on page 105 . if a logic high level (?one?) is present on an asynchronous external interrupt pin configured as ?interrupt on rising edge, falling edge, or any logic change on pin? while the external inter- rupt is not enabled, the correspo nding external inte rrupt flag will be set when resuming from the above mentioned sleep mode, as the clamping in these sleep mode produces the requested logic change. assembly code example (1) ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16,(1< 106 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-27. alternate port functions (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are co mmon to all pins within the same port. clk i/o , sleep, and pud are common to all ports. all other signals are unique for each pin. clk rpx rrx wrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q set clr 0 1 0 1 0 1 dixn aioxn dieoexn pvovxn pvoexn ddovxn ddoexn puoexn puovxn puoexn: pxn pull-up override enable puovxn: pxn pull-up override value ddoexn: pxn data direction override enable ddovxn: pxn data direction override value pvoexn: pxn port value override enable pvovxn: pxn port value override value dixn: digital input pin n on portx aioxn: analog input/output pin n on portx reset reset q q d clr q q d clr q q d clr pinxn portxn ddxn data b u s 0 1 dieovxn sleep dieoexn: pxn digital input-enable override enable dieovxn: pxn digital input-enable override value sleep: sleep control pxn i/o 0 1 ptoexn ptoexn: pxn, port toggle override enable wpx: write pinx wpx 107 9159a?auto?09/10 atmel ata6614 [preliminary] table 6-35 summarizes the function of the overriding signals. the pin and port indexes from figure 6-27 on page 106 are not shown in the succeeding tables. the overriding signals are generated internally in the modules having the alternate function. the following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. refer to the alternate function description for fur- ther details. table 6-35. generic description of overriding signals for alternate functions signal name full name description puoe pull-up override enable if this signal is set, the pull-up enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled when {ddxn, portxn, pud} = 0b010. puov pull-up override value if puoe is set, the pull-up is enabled/disabled when puov is set/cleared, regardless of the setting of the ddxn, portxn, and pud register bits. ddoe data direction override enable if this signal is set, the output driver enable is controlled by the ddov signal. if this signal is cleared, the output driver is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output driver is enabled/disabled when ddov is set/cleared, regardless of the setting of the ddxn register bit. pvoe port value override enable if this signal is set and the output driver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, th e port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bit. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted. dieoe digital input enable override enable if this bit is set, the digital input enable is controlled by the dieov signal. if this signal is cleared, the digital input enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital input is enabled/disabled when dieov is set/cleared, regard less of the mcu state (normal mode, sleep mode). di digital input this is the digital input to alternate functions. in the figure, the signal is connected to the outp ut of the schmitt trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer. aio analog input/output this is the analog i nput/output to/from alte rnate functions. the signal is connected directly to the pad, and can be used bi-directionally. 108 9159a?auto?09/10 atmel ata6614 [preliminary] 6.13.3.1 alternate functions of port b the port b pins with alternate functions are shown in table 6-36 . the alternate pin configuration is as follows: ? xtal2/tosc2/pcint7 ? port b, bit 7 xtal2: chip clock oscillator pi n 2. used as clock pin for cr ystal oscillator or low-frequency crystal oscillator. when used as a clock pi n, the pin can not be used as an i/o pin. tosc2: timer oscillator pin 2. used only if in ternal calibrated rc oscillator is selected as chip clock source, and the asynchronous timer is enabled by the correct setting in assr. when the as2 bit in assr is set (one) and t he exclk bit is cleared (zero) to enable asyn- chronous clocking of timer/counter2 using th e crystal oscillator, pin pb7 is disconnected from the port, and becomes the inve rting output of the oscillator am plifier. in this mode, a crys- tal oscillator is connected to this pin, a nd the pin cannot be used as an i/o pin. pcint7: pin change interrupt source 7. the pb7 pin can serve as an external interrupt source. if pb7 is used as a clock pin, ddb 7, portb7 and pinb7 will all read 0. ? xtal1/tosc1/pcint6 ? port b, bit 6 xtal1: chip clock oscillator pin 1. used for a ll chip clock sources exce pt internal calibrated rc oscillator. when used as a clock pin, the pin can not be used as an i/o pin. tosc1: timer oscillator pin 1. used only if in ternal calibrated rc oscillator is selected as chip clock source, and the asynchronous timer is enabled by the correct setting in assr. table 6-36. port b pins alternate functions port pin alternate functions pb7 xtal2 ( chip clock oscillator pin 2 ) tosc2 ( timer oscillator pin 2 ) pcint7 (pin change interrupt 7) pb6 xtal1 ( chip clock oscillator pin 1 or external clock input ) tosc1 ( timer oscillator pin 1 ) pcint6 (pin change interrupt 6) pb5 sck (spi bus master clock input) pcint5 (pin change interrupt 5) pb4 miso (spi bus master input/slave output) pcint4 (pin change interrupt 4) pb3 mosi (spi bus master output/slave input) oc2a (timer/counter2 output compare match a output) pcint3 (pin change interrupt 3) pb2 ss (spi bus master slave select) oc1b (timer/counter1 output compare match b output) pcint2 (pin change interrupt 2) pb1 oc1a (timer/counter1 output compare match a output) pcint1 (pin change interrupt 1) pb0 icp1 (timer/counter1 input capture input) clko (divided system clock output) pcint0 (pin change interrupt 0) 109 9159a?auto?09/10 atmel ata6614 [preliminary] when the as2 bit in assr is set (one) to ena ble asynchronous clocki ng of timer/counter2, pin pb6 is disconnected from t he port, and becomes th e input of the invert ing oscillator ampli- fier. in this mode, a crystal os cillator is connected to this pin, and the pin can not be used as an i/o pin. pcint6: pin change interrupt source 6. the pb6 pin can serve as an external interrupt source. if pb6 is used as a clock pin, ddb 6, portb6 and pinb6 will all read 0. ? sck/pcint5 ? port b, bit 5 sck: master clock output, slave clock input pin for spi channel. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb5. when the spi is enabled as a master, the data direction of this pin is controlled by ddb5. when the pin is forced by the spi to be an i nput, the pull-up can still be controlled by the portb5 bit. pcint5: pin change interrupt source 5. the pb5 pin can serve as an external interrupt source. ? miso/pcint4 ? port b, bit 4 miso: master data input, slave data output pin for spi channel. when the spi is enabled as a master, this pin is configured as an input regardless of the setting of ddb4. when the spi is enabled as a slave, the data direction of this pin is controlled by ddb4. when the pin is forced by the spi to be an input, the pull-up can still be controlled by the portb4 bit. pcint4: pin change interrupt source 4. the pb4 pin can serve as an external interrupt source. ? mosi/oc2/pcint3 ? port b, bit 3 mosi: spi master data output, slave data input for spi channel. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb3. when the spi is enabled as a master, the data direction of this pin is controlled by ddb3. when the pin is forced by the spi to be an i nput, the pull-up can still be controlled by the portb3 bit. oc2, output compare match output: the pb3 pin can serve as an external output for the timer/counter2 compare match. the pb3 pin has to be configured as an output (ddb3 set (one)) to serve this function. the oc2 pin is also the output pin for the pwm mode timer function. pcint3: pin change interrupt source 3. the pb3 pin can serve as an external interrupt source. ?ss /oc1b/pcint2 ? port b, bit 2 ss : slave select input. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb2. as a slave, t he spi is activated when this pin is driven low. when the spi is enabled as a master, the data direction of this pin is controlled by ddb2. when the pin is forced by the spi to be an input , the pull-up can still be controlled by the portb2 bit. oc1b, output compare match output: the pb2 pin can serve as an external output for the timer/counter1 compare match b. the pb2 pin has to be configured as an output (ddb2 set (one)) to serve this function. the oc1b pin is also the output pin for the pwm mode timer function. 110 9159a?auto?09/10 atmel ata6614 [preliminary] pcint2: pin change interrupt source 2. the pb2 pin can serve as an external interrupt source. ? oc1a/pcint1 ? port b, bit 1 oc1a, output compare match output: the pb1 pin can serve as an external output for the timer/counter1 compare match a. the pb1 pin has to be configured as an output (ddb1 set (one)) to serve this function. the oc1a pin is also the output pin for the pwm mode timer function. pcint1: pin change interrupt source 1. the pb1 pin can serve as an external interrupt source. ? icp1/clko/pcint0 ? port b, bit 0 icp1, input capture pin: the pb0 pin can act as an input capture pin for timer/counter1. clko, divided system clock: the divided system clock can be output on the pb0 pin. the divided system clock will be output if the ck out fuse is programm ed, regardless of the portb0 and ddb0 settings. it will also be output during reset. pcint0: pin change interrupt source 0. the pb0 pin can serve as an external interrupt source. table 6-37 and table 6-38 on page 111 relate the alternate functions of port b to the overrid- ing signals shown in figure 6-27 on page 106 . spi mstr input and spi slave output constitute the miso signal, while mosi is di vided into spi mstr output and spi slave input. table 6-37. overriding signals for alternate functions in pb7..pb4 signal name pb7/xtal2/ tosc2/pcint7 (1) pb6/xtal1/ tosc1/pcint6 (1) pb5/sck/ pcint5 pb4/miso/ pcint4 puoe intrc ? extck + as2 intrc + as2 spe ? mstr spe ? mstr puov 0 0 portb5 ? pud portb4 ? pud ddoe intrc ? extck + as2 intrc + as2 spe ? mstr spe ? mstr ddov 0 0 0 0 pvoe 0 0 spe ? mstr spe ? mstr pvov 0 0 sck output spi slave output dieoe intrc ? extck + as2 + pcint7 ? pcie0 intrc + as2 + pcint6 ? pcie0 pcint5 ? pcie0 pcint4 ? pcie0 dieov (intrc + extck) ? as2 intrc ? as2 11 di pcint7 input pcint6 input pcint5 input sck input pcint4 input spi mstr input aio oscillator output oscillator/clock input ?? 111 9159a?auto?09/10 atmel ata6614 [preliminary] notes: 1. intrc means that one of the internal rc oscillators ar e selected (by the cksel fuses), extck means that external clock is selected (by the cksel fuses) 6.13.3.2 alternate functions of port c the port c pins with alternate functions are shown in table 6-39 . table 6-38. overriding signals for alternate functions in pb3..pb0 signal name pb3/mosi/ oc2/pcint3 pb2/ss / oc1b/pcint2 pb1/oc1a/ pcint1 pb0/icp1/ pcint0 puoe spe ? mstr spe ? mstr 00 puov portb3 ? pud portb2 ? pud 00 ddoe spe ? mstr spe ? mstr 00 ddov0000 pvoe spe ? mstr + oc2a enable oc1b enable oc1a enable 0 pvov spi mstr output + oc2a oc1b oc1a 0 dieoe pcint3 ? pcie0 pcint2 ? pcie0 pcint1 ? pcie0 pcint0 ? pcie0 dieov1111 di pcint3 input spi slave input pcint2 input spi ss pcint1 input pcint0 input icp1 input aio???? table 6-39. port c pins alternate functions port pin alternate function pc6 reset (reset pin) pcint14 (pin change interrupt 14) pc5 adc5 (adc input channel 5) scl (2-wire serial bus clock line) pcint13 (pin change interrupt 13) pc4 adc4 (adc input channel 4) sda (2-wire serial bus data input/output line) pcint12 (pin change interrupt 12) pc3 adc3 (adc input channel 3) pcint11 (pin change interrupt 11) pc2 adc2 (adc input channel 2) pcint10 (pin change interrupt 10) pc1 adc1 (adc input channel 1) pcint9 (pin change interrupt 9) pc0 adc0 (adc input channel 0) pcint8 (pin change interrupt 8) 112 9159a?auto?09/10 atmel ata6614 [preliminary] the alternate pin configuration is as follows: ? reset /pcint14 ? port c, bit 6 reset , reset pin: when the rstdisbl fuse is programmed, this pin functions as a normal i/o pin, and the part will have to rely on power-on reset and brown-out reset as its reset sources. when the rstdisbl fuse is unprogrammed, the reset circuitry is connected to the pin, and the pin can not be used as an i/o pin. if pc6 is used as a reset pin, ddc6, portc6 and pinc6 will all read 0. pcint14: pin change interrupt source 14. the pc6 pin can serve as an external interrupt source. ? scl/adc5/pcint13 ? port c, bit 5 scl, 2-wire serial interface clock: when the twen bit in twcr is set (one) to enable the 2-wire serial interface, pin pc5 is disconnected from the port and becomes the serial clock i/o pin for the 2-wire serial interface. in this m ode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. pc5 can also be used as adc input channel 5. note that adc input channel 5 uses digital power. pcint13: pin change interrupt source 13. the pc5 pin can serve as an external interrupt source. ? sda/adc4/pcint12 ? port c, bit 4 sda, 2-wire serial interface data: when the twen bit in twcr is set (one) to enable the 2-wire serial interface, pin pc4 is disconnected from the port and becomes the serial data i/o pin for the 2-wire serial interface. in this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. pc4 can also be used as adc input channel 4. note that adc input channel 4 uses digital power. pcint12: pin change interrupt source 12. the pc4 pin can serve as an external interrupt source. ? adc3/pcint11 ? port c, bit 3 pc3 can also be used as adc input channel 3. note that adc input channel 3 uses analog power. pcint11: pin change interrupt source 11. the pc3 pin can serve as an external interrupt source. ? adc2/pcint10 ? port c, bit 2 pc2 can also be used as adc input channel 2. note that adc input channel 2 uses analog power. pcint10: pin change interrupt source 10. the pc2 pin can serve as an external interrupt source. 113 9159a?auto?09/10 atmel ata6614 [preliminary] ? adc1/pcint9 ? port c, bit 1 pc1 can also be used as adc input channel 1. note that adc input channel 1 uses analog power. pcint9: pin change interrupt source 9. the pc1 pin can serve as an external interrupt source. ? adc0/pcint8 ? port c, bit 0 pc0 can also be used as adc input channel 0. note that adc input channel 0 uses analog power. pcint8: pin change interrupt source 8. the pc0 pin can serve as an external interrupt source. table 6-40 and table 6-41 relate the alternate functions of port c to the overriding signals shown in figure 6-27 on page 106 . note: 1. when enabled, the 2-wire serial interface enables slew-rate controls on the output pins pc4 and pc5. this is not shown in the figure. in addition, spike filters are connected between the aio outputs shown in the port figure and the digital logic of the twi module. table 6-40. overriding signals for alternate functions in pc6..pc4 (1) signal name pc6/reset /pcint14 pc5/scl/adc5/pcint 13 pc4/sda/adc4/pcint12 puoe rstdisbl twen twen puov 1 portc5 ? pud portc4 ? pud ddoe rstdisbl twen twen ddov 0 scl_out sda_out pvoe 0 twen twen pvov 0 0 0 dieoe rstdisbl + pcint14 ? pcie1 pcint13 ? pcie1 + adc5d pcint12 ? pcie1 + adc4d dieov rstdisbl pcint13 ? pcie1 pcint12 ? pcie1 di pcint14 input pcint13 input pcint12 input aio reset input adc5 input / scl input adc4 input / sda input 114 9159a?auto?09/10 atmel ata6614 [preliminary] 6.13.3.3 alternate functions of port d the port d pins with alternate functions are shown in table 6-42 . table 6-41. overriding signals for alternate functions in pc3..pc0 signal name pc3/adc3/ pcint11 pc2/adc2/ pcint10 pc1/adc1/ pcint9 pc0/adc0/ pcint8 puoe0000 puov0000 ddoe0000 ddov0000 pvoe0000 pvov0000 dieoe pcint11 ? pcie1 + adc3d pcint10 ? pcie1 + adc2d pcint9 ? pcie1 + adc1d pcint8 ? pcie1 + adc0d dieov pcint11 ? pcie1 pcint10 ? pcie 1 pcint9 ? pcie1 pcint8 ? pcie1 di pcint11 input pcint10 input pcint9 input pcint8 input aio adc3 input adc2 input adc1 input adc0 input table 6-42. port d pins alternate functions port pin alternate function pd7 ain1 (analog comparator negative input) pcint23 (pin change interrupt 23) pd6 ain0 (analog comparator positive input) oc0a (timer/counter0 output compare match a output) pcint22 (pin change interrupt 22) pd5 t1 (timer/counter 1 external counter input) oc0b (timer/counter0 output compare match b output) pcint21 (pin change interrupt 21) pd4 xck (usart external clock input/output) t0 (timer/counter 0 external counter input) pcint20 (pin change interrupt 20) pd3 int1 (external interrupt 1 input) oc2b (timer/counter2 output compare match b output) pcint19 (pin change interrupt 19) pd2 int0 (external interrupt 0 input) pcint18 (pin change interrupt 18) pd1 txd (usart output pin) pcint17 (pin change interrupt 17) pd0 rxd (usart input pin) pcint16 (pin change interrupt 16) 115 9159a?auto?09/10 atmel ata6614 [preliminary] the alternate pin configuration is as follows: ? ain1/oc2b/pcint23 ? port d, bit 7 ain1, analog comparator negative input. configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. pcint23: pin change interrupt source 23. the pd7 pin can serve as an external interrupt source. ? ain0/oc0a/pcint22 ? port d, bit 6 ain0, analog comparator positive input. configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. oc0a, output compare match output: the pd6 pin can serve as an external output for the timer/counter0 compare match a. the pd6 pin has to be configured as an output (ddd6 set (one)) to serve this function. the oc0a pin is also the output pin for the pwm mode timer function. pcint22: pin change interrupt source 22. the pd6 pin can serve as an external interrupt source. ? t1/oc0b/pcint21 ? port d, bit 5 t1, timer/counter1 counter source. oc0b, output compare match output: the pd5 pin can serve as an external output for the timer/counter0 compare match b. the pd5 pin has to be configured as an output (ddd5 set (one)) to serve this function. the oc0b pin is also the output pin for the pwm mode timer function. pcint21: pin change interrupt source 21. the pd5 pin can serve as an external interrupt source. ? xck/t0/pcint20 ? port d, bit 4 xck, usart external clock. t0, timer/counter0 counter source. pcint20: pin change interrupt source 20. the pd4 pin can serve as an external interrupt source. ? int1/oc2b/pcint19 ? port d, bit 3 int1, external interrupt source 1: the pd3 pin can serve as an external interrupt source. oc2b, output compare match output: the pd3 pin can serve as an external output for the timer/counter0 compare match b. the pd3 pin has to be configured as an output (ddd3 set (one)) to serve this function. the oc2b pin is also the output pin for the pwm mode timer function. pcint19: pin change interrupt source 19. the pd3 pin can serve as an external interrupt source. 116 9159a?auto?09/10 atmel ata6614 [preliminary] ? int0/pcint18 ? port d, bit 2 int0, external interrupt source 0: the pd2 pin can serve as an external interrupt source. pcint18: pin change interrupt source 18. the pd2 pin can serve as an external interrupt source. ? txd/pcint17 ? port d, bit 1 txd, transmit data (data output pin for the usart). when the usart transmitter is enabled, this pin is configured as an output regardless of the value of ddd1. pcint17: pin change interrupt source 17. the pd1 pin can serve as an external interrupt source. ? rxd/pcint16 ? port d, bit 0 rxd, receive data (data input pin for the usart). when the usart receiver is enabled this pin is configured as an input regardless of the value of ddd0. when the usart forces this pin to be an input, the pull-up can still be controlled by the portd0 bit. pcint16: pin change interrupt source 16. the pd0 pin can serve as an external interrupt source. table 6-43 and table 6-44 relate the alternate functions of port d to the overriding signals shown in figure 6-27 on page 106 . table 6-43. overriding signals for alternate functions pd7..pd4 signal name pd7/ain1 /pcint23 pd6/ain0/ oc0a/pcint22 pd5/t1/oc0b/ pcint21 pd4/xck/ t0/pcint20 puoe0000 puo0000 ddoe0000 ddov0000 pvoe 0 oc0a enable oc0b enable umsel pvov 0 oc0a oc0b xck output dieoe pcint23 ? pcie2 pcint22 ? pcie2 p cint21 ? pcie2 pcint20 ? pcie2 dieov1111 di pcint23 input pcint22 input pcint21 input t1 input pcint20 input xck input t0 input aio ain1 input ain0 input ? ? 117 9159a?auto?09/10 atmel ata6614 [preliminary] 6.13.4 register description 6.13.4.1 mcucr ? mcu control register ? bit 4 ? pud: pull-up disable when this bit is written to one, the pull-ups in the i/o ports are disabled even if the ddxn and portxn registers are configured to enable the pull-ups ({ddxn, portxn} = 0b01). see ?configuring the pin? on page 101 for more details about this feature. 6.13.4.2 portb ? the port b data register 6.13.4.3 ddrb ? the port b data direction register table 6-44. overriding signals for alternate functions in pd3..pd0 signal name pd3/oc2b/int1/ pcint19 pd2/int0/ pcint18 pd1/txd/ pcint17 pd0/rxd/ pcint16 puoe 0 0 txen rxen puo 0 0 0 portd0 ? pud ddoe 0 0 txen rxen ddov 0 0 1 0 pvoe oc2b enable 0 txen 0 pvov oc2b 0 txd 0 dieoe int1 enable + pcint19 ? pcie2 int0 enable + pcint18 ? pcie1 pcint17 ? pcie2 pcint16 ? pcie2 dieov1111 di pcint19 input int1 input pcint18 input int0 input pcint17 input pcint16 input rxd aio???? bit 7 6 5 4 3 2 1 0 0x35 (0x55) ? bods bodse pud ? ? ivsel ivce mcucr read/write r r r r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x05 (0x25) portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 portb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x04 (0x24) ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 118 9159a?auto?09/10 atmel ata6614 [preliminary] 6.13.4.4 pinb ? the port b input pins address 6.13.4.5 portc ? the port c data register 6.13.4.6 ddrc ? the port c data direction register 6.13.4.7 pinc ? the port c input pins address 6.13.4.8 portd ? the port d data register 6.13.4.9 ddrd ? the port d data direction register 6.13.4.10 pind ? the port d input pins address bit 76543210 0x03 (0x23) pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 pinb read/writerrrrrrrr initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 0x08 (0x28) ? portc6 portc5 portc4 portc3 portc2 portc1 portc0 portc read/write r r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x07 (0x27) ? ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc read/write r r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x06 (0x26) ? pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 pinc read/writerrrrrrrr initial value 0 n/a n/a n/a n/a n/a n/a n/a bit 76543210 0x0b (0x2b) portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 portd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x0a (0x2a) ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x09 (0x29) pind7 pind6 pind5 pind4 pi nd3 pind2 pind1 pind0 pind read/writerrrrrrrr initial value n/a n/a n/a n/a n/a n/a n/a n/a 119 9159a?auto?09/10 atmel ata6614 [preliminary] 6.14 8-bit timer/counter0 with pwm 6.14.1 features ? two independent output compare units ? double buffered outp ut compare registers ? clear timer on compare match (auto reload) ? glitch free, phase correct pulse width modulator (pwm) ? variable pwm period ? frequency generator ? three independent interrupt sources (tov0, ocf0a, and ocf0b) 6.14.2 overview timer/counter0 is a general purpose 8-bit ti mer/counter module, with two independent out- put compare units, and with pwm support. it allows accurate program execution timing (event management) and wave generation. a simplified block diagram of the 8-bit timer/counter is shown in figure 6-28 . the device-spe- cific i/o register and bit locations are listed in the ?register description? on page 131 . the prtim0 bit in ?minimizing power consumption? on page 67 must be written to zero to enable timer/counter0 module. figure 6-28. 8-bit timer/counter block diagram clock select timer/counter data bus ocrna ocrnb = = tcntn waveform generation waveform generation ocna ocnb = fixed top value control logic = 0 top bottom count clear direction tovn (int.req.) ocna (int.req.) ocnb (int.req.) tccrna tccrnb tn edge detector ( from prescaler ) clk tn 120 9159a?auto?09/10 atmel ata6614 [preliminary] 6.14.2.1 definitions many register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, in this case 0. a lower case ?x? replaces the output com- pare unit, in this case compar e unit a or compare unit b. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt0 for accessing timer/counter0 counter value and so on. the definitions in table 6-45 are also used extensively throughout the document. 6.14.2.2 registers the timer/counter (tcnt0) and output compare registers (ocr0a and ocr0b) are 8-bit registers. interrupt request (abbreviated to int.req. in the figure) signals are all visible in the timer interrupt flag register (tifr0). all in terrupts are individually masked with the timer interrupt mask register (timsk0). tifr0 and timsk0 are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the t0 pin. the clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t0 ). the double buffered output compare registers (ocr0a and ocr0b) are compared with the timer/counter value at all times. the result of the compare can be used by the waveform generator to generate a pwm or variable frequency output on the output compare pins (oc0a and oc0b). see ?using the output compare unit? on page 148. for details. the com- pare match event will also set the compare flag (ocf0a or ocf0b) which can be used to generate an output compare interrupt request. 6.14.3 timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic wh ich is controlled by the clock select (cs02:0) bits located in the timer/counter control r egister (tccr0b). for details on clock sources and prescaler, see ?timer/counter0 and timer/counter1 prescalers? on page 167 . table 6-45. definitions bottom the counter reaches the bottom when it becomes 0x00. max the counter reaches its maximum when it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr0a register. the assignment is dependent on the mode of operation. 121 9159a?auto?09/10 atmel ata6614 [preliminary] 6.14.4 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. fig- ure 6-29 shows a block diagram of the counter and its surroundings. figure 6-29. counter unit block diagram signal description (internal signals): count increment or decrement tcnt0 by 1. direction select between increment and decrement. clear clear tcnt0 (set all bits to zero). clk t n timer/counter clock, referred to as clk t0 in the following. top signalize that tcnt0 has reached maximum value. bottom signalize that tcnt0 has re ached minimum value (zero). depending of the mode of operation used, the counter is cleared, incremented, or decre- mented at each timer clock (clk t0 ). clk t0 can be generated from an external or internal clock source, selected by the clock select bits (c s02:0). when no clock source is selected (cs02:0 = 0) the timer is stopped. however, the tcnt0 value can be accessed by the cpu, regardless of whether clk t0 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the wgm01 and wgm00 bits located in the timer/counter control register (tccr0a) and the wgm02 bit located in the timer/counter control register b (tccr0b). t here are close connecti ons between how the counter behaves (counts) and how waveforms are generated on the output compare outputs oc0a and oc0b. for more details about advanced counting sequences and waveform gener- ation, see ?modes of operation? on page 124 . the timer/counter overflow flag (tov0) is set according to the mode of operation selected by the wgm02:0 bits. tov0 can be used for generating a cpu interrupt. data bus tcntn control logic count tovn (int.req.) clock select top tn edge detector ( from prescaler ) clk tn bottom direction clear 122 9159a?auto?09/10 atmel ata6614 [preliminary] 6.14.5 output compare unit the 8-bit comparator continuously compares tcnt0 with the output compare registers (ocr0a and ocr0b). whenever tcnt0 equals ocr0a or ocr0b, the comparator signals a match. a match will set the output compare fl ag (ocf0a or ocf0b) at the next timer clock cycle. if the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. the output compare flag is automatically cleared when the interrupt is executed. alternatively, the flag can be cleared by software by writing a logical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to operating mode set by the wgm02:0 bits and compare output mode (com0x1:0) bits. the max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation ( ?modes of operation? on page 124 ). figure 6-30 shows a block diagram of the output compare unit. figure 6-30. output compare unit, block diagram the ocr0x registers are double buffered when using any of the pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double bufferi ng synchronizes the update of the ocr0x compare registers to either top or bottom of the counting sequence. the synchronization pre- vents the occurrence of odd-length, non-symme trical pwm pulses, thereby making the output glitch-free. the ocr0x register access may seem complex, but this is not case. when the double buffer- ing is enabled, the cpu has access to the ocr0x buffer register, and if double buffering is disabled the cpu will a ccess the ocr0x directly. 6.14.5.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (foc0x) bit. fo rcing compare match will not set the ocf0x flag or reload/clear the timer, but the oc0x pin will be updated as if a real com- pare match had occurred (the com0x1:0 bits settings define whether the oc0x pin is set, cleared or toggled). ocfn x (int.req.) = (8-bit comparator ) ocrnx ocnx data b u s tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom 123 9159a?auto?09/10 atmel ata6614 [preliminary] 6.14.5.2 compare match blocking by tcnt0 write all cpu write operations to th e tcnt0 register will block any co mpare match that occur in the next timer clock cycle, even when the timer is stopp ed. this feature allows ocr0x to be initial- ized to the same value as tcnt0 without triggering an interrupt when the timer/counter clock is enabled. 6.14.5.3 using the output compare unit since writing tcnt0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing tcnt0 when using the output compare unit, independently of whether the timer/counter is running or not. if the value written to tcnt0 equals the ocr0x value, the compare match will be miss ed, resulting in incorrect waveform generation. similarly, do not write the tcnt0 value equal to bottom when the counter is downcounting. the setup of the oc0x should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc0x value is to use the force output com- pare (foc0x) strobe bits in normal mode. th e oc0x registers keep their values even when changing between waveform generation modes. be aware that the com0x1:0 bits are not double buffered together with the compare value. changing the com0x1:0 bits will take effect immediately. 6.14.6 compare match output unit the compare output mode (com0x1:0) bits have two functions. the waveform generator uses the com0x1:0 bits for defining the output compare (oc0x) state at the next compare match. also, the com0x1:0 bits control the oc0x pin output source. figure 6-31 shows a sim- plified schematic of the logic affected by the com0x1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control reg- isters (ddr and port) th at are affected by the com0x1:0 bits are shown. when referring to the oc0x state, the reference is for the internal oc0x register, not the oc0x pin. if a system reset occur, the oc0x register is reset to ?0?. figure 6-31. compare match output unit, schematic port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data bus focn clk i/o 124 9159a?auto?09/10 atmel ata6614 [preliminary] the general i/o port function is overridden by the output compare (oc0x) from the waveform generator if either of the com0x1:0 bits are set. however, the oc0x pin direction (input or output) is still controlled by the data direction register (ddr ) for the port pin. the data direc- tion register bit for the oc0x pin (ddr_oc0x) must be set as output before the oc0x value is visible on the pin. the port override function is independent of the waveform generation mode. the design of the output compare pin logic allows initialization of the oc0x state before the output is enabled. note that some com0x1:0 bit settings are reserved for certain modes of operation. see ?register description? on page 131. 6.14.6.1 compare output mode and waveform generation the waveform generator uses the com0x1:0 bi ts differently in normal, ctc, and pwm modes. for all modes, setting the com0x1:0 = 0 tells the waveform generator that no action on the oc0x register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 6-46 on page 131 . for fast pwm mode, refer to table 6-47 on page 131 , and for phase correct pwm refer to table 6-48 on page 132 . a change of the com0x1:0 bits state will have effe ct at the first compare match after the bits are written. for non-pwm modes, the action can be forced to have immediate effect by using the foc0x strobe bits. 6.14.7 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm02:0) and compare output mode (com0x1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com0x1:0 bits control whether the pwm output generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the com0x1:0 bits control whether the output should be set, cleared, or tog- gled at a compare match ( see ?compare match output unit? on page 123. ). for detailed timing information refer to ?timer/counter timing diagrams? on page 129 . 6.14.7.1 normal mode the simplest mode of operation is the normal mode (wgm02:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 8-bit value (top = 0xff) and then restarts from the bot- tom (0x00). in normal operation the timer/counter overflow flag (tov0) will be set in the same timer clock cycle as the tcnt0 becomes zero . the tov0 flag in this case behaves like a ninth bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov0 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 125 9159a?auto?09/10 atmel ata6614 [preliminary] 6.14.7.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm02:0 = 2), the ocr0a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the coun- ter value (tcnt0) matches the ocr0a. the ocr0a defines the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output fre- quency. it also simplifies the operati on of counting external events. the timing diagram for the ctc mode is shown in figure 6-32 . the counter value (tcnt0) increases until a compare match occurs between tcnt0 and ocr0a, and then counter (tcnt0) is cleared. figure 6-32. ctc mode, timing diagram an interrupt can be generated each time the counter value reaches the top value by using the ocf0a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing top to a value close to bottom when the counter is running with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr0a is lower than the current value of tcnt0, the counter will miss the compare match. the counter will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. for generating a waveform output in ctc mode, the oc0a output can be set to toggle its log- ical level on each compare match by setting the compare output mode bits to toggle mode (com0a1:0 = 1). the oc0a value will not be visi ble on the port pin unless the data direction for the pin is set to output. the waveform generated will have a maximum frequency of f oc0 =f clk_i/o /2 when ocr0a is set to zero (0x00). the waveform frequency is defined by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tov0 flag is set in the same timer clock cycle that the counter counts from max to 0x00. tcntn ocn (toggle) ocnx interrupt flag set 1 4 period 2 3 (comnx1:0 = 1) f ocnx f clk_i/o 2 n 1 ocrnx + () ?? ------------------------------------------------------- = 126 9159a?auto?09/10 atmel ata6614 [preliminary] 6.14.7.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm02:0 = 3 or 7) provides a high fre- quency pwm waveform generation option. the fast pwm differs from the other pwm option by its single-slope operation. t he counter counts from bottom to top then restarts from bottom. top is defined as 0xff when wgm2:0 = 3, and ocr0a when wgm2:0 = 7. in non-inverting compare output mode, the output compare (oc0x) is cleared on the compare match between tcnt0 and ocr0x, and set at bottom. in inverting compare output mode, the output is set on compare match and cleared at bottom. due to the single-slope opera- tion, the operating frequency of the fast pwm mo de can be twice as high as the phase correct pwm mode that use dual-slope operation. th is high frequency makes the fast pwm mode well suited for power regulation, rectificat ion, and dac applications. high frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. in fast pwm mode, the counter is incremented until the counter value matches the top value. the counter is then cleared at the following ti mer clock cycle. the timing diagram for the fast pwm mode is shown in figure 6-33 . the tcnt0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt0 slopes represent com- pare matches between ocr0x and tcnt0. figure 6-33. fast pwm mode, timing diagram the timer/counter overflow flag (tov0) is se t each time the counter reaches top. if the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. in fast pwm mode, the compare unit allows generation of pwm waveforms on the oc0x pins. setting the com0x1:0 bits to two will produce a non-inverted pwm and an inverted pwm out- put can be generated by setting the com0x1:0 to three: setting the com0a1:0 bits to one allows the oc0a pin to toggle on compare matches if the wgm02 bit is set. this option is not available for the oc0b pin (see table 6-50 on page 132 ). the actual oc0x value will only be visible on the port pin if the data direction for the port pin is set as output. the pwm waveform is generated by setting (or clearing) the oc0x register at the compare match between ocr0x and tcnt0, and clearing (or setting) the oc0x register at the timer clock cycle the counter is cleared (changes from top to bottom). tcntn ocrnx update and tovn interrupt flag set 1 period 2 3 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx interrupt flag set 4 5 6 7 127 9159a?auto?09/10 atmel ata6614 [preliminary] the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a register represents special cases when generating a pwm waveform output in the fast pwm mode. if the ocr0a is set equal to bottom, the out- put will be a narrow spike for each max+1 time r clock cycle. setting th e ocr0a equal to max will result in a constantly high or low output (d epending on the polarity of the output set by the com0a1:0 bits.) a frequency (with 50% duty cycle) waveform output in fast pwm mode can be achieved by setting oc0x to toggle its logical level on each compare match (com0x1:0 = 1). the wave- form generated will have a maximum frequency of f oc0 = f clk_i/o /2 when ocr0a is set to zero. this feature is similar to the oc0a toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast pwm mode. 6.14.7.4 phase correct pwm mode the phase correct pwm mode (wgm02:0 = 1 or 5) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is based on a dual-slope operation. the counter counts repeatedly from bottom to top and then from top to bot- tom. top is defined as 0xff when wgm2:0 = 1, and ocr0a when wgm2:0 = 5. in non-inverting compare output mode, the output compare (oc0x) is cleared on the compare match between tcnt0 and ocr0x while upcounting, and set on the compare match while downcounting. in inverting output compare m ode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. in phase correct pwm mode the counter is incremented until the counter value matches top. when the counter reaches top, it changes th e count direction. the tcnt0 value will be equal to top for one timer clock cycle. the ti ming diagram for the phase correct pwm mode is shown on figure 6-34 . the tcnt0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the di agram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt0 slopes represent compare matches between ocr0x and tcnt0. f ocnxpwm f clk_i/o n 256 ? -------------------- - = 128 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-34. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bot- tom value. in phase correct pwm mode, the compare unit allows generation of pwm waveforms on the oc0x pins. setting the com0x1:0 bits to two will produce a non-inverted pwm. an inverted pwm output can be generated by setting the com0x1:0 to three: setting the com0a0 bits to one allows the oc0a pin to toggle on compare matches if the wgm02 bit is set. this option is not available for the oc0b pin (see table 6-51 on page 133 ). the actual oc0x value will only be visible on the port pin if the data direction for the port pin is set as output. the pwm wave- form is generated by clearing (or setting) the oc0x register at the compare match between ocr0x and tcnt0 when the counter increments, and setting (or clearing) the oc0x register at compare match between ocr0x and tcnt0 when the counter decrements. the pwm fre- quency for the output when using phase correct pwm can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr0a is set equal to bottom, the output will be continuously low an d if set equal to max the out put will be continuously high for non-inverted pwm mode. for in verted pwm the output will have the opposite logic values. at the very start of period 2 in figure 6-34 ocnx has a transition from high to low even though there is no compare match. the point of this transition is to guarantee symmetry around bot- tom. there are two cases that give a transition without compare match. tovn interrupt flag set ocnx interrupt flag set 1 2 3 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx update f ocnxpcpwm f clk_i/o n 510 ? -------------------- - = 129 9159a?auto?09/10 atmel ata6614 [preliminary] ? ocrnx changes its value from max, like in figure 6-34 . when the ocr0a value is max the ocn pin value is the same as the result of a down-counting compare match. to ensure symmetry around bottom the ocnx value at max must correspond to the result of an up-counting compare match. ? the timer starts counting from a value higher than the one in ocrnx, and for that reason misses the compare match and hence the ocnx change that would have happened on the way up. 6.14.8 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t0 ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set. figure 6-35 contains timing data for basic timer/counter operation. the figure shows the count sequence close to the max value in all modes other than phase correct pwm mode. figure 6-35. timer/counter timing diagram, no prescaling figure 6-36 shows the same timing data, but with the prescaler enabled. figure 6-36. timer/counter timing dia gram, with prescaler (f clk_i/o /8) figure 6-37 shows the setting of ocf0b in all modes and ocf0a in all modes except ctc mode and pwm mode, where ocr0a is top. clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) 130 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-37. timer/counter timing diagram, setting of ocf0x, with prescaler (f clk_i/o /8) figure 6-38 shows the setting of ocf0a and the clearing of tcnt0 in ctc mode and fast pwm mode where ocr0a is top. figure 6-38. timer/counter timing diagram, clear timer on compare match mode, with prescaler (f clk_i/o /8) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) 131 9159a?auto?09/10 atmel ata6614 [preliminary] 6.14.9 register description 6.14.9.1 tccr0a ? timer/counter control register a ? bits 7:6 ? com0a1:0: compare match output a mode these bits control the output compare pin (oc0a) behavior. if one or both of the com0a1:0 bits are set, the oc0a output overrides the normal port functionality of the i/o pin it is con- nected to. however, note that the data direction register (ddr) bit corresponding to the oc0a pin must be set in order to enable the output driver. when oc0a is connected to the pin, the func tion of the com0a1:0 bits depends on the wgm02:0 bit setting. table 6-46 shows the com0a1:0 bit functionality when the wgm02:0 bits are set to a normal or ctc mode (non-pwm). table 6-47 shows the com0a1:0 bit functionality when the wgm01:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at bottom. see ?fast pwm mode? on page 126 for more details. bit 7 6 5 4 3 210 0x24 (0x44) com0a1 com0a0 com0b1 com0b0 ? ? wgm01 wgm00 tccr0a read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 6-46. compare output mode, non-pwm mode com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 0 1 toggle oc0a on compare match 1 0 clear oc0a on compare match 1 1 set oc0a on compare match table 6-47. compare output mode, fast pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 01 wgm02 = 0: normal port operation, oc0a disconnected. wgm02 = 1: toggle oc0a on compare match. 10 clear oc0a on compare match, set oc0a at bottom, (non-inverting mode). 11 set oc0a on compare match, clear oc0a at bottom, (inverting mode). 132 9159a?auto?09/10 atmel ata6614 [preliminary] table 6-48 shows the com0a1:0 bit functionality when the wgm02:0 bits are set to phase correct pwm mode. note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 153 for more details. ? bits 5:4 ? com0b1:0: compare match output b mode these bits control the output compare pin (oc0b) behavior. if one or both of the com0b1:0 bits are set, the oc0b output overrides the normal port functionality of the i/o pin it is con- nected to. however, note that the data direction register (ddr) bit corresponding to the oc0b pin must be set in order to enable the output driver. when oc0b is connected to the pin, the func tion of the com0b1:0 bits depends on the wgm02:0 bit setting. table 6-49 shows the com0b1:0 bit functionality when the wgm02:0 bits are set to a normal or ctc mode (non-pwm). table 6-50 shows the com0b1:0 bit functionality when the wgm02:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr0b equals top and com0b1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 126 for more details. table 6-48. compare output mode, phase correct pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 01 wgm02 = 0: normal port o peration, oc0a disconnected. wgm02 = 1: toggle oc0a on compare match. 10 clear oc0a on compare match when up-counting. set oc0a on compare match when down-counting. 11 set oc0a on compare match when up-counting. clear oc0a on compare match when down-counting. table 6-49. compare output mode, non-pwm mode com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected. 0 1 toggle oc0b on compare match 1 0 clear oc0b on compare match 1 1 set oc0b on compare match table 6-50. compare output mode, fast pwm mode (1) com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected. 01reserved 10 clear oc0b on compare match, set oc0b at bottom, (non-inverting mode) 11 set oc0b on compare match, clear oc0b at bottom, (inverting mode). 133 9159a?auto?09/10 atmel ata6614 [preliminary] table 6-51 shows the com0b1:0 bit functionality when the wgm02:0 bits are set to phase correct pwm mode. note: 1. a special case occurs when ocr0b equals top and com0b1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 127 for more details. ? bits 3, 2 ? res: reserved bits these bits are reserved bits in the atmel ? atmega48pa/88pa/168pa/328p and will always read as zero. ? bits 1:0 ? wgm01:0: waveform generation mode combined with the wgm02 bit found in the t ccr0b register, these bits control the counting sequence of the counter, the source for maximum (top) counter value, and what type of waveform generation to be used, see table 6-52 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and two types of pulse width modulation (pwm) modes (see ?modes of operation? on page 124 ). notes: 1. max = 0xff 2. bottom = 0x00 table 6-51. compare output mode, phase correct pwm mode (1) com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected. 01reserved 10 clear oc0b on compare match when up-counting. set oc0b on compare match when down-counting. 11 set oc0b on compare match when up-counting. clear oc0b on compare match when down-counting. table 6-52. waveform generation mode bit description mode wgm02 wgm01 wgm00 timer/counte r mode of operation top update of ocrx at tov flag set on (1)(2) 0 0 0 0 normal 0xff immediate max 1001 pwm, phase correct 0xff top bottom 2 0 1 0 ctc ocra immediate max 3 0 1 1 fast pwm 0xff bottom max 4100reserved ? ? ? 5101 pwm, phase correct ocra top bottom 6110reserved ? ? ? 7111fast pwmocrabottomtop 134 9159a?auto?09/10 atmel ata6614 [preliminary] 6.14.9.2 tccr0b ? timer/counter control register b ? bit 7 ? foc0a: force output compare a the foc0a bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibi lity with future devices, this bit must be set to zero when tccr0b is written when operating in pwm mode. when writing a logical one to the foc0a bit, an immediate compare match is forced on the waveform generation unit. the oc0a out- put is changed according to its com0a1:0 bits setting. note that the foc0a bit is implemented as a strobe. therefore it is the value present in the com0a1:0 bits that deter- mines the effect of the forced compare. a foc0a strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr0a as top. the foc0a bit is always read as zero. ? bit 6 ? foc0b: force output compare b the foc0b bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibi lity with future devices, this bit must be set to zero when tccr0b is written when operating in pwm mode. when writing a logical one to the foc0b bit, an immediate compare match is forced on the waveform generation unit. the oc0b out- put is changed according to its com0b1:0 bits setting. note that the foc0b bit is implemented as a strobe. therefore it is the value present in the com0b1:0 bits that deter- mines the effect of the forced compare. a foc0b strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr0b as top. the foc0b bit is always read as zero. ? bits 5:4 ? res: reserved bits these bits are reserved bits in the atmel ? atmega48pa/88pa/168pa/328p and will always read as zero. ? bit 3 ? wgm02: waveform generation mode see the description in the ?tccr0a ? timer/counter control register a? on page 131 . ? bits 2:0 ? cs02:0: clock select the three clock select bits select the clock source to be used by the timer/counter. bit 7 6 5 4 3 2 1 0 0x25 (0x45) foc0a foc0b ? ? wgm02 cs02 cs01 cs00 tccr0b read/write w w r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 135 9159a?auto?09/10 atmel ata6614 [preliminary] if external pin modes are used for the timer/c ounter0, transitions on the t0 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 6.14.9.3 tcnt0 ? timer/counter register the timer/counter register gives direct access, both for read and write operations, to the timer/counter unit 8-bit counter. writing to t he tcnt0 register blocks (removes) the com- pare match on the following timer clock. modify ing the counter (tcnt0) while the counter is running, introduces a risk of missing a compare match between tcnt0 and the ocr0x registers. 6.14.9.4 ocr0a ? output compare register a the output compare register a contains an 8-bit value that is continuously compared with the counter value (tcnt0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0a pin. 6.14.9.5 ocr0b ? output compare register b the output compare register b contains an 8-bit value that is continuously compared with the counter value (tcnt0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0b pin. table 6-53. clock select bit description cs02 cs01 cs00 description 0 0 0 no clock source (timer/counter stopped) 001clk i/o /(no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on t0 pin. clock on falling edge. 1 1 1 external clock source on t0 pin. clock on rising edge. bit 76543210 0x26 (0x46) tcnt0[7:0] tcnt0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x27 (0x47) ocr0a[7:0] ocr0a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x28 (0x48) ocr0b[7:0] ocr0b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 136 9159a?auto?09/10 atmel ata6614 [preliminary] 6.14.9.6 timsk 0 ? timer/counter interrupt mask register ? bits 7..3 ? res: reserved bits these bits are reserved bits in the atmega48pa/88pa/168pa/328p and will always read as zero. ? bit 2 ? ocie0b: timer/counter output compare match b interrupt enable when the ocie0b bit is written to one, and the i-bit in the status register is set, the timer/counter compare match b interrupt is enab led. the corresponding interrupt is executed if a compare match in timer/counter occurs , i.e., when the ocf0b bit is set in the timer/counter interrupt flag register ? tifr0. ? bit 1 ? ocie0a: timer/counter0 output compare match a interrupt enable when the ocie0a bit is written to one, and the i-bit in the status register is set, the timer/counter0 compare match a interrupt is enabled. the corresponding interrupt is exe- cuted if a compare match in timer/counter0 occurs, i.e., when the ocf0a bit is set in the timer/counter 0 interrupt flag register ? tifr0. ? bit 0 ? toie0: timer/counter0 overflow interrupt enable when the toie0 bit is written to one, and the i-bit in the status register is set, the timer/counter0 overflow interrupt is enabled. the corresponding interrupt is executed if an overflow in timer/counter0 occurs, i.e., when th e tov0 bit is set in the timer/counter 0 inter- rupt flag register ? tifr0. 6.14.9.7 tifr 0 ? timer/counter 0 interrupt flag register ? bits 7..3 ? res: reserved bits these bits are reserved bits in the atmega48pa/88pa/168pa/328p and will always read as zero. ? bit 2 ? ocf0b: timer/counter 0 output compare b match flag the ocf0b bit is set when a compare match occurs between the timer/counter and the data in ocr0b ? output compare register0 b. ocf0b is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf0b is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie0b (timer/counter compare b match interrupt enable), and ocf0b are set, the timer/counter compare match interrupt is executed. bit 7 6 5 4 3 2 1 0 (0x6e) ?????ocie0bocie0atoie0timsk0 read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x15 (0x35) ?????ocf0bocf0atov0tifr0 read/write rrrrrr/wr/wr/w initial value00000000 137 9159a?auto?09/10 atmel ata6614 [preliminary] ? bit 1 ? ocf0a: timer/counter 0 output compare a match flag the ocf0a bit is set when a compare match occurs between the timer/counter0 and the data in ocr0a ? output compare register0. ocf0a is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf0a is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie0a (timer/counter0 compare match interrupt enable), and ocf0a are set, the timer/counter0 compare match interrupt is executed. ? bit 0 ? tov0: timer/counter0 overflow flag the bit tov0 is set when an overflow occurs in timer/counter0. tov0 is cleared by hardware when executing the corresponding interrupt hand ling vector. alternatively, tov0 is cleared by writing a logic one to the flag. when the sreg i-bit, toie0 (timer/counter0 overflow interrupt enable), and tov0 are set, the timer/counter0 overflow interrupt is executed. the setting of this flag is dependent of the wgm02:0 bit setting. refer to table 6-52 , ?wave- form generation mode bit description? on page 133 138 9159a?auto?09/10 atmel ata6614 [preliminary] 6.15 16-bit timer/counter1 with pwm 6.15.1 features ? true 16-bit design (i.e., allows 16-bit pwm) ? two independent output compare units ? double buffered outp ut compare registers ? one input capture unit ? input capture noise canceler ? clear timer on compare match (auto reload) ? glitch-free, phase correct pu lse width modulator (pwm) ? variable pwm period ? frequency generator ? external event counter ? four independent interrupt sources (tov1, ocf1a, ocf1b, and icf1) 6.15.2 overview the 16-bit timer/counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. most register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, and a lower case ?x? replaces the output compare unit channel. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt1 for accessing timer/counter1 counter value and so on. a simplified block diagram of the 16-bit timer/counter is shown in figure 6-39 . the device-specific i/o register and bit locations are listed in the ?register description? on page 160 . the prtim1 bit in ?prr ? power reduction register? on page 70 must be written to zero to enable timer/counter1 module. 139 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-39. 16-bit timer/counter block diagram (1) note: 1. refer to table 6-36 on page 108 and table 6-42 on page 114 for timer/counter1 pin placement and description. 6.15.2.1 registers the timer/counter (tcnt1), output compare registers (ocr1a/b), and input capture reg- ister (icr1) are all 16-bit registers. special pr ocedures must be followed when accessing the 16-bit registers. these procedures are described in the section ?accessing 16-bit registers? on page 140 . the timer/counter control registers (tccr1a/b) are 8-bit registers and have no cpu access restrictions. interrupt requests (abbreviated to int.req. in the figure) signals are all visible in the timer interrupt flag register (tifr1). all interr upts are individually masked with the timer interrupt mask register (timsk1). tifr1 and timsk1 are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the t1 pin. the clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t 1 ). clock select timer/counter data b u s ocrna ocrnb icrn = = tcntn waveform generation waveform generation ocna ocnb noise canceler icpn = fixed top values edge detector control logic = 0 top bottom count clear direction tovn (int.req.) ocna (int.req.) ocnb (int.req.) icfn (int.req.) tccrna tccrnb ( from analog comparator ouput ) tn edge detector ( from prescaler ) clk tn 140 9159a?auto?09/10 atmel ata6614 [preliminary] the double buffered output compare registers (ocr1a/b) are compared with the timer/counter value at all time. the result of the compare can be used by the waveform gen- erator to generate a pwm or variable frequency output on the output compare pin (oc1a/b). see ?output compare units? on page 147 . the compare match even t will also set the com- pare match flag (ocf1a/b) which can be used to generate an output compare interrupt request. the input capture register can capture the ti mer/counter value at a given external (edge triggered) event on either the input capture pin (icp1) or on the analog comparator pins (see ?analog comparator? on page 271 ) the input capture unit includes a digital filtering unit (noise canceler) for reducing the chance of capturing noise spikes. the top value, or maximum timer/counter value, can in some modes of operation be defined by either the ocr1a register, the icr1 register, or by a set of fixed values. when using ocr1a as top value in a pwm mode, the ocr1a register can not be used for gener- ating a pwm output. however, the top value will in this case be double buffered allowing the top value to be changed in run time. if a fixed top value is required, the icr1 register can be used as an alternative, freeing the ocr1a to be used as pwm output. 6.15.2.2 definitions the following definitions are used extensively throughout the section: 6.15.3 accessing 16-bit registers the tcnt1, ocr1a/b, and icr1 are 16-bit registers that can be accessed by the avr cpu via the 8-bit data bus. the 16-bit register must be byte accessed using two read or write oper- ations. each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. the same temporary register is shared between all 16-bit registers within each 16-bit timer. accessing the low byte triggers the 16-bit read or write operation. when the low byte of a 16-bit register is written by the cpu, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. when the low byte of a 16-bit register is read by the cpu, the high byte of the 16-bit register is cop- ied into the temporary register in the same clock cycle as the low byte is read. not all 16-bit accesses uses the temporary register for the high byte. reading the ocr1a/b 16-bit registers does not involve using the temporary register. to do a 16-bit write, the high byte must be written before the low byte. for a 16-bit read, the low byte must be read before the high byte. the following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. the same principle can be used directly for access- ing the ocr1a/b and icr1 registers. note t hat when using ?c?, the compiler handles the 16-bit access. bottom the counter reaches the bottom when it becomes 0x0000. max the counter reaches its max imum when it becomes 0xffff (decimal 65535). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be one of the fixed values: 0x00ff, 0x01ff, or 0x03ff, or to the value stored in the ocr1a or icr1 register. the assign- ment is dependent of th e mode of operation. 141 9159a?auto?09/10 atmel ata6614 [preliminary] note: 1. see ?about code examples? on page 33. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructi ons that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example returns the tcnt1 value in the r17:r16 register pair. it is important to notice that accessing 16-bit registers are atomic operations. if an interrupt occurs between the two instructions accessi ng the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer regis- ters, then the result of the ac cess outside the interr upt will be corrupted. therefore, when both the main code and the interrupt code update the temporary register, the main code must dis- able the interrupts during the 16-bit access. the following code examples show how to do an atomic read of the tcnt1 register contents. reading any of the ocr1a/b or icr1 registers can be done by using the same principle. assembly code examples (1) ... ; set tcnt 1 to 0x01ff ldi r17,0x01 ldi r16,0xff out tcnt 1 h,r17 out tcnt 1 l,r16 ; read tcnt 1 into r17:r16 in r16,tcnt 1 l in r17,tcnt 1 h ... c code examples (1) unsigned int i; ... /* set tcnt 1 to 0x01ff */ tcnt 1 = 0x1ff; /* read tcnt 1 into i */ i = tcnt 1 ; ... 142 9159a?auto?09/10 atmel ata6614 [preliminary] note: 1. see ?about code examples? on page 33. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructi ons that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example returns the tcnt1 value in the r17:r16 register pair. the following code examples show how to do an atomic write of the tcnt1 register contents. writing any of the ocr1a/b or icr1 register s can be done by using the same principle. assembly code example (1) tim16_readtcnt 1 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcnt 1 into r17:r16 in r16,tcnt 1 l in r17,tcnt 1 h ; restore global interrupt flag out sreg,r18 ret c code example (1) unsigned int tim16_readtcnt 1 ( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* read tcnt 1 into i */ i = tcnt 1 ; /* restore global interrupt flag */ sreg = sreg; return i; } 143 9159a?auto?09/10 atmel ata6614 [preliminary] note: 1. see ?about code examples? on page 33. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructi ons that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example requires that the r17:r16 register pair contains the value to be written to tcnt1. 6.15.3.1 reusing the temporary high byte register if writing to more than one 16-bit register where the high byte is the same for all registers writ- ten, then the high byte only needs to be written once. however, note that the same rule of atomic operation described previously also applies in this case. 6.15.4 timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic which is controlled by the clock select (cs12:0) bits located in the timer/counter control register b (tccr1b). for detail s on clock sources and prescaler, see ?timer/counter0 and timer/counter1 prescalers? on page 167 . assembly code example (1) tim16_writetcnt 1 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcnt 1 to r17:r16 out tcnt 1 h,r17 out tcnt 1 l,r16 ; restore global interrupt flag out sreg,r18 ret c code example (1) void tim16_writetcnt 1 ( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* set tcnt 1 to i */ tcnt 1 = i; /* restore global interrupt flag */ sreg = sreg; } 144 9159a?auto?09/10 atmel ata6614 [preliminary] 6.15.5 counter unit the main part of the 16-bit timer/counter is the programmable 16-bit bi-directional counter unit. figure 6-40 shows a block diagram of the counter and its surroundings. figure 6-40. counter unit block diagram signal description (internal signals): count increment or decrement tcnt1 by 1. direction select between increment and decrement. clear clear tcnt1 (set all bits to zero). clk t 1 timer/counter clock. top signalize that tcnt1 has reached maximum value. bottom signalize that tcnt1 has re ached minimum value (zero). the 16-bit counter is mapped into two 8-bit i/o memory locations: counter high (tcnt1h) containing the upper eight bits of the counter, and counter low (tcnt1l) containing the lower eight bits. the tcnt1h register can only be indirectly accessed by the cpu. when the cpu does an access to the tcnt1h i/o location, t he cpu accesses the high byte temporary regis- ter (temp). the temporary register is updated with the tcnt1h value when the tcnt1l is read, and tcnt1h is updated with the temporary register value when tcnt1l is written. this allows the cpu to read or write the entire 16 -bit counter value within one clock cycle via the 8-bit data bus. it is important to notice that there are special cases of writing to the tcnt1 register when the counter is counting that will give unpredictable resu lts. the special cases are described in the sections where they are of importance. depending on the mode of operation used, the counter is cleared, incremented, or decre- mented at each timer clock (clk t 1 ). the clk t 1 can be generated from an external or internal clock source, selected by the clock select bits (cs12:0). when no clock source is selected (cs12:0 = 0) the timer is stopped. however, the tcnt1 value can be accessed by the cpu, independent of whether clk t 1 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the waveform generation mode bits (wgm13:0) located in the timer/counter control registers a and b (tccr1a and tccr1b). there are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs oc1x. for more details about advanced count- ing sequences and waveform generation, see ?modes of operation? on page 150 . temp (8-bit) data bus (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) control logic count clear direction tovn (int.req.) clock select top bottom tn edge detector ( from prescaler ) clk tn 145 9159a?auto?09/10 atmel ata6614 [preliminary] the timer/counter overflow flag (tov1) is set according to the mode of operation selected by the wgm13:0 bits. tov1 can be used for generating a cpu interrupt. 6.15.6 input capture unit the timer/counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence. the external signal indicating an event, or multiple events, can be applied via the icp1 pin or alternatively, via the analog-comparator unit. the time-stamps can then be used to ca lculate frequency, duty-cycle, and other features of the signal applied. alternatively the time-stamps can be used for creating a log of the events. the input capture unit is illustrated by the block diagram shown in figure 6-41 . the elements of the block diagram that are not directly a part of the input capture unit are gray shaded. the small ?n? in register and bit names indicates the timer/counter number. figure 6-41. input capture unit block diagram when a change of the logic level (an event) occurs on the input capture pin (icp1), alterna- tively on the analog comparator output (aco), and this change confirms to the setting of the edge detector, a capture will be tr iggered. when a captur e is triggered, the 16-bit value of the counter (tcnt1) is written to the input capture register (icr1). the input capture flag (icf1) is set at the same system clock as th e tcnt1 value is copied into icr1 register. if enabled (icie1 = 1), the input capture flag generates an input capture interrupt. the icf1 flag is automatically cleared when the interrupt is executed. alternatively the icf1 flag can be cleared by software by writing a logical one to its i/o bit location. reading the 16-bit value in the input capture register (icr1) is done by first reading the low byte (icr1l) and then the high byte (icr1h). when the low byte is read the high byte is cop- ied into the high byte temporary register (temp). when the cpu reads the icr1h i/o location it will access the temp register. icfn (int.req.) analog comparator write icrn (16-bit register) icrnh (8-bit) noise canceler icpn edge detector temp (8-bit) data bus (8-bit) icrnl (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) acic* icnc ices aco* 146 9159a?auto?09/10 atmel ata6614 [preliminary] the icr1 register can only be written when using a waveform generat ion mode that utilizes the icr1 register for defining the counter?s top value. in these cases the waveform genera- tion mode (wgm13:0) bits must be set before the top value can be written to the icr1 register. when writing the icr1 register the high byte must be written to the icr1h i/o loca- tion before the low byte is written to icr1l. for more information on how to access the 16-bit registers refer to ?accessing 16-bit regis- ters? on page 140 . 6.15.6.1 input capture trigger source the main trigger source for the input capture unit is the input capture pin (icp1). timer/counter1 can alternatively use the analog comparator output as trigger source for the input capture unit. the analog comparator is selected as trigger source by setting the analog comparator input capture (acic) bit in the analog comparator control and status register (acsr). be aware that changing trigger source can trigger a capture. the input capture flag must therefore be cleared after the change. both the input capture pin (icp1) and the analog comparator output (aco) inputs are sam- pled using the same technique as for the t1 pin ( figure 6-52 on page 167 ). the edge detector is also identical. however, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. note that the input of the noise canceler and edge detector is always enabled unless the timer/counter is set in a waveform generation mode that uses icr1 to define top. an input capture can be triggered by softwar e by controlling the port of the icp1 pin. 6.15.6.2 noise canceler the noise canceler improves noise immunity by using a simple digital filtering scheme. the noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. the noise canceler is enabled by setting the input capture noise canceler (icnc1) bit in timer/counter control register b (tccr1b). when enabled the noise canceler introduces additional four system clock cycles of delay fr om a change applied to the input, to the update of the icr1 register. the noise canceler uses the system clock and is therefore not affected by the prescaler. 6.15.6.3 using the input capture unit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time betwee n two events is critical. if the processor has not read the captured value in the icr1 regist er before the next ev ent occurs, the icr1 will be overwritten with a new valu e. in this case the result of the capture will be incorrect. when using the input capture interrupt, the icr1 register should be read as early in the inter- rupt handler routine as possible. even though t he input capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. using the input capture unit in any mode of operation when the top value (resolution) is actively changed during operation, is not re commended. measurement of an external signal?s duty cycle requires that the trigger edge is changed after each capture. changing the edge sensing must be done as early as possible after the icr1 register has been read. 147 9159a?auto?09/10 atmel ata6614 [preliminary] after a change of the edge, the input capture flag (icf1) must be cleared by software (writing a logical one to the i/o bit location). for measuring frequency only, the clearing of the icf1 flag is not required (if an interrupt handler is used). 6.15.7 output compare units the 16-bit comparator continuously compares tcnt1 with the output compare register (ocr1x). if tcnt equals ocr1x the compar ator signals a match. a match will set the output compare flag (ocf1x) at the next timer clock cycle . if enabled (ocie1x = 1), the output compare flag generates an output compare interrupt. the ocf1x flag is automatically cleared when the interrupt is executed. alternatively the ocf1x flag can be cleared by soft- ware by writing a logical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to operating mode set by the waveform generation mode (wgm13:0) bits and compare output mode (com1x1:0) bits. the top and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation ( see ?modes of operation? on page 150. ) a special feature of output compare unit a allows it to define the timer/counter top value (i.e., counter resolution). in addition to the counter resolution, the top value defines the period time for waveforms generated by the waveform generator. figure 6-42 shows a block diagram of the output compare unit. the small ?n? in the register and bit names indicates the device number (n = 1 for timer/counter 1), and the ?x? indicates output compare unit (a/b). the elements of the block diagram that are not directly a part of the output compare unit are gray shaded. figure 6-42. output compare unit, block diagram the ocr1x register is double buffered when using any of the twelve pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double bufferi ng synchronizes the update of the ocr1x compare register to either top or bottom of the counting sequence. ocfnx (int.req.) = (16-bit comparator ) ocrnx buffer (16-bit register) ocrnxh buf. (8-bit) ocnx temp (8-bit) data bus (8-bit) ocrnxl buf. (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) comnx1:0 wgmn3:0 ocrnx (16-bit register) ocrnxh (8-bit) ocrnxl (8-bit) waveform generator top bottom 148 9159a?auto?09/10 atmel ata6614 [preliminary] the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr1x register access may seem complex, but this is not case. when the double buffer- ing is enabled, the cpu has access to the ocr1x buffer register, and if double buffering is disabled the cpu will access the ocr1x direct ly. the content of the ocr1x (buffer or com- pare) register is only changed by a write operation (the timer/counter does not update this register automatically as the tcnt1 and icr1 register). therefore ocr1x is not read via the high byte temporary register (temp). however, it is a good practice to read the low byte first as when accessing other 16-bit registers. wr iting the ocr1x registers must be done via the temp register since the compare of all 16 bits is done continuously. the high byte (ocr1xh) has to be written first. when the high byte i/o lo cation is written by the cpu, the temp regis- ter will be updated by the value written. then w hen the low byte (ocr1xl) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of ei ther the o cr1x buffer or ocr1x compare register in the same system clock cycle. for more information of how to access the 16-bit registers refer to ?accessing 16-bit registers? on page 140 . 6.15.7.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (foc1x) bit. forcing compare match will not set the ocf1x flag or reload/clear the timer, but the oc1x pin will be updated as if a real com- pare match had occurred (the com11:0 bits se ttings define whether the oc1x pin is set, cleared or toggled). 6.15.7.2 compare match blocking by tcnt1 write all cpu writes to the tcnt1 register will blo ck any compare match that occurs in the next timer clock cycle, even when the timer is stopped . this feature allows ocr1x to be initialized to the same value as tcnt1 without triggering an interrupt when the timer/counter clock is enabled. 6.15.7.3 using the output compare unit since writing tcnt1 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing tcnt1 when using any of the output compare channels, independent of whether the timer/counter is running or not. if the value written to tcnt1 equals the ocr1x value, the compare match will be missed, resulting in incorrect waveform generation. do not write the tcnt1 equal to top in pwm modes with variable top values. the compare match for th e top will be ignored a nd the counter will con- tinue to 0xffff. similarly, do not write the tcnt1 value equal to bottom when the counter is downcounting. the setup of the oc1x should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc1x value is to use the force output com- pare (foc1x) strobe bits in normal mode. the oc1x register keeps its value even when changing between waveform generation modes. be aware that the com1x1:0 bits are not double buffered together with the compare value. changing the com1x1:0 bits will take effect immediately. 149 9159a?auto?09/10 atmel ata6614 [preliminary] 6.15.8 compare match output unit the compare output mode (com1x1:0) bits have two functions. the waveform generator uses the com1x1:0 bits for defining the output compare (oc1x) state at the next compare match. secondly the com1x1:0 bits control the oc1x pin output source. figure 6-43 shows a simplified schematic of the logic affected by t he com1x1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the com1x1:0 bits are shown. when referring to the oc1x state, the reference is for the inte rnal oc1x register, not the oc1x pin. if a sys- tem reset occur, the oc1x register is reset to ?0?. figure 6-43. compare match output unit, schematic the general i/o port function is overridden by the output compare (oc1x) from the waveform generator if either of the com1x1:0 bits are set. however, the oc1x pin direction (input or output) is still co ntrolled by the data direction register (ddr) for the port pin. the data direc- tion register bit for the oc1x pin (ddr_oc1x) must be set as output before the oc1x value is visible on the pin. the port override function is generally independent of the waveform gener- ation mode, but there are some exceptions. refer to table 6-54 , table 6-55 and table 6-56 for details. the design of the output compare pin logic allows initialization of the oc1x state before the output is enabled. note that some com1x1:0 bit settings are reserved for certain modes of operation. see ?register description? on page 160. the com1x1:0 bits have no effect on the input capture unit. port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data b u s focnx clk i/o 150 9159a?auto?09/10 atmel ata6614 [preliminary] 6.15.8.1 compare output mode and waveform generation the waveform generator uses the com1x1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the com1x1:0 = 0 tells the waveform generator that no action on the oc1x register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 6-54 on page 160 . for fast pwm mode refer to table 6-55 on page 160 , and for phase correct and phase and frequency correct pwm refer to table 6-56 on page 161 . a change of the com1x1:0 bits state will have effe ct at the first compare match after the bits are written. for non-pwm modes, the action can be forced to have immediate effect by using the foc1x strobe bits. 6.15.9 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm13:0) and compare output mode (com1x1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com1x1:0 bits control whether the pwm output generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the com1x1:0 bits control whether the output should be set, cleared or tog- gle at a compare match ( see ?compare match output unit? on page 149. ) for detailed timing information refer to ?timer/counter timing diagrams? on page 157 . 6.15.9.1 normal mode the simplest mode of operation is the normal mode (wgm13:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 16-bit valu e (max = 0xffff) and then restarts from the bottom (0x0000). in normal operation the timer/counter overflow flag (tov1) will be set in the same timer clock cycle as the tcnt1 become s zero. the tov1 flag in this case behaves like a 17th bit, except that it is only set, not cleared. however, combined with the timer over- flow interrupt that automatically clears the tov1 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the input capture unit is easy to use in normal mode. however, observe that the maximum interval between the external events must not exceed the resolution of the counter. if the inter- val between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. the output compare units can be used to generate interrupts at some given time. using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 6.15.9.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm13:0 = 4 or 12), the ocr1a or icr1 register are used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt1) matches either the ocr1a (wgm13:0 = 4) or the icr1 (wgm13:0 = 12). the ocr1a or icr1 define the top value for the counter, hence also its res- olution. this mode allows greater control of the compare match output frequency. it also simplifies the operation of counting external events. 151 9159a?auto?09/10 atmel ata6614 [preliminary] the timing diagram for the ctc mode is shown in figure 6-44 . the counter value (tcnt1) increases until a compare match occurs with either ocr1a or icr1, and then counter (tcnt1) is cleared. figure 6-44. ctc mode, timing diagram an interrupt can be generated at each time the counter value reaches the top value by either using the ocf1a or icf1 flag according to the register used to define the top value. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing the top to a value close to bottom when the counter is running with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr1a or icr1 is lower than the current value of tcnt1, the counter will miss the compar e match. the counter will then have to count to its maximum value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. in many cases this feature is not desirable. an alternative will then be to use the fast pwm mode using ocr1a for defining top (wgm13:0 = 15) since the ocr1a then will be double buffered. for generating a waveform output in ctc mode, the oc1a output can be set to toggle its log- ical level on each compare match by setting the compare output mode bits to toggle mode (com1a1:0 = 1). the oc1a value will not be visi ble on the port pin unless the data direction for the pin is set to output (ddr_oc1a = 1) . the waveform genera ted will have a maximum frequency of f oc 1 a = f clk_i/o /2 when ocr1a is set to zero (0x0000). the waveform frequency is defined by the following equation: the n variable represents the prescaler factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tov1 flag is set in the same timer clock cycle that the counter counts from max to 0x0000. 6.15.9.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm13:0 = 5, 6, 7, 14, or 15) provides a high frequency pwm waveform generation option. the fast pwm differs from the other pwm options by its single-slope operation. the counter counts from bottom to top then restarts from bottom. in non-inverting compare output mode, the output compare (oc1x) is cleared on the compare match between tcnt1 and ocr1x, and set at bottom. in inverting compare output mode output is set on compare match and cleared at bottom. tcntn ocna (toggle) ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 4 period 2 3 (comna1:0 = 1) f ocna f clk_i/o 2 n 1 ocrna + () ?? -------------------------------------------------------- = 152 9159a?auto?09/10 atmel ata6614 [preliminary] due to the single-slope operation, the operating frequency of the fast pwm mode can be twice as high as the phase correct and phase an d frequency correct pwm modes that use dual-slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and dac applications . high frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. the pwm resolution for fast pwm can be fixed to 8-, 9-, or 10-bit, or defined by either icr1 or ocr1a. the minimum resolution allowed is 2- bit (icr1 or ocr1a set to 0x0003), and the maximum resolution is 16-bit (i cr1 or ocr1a set to max). the pwm resolution in bits can be calculated by using the following equation: in fast pwm mode the counter is incremented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgm13:0 = 5, 6, or 7), the value in icr1 (wgm13:0 = 14), or the value in ocr1a (wgm13:0 = 15). the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 6-45 . the figure shows fast pwm mode when ocr1a or icr1 is used to define top. the tcnt1 value is in the timing diagram shown as a histogram for illustra ting the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt1 slopes represent compare matches between ocr1x and tcnt1. the oc1x interrup t flag will be set when a compare match occurs. figure 6-45. fast pwm mode, timing diagram the timer/counter overflow flag (tov1) is se t each time the counter reaches top. in addi- tion the oc1a or icf1 flag is set at the same timer clock cycle as tov1 is set when either ocr1a or icr1 is used for de fining the top value. if one of the interrupts are enabled, the interrupt handler routine can be used for updating the top and compare values. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will nev er occur between the tcnt1 and the ocr1x. note that when using fixed top values the unused bits are masked to zero when any of the ocr1x registers are written. r fpwm top 1 + () log 2 () log ---------------------------------- - = tcntn ocrnx/top update and tovn interrupt flag set and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 7 period 2 3 4 5 6 8 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 153 9159a?auto?09/10 atmel ata6614 [preliminary] the procedure for updating icr1 differs from updating ocr1a when used for defining the top value. the icr1 register is not double buffered. this means that if icr1 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new icr1 value written is lower than the current value of tcnt1. the result will then be that the counter will miss the compare match at the top value. the counter will then have to count to the max value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. the ocr1a register however, is double buffered. this feature allows the ocr1a i/o location to be written anytime. when the ocr1a i/o location is written the value written will be put into the ocr1a buffer re gister. the ocr1a compar e register will then be updated with the value in the buffer register at the next timer clock cycle the tcnt1 matches top. the update is done at the same timer clock cycle as the tcnt1 is cleared and the tov1 flag is set. using the icr1 register for defining top work s well when using fixed top values. by using icr1, the ocr1a register is free to be used for generating a pwm output on oc1a. how- ever, if the base pwm frequency is actively changed (by changing the top value), using the ocr1a as top is clearly a better choice due to its double buffer feature. in fast pwm mode, the compare units allow generation of pwm waveforms on the oc1x pins. setting the com1x1:0 bits to two will produc e a inverted pwm and an non-inverted pwm out- put can be generated by setting the com1x1:0 to three (see table on page 160 ). the actual oc1x value will only be visible on the port pin if the data direction for the port pin is set as out- put (ddr_oc1x). the pwm waveform is generated by setting (or clearing) the oc1x register at the compare match between ocr1x and tcnt1, and clearing (or setting) the oc1x regis- ter at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr1x register represents special cases when generating a pwm waveform output in the fast pwm mode. if the ocr1x is set equal to bottom (0x0000) the output will be a narrow spike for each top+1 timer clock cycle. setting the ocr1x equal to top will result in a constant high or low output (d epending on the polar ity of the output set by the com1x1:0 bits.) a frequency (with 50% duty cycle) waveform output in fast pwm mode can be achieved by setting oc1a to toggle its logical level on each compare match (com1a1:0 = 1). this applies only if ocr1a is used to define the top va lue (wgm13:0 = 15). t he waveform generated will have a maximum frequency of f oc 1 a = f clk_i/o /2 when ocr1a is set to zero (0x0000). this fea- ture is similar to the oc1a toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast pwm mode. 6.15.9.4 phase correct pwm mode the phase correct pulse width modulation or phase correct pwm mode (wgm13:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is, like the phase and frequency correct pwm mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting compare output mode, the output compare (oc1x) is cleared on the compare match between tcnt1 and ocr1x while upcounting, and set on the compare match while downcounting. f ocnxpwm f clk_i/o n 1 top + () ? ------------------------------------- = 154 9159a?auto?09/10 atmel ata6614 [preliminary] in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the sym- metric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the pwm resolution for the phase correct pwm mode can be fixed to 8-, 9-, or 10-bit, or defined by either icr1 or ocr1a. the minimum resolution allowed is 2-bit (icr1 or ocr1a set to 0x0003), and the maximum resolution is 16-bit (icr1 or ocr1a set to max). the pwm resolution in bits can be calculated by using the following equation: in phase correct pwm mode the counter is incremented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgm13:0 = 1, 2, or 3), the value in icr1 (wgm13:0 = 10), or the value in ocr1a (wgm13:0 = 11). the counter has then reached the top and changes the count direction. the tcnt1 value will be equal to top for one timer clock cycle. the timing diagram for th e phase correct pwm mode is shown on figure 6-46 . the figure shows phase correct pwm mode when ocr1a or icr1 is used to define top. the tcnt1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt1 slopes represent compare matches between ocr1x and tcnt1. the oc1x interrup t flag will be set when a compare match occurs. figure 6-46. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov1) is set each time the counter reaches bottom. when either ocr1a or icr1 is used for defining the top value, the oc1a or icf1 flag is set accordingly at the same timer clock cycle as the ocr1x registers are updated with the dou- ble buffer value (at top). the interrupt flags can be used to generate an interrupt each time the counter reaches the top or bottom value. r pcpwm top 1 + () log 2 () log ---------------------------------- - = ocrnx/top update and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tovn interrupt flag set (interrupt on bottom) tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 155 9159a?auto?09/10 atmel ata6614 [preliminary] when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will nev er occur between the tcnt1 and the ocr1x. note that when using fixed top values, the unus ed bits are masked to zero when any of the ocr1x registers are written. as the third period shown in figure 6-46 illustrates, changing the top actively while the timer/counter is running in the phase correct mode can result in an unsymmetrical output. the reason for this can be found in the time of update of the ocr1x register. since the ocr1x update occurs at top, the pwm period starts and ends at top. this implies that the length of the falling slope is determined by the previous top value, while the length of the rising slope is determined by the new top value. when these two values dif- fer the two slopes of the peri od will differ in length. the di fference in length gives the unsymmetrical result on the output. it is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the top value while the ti mer/counter is running. when using a static top value there are practically no differences between the two modes of operation. in phase correct pwm mode, the compare units allow generation of pwm waveforms on the oc1x pins. setting the com1x1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the com1x1:0 to three (see table on page 161 ). the actual oc1x value will only be visible on th e port pin if the data direction for the port pin is set as output (ddr_oc1x). the pwm wavefo rm is generated by setting (or clearing) the oc1x register at the compare match between ocr1x and tcnt1 when the counter incre- ments, and clearing (or setting) the oc1x register at compare match between ocr1x and tcnt1 when the counter decrements. the pwm frequency for the output when using phase correct pwm can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr1x register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr1x is set equal to bottom the output will be continuously low and if set equal to top the ou tput will be continuously high for non-inverted pwm mode. for inverted pwm the output will have the opposite logic values. if ocr1a is used to define the top value (wgm13:0 = 11) and com1a1:0 = 1, the oc1a out- put will toggle with a 50% duty cycle. 6.15.9.5 phase and frequency correct pwm mode the phase and frequency correct pulse width modulation, or phase and frequency correct pwm mode (wgm13:0 = 8 or 9) provides a high resolution phase and frequency correct pwm waveform generation option. the phase and frequency correct pwm mode is, like the phase correct pwm mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting compare output mode, the output compare (oc1x) is cleared on the compare match between tcnt1 and ocr1x while upcounting, and set on the compare match while downcounting. in inverting compare output mode, the operation is inverted. the dual-slope operation gives a lower max- imum operation frequency compared to the single-slope operation. however, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. f ocnxpcpwm f clk_i/o 2 ntop ?? --------------------------------- = 156 9159a?auto?09/10 atmel ata6614 [preliminary] the main difference between the phase corr ect, and the phase and frequency correct pwm mode is the time the ocr1x register is updated by the ocr1x buffer register, (see figure 6-46 and figure 6-47 ). the pwm resolution for the phase and frequency correct pwm mode can be defined by either icr1 or ocr1a. the minimum resolution allowed is 2-bit (icr1 or ocr1a set to 0x0003), and the maximum resolution is 16-bit (icr1 or ocr1a set to max). the pwm resolution in bits can be calculated using the following equation: in phase and frequency correct pwm mode the counter is incremented until the counter value matches either the value in icr1 (wgm13:0 = 8), or the value in ocr1a (wgm13:0 = 9). the counter has then re ached the top and change s the count direction. the tcnt1 value will be equal to top for one timer clock cycle. the timing diagram for the phase correct and fre- quency correct pwm mode is shown on figure 6-47 . the figure shows phase and frequency correct pwm mode when ocr1a or icr1 is used to define top. the tcnt1 value is in the timing diagram shown as a hist ogram for illustrating the dual-s lope operation. the diagram includes non-inverted and inverted pwm output s. the small horizontal line marks on the tcnt1 slopes represent compare matches between ocr1x and tcnt1. the oc1x interrupt flag will be set when a compare match occurs. figure 6-47. phase and frequency correct pwm mode, timing diagram the timer/counter overflow flag (tov1) is set at the same timer clock cycle as the ocr1x registers are updated with the double buffer value (at bottom). when either ocr1a or icr1 is used for defining the top value, the oc1a or icf1 flag set when tcnt1 has reached top. the interrupt flags can then be used to generate an interrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will neve r occur between the tcnt1 and the ocr1x. r pfcpwm top 1 + () log 2 () log ---------------------------------- - = ocrnx/top updateand tovn interrupt flag set (interrupt on bottom) ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 157 9159a?auto?09/10 atmel ata6614 [preliminary] as figure 6-47 shows the output generated is, in contrast to the phase correct mode, symmet- rical in all periods. since the ocr1x registers are updated at bottom, the length of the rising and the falling slopes will always be equal. this gives symme trical output pulses and is therefore frequency correct. using the icr1 register for defining top work s well when using fixed top values. by using icr1, the ocr1a register is free to be used for generating a pwm output on oc1a. how- ever, if the base pwm frequency is actively changed by changing the top value, using the ocr1a as top is clearly a better choice due to its double buffer feature. in phase and frequency correct pwm mode, the compare units allow generation of pwm waveforms on the oc1x pins. setting the com1x1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the com1x1:0 to three (see table on page 161 ). the actual oc1x value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_oc1x). the pwm waveform is generated by setting (or clearing) the oc1x register at the compare match between ocr1x and tcnt1 when the counter increments, and clearing (or setting) the oc1x register at compare match between ocr1x and tcnt1 when the counter decrements. the pwm frequency for the out- put when using phase and frequency correct pw m can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr1x register represents special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr1x is set equal to bot- tom the output will be cont inuously low and if set equal to to p the output will be set to high for non-inverted pwm mode. for inverted pwm the output will have the opposite logic values. if ocr1a is used to define the top value (wgm13:0 = 9) and com1a1:0 = 1, the oc1a out- put will toggle with a 50% duty cycle. 6.15.10 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t1 ) is therefore shown as a clock enable signal in the follow ing figures. the figures include information on when interrupt flags are set, and when the ocr1x register is updated with the ocr1x buffer value (only for modes utilizing double buffering). figure 6-48 shows a timing diagram for the setting of ocf1x. f ocnxpfcpwm f clk_i/o 2 ntop ?? --------------------------------- = 158 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-48. timer/counter timing diagram, setting of ocf1x, no prescaling figure 6-49 shows the same timing data, but with the prescaler enabled. figure 6-49. timer/counter timing diagram, setting of ocf1x, with prescaler (f clk_i/o /8) figure 6-50 shows the count sequence close to to p in various modes. when using phase and frequency correct pwm mode the ocr1x register is updated at bottom. the timing diagrams will be the same, but top should be replaced by bottom, top-1 by bottom+1 and so on. the same renaming applies for modes that set the tov1 flag at bottom. clk tn (clk i/o /1) ocfnx clk i/o ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) 159 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-50. timer/counter timing diagram, no prescaling figure 6-51 shows the same timing data, but with the prescaler enabled. figure 6-51. timer/counter timing dia gram, with prescaler (f clk_i/o /8) tovn (fpwm) and icfn (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk tn (clk i/o /1) clk i/o tovn (fpwm) and icf n (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) 160 9159a?auto?09/10 atmel ata6614 [preliminary] 6.15.11 register description 6.15.11.1 tccr1a ? timer/counter1 control register a ? bit 7:6 ? com1a1:0: compare output mode for channel a ? bit 5:4 ? com1b1:0: compare output mode for channel b the com1a1:0 and com1b1:0 control the output compare pins (oc1a and oc1b respec- tively) behavior. if one or both of the com1a1:0 bits are written to one, the oc1a output overrides the normal port functionality of the i /o pin it is connected to. if one or both of the com1b1:0 bit are written to one, the oc1b output overrides the normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit corre- sponding to the oc1a or oc1b pin must be set in order to enable the output driver. when the oc1a or oc1b is connected to the pi n, the function of the com1x1:0 bits is depen- dent of the wgm13:0 bits setting. table 6-54 shows the com1x1:0 bit functionality when the wgm13:0 bits are set to a normal or a ctc mode (non-pwm). table 6-55 shows the com1x1:0 bit functionality when the wgm13:0 bits are set to the fast pwm mode. note: 1. a special case occurs when ocr1a/oc r1b equals top and com1a1/com1b1 is set. in this case the compare match is ignored, but the set or clear is done at bottom. see ?fast pwm mode? on page 151. for more details. bit 7 6 5 4 3210 (0x80) com1a1 com1a0 com1b1 com1b0 ? ? wgm11 wgm10 tccr1a read/write r/w r/w r/w r/w r r r/w r/w initial value0 0 0 0 0000 table 6-54. compare output mode, non-pwm com1a1/com1b1 com1a0/com1b0 description 0 0 normal port operation, oc1a/oc1b disconnected. 0 1 toggle oc1a/oc1b on compare match. 10 clear oc1a/oc1b on compar e match (set output to low level). 11 set oc1a/oc1b on compare match (set output to high level). table 6-55. compare output mode, fast pwm (1) com1a1/com1b1 com1a0/com1b0 description 0 0 normal port operation, oc1a/oc1b disconnected. 01 wgm13:0 = 14 or 15: toggle oc1a on compare match, oc1b disconnected (normal port operation). for all other wgm1 settings, normal port operation, oc1a/oc1b disconnected. 10 clear oc1a/oc1b on compare match, set oc1a/oc1b at bottom (non-inverting mode) 11 set oc1a/oc1b on compare match, clear oc1a/oc1b at bottom (inverting mode) 161 9159a?auto?09/10 atmel ata6614 [preliminary] table 6-56 shows the com1x1:0 bit functionality when the wgm13:0 bits are set to the phase correct or the phase and frequency correct, pwm mode. note: 1. a special case occurs when ocr1a/ ocr1b equals top and com1a1/com1b1 is set. see ?phase correct pwm mode? on page 153. for more details. ? bit 1:0 ? wgm11:0: waveform generation mode combined with the wgm13:2 bits found in the tccr1b register, these bits control the count- ing sequence of the counter, the source for maximum (top) counter value, and what type of waveform generation to be used, see table 6-57 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and three types of pulse width modulation (pwm) modes. ( see ?modes of operation? on page 150. ). table 6-56. compare output mode, phase correct and phase and frequency correct pwm (1) com1a1/com1b1 com1a0/com1b0 description 0 0 normal port operation, oc1a/oc1b disconnected. 01 wgm13:0 = 9 or 11: toggle oc1a on compare match, oc1b disconnected (normal port operation). for all other wgm1 settings, normal port operation, oc1a/oc1b disconnected. 10 clear oc1a/oc1b on compare match when up-counting. set oc1a/oc1b on compare match when downcounting. 11 set oc1a/oc1b on co mpare match when up-counting. clear oc1a/oc1b on compare match when downcounting. 162 9159a?auto?09/10 atmel ata6614 [preliminary] note: 1. the ctc1 and pwm11:0 bit defi nition names are obsolete. use the wgm 12:0 definitions. however, the functionality and location of these bits are compatible with previous versions of the timer. 6.15.11.2 tccr1b ? timer/counter1 control register b ? bit 7 ? icnc1: input capture noise canceler setting this bit (to one) activates the input capture noise canceler. when the noise canceler is activated, the input from the input capture pi n (icp1) is filtered. the filter function requires four successive equal valued samples of the icp1 pin for changing its output. the input cap- ture is therefore dela yed by four osc illator cycles when the noise canceler is enabled. ? bit 6 ? ices1: input capture edge select this bit selects which edge on the input capture pin (icp1) that is used to trigger a capture event. when the ices1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ices1 bit is written to one, a risi ng (positive) edge w ill trigger the capture. when a capture is triggered according to the ices1 setting, the counter value is copied into the input capture regist er (icr1). the event will also se t the input capture flag (icf1), and this can be used to cause an input capture interrupt, if this interrupt is enabled. table 6-57. waveform generation mode bit description (1) mode wgm13 wgm12 (ctc1) wgm11 (pwm11) wgm10 (pwm10) timer/counter mode of operation top update of ocr1 x at tov1 flag set on 0 0 0 0 0 normal 0xffff immediate max 1 0 0 0 1 pwm, phase correct, 8-bit 0x00ff top bottom 2 0 0 1 0 pwm, phase correct, 9-bit 0x01ff top bottom 3 0 0 1 1 pwm, phase correct, 10-bit 0x03ff top bottom 4 0 1 0 0 ctc ocr1a immediate max 5 0 1 0 1 fast pwm, 8-bit 0x00ff bottom top 6 0 1 1 0 fast pwm, 9-bit 0x01ff bottom top 7 0 1 1 1 fast pwm, 10-bit 0x03ff bottom top 81000 pwm, phase and frequency correct icr1 bottom bottom 91001 pwm, phase and frequency correct ocr1a bottom bottom 10 1 0 1 0 pwm, phase correct icr1 top bottom 11 1 0 1 1 pwm, phase correct ocr1a top bottom 12 1 1 0 0 ctc icr1 immediate max 13 1 1 0 1 (reserved) ? ? ? 141110fast pwm icr1bottomtop 151111fast pwm ocr1abottomtop bit 7654 3210 (0x81) icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 tccr1b read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 163 9159a?auto?09/10 atmel ata6614 [preliminary] when the icr1 is used as top value (see description of the wgm13:0 bits located in the tccr1a and the tccr1b register), the icp1 is disconnected and consequently the input capture function is disabled. ? bit 5 ? reserved bit this bit is reserved for future use. for ensuri ng compatibility wit h future devices, this bit must be written to zero wh en tccr1b is written. ? bit 4:3 ? wgm13:2: waveform generation mode see tccr1a register description. ? bit 2:0 ? cs12:0: clock select the three clock select bits select the clock source to be used by the timer/counter, see fig- ure 6-48 and figure 6-49 . if external pin modes are used for the timer/c ounter1, transitions on the t1 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 6.15.11.3 tccr1c ? timer/counter1 control register c ? bit 7 ? foc1a: force output compare for channel a ? bit 6 ? foc1b: force output compare for channel b the foc1a/foc1b bits are only active when the wgm13:0 bits specifies a non-pwm mode. when writing a logical one to the foc1a/foc1b bit, an immediate compare match is forced on the waveform generation unit. the oc1a/oc1b output is changed according to its com1x1:0 bits setting. note that the foc1a/foc1b bits are implemented as strobes. there- fore it is the value present in the com1x1:0 bits that determine the effect of the forced compare. a foc1a/foc1b strobe will not generat e any interrupt nor will it clear the timer in clear timer on compare match (ctc) mode using ocr1a as top. the foc1a/foc1b bits are always read as zero. table 6-58. clock select bit description cs12 cs11 cs10 description 0 0 0 no clock source (timer/counter stopped). 001clk i/o /1 (no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on t1 pin. clock on falling edge. 1 1 1 external clock source on t1 pin. clock on rising edge. bit 7 6 5 4 3 2 1 0 (0x82) foc1a foc1b ? ? ? ? ? ? tccr1c read/write r/w r/w r r r r r r initial value 0 0 0 0 0 0 0 0 164 9159a?auto?09/10 atmel ata6614 [preliminary] 6.15.11.4 tcnt1h and tcnt1l ? timer/counter1 the two timer/counter i/o locations (tcnt1h and tcnt1l, combined tcnt1) give direct access, both for read and for write operations, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is perfor med using an 8-bit temporary high byte regis- ter (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 140. modifying the counter (tcnt1) while the counter is running introduces a risk of missing a compare match between tcnt1 and one of the ocr1x registers. writing to the tcnt1 register blocks (remov es) the compare match on the following timer clock for all compare units. 6.15.11.5 ocr1ah and ocr1al ? output compare register 1 a 6.15.11.6 ocr1bh and ocr1bl ? output compare register 1 b the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt1). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc1x pin. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the cpu writes to these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 140. 6.15.11.7 icr1h and icr1l ? input capture register 1 the input capture is updated with the counter (tcnt1) value each time an event occurs on the icp1 pin (or optionally on the analog comparator output for timer/counter1). the input capture can be used for defining the counter top value. bit 76543210 (0x85) tcnt1[15:8] tcnt1h (0x84) tcnt1[7:0] tcnt1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0x89) ocr1a[15:8] ocr1ah (0x88) ocr1a[7:0] ocr1al read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0x8b) ocr1b[15:8] ocr1bh (0x8a) ocr1b[7:0] ocr1bl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0x87) icr1[15:8] icr1h (0x86) icr1[7:0] icr1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 165 9159a?auto?09/10 atmel ata6614 [preliminary] the input capture register is 16-bit in size. to ensure that both the high and low bytes are read simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 140. 6.15.11.8 timsk1 ? timer/counter1 interrupt mask register ? bit 7, 6 ? res: reserved bits these bits are unused bits in the atmel ? atmega48pa/88pa/168 pa/328p, and will always read as zero. ? bit 5 ? icie1: timer/counter1, input capture interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 input capture in terrupt is enabled. the corresponding interrupt vector (see ?interrupts? on page 81) is executed when the icf1 flag, located in tifr1, is set. ? bit 4, 3 ? res: reserved bits these bits are unused bits in the atmel atmega48pa/88 pa/168pa/328p, and will always read as zero. ? bit 2 ? ocie1b: timer/counter1, output compare b match interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 output compare b match interrupt is enabled. the correspond- ing interrupt vector (see ?interrupts? on pa ge 81) is executed when the ocf1b flag, located in tifr1, is set. ? bit 1 ? ocie1a: timer/counter1, output compare a match interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 output compare a match interrupt is enabled. the correspond- ing interrupt vector (see ?interrupts? on pa ge 81) is executed when the ocf1a flag, located in tifr1, is set. ? bit 0 ? toie1: timer/counter1, overflow interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 overflow interrupt is enabled. the corresponding interrupt vec- tor (see ?interrupts? on page 81 ) is executed when the tov1 flag, located in tifr1, is set. 6.15.11.9 tifr1 ? timer/counter1 interrupt flag register ? bit 7, 6 ? res: reserved bits these bits are unused bits in the atmel ? atmega48pa/88pa/168 pa/328p, and will always read as zero. bit 76543210 (0x6f) ? ? icie1 ? ? ocie1b ocie1a toie1 timsk1 read/write r r r/w r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x16 (0x36) ? ? icf1 ? ? ocf1b ocf1a tov1 tifr1 read/write r r r/w r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 166 9159a?auto?09/10 atmel ata6614 [preliminary] ? bit 5 ? icf1: timer/count er1, input capture flag this flag is set when a capture event occurs on the icp1 pin. when the input capture register (icr1) is set by the wgm13:0 to be used as the top value, the icf1 flag is set when the counter reaches the top value. icf1 is automatically cleared when the input capture interrupt vector is executed. alterna- tively, icf1 can be cleared by writing a logic one to its bit location. ? bit 4, 3 ? res: reserved bits these bits are unused bits in the atmel ? atmega48pa/88pa/168 pa/328p, and will always read as zero. ? bit 2 ? ocf1b: timer/counter1, output compare b match flag this flag is set in the timer clock cycle afte r the counter (tcnt1) value matches the output compare register b (ocr1b). note that a forced output compare (foc 1b) strobe will not set the ocf1b flag. ocf1b is automatically cleared when the output compare match b interrupt vector is exe- cuted. alternatively, ocf1b can be cleared by writing a logic one to its bit location. ? bit 1 ? ocf1a: timer/counter1, output compare a match flag this flag is set in the timer clock cycle afte r the counter (tcnt1) value matches the output compare register a (ocr1a). note that a forced output compare (foc 1a) strobe will not set the ocf1a flag. ocf1a is automatically cleared when the output compare match a interrupt vector is exe- cuted. alternatively, ocf1a can be cleared by writing a logic one to its bit location. ? bit 0 ? tov1: timer/counter1, overflow flag the setting of this flag is dependent of the wgm13:0 bits setting. in normal and ctc modes, the tov1 flag is set when the timer overflows. refer to table 6-57 on page 162 for the tov1 flag behavior when using another wgm13:0 bit setting. tov1 is automatically cleared when the timer/co unter1 overflow interrupt vector is exe- cuted. alternatively, tov1 can be cleared by writing a logic one to its bit location. 167 9159a?auto?09/10 atmel ata6614 [preliminary] 6.16 timer/counter0 and timer/counter1 prescalers ?8-bit timer/counter0 with pwm? on page 119 and ?16-bit timer/counter1 with pwm? on page 138 share the same prescaler module, but the timer/counters can have different prescaler settings. the description below applies to both timer/counter1 and timer/counter0. 6.16.1 internal clock source the timer/counter can be clocked directly by the system clock (by setting the csn2:0 = 1). this provides the fastest operation, with a maximum timer/counter clock frequency equal to system clock frequency (f clk_i/o ). alternatively, one of four taps from the prescaler can be used as a clock source. the prescaled clock has a frequency of either f clk_i/o /8, f clk_i/o /64, f clk_i/o /256, or f clk_i/o /1024. 6.16.2 prescaler reset the prescaler is free running, i.e., operates in dependently of the clock select logic of the timer/counter, and it is shared by timer/counter1 and timer/counter0. since the prescaler is not affected by the time r/counter?s clock select, the state of the prescaler will have implica- tions for situations where a prescaled clock is used. one example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > csn2:0 > 1). the number of system clock cycles from wh en the timer is enabled to the fi rst count occurs can be from 1 to n+1 system clock cycles, where n equals the prescaler divisor (8, 64, 256, or 1024). it is possible to use the prescaler reset for syn chronizing the timer/counter to program execu- tion. however, care must be taken if the other timer/counter that shares the same prescaler also uses prescaling. a prescale r reset will affect the prescaler period for all timer/counters it is connected to. 6.16.3 external clock source an external clock source applied to the t1/t0 pin can be used as timer/counter clock (clk t1 /clk t0 ). the t1/t0 pin is sampled once every system clock cycle by the pin synchroniza- tion logic. the synchronized (sampled) signal is then passed through the edge detector. figure 6-52 shows a functional equivalent block diagram of the t1/t0 synchronization and edge detector logic. the registers are clocked at the positive edge of the internal system clock ( clk i/o ). the latch is transparent in the high period of the internal system clock. the edge detector generates one clk t1 /clk t 0 pulse for each positive (csn2:0 = 7) or negative (csn2:0 = 6) edge it detects. figure 6-52. t1/t0 pin sampling the synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the t1/t0 pin to the counter is updated. tn_sync (to clock select logic) edge detector synchronization dq dq le dq tn clk i/o 168 9159a?auto?09/10 atmel ata6614 [preliminary] enabling and disabling of the clock input must be done when t1/t0 has been stable for at least one system clock cycle, otherwise it is a risk that a false timer/counter clock pulse is generated. each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. the external clock must be guaranteed to have less than half the system clock frequency (f extclk < f clk_i/o /2) given a 50/50% duty cycle. since the edge detector uses sampling, the maximum frequency of an exte rnal clock it can detect is half the sampling frequency (nyquist sampling theorem). however, due to variation of the system clock fre- quency and duty cycle caused by oscillator source (crystal , resonator, and capacitors) tolerances, it is recommended that maximum fr equency of an external clock source is less than f clk_i/o /2.5. an external clock source can not be prescaled. figure 6-53. prescaler for timer/counter0 and timer/counter1 (1) note: 1. the synchronization logic on the input pins ( t1/t0) is shown in figure 6-52 . psrsync clear clk t1 clk t0 t1 t0 clk i/o synchronization synchronization 169 9159a?auto?09/10 atmel ata6614 [preliminary] 6.16.4 register description 6.16.4.1 gtccr ? general timer/counter control register ? bit 7 ? tsm: timer/counter synchronization mode writing the tsm bit to one activates the timer/counter synchronization mode. in this mode, the value that is written to the psrasy and psrsync bits is kept, he nce keeping the corre- sponding prescaler reset signals asserted. this ensures that the corresponding timer/counters are halted and can be configured to the same value without the risk of one of them advancing du ring configuration. when the tsm bit is written to zero, the psrasy and psrsync bits are cleared by hardware, and the timer/counters start counting simultaneously. ? bit 0 ? psrsync: prescaler reset when this bit is one, timer/co unter1 and timer/coun ter0 prescaler will be reset. this bit is normally cleared immediately by hardware, ex cept if the tsm bit is set. note that timer/counter1 and timer/counter0 share the same prescaler and a reset of this prescaler will affect both timers. bit 765432 1 0 0x23 (0x43) tsm ? ? ? ? ? psrasy psrsync gtccr read/write r/w r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 170 9159a?auto?09/10 atmel ata6614 [preliminary] 6.17 8-bit timer/counter2 with pwm and asynchronous operation 6.17.1 features ? single channel counter ? clear timer on compare match (auto reload) ? glitch-free, phase correct pu lse width modulator (pwm) ? frequency generator ? 10-bit clock prescaler ? overflow and compare ma tch interrupt sources (tov2, ocf2a and ocf2b) ? allows clocking from external 32 khz wa tch crystal independent of the i/o clock 6.17.2 overview timer/counter2 is a general purpose, single c hannel, 8-bit timer/counter module. a simplified block diagram of the 8-bit timer/counter is shown in figure 6-54 . the device-specific i/o reg- ister and bit locations are listed in the ?register description? on page 184 . the prtim2 bit in ?minimizing power consumption? on page 67 must be written to zero to enable timer/counter2 module. figure 6-54. 8-bit timer/counter block diagram clock select timer/counter data bus ocrna ocrnb = = tcntn waveform generation waveform generation ocna ocnb = fixed top value control logic = 0 top bottom count clear direction tovn (int.req.) ocna (int.req.) ocnb (int.req.) tccrna tccrnb tn edge detector ( from prescaler ) clk tn 171 9159a?auto?09/10 atmel ata6614 [preliminary] 6.17.2.1 registers the timer/counter (tcnt2) and output compare register (ocr2a and ocr2b) are 8-bit registers. interrupt request (shorten as int.req.) signals are all visible in the timer interrupt flag register (tifr2). all interrupts are individually masked with the timer interrupt mask register (timsk2). tifr2 and timsk2 are not shown in the figure. the timer/counter can be clocked internally, vi a the prescaler, or asynchronously clocked from the tosc1/2 pins, as detailed later in this section. the asynchronous operation is con- trolled by the asynchronous status register (assr). the clock select logic block controls which clock source he timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t2 ). the double buffered output compare register (ocr2a and ocr2b) are compared with the timer/counter value at all times. the result of the compare can be used by the waveform generator to generate a pwm or variable frequency output on the output compare pins (oc2a and oc2b). see ?output compare unit? on page 172. for details. the compare match event will also set the compare flag (ocf2a or ocf2b) which can be used to generate an output compare interrupt request. 6.17.2.2 definitions many register and bit references in this document are written in general form. a lower case ?n? replaces the timer/counter number, in this case 2. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt2 for accessing timer/counter2 counter value and so on. the definitions in table 6-59 are also used extensively throughout the section. 6.17.3 timer/counter clock sources the timer/counter can be clocked by an inte rnal synchronous or an external asynchronous clock source. the clock source clk t2 is by default equal to the mcu clock, clk i/o . when the as2 bit in the assr register is written to l ogic one, the clock source is taken from the timer/counter oscillator connected to tosc1 and tosc2. for details on asynchronous operation, see ?assr ? asynchronous status register? on page 190 . for details on clock sources and prescaler, see ?timer/counter prescaler? on page 183 . 6.17.4 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. fig- ure 6-55 on page 172 shows a block diagram of the counter and its surrounding environment. table 6-59. definitions bottom the counter reaches the bottom when it becomes zero (0x00). max the counter reaches its maximum when it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr2a register. the assignment is dependent on the mode of operation. 172 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-55. counter unit block diagram signal description (internal signals): count increment or decrement tcnt2 by 1. direction selects between increment and decrement. clear clear tcnt2 (set all bits to zero). clk tn timer/counter clock, referred to as clk t2 in the following. top signalizes that tcnt2 has reached maximum value. bottom signalizes that tcnt2 has reached minimum value (zero). depending on the mode of operation used, the counter is cleared, incremented, or decre- mented at each timer clock (clk t2 ). clk t2 can be generated from an external or internal clock source, selected by the clock select bits (c s22:0). when no clock source is selected (cs22:0 = 0) the timer is stopped. however, the tcnt2 value can be accessed by the cpu, regardless of whether clk t2 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the wgm21 and wgm20 bits located in the timer/counter control register (tccr2a) and the wgm22 located in the timer/coun- ter control register b (tccr2b). there are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs oc2a and oc2b. for more details about advanced counting sequences and waveform generation, see ?modes of operation? on page 175 . the timer/counter overflow flag (tov2) is set according to the mode of operation selected by the wgm22:0 bits. tov2 can be used for generating a cpu interrupt. 6.17.5 output compare unit the 8-bit comparator continuously compares tcnt2 with the output compare register (ocr2a and ocr2b). whenever tcnt2 equals ocr2a or ocr2b, the comparator signals a match. a match will set the output compare flag (ocf2a or ocf2b) at the next timer clock cycle. if the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. the output compare flag is automatically cleared when the interrupt is executed. alternatively, the output compare flag can be cleared by software by writing a log- ical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to operating mode set by the wgm22:0 bits and compare output mode (com2x1:0) bits. the max and bottom signals are used by the waveform generator for han- dling the special cases of the extreme values in some modes of operation ( ?modes of operation? on page 175 ). data b u s tcntn control logic count tovn (int.req.) top bottom direction clear tosc1 t/c oscillator tosc2 prescaler clk i/o clk tn 173 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-56 shows a block diagram of the output compare unit. figure 6-56. output compare unit, block diagram the ocr2x register is double buffered when us ing any of the pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buffering sy nchronizes the update of the ocr2x compare register to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr2x register access may seem complex, but this is not case. when the double buffer- ing is enabled, the cpu has access to the ocr2x buffer register, and if double buffering is disabled the cpu will a ccess the ocr2x directly. 6.17.5.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (foc2x) bit. fo rcing compare match will not set the ocf2x flag or reload/clear the timer, but the oc2x pin will be updated as if a real com- pare match had occurred (the com2x1:0 bits settings define whether the oc2x pin is set, cleared or toggled). 6.17.5.2 compare match blocking by tcnt2 write all cpu write operations to the tcnt2 register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. this feature allows ocr2x to be initialized to the same value as tcnt2 without triggering an interrupt when the timer/counter clock is enabled. ocfn x (int.req.) = (8-bit comparator ) ocrnx ocnx data b u s tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom 174 9159a?auto?09/10 atmel ata6614 [preliminary] 6.17.5.3 using the output compare unit since writing tcnt2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing tcnt2 when using the output compare channel, independently of whether the timer/counter is running or not. if the value written to tcnt2 equals the ocr2x value, the compare match will be miss ed, resulting in incorrect waveform generation. similarly, do not write the tcnt2 value equal to bottom when the counter is downcounting. the setup of the oc2x should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc2x value is to use the force output com- pare (foc2x) strobe bit in normal mode. the oc2x register keeps its value even when changing between waveform generation modes. be aware that the com2x1:0 bits are not double buffered together with the compare value. changing the com2x1:0 bits will take effect immediately. 6.17.6 compare match output unit the compare output mode (com2x1:0) bits have two functions. the waveform generator uses the com2x1:0 bits for defining the output compare (oc2x) state at the next compare match. also, the com2x1:0 bits control the oc2x pin output source. figure 6-57 shows a sim- plified schematic of the logic affected by the com2x1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control reg- isters (ddr and port) th at are affected by the com2x1:0 bits are shown. when referring to the oc2x state, the reference is for the internal oc2x register, not the oc2x pin. figure 6-57. compare match output unit, schematic port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data b u s focnx clk i/o 175 9159a?auto?09/10 atmel ata6614 [preliminary] the general i/o port function is overridden by the output compare (oc2x) from the waveform generator if either of the com2x1:0 bits are set. however, the oc2x pin direction (input or output) is still controlled by the data direction register (ddr ) for the port pin. the data direc- tion register bit for the oc2x pin (ddr_oc2x) must be set as output before the oc2x value is visible on the pin. the port override function is independent of the waveform generation mode. the design of the output compare pin logic allows initialization of the oc2x state before the output is enabled. note that some com2x1:0 bit settings are reserved for certain modes of operation. see ?register description? on page 184. 6.17.6.1 compare output mode and waveform generation the waveform generator uses the com2x1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the com2x1:0 = 0 tells the waveform generator that no action on the oc2x register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 6-63 on page 185 . for fast pwm mode, refer to table 6-64 on page 185 , and for phase correct pwm refer to table 6-65 on page 186 . a change of the com2x1:0 bits state will have effe ct at the first compare match after the bits are written. for non-pwm modes, the action can be forced to have immediate effect by using the foc2x strobe bits. 6.17.7 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm22:0) and compare output mode (com2x1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com2x1:0 bits control whether the pwm output generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the com2x1:0 bits control whether the output should be set, cleared, or tog- gled at a compare match ( see ?compare match output unit? on page 174. ). for detailed timing information refer to ?timer/counter timing diagrams? on page 180 . 6.17.7.1 normal mode the simplest mode of operation is the normal mode (wgm22:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 8-bit value (top = 0xff) and then restarts from the bot- tom (0x00). in normal operation the timer/counter overflow flag (tov2) will be set in the same timer clock cycle as the tcnt2 becomes zero . the tov2 flag in this case behaves like a ninth bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov2 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 176 9159a?auto?09/10 atmel ata6614 [preliminary] 6.17.7.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm22:0 = 2), the ocr2a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the coun- ter value (tcnt2) matches the ocr2a. the ocr2a defines the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output fre- quency. it also simplifies the operati on of counting external events. the timing diagram for the ctc mode is shown in figure 6-58 . the counter value (tcnt2) increases until a compare match occurs between tcnt2 and ocr2a, and then counter (tcnt2) is cleared. figure 6-58. ctc mode, timing diagram an interrupt can be generated each time the counter value reaches the top value by using the ocf2a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing top to a value close to bottom when the counter is running with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr2a is lower than the current value of tcnt2, the counter will miss the compare match. the counter will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. for generating a waveform output in ctc mode, the oc2a output can be set to toggle its log- ical level on each compare match by setting the compare output mode bits to toggle mode (com2a1:0 = 1). the oc2a value will not be visi ble on the port pin unless the data direction for the pin is set to output. the waveform generated will have a maximum frequency of f oc2a =f clk_i/o /2 when ocr2a is set to zero (0x00). the waveform frequency is defined by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). as for the normal mode of operation, the tov2 flag is set in the same timer clock cycle that the counter counts from max to 0x00. tcntn ocnx (toggle) ocnx interrupt flag set 1 4 period 2 3 (comnx1:0 = 1) f ocnx f clk_i/o 2 n 1 ocrnx + () ?? ------------------------------------------------------- = 177 9159a?auto?09/10 atmel ata6614 [preliminary] 6.17.7.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm22:0 = 3 or 7) provides a high fre- quency pwm waveform generation option. the fast pwm differs from the other pwm option by its single-slope operation. t he counter counts from bottom to top then restarts from bottom. top is defined as 0xff when wgm2:0 = 3, and ocr2a when mgm2:0 = 7. in non-inverting compare output mode, the output compare (oc2x) is cleared on the compare match between tcnt2 and ocr2x, and set at bottom. in inverting compare output mode, the output is set on compare match and cleared at bottom. due to the single-slope opera- tion, the operating frequency of the fast pwm mo de can be twice as high as the phase correct pwm mode that uses dual-slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectificat ion, and dac applications. high frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. in fast pwm mode, the counter is incremented until the counter value matches the top value. the counter is then cleared at the following ti mer clock cycle. the timing diagram for the fast pwm mode is shown in figure 6-59 . the tcnt2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt2 slopes represent com- pare matches between ocr2x and tcnt2. figure 6-59. fast pwm mode, timing diagram the timer/counter overflow flag (tov2) is se t each time the counter reaches top. if the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. in fast pwm mode, the compare unit allows generation of pwm waveforms on the oc2x pin. setting the com2x1:0 bits to two will produce a non-inverted pwm and an inverted pwm out- put can be generated by setting the com2x1:0 to three. top is defined as 0xff when wgm2:0 = 3, and ocr2a when mgm2:0 = 7. (see table 6-61 on page 184 ). the actual oc2x value will only be visible on the port pin if the data direction for the port pin is set as out- put. the pwm waveform is generated by setting (or clearing) the oc2x register at the compare match between ocr2x and tcnt2, and clearing (or setting) the oc2x register at the timer clock cycle the counter is cleared (changes from top to bottom). tcntn ocrnx update and tovn interrupt flag set 1 period 2 3 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx interrupt flag set 4 5 6 7 178 9159a?auto?09/10 atmel ata6614 [preliminary] the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr2a register represent special cases when generating a pwm waveform output in the fast pwm mode. if the ocr2a is set equal to bott om, the output will be a narrow spike for each max+1 timer clock cycle. setti ng the ocr2a equal to max will result in a constantly high or low output (depending on the polarity of the output set by the com2a1:0 bits.) a frequency (with 50% duty cycle) waveform output in fast pwm mode can be achieved by setting oc2x to toggle its logical level on each compare match (com2x1:0 = 1). the wave- form generated will have a maximum frequency of f oc2 = f clk_i/o /2 when ocr2a is set to zero. this feature is similar to the oc2a toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast pwm mode. 6.17.7.4 phase correct pwm mode the phase correct pwm mode (wgm22:0 = 1 or 5) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is based on a dual-slope operation. the counter counts repeatedly from bottom to top and then from top to bot- tom. top is defined as 0xff when wgm2:0 = 3, and ocr2a when mgm2:0 = 7. in non-inverting compare output mode, the output compare (oc2x) is cleared on the compare match between tcnt2 and ocr2x while upcounting, and set on the compare match while downcounting. in inverting output compare m ode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. in phase correct pwm mode the counter is incremented until the counter value matches top. when the counter reaches top, it changes th e count direction. the tcnt2 value will be equal to top for one timer clock cycle. the ti ming diagram for the phase correct pwm mode is shown on figure 6-60 . the tcnt2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the di agram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt2 slopes represent compare matches between ocr2x and tcnt2. f ocnxpwm f clk_i/o n 256 ? -------------------- - = 179 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-60. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov2) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bot- tom value. in phase correct pwm mode, the compare unit allows generation of pwm waveforms on the oc2x pin. setting the com2x1:0 bits to two will produce a non-invert ed pwm. an inverted pwm output can be generated by setting the com2x1:0 to three. top is defined as 0xff when wgm2:0 = 3, and ocr2a when mgm2:0 = 7 (see table 6-62 on page 185 ). the actual oc2x value will only be visible on the port pin if the data direction for the port pin is set as out- put. the pwm waveform is generated by clearing (or setting) the oc2x register at the compare match between ocr2x and tcnt2 when the counter increments, and setting (or clearing) the oc2x register at compare match between ocr2x and tcnt2 when the counter decrements. the pwm frequency for the output when using phase correct pwm can be calcu- lated by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr2a register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr2a is set equal to bottom, the output will be continuously low an d if set equal to max the out put will be continuously high for non-inverted pwm mode. for in verted pwm the output will have the opposite logic values. tovn interrupt flag set ocnx interrupt flag set 1 2 3 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx update f ocnxpcpwm f clk_i/o n 510 ? -------------------- - = 180 9159a?auto?09/10 atmel ata6614 [preliminary] at the very start of period 2 in figure 6-60 ocnx has a transition from high to low even though there is no compare match. the point of this transition is to guarantee symmetry around bot- tom. there are two cases that give a transition without compare match. ? ocr2a changes its value from max, like in figure 6-60 . when the ocr2a value is max the ocn pin value is the same as the result of a down-counting compare match. to ensure symmetry around bottom the ocn value at max must correspond to the result of an up-counting compare match. ? the timer starts counting from a value higher than the one in ocr2a, and for that reason misses the compare match and hence the ocn change that would have happened on the way up. 6.17.8 timer/counter timing diagrams the following figures show the timer/counter in synchronous mode, and the timer clock (clk t2 ) is therefore shown as a clock enable signal. in asynchronous mode, clk i/o should be replaced by the timer/counter o scillator clock. the fi gures include informat ion on when inter- rupt flags are set. figure 6-61 contains timing data for basic timer/counter operation. the figure shows the count sequence close to the max value in all modes other than phase correct pwm mode. figure 6-61. timer/counter timing diagram, no prescaling figure 6-62 shows the same timing data, but with the prescaler enabled. figure 6-62. timer/counter timing dia gram, with prescaler (f clk_i/o /8) clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) 181 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-63 shows the setting of ocf2a in all modes except ctc mode. figure 6-63. timer/counter timing diagram, setting of ocf2a, with prescaler (f clk_i/o /8) figure 6-64 shows the setting of ocf2a and the clearing of tcnt2 in ctc mode. figure 6-64. timer/counter timing diagram, clear timer on compare match mode, with prescaler (f clk_i/o /8) 6.17.9 asynchronous operation of timer/counter2 when timer/counter2 operates asynchronously, some considerations must be taken. ? warning: when switching between asynchronous and synchronous clocking of timer/counter2, the timer registers tcnt2, ocr2x, and tccr2x might be corrupted. a safe procedure for switching clock source is: a. disable the timer/counter2 interrupts by clearing ocie2x and toie2. b. select clock source by setting as2 as appropriate. c. write new values to tcnt2, ocr2x, and tccr2x. d. to switch to asynchronous operation: wait for tcn2xub, ocr2xub, and tcr2xub. e. clear the timer/counter2 interrupt flags. f. enable interrupts, if needed. ? the cpu main clock frequency must be more than four times th e oscillator frequency. ? when writing to one of the registers tcnt2, ocr2x, or tccr2x, the value is transferred to a temporary register, and latched after two positive edges on tosc1. the user should not write a new value before the contents of the temporary register have been transferred to its destination. each of the five mentioned registers have their individual temporary register, which means that e.g. writing to tcnt2 does not disturb an ocr2x write in progress. to detect that a transfer to the destination register has taken place, the asynchronous status register ? assr has been implemented. ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) 182 9159a?auto?09/10 atmel ata6614 [preliminary] ? when entering power-save or adc noise reduction mode after having written to tcnt2, ocr2x, or tccr2x, the user must wait until the written register has been updated if timer/counter2 is used to wake up the device. otherwise, the mcu will enter sleep mode before the changes are effective. this is particularly important if any of the output compare2 interrupt is used to wake up the device, since the output compare function is disabled during writing to ocr2x or tcnt2. if the write cycle is not finished, and the mcu enters sleep mode before the corresponding ocr2xub bit retu rns to zero, the device will never receive a compare match interrupt, and the mcu will not wake up. ? if timer/counter2 is used to wake the device up from power-save or adc noise reduction mode, precautions must be taken if the user wants to re-enter one of these modes: if re-entering sleep mode within the tosc1 cycle, the interrupt will immi diately occur and the device wake up again. the result is multiple interrupts and wake-ups within one tosc1 cycle from the first interrupt. if the user is in doubt whether the time before re-entering power-save or adc noise reduction mode is sufficient, the following algorithm can be used to ensure that one tosc1 cycle has elapsed: a. write a value to tccr2x, tcnt2, or ocr2x. b. wait until the corresponding update busy flag in assr returns to zero. c. enter power-save or adc noise reduction mode. ? when the asynchronous operati on is selected, the 32.768 khz oscillator for ti mer/counter2 is always running, except in power-down and standby modes. after a power-up reset or wake-up from power-down or standby mode, the user should be aware of the fact that this oscillator might take as long as one second to stabilize. the user is advised to wait for at least one second before using timer/counter2 after power-up or wake-up from power-down or standby mode. the contents of all timer/counter2 registers must be considered lost after a wake-up from power-down or standby mode due to unstable clock signal upon start-up, no matter whether the oscillator is in use or a clock signal is applied to the tosc1 pin. ? description of wake up from power-save or adc noise reduction mode when the timer is clocked asynchronously: when the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. after wake-up, the mcu is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following sleep. ? reading of the tcnt2 register shortly after wake-up from power-save may give an incorrect result. since tcnt2 is clocked on the asynchronous tosc clock, reading tcnt2 must be done through a register synchronized to the in ternal i/o clock domain. synchronization takes place for every rising tosc1 edge. when waking up from power-save mode, and the i/o clock (clk i/o ) again becomes active, tcnt2 will read as the previous value (before entering sleep) until the next rising tosc1 edge. the phase of the tosc clock after waking up from power-save mode is essentially unpredictable, as it depends on the wake-up time. the recommended procedure for reading tcnt2 is thus as follows: a. write any value to either of the registers ocr2x or tccr2x. b. wait for the corresponding update busy flag to be cleared. c. read tcnt2. 183 9159a?auto?09/10 atmel ata6614 [preliminary] during asynchronous operation, the synchronizati on of the interrupt flags for the asynchro- nous timer takes 3 processor cycles plus one ti mer cycle. the timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the interrupt flag. the output compare pin is changed on the timer clock and is not synchronized to the processor clock. 6.17.10 timer/counter prescaler figure 6-65. prescaler for timer/counter2 the clock source for timer/counter2 is named clk t2s . clk t2s is by default connected to the main system i/o clock clk i o . by setting the as2 bit in assr, timer/counter2 is asynchro- nously clocked from the tosc1 pin. this enables use of timer/counter2 as a real time counter (rtc). when as2 is set, pins tosc1 and tosc2 are disconnected from port c. a crystal can then be connected between the to sc1 and tosc2 pins to serve as an indepen- dent clock source for timer/counter2. the oscillator is optimized for use with a 32.768khz crystal. for timer/counter2, the possible prescaled selections are: clk t2s /8, clk t2s /32, clk t2s /64, clk t2s /128, clk t2s /256, and clk t2s /1024. additionally, clk t2s as well as 0 (stop) may be selected. setting the psrasy bit in gtccr resets the prescaler. this allows th e user to oper- ate with a predictable prescaler. 10-bit t/c prescaler timer/counter2 clock source clk i/o clk t2s tosc1 as2 cs20 cs21 cs22 clk t2s /8 clk t2s /64 clk t2s /128 clk t2s /1024 clk t2s /256 clk t2s /32 0 psrasy clear clk t2 184 9159a?auto?09/10 atmel ata6614 [preliminary] 6.17.11 register description 6.17.11.1 tccr2a ? timer/counter control register a ? bits 7:6 ? com2a1:0: compare match output a mode these bits control the output compare pin (oc2a) behavior. if one or both of the com2a1:0 bits are set, the oc2a output overrides the normal port functionality of the i/o pin it is con- nected to. however, note that the data direction register (ddr) bit corresponding to the oc2a pin must be set in order to enable the output driver. when oc2a is connected to the pin, the function of the com2a1:0 bits depends on the wgm22:0 bit setting. table 6-60 shows the com2a1:0 bit f unctionality when the wgm22:0 bits are set to a normal or ctc mode (non-pwm). table 6-61 shows the com2a1:0 bit functionality when the wgm21:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr2a equals top and com2a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at bottom. see ?fast pwm mode? on page 177 for more details. bit 7 6 5 4 3 2 1 0 (0xb0) com2a1 com2a0 com2b1 com2b0 ? ? wgm21 wgm20 tccr2a read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 6-60. compare output mode, non-pwm mode com2a1 com2a0 description 0 0 normal port operation, oc0a disconnected. 0 1 toggle oc2a on compare match 1 0 clear oc2a on compare match 1 1 set oc2a on compare match table 6-61. compare output mode, fast pwm mode (1) com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 01 wgm22 = 0: normal port operation, oc0a disconnected. wgm22 = 1: toggle oc2a on compare match. 10 clear oc2a on compare match, set oc2a at bottom, (non-inverting mode). 11 set oc2a on compare match, clear oc2a at bottom, (inverting mode). 185 9159a?auto?09/10 atmel ata6614 [preliminary] table 6-62 shows the com2a1:0 bit functionality when the wgm22:0 bits are set to phase correct pwm mode. note: 1. a special case occurs when ocr2a equals top and com2a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 178 for more details. ? bits 5:4 ? com2b1:0: compare match output b mode these bits control the output compare pin (oc2b) behavior. if one or both of the com2b1:0 bits are set, the oc2b output overrides the normal port functionality of the i/o pin it is con- nected to. however, note that the data direction register (ddr) bit corresponding to the oc2b pin must be set in order to enable the output driver. when oc2b is connected to the pin, the function of the com2b1:0 bits depends on the wgm22:0 bit setting. table 6-63 shows the com2b1:0 bit f unctionality when the wgm22:0 bits are set to a normal or ctc mode (non-pwm). table 6-64 shows the com2b1:0 bit functionality when the wgm22:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr2b equals top and com2b1 is set. in this case, the com- pare match is ignored, but the set or clear is done at bottom. see ?phase correct pwm mode? on page 178 for more details. table 6-62. compare output mode, phase correct pwm mode (1) com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 01 wgm22 = 0: normal port o peration, oc2a disconnected. wgm22 = 1: toggle oc2a on compare match. 10 clear oc2a on compare match when up-counting. set oc2a on compare match when down-counting. 11 set oc2a on compare match when up-counting. clear oc2a on compare match when down-counting. table 6-63. compare output mode, non-pwm mode com2b1 com2b0 description 0 0 normal port operation, oc2b disconnected. 0 1 toggle oc2b on compare match 1 0 clear oc2b on compare match 1 1 set oc2b on compare match table 6-64. compare output mode, fast pwm mode (1) com2b1 com2b0 description 0 0 normal port operation, oc2b disconnected. 01reserved 10 clear oc2b on compare match, set oc2b at bottom, (non-inverting mode). 11 set oc2b on compare match, clear oc2b at bottom, (inverting mode). 186 9159a?auto?09/10 atmel ata6614 [preliminary] table 6-65 shows the com2b1:0 bit functionality when the wgm22:0 bits are set to phase correct pwm mode. note: 1. a special case occurs when ocr2b equals top and com2b1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 178 for more details. ? bits 3, 2 ? res: reserved bits these bits are reserved bits in the atmega48pa/88pa/168pa/328p and will always read as zero. ? bits 1:0 ? wgm21:0: waveform generation mode combined with the wgm22 bit found in the t ccr2b register, these bits control the counting sequence of the counter, the source for maximum (top) counter value, and what type of waveform generation to be used, see table 6-66 . modes of operation supported by the timer/c ounter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and two types of pulse width modulation (pwm) modes (see ?modes of operation? on page 175 ). notes: 1. max = 0xff 2. bottom = 0x00 table 6-65. compare output mode, phase correct pwm mode (1) com2b1 com2b0 description 0 0 normal port operation, oc2b disconnected. 01reserved 10 clear oc2b on compare match when up-counting. set oc2b on compare match when down-counting. 11 set oc2b on compare match when up-counting. clear oc2b on compare match when down-counting. table 6-66. waveform generation mode bit description mode wgm2 wgm1 wgm0 timer/counter mode of operation top update of ocrx at tov flag set on (1)(2) 0 0 0 0 normal 0xff immediate max 1001 pwm, phase correct 0xff top bottom 2 0 1 0 ctc ocra immediate max 3 0 1 1 fast pwm 0xff bottom max 4100reserved ? ? ? 5101 pwm, phase correct ocra top bottom 6110reserved ? ? ? 7 1 1 1 fast pwm ocra bottom top 187 9159a?auto?09/10 atmel ata6614 [preliminary] 6.17.11.2 tccr2b ? timer/counter control register b ? bit 7 ? foc2a: force output compare a the foc2a bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibi lity with future devices, this bit must be set to zero when tccr2b is written when operating in pwm mode. when writing a logical one to the foc2a bit, an immediate compare match is forced on the waveform generation unit. the oc2a out- put is changed according to its com2a1:0 bits setting. note that the foc2a bit is implemented as a strobe. therefore it is the value present in the com2a1:0 bits that deter- mines the effect of the forced compare. a foc2a strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr2a as top. the foc2a bit is always read as zero. ? bit 6 ? foc2b: force output compare b the foc2b bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibi lity with future devices, this bit must be set to zero when tccr2b is written when operating in pwm mode. when writing a logical one to the foc2b bit, an immediate compare match is forced on the waveform generation unit. the oc2b out- put is changed according to its com2b1:0 bits setting. note that the foc2b bit is implemented as a strobe. therefore it is the value present in the com2b1:0 bits that determines the effect of the forced compare. a foc2b strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr2b as top. the foc2b bit is always read as zero. ? bits 5:4 ? res: reserved bits these bits are reserved bits in the atmel ? atmega48pa/88pa/168pa/328p and will always read as zero. ? bit 3 ? wgm22: waveform generation mode see the description in the ?tccr2a ? timer/counter control register a? on page 184 . ? bit 2:0 ? cs22:0: clock select the three clock select bits select the clock source to be used by the timer/counter, see table 6-67 on page 188 . bit 7 6 5 4 3 210 (0xb1) foc2a foc2b ? ? wgm22 cs22 cs21 cs20 tccr2b read/write w w r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 188 9159a?auto?09/10 atmel ata6614 [preliminary] if external pin modes are used for the timer/c ounter0, transitions on the t0 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 6.17.11.3 tcnt2 ? timer/counter register the timer/counter register gives direct access, both for read and write operations, to the timer/counter unit 8-bit counter. writing to t he tcnt2 register blocks (removes) the com- pare match on the following timer clock. modify ing the counter (tcnt2) while the counter is running, introduces a risk of missing a compare match between tcnt2 and the ocr2x registers. table 6-67. clock select bit description cs22 cs21 cs20 description 0 0 0 no clock source (timer/counter stopped). 001clk t2s /(no prescaling) 010clk t2s /8 (from prescaler) 011clk t2s /32 (from prescaler) 100clk t2s /64 (from prescaler) 101clk t2s /128 (from prescaler) 110clk t 2 s /256 (from prescaler) 111clk t 2 s /1024 (from prescaler) bit 76543210 (0xb2) tcnt2[7:0] tcnt2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 189 9159a?auto?09/10 atmel ata6614 [preliminary] 6.17.11.4 ocr2a ? output compare register a the output compare register a contains an 8-bit value that is continuously compared with the counter value (tcnt2). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc2a pin. 6.17.11.5 ocr2b ? output compare register b the output compare register b contains an 8-bit value that is continuously compared with the counter value (tcnt2). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc2b pin. 6.17.11.6 timsk 2 ? timer/counter 2 interrupt mask register ? bit 2 ? ocie2b: timer/counter2 output compare match b interrupt enable when the ocie2b bit is written to one and the i-bit in the status register is set (one), the timer/counter2 compare match b interrupt is enabled. the corresponding interrupt is exe- cuted if a compare match in timer/counter2 occurs, i.e., when the ocf2b bit is set in the timer/counter 2 interrupt flag register ? tifr2. ? bit 1 ? ocie2a: timer/counter2 output compare match a interrupt enable when the ocie2a bit is written to one and the i-bit in the status register is set (one), the timer/counter2 compare match a interrupt is enabled. the corresponding interrupt is exe- cuted if a compare match in timer/counter2 occurs, i.e., when the ocf2a bit is set in the timer/counter 2 interrupt flag register ? tifr2. ? bit 0 ? toie2: timer/counter2 overflow interrupt enable when the toie2 bit is written to one and the i-bi t in the status register is set (one), the timer/counter2 overflow interrupt is enabled. the corresponding interrupt is executed if an overflow in timer/counter2 occurs, i.e., when th e tov2 bit is set in the timer/counter2 inter- rupt flag register ? tifr2. bit 76543210 (0xb3) ocr2a[7:0] ocr2a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0xb4) ocr2b[7:0] ocr2b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543 2 1 0 (0x70) ?????ocie2bocie2atoie2timsk2 read/write rrrrr r/wr/wr/w initial value 00000 0 0 0 190 9159a?auto?09/10 atmel ata6614 [preliminary] 6.17.11.7 tifr 2 ? timer/counter 2 interrupt flag register ? bit 2 ? ocf2b: output compare flag 2 b the ocf2b bit is set (one) when a compare match occurs between the timer/counter2 and the data in ocr2b ? output compare register2. ocf2b is cleared by hardware when exe- cuting the corresponding interrupt handling vector. alternatively, ocf2b is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie2b (timer/counter2 compare match inter- rupt enable), and ocf2b are set (one), the timer/counter2 compare match interrupt is executed. ? bit 1 ? ocf2a: output compare flag 2 a the ocf2a bit is set (one) when a compare match occurs between the timer/counter2 and the data in ocr2a ? output compare register2. ocf2a is cleared by hardware when exe- cuting the corresponding interrupt handling vector. alternatively, ocf2a is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie2a (timer/counter2 compare match inter- rupt enable), and ocf2a are set (one), the timer/counter2 compare match interrupt is executed. ? bit 0 ? tov2: timer/counter2 overflow flag the tov2 bit is set (one) when an overflow oc curs in timer/counter2. tov2 is cleared by hardware when executing the corresponding interr upt handling vector. alternatively, tov2 is cleared by writing a logic one to the flag. when the sreg i-bit, toie2a (timer/counter2 overflow interrupt enable), and tov2 are set (one), the timer/counter2 overflow interrupt is executed. in pwm mode, this bit is set when timer/counter2 changes counting direction at 0x00. 6.17.11.8 assr ? asynchr onous status register ? bit 7 ? res: reserved bit this bit is reserved and will always read as zero. ? bit 6 ? exclk: enable external clock input when exclk is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an exter nal clock can be input on time r oscillator 1 (tosc1) pin instead of a 32 khz crystal. writing to exclk should be done before asynchronous operation is selected. note that the crystal oscilla tor will only run when this bit is zero. ? bit 5 ? as2: asynchronous timer/counter2 when as2 is written to zero, timer/counter2 is clocked from the i/o clock, clk i/o . when as2 is written to one, timer/ counter2 is clocked from a crystal oscillator connect ed to the timer oscillator 1 (tosc1) pin. when the value of as2 is changed, the conten ts of tcnt2, ocr2a, ocr2b, tccr2a and tccr2b might be corrupted. bit 76543210 0x17 (0x37) ?????ocf2bocf2atov2tifr2 read/write rrrrrr/wr/wr/w initial value00000000 bit 7 6 5 4 3 2 1 0 (0xb6) ? exclk as2 tcn2ub ocr2aub ocr2bub tcr2aub tcr2bub assr read/write r r/w r/w r r r r r initial value 0 0 0 0 0 0 0 0 191 9159a?auto?09/10 atmel ata6614 [preliminary] ? bit 4 ? tcn2ub: timer/counter2 update busy when timer/counter2 operates asynchronously and tcnt2 is written, this bit becomes set. when tcnt2 has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that tcnt2 is ready to be updated with a new value. ? bit 3 ? ocr2aub: output co mpare register2 update busy when timer/counter2 operates asynchronously and ocr2a is written, this bit becomes set. when ocr2a has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that ocr2a is ready to be updated with a new value. ? bit 2 ? ocr2bub: output compare register2 update busy when timer/counter2 operates asynchronously and ocr2b is written, this bit becomes set. when ocr2b has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that ocr2b is ready to be updated with a new value. ? bit 1 ? tcr2aub: timer/counter control register2 update busy when timer/counter2 operates asynchronously and tccr2a is written, this bit becomes set. when tccr2a has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that tccr2a is r eady to be updat ed with a new value. ? bit 0 ? tcr2bub: timer/counter control register2 update busy when timer/counter2 operates asynchronously and tccr2b is written, this bit becomes set. when tccr2b has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that tccr2b is r eady to be updat ed with a new value. if a write is performed to any of the five timer/counter2 registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. the mechanisms for reading tcnt2, ocr2a, ocr2b, tccr2a and tccr2b are different. when reading tcnt2, the actual timer value is read. when reading ocr2a, ocr2b, tccr2a and tccr2b the value in the te mporary storage re gister is read. 6.17.11.9 gtccr ? general timer/counter control register ? bit 1 ? psrasy: prescaler reset timer/counter2 when this bit is one, the timer/counter2 prescale r will be reset. this bit is normally cleared immediately by hardware. if the bit is written when timer/counter2 is operating in asynchro- nous mode, the bit will remain one until the prescaler has been reset. the bit will not be cleared by hardware if the tsm bit is set. refer to the description of the ?bit 7 ? tsm: timer/counter synchronization mode? on page 169 for a description of the timer/counter synchronization mode. bit 7 6 5 4 3 2 1 0 0x23 (0x43) tsm ? ? ? ? ? psrasy psrsync gtccr read/write r/w r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 192 9159a?auto?09/10 atmel ata6614 [preliminary] 6.18 spi ? serial pe ripheral interface 6.18.1 features ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? seven programmable bit rates ? end of transmission interrupt flag ? write collision flag protection ? wake-up from idle mode ? double speed (ck/2) master spi mode 6.18.2 overview the serial peripheral interface (spi) allows high-speed synchronous data transfer between the atmel ? atmega48pa/88pa/168pa/328p and peripheral devices or between several avr devices. the usart can also be used in master spi mode, see ?usart in spi mode? on page 229. the prspi bit in ?minimizing power consumption? on page 67 must be written to zero to enable spi module. figure 6-66. spi block diagram (1) note: 1. refer to table 6-36 on page 108 for spi pin placement. spi2x spi2x divider /2/4/8/16/32/64/128 193 9159a?auto?09/10 atmel ata6614 [preliminary] the interconnection between master and slave cpus with spi is shown in figure 6-67 on page 193 . the system consists of two shift registers, and a master clock generator. the spi master initiates the communication cycle when pulling low the slave select ss pin of the desired slave. master and slave prepare the data to be sent in their respective shift registers, and the master generates the required clock pulses on the sck line to interchange data. data is always shifted from master to slave on the master out ? slave in, mosi, line, and from slave to master on the master in ? slave out, miso, line. after each data packet, the master will synchronize the slave by pu lling high the slave select, ss , line. when configured as a master, the spi interface has no automatic control of the ss line. this must be handled by user software before communication can start. when this is done, writing a byte to the spi data register starts the spi clock generator, and the hardware shifts the eight bits into the slave. after shifting one byte, the spi clock generator stops, setting the end of transmission flag (spif). if the spi interrupt enable bit (spie) in the spcr register is set, an interrupt is requested. the master may continue to shift the next byte by writing it into spdr, or signal the end of packet by pulling high the slave select, ss line. the last incoming byte will be kept in the bu ffer register for later use. when configured as a slave, the spi interface will remain sleeping with miso tri-stated as long as the ss pin is driven high. in this state, software may update the contents of the spi data register, spdr, but the data will not be shifted out by incoming clock pulses on the sck pin until the ss pin is driven low. as one byte has been completely shifted, the end of trans- mission flag, spif is set. if the spi interrupt enable bit, spie, in the spcr register is set, an interrupt is requested. the slave may continue to place new data to be sent into spdr before reading the incoming data. the last incoming byte will be kept in the buffer register for later use. figure 6-67. spi master-slave interconnection the system is single buffered in the transmit direction and double buffered in the receive direc- tion. this means that bytes to be transmitted cannot be written to the spi data register before the entire shift cycle is completed. when receiving data, however, a received character must be read from the spi data register before the next character has been completely shifted in. otherwise, the first byte is lost. in spi slave mode, the control logic will sample th e incoming signal of the sck pin. to ensure correct sampling of the clock signal, the minimum low and high periods should be: low periods: longer than 2 cpu clock cycles. high periods: longer than 2 cpu clock cycles. shift enable 194 9159a?auto?09/10 atmel ata6614 [preliminary] when the spi is enabled, the data direction of the mosi, miso, sck, and ss pins is overrid- den according to table 6-68 on page 194 . for more details on automatic port overrides, refer to ?alternate port functions? on page 105 . note: see ?alternate functions of port b? on page 108 for a detailed description of how to define the direction of the user defined spi pins. the following code examples show how to initia lize the spi as a master and how to perform a simple transmission. ddr_ spi in the examples must be replaced by the actual data direction register controlling the spi pins. dd_mosi, dd_m iso and dd_sck must be replaced by the actual data direction bits for these pins. e.g. if mosi is placed on pin pb5, replace dd_mosi with ddb5 and ddr_spi with ddrb. table 6-68. spi pin overrides (note:) pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ss user defined input 195 9159a?auto?09/10 atmel ata6614 [preliminary] note: 1. see ?about code examples? on page 33. assembly code example (1) spi_masterinit: ; set mosi and sck output, all others input ldi r17,(1< 198 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-68. spi transfer format with cpha = 0 figure 6-69. spi transfer format with cpha = 1 6.18.5 register description 6.18.5.1 spcr ? spi control register ? bit 7 ? spie: spi interrupt enable this bit causes the spi interrupt to be executed if spi f bit in the spsr register is set and the if the global interrupt enable bit in sreg is set. ? bit 6 ? spe: spi enable when the spe bit is written to one, the spi is en abled. this bit must be set to enable any spi operations. bit 1 bit 6 lsb msb sck (cpol = 0) mode 0 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 2 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 msb first (dord = 0) lsb first (dord = 1) sck (cpol = 0) mode 1 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 3 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb first (dord = 0) lsb first (dord = 1) bit 76543210 0x2c (0x4c) spie spe dord mstr cpol cpha spr1 spr0 spcr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 199 9159a?auto?09/10 atmel ata6614 [preliminary] ? bit 5 ? dord: data order when the dord bit is written to one, the lsb of the data word is transmitted first. when the dord bit is written to zero, the msb of the data word is transmitted first. ? bit 4 ? mstr: master/slave select this bit selects master spi mode when written to one, and slave spi mode when written logic zero. if ss is configured as an input and is driven low while mstr is set, mstr will be cleared, and spif in spsr will become set. the us er will then have to set mstr to re-enable spi master mode. ? bit 3 ? cpol: clock polarity when this bit is written to one, sck is high w hen idle. when cpol is written to zero, sck is low when idle . refer to figure 6-68 and figure 6-69 for an example. the cpol functionality is summarized below: ? bit 2 ? cpha: clock phase the settings of the clock phase bit (cpha) determine if data is sampled on the leading (first) or trailing (last) edge of sck. refer to figure 6-68 and figure 6-69 for an example. the cpol functionality is summarized below: ? bits 1, 0 ? spr1, spr0: spi clock rate select 1 and 0 these two bits control the sck rate of the device configured as a master. spr1 and spr0 have no effect on the slave. t he relationship between sck and the oscillator clock frequency f osc is shown in the following table: table 6-70. cpol functionality cpol leading edge trailing edge 0 rising falling 1 falling rising table 6-71. cpha functionality cpha leading edge trailing edge 0 sample setup 1 setup sample table 6-72. relationship between sck and the oscillator frequency spi2x spr1 spr0 sck frequency 000 f osc / 4 001 f osc / 16 010 f osc / 64 011 f osc / 128 100 f osc / 2 101 f osc / 8 110 f osc / 32 111 f osc / 64 200 9159a?auto?09/10 atmel ata6614 [preliminary] 6.18.5.2 spsr ? spi status register ? bit 7 ? spif: spi interrupt flag when a serial transfer is complete, the spif flag is set. an interrupt is generated if spie in spcr is set and global interrupts are enabled. if ss is an input and is driven low when the spi is in master mode, this will also set the spif fl ag. spif is cleared by hardware when execut- ing the corresponding interrupt handling vector. alte rnatively, the spif bit is cleared by first reading the spi status register with spif set, then accessing the spi data register (spdr). ? bit 6 ? wcol: write collision flag the wcol bit is set if the spi data register (spdr) is written during a data transfer. the wcol bit (and the spif bit) are cleared by first reading the spi status register with wcol set, and then accessing the spi data register. ? bit 5..1 ? res: reserved bits these bits are reserved bits in the atmega48pa/88pa/168pa/328p and will always read as zero. ? bit 0 ? spi2x: double spi speed bit when this bit is written logic one the spi s peed (sck frequency) will be doubled when the spi is in master mode (see table 6-72 ). this means that the mi nimum sck period will be two cpu clock periods. when the spi is configured as slave, the spi is only guaranteed to work at f osc /4 or lower. the spi interface on the atmega48pa/88pa/168pa/328p is also used for program memory and eeprom downloading or uploading. see page 333 for serial programming and verification. 6.18.5.3 spdr ? spi data register the spi data register is a read/write register used for data transfer between the register file and the spi shift register. writing to the register initiates data transmission. reading the reg- ister causes the shift register receive buffer to be read. bit 76543210 0x2d (0x4d) spifwcol?????spi2xspsr read/write rrrrrrrr/w initial value00000000 bit 76543210 0x2e (0x4e) msb lsb spdr read/write r/wr/wr/wr/wr/wr/wr/wr/w initial value x x x x x x x x undefined 201 9159a?auto?09/10 atmel ata6614 [preliminary] 6.19 usart0 6.19.1 features ? full duplex operation (independent se rial receive and transmit registers) ? asynchronous or synchronous operation ? master or slave clocked synchronous operation ? high resolution baud rate generator ? supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits ? odd or even parity generation and parity check supported by hardware ? data overrun detection ? framing error detection ? noise filtering includes false start bi t detection and digital low pass filter ? three separate interrupts on tx complete, tx data register empty and rx complete ? multi-processor communication mode ? double speed asynchronous communication mode 6.19.2 overview the universal synchronous and asynchronous se rial receiver and transmitter (usart) is a highly flexible serial communication device. the usart0 can also be used in master spi mode, see ?usart in spi mode? on page 229. the power reduction usart bit, prusart0, in ?minimizing power co nsumption? on page 67 must be disabled by writing a logical zero to it. a simplified block diagram of the usart transmitter is shown in figure 6-70 on page 202 . cpu accessible i/o registers and i/o pins are shown in bold. the dashed boxes in the block diagram separate the three main parts of the usart (listed from the top): clock generator, transmitter and receiver. control registers are shared by all units. the clock generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. the xckn (transfer clock) pin is only used by synchronous transfer mode. the transmitter consists of a single write buffer, a serial shift register, parity generator and control logic for handling different serial frame formats. the write buffer allows a continuous transfer of data without any delay between frames. the receiver is the most complex part of the usart module due to its clock and data recovery units. the recovery units are used for asynchronous data reception. in addi- tion to the recovery units, the receiver includes a parity checker, control logic, a shift register and a two level receive buffer (udrn). the receiver supports the same frame for- mats as the transmitter, and can detect frame error, data overrun and parity errors. 202 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-70. usart block diagram (1) note: 1. refer to table 6-42 on page 114 for usart0 pin placement. 6.19.3 clock generation the clock generation logic generates the base clock for the transmitter and receiver. the usart supports four modes of clock operation: normal asynchronous, double speed asyn- chronous, master synchronous and slave synchronous mode. the umseln bit in usart control and status register c (ucsrnc) selects between asynchronous and synchronous operation. double speed (asynchronous mode on ly) is controlled by the u2xn found in the ucsrna register. when using sy nchronous mode (umseln = 1), the data direction regis- ter for the xckn pin (ddr_xckn) controls whether the clock source is internal (master mode) or external (slave mode). the xckn pin is only active when using synchronous mode. parity generator ubrrn [h:l] udr n(transmit) ucsrna ucsrnb ucsrnc baud rate generator transmit shift register receive shift register rxdn txdn pin control udrn (receive) pin control xckn data recovery clock recovery pin control tx control rx control parity checker data bus osc sync logic clock generator transmitter receiver 203 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-71 shows a block diagram of the clock generation logic. figure 6-71. clock generation logic, block diagram signal description: txclk transmitter clock (internal signal). rxclk receiver base clock (internal signal). xcki input from xck pin (internal signal). used for synchronous slave operation. xcko clock output to xck pin (internal signal). used for synchronous master operation. fosc xtal pin frequency (system clock). 6.19.3.1 internal clock generation ? the baud rate generator internal clock generation is used for the asynchronous and the synchronous master modes of operation. the description in this section refers to figure 6-71 . the usart baud rate register (ubrrn) and the down-counter connected to it function as a programmable prescaler or baud rate generator. the down-counter, running at system clock (f osc ), is loaded with the ubrrn value each time the counter has counted down to zero or when the ubrrnl register is written. a cl ock is generated each time the counter reaches zero. this clock is the baud rate generator clock output (= f osc /(ubrrn+1)). the transmitter divides the baud rate generator clock output by 2, 8 or 16 depending on mode. the baud rate generator output is used directly by the receiver?s clock and data recovery units. however, the recovery units use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the umseln, u2xn and ddr_xckn bits. prescaling down-counter /2 ubrrn /4 /2 foscn ubrrn+1 sync register osc xckn pin txclk u2xn umseln ddr_xckn 0 1 0 1 xcki xcko ddr_xckn rxclk 0 1 1 0 edge detector ucpoln 204 9159a?auto?09/10 atmel ata6614 [preliminary] table 6-73 contains equations for calculating the bau d rate (in bits per second) and for calcu- lating the ubrrn value for each mode of operation using an internally generated clock source. note: 1. the baud rate is defined to be the transfer rate in bit per second (bps) baud baud rate (in bits per second, bps) f osc system oscillator clock frequency ubrrn contents of the ubrrnh and ubrrnl registers, (0-4095) some examples of ubrrn values for some system clock frequencies are found in table 6-81 (see page 225 ). 6.19.3.2 double speed operation (u2xn) the transfer rate can be doubled by setting the u2xn bit in ucsrna. setting this bit only has effect for the asynchronous operation. set this bit to zero when using synchronous operation. setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchrono us communication. note however that the receiver will in this case only use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate setting and system clock are required when this mode is used. for the transmitter, there are no downsides. table 6-73. equations for calculating baud rate register setting operating mode equation for calculating baud rate (1) equation for calculating ubrrn value asynchronous normal mode (u2xn = 0) asynchronous double speed mode (u2xn = 1) synchronous master mode baud f osc 16 ubrr n 1 + () ----------------------------------------- - = ubrr n f osc 16 baud ----------------------- - 1 ? = baud f osc 8 ubrr n 1 + () -------------------------------------- - = ubrr n f osc 8 baud -------------------- 1 ? = baud f osc 2 ubrr n 1 + () -------------------------------------- - = ubrr n f osc 2 baud -------------------- 1 ? = 205 9159a?auto?09/10 atmel ata6614 [preliminary] 6.19.3.3 external clock external clocking is used by t he synchronous slave modes of operation. the description in this section refers to figure 6-71 for details. external clock input from the xckn pin is sampled by a synchronization register to minimize the chance of meta-stability. th e output from the synchronizati on register must then pass through an edge detector before it can be used by the transmitter and receiver. this process introduces a two cpu clock period delay and therefore the maximum external xckn clock fre- quency is limited by the following equation: note that f osc depends on the stability of the system clock source. it is therefor e recommended to add some margin to avoid possible loss of data due to frequency variations. 6.19.3.4 synchronous clock operation when synchronous mode is used (umseln = 1), the xckn pin will be used as either clock input (slave) or clock output (master). the dependency between the clock edges and data sampling or data change is the same. the basic principle is that data input (on rxdn) is sam- pled at the opposite xckn clock edge of the edge the data output (txdn) is changed. figure 6-72. synchronous mode xckn timing. the ucpoln bit ucrsc selects which xckn clock edge is used for data sampling and which is used for data change. as figure 6-72 shows, when ucpoln is zero the data will be changed at rising xckn edge and sampled at falling xckn edge. if ucpoln is set, the data will be changed at falling xckn edge and sampled at ri sing xckn edge. 6.19.4 frame formats a serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. the usart accepts all 30 combina- tions of the following as valid frame formats: ? 1 start bit ? 5, 6, 7, 8, or 9 data bits ? no, even or odd parity bit ? 1 or 2 stop bits f xck f osc 4 ----------- < rxd / txd xck rxd / txd xck ucpol = 0 ucpol = 1 sample sample 206 9159a?auto?09/10 atmel ata6614 [preliminary] a frame starts with the start bit followed by the least significant data bit. then the next data bits, up to a total of nine, are succeeding, endi ng with the most significant bit. if enabled, the parity bit is inserted after the data bits, before the stop bits. when a complete frame is trans- mitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. figure 6-73 illustrates the possible combinations of the frame formats. bits inside brackets are optional. figure 6-73. frame formats st start bit, always low. (n) data bits (0 to 8). p parity bit. can be odd or even. sp stop bit, always high. idle no transfers on the communication line (rxdn or txdn). an idle line must be high. the frame format used by the usart is set by the ucszn2:0, upmn1:0 and usbsn bits in ucsrnb and ucsrnc. the receiver and transmitter use the same setting. note that chang- ing the setting of any of these bits will corrupt all ongoing communication for both the receiver and transmitter. the usart character size (ucszn2:0) bits select the number of data bits in the frame. the usart parity mode (upmn1:0) bits enable and set the type of parity bit. the selection between one or two stop bits is done by the usart stop bit select (usbsn) bit. the receiver ignores the second stop bit. an fe (frame error) will therefore only be detected in the cases where the first stop bit is zero. 6.19.4.1 parity bit calculation the parity bit is calculated by doing an exclusive-or of all the data bits. if odd parity is used, the result of the exclusive or is inverted. the relation between the parity bit and data bits is as follows: p even parity bit using even parity p odd parity bit using odd parity d n data bit n of the character if used, the parity bit is located between the last data bit and first stop bit of a serial frame. 1 0 2 3 4 [5] [6] [7] [8] [p] st sp1 [sp2] (st / idle) (idle) frame p even d n 1 ? d 3 d 2 d 1 d 0 0 p odd d n 1 ? d 3 d 2 d 1 d 0 1 = = 207 9159a?auto?09/10 atmel ata6614 [preliminary] 6.19.5 usart initialization the usart has to be initialized before any communication can take place. the initialization process normally consists of setting the baud rate, setting frame format and enabling the transmitter or the receiver depending on th e usage. for interrupt driven usart operation, the global interrupt flag should be cleared (and interrupts globally disabled) when doing the initialization. before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. the txcn flag can be used to check that the transmitter has completed all transfers, and the rxc flag can be used to check that there are no unread data in the receive buffer. note that the txcn flag must be cleared before each transmission (before udrn is written) if it is used for this purpose. the following simple usart initia lization code examples show one assembly and one c func- tion that are equal in functionality. the examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame fo rmat. the baud rate is given as a function parameter. for the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. 208 9159a?auto?09/10 atmel ata6614 [preliminary] note: 1. see ?about code examples? on page 33. more advanced initialization routines can be made that include frame format as parameters, disable interrupts and so on. however, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine, or be combined with initialization code for other i/o modules. assembly code example (1) usart_init: ; set baud rate out ubrrnh, r17 out ubrrnl, r16 ; enable receiver and transmitter ldi r16, (1< 212 9159a?auto?09/10 atmel ata6614 [preliminary] 6.19.7.1 receiving frames with 5 to 8 data bits the receiver starts data reception when it detects a valid start bit. each bit that follows the start bit will be sampled at the baud rate or xckn clock, and shifted into the receive shift reg- ister until the first stop bit of a frame is received. a second stop bit will be ignored by the receiver. when the first stop bit is received, i.e., a complete serial frame is present in the receive shift register, the content s of the shift register will be moved into the receive buffer. the receive buffer can then be read by reading the udrn i/o location. the following code example shows a simple us art receive function based on polling of the receive complete (rxcn) flag. when using frames with less than eight bits the most signifi- cant bits of the data read from the udrn will be masked to zero. the usart has to be initialized before the function can be used. note: 1. see ?about code examples? on page 33. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructi ons that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. the function simply waits for data to be present in the receive buffer by checking the rxcn flag, before reading the buffer and returning the value. 6.19.7.2 receiving frames with 9 data bits if 9-bit characters are used (ucszn=7) the ninth bit must be read from the rxb8n bit in ucsrnb before reading the low bits from the udrn. th is rule applies to the fen, dorn and upen status flags as well. read status from ucsrna, then data from udrn. reading the udrn i/o location will change the state of the receive buffer fifo and consequently the txb8n, fen, dorn and upen bits, which all are stored in the fifo, will change. the following code example shows a simple usart receive function that handles both nine bit characters and the status bits. assembly code example (1) usart_receive: ; wait for data to be received sbis ucsrna, rxcn rjmp usart_receive ; get and return received data from buffer in r16, udrn ret c code example (1) unsigned char usart_receive( void ) { /* wait for data to be received */ while ( !(ucsrna & (1< 214 9159a?auto?09/10 atmel ata6614 [preliminary] 6.19.7.3 receive compete flag and interrupt the usart receiver has one flag that indicates the receiver state. the receive complete (rxcn) flag indicates if there are unread data present in the receive buffer. this flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). if the receiver is disabled (rxenn = 0), the receive buffer will be flushed and consequently the rxcn bit will become zero. when the receive complete in terrupt enable (rxcien) in ucsrnb is set, the usart receive complete interrupt will be executed as long as the rxcn flag is set (provided that global interrupts are enabled). when interrupt-driven data reception is used, the receive com- plete routine must read the received data from udrn in order to clear the rxcn flag, otherwise a new in terrupt will occur once the inte rrupt routine terminates. 6.19.7.4 receiver error flags the usart receiver has three error flags: frame error (fen), data overrun (dorn) and parity error (upen). all can be accessed by reading ucsrna. common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. due to the buffering of the error flags, the ucsrna must be read before the receive buffer (udrn), since reading the udrn i/o location changes the buffer read location. another equality for the error flags is that they can not be altered by software doing a write to the flag location. however, all flags must be set to zero when the ucsrna is written for upward compatibility of future usart implementations. none of the error flags can generate interrupts. the frame error (fen) flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. the fen flag is zero when the stop bit was correctly read (as one), and the fen flag will be one when the stop bit was incorr ect (zero). this flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. the fen flag is not affected by the setting of the usbsn bit in ucsrnc since the receiver ignores all, except for the first, stop bits. for compatibility with future devices, always set this bit to zero when writing to ucsrna. the data overrun (dorn) flag indicates data loss due to a receiver buffer full condition. a data overrun occurs when the receive buffer is fu ll (two characters), it is a new character waiting in the receive shift register, and a new start bit is detected. if the dorn flag is set there was one or more serial frame lost between the frame last read from udrn, and the next frame read from udrn. for compatib ility with future device s, always write this bit to zero when writing to ucsrna. the dorn flag is cleared when the frame received was successfully moved from the shift register to the receive buffer. the parity error (upen) flag indicates that the next frame in the receive buffer had a parity error when received. if parity check is not enabled the upen bit will always be read zero. for compatibility with future devices, always set this bit to zero when writing to ucsrna. for more details see ?parity bit calculation? on page 206 and ?parity checker? on page 215 . 215 9159a?auto?09/10 atmel ata6614 [preliminary] 6.19.7.5 parity checker the parity checker is active when the high usart parity mode (upmn1) bit is set. type of parity check to be performed (odd or even) is selected by the upmn0 bit. when enabled, the parity checker calculates the parity of the dat a bits in incoming frames and compares the result with the parity bit from the serial frame. the result of the check is stored in the receive buffer together with the received data and stop bits. the parity error (upen) flag can then be read by software to check if the frame had a parity error. the upen bit is set if the next character that can be read from the receive buffer had a parity error when received and the parity checking was enabled at that point (upmn1 = 1). this bit is valid until the receive buffer (udrn) is read. 6.19.7.6 disabling the receiver in contrast to the tran smitter, disabling of the receiver will be immediate. data from ongoing receptions will therefore be lost. when disabled (i.e., the rxenn is set to zero) the receiver will no longer override the normal function of th e rxdn port pin. the receiver buffer fifo will be flushed when the receiver is disabled. remaining data in the buffer will be lost 6.19.7.7 flushing the receive buffer the receiver buffer fifo will be flushed when the receiver is disabled, i.e., the buffer will be emptied of its contents. unread data will be lost . if the buffer has to be flushed during normal operation, due to for instance an error conditi on, read the udrn i/o location until the rxcn flag is cleared. the following code example shows how to flush the receive buffer. note: 1. see ?about code examples? on page 33. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructi ons that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. 6.19.8 asynchronous data reception the usart includes a clock recovery and a data recovery unit for handling asynchronous data reception. the clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the rxdn pin. the data recov- ery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the receiver. the asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. assembly code example (1) usart_flush: sbis ucsrna, rxcn ret in r16, udrn rjmp usart_flush c code example (1) void usart_flush( void ) { unsigned char dummy; while ( ucsrna & (1< 217 9159a?auto?09/10 atmel ata6614 [preliminary] if two or all three samples have low levels, the re ceived bit is registered to be a logic 0. this majority voting process acts as a low pass filter for the incoming signal on the rxdn pin. the recovery process is then repeated until a complete frame is received. including the first stop bit. note that the receiver only uses the first stop bit of a frame. figure 6-76 on page 217 shows the sampling of the stop bit and the earliest possible begin- ning of the start bit of the next frame. figure 6-76. stop bit sampling and ne xt start bit sampling the same majority voting is done to the stop bit as done for the other bits in the frame. if the stop bit is registered to have a logic 0 value, the frame error (fen) flag will be set. a new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting. for normal speed mode, the first low level sample can be at point marked (a) in figure 6-76 . for double speed mode the fi rst low level must be delayed to (b). (c) marks a stop bit of full length. the early start bit detection influences the operational range of the receiver. 6.19.8.3 asynchronous operational range the operational range of the receiver is depe ndent on the mismatch between the received bit rate and the internally generated baud rate. if the transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud rate of the receiver does not have a similar (see table 6-74 on page 218 ) base frequency, the receiver w ill not be able to synchronize the frames to the start bit. the following equations can be used to calculate the ratio of the incoming data rate and inter- nal receiver baud rate. d sum of character size and parity size (d = 5 to 10 bit) s samples per bit. s = 16 for normal speed mode and s = 8 for double speed mode. s f first sample number used for majority voting. s f = 8 for normal speed and s f = 4 for double speed mode. s m middle sample number used for majority voting. s m = 9 for normal speed and s m = 5 for double speed mode. r slow is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate. r fast is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate. 1234567 8 9 10 0/1 0/1 0/1 stop 1 123 4 5 6 0/1 rxd sample (u2x = 0) sample (u2x = 1) (a) (b) (c) r slow d 1 + () s s 1 ? ds ? s f ++ --------------------------------------------- = r fast d 2 + () s d 1 + () ss m + ----------------------------------- = 218 9159a?auto?09/10 atmel ata6614 [preliminary] table 6-74 on page 218 and table 6-75 on page 218 list the maximum receiver baud rate error that can be tolerated. note that normal speed mode has higher toleration of baud rate variations. the recommendations of the maximum receiver baud rate error was made under the assump- tion that the receiver and transmitter equally divides the maximum total error. there are two possible sources for the receivers baud rate error. the receiver?s system clock (xtal) will always have some minor instability ov er the supply voltage range and the temper- ature range. when using a crystal to generate the system clock, this is rarely a problem, but for a resonator the system clock may differ more than 2% depen ding of the resonators toler- ance. the second source for the error is more controllable. the baud rate generator can not always do an exact division of the system frequency to get the baud rate wanted. in this case an ubrrn value that gives an acceptable low error can be used if possible. 6.19.9 multi-processor communication mode setting the multi-processor communication mode (mpcmn) bit in ucsrna enables a filtering function of incoming frames received by the usart receiver. frames that do not contain address information will be ignored and not put into the receive bu ffer. this effectively reduces the number of incoming frames that has to be handled by the cpu, in a system with multiple mcus that communicate via the same serial bus. the transmitter is unaffected by the mpcmn setting, but has to be used differently when it is a part of a system utilizing the multi-processor communication mode. table 6-74. recommended maximum receiver baud rate error for normal speed mode (u2xn = 0) d # (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 93.20 106.67 +6.67/-6.8 3.0 6 94.12 105.79 +5.79/-5.88 2.5 7 94.81 105.11 +5.11/-5.19 2.0 8 95.36 104.58 +4.58/-4.54 2.0 9 95.81 104.14 +4.14/-4.19 1.5 10 96.17 103.78 +3.78/-3.83 1.5 table 6-75. recommended maximum receiver baud rate error for double speed mode (u2xn = 1) d # (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 94.12 105.66 +5.66/-5.88 2.5 6 94.92 104.92 +4.92/-5.08 2.0 7 95.52 104,35 +4.35/-4.48 1.5 8 96.00 103.90 +3.90/-4.00 1.5 9 96.39 103.53 +3.53/-3.61 1.5 10 96.70 103.23 +3.23/-3.30 1.0 219 9159a?auto?09/10 atmel ata6614 [preliminary] if the receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indicates if the frame contains data or address information. if the receiver is set up for frames with nine data bits, then the ninth bit (rxb8n) is used for identifying address and data frames. when the frame type bit (the first stop or the ni nth bit) is one, the frame contains an address. when the frame type bit is zero the frame is a data frame. the multi-processor communication mode enables several slave mcus to receive data from a master mcu. this is done by first decoding an address frame to find out which mcu has been addressed. if a particular slave mcu has been addressed, it will receive the following data frames as normal, while the other slave mcus will ignore the received frames until another address frame is received. 6.19.9.1 using mpcmn for an mcu to act as a master mcu, it can use a 9-bit character frame format (ucszn = 7). the ninth bit (txb8n) must be set when an address frame (txb8n = 1) or cleared when a data frame (txb = 0) is being transmitted. the slave mcus must in this case be set to use a 9-bit character frame format. the following procedure should be used to exchange data in multi-processor communication mode: 1. all slave mcus are in multi-proc essor communication mode (mpcmn in ucsrna is set). 2. the master mcu sends an address frame, and all slaves receive and read this frame. in the slave mcus, the rxcn flag in ucsrna will be set as normal. 3. each slave mcu reads the udrn register and determines if it has been selected. if so, it clears the mpcmn bit in ucsrna, otherwise it waits for the next address byte and keeps the mpcmn setting. 4. the addressed mcu will receive all data fram es until a new address frame is received. the other slave mcus, which still have the mp cmn bit set, will ignore the data frames. 5. when the last data frame is received by the addressed mcu, the addressed mcu sets the mpcmn bit and waits for a new address frame from master. the process then repeats from 2. using any of the 5- to 8-bit character frame formats is possible, but impractical since the receiver must change between using n and n+1 character frame formats. this makes full-duplex operation difficult since the transmi tter and receiver uses the same character size setting. if 5- to 8-bit character frames are used , the transmitter must be set to use two stop bit (usbsn = 1) since the first stop bit is used for indicating the frame type. do not use read-modify-write instructions (sbi and cbi) to set or clear the mpcmn bit. the mpcmn bit shares the same i/o location as the txcn flag and this might accidentally be cleared when using sbi or cbi instructions. 220 9159a?auto?09/10 atmel ata6614 [preliminary] 6.19.10 register description 6.19.10.1 udrn ? usart i/o data register n the usart transmit data buffer register a nd usart receive data buffer registers share the same i/o address referred to as usart data register or udrn. the transmit data buffer register (txb) will be the destination for data wr itten to the udrn regi ster location. reading the udrn register location will re turn the contents of the receiv e data buffer register (rxb). for 5-, 6-, or 7-bit characters the upper unused bits will be ignored by th e transmitter and set to zero by the receiver. the transmit buffer can only be written when the udren flag in the uc srna register is set. data written to udrn when the udren flag is not set, will be ignored by the usart trans- mitter. when data is written to the transmit buffer, and the transmitter is enabled, the transmitter will load the data into the transmit sh ift register when the sh ift register is empty. then the data will be serially transmitted on the txdn pin. the receive buffer consists of a two level fi fo. the fifo will change its state whenever the receive buffer is accessed. due to this behavior of the receive buffer, do not use read-mod- ify-write instructions ( sbi and cbi) on this location. be ca reful when using bit test instructions (sbic and sbis), since these also will change the state of the fifo. 6.19.10.2 ucsrna ? usart control and status register n a ? bit 7 ? rxcn: usart receive complete this flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain an y unread data). if the receiver is disabled, the receive buffer will be flushed and consequen tly the rxcn bit will become zero. the rxcn flag can be used to generate a receive complete interrupt (see description of the rxcien bit). ? bit 6 ? txcn: usart transmit complete this flag bit is set when the entire frame in the transmit shift register has been shifted out and there are no new data currently present in the transmit buffer (udrn). the txcn flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. the txcn flag can generate a transmit complete interrupt (see description of the txcien bit). ? bit 5 ? udren: usart data register empty the udren flag indicates if the transmit buff er (udrn) is ready to receive new data. if udren is one, the buffer is empty, and therefore ready to be written. the udren flag can generate a data register empty interrup t (see description of the udrien bit). udren is set after a reset to indicate that the transmitter is ready. bit 76543210 rxb[7:0] udrn (read) txb[7:0] udrn (write) read/write r/wr/wr/wr/wr/wr/wr/wr/w initial value 0 0 0 0 0 0 0 0 bit 76543210 rxcn txcn udren fen dorn upen u2xn mpcmn ucsrna read/write r r/w r r r r r/w r/w initial value 0 0 1 0 0 0 0 0 221 9159a?auto?09/10 atmel ata6614 [preliminary] ? bit 4 ? fen: frame error this bit is set if the next character in the receive buffer had a frame error when received. i.e., when the first stop bit of the next character in the receive buffer is zero. this bit is valid until the receive buffer (udrn) is read. the fen bit is zero when the stop bit of received data is one. always set this bit to zero when writing to ucsrna. ? bit 3 ? dorn: data overrun this bit is set if a data overrun condition is detected. a data overrun occurs when the receive buffer is full (two charac ters), it is a new character wa iting in the receive shift regis- ter, and a new start bit is dete cted. this bit is valid until the receive buffer (udrn) is read. always set this bit to ze ro when writing to ucsrna. ? bit 2 ? upen: usart parity error this bit is set if the next character in the re ceive buffer had a parity error when received and the parity checking was enabled at that point (upmn1 = 1). this bit is valid until the receive buffer (udrn) is read. always set this bit to zero when writing to ucsrna. ? bit 1 ? u2xn: double the usart transmission speed this bit only has effect for the asynchronous operation. write this bit to zero when using syn- chronous operation. writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. ? bit 0 ? mpcmn: multi-processor communication mode this bit enables the multi-processor communica tion mode. when the mpcmn bit is written to one, all the incoming frames received by the usart receiver that do not contain address information will be ignored. the tr ansmitter is unaffected by the mpcmn setting. for more detailed information see ?multi-processor communication mode? on page 218 . 6.19.10.3 ucsrnb ? usart control and status register n b ? bit 7 ? rxcien: rx comp lete interrupt enable n writing this bit to one enables interrupt on th e rxcn flag. a usart receive complete inter- rupt will be generated only if the rxcien bit is written to one, the global interrupt flag in sreg is written to one and the rxcn bit in ucsrna is set. ? bit 6 ? txcien: tx complete interrupt enable n writing this bit to one enable s interrupt on the txcn flag. a usart transmit complete inter- rupt will be generated only if the txcien bit is written to one, the global interrupt flag in sreg is written to one and the txcn bit in ucsrna is set. bit 7 6 5 4 3 2 1 0 rxcien txcien udrien rxenn txe nn ucszn2 rxb8n txb8n ucsrnb read/write r/w r/w r/w r/w r/w r/w r r/w initial value 0 0 0 0 0 0 0 0 222 9159a?auto?09/10 atmel ata6614 [preliminary] ? bit 5 ? udrien: usart data register empty interrupt enable n writing this bit to one enables interrupt on the udren flag. a data register empty interrupt will be generated only if t he udrien bit is written to one, th e global interrupt flag in sreg is written to one and the udren bit in ucsrna is set. ? bit 4 ? rxenn: receiver enable n writing this bit to one enables the usart re ceiver. the receiver will override normal port operation for the rxdn pin when enabled. disabling the receiver will flush the receive buffer invalidating the fen, dorn, and upen flags. ? bit 3 ? txenn: transmitter enable n writing this bit to one enables the usart trans mitter. the transmitter will override normal port operation for the txdn pin when enabled. th e disabling of the transmitter (writing txenn to zero) will not become effective until ongoing and pending transm issions are completed, i.e., when the transmit shift register and transmit buffer register do not contain data to be trans- mitted. when disabled, the transmitter will no longer override the txdn port. ? bit 2 ? ucszn2: character size n the ucszn2 bits combined with the ucszn1:0 bi t in ucsrnc sets the number of data bits (character size) in a frame the receiver and transmitter use. ? bit 1 ? rxb8n: receive data bit 8 n rxb8n is the ninth data bit of the received c haracter when operating with serial frames with nine data bits. must be read before reading the low bits from udrn. ? bit 0 ? txb8n: transmit data bit 8 n txb8n is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. must be written before writing the low bits to udrn. 6.19.10.4 ucsrnc ? usart control and status register n c ? bits 7:6 ? umseln1:0 usart mode select these bits select the mode of operation of the usartn as shown in table 6-76 . note: 1. see ?usart in spi mode? on page 229 for full description of the master spi mode (mspim) operation bit 7 6 5 4 3 2 1 0 umseln1 umseln0 upmn1 upmn0 us bsn ucszn1 ucszn0 ucpoln ucsrnc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 1 1 0 table 6-76. umseln bits settings umseln1 umseln0 mode 0 0 asynchronous usart 0 1 synchronous usart 1 0 (reserved) 1 1 master spi (mspim) (1) 223 9159a?auto?09/10 atmel ata6614 [preliminary] ? bits 5:4 ? upmn1:0: parity mode these bits enable and set type of parity generation and check. if enabl ed, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. the receiver will generate a parity value for the incomi ng data and compare it to the upmn set- ting. if a mismatch is detected, the upen flag in ucsrna will be set. ? bit 3 ? usbsn: stop bit select this bit selects the number of stop bits to be inserted by the transmitter. the receiver ignores this setting. ? bit 2:1 ? ucszn1:0: character size the ucszn1:0 bits combined with the ucszn2 bi t in ucsrnb sets the number of data bits (character size) in a frame the receiver and transmitter use. ? bit 0 ? ucpoln: clock polarity this bit is used for synchronous mode only. write this bit to zero when asynchronous mode is used. the ucpoln bit sets the relationship between data output change and data input sam- ple, and the synchronous clock (xckn). table 6-77. upmn bits settings upmn1 upmn0 parity mode 00disabled 01reserved 1 0 enabled, even parity 1 1 enabled, odd parity table 6-78. usbs bit settings usbsn stop bit(s) 01-bit 12-bit table 6-79. ucszn bits settings ucszn2 ucszn1 ucszn0 character size 0 0 0 5-bit 0 0 1 6-bit 0 1 0 7-bit 0 1 1 8-bit 100reserved 101reserved 110reserved 1 1 1 9-bit 224 9159a?auto?09/10 atmel ata6614 [preliminary] 6.19.10.5 ubrrnl and ubrrnh ? usart baud rate registers ? bit 15:12 ? reserved bits these bits are reserved for future use. for compatibility with future devices, these bit must be written to zero when ubrrnh is written. ? bit 11:0 ? ubrr11:0: usart baud rate register this is a 12-bit register which contains the usart baud rate. the ubrrnh contains the four most significant bits, and the ubrrnl contains the eight least significant bits of the usart baud rate. ongoing transmissions by the trans mitter and receiver will be corrupted if the baud rate is changed. writi ng ubrrnl will trigger an im mediate update of the baud rate prescaler. 6.19.11 examples of baud rate setting for standard crystal and resonator frequencies, the most commonly used baud rates for asyn- chronous operation can be generated by using the ubrrn settings in table 6-81 . ubrrn values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table. higher error ratings are ac ceptable, but the receiver will have less noise resistance when the error ratings are high, especially for large serial frames (see ?asynchro- nous operational range? on page 217 ). the error values are calculated using the following equation: table 6-80. ucpoln bit settings ucpoln transmitted data changed (output of txdn pin) received data sampled (input on rxdn pin) 0 rising xckn edge falling xckn edge 1 falling xckn edge rising xckn edge bit 151413121110 9 8 ? ? ? ? ubrrn[11:8] ubrrnh ubrrn[7:0] ubrrnl 76543210 read/write r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 00000000 error[%] baudrate closest match baudrate -------------------------------------------------------- 1 ? ?? ?? 100% ? = 225 9159a?auto?09/10 atmel ata6614 [preliminary] note: 1. ubrrn = 0, error = 0.0% table 6-81. examples of ubrrn settings for co mmonly used oscillator frequencies baud rate (bps) f osc = 1.0000mhz f osc = 1.8432mhz f osc = 2.0000mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 120.2%250.2%230.0%470.0%250.2%510.2% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5% 76.8k ? ? 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5% 115.2k ? ? 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5% 230.4k??????00.0%???? 250k??????????00.0% max. (1) 62.5kbps 125kbps 115.2kbps 230.4kbps 125kbps 250kbps 226 9159a?auto?09/10 atmel ata6614 [preliminary] table 6-82. examples of ubrrn settings for common ly used oscillator frequencies (continued) baud rate (bps) f osc = 3.6864mhz f osc = 4.0000mhz f osc = 7.3728mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 230.0%470.0%250.2%510.2%470.0%950.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0. 2% 25 0.2% 23 0.0% 47 0.0% 28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0% 38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0% 230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0% 250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8% 0.5m ? ? 0 -7.8% ? ? 0 0.0% 0 -7.8% 1 -7.8% 1m ??????????0-7.8% max. (1) 230.4kbps 460.8kbps 250kbps 0.5 bps 460.8kbps 921.6kbps 1. ubrrn = 0, error = 0.0% 227 9159a?auto?09/10 atmel ata6614 [preliminary] table 6-83. examples of ubrrn settings for common ly used oscillator frequencies (continued) baud rate (bps) f osc = 8.0000mhz f osc = 11.0592 mhz f osc = 14.7456mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.2% 51 0.2% 35 0. 0% 71 0.0% 47 0.0% 95 0.0% 28.8k 16 2.1% 34 -0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0% 38.4k 12 0.2% 25 0.2% 17 0. 0% 35 0.0% 23 0.0% 47 0.0% 57.6k 8 -3.5% 16 2.1% 11 0. 0% 23 0.0% 15 0.0% 31 0.0% 76.8k 6 -7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0% 115.2k 3 8.5% 8 -3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0% 230.4k 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0% 250k 1 0.0% 3 0.0% 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3% 0.5m 0 0.0% 1 0.0% ? ? 2 -7.8% 1 -7.8% 3 -7.8% 1m ??00.0%????0-7.8%1-7.8% max. (1) 0.5mbps 1mbps 691.2kbps 1. 3824mbps 921.6kbps 1.8432mbps 1. ubrrn = 0, error = 0.0% 228 9159a?auto?09/10 atmel ata6614 [preliminary] table 6-84. examples of ubrrn settings for common ly used oscillator frequencies (continued) baud rate (bps) f osc = 16.0000mhz f osc = 18.4320mhz f osc = 20.0000mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2% 19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2% 28.8k 34 -0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 -0.2% 38.4k 25 0.2% 51 0.2% 29 0.0% 59 0.0% 32 -1.4% 64 0.2% 57.6k 16 2.1% 34 -0.8% 19 0.0% 39 0.0% 21 -1.4% 42 0.9% 76.8k 12 0.2% 25 0.2% 14 0.0% 29 0.0% 15 1.7% 32 -1.4% 115.2k 8 -3.5% 16 2.1% 9 0.0% 19 0.0% 10 -1.4% 21 -1.4% 230.4k 3 8.5% 8 -3.5% 4 0.0% 9 0.0% 4 8.5% 10 -1.4% 250k 3 0.0% 7 0.0% 4 -7.8% 8 2.4% 4 0.0% 9 0.0% 0.5m 1 0.0% 3 0.0% ? ? 4 -7.8% ? ? 4 0.0% 1m 00.0%10.0%???????? max. (1) 1mbps 2mbps 1.152mbps 2.304 bps 1.25mbps 2.5mbps 1. ubrrn = 0, error = 0.0% 229 9159a?auto?09/10 atmel ata6614 [preliminary] 6.20 usart in spi mode 6.20.1 features ? full duplex, three-wire synchronous data transfer ? master operation ? supports all four spi modes of operation (mode 0, 1, 2, and 3) ? lsb first or msb first data tran sfer (configurable data order) ? queued operation (double buffered) ? high resolution baud rate generator ? high speed operation (f xckmax = f ck /2) ? flexible interrupt generation 6.20.2 overview the universal synchronous and asynchronous serial receiver and transmitter (usart) can be set to a master spi compliant mode of operation. setting both umseln1:0 bits to one enables the usart in mspim logic. in this mode of oper- ation the spi master control logic takes dire ct control over the usart resources. these resources include the transmitter and receiver shift register and buffers, and the baud rate generator. the parity generator and checker, the data and clock recovery logic, and the rx and tx control logic is disabled. the usart rx and tx control logic is replaced by a com- mon spi transfer control logic. however, the pin control logic and interrupt generation logic is identical in both modes of operation. the i/o register locations are the same in both modes. however, some of the functionality of the control registers changes when using mspim. 6.20.3 clock generation the clock generation logic generates the base clock for the transmitter and receiver. for usart mspim mode of operation only internal clock generation (i.e. master operation) is supported. the data direction register for the xckn pin (ddr_xckn) must therefore be set to one (i.e. as output) for the usart in mspim to operate correctly. preferably the ddr_xckn should be set up before the usart in mspim is enabled (i.e. txenn and rxenn bit set to one). the internal clock generation used in mspim mode is identical to the usart synchronous master mode. the baud rate or ubrrn setting can therefore be calculated using the same equations, see table 6-85 : table 6-85. equations for calculating baud rate register setting operating mode equation for calculating baud rate (1) equation for calculating ubrrn value synchronous master mode baud f osc 2 ubrr n 1 + () -------------------------------------- - = ubrr n f osc 2 baud -------------------- 1 ? = 230 9159a?auto?09/10 atmel ata6614 [preliminary] note: 1. the baud rate is defined to be the transfer rate in bit per second (bps) baud baud rate (in bits per second, bps) f osc system oscillator clock frequency ubrrn contents of the ubrrnh and ubrrnl registers, (0-4095) 6.20.4 spi data modes and timing there are four combinations of xckn (sck) phase and polarity with respect to serial data, which are determined by control bits ucphan and ucpoln. the data transfer timing dia- grams are shown in figure 6-77 . data bits are shifted out and latched in on opposite edges of the xckn signal, ensuring su fficient time for data signals to stabilize. the ucpoln and ucphan functionality is summarized in table 6-86 . note that changing the setting of any of these bits will corrupt all ongoing communication for both the receiver and transmitter. figure 6-77. ucphan and ucpoln data transfer timing diagrams. 6.20.5 frame formats a serial frame for the mspim is defined to be one character of 8 data bits. the usart in mspim mode has two valid frame formats: ? 8-bit data with msb first ? 8-bit data with lsb first a frame starts with the least or most significant data bit. then the next data bits, up to a total of eight, are succeeding, ending with the most or least significant bit accordingly. when a com- plete frame is transmitted, a new frame can directly follow it, or the communication line can be set to an idle (high) state. table 6-86. ucpoln and ucphan functionality- ucpoln ucphan spi mode lead ing edge trailing edge 0 0 0 sample (rising) setup (falling) 0 1 1 setup (rising) sample (falling) 1 0 2 sample (falling) setup (rising) 1 1 3 setup (falling) sample (rising) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) ucpol=0 ucpol=1 ucpha=0 ucpha=1 231 9159a?auto?09/10 atmel ata6614 [preliminary] the udordn bit in ucsrnc sets the frame fo rmat used by the usart in mspim mode. the receiver and transmitter use the same setting. note that changing the setting of any of these bits will corrupt all ongoing communication for both the receiver and transmitter. 16-bit data transfer can be achieved by writing two data bytes to udrn. a uart transmit com- plete interrupt will then signal that the 16-bit value ha s been shifted out. 6.20.5.1 usart mspim initialization the usart in mspim mode has to be initialized before any communication can take place. the initialization process normally consists of setting the baud rate, setting master mode of operation (by setting ddr_xckn to one), setting frame format and enabling the transmitter and the receiver. only the transmitter can operate independently. for interrupt driven usart operation, the global interrupt flag should be cleared (and thus interrupts globally disabled) when doing the initialization. note: to ensure immediate initialization of the xckn output the baud-rate r egister (ubrrn) must be zero at the time the transmitter is enabled. contrary to the normal mode usart operation the ubrrn must then be written to the desired value af ter the transmitter is enabled, but before the first transmission is started. setting ubrrn to ze ro before enabling the transmitter is not neces- sary if the initialization is done immediately after a reset since ubrrn is reset to zero. before doing a re-initialization with changed baud rate, data mode, or frame format, be sure that there is no ongoing transmissions during the period the registers are changed. the txcn flag can be used to check that the transmitt er has completed all transfers, and the rxcn flag can be used to check that there are no unread data in the receive buffer. note that the txcn flag must be cleared before each transmission (before udrn is writte n) if it is used for this purpose. the following simple usart initia lization code examples show one assembly and one c func- tion that are equal in functionality. the exampl es assume polling (no interrupts enabled). the baud rate is given as a function parameter. for the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. 232 9159a?auto?09/10 atmel ata6614 [preliminary] note: 1. see ?about code examples? on page 33. assembly code example (1) usart_init: clr r18 out ubrrnh,r18 out ubrrnl,r18 ; setting the xckn port pin as output, enables master mode. sbi xckn_ddr, xckn ; set mspi mode of operation and spi data mode 0. ldi r18, (1< 234 9159a?auto?09/10 atmel ata6614 [preliminary] note: 1. see ?about code examples? on page 33. 6.20.6.1 transmitter and receiver flags and interrupts the rxcn, txcn, and udren flags and correspon ding interrupts in usart in mspim mode are identical in function to the normal usart operation. however, the receiver error status flags (fe, dor, and pe) are not in use and is always read as zero. 6.20.6.2 disabling the transmitter or receiver the disabling of the transmitter or receiver in usart in mspim mode is identical in function to the normal usart operation. assembly code example (1) usart_mspim_transfer: ; wait for empty transmit buffer sbis ucsrna, udren rjmp usart_mspim_transfer ; put data (r16) into buffer, sends the data out udrn,r16 ; wait for data to be received usart_mspim_wait_rxcn: sbis ucsrna, rxcn rjmp usart_mspim_wait_rxcn ; get and return received data from buffer in r16, udrn ret c code example (1) unsigned char usart_receive( void ) { /* wait for empty transmit buffer */ while ( !( ucsrna & (1< 236 9159a?auto?09/10 atmel ata6614 [preliminary] 6.20.8 register description the following section describes the registers used for spi operation using the usart. 6.20.8.1 udrn ? usart mspim i/o data register the function and bit description of the usart data register (udrn) in mspi mode is identical to normal usart operation. see ?udrn ? usart i/o data register n? on page 220. 6.20.8.2 ucsrna ? usart mspim control and status register n a ? bit 7 - rxcn: usart receive complete this flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain an y unread data). if the receiver is disabled, the receive buffer will be flushed and consequen tly the rxcn bit will become zero. the rxcn flag can be used to generate a receive complete interrupt (see description of the rxcien bit). ? bit 6 - txcn: usart transmit complete this flag bit is set when the entire frame in the transmit shift register has been shifted out and there are no new data currently present in the transmit buffer (udrn). the txcn flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. the txcn flag can generate a transmit complete interrupt (see description of the txcien bit). ? bit 5 - udren: usart data register empty the udren flag indicates if the transmit buff er (udrn) is ready to receive new data. if udren is one, the buffer is empty, and therefore ready to be written. the udren flag can generate a data register empty interrupt (see description of the udrie bit). udren is set after a reset to indicate that the transmitter is ready. ? bit 4:0 - reserved bits in mspi mode when in mspi mode, these bits are reserved for future use. for compatibility with future devices, these bits must be written to zero when ucsrna is written. 6.20.8.3 ucsrnb ? usart mspim control and status register n b ? bit 7 - rxcien: rx complete interrupt enable writing this bit to one enables interrupt on th e rxcn flag. a usart receive complete inter- rupt will be generated only if the rxcien bit is written to one, the global interrupt flag in sreg is written to one and the rxcn bit in ucsrna is set. bit 7 6 5 4 3 2 1 0 rxcn txcn udren - - - - - ucsrna read/write r r/w r r r r r r initial value 0 0 0 0 0 1 1 0 bit 7 6543210 rxcien txcien udrie rxenn txenn - - - ucsrnb read/write r/w r/w r/w r/w r/w r r r initial value 0 0 0 0 0 1 1 0 237 9159a?auto?09/10 atmel ata6614 [preliminary] ? bit 6 - txcien: tx complete interrupt enable writing this bit to one enable s interrupt on the txcn flag. a usart transmit complete inter- rupt will be generated only if the txcien bit is written to one, the global interrupt flag in sreg is written to one and the txcn bit in ucsrna is set. ? bit 5 - udrie: usart data re gister empty interrupt enable writing this bit to one enables interrupt on the udren flag. a data register empty interrupt will be generated only if the udrie bit is written to one, the global interrupt flag in sreg is written to one and the udren bit in ucsrna is set. ? bit 4 - rxenn: receiver enable writing this bit to one enables the usart receiv er in mspim mode. the receiver will over- ride normal port operation for the rxdn pin when enabled. dis abling the receiver will flush the receive buffer. only enabling t he receiver in mspi mode (i.e. setting rxenn=1 and txenn=0) has no meaning since it is the transmitter that controls the transfer clock and since only master mode is supported. ? bit 3 - txenn: transmitter enable writing this bit to one enables the usart trans mitter. the transmitter will override normal port operation for the txdn pin when enabled. th e disabling of the transmitter (writing txenn to zero) will not become effective until ongoing and pending transm issions are completed, i.e., when the transmit shift register and transmit buffer register do not contain data to be trans- mitted. when disabled, the transmitter will no longer override the txdn port. ? bit 2:0 - reserved bits in mspi mode when in mspi mode, these bits are reserved for future use. for compatibility with future devices, these bits must be written to zero when ucsrnb is written. 6.20.8.4 ucsrnc ? usart mspim control and status register n c ? bit 7:6 - umseln1:0: usart mode select these bits select the mode of operation of the usart as shown in table 6-88 . see ?ucsrnc ? usart control and status register n c? on page 222 for full description of the normal usart operation. the mspim is enabled when both umseln bits are set to one. the udordn, ucphan, and ucpoln can be set in the same write operation where the mspim is enabled. bit 7 6 5 4 3 2 1 0 umseln1 umseln0 - - - udordn ucphan ucpoln ucsrnc read/write r/w r/w r r r r/w r/w r/w initial value 0 0 0 0 0 1 1 0 table 6-88. umseln bits settings umseln1 umseln0 mode 0 0 asynchronous usart 0 1 synchronous usart 1 0 reserved 1 1 master spi (mspim) 238 9159a?auto?09/10 atmel ata6614 [preliminary] ? bit 5:3 - reserved bits in mspi mode when in mspi mode, these bits are reserved for future use. for compatibility with future devices, these bits must be written to zero when ucsrnc is written. ? bit 2 - udordn: data order when set to one the lsb of the data word is transmitted first. when set to zero the msb of the data word is transmitted first. refer to the frame formats section page 4 for details. ? bit 1 - ucphan: clock phase the ucphan bit setting determine if data is samp led on the leasing edge (first) or tailing (last) edge of xckn. refer to the spi data modes and timing section page 4 for details. ? bit 0 - ucpoln: clock polarity the ucpoln bit sets the polarity of the xckn clock. the combination of the ucpoln and ucphan bit settings determine the timing of the data transfer. refer to the spi data modes and timing section page 4 for details. 6.20.8.5 usart mspim baud rate registers - ubrrnl and ubrrnh the function and bit description of the baud rate registers in mspi mode is identical to normal usart operation. see ?ubrrnl and ubrrnh ? usart baud rate registers? on page 224. 239 9159a?auto?09/10 atmel ata6614 [preliminary] 6.21 2-wire serial interface 6.21.1 features ? simple yet powerful and flexible communication interface, only two bus lines needed ? both master and sla ve operation supported ? device can operate as transmitter or receiver ? 7-bit address space allows up to 128 different slave addresses ? multi-master arbitration support ? up to 400 khz data transfer speed ? slew-rate limited output drivers ? noise suppression circuitry re jects spikes on bus lines ? fully programmable slave address with general call support ? address recognition causes wake-up when avr is in sleep mode ? compatible with philips? i 2 c protocol 6.21.2 2-wire serial interface bus definition the 2-wire serial interface (twi) is ideally su ited for typical microcontroller applications. the twi protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for clock (scl) and one for data (sda). the only external hardware needed to implement the bus is a single pull-up resistor for each of the twi bus lines. all devices connected to the bus have indi vidual addresses, and mechanisms for resolv- ing bus contention are inherent in the twi protocol. figure 6-78. twi bus interconnection device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc 240 9159a?auto?09/10 atmel ata6614 [preliminary] 6.21.2.1 twi terminology the following definitions are frequently encountered in this section. the prtwi bit in ?minimizing power consumption? on page 67 must be written to zero to enable the 2-wire serial interface. 6.21.2.2 electrical interconnection as depicted in figure 6-78 , both bus lines are connected to the positive supply voltage through pull-up resistors. the bus drivers of all twi- compliant devices are open-drain or open-collec- tor. this implements a wired-and fu nction which is essential to the operation of the interface. a low level on a twi bus line is generated when one or more twi devices output a zero. a high level is output when all twi devices tri-state their outputs, allowing the pull-up resistors to pull the line high. note that all avr devices connected to the twi bus must be powered in order to allow any bus operation. the number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400pf and the 7-bit slave address space. a detailed specification of the electrical char- acteristics of the twi is given in ?2-wire serial interface characteristics? on page 346 . two different sets of specifications are present ed there, one relevant for bus speeds below 100khz, and one valid for bus speeds up to 400khz. table 6-89. twi terminology term description master the device that initiates and terminates a transmission. the master also generates the scl clock. slave the device addressed by a master. transmitter the device placing data on the bus. receiver the device reading data from the bus. 241 9159a?auto?09/10 atmel ata6614 [preliminary] 6.21.3 data transfer and frame format 6.21.3.1 transferring bits each data bit transferred on the twi bus is accompanied by a pulse on the clock line. the level of the data line must be stable when the clock line is high. the only exception to this rule is for generating start and stop conditions. figure 6-79. data validity 6.21.3.2 start and stop conditions the master initiates and terminates a data transmission. the transmission is initiated when the master issues a start condition on the bus, and it is terminated when the master issues a stop condition. between a start and a stop condition, the bus is considered busy, and no other master should try to seize control of the bus. a special case occurs when a new start condition is issued between a start and st op condition. this is referred to as a repeated start condition, and is used when the master wishes to initiate a new transfer without relinquishing control of the bus. afte r a repeated start, the bus is considered busy until the next stop. this is identical to the start behavior, and therefore start is used to describe both start and repeated start for the re mainder of this datasheet, unless otherwise noted. as depicted below, start and stop conditions are signalled by changing the level of the sda line when the scl line is high. figure 6-80. start, repeated start and stop conditions sda scl data stable data stable data change sda scl start stop repeated start stop start 242 9159a?auto?09/10 atmel ata6614 [preliminary] 6.21.3.3 address packet format all address packets transmitted on the twi bus ar e 9 bits long, consisting of 7 address bits, one read/write control bit and an acknowledge bit. if the read/write bit is set, a read operation is to be performed, otherwise a write operation should be performed. when a slave recognizes that it is being addressed, it should acknowledge by pulling sda low in the ninth scl (ack) cycle. if the addressed slave is busy , or for some other reason can not service the master?s request, the sda line should be left high in the ack clock cycle. the master can then transmit a stop condition, or a repeated start condition to initiate a new transmission. an address packet consisting of a slave address and a read or a write bit is called sla+r or sla+w, respectively. the msb of the address byte is transmitted first. slave addresses can freely be allocated by the designer, but the address 0000 000 is reserved for a general call. when a general call is issued, all slaves shoul d respond by pulling the sda line low in the ack cycle. a general call is used when a master wishes to transmit the same message to sev- eral slaves in the system. when the general call address followed by a write bit is transmitted on the bus, all slaves set up to acknowledge the general call will pull the sda line low in the ack cycle. the following data pa ckets will then be received by all the slaves that acknowl- edged the general call. note that transmitting the general call address followed by a read bit is meaningless, as this would cause contention if several slaves started transmitting different data. all addresses of the format 1111 xxx should be reserved for future purposes. figure 6-81. address packet format 6.21.3.4 data packet format all data packets transmitted on the twi bus are nine bits long, consisting of one data byte and an acknowledge bit. during a data transfer, the master generates the clock and the start and stop conditions, while the receiver is responsible for acknowledging the reception. an acknowledge (ack) is signalled by the receiv er pulling the sda line lo w during the ninth scl cycle. if the receiver leaves the sda line hi gh, a nack is signalled. when the receiver has received the last byte, or for some reason cannot receive any more bytes, it should inform the transmitter by sending a nack after the final by te. the msb of the data byte is transmitted first. sda scl start 12 789 addr msb addr lsb r/w ack 243 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-82. data packet format 6.21.3.5 combining address and data packets into a transmission a transmission basically consists of a start condition, a sla+r/w, one or more data pack- ets and a stop condition. an empty message, consisting of a start followed by a stop condition, is illegal. note that the wired-a nding of the scl line can be used to implement handshaking between the master and the slave. the slave can extend the scl low period by pulling the scl line low. this is us eful if the clock speed set up by the master is too fast for the slave, or the slave needs extra time for processing between the data transmissions. the slave extending the scl low period will not affect the scl high period, which is determined by the master. as a consequence, the slave can reduce the twi data transfer speed by prolong- ing the scl duty cycle. figure 6-83 shows a typical data transmission. note that several data bytes can be transmitted between the sla+r/w and the stop condition, depending on the software protocol imple- mented by the application software. figure 6-83. typical data transmission 12 789 data msb data lsb ack aggregate sda sda from transmitter sda from receiver scl from master sla+r/w data byte stop, repeated start or next data byte 12 789 data byte data msb data lsb ack sda scl start 12 789 addr msb addr lsb r/w ack sla+r/w stop 244 9159a?auto?09/10 atmel ata6614 [preliminary] 6.21.4 multi-master bus systems, arbitration and synchronization the twi protocol allows bus systems with se veral masters. special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more mas- ters initiate a transmission at the same time. two problems arise in multi-master systems: ? an algorithm must be implemented allowing only one of the masters to complete the transmission. all other masters should cease transmission when they discover that they have lost the selection process. this selection proc ess is called arbitration. when a contending master discovers that it has lost the arbitration process, it should immediately switch to slave mode to check whether it is being addressed by the winning master. the fact that multiple masters have started transmission at the same time should not be detectable to the slaves, i.e. the data being transferred on the bus must not be corrupted. ? different masters may use different scl frequencies. a scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. this will fac ilitate the arbitration process. the wired-anding of the bus lines is used to solve both these problems. the serial clocks from all masters will be wired-anded, yieldi ng a combined clock with a high period equal to the one from the master with the shortest high period. the low period of the combined clock is equal to the low period of the master with the longest low period. note that all masters listen to the scl line, effectively starting to count their scl high and low time-out periods when the combined scl line goes high or low, respectively. figure 6-84. scl synchronization betw een multiple masters ta low ta high scl from master a scl from master b scl bus line tb low tb high masters start counting low period masters start counting high period 245 9159a?auto?09/10 atmel ata6614 [preliminary] arbitration is carried out by all masters continuously monitoring the sda line after outputting data. if the value read from the sda line does not match the value the master had output, it has lost the arbitration. note that a master can only lose arbitration when it outputs a high sda value while another master outputs a low value. the losing master should immediately go to slave mode, checking if it is being address ed by the winning master. the sda line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or address packet. arbitration will continue until only one master remains, and this may take many bits. if several masters are trying to address the same slave, arbitration will con- tinue into the data packet. figure 6-85. arbitration between two masters note that arbitration is not allowed between: ? a repeated start cond ition and a data bit. ? a stop condition and a data bit. ? a repeated start and a stop condition. it is the user software?s responsibility to ensure that these illegal arbitr ation conditions never occur. this implies that in mu lti-master systems, all data tr ansfers must use the same compo- sition of sla+r/w and data packets. in other words: all transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. sda from master a sda from master b sda line synchronized scl line start master a loses arbitration, sda a sda 246 9159a?auto?09/10 atmel ata6614 [preliminary] 6.21.5 overview of the twi module the twi module is comprised of several submodules, as shown in figure 6-86 . all registers drawn in a thick line are accessible through the avr data bus. figure 6-86. overview of the twi module 6.21.5.1 scl and sda pins these pins interface the avr twi with the rest of the mcu system. the output drivers contain a slew-rate limiter in order to conform to the twi specification. the input stages contain a spike suppression unit removing spikes shorter than 50 ns. note that the internal pull-ups in the avr pads can be enabled by setting the po rt bits corresponding to the scl and sda pins, as explained in the i/o port section. the internal pull-ups can in some systems eliminate the need for external ones. 6.21.5.2 bit rate generator unit this unit controls the period of scl when operating in a master mode. the scl period is con- trolled by settings in the twi bit rate regist er (twbr) and the prescaler bits in the twi status register (twsr). slave operation does not depend on bit rate or prescaler settings, but the cpu clock frequency in the slave must be at least 16 times higher than the scl frequency. twi unit address register (twar) address match unit address comparator control unit control register (twcr) status register (twsr) state machine and status control scl slew-rate control spike filter sda slew-rate control spike filter bit rate generator bit rate register (twbr) prescaler bus interface unit start / stop control arbitration detection ack spike suppression address/data shift register (twdr) 247 9159a?auto?09/10 atmel ata6614 [preliminary] note that slaves may prolong the scl low peri od, thereby reducing the average twi bus clock period. the scl frequency is generated according to the following equation: ? twbr = value of the twi bit rate register. ? prescalervalue = value of the prescaler, see table 6-95 on page 268 . note: pull-up resistor values should be selected according to the scl frequency and the capacitive bus line load. see table 6-144 on page 346 for value of pull-up resistor. 6.21.5.3 bus interface unit this unit contains the data and address shift register (twdr), a start/stop controller and arbitration detection hardware. the twdr contains the address or data bytes to be trans- mitted, or the address or data bytes received. in addition to the 8-bit twdr, the bus interface unit also contains a register containing the (n)ack bit to be transmitted or received. this (n)ack register is not directly accessible by the application software. however, when receiv- ing, it can be set or cleared by manipulati ng the twi control register (twcr). when in transmitter mode, the value of the received (n)ack bit can be determined by the value in the twsr. the start/stop controller is responsible for generation and detection of start, repeated start, and stop conditions. the star t/stop controller is able to detect start and stop conditions even when the avr mcu is in one of the sleep modes, enabling the mcu to wake up if addressed by a master. if the twi has initiated a transmission as mast er, the arbitration detection hardware continu- ously monitors the transmission trying to determi ne if arbitration is in process. if the twi has lost an arbitration, the control unit is informed. correct action can then be taken and appropri- ate status codes generated. 6.21.5.4 address match unit the address match unit checks if received addr ess bytes match the seven-bit address in the twi address register (twar). if the twi general call recognition enable (twgce) bit in the twar is written to one, all incoming addr ess bits will also be compared against the gen- eral call address. upon an address match, the co ntrol unit is in formed, allowing correct action to be taken. the twi may or may not ack nowledge its address, depending on settings in the twcr. the address match unit is able to compare addresses even when the avr mcu is in sleep mode, enabling the mcu to wake up if addressed by a master. if another interrupt (e.g., int0) occurs during twi power-down address match and wakes up the cpu, the twi aborts operation and return to it?s idle state. if this cause any problems, ensure that twi address match is the only enabled interrupt when entering power-down (1) . note: 1. this applies to all device revisions except atmega88pa revision c or newer. scl frequency cpu clock frequency 16 2(twbr) prescalervalue () ? + -------------------------------------------------------------------------------------------- = 248 9159a?auto?09/10 atmel ata6614 [preliminary] 6.21.5.5 control unit the control unit monitors the twi bus and gener ates responses corres ponding to settings in the twi control register (twcr). when an event requiring the attention of the application occurs on the twi bus, the twi interrupt flag (twint) is asserted. in the next clock cycle, the twi status register (twsr) is updated with a status code identifying the event. the twsr only contains relevant status information when the twi interrupt flag is asserted. at all other times, the twsr contains a special status code indicating that no relevant status information is available. as long as the twint flag is set, the scl line is held low. this allows the appli- cation software to complete its tasks before allowing the twi transmission to continue. the twint flag is set in the following situations: ? after the twi has transmitted a start/repeated start condition. ? after the twi has transmitted sla+r/w. ? after the twi has transmitted an address byte. ? after the twi has lost arbitration. ? after the twi has been addressed by own slave address or general call. ? after the twi has received a data byte. ? after a stop or repeated start has been received while still addressed as a slave. ? when a bus error has occurred due to an illegal start or stop condition. 6.21.6 using the twi the avr twi is byte-oriented and interrupt bas ed. interrupts are issued after all bus events, like reception of a byte or transmission of a start condition. because the twi is inter- rupt-based, the application software is free to carry on other operations during a twi byte transfer. note that the twi interrupt enable (twie) bit in twcr together with the global inter- rupt enable bit in sreg allow the application to decide whether or not assertion of the twint flag should generate an interrupt request. if the twie bit is cleared, the application must poll the twint flag in order to detect actions on the twi bus. when the twint flag is asserted, the twi has finished an operation and awaits application response. in this case, the twi status register (twsr) contains a value indicating the cur- rent state of the twi bus. the application software can then decide how the twi should behave in the next twi bus cycle by manipulating the twcr and twdr registers. figure 6-87 is a simple example of how the application can interface to the twi hardware. in this example, a master wishes to transmit a single data byte to a slave. this description is quite abstract, a more detailed explanation follows later in this section. a simple code example implementing the desired behavior is also presented. 249 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-87. interfacing the application to the twi in a typical transmission 1. the first step in a twi transmission is to transmit a start condition. this is done by writing a specific value into twcr, instructing the twi hardware to transmit a start condition. which value to write is described later on. however, it is important that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any operation as long as the tw int bit in twcr is set. immediately after the application has cleared twint, the twi will initiate transmission of the start condition. 2. when the start condition has been transmitted, the twint flag in twcr is set, and twsr is updated with a status code indicating that the start condition has success- fully been sent. 3. the application software should now examine the value of twsr, to make sure that the start condition was successfully transmitted. if twsr indicates otherwise, the application software might take some spec ial action, like calling an error routine. assuming that the status code is as expect ed, the application must load sla+w into twdr. remember that twdr is used both for address and data. after twdr has been loaded with the desired sla+w, a spec ific value must be written to twcr, instructing the twi hardware to transmit the sla+w present in twdr. which value to write is described later on. however, it is im portant that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not st art any operation as long as the twint bit in twcr is set. im mediately after the application has cleared twint, the twi will initiate tran smission of the address packet. 4. when the address packet has been transmitted, the twint flag in twcr is set, and twsr is updated with a status code indicating that the address packet has success- fully been sent. the status code will also reflect whether a slave acknowledged the packet or not. 5. the application software should now examine the value of twsr, to make sure that the address packet was successfully transmitted, and that the value of the ack bit was as expected. if twsr indicates otherwise, the application software might take some special action, like calling an error routine. assuming that the status code is as expected, the application must load a data packet into twdr. subsequently, a specific value must be written to twcr, instructing the twi hardware to transmit the data packet present in twdr. which value to write is described later on. start sla+w a data a stop 1. application writes to twcr to initiate transmission of start 2. twint set. status code indicates start condition sent 4. twint set. status code indicates sla+w sent, ack received 6. twint set. status code indicates data sent, ack received 3. check twsr to see if start was sent. application loads sla+w into twdr, and loads appropriate control signals into twcr, makin sure that twint is written to one, and twsta is written to zero. 5. check twsr to see if sla+w was sent and ack received. application loads data into twdr, and loads appropriate control signals into twcr, making sure that twint is written to one 7. check twsr to see if data was sent and ack received. application loads appropriate control signals to send stop into twcr, making sure that twint is written to one twi bus indicates twint set application action twi hardware action 250 9159a?auto?09/10 atmel ata6614 [preliminary] however, it is important that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start an y operation as long as the twint bit in twcr is set. immediately after the applicat ion has cleared twint, the twi will initiate transmission of the data packet. 6. when the data packet has been transmitted, the twint flag in twcr is set, and twsr is updated with a status code indicating that the data packet has successfully been sent. the status code will also reflec t whether a slave acknowledged the packet or not. 7. the application software should now examine the value of twsr, to make sure that the data packet was successfully transmitted, and that the value of the ack bit was as expected. if twsr indicates otherwise, the application software might take some spe- cial action, like calling an error routine. assu ming that the status code is as expected, the application must write a specific valu e to twcr, instructing the twi hardware to transmit a stop condition. which value to wr ite is described later on. however, it is important that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any operation as long as the twint bit in twcr is set. immediately after the applicat ion has cleared twint, the twi will initiate transmission of the stop condition. note that twint is not set after a stop condition has been sent. even though this example is simple, it shows the principles involved in all twi transmissions. these can be summarized as follows: ? when the twi has finished an operation and expects application response, the twint flag is set. the scl line is pull ed low until twint is cleared. ? when the twint flag is set, the user must update all twi registers with the value relevant for the next twi bus cycle. as an example, twdr must be loaded with the value to be transmitted in the next bus cycle. ? after all twi register updates and other pending application software tasks have been completed, twcr is written. when writing tw cr, the twint bit should be set. writing a one to twint clears the flag. the twi will then commence executing whatever operation was specified by the twcr setting. in the following an assembly and c implementation of the example is given. note that the code below assumes that several definitions have been made, for example by using include-files. 251 9159a?auto?09/10 atmel ata6614 [preliminary] assembly code example c example comments 1 ldi r16, (1< 253 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-88. data transfer in master transmitter mode a start condition is sent by wr iting the following value to twcr: twen must be set to enable the 2-wire serial interface, twsta must be written to one to transmit a start condition and twint must be wr itten to one to clear the twint flag. the twi will then test the 2-wire serial bus and generate a start condition as soon as the bus becomes free. after a start condition has been transmitted, the twint flag is set by hard- ware, and the status code in twsr will be 0x08 (see table 6-90 ). in order to enter mt mode, sla+w must be transmitted. this is done by writing sla+w to twdr. thereafter the twint bit should be cleared (by writing it to one) to continue the transfer. this is accomplished by writing the following value to twcr: when sla+w have been transmitted and an acknowledgement bit has been received, twint is set again and a number of status codes in twsr are possible. po ssible status codes in master mode are 0x18, 0x20, or 0x38. the appropriate action to be taken for each of these status codes is detailed in table 6-90 . when sla+w has been successfully transmitted, a data packet should be transmitted. this is done by writing the data byte to twdr. twdr mu st only be written when twint is high. if not, the access will be discard ed, and the write collision bit (twwc) will be set in the twcr register. after updating twdr, the twint bit should be cleared (by writing it to one) to con- tinue the transfer. this is accomplish ed by writing the following value to twcr: this scheme is repeated until the last byte has been sent and the transfer is ended by gener- ating a stop condition or a repeated start condition. a stop condition is generated by writing the following value to twcr: a repeated start condition is generated by writing the following value to twcr: twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x01 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x device 1 master transmitter device 2 slave receiver device 3 device n sda scl ........ r1 r2 v cc 254 9159a?auto?09/10 atmel ata6614 [preliminary] after a repeated start condition (state 0x10) the 2-wire serial interface can access the same slave again, or a new slave without transmitting a stop condition. repeated start enables the master to switch between slaves, master transmitter mode and master receiver mode without losing control of the bus. table 6-90. status codes for master transmitter mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twin t twe a 0x08 a start condition has been transmitted load sla+w 0 0 1 x sla+w will be transmitted; ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+w or load sla+r 0 0 0 0 1 1 x x sla+w will be transmitted; ack or not ack will be received sla+r will be transmitted; logic will switch to master receiver mode 0x18 sla+w has been transmitted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x20 sla+w has been transmitted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x28 data byte has been transmit- ted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x30 data byte has been transmit- ted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x38 arbitration lost in sla+w or data bytes no twdr action or no twdr action 0 1 0 0 1 1 x x 2-wire serial bus will be released and not addressed slave mode entered a start condition will be transmitted when the bus becomes free 255 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-89. formats and states in the master transmitter mode 6.21.7.2 master receiver mode in the master receiver mode, a number of data bytes are received from a slave transmitter (slave see figure 6-90 ). in order to enter a master mode, a start condition must be trans- mitted. the format of the following address packet determines whether master transmitter or master receiver mode is to be entered. if sla+w is transmitted, mt mode is entered, if sla+r is transmitted, mr mode is entered. all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. s sla w a data a p $08 $18 $28 r sla w $10 ap $20 p $30 a or a $38 a other master continues a or a $38 other master continues r a $68 other master continues $78 $b0 to corresponding states in slave mode mt m r successfull transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address not acknowledge received after a data byte arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the 2-wire serial bus. the p rescaler bits are zero or masked to zero s 256 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-90. data transfer in ma ster receiver mode a start condition is sent by wr iting the following value to twcr: twen must be written to one to enable the 2-wire serial interface, twsta must be written to one to transmit a start condition and twint must be set to clear the twint flag. the twi will then test the 2-wire seri al bus and generate a start co ndition as soon as the bus becomes free. after a start condition has been transmitted, the twint flag is set by hard- ware, and the status code in twsr will be 0x08 (see table 6-90 ). in order to enter mr mode, sla+r must be transmitted. this is done by wr iting sla+r to twdr. thereafter the twint bit should be cleared (by writing it to one) to continue the transfer. this is accomplished by writing the following value to twcr: when sla+r have been transmitted and an acknowledgement bit has been received, twint is set again and a number of status codes in twsr are possible. po ssible status codes in master mode are 0x38, 0x40, or 0x48. the appropriate action to be taken for each of these status codes is detailed in table 6-91 . received data can be read from the twdr register when the twint flag is set high by hardware. th is scheme is repeated until the last byte has been received. after the last byte has been received, the mr should inform the st by sending a nack after the last received data byte. the transfer is ended by generating a stop condi- tion or a repeated start condition. a stop c ondition is generated by writing the following value to twcr: a repeated start condition is generated by writing the following value to twcr: after a repeated start condition (state 0x10) the 2-wire serial interface can access the same slave again, or a new slave without transmitting a stop condition. repeated start enables the master to switch between slaves, master transmitter mode and master receiver mode without losing control over the bus. twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x01 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x device 1 master receiver device 2 slave transmitter device 3 device n sda scl ........ r1 r2 v cc 257 9159a?auto?09/10 atmel ata6614 [preliminary] table 6-91. status codes for master receiver mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twin t twe a 0x08 a start condition has been transmitted load sla+r 0 0 1 x sla+r will be transmitted ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+r or load sla+w 0 0 0 0 1 1 x x sla+r will be transmitted ack or not ack will be received sla+w will be transmitted logic will switch to master transmitter mode 0x38 arbitration lost in sla+r or not ack bit no twdr action or no twdr action 0 1 0 0 1 1 x x 2-wire serial bus will be released and not addressed slave mode will be entered a start condition will be transmitted when the bus becomes free 0x40 sla+r has been transmitted; ack has been received no twdr action or no twdr action 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x48 sla+r has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x50 data byte has been received; ack has been returned read data byte or read data byte 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x58 data byte has been received; not ack has been returned read data byte or read data byte or read data byte 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 258 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-91. formats and states in the master receiver mode 6.21.7.3 slave receiver mode in the slave receiver mode, a number of data bytes are received from a master transmitter (see figure 6-92 ). all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. figure 6-92. data transfer in slave receiver mode s sla r a data a $08 $40 $50 sla r $10 ap $48 a or a $38 other master continues $38 other master continues w a $68 other master continues $78 $b0 to corresponding states in slave mode mr m t successfull reception from a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the 2-wire serial bus. the p rescaler bits are zero or masked to zero p data a $58 a r s device 3 device n sda scl ........ r1 r2 v cc device 2 master transmitter device 1 slave receiver 259 9159a?auto?09/10 atmel ata6614 [preliminary] to initiate the slave receiver mode, twar and twcr must be initialized as follows: the upper 7 bits are the address to which the 2-wire serial interface will respond when addressed by a master. if the lsb is set, th e twi will respond to the general call address (0x00), otherwise it will igno re the general call address. twen must be written to one to enable the twi. the twea bit must be written to one to enable the acknowledgement of the device?s own slave address or the general call address. twsta and twsto must be written to zero. when twar and twcr have been initialized, the twi waits until it is addressed by its own slave address (or the general call address if enabled ) followed by the data direction bit. if the direction bit is ?0? (write), the twi will oper ate in sr mode, otherwise st mode is entered. after its own slave address and the write bit have been received, the twint flag is set and a valid status code can be read from twsr. the status code is used to determine the appropri- ate software action. the appropriate action to be taken for each status code is detailed in table 6-92 . the slave receiver mode may also be entered if arbitration is lost while the twi is in the master mode (see states 0x68 and 0x78). if the twea bit is reset during a transfer, the tw i will return a ?not ackn owledge? (?1?) to sda after the next received data byte. this can be used to indicate that the slave is not able to receive any more bytes. while twea is zero, the twi does not acknowledge its own slave address. however, the 2-wire serial bus is still monitor ed and address recognition may resume at any time by setting twea. this im plies that the twea bit may be used to tempo- rarily isolate the twi from the 2-wire serial bus. in all sleep modes other than idle mode, the clock system to the twi is turned off. if the twea bit is set, the interface can st ill acknowledge its own slave addr ess or the general call address by using the 2-wire serial bus clock as a cl ock source. the part will then wake up from sleep and the twi will hold the scl clock low during the wake up and until the twint flag is cleared (by writing it to one) . further data reception will be ca rried out as normal, with the avr clocks running as normal. observe that if the avr is set up with a long start-up time, the scl line may be held low for a long time, blocking other data transmissions. note that the 2-wire serial interface data register ? twdr does not reflect the last byte pres- ent on the bus when waking up from these sleep modes. twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address twcr twint twea twsta twsto twwc twen ? twie value 0 100 01 0 x 260 9159a?auto?09/10 atmel ata6614 [preliminary] table 6-92. status codes for slave receiver mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hard- ware application software response next action taken by twi hardware to/from twdr to twcr sta sto twin t twe a 0x60 own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x68 arbitration lost in sla+r/w as master; own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x70 general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x78 arbitration lost in sla+r/w as master; general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x80 previously addressed with own sla+w; data has been received; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x88 previously addressed with own sla+w; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0x90 previously addressed with general call; data has been re- ceived; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x98 previously addressed with general call; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xa0 a stop condition or repeated start condition has been received while still addressed as slave no action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 261 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-93. formats and states in the slave receiver mode 6.21.7.4 slave transmitter mode in the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see figure 6-94 ). all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. figure 6-94. data transfer in slave transmitter mode s sla w a data a $60 $80 $88 a $68 reception of the own slave address and one or more data bytes. all are acknowledged last data byte received is not acknowledged arbitration lost as master and addressed as slave reception of the general call address and one or more data bytes last data byte received is not acknowledged n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the 2-wire serial bus. the prescaler bits are zero or masked to zero p or s data a $80 $a0 p or s a adataa $70 $90 $98 a $78 p or s data a $90 $a0 p or s a general call arbitration lost as master and addressed as slave by general call data a device 3 device n sda scl ........ r1 r2 v cc device 2 master receiver device 1 slave transmitter 262 9159a?auto?09/10 atmel ata6614 [preliminary] to initiate the slave transmitter mode, twar and twcr must be in itialized as follows: the upper seven bits are the a ddress to which the 2-wire seri al interface will respond when addressed by a master. if the lsb is set, th e twi will respond to the general call address (0x00), otherwise it will igno re the general call address. twen must be written to one to enable the twi. the twea bit must be written to one to enable the acknowledgement of the device?s own slave address or the general call address. twsta and twsto must be written to zero. when twar and twcr have been initialized, the twi waits until it is addressed by its own slave address (or the general call address if enabled ) followed by the data direction bit. if the direction bit is ?1? (read), the twi will operate in st mode, otherwise sr mode is entered. after its own slave address and the write bit have been received, the twint flag is set and a valid status code can be read from twsr. the status code is used to determine the appropri- ate software action. the appropriate action to be taken for each status code is detailed in table 6-93 . the slave transmitter mode may also be entered if arbitration is lost while the twi is in the master mode (see state 0xb0). if the twea bit is written to zero during a transfer, the twi will transmit the last byte of the transfer. stat e 0xc0 or state 0xc8 will be entered, de pending on whether the master receiver transmits a nack or ack after the final byte. the twi is switched to the not addressed slave mode, and will ignor e the master if it c ontinues the transfer. th us the master receiver receives all ?1? as serial data. state 0xc8 is entered if the master demands additional data bytes (by transmitting ack), even though the sl ave has transmitted the last byte (twea zero and expecting nack from the master). while twea is zero, the twi does not respond to its own slave address. however, the 2-wire serial bus is still monitored and address reco gnition may resume at any time by setting twea. this implies that the twea bit may be used to temporarily isolate the twi from the 2-wire serial bus. in all sleep modes other than idle mode, the clock system to the twi is turned off. if the twea bit is set, the interface can st ill acknowledge its own slave addr ess or the general call address by using the 2-wire serial bus clock as a cl ock source. the part will then wake up from sleep and the twi will hold the scl clock will low during the wake up and until the twint flag is cleared (by writing it to one). further data transmission will be ca rried out as normal, with the avr clocks running as normal. observe that if the avr is set up with a long start-up time, the scl line may be held low for a long ti me, blocking other data transmissions. note that the 2-wire serial interface data register ? twdr does not reflect the last byte pres- ent on the bus when waking up from these sleep modes. twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address twcr twint twea twsta twsto twwc twen ? twie value 0 100 01 0 x 263 9159a?auto?09/10 atmel ata6614 [preliminary] table 6-93. status codes for slave transmitter mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hard- ware application software response next action taken by twi hardware to/from twdr to twcr sta sto twin t twe a 0xa8 own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be re- ceived 0xb0 arbitration lost in sla+r/w as master; own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be re- ceived 0xb8 data byte in twdr has been transmitted; ack has been received load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be re- ceived 0xc0 data byte in twdr has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xc8 last data byte in twdr has been transmitted (twea = ?0?); ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 264 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-95. formats and states in the slave transmitter mode 6.21.7.5 miscellaneous states there are two status codes that do not correspond to a defined twi state, see table 6-94 . status 0xf8 indicates that no relevant information is available because the twint flag is not set. this occurs between other states, and when the twi is not involved in a serial transfer. status 0x00 indicates that a bus error has occurred during a 2-wire serial bus transfer. a bus error occurs when a start or stop condition occurs at an illegal position in the format frame. examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. when a bus error occurs, twint is set. to recover from a bus error, the twsto flag must set and twint must be cleared by writing a logic one to it. this causes the twi to enter the not addressed slave mode and to clear the twsto flag (no other bits in twcr are affected). the sda and scl lines are released, and no stop condi- tion is transmitted. 6.21.7.6 combining several twi modes in some cases, several twi modes must be combined in order to complete the desired action. consider for example reading data from a serial eeprom. typically, such a transfer involves the following steps: 1. the transfer must be initiated. 2. the eeprom must be instructed what location should be read. 3. the reading must be performed. 4. the transfer must be finished. s sla r a data a $a8 $b8 a $b0 reception of the own slave address and one or more data bytes last data byte transmitted. switched to not addressed slave (twea = '0') arbitration lost as master and addressed as slave n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the 2-wire serial bus. the prescaler bits are zero or masked to zero p or s data $c0 data a a $c8 p or s all 1's a table 6-94. miscellaneous states status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twin t twe a 0xf8 no relevant state information available; twint = ?0? no twdr action no twcr action wait or proceed current transfer 0x00 bus error due to an illegal start or stop condition no twdr action 0 1 1 x only the internal hardware is affected, no stop condi- tion is sent on the bus. in all cases, the bus is released and twsto is cleared. 265 9159a?auto?09/10 atmel ata6614 [preliminary] note that data is transmitted both from master to slave and vice versa. the master must instruct the slave what location it wants to read, requiring the use of the mt mode. subse- quently, data must be read from the slave, implying the use of the mr mode. thus, the transfer direction must be changed. the master must keep control of the bus during all these steps, and the steps should be carried out as an atomical operation. if this principle is violated in a multi master system, another master can alter the data pointer in the eeprom between steps 2 and 3, and the master will read the wrong data location. such a change in transfer direction is accomplished by transmitting a repeated start between the transmission of the address byte and reception of the data. after a repeated start, the master keeps ownership of the bus. the following figure shows the flow in this transfer. figure 6-96. combining several twi modes to access a serial eeprom 6.21.8 multi-master systems and arbitration if multiple masters are connected to the same bus, transmissions may be initiated simultane- ously by one or more of them. the twi standard ensures that such situations are handled in such a way that one of the masters will be allowed to proceed with the transfer, and that no data will be lost in the process. an example of an arbitration si tuation is depicted below, where two masters are trying to transmit data to a slave receiver. figure 6-97. an arbitration example several different scenarios may arise during arbitration, as described below: ? two or more masters are performing identical communication with the same slave. in this case, neither the slave nor any of the masters will know about the bus contention. ? two or more masters are accessing the same slave with different data or direction bit. in this case, arbitration will occur, either in the read /write bit or in the data bits. the masters trying to output a one on sda while another master outputs a zero will lose the arbitration. losing masters will switch to not addressed slave mode or wa it until the bus is free and transmit a new start condition, depending on application software action. master transmitter master receiver s = start rs = repeated start p = stop transmitted from master to slave transmitted from slave to master s sla+w a address a rs sla+r a data a p device 1 master transmitter device 2 master transmitter device 3 slave receiver device n sda scl ........ r1 r2 v cc 266 9159a?auto?09/10 atmel ata6614 [preliminary] ? two or more masters are access ing different slaves. in this ca se, arbitration will occur in the sla bits. masters trying to output a one on sda while another master outputs a zero will lose the arbitration. masters losing ar bitration in sla will switch to slave mode to check if they are being addressed by the winning master. if addressed, they will switch to sr or st mode, depending on the value of the read/write bit. if they are not being addressed, they will switch to not addressed slave mode or wait until the bus is free and transmit a new start condition, depending on application software action. this is summarized in figure 6-98 . possible status values are given in circles. figure 6-98. possible status codes caused by arbitration 6.21.9 register description 6.21.9.1 twbr ? twi bit rate register ? bits 7..0 ? twi bit rate register twbr selects the division factor for the bit rate generator. the bit rate generator is a fre- quency divider which generates the scl cl ock frequency in the master modes. see ?bit rate generator unit? on page 246 for calculating bit rates. 6.21.9.2 twcr ? twi control register the twcr is used to control the operation of the twi. it is used to enable the twi, to initiate a master access by applying a start condition to the bus, to generate a receiver acknowl- edge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the twdr. it also indicates a write collision if data is attempted written to twdr while the regi ster is inaccessible. own address / general call received arbitration lost in sla twi bus will be released and not addressed slave mode will be entered a start condition will be transmitted when the bus becomes free no arbitration lost in data direction ye s write data byte will be received and not ack will be returned data byte will be received and ack will be returned last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received read b0 68/78 38 sla start data stop bit 76543210 (0xb8) twbr7 twbr6 twbr5 twbr4 twbr3 twbr2 twbr1 twbr0 twbr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0xbc) twint twea twsta twsto twwc twen ? twie twcr read/write r/w r/w r/w r/w r r/w r r/w initial value00000000 267 9159a?auto?09/10 atmel ata6614 [preliminary] ? bit 7 ? twint: twi interrupt flag this bit is set by hardware when the twi has finished its current job and expects application software response. if the i-bit in sreg and twie in twcr ar e set, the mcu will jump to the twi interrupt vector. while the twint flag is set, the scl low period is stretched. the twint flag must be cleared by software by writing a logic one to it. note that this flag is not automatically cleared by hardware when executing the interrupt routine. also note that clear- ing this flag starts the operation of the twi, so all accesses to the twi address register (twar), twi status register (twsr), and twi data register (twdr) must be complete before clearing this flag. ? bit 6 ? twea: twi enable acknowledge bit the twea bit controls the generation of the ac knowledge pulse. if the twea bit is written to one, the ack pulse is generated on the twi bus if the following conditions are met: 1. the device?s own slave address has been received. 2. a general call has been received, while the twgce bit in the twar is set. 3. a data byte has been received in master receiver or slave receiver mode. by writing the twea bit to zero, the device can be virtually disconnected from the 2-wire serial bus temporarily. address recognition can then be resumed by writing the twea bit to one again. ? bit 5 ? twsta: twi start condition bit the application writes the twsta bit to one when it desires to become a master on the 2-wire serial bus. the twi hardware checks if the bus is available, and generates a start condi- tion on the bus if it is free. however, if the bus is not free, the twi waits until a stop condition is detected, and then generates a new start condition to claim the bus master status. twsta must be cleared by software when the start condition has been transmitted. ? bit 4 ? twsto: twi stop condition bit writing the twsto bit to one in master m ode will generate a stop condition on the 2-wire serial bus. when the stop condition is executed on the bus, the twsto bit is cleared auto- matically. in slave mode, setting the twsto bit can be used to recover from an error condition. this will not generate a stop c ondition, but the twi retu rns to a well-defined unad- dressed slave mode and releases the scl and sda lines to a high impedance state. ? bit 3 ? twwc: twi write collision flag the twwc bit is set when attempting to write to the twi data register ? twdr when twint is low. this flag is cleared by writin g the twdr register when twint is high. ? bit 2 ? twen: twi enable bit the twen bit enables twi operation and activate s the twi interface. wh en twen is written to one, the twi takes control over the i/o pins connected to the scl and sda pins, enabling the slew-rate limiters and spike filters. if this bit is written to zero, the twi is switched off and all twi transmissions are terminated, regardless of any ongoing operation. ? bit 1 ? res: reserved bit this bit is a reserved bit an d will always read as zero. 268 9159a?auto?09/10 atmel ata6614 [preliminary] ? bit 0 ? twie: twi interrupt enable when this bit is written to one, and the i-bit in sreg is set, the tw i interrupt request will be activated for as long as the twint flag is high. 6.21.9.3 twsr ? twi status register ? bits 7..3 ? tws: twi status these 5 bits reflect the status of the twi logic and the 2-wire serial bus. the different status codes are described later in this section. note that the value read from twsr contains both the 5-bit status value and the 2-bit prescaler value. the application designer should mask the prescaler bits to zero when checking the stat us bits. this makes status checking independent of prescaler setting. this approach is used in this datasheet, unless otherwise noted. ? bit 2 ? res: reserved bit this bit is reserved and will always read as zero. ? bits 1..0 ? twps: twi prescaler bits these bits can be read and written, and control the bit rate prescaler. to calculate bit rates, see ?bit rate generator unit? on page 246 . the value of twps1..0 is used in the equation. 6.21.9.4 twdr ? twi data register in transmit mode, twdr contains the next byte to be transmitted. in receive mode, the twdr contains the last byte received. it is writ able while the twi is not in the process of shift- ing a byte. this occurs when the twi interrupt flag (twint) is set by hardware. note that the data register cannot be initialized by the user before the first interrupt occurs. the data in twdr remains stable as long as twint is set. while data is shifted out, data on the bus is simultaneously shifted in. twdr always contains the last byte present on the bus, except after a wake up from a sleep mode by the twi interrupt. in this case, the contents of twdr is undefined. bit 76543210 (0xb9) tws7 tws6 tws5 tws4 tws3 ? twps1 twps0 twsr read/write rrrrrrr/wr/w initial value11111000 table 6-95. twi bit rate prescaler twps1 twps0 prescaler value 001 014 1016 1164 bit 76543210 (0xbb) twd7 twd6 twd5 twd4 twd3 twd2 twd1 twd0 twdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11111111 269 9159a?auto?09/10 atmel ata6614 [preliminary] in the case of a lost bus arbitration, no data is lost in the transition from master to slave. han- dling of the ack bit is controlled automatically by the twi logic, the cpu cannot access the ack bit directly. ? bits 7..0 ? twd: twi data register these eight bits constitute the next data byte to be transmitted, or the latest data byte received on the 2-wire serial bus. 6.21.9.5 twar ? twi (slave) address register the twar should be loaded with the 7-bit slave address (in the seven most significant bits of twar) to which the twi will respond when progra mmed as a slave tran smitter or receiver, and not needed in the master modes. in multi master systems, twar must be set in masters which can be addressed as slaves by other masters. the lsb of twar is used to enable recognition of the general call address (0x00). there is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address. if a match is found, an interrupt request is generated. ? bits 7..1 ? twa: twi (slave) address register these seven bits constitute th e slave address of the twi unit. ? bit 0 ? twgce: twi general call recognition enable bit if set, this bit enables the recognition of a general call given over the 2-wire serial bus. 6.21.9.6 twamr ? twi (sla ve) address mask register ? bits 7..1 ? twam: twi address mask the twamr can be loaded with a 7-bit salve address mask. each of the bits in twamr can mask (disable) the corresponding address bits in the twi address register (twar). if the mask bit is set to one then the address match logic ignores the compare between the incoming address bit and the corresponding bit in twar. figure 6-99 shown the address match logic in detail. bit 76543210 (0xba) twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce twar read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11111110 bit 76543210 (0xbd) twam[6:0] ? twamr read/write r/w r/w r/w r/w r/w r/w r/w r initial value00000000 270 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-99. twi address match logic, block diagram ? bit 0 ? res: reserved bit this bit is an unused bit in the atmega48pa/88pa /168pa/328p, and will always read as zero. address match address bit comparator 0 address bit comparator 6..1 twar0 twamr0 address bit 0 271 9159a?auto?09/10 atmel ata6614 [preliminary] 6.22 analog comparator 6.22.1 overview the analog comparator compares the input val ues on the positive pin ain0 and negative pin ain1. when the voltage on the positive pin ain0 is higher than the voltage on the negative pin ain1, the analog comparator output, aco, is set. the comparator?s output can be set to trig- ger the timer/counter1 input capture function. in addition, the comparator can trigger a separate interrupt, exclusive to the analog compar ator. the user can select interrupt trigger- ing on comparator output rise, fall or toggle. a block diagram of the comparator and its surrounding logic is shown in figure 6-100 . the power reduction adc bit, pradc, in ?minimizing power consumption? on page 67 must be disabled by writing a logical zero to be able to use the adc input mux. figure 6-100. analog comparator block diagram (2) notes: 1. see table 6-96 on page 271 . 2. refer to table 6-42 on page 114 for analog comparator pin placement. 6.22.2 analog comparator multiplexed input it is possible to select any of the adc7..0 pins to replace the negative input to the analog comparator. the adc multiplexer is used to select this input, and consequently, the adc must be switched off to utilize this feature. if th e analog comparator multiplexer enable bit (acme in adcsrb) is set and the adc is switch ed off (aden in adcsra is zero), mux2..0 in admux select the input pin to replace the negative input to the analog comparator, as shown in table 6-96 . if acme is cleared or aden is set, ain1 is applied to the negative input to the analog comparator. acbg bandgap reference adc multiplexer output acme aden (1) table 6-96. analog comparator multiplexed input acme aden mux2..0 analog co mparator negative input 0 x xxx ain1 1 1 xxx ain1 1 0 000 adc0 1 0 001 adc1 272 9159a?auto?09/10 atmel ata6614 [preliminary] 6.22.3 register description 6.22.3.1 adcsrb ? adc control and status register b ? bit 6 ? acme: analog comparator multiplexer enable when this bit is writte n logic one and the adc is switched off (aden in adcsra is zero), the adc multiplexer selects the negati ve input to the analog comparator. when this bit is written logic zero, ain1 is applied to the negative in put of the analog comparator. for a detailed description of this bit, see ?analog comparator multiplexed input? on page 271 . 6.22.3.2 acsr ? analog comparator control and status register ? bit 7 ? acd: analog comparator disable when this bit is written logic one, the power to the analog comparator is switched off. this bit can be set at any time to tu rn off the analog comparator. th is will reduce power consumption in active and idle mode. when changing the acd bit, the analog comparator interrupt must be disabled by clearing the acie bit in acsr . otherwise an interrupt can occur when the bit is changed. ? bit 6 ? acbg: analog comparator bandgap select when this bit is set, a fixed bandgap referenc e voltage replaces the positive input to the ana- log comparator. when this bit is cleared, ain0 is applied to the positive input of the analog comparator. when the bandgap re ferance is used as input to the analog comparator, it will take a certain time for the volt age to stabilize. if not stabilized, the first conversion may give a wrong value. see ?internal voltage reference? on page 74 ? bit 5 ? aco: analog comparator output the output of the analog comparator is sy nchronized and then directly connected to aco. the synchronization introduces a delay of 1 - 2 clock cycles. 1 0 010 adc2 1 0 011 adc3 1 0 100 adc4 1 0 101 adc5 1 0 110 adc6 1 0 111 adc7 table 6-96. analog comparator multiplexed input acme aden mux2..0 analog co mparator negative input bit 7 6543210 (0x7b) ? acme ? ? ? adts2 adts1 adts0 adcsrb read/write r r/w r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x30 (0x50) acd acbg aco aci acie acic acis1 acis0 acsr read/write r/w r/w r r/w r/w r/w r/w r/w initial value00n/a00000 273 9159a?auto?09/10 atmel ata6614 [preliminary] ? bit 4 ? aci: analog comparator interrupt flag this bit is set by hardware when a comparator output event triggers the interrupt mode defined by acis1 and acis0. the analog comparator interrupt routine is executed if the acie bit is set and the i-bit in sreg is set. aci is cleare d by hardware when executing the corresponding interrupt handling vector. alternatively, aci is cleared by writing a logic one to the flag. ? bit 3 ? acie: analog comparator interrupt enable when the acie bit is written logic one and the i- bit in the status register is set, the analog comparator interrupt is activated. when written logic zero, the interrupt is disabled. ? bit 2 ? acic: analog comparator input capture enable when written logic one, this bit enables the input capture function in timer/counter1 to be trig- gered by the analog comparator. the comparator output is in this case directly connected to the input capture front-end logi c, making the compar ator utilize the noise canceler and edge select features of the timer/counter1 input capture interrupt. when written logic zero, no con- nection between the analog comparator and the input capture function exists. to make the comparator trigger the timer/counter1 input capture interrupt, the icie1 bit in the timer inter- rupt mask register (timsk1) must be set. ? bits 1, 0 ? acis1, acis0: analog comparator interrupt mode select these bits determine which comparator events that trigger the analog comparator interrupt. the different settings are shown in table 6-97 . when changing the acis1/acis0 bits, the analog comparator interrupt must be disabled by clearing its interrupt enable bit in the acsr register. otherwise an interrupt can occur when the bits are changed. table 6-97. acis1/acis0 settings acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle. 01reserved 1 0 comparator interrupt on falling output edge. 1 1 comparator interrupt on rising output edge. 274 9159a?auto?09/10 atmel ata6614 [preliminary] 6.22.3.3 didr1 ? digital input disable register 1 ? bit 7..2 ? res: reserved bits these bits are unused bits in the atme ga48pa/88pa/168pa/328p, and will always read as zero. ? bit 1, 0 ? ain1d, ain0d: ain1, ain0 digital input disable when this bit is written logic one, the digital in put buffer on the ain1/0 pin is disabled. the cor- responding pin register bit will always read as zero when this bit is set. when an analog signal is applied to the ain1/0 pin and the digi tal input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. bit 76543210 (0x7f) ??????ain1dain0ddidr1 read/write rrrrrrr/wr/w initial value 00000000 275 9159a?auto?09/10 atmel ata6614 [preliminary] 6.23 analog-to-digital converter 6.23.1 features ? 10-bit resolution ? 0.5lsb integral non-linearity ? 2 lsb absolute accuracy ? 13 - 260s conversion time ? up to 76.9ksps (up to 15ksp s at maximum resolution) ? 6 multiplexed single ended input channels ? 2 additional multiplexed single ended input channels (tqfp and qfn/mlf package only) ? temperature sensor input channel ? optional left adjustment for adc result readout ? 0 - v cc adc input voltage range ? selectable 1.1v adc reference voltage ? free running or single conversion mode ? interrupt on adc conversion complete ? sleep mode no ise canceler 6.23.2 overview the atmel ? atmega48pa/88pa/168pa/328p features a 10-bit successive approximation adc. the adc is connected to an 8-channel analog multiplexer which allows eight sin- gle-ended voltage inputs constructed from the pins of port a. the single-ended voltage inputs refer to 0v (gnd). the adc contains a sample and hold circuit wh ich ensures that the input voltage to the adc is held at a constant level during conversion. a block diagram of the adc is shown in figure 6-101 on page 276 . the adc has a separate analog supply voltage pin, av cc . av cc must not differ more than 0.3v from v cc . see the paragraph ?adc noise canceler? on page 281 on how to connect this pin. internal reference voltages of nominally 1.1v or av cc are provided on-chip. the voltage refer- ence may be externally decoupled at the aref pin by a capacitor for better noise performance. the power reduction adc bit, pradc, in ?minimizing power consumption? on page 67 must be disabled by writing a logical zero to enable the adc. the adc converts an analog input voltage to a 10-bit digital value through successive approx- imation. the minimum value represents gnd and the maximum value represents the voltage on the aref pin minus 1 lsb. optionally, av cc or an internal 1.1v reference voltage may be connected to the aref pin by writing to the refsn bits in the admux register. the internal voltage reference may thus be decoupled by an external capacitor at the aref pin to improve noise immunity. 276 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-101. analog to digital converter block schematic operation, the analog input channel is selected by writing to the mux bits in admux. any of the adc input pins, as well as gnd and a fixed bandgap voltage reference, can be selected as single ended inputs to the adc. the adc is enabled by setting the adc enable bit, aden in adc- sra. voltage reference and input channel selections will not go into effect until aden is set. the adc does not consume power when aden is cleared, so it is recommended to switch off the adc before entering power saving sleep modes. the adc generates a 10-bit result which is presented in the adc data registers, adch and adcl. by default, the result is presented ri ght adjusted, but can optionally be presented left adjusted by setting the adlar bit in admux. if the result is left adjusted and no more than 8-bi t precision is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch, to ensure that the content of the data registers belongs to the same conversion. once adcl is read, adc access to data regis- ters is blocked. adc conversion complete irq 8-bit data bus 15 0 adc multiplexer select (admux) adc ctrl. & status register (adcsra) adc data register (adch/adcl) mux2 adie adfr adsc aden adif adif mux1 mux0 adps0 adps1 adps2 mux3 conversion logic 10-bit dac + - sample & hold comparator internal 1.1v reference mux decoder avcc adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 refs0 refs1 adlar channel selection adc[9:0] adc multiplexer output aref bandgap reference prescaler gnd input mux temperature sensor 277 9159a?auto?09/10 atmel ata6614 [preliminary] this means that if adcl has been read, and a conversion completes before adch is read, neither register is updated and the result fr om the conversion is lost. when adch is read, adc access to the adch and ad cl registers is re-enabled. the adc has its own interrupt which can be triggered when a conversion completes. when adc access to the data registers is prohib ited between reading of adch and adcl, the interrupt will trigger even if the result is lost. 6.23.3 starting a conversion a single conversion is started by disab ling the power reduction adc bit, pradc, in ?minimiz- ing power consumption? on page 67 by writing a logical zero to it and writing a logical one to the adc start conversion bit, adsc. this bit st ays high as long as the conversion is in prog- ress and will be cleared by hardware when the conversion is completed. if a different data channel is selected while a conv ersion is in progress, the a dc will finish the current conver- sion before performing the channel change. alternatively, a conversion can be triggered automatically by various sources. auto triggering is enabled by setting the adc auto trigger en able bit, adate in adcsra. the trigger source is selected by setting the adc trigger select bi ts, adts in adcsrb (see description of the adts bits for a list of the trigger sources). when a positive edge occurs on the selected trigger signal, the adc prescaler is reset and a conversion is started. this provides a method of start- ing conversions at fixed intervals. if the trigger signal still is set when the conversion completes, a new conversion will no t be started. if another positi ve edge occurs on the trigger signal during conversion, the ed ge will be ignored. note that an interrupt flag will be set even if the specific interrupt is disabled or the globa l interrupt enable bit in sreg is cleared. a con- version can thus be triggered without causing an interrupt. however, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. figure 6-102. adc auto trigger logic using the adc interrupt flag as a trigger s ource makes the adc start a new conversion as soon as the ongoing conversion has finished. th e adc then operates in free running mode, constantly sampling and updating the adc data r egister. the first conversion must be started by writing a logical one to the adsc bit in adcsra. in this mode the adc will perform suc- cessive conversions independently of whether the adc interrupt flag, adif is cleared or not. adsc adif source 1 source n adts[2:0] conversion logic prescaler start clk adc . . . . edge detector adate 278 9159a?auto?09/10 atmel ata6614 [preliminary] if auto triggering is enabled, single conversi ons can be started by writing adsc in adcsra to one. adsc can also be used to determine if a conv ersion is in progress. the adsc bit will be read as one during a conversion, independently of how the conversion was started. 6.23.4 prescaling and conversion timing figure 6-103. adc prescaler by default, the successive approximation circui try requires an input clock frequency between 50khz and 200khz to get maximum resolution. if a lower resolution than 10bits is needed, the input clock frequency to the adc can be higher than 200khz to get a higher sample rate. the adc module contains a prescaler, which generates an acceptable adc clock frequency from any cpu frequency above 100khz. the presca ling is set by the ad ps bits in adcsra. the prescaler starts counting from the moment the adc is switched on by setting the aden bit in adcsra. the prescaler keeps running for as long as the aden bit is set, and is contin- uously reset when aden is low. when initiating a single ended conversion by setting the adsc bit in adcsra, the conversion starts at the following rising edge of the adc clock cycle. a normal conversion takes 13 adc clock cycles . the first conversion after the adc is switched on (aden in adcsra is set) takes 25 adc clock cycles in order to initialize the ana- log circuitry. when the bandgap reference voltag e is used as input to the adc, it will take a certain time for the voltage to stabilize. if not stabilized, the first value read after the first conversion may be wrong. the actual sample-and-hold take s place 1.5 adc clock cycles afte r the start of a normal con- version and 13.5 adc clock cycles after the start of an first conversion. when a conversion is complete, the result is written to the adc data registers, and adif is set. in single conver- sion mode, adsc is cleared simultaneously. the software may then set adsc again, and a new conversion will be in itiated on the first ri sing adc clock edge. when auto triggering is used, the prescaler is reset when the trigger event occurs. this assures a fixed delay from the trigger event to the start of conversion. in this mode, the sam- ple-and-hold takes place two adc clock cycles after the rising edge on the trigger source signal. three additional cpu clock cycles are used for synchronization logic. 7-bit adc prescaler adc clock source ck adps0 adps1 adps2 ck/128 ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 reset aden start 279 9159a?auto?09/10 atmel ata6614 [preliminary] in free running mode, a new conversion will be started immediately after the conversion completes, while adsc remains high. fo r a summary of conversion times, see table 6-98 on page 280 . figure 6-104. adc timing diagram, first conver sion (single conversion mode) figure 6-105. adc timing diagram, single conversion figure 6-106. adc timing diagram, auto triggered conversion sign and msb of result lsb of result adc clock adsc sample & hold adif adch adcl cycle number aden 1 212 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 first conversion next conversion 3 mux and refs update mux and refs update conversion complete 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 3 sample & hold mux and refs update conversion complete mux and refs update 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of result lsb of result adc clock trigger source adif adch adcl cycle number 12 one conversion next conversion conversion complete prescaler reset adate prescaler reset sample & hold mux and refs update 280 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-107. adc timing diagram, free running conversion 6.23.5 changing channel or reference selection the muxn and refs1:0 bits in the admux register are single buffered through a temporary register to which the cpu has random access. this ensures that the channels and reference selection only takes place at a safe point during the conversion. the channel and reference selection is continuously updated until a conver sion is started. once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the adc. continuous updating resumes in the last adc clock cycle before the conversion completes (adif in adcsra is set). note that the conversion starts on the following rising adc clock edge after adsc is written. the user is thus advised not to write new channel or reference selection values to admux until one a dc clock cycle after adsc is written. if auto triggering is used, the exact time of t he triggering event can be indeterministic. special care must be taken when updating the admux register, in order to control which conversion will be affected by the new settings. if both adate and aden is written to one, an interrupt event can occur at any time. if the admux register is changed in this period, the us er cannot tell if the next conversion is based on the old or the new settings. admux can be safely updated in the following ways: a. when adate or aden is cleared. b. during conversion, minimum one adc clock cycle after the trigger event. c. after a conversion, before the interrupt flag used as trigger source is cleared. when updating admux in one of these conditio ns, the new settings will affect the next adc conversion. table 6-98. adc conversion time condition sample & hold (cycles from start of conversion) conversion time (cycles) first conversion 13.5 25 normal conversions, single ended 1.5 13 auto triggered conversions 2 13.5 11 12 13 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 34 conversion complete sample & hold mux and refs update 281 9159a?auto?09/10 atmel ata6614 [preliminary] 6.23.5.1 adc input channels when changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: in single conversion mode, always select the channel before starting the conversion. the channel selection may be changed one adc cloc k cycle after writing one to adsc. however, the simplest method is to wait for the conversion to complete before changing the channel selection. in free running mode, always select the channel before starting the first conversion. the channel selection may be changed one adc cloc k cycle after writing one to adsc. however, the simplest method is to wait for the first conversion to complete, and then change the chan- nel selection. since the next c onversion has already started aut omatically, the next result will reflect the previous channel selection. subsequent conversions will reflect the new channel selection. 6.23.5.2 adc voltage reference the reference voltage for the adc (v ref ) indicates the conversion range for the adc. single ended channels that exceed v ref will result in codes close to 0x3ff. v ref can be selected as either av cc , internal 1.1v reference, or external aref pin. av cc is connected to the adc through a passive s witch. the internal 1.1v reference is gener- ated from the internal bandgap reference (v bg ) through an internal amplifier. in either case, the external aref pin is directly connected to the adc, and the reference voltage can be made more immune to noise by connecting a capacitor between the aref pin and ground. v ref can also be measured at the aref pin with a high impedance voltmeter. note that v ref is a high impedance source, and only a capacitive load should be connected in a system. if the user has a fixed voltage source connected to the aref pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external volt- age. if no external voltage is applied to the aref pin, the user may switch between av cc and 1.1v as reference selection. the first adc conv ersion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. 6.23.6 adc noise canceler the adc features a noise canceler that enables conversion during sleep mode to reduce noise induced from the cpu core and other i/o peripherals. the noise canceler can be used with adc noise reduction and idle mode. to make use of this feature, the following proce- dure should be used: a. make sure that the adc is enabled and is not busy converting. single conversion mode must be selected and the adc conversion complete interrupt must be enabled. b. enter adc noise reduction mode (or idle mode). the adc will start a conversion once the cpu has been halted. c. if no other interrupts occur before the adc conversion completes, the adc inter- rupt will wake up the cpu and execute the adc conversion complete interrupt routine. if another interrupt wakes up the cpu before the adc conversion is com- plete, that interrupt will be executed, and an adc conversion complete interrupt request will be generated when the adc conversion completes. the cpu will remain in active mode until a new sleep command is executed. 282 9159a?auto?09/10 atmel ata6614 [preliminary] note that the adc will not be automatically turned off when entering other sleep modes than idle mode and adc noise reduction mode. the user is advised to write zero to aden before entering such sleep modes to av oid excessive power consumption. 6.23.6.1 analog input circuitry the analog input circuitry for single ended channels is illustrated in figu re 6-108. an analog source applied to adcn is subjected to t he pin capacitance and input leakage of that pin, regardless of whether that channel is select ed as input for the adc. when the channel is selected, the source must drive the s/h c apacitor through the series resistance (combined resistance in the input path). the adc is optimized for analog signals with an output impedance of approximately 10k or less. if such a source is used, the sampling time will be negligible. if a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the s/h capacitor, with can vary widely. the user is recommended to only use low impedance sources with slowly varying signal s, since this minimizes the required charge transfer to the s/h capacitor. signal components higher than the nyquist frequency (f adc /2) should not be present for either kind of channels, to avoid distortion from unpredict able signal convolution. the user is advised to remove high frequency components with a lo w-pass filter before applying the signals as inputs to the adc. figure 6-108. analog input circuitry 6.23.6.2 analog noise canceling techniques digital circuitry inside and outside the device generates emi which might affect the accuracy of analog measurements. if conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. keep analog signal paths as short as possible. make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. b. the av cc pin on the device should be connected to the digital v cc supply voltage via an lc network as shown in figure 6-109 . c. use the adc noise canceler function to reduce induced noise from the cpu. adcn i ih 1..100 k c s/h = 14 pf v cc /2 i il 283 9159a?auto?09/10 atmel ata6614 [preliminary] d. if any adc [3..0] port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. however, using the 2-wire interface (adc4 and adc5) will only affect the conv ersion on adc4 and adc5 and not the other adc channels. figure 6-109. adc power connections 6.23.6.3 adc accuracy definitions an n-bit single-ended adc converts a voltage linearly between gnd and v ref in 2 n steps (lsbs). the lowest code is read as 0, and the highest code is read as 2 n -1. several parameters describe the deviation from the ideal behavior: ? offset: the deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 lsb). ideal value: 0 lsb. gnd vcc pc5 (adc5/scl) pc4 (adc4/sda) pc3 (adc3) pc2 (adc2) pc1 (adc1) pc0 (adc0) adc7 gnd aref avcc adc6 pb5 10 h 100nf analog ground plane 284 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-110. offset error ? gain error: after adjusting for offset, the gain error is found as the deviation of the last transition (0x3fe to 0x3ff) compared to the ideal transition (at 1.5 lsb below maximum). ideal value: 0 lsb figure 6-111. gain error ? integral non-linearity (inl): after adjusting for offset and gain error, the inl is the maximum deviation of an actual transition compared to an ideal transition for any code. ideal value: 0 lsb. output code v ref input voltage ideal adc actual adc offset error output code v ref input voltage ideal adc actual adc gain error 285 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-112. integral non-linearity (inl) ? differential non-linearity (dnl): the maximum devi ation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1lsb). ideal value: 0lsb. figure 6-113. differential non-linearity (dnl) ? quantization error: due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1lsb wide) will code to the same value. always 0.5lsb. ? absolute accuracy: the maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. this is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. ideal value: 0.5lsb. output code v ref input voltage ideal adc actual adc inl output code 0x3ff 0x000 0 v ref input voltage dnl 1 lsb 286 9159a?auto?09/10 atmel ata6614 [preliminary] 6.23.7 adc conversion result after the conversion is complete (adif is high), the conversion result can be found in the adc result registers (adcl, adch). for single ended conversion, the result is where v in is the voltage on the selected input pin and v ref the selected voltage reference (see table 6-100 on page 287 and table 6-101 on page 288 ). 0x000 represents analog ground, and 0x3ff represents the selected reference voltage minus one lsb. 6.23.8 temperature measurement the temperature measurement is based on an on-chip temperature sensor that is coupled to a single ended adc8 channel. selecting the adc8 channel by writing the mux3..0 bits in admux register to "1000" enables the temperature sensor. the internal 1.1v voltage refer- ence must also be selected for the adc voltage reference source in the temperature sensor measurement. when the temperature sensor is enabled, the adc converter can be used in single conversion mode to measure the voltage over the temperature sensor. the measured voltage has a linear relationship to the temperature as described in table 6-99 . the voltage sensitivity is approximately 1mv/ c and the accuracy of the temperature mea- surement is 10c. the values described in table 6-99 are typical values. however, due to the process variation the temperature sensor output voltage varies from one chip to another. to be capable of achieving more accurate results the temperature measurement can be calibrated in the appli- cation software. the software calibration requires that a calibration value is measured and stored in a register or eeprom for each chip, as a part of th e production test. the software calibration can be done utilizing the formula: t = { [(adch << 8) | adcl] - t os } / k where adcn are the adc data registers, k is a fixed coefficient and t os is the temperature sensor offset value determined and stored into eeprom as a part of the production test. adc v in 1024 ? v ref ----------------------------- = table 6-99. temperature vs. sensor output voltage (typical case) temperature / c -45c +25c +85c voltage / mv 242mv 314mv 380mv 287 9159a?auto?09/10 atmel ata6614 [preliminary] 6.23.9 register description 6.23.9.1 admux ? adc multip lexer selection register ? bit 7:6 ? refs1:0: reference selection bits these bits select the voltage reference for the adc, as shown in table 6-100 . if these bits are changed during a conversion, the change will not go in effect unt il this conversion is complete (adif in adcsra is set). the internal vo ltage reference options may not be used if an external reference voltage is being applied to the aref pin. ? bit 5 ? adlar: adc left adjust result the adlar bit affects the presentation of the adc conversion result in the adc data regis- ter. write one to adlar to left adjust the result. otherwise, the result is right adjusted. changing the adlar bit will affect the adc data register immediately, regardless of any ongoing conversions. for a complete description of this bit, see ?adcl and adch ? the adc data register? on page 290 . ? bit 4 ? res: reserved bit this bit is an unused bit in the atmega48pa/88pa /168pa/328p, and will always read as zero. ? bits 3:0 ? mux3:0: analog channel selection bits the value of these bits selects which analog inputs are connected to the adc. see table 6-101 for details. if these bits are changed during a conver sion, the change will not go in effect until this conversion is comple te (adif in adcsra is set). bit 76543210 (0x7c) refs1 refs0 adlar ? mux3 mux2 mux1 mux0 admux read/write r/w r/w r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 6-100. voltage reference selections for adc refs1 refs0 voltage re ference selection 0 0 aref, internal v ref turned off 01 av cc with external capacitor at aref pin 10reserved 1 1 internal 1.1v voltage reference with external capacitor at aref pin 288 9159a?auto?09/10 atmel ata6614 [preliminary] note: 1. for temperature sensor. 6.23.9.2 adcsra ? adc control and status register a ? bit 7 ? aden: adc enable writing this bit to one en ables the adc. by writing it to zero, the adc is turned off. turning the adc off while a conversion is in prog ress, will terminate this conversion. ? bit 6 ? adsc: adc start conversion in single conversion mode, write this bit to one to start each conversion. in free running mode, write this bit to one to start the first conversion. the first conversion after adsc has been written after the adc has been enabled, or if adsc is written at the same time as the adc is enabled, will take 25 adc clock cycles instead of the normal 13. this first conversion performs initialization of the adc. adsc will read as one as long as a conversi on is in progress. when the conversion is com- plete, it returns to zero. writing zero to this bit has no effect. table 6-101. input channel selections mux3..0 single ended input 0000 adc0 0001 adc1 0010 adc2 0011 adc3 0100 adc4 0101 adc5 0110 adc6 0111 adc7 1000 adc8 (1) 1001 (reserved) 1010 (reserved) 1011 (reserved) 1100 (reserved) 1101 (reserved) 1110 1.1v (v bg ) 1111 0v (gnd) bit 76543210 (0x7a) aden adsc adate adif adi e adps2 adps1 adps0 adcsra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 289 9159a?auto?09/10 atmel ata6614 [preliminary] ? bit 5 ? adate: adc auto trigger enable when this bit is written to on e, auto triggering of the adc is enabled. the adc will start a conversion on a positive edge of the selected trigger signal. the trigger source is selected by setting the adc trigger sele ct bits, adts in adcsrb. ? bit 4 ? adif: adc interrupt flag this bit is set when an adc conversion completes and the data registers are updated. the adc conversion complete interrupt is executed if the adie bit and the i-bit in sreg are set. adif is cleared by hardware when executi ng the corresponding interrupt handling vector. alternatively, adif is cleared by writing a l ogical one to the flag. beware that if doing a read-modify-write on adcsra, a pending interrupt can be disabled. this also applies if the sbi and cbi instructions are used. ? bit 3 ? adie: adc interrupt enable when this bit is written to one and the i-bit in sreg is set, the adc conversion complete interrupt is activated. ? bits 2:0 ? adps2:0: adc prescaler select bits these bits determine the division factor between the system clock frequency and the input clock to the adc. table 6-102. adc prescaler selections adps2 adps1 adps0 division factor 000 2 001 2 010 4 011 8 100 16 101 32 110 64 1 1 1 128 290 9159a?auto?09/10 atmel ata6614 [preliminary] 6.23.9.3 adcl and adch ? the adc data register 6.23.9.4 adlar = 0 6.23.9.5 adlar = 1 when an adc conversion is complete, the result is found in these two registers. when adcl is read, the adc da ta register is not updated until adch is read. consequently, if the result is left adjusted and no more than 8-bi t precision is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch. the adlar bit in admux, and the muxn bits in admux affect the way the result is read from the registers. if adlar is set, the result is left adjusted. if adlar is cleared (default), the result is right adjusted. ? adc9:0: adc conversion result these bits represent the result from the conversion, as detailed in ?adc conversion result? on page 286 . 6.23.9.6 adcsrb ? adc control and status register b ? bit 7, 5:3 ? res: reserved bits these bits are reserved for future use. to ensure compatibility with future devices, these bist must be written to zero when adcsrb is written. ? bit 2:0 ? adts2:0: adc auto trigger source if adate in adcsra is written to one, the valu e of these bits selects which source will trigger an adc conversion. if adate is cleared, the adts2:0 settings will have no effect. a conver- sion will be triggered by the rising edge of the selected interrupt flag. bit 151413121110 9 8 (0x79) ?????? adc9 adc8 adch (0x78) adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl 76543210 read/writerrrrrrrr rrrrrrrr initial value00000000 00000000 bit 151413121110 9 8 (0x79) adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch (0x78) adc1 adc0 ? ? ? ? ? ? adcl 76543210 read/writerrrrrrrr rrrrrrrr initial value 0 0 0 0 0 0 0 0 00000000 bit 76543210 (0x7b) ? acme ? ? ? adts2 adts1 adts0 adcsrb read/write r r/w r r r r/w r/w r/w initial value00000000 291 9159a?auto?09/10 atmel ata6614 [preliminary] note that switching from a trigger source that is cleared to a tr igger source that is set, will gen- erate a positive edge on the trigger signal. if aden in adcsra is set, this will start a conversion. switching to free running mode (a dts[2:0]=0) will not cause a trigger event, even if the adc interrupt flag is set. 6.23.9.7 didr0 ? digital input disable register 0 ? bits 7:6 ? res: reserved bits these bits are reserved for future use. to ensure compatibility with future devices, these bits must be written to zero when didr0 is written. ? bit 5:0 ? adc5d..adc0d: ad c5..0 digital input disable when this bit is written logic one, the digital input buffer on the corresponding adc pin is dis- abled. the corresponding pin re gister bit will always read as zero when this bit is set. when an analog signal is applied to the adc5..0 pin an d the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. note that adc pins adc7 and adc6 do not have digital input buffers, and therefore do not require digital input disable bits. table 6-103. adc auto trigger source selections adts2 adts1 adts0 trigger source 0 0 0 free running mode 0 0 1 analog comparator 0 1 0 external interrupt request 0 0 1 1 timer/counter0 compare match a 1 0 0 timer/counter0 overflow 1 0 1 timer/counter1 compare match b 1 1 0 timer/counter1 overflow 1 1 1 timer/counter1 capture event bit 76543210 (0x7e) ? ? adc5d adc4d adc3d adc2d adc1d adc0d didr0 read/write r r r/w r/w r/w r/w r/w r/w initial value00000000 292 9159a?auto?09/10 atmel ata6614 [preliminary] 6.24 debugwire on-c hip debug system 6.24.1 features ? complete program flow control ? emulates all on-chip func tions, both digital and analog, except reset pin ? real-time operation ? symbolic debugging support (both at c and assembler source level, or for other hlls) ? unlimited number of prog ram break points (using software break points) ? non-intrusive operation ? electrical characteristics identical to real device ? automatic configuration system ? high-speed operation ? programming of non-volatile memories 6.24.2 overview the debugwire on-chip debug system uses a one- wire, bi-directional interface to control the program flow, execute avr instructions in the cpu and to program the different non-volatile memories. 6.24.3 physical interface when the debugwire enable (dwen) fuse is programmed and lock bits are unpro- grammed, the debugwire system within the target device is activated. the reset port pin is configured as a wire-and (open-drain) bi-directional i/o pin with pull-up enabled and becomes the communication gateway between target and emulator. figure 6-114. the debugwire setup figure 6-114 shows the schematic of a target mcu, with debugwire enabled, and the emula- tor connector. the system clock is not affected by debugwire and will always be the clock source selected by the cksel fuses. dw gnd dw(reset) vcc 1.8 - 5.5v 293 9159a?auto?09/10 atmel ata6614 [preliminary] when designing a system wher e debugwire will be used, the following observations must be made for correct operation: ? pull-up resistors on the dw/(reset) line must not be smaller than 10k . the pull-up resistor is not required for debugwire functionality. ? connecting the reset pin directly to v cc will not work. ? capacitors connected to th e reset pin must be disconne cted when using debugwire. ? all external reset sources must be disconnected. 6.24.4 software break points debugwire supports program memory break points by the avr break instruction. setting a break point in atmel ? avr studio ? will insert a break instru ction in the program memory. the instruction replaced by the break instruct ion will be stored. when program execution is continued, the stored instructio n will be executed befo re continuing from the program memory. a break can be inserted manually by putting the break instruction in the program. the flash must be re-programmed each time a break point is changed. this is automatically handled by avr studio through the debugwire in terface. the use of br eak points will there- fore reduce the flash data retention. devices used for debugging purposes should not be shipped to end customers. 6.24.5 limitations of debugwire the debugwire communication pin (dw) is physically located on the same pin as external reset (reset). an external rese t source is therefore not su pported when the debugwire is enabled. a programmed dwen fuse enables some parts of the clock system to be running in all sleep modes. this will increase the power consumption while in sleep. thus, the dwen fuse should be disabled when debugwire is not used. 6.24.6 register description the following section describes the registers used with the debugwire. 6.24.6.1 dwdr ? debugwire data register the dwdr register provides a communication channel from the running program in the mcu to the debugger. this register is only accessible by the debugwire and can therefore not be used as a general purpose register in the normal operations. bit 76543210 dwdr[7:0] dwdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 294 9159a?auto?09/10 atmel ata6614 [preliminary] 6.25 self-programming the flash, atmega48pa 6.25.1 overview in atmega48pa, there is no read-while-write support, and no separate boot loader section. the spm instruction can be executed from the entire flash. the device provides a self-programming mechanism for downloading and uploading program code by the mcu itself. the self-programming can use any available data interface and asso- ciated protocol to read code and write (program) that code into the program memory. the program memory is updated in a page by page fashion. before programming a page with the data stored in the temporary page buffer, the page must be erased. the temporary page buffer is filled one word at a ti me using spm and the buffer can be filled either before the page erase command or between a page erase and a page write operation: alternative 1, fill the bu ffer before a page erase ? fill temporary page buffer ? perform a page erase ? perform a page write alternative 2, fill the bu ffer after page erase ? perform a page erase ? fill temporary page buffer ? perform a page write if only a part of the page needs to be changed, the rest of the page must be stored (for exam- ple in the temporary page buffer) before the erase, and then be re-written. when using alternative 1, the boot loader provides an effe ctive read-modify-write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. if alternative 2 is used, it is not possible to read the old data while loading since the page is already erased. the temporary page buffer can be accessed in a random sequence. it is essential that the page address used in both the page erase and page write operation is addressing the same page. 6.25.1.1 performing page erase by spm to execute page erase, set up the address in the z-pointer, write ?00000011? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage in the z-register. other bits in the z-pointer will be ignored during this operation. ? the cpu is halted during the page erase operation. 6.25.1.2 filling the temporary buffer (page loading) to write an instruction word, set up the address in the z-pointer and data in r1:r0, write ?00000001? to spmcsr and execute spm within four clock cycles after writing spmcsr. the content of pcword in the z-register is used to address the data in the temporary buffer. the temporary buffer will auto -erase after a page wr ite operation or by writing the rwwsre bit in spmcsr. it is also erased after a system reset. note that it is not possible to write more than one time to each address without erasing the temporary buffer. if the eeprom is written in th e middle of an spm page load operation, all data loaded will be lost. 295 9159a?auto?09/10 atmel ata6614 [preliminary] 6.25.1.3 performing a page write to execute page write, set up the address in the z-pointer, write ?00000101? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage. other bits in the z-pointer must be written to zero during this operation. ? the cpu is halted during the page write operation. 6.25.2 addressing the flash during self-programming the z-pointer is used to address the spm commands. since the flash is organized in pages (see table 6-130 on page 324 ), the program counter can be treated as having two different sections. one section, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. this is shown in figure 6-118 on page 307 . note that the page erase and page write operations are addressed independently. therefore it is of major importance that the software addresses the same page in both the page erase and page write operation. the lpm instruction uses the z-pointer to store the address. since this instruction addresses the flash byte-by-byte, also the lsb (bit z0) of the z-pointer is used. figure 6-115. addressing the flash during spm (1) note: 1. the different variables used in figure 6-118 are listed in table 6-130 on page 324 . bit 151413121110 9 8 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30) z7z6z5z4z3z2z1z0 76543210 program memory 0 1 15 z - register bit 0 zpagemsb word address within a page page address within the flash zpcmsb instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter 296 9159a?auto?09/10 atmel ata6614 [preliminary] 6.25.2.1 eeprom write prev ents writing to spmcsr note that an eeprom write operation will bl ock all software programming to flash. reading the fuses and lock bits from software will also be prevented during th e eeprom write opera- tion. it is recommended that the user checks the status bit (eepe) in the eecr register and verifies that the bit is cleared before writing to the spmcsr register. 6.25.2.2 reading the fuse and lock bits from software it is possible to read both the fuse and lock bits from software. to read the lock bits, load the z-pointer with 0x00 01 and set the blbset and selfprgen bits in spmcsr. when an lpm instruction is executed within three cpu cycl es after the blbset an d selfprgen bits are set in spmcsr, the value of the lock bits will be loaded in the destin ation register. the blb- set and selfprgen bits will auto-clear upon completion of reading the lock bits or if no lpm instruction is executed within three cpu c ycles or no spm instruction is executed within four cpu cycles. when blbset and selfprgen are cleared, lpm will work as described in the instruction set manual. the algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. to read the fu se low byte, load the z-pointer with 0x0000 an d set the blbset and selfprgen bits in spmcsr. when an lpm instruction is executed within three cycles after the blbset and selfprgen bits are set in the spmcsr, the value of the fuse low byte (flb) will be loaded in the destination regist er as shown below.see table 6-124 on page 321 for a detailed description and mapping of the fuse low byte. similarly, when reading the fuse high byte (fhb), load 0x0003 in the z-pointer. when an lpm instruction is executed within three cycles after the bl bset and selfprgen bits are set in the spmcsr, the value of the fuse high byte will be loaded in the destination register as shown below. see table 6-124 on page 321 for detailed description and mapping of the extended fuse byte. similarly, when reading the extended fuse byte (efb), load 0x0002 in the z-pointer. when an lpm instruction is executed within three cycles after the bl bset and selfprgen bits are set in the spmcsr, the value of the extended fu se byte will be loaded in the destination reg- ister as shown below. see table 6-124 on page 321 for detailed description and mapping of the extended fuse byte. fuse and lock bits that are pr ogrammed, will be read as zero. fuse and lock bits that are unprogrammed, will be read as one. bit 76543210 rd ??????lb2lb1 bit 76543210 rd flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 bit 76543210 rd fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 bit 76543210 rd fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 297 9159a?auto?09/10 atmel ata6614 [preliminary] 6.25.2.3 preventing flash corruption during periods of low v cc , the flash program can be corrupted because the supply voltage is too low for the cpu and the flash to operate properly. these issues are the same as for board level systems using the flash, and the same design solutions should be applied. a flash program corruption can be caused by two situations when the voltage is too low. first, a regular write sequence to the flash requires a minimum voltage to operate correctly. sec- ondly, the cpu itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. keep the avr reset active (low) during peri ods of insufficient power supply voltage. this can be done by enabling the internal brown-out detector (bod) if the operating voltage matches the detection level. if not, an external low v cc reset protection circuit can be used. if a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 2. keep the avr core in power-down sleep mode during periods of low v cc . this will pre- vent the cpu from attempting to decode and execute instructions, effectively protecting the spmcsr register and thus the flash from unintentional writes. 6.25.2.4 programming time for flash when using spm the calibrated rc oscillator is used to time flash accesses. table 6-110 shows the typical programming time for flash accesses from the cpu. note: 1. minimum and maximum programming time is per individual operation. table 6-104. spm programming time (1) symbol min programming ti me max programming time flash write (page erase, page write, and write lock bits by spm) 3.7 ms 4.5 ms 298 9159a?auto?09/10 atmel ata6614 [preliminary] 6.25.2.5 simple assembly code example for a boot loader note that the rwwsb bit will alwa ys be read as zero in atmel ? atmega48pa. nevertheless, it is recommended to check this bit as shown in the code example, to ensure compatibility with devices supporting read-while-write. ;-the routine writes one page of data from ram to flash ; the first data location in ram is pointed to by the y pointer ; the first data location in flash is pointed to by the z-pointer ;-error handling is not included ;-the routine must be placed inside the boot space ; (at least the do_spm sub routine). only code inside nrww section can ; be read during self-programming (page erase and page write). ;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;-it is assumed that either the interrupt table is moved to the boot ; loader section or that the interrupts are disabled. .equ pagesizeb = pagesize*2 ;pagesizeb is page size in bytes, not words .org smallbootstart write_page: ; page erase ldi spmcrval, (1< 301 9159a?auto?09/10 atmel ata6614 [preliminary] ? bit 0 ? selfprgen: self programming enable this bit enables the spm instruction for the nex t four clock cycles. if written to one together with either rwwsre, blbset, pgwrt, or pgers, the following spm instruction will have a special meaning, see description above. if only selfprgen is written, the following spm instruction will store the value in r1:r0 in the temporary page bu ffer addressed by the z-pointer. the lsb of the z-po inter is ignored. the selfprg en bit will auto-clear upon com- pletion of an spm instruction, or if no spm inst ruction is executed within four clock cycles. during page erase and page write, the selfprgen bit remains high until the operation is completed. writing any other combination than ?10001?, ?01001?, ?00101?, ?00011? or ?00001? in the lower five bits will have no effect. 302 9159a?auto?09/10 atmel ata6614 [preliminary] 6.26 boot loader support ? read- while-write self-programming, atmel atmega88pa, at mega168pa and atmega328p 6.26.1 features ? read-while-write self-programming ? flexible boot memory size ? high security (separate boot lock bits for a flexible protection) ? separate fuse to select reset vector ? optimized page (1) size ? code efficient algorithm ? efficient read-modi fy-write support note: 1. a page is a section in the flash consisting of several bytes (see table 6-130 on page 324 ) used during programming. the page organizat ion does not affect normal operation. 6.26.2 overview in atmel atmega88pa, atmega168pa and atmega328p, the boot loader support provides a real read-while-write self-programming mechanism for downloading and uploading pro- gram code by the mcu itself. this featur e allows flexible application software updates controlled by the mcu using a flash-resident boot loader program. the boot loader program can use any available data interface and associated protocol to read code and write (program) that code into the flash memory, or read the code from the program memory. the program code within the boot loader section has the capab ility to write into the entire flash, including the boot loader memory. the boot loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. the size of the boot loader memory is configurable with fuses and the boot loader has two separate sets of boot lock bits which can be set independently. this gives the user a unique flexibility to select different levels of protection. 6.26.3 application and boot loader flash sections the flash memory is organized in two main sections, the application section and the boot loader section (see figure 6-117 ). the size of the different sections is configured by the bootsz fuses as shown in table 6-111 on page 314 and figure 6-117 . these two sections can have different level of protection sinc e they have different sets of lock bits. 6.26.3.1 application section the application section is the section of the flash that is used for storing the application code. the protection level for the application section can be selected by the application boot lock bits (boot lock bits 0), see table 6-106 on page 306 . the application section can never store any boot loader code since the spm instruction is disabled when executed from the applica- tion section. 6.26.3.2 bls ? boot loader section while the application section is used for st oring the application code, the the boot loader software must be located in the bls since the spm instruction can initiate a programming when executing from the bls only. the spm instruction can access the entire flash, including the bls itself. the protection level for the boot loader section can be selected by the boot loader lock bits (boot lock bits 1), see table 6-107 on page 306 . 303 9159a?auto?09/10 atmel ata6614 [preliminary] 6.26.4 read-while-write and no read-while-write flash sections whether the cpu supports read-while-write or if the cpu is halted during a boot loader software update is dependent on which address that is being programmed. in addition to the two sections that are configurable by the bootsz fuses as described above, the flash is also divided into two fixed sections, the read-while-write (rww) section and the no read-while-write (nrww) section. the limit between the rww- and nrww sections is given in table 6-112 on page 314 and figure 6-117 on page 305 . the main difference between the two sections is: ? when erasing or writing a page located inside the rww section, the nrww section can be read during the operation. ? when erasing or writing a page located inside the nrww section, the cpu is halted during the entire operation. note that the user software can never read any code that is located inside the rww section during a boot loader software operation. the syntax ?read-while-write section? refers to which section that is being programmed (erased or written), not which section that actually is being read during a boot loader software update. 6.26.4.1 rww ? read-while-write section if a boot loader software update is programmi ng a page inside the rww section, it is possi- ble to read code from the flash, but only code that is located in the nrww section. during an on-going programming, the software must ensure that the rww section never is being read. if the user software is trying to read code that is located inside the rww section (i.e., by a call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown state. to avoid this, the interrupts should either be disabled or moved to the boot loader sec- tion. the boot loader section is always located in the nrww section. the rww section busy bit (rwwsb) in the store program memory cont rol and status register (spmcsr) will be read as logical one as long as the rww section is blocked for reading. after a program- ming is completed, the rwwsb must be cleared by software before reading code located in the rww section. see ?spmcsr ? store program memory control and status register? on page 317. for details on how to clear rwwsb. 6.26.4.2 nrww ? no read-while-write section the code located in the nrww section can be read when the boot loader software is updat- ing a page in the rww section. when the boot loader code updates the nrww section, the cpu is halted during the entire page erase or page write operation. table 6-105. read-while-write features which section does the z-pointer address during the programming? which section can be read during programming? cpu halted? read-while-write supported? rww section nrww section no yes nrww section none yes no 304 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-116. read-while-write vs. no read-while-write read-while-write (rww) section no read-while-write (nrww) section z-pointer addresses rww section z-pointer addresses nrww section cpu is halted during the operation code located in nrww section can be read during the operation 305 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-117. memory sections note: 1. the parameters in the figure above are given in table 6-111 on page 314 . 6.26.5 boot loader lock bits if no boot loader capability is needed, the entire flash is available for application code. the boot loader has two separate sets of boot lock bits which can be set independently. this gives the user a unique fl exibility to select different levels of protection. the user can select: ? to protect the entire flash from a software update by the mcu. ? to protect only the boot loader flash section from a software update by the mcu. ? to protect only the application flash section from a software update by the mcu. ? allow software update in the entire flash. see table 6-106 and table 6-107 for further details. the boot lock bits can be set in software and in serial or parallel programming mode, but they can be cleared by a chip erase com- mand only. the general write lock (lock bit mode 2) does not control the programming of the flash memory by spm instruction. similarly, the general read/write lock (lock bit mode 1) does not control reading nor writing by lpm/spm, if it is attempted. 0x0000 flashend program memory bootsz = '11' application flash section boot loader flash section flashend program memory bootsz = '10' 0x0000 program memory bootsz = '01' program memory bootsz = '00' application flash section boot loader flash section 0x0000 flashend application flash section flashend end rww start nrww application flash section boot loader flash section boot loader flash section end rww start nrww end rww start nrww 0x0000 end rww, end application start nrww, start boot loader application flash section application flash section application flash section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section end application start boot loader end application start boot loader end application start boot loader 306 9159a?auto?09/10 atmel ata6614 [preliminary] note: 1. ?1? means unprogrammed, ?0? means programmed note: 1. ?1? means unprogrammed, ?0? means programmed 6.26.6 entering the boot loader program entering the boot loader takes place by a jump or call from the application program. this may be initiated by a trigger such as a command received via usart, or spi interface. alterna- tively, the boot reset fuse can be programmed so that the reset vector is pointing to the boot flash start address after a reset. in this case, the boot loader is started after a reset. after the application code is loaded, the program can start executing the application code. note that the fuses cannot be changed by the mcu itself. this means that once the boot reset fuse is programmed, the reset vector will always point to the boot loader reset and the fuse can only be changed through the serial or parallel programming interface. note: 1. ?1? means unprogrammed, ?0? means programmed table 6-106. boot lock bit0 protection modes (application section) (1) blb0 mode blb02 blb01 protection 111 no restrictions for spm or lpm accessing the application section. 2 1 0 spm is not allowed to writ e to the application section. 300 spm is not allowed to write to the application section, and lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 401 lpm executing from the boot loader section is not allowed to read from the application sect ion. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. table 6-107. boot lock bit1 protection modes (boot loader section) (1) blb1 mode blb12 blb11 protection 111 no restrictions for spm or lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 300 spm is not allowed to write to the boot loader section, and lpm executing from the applicat ion section is not allowed to read from the boot loader se ction. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 401 lpm executing from the applicat ion section is not allowed to read from the boot loader se ction. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. table 6-108. boot reset fuse (1) bootrst reset address 1 reset vector = application reset (address 0x0000) 0 reset vector = boot loader reset (see table 6-111 on page 314 ) 307 9159a?auto?09/10 atmel ata6614 [preliminary] 6.26.7 addressing the flash during self-programming the z-pointer is used to address the spm commands. since the flash is organized in pages (see table 6-130 on page 324 ), the program counter can be treated as having two different sections. one section, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. this is1 shown in figure 6-118 . note that the page erase and page write operations are addressed independently. therefore it is of major importance that the boot loader soft- ware addresses the same page in both the page erase and page write operation. once a programming operation is initiated, the address is latched and the z-pointer can be used for other operations. the only spm operation that does not use the z-pointer is setting the boot loader lock bits. the content of the z-pointer is ignored and w ill have no effect on the operation. the lpm instruction does also use the z-pointer to store the address. since this instruction addresses the flash byte-by-byte, also the lsb (bit z0) of the z-pointer is used. figure 6-118. addressing the flash during spm (1) note: 1. the different variables used in figure 6-118 are listed in table 6-113 on page 314 . bit 151413121110 9 8 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30) z7z6z5z4z3z2z1z0 76543210 program memory 0 1 15 z - register bit 0 zpagemsb word address within a page page address within the flash zpcmsb instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter 308 9159a?auto?09/10 atmel ata6614 [preliminary] 6.26.8 self-programming the flash the program memory is updated in a page by page fashion. before programming a page with the data stored in the temporary page buffer, the page must be erased. the temporary page buffer is filled one word at a ti me using spm and the buffer can be filled either before the page erase command or between a page erase and a page write operation: alternative 1, fill the bu ffer before a page erase ? fill temporary page buffer ? perform a page erase ? perform a page write alternative 2, fill the bu ffer after page erase ? perform a page erase ? fill temporary page buffer ? perform a page write if only a part of the page needs to be changed, the rest of the page must be stored (for exam- ple in the temporary page buffer) before the erase, and then be rewritten. when using alternative 1, the boot loader provides an effe ctive read-modify-write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. if alternative 2 is used, it is not possible to read the old data while loading since the page is already erased. the temporary page buffer can be accessed in a random sequence. it is essential that the page address used in both the page erase and page write operation is addressing the same page. see ?simple assembly code example for a boot loader? on page 312 for an assembly code example. 6.26.8.1 performing page erase by spm to execute page erase, set up the address in the z-pointer, write ?x0000011? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage in the z-register. other bits in the z-pointer will be ignored during this operation. ? page erase to the rww section: the nrww section can be read during the page erase. ? page erase to the nrww section: the cpu is halted during the operation. 6.26.8.2 filling the temporary buffer (page loading) to write an instruction word, set up the address in the z-pointer and data in r1:r0, write ?00000001? to spmcsr and execute spm within four clock cycles after writing spmcsr. the content of pcword in the z-register is used to address the data in the temporary buffer. the temporary buffer will auto -erase after a page wr ite operation or by writing the rwwsre bit in spmcsr. it is also erased after a system reset. note that it is not possible to write more than one time to each address without erasing the temporary buffer. if the eeprom is written in th e middle of an spm page load operation, all data loaded will be lost. 309 9159a?auto?09/10 atmel ata6614 [preliminary] 6.26.8.3 performing a page write to execute page write, set up the address in the z-pointer, write ?x0000101? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage. other bits in the z-pointer must be written to zero during this operation. ? page write to the rww section: the nrww section can be read during the page write. ? page write to the nrww section: the cpu is halted during the operation. 6.26.8.4 using the spm interrupt if the spm interrupt is enabled, the spm interrupt will generate a constant interrupt when the selfprgen bit in spmcsr is cleared. this means that the interrupt can be used instead of polling the spmcsr register in software. when using the spm in terrupt, the interrupt vectors should be moved to the bls section to avoid that an interrupt is accessing the rww section when it is blocked for reading. how to move the interrupts is described in ?interrupts? on page 81 . 6.26.8.5 consideration while updating bls special care must be taken if the user allows the boot loader section to be updated by leaving boot lock bit11 unprogrammed. an accidental write to the boot loader itself can corrupt the entire boot loader, and further software updates might be impossible. if it is not necessary to change the boot loader software itself, it is recommended to program the boot lock bit11 to protect the boot loader software from any internal software changes. 6.26.8.6 prevent reading the rww section during self-programming during self-programming (either page erase or page write), the rww section is always blocked for reading. the user software itself must prevent that this section is addressed during the self programming o peration. the rwwsb in the spmcsr will be set as long as the rww section is busy. during self-programming the in terrupt vector table should be moved to the bls as described in ?watchdog timer? on page 75 , or the interrupts must be disabled. before addressing the rww section after the programming is completed, the user software must clear the rwwsb by writing the rwwsre. see ?simple assembly code example for a boot loader? on page 312 for an example. 6.26.8.7 setting the boot loader lock bits by spm to set the boot loader lock bits and general loc k bits, write the desired data to r0, write ?x0001001? to spmcsr and execute spm within four clock cycles after writing spmcsr. see table 6-106 and table 6-107 for how the different settings of the boot loader bits affect the flash access. if bits 5..0 in r0 are cleared (zero), the co rresponding lock bit will be programmed if an spm instruction is exec uted within four cycles after blbset and selfprgen are set in spmcsr. the z-pointer is don?t ca re during this operation, but for future compatibility it is recommended to load the z-pointer with 0x0001 (same as used for reading the lo ck bits). for future compati- bility it is also recommended to set bits 7 a nd 6 in r0 to ?1? when writing the lock bits. when programming the lock bits the entire flash can be read during the operation. bit 76543210 r0 1 1 blb12 blb11 blb02 blb01 lb2 lb1 310 9159a?auto?09/10 atmel ata6614 [preliminary] 6.26.8.8 eeprom write prev ents writing to spmcsr note that an eeprom write operation will bl ock all software programming to flash. reading the fuses and lock bits from software will also be prevented during th e eeprom write opera- tion. it is recommended that the user checks the status bit (eepe) in the eecr register and verifies that the bit is cleared before writing to the spmcsr register. 6.26.8.9 reading the fuse and lock bits from software it is possible to read both the fuse and lock bits from software. to read the lock bits, load the z-pointer with 0x00 01 and set the blbset and selfprgen bits in spmcsr. when an lpm instruction is executed within three cpu cycl es after the blbset an d selfprgen bits are set in spmcsr, the value of the lock bits will be loaded in the destin ation register. the blb- set and selfprgen bits will auto-clear upon completion of reading the lock bits or if no lpm instruction is executed within three cpu c ycles or no spm instruction is executed within four cpu cycles. when blbset and selfprgen are cleared, lpm will work as described in the instruction set manual. the algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. to read the fu se low byte, load the z-pointer with 0x0000 an d set the blbset and selfprgen bits in spmcsr. when an lpm instruction is executed within three cycles after the blbset and selfprgen bits are set in the spmcsr, the value of the fuse low byte (flb) will be loaded in the destinat ion register as sh own below. refer to table 6-124 on page 321 for a detailed description and mapping of the fuse low byte. similarly, when reading the fuse high byte, load 0x0003 in the z-pointer. when an lpm instruction is executed within three cycles after the blbset and selfprgen bits are set in the spmcsr, the value of the fuse high byte (f hb) will be loaded in th e destination register as shown below. refer to table 6-126 on page 321 for detailed description and mapping of the fuse high byte. when reading the extended fuse byte, load 0x0002 in the z-pointer. when an lpm instruction is executed within three cycles after the blbset and selfprgen bits are set in the spmcsr, the value of the extended fuse byte (efb) will be loaded in the destinat ion register as shown below. refer to table 6-124 on page 321 for detailed description and mapping of the extended fuse byte. fuse and lock bits that are pr ogrammed, will be read as zero. fuse and lock bits that are unprogrammed, will be read as one. bit 76543210 rd ? ? blb12 blb11 blb02 blb01 lb2 lb1 bit 76543210 rd flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 bit 76543210 rd fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 bit 76543210 rd ? ? ? ? efb3 efb2 efb1 efb0 311 9159a?auto?09/10 atmel ata6614 [preliminary] 6.26.8.10 reading the signature row from software to read the signature row from software, load the z-pointer with the signature byte address given in table 6-109 on page 311 and set the sigrd and spmen bits in spmcsr. when an lpm instruction is executed wit hin three cpu cycles after the sigrd and spmen bits are set in spmcsr, the signature byte value will be loaded in the de stination register. the sigrd and spmen bits will auto-clear upon completion of reading the signature row lock bits or if no lpm instruction is executed within th ree cpu cycles. when sigrd and spmen are cleared, lpm will work as described in the instruction set manual. note: all other addresses are reserved for future use. 6.26.8.11 preventing flash corruption during periods of low v cc , the flash program can be corrupted because the supply voltage is too low for the cpu and the flash to operate properly. these issues are the same as for board level systems using the flash, and the same design solutions should be applied. a flash program corruption can be caused by two situations when the voltage is too low. first, a regular write sequence to the flash requires a minimum voltage to operate correctly. sec- ondly, the cpu itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. if there is no need for a boot loader update in the system, program the boot loader lock bits to prevent any boot loader software updates. 2. keep the avr reset active (low) during peri ods of insufficient power supply voltage. this can be done by enabling the internal brown-out detector (bod) if the operating voltage matches the detection level. if not, an external low v cc reset protection circuit can be used. if a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 3. keep the avr core in power-down sleep mode during periods of low v cc . this will pre- vent the cpu from attempting to decode and execute instructions, effectively protecting the spmcsr register and thus the flash from unintentional writes. 6.26.8.12 programming time for flash when using spm the calibrated rc oscillator is used to time flash accesses. table 6-110 shows the typical programming time for flash accesses from the cpu. note: 1. minimum and maximum programming time is per individual operation. table 6-109. signature row addressing signature byte z-pointer address device signature byte 1 0x0000 device signature byte 2 0x0002 device signature byte 3 0x0004 rc oscillator calibration byte 0x0001 table 6-110. spm programming time (1) symbol min programming time max programming time flash write (page erase, page write, and write lock bits by spm) 3.7 ms 4.5 ms 312 9159a?auto?09/10 atmel ata6614 [preliminary] 6.26.8.13 simple assembly code example for a boot loader ;-the routine writes one page of data from ram to flash ; the first data location in ram is pointed to by the y pointer ; the first data location in flash is pointed to by the z-pointer ;-error handling is not included ;-the routine must be placed inside the boot space ; (at least the do_spm sub routine). only code inside nrww section can ; be read during self-programming (page erase and page write). ;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;-it is assumed that either the interrupt table is moved to the boot ; loader section or that the interrupts are disabled. .equ pagesizeb = pagesize*2 ;pagesizeb is page size in bytes, not words .org smallbootstart write_page: ; page erase ldi spmcrval, (1< 315 9159a?auto?09/10 atmel ata6614 [preliminary] 6.26.8.15 atmega168pa boot loader parameters in table 6-114 through table 6-116 , the parameters used in the description of the self programming are given. note: the different bootsz fuse configurations are shown in figure 6-117 on page 305 . for details about these two section, see ?nrww ? no read-while-write section? on page 303 and ?rww ? read-while-write section? on page 303 note: 1. z15:z14: always ignored z0: should be zero for all spm commands, byte select for the lpm instruction. see ?addressing the flash during self-programming? on page 307 for details about the use of z-pointer during self-programming. table 6-114. boot size configuration, atmel ? atmega168pa bootsz1 bootsz0 boot size pages application flash section boot loader flash section end application section boot reset address (start boot loader section) 1 1 128 words 2 0x0000 - 0x1f7f 0x1f80 - 0x1fff 0x1f7f 0x1f80 1 0 256 words 4 0x0000 - 0x1eff 0x1f00 - 0x1fff 0x1eff 0x1f00 0 1 512 words 8 0x0000 - 0x1dff 0x1e00 - 0x1fff 0x1dff 0x1e00 0 0 1024 words 16 0x0000 - 0x1bff 0x1c00 - 0x1fff 0x1bff 0x1c00 table 6-115. read-while-write limit, atmel atmega168pa section pages address read-while-write section (rww) 112 0x0000 - 0x1bff no read-while-write section (nrww) 16 0x1c00 - 0x1fff table 6-116. explanation of different variables used in figure 6-118 and the mapping to the z-pointer, atmega168pa variable corresponding z-value (1) description pcmsb 12 most significant bit in the progra m counter. (the program counter is 13bits pc[12:0]) pag e m s b 5 most significant bit which is us ed to address the words within one page (64 words in a page requires 6 bits pc [5:0]) zpcmsb z13 bit in z-register that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagemsb z6 bit in z-register that is mapped to pagemsb. because z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[12:6] z13:z7 program counter page address: page select, for page erase and page write pcword pc[5:0] z6:z1 program counter word address: word select, for filling temporary buffer (must be zero during page write operation) 316 9159a?auto?09/10 atmel ata6614 [preliminary] 6.26.8.16 atmega328p boot loader parameters in table 6-117 through table 6-119 , the parameters used in the description of the self programming are given. note: the different bootsz fuse configurations are shown in figure 6-117 on page 305 . for details about these two section, see ?nrww ? no read-while-write section? on page 303 and ?rww ? read-while-write section? on page 303 . note: 1. z15: always ignored z0: should be zero for all spm commands, byte select for the lpm instruction. see ?addressing the flash during self-programming? on page 307 for details about the use of z-pointer during self-programming. table 6-117. boot size configuration, atmel ? atmega328p bootsz1 bootsz0 boot size pages application flash section boot loader flash section end application section boot reset address (start boot loader section) 1 1 256 words 4 0x0000 - 0x3eff 0x3f00 - 0x3fff 0x3eff 0x3f00 1 0 512 words 8 0x0000 - 0x3dff 0x3e00 - 0x3fff 0x3dff 0x3e00 0 1 1024 words 16 0x0000 - 0x3bff 0x3c00 - 0x3fff 0x3bff 0x3c00 0 0 2048 words 32 0x0000 - 0x37ff 0x3800 - 0x3fff 0x37ff 0x3800 table 6-118. read-while-write limit, atmel atmega328p section pages address read-while-write section (rww) 224 0x0000 - 0x37ff no read-while-write section (nrww) 32 0x3800 - 0x3fff table 6-119. explanation of different variables used in figure 6-118 and the mapping to the z-pointer, atmel atmega328p variable corresponding z-value (1) description pcmsb 13 most significant bit in the progra m counter. (the program counter is 14 bits pc[13:0]) pag e m s b 5 most significant bit which is us ed to address the words within one page (64 words in a page requires 6 bits pc [5:0]) zpcmsb z14 bit in z-register that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagemsb z6 bit in z-register that is mapped to pagemsb. because z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[13:6] z14:z7 program counter page address: page select, for page erase and page write pcword pc[5:0] z6:z1 program counter word address: word select, for filling temporary buffer (must be zero during page write operation) 317 9159a?auto?09/10 atmel ata6614 [preliminary] 6.26.9 register description 6.26.9.1 spmcsr ? store program memory control and status register the store program memory control and status register contains the control bits needed to control the boot loader operations. ? bit 7 ? spmie: spm interrupt enable when the spmie bit is written to one, and the i-bit in the status register is set (one), the spm ready interrupt will be enabled. th e spm ready interrupt will be ex ecuted as long as the self- prgen bit in the spmcsr register is cleared. ? bit 6 ? rwwsb: read-while-write section busy when a self-programming (page erase or page write) operation to the rww section is initi- ated, the rwwsb will be set (one) by hardware. when the rwwsb bit is set, the rww section cannot be accessed. the rwwsb bit will be cleared if the rwwsre bit is written to one after a self-programming operation is comple ted. alternatively the rwwsb bit will auto- matically be cleared if a page load operation is initiated. ? bit 5 ? res: reserved bit this bit is a reserved bit in the atmega48pa/88pa/168pa/328p and always read as zero. ? bit 4 ? rwwsre: read-while-write section read enable when programming (page erase or page write) to the rww section, the rww section is blocked for reading (the rwwsb will be set by hardware). to re -enable the rww section, the user software must wait until the programm ing is completed (selfprgen will be cleared). then, if the rwwsre bit is written to one at the same time as selfprgen, the next spm instruction within four clock cycles re-enables the rww section. the rww section cannot be re-enabled while the flash is busy with a page erase or a page write (selfprgen is set). if the rwwsre bit is written while the flash is being loaded, th e flash load operation will abort and the data l oaded will be lost. ? bit 3 ? blbset: boot lock bit set if this bit is written to one at the same time as selfprgen, the next spm instruction within four clock cycles sets boot lock bits and memo ry lock bits, according to the data in r0. the data in r1 and the ad dress in the z-pointer are ignored. the blbset bit will automatically be cleared upon completion of the lock bit set, or if no spm instruction is executed within four clock cycles. an lpm instruction within three cycles after blbset and selfprgen are set in the spmcsr register, will read either the lock bits or the fuse bits (depending on z0 in the z-pointer) into the destination register. see ?reading the fuse and lock bits from software? on page 310 for details. bit 7 6 5 4 3 2 1 0 0x37 (0x57) spmie rwwsb ? rwwsre blbset pgwrt pgers selfprgen spmcsr read/write r/w r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 318 9159a?auto?09/10 atmel ata6614 [preliminary] ? bit 2 ? pgwrt: page write if this bit is written to one at the same time as selfprgen, the next spm instruction within four clock cycles executes page write, with the data stored in the temporary buffer. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgwrt bit will auto-clear upon completion of a page write, or if no spm instruction is executed within four clock cycles. the cpu is ha lted during the entire page write operation if the nrww section is addressed. ? bit 1 ? pgers: page erase if this bit is written to one at the same time as selfprgen, the next spm instruction within four clock cycles executes pa ge erase. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored . the pgers bit will auto -clear upon completion of a page erase, or if no spm instruction is executed within four clock cycles. the cpu is halted during the entire page write operation if the nrww section is addressed. ? bit 0 ? selfprgen: self programming enable this bit enables the spm instruction for the nex t four clock cycles. if written to one together with either rwwsre, blbset, pg wrt or pgers, the following spm instruction will have a special meaning, see description above. if only selfprgen is written, the following spm instruction will store the value in r1:r0 in the temporary page bu ffer addressed by the z-pointer. the lsb of the z-po inter is ignored. the selfprg en bit will auto-clear upon com- pletion of an spm instruction, or if no spm inst ruction is executed within four clock cycles. during page erase and page write, the selfprgen bit remains high until the operation is completed. writing any other combination than ?10001?, ?01001?, ?00101?, ?00011? or ?00001? in the lower five bits will have no effect. 319 9159a?auto?09/10 atmel ata6614 [preliminary] 6.27 memory programming 6.27.1 program and data memory lock bits the atmel ? atmega88pa/168pa/328p provides six lock bits which can be left unpro- grammed (?1?) or can be programmed (?0?) to obtain the additional features listed in table 6-121 . the lock bits can only be erased to ?1? with the chip erase command. the atmega48pa has no separate boot loader section. the spm instruction is enabled for the whole flash if the selfprgen fuse is prog rammed (?0?), otherwise it is disabled. notes: 1. ?1? means unprogrammed, ?0? means programmed. 2. only on atmel atmega88pa/168pa/328p. notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed table 6-120. lock bit byte (1) lock bit byte bit no desc ription default value 7 ? 1 (unprogrammed) 6 ? 1 (unprogrammed) blb12 (2) 5 boot lock bit 1 (unprogrammed) blb11 (2) 4 boot lock bit 1 (unprogrammed) blb02 (2) 3 boot lock bit 1 (unprogrammed) blb01 (2) 2 boot lock bit 1 (unprogrammed) lb2 1 lock bit 1 (unprogrammed) lb1 0 lock bit 1 (unprogrammed) table 6-121. lock bit protection modes (1)(2) memory lock bits protection type lb mode lb2 lb1 1 1 1 no memory lock features enabled. 210 further programming of the flash and eeprom is disabled in parallel and serial programming mode. the fuse bits are locked in both serial and parallel programming mode. (1) 300 further programming and verification of the flash and eeprom is disabled in parall el and serial programming mode. the boot lock bits and fuse bits are locked in both serial and parallel programming mode. (1) 320 9159a?auto?09/10 atmel ata6614 [preliminary] notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed 6.27.2 fuse bits the atmel atmega48pa/88pa/168pa/328p has three fuse bytes. table 6-124 - table 6-128 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. note that the fuses are read as logical zero, ?0?, if they are programmed. table 6-122. lock bit protection modes (1)(2) . only atmel ? atmega88pa/168pa/328p. blb0 mode blb02 blb01 111 no restrictions for spm or lpm accessing the application section. 2 1 0 spm is not allowed to write to the application section. 300 spm is not allowed to write to the application section, and lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupt s are disabled while executing from the application section. 401 lpm executing from the boot load er section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. blb1 mode blb12 blb11 111 no restrictions for spm or lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 300 spm is not allowed to write to the boot loader section, and lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interr upts are disabled while executing from the boot loader section. 401 lpm executing from the application section is not allowed to read from the boot loader sect ion. if interrupt vectors are placed in the application sectio n, interrupts are disabled while executing from the boot loader section. table 6-123. extended fuse byte for atmel atmega48pa extended fuse byte bit no de scription default value ?7? 1 ?6? 1 ?5? 1 ?4? 1 ?3? 1 ?2? 1 ?1? 1 selfprgen 0 self programming enable 1 (unprogrammed) 321 9159a?auto?09/10 atmel ata6614 [preliminary] note: 1. the default value of bootsz[1:0] results in maximum boot size. see ?pin name mapping? on page 325 . note: 1. see table 6-142 on page 343 for bodlevel fuse decoding. table 6-124. extended fuse byte for atmel ? atmega88pa/168pa extended fuse byte bit no description default value ?7?1 ?6?1 ?5?1 ?4?1 ?3?1 bootsz1 2 select boot size (see table 6-111 on page 314 and table 6-114 on page 315 for details) 0 (programmed) (1) bootsz0 1 select boot size (see table 6-111 on page 314 and table 6-114 on page 315 for details) 0 (programmed) (1) bootrst 0 select reset vector 1 (unprogrammed) table 6-125. extended fuse byte for atmel atmega328p extended fuse byte bit no description default value ?7? 1 ?6? 1 ?5? 1 ?4? 1 ?3? 1 bodlevel2 (1) 2 brown-out detector trigger level 1 (unprogrammed) bodlevel1 (1) 1 brown-out detector trigger level 1 (unprogrammed) bodlevel0 (1) 0 brown-out detector trigger level 1 (unprogrammed) table 6-126. fuse high byte for atme l atmega48pa/88pa/168pa high fuse byte bit no desc ription default value rstdisbl (1) 7 external reset disable 1 (unprogrammed) dwen 6 debugwire enable 1 (unprogrammed) spien (2) 5 enable serial program and data downloading 0 (programmed, spi programming enabled) wdton (3) 4 watchdog timer always on 1 (unprogrammed) 322 9159a?auto?09/10 atmel ata6614 [preliminary] notes: 1. see ?alternate functions of port c? on page 111 for description of rstdisbl fuse. 2. the spien fuse is not accessible in serial programming mode. 3. see ?wdtcsr ? watchdog timer control register? on page 79 for details. 4. see table 6-142 on page 343 for bodlevel fuse decoding. notes: 1. see ?alternate functions of port c? on page 111 for description of rstdisbl fuse. 2. the spien fuse is not accessible in serial programming mode. 3. see ?wdtcsr ? watchdog timer control register? on page 79 for details. 4. the default value of bootsz[1:0] results in maximum boot size. see ?pin name mapping? on page 325 . eesave 3 eeprom memory is preserved through the chip erase 1 (unprogrammed), eeprom not reserved bodlevel2 (4) 2 brown-out detector trigger level 1 (unprogrammed) bodlevel1 (4) 1 brown-out detector trigger level 1 (unprogrammed) bodlevel0 (4) 0 brown-out detector trigger level 1 (unprogrammed) table 6-127. fuse high byte for atmel atmega328p high fuse byte bit no desc ription default value rstdisbl (1) 7 external reset disable 1 (unprogrammed) dwen 6 debugwire enable 1 (unprogrammed) spien (2) 5 enable serial program and data downloading 0 (programmed, spi programming enabled) wdton (3) 4 watchdog timer always on 1 (unprogrammed) eesave 3 eeprom memory is preserved through the chip erase 1 (unprogrammed), eeprom not reserved bootsz1 2 select boot size (see table 6-111 on page 314 , table 6-114 on page 315 and table 6-117 on page 316 for details) 0 (programmed) (4) bootsz0 1 select boot size (see table 6-111 on page 314 , table 6-114 on page 315 and table 6-117 on page 316 for details) 0 (programmed) (4) bootrst 0 select reset vector 1 (unprogrammed) table 6-126. fuse high byte for atmel atme ga48pa/88pa/168pa (continued) high fuse byte bit no desc ription default value 323 9159a?auto?09/10 atmel ata6614 [preliminary] note: 1. the default value of sut1..0 results in maximum start-up time for the default clock source. see table 6-15 on page 59 for details. 2. the default setting of cksel3..0 results in internal rc oscillator @ 8 mhz. see table 6-14 on page 59 for details. 3. the ckout fuse allows the system cl ock to be output on portb0. see ?clock output buf- fer? on page 61 for details. 4. see ?system clock prescaler? on page 61 for details. the status of the fuse bits is not affected by chip erase. note that the fuse bits are locked if lock bit1 (lb1) is programmed. program the fuse bits before programming the lock bits. 6.27.2.1 latching of fuses the fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves programmin g mode. this does not apply to the eesave fuse which will take effect once it is programmed. the fuse s are also latched on power-up in normal mode. 6.27.3 signature bytes all atmel ? microcontrollers have a three-byte signature code which identifies the device. this code can be read in both serial and parallel mode, also when the device is locked. the three bytes reside in a separate address space. for the atmel atmega48pa/88pa/168pa/328p the signature bytes are given in table 6-129 . table 6-128. fuse low byte low fuse byte bit no description default value ckdiv8 (4) 7 divide clock by 8 0 (programmed) ckout (3) 6 clock output 1 (unprogrammed) sut1 5 select start-up time 1 (unprogrammed) (1) sut0 4 select start-up time 0 (programmed) (1) cksel3 3 select clock source 0 (programmed) (2) cksel2 2 select clock source 0 (programmed) (2) cksel1 1 select clock source 1 (unprogrammed) (2) cksel0 0 select clock source 0 (programmed) (2) table 6-129. device id part signature bytes address 0x000 0x001 0x002 atmega48pa 0x1e 0x92 0x0a atmega88pa 0x1e 0x93 0x0f atmega168pa 0x1e 0x94 0x0b atmega328p 0x1e 0x95 0x0f 324 9159a?auto?09/10 atmel ata6614 [preliminary] 6.27.4 calibration byte the atmel ? atmega48pa/88pa/168pa/328p has a byte calibration value for the internal rc oscillator. this byte re sides in the high byte of address 0x000 in the signature address space. during reset, this byte is automatically written into the osccal register to ensure correct fre- quency of the calibrated rc oscillator. 6.27.5 page size 6.27.6 parallel programming parameters, pin mapping, and commands this section describes how to parallel program and verify flash program memory, eeprom data memory, memory lock bits, and fuse bits in the atmega48pa/88pa/168pa/328p. pulses are assumed to be at least 250ns unless otherwise noted. 6.27.6.1 signal names in this section, some pins of the atmel atmega48pa/88pa/168pa/328p are referenced by signal names describing their functionality during parallel programming, see figure 6-119 and table 6-132 . pins not described in the following table are referenced by pin names. the xa1/xa0 pins determine the action execut ed when the xtal1 pin is given a positive pulse. the bit coding is shown in table 6-134 . when pulsing wr or oe , the command loaded determines the action executed. the different commands are shown in table 6-135 . table 6-130. no. of words in a page and no. of pages in the flash device flash size page size pcword no. of pages pcpage pcmsb atmega48pa 2k words (4k bytes) 32 words pc[4:0] 64 pc[10:5] 10 atmega88pa 4k words (8k bytes) 32 words pc[4:0] 128 pc[11:5] 11 atmega168pa 8k words (16k bytes) 64 words pc[5:0] 128 pc[12:6] 12 atmega328p 16k words (32k bytes) 64 words pc[5:0] 256 pc[13:6] 13 table 6-131. no. of words in a page and no. of pages in the eeprom device eeprom size page size pcword no. of pages pcpage eeamsb atmega48pa 256 bytes 4 bytes eea[1:0] 64 eea[7:2] 7 atmega88pa 512 bytes 4 bytes eea[1:0] 128 eea[8:2] 8 atmega168pa 512 bytes 4 bytes eea[1:0] 128 eea[8:2] 8 atmega328p 1k bytes 4 bytes eea[1:0] 256 eea[9:2] 9 325 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-119. parallel programming note: v cc - 0.3v < av cc < v cc + 0.3v, however, av cc should always be within 4.5 - 5.5v table 6-132. pin name mapping signal name in programming mode pin name i/o function rdy/bsy pd1 o 0: device is busy programming, 1: device is ready for new command oe pd2 i output enable (active low) wr pd3 i write pulse (active low) bs1 pd4 i byte select 1 (?0? sele cts low byte, ?1? selects high byte) xa0 pd5 i xtal action bit 0 xa1 pd6 i xtal action bit 1 pag e l p d 7 i program memory and eeprom data page load bs2 pc2 i byte select 2 (?0? sele cts low byte, ?1? selects 2?nd high byte) data {pc[1:0]: pb[5:0]} i/o bi-directional data bus (output when oe is low) table 6-133. pin values used to enter programming mode pin symbol value pagel prog_enable[3] 0 xa1 prog_enable[2] 0 xa0 prog_enable[1] 0 bs1 prog_enable[0] 0 vcc gnd xtal1 pd1 pd2 pd3 pd4 pd5 pd6 pc[1:0]:pb[5:0] data reset pd7 +12 v bs1 xa0 xa1 oe rdy/bsy pagel pc2 wr bs2 avcc +4.5 - 5.5v +4.5 - 5.5v 326 9159a?auto?09/10 atmel ata6614 [preliminary] 6.27.7 parallel programming 6.27.7.1 enter programming mode the following algorithm puts the device in parallel (high-voltage) programming mode: 1. set prog_enable pins listed in table 6-133 on page 325 to ?0000?, reset pin to 0v and v cc to 0v. 2. apply 4.5 - 5.5v between v cc and gnd. ensure that v cc reaches at least 1.8v within the next 20s. 3. wait 20 - 60s, and apply 11.5 - 12.5v to reset. 4. keep the prog_enable pins unchanged for at least 10s after the high-voltage has been applied to ensure the prog_enable signature has been latched. 5. wait at least 300s before giving any parallel programming commands. 6. exit programming mode by power the device down or by bringing reset pin to 0v. if the rise time of the v cc is unable to fulfill the requirements lis ted above, the following alterna- tive algorithm can be used. 1. set prog_enable pins listed in table 6-133 on page 325 to ?0000?, reset pin to 0v and v cc to 0v. 2. apply 4.5 - 5.5v between v cc and gnd. 3. monitor v cc , and as soon as v cc reaches 0.9 - 1.1v, apply 11.5 - 12.5v to reset. table 6-134. xa1 and xa0 coding xa1 xa0 action when xtal1 is pulsed 00 load flash or eeprom address (high or low address byte determined by bs1). 0 1 load data (high or low data byte for flash determined by bs1). 1 0 load command 1 1 no action, idle table 6-135. command byte bit coding command byte command executed 1000 0000 chip erase 0100 0000 write fuse bits 0010 0000 write lock bits 0001 0000 write flash 0001 0001 write eeprom 0000 1000 read signature bytes and calibration byte 0000 0100 read fuse and lock bits 0000 0010 read flash 0000 0011 read eeprom 327 9159a?auto?09/10 atmel ata6614 [preliminary] 4. keep the prog_enable pins unchanged for at least 10s after the high-voltage has been applied to ensure the prog_enable signature has been latched. 5. wait until v cc actually reaches 4.5 -5.5v before giving any parallel programming commands. 6. exit programming mode by power the device down or by bringing reset pin to 0v. 6.27.7.2 considerations for efficient programming the loaded command and address are retained in the device during programming. for effi- cient programming, the following should be considered. ? the command needs only be loaded once when writing or reading multiple memory locations. ? skip writing the data value 0xff, that is the contents of the entire eeprom (unless the eesave fuse is programmed) and flash after a chip erase. ? address high byte needs only be loaded before programming or reading a new 256 word window in flash or 256 byte eeprom. this consideration also applies to signature bytes reading. 6.27.7.3 chip erase the chip erase will erase the flash and eeprom (1) memories plus lock bits. the lock bits are not reset until the program memory has been completely erased. the fuse bits are not changed. a chip erase must be performe d before the flash and/or eeprom are reprogrammed. note: 1. the eeprpom memory is preserved during chip erase if the eesave fuse is programmed. load command ?chip erase? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?1000 0000?. this is the command for chip erase. 4. give xtal1 a positive pulse. this loads the command. 5. give wr a negative pulse. this starts the chip erase. rdy/bsy goes low. 6. wait until rdy/bsy goes high before loading a new command. 6.27.7.4 programming the flash the flash is organized in pages, see table 6-130 on page 324 . when programming the flash, the program data is latched into a page buffer. this allows one page of program data to be programmed simultaneously. the following proc edure describes how to program the entire flash memory: a. load command ?write flash? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?0001 0000?. this is the command for write flash. 4. give xtal1 a positive pulse. this loads the command. b. load address low byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?0?. this selects low address. 328 9159a?auto?09/10 atmel ata6614 [preliminary] 3. set data = address low byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address low byte. c. load data low byte 1. set xa1, xa0 to ?01?. this enables data loading. 2. set data = data low byte (0x00 - 0xff). 3. give xtal1 a positive pulse. this loads the data byte. d. load data high byte 1. set bs1 to ?1?. this selects high data byte. 2. set xa1, xa0 to ?01?. this enables data loading. 3. set data = data high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the data byte. e. latch data 1. set bs1 to ?1?. this selects high data byte. 2. give pagel a positive pulse. this latches the data bytes. (see figure 6-121 for signal waveforms) f. repeat b through e until the entire buffer is filled or until all data within the page is loaded. while the lower bits in the address are mapped to words within the page, the higher bits address the pages within the fl ash. this is illustrated in figure 6-120 on page 329 . note that if less than eight bits are required to address words in the page (pagesize < 256), the most sig- nificant bit(s) in the address low byte are used to address the page when performing a page write. g. load address high byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?1?. this selects high address. 3. set data = address high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address high byte. h. program page 1. give wr a negative pulse. this starts programming of the entire page of data. rdy/bsy goes low. 2. wait until rdy/bsy goes high (see figure 6-121 for signal waveforms). i. repeat b through h until the entire flash is programmed or until all data has been programmed. j. end page programming 1. 1. set xa1, xa0 to ?10?. this enables command loading. 2. set data to ?0000 0000?. this is the command for no operation. 3. give xtal1 a positive pulse. this loads the command, and the internal write signals are reset. 329 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-120. addressing the flash which is organized in pages (1) note: 1. pcpage and pcword are listed in table 6-130 on page 324 . figure 6-121. programming the flash waveforms (1) note: 1. ?xx? is don?t care. the letters re fer to the programming description above. 6.27.7.5 programming the eeprom the eeprom is organized in pages, see table 6-131 on page 324 . when programming the eeprom, the program data is latched into a page buffer. this allows one page of data to be programmed simultan eously. the programming algorithm for the eeprom data memory is as follows (refer to ?programming the flash? on page 327 for details on command, address and data loading): 1. a: load command ?0001 0001?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. c: load data (0x00 - 0xff). program memory word address within a page page address within the flash instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter rdy/bsy wr oe reset +12v pagel bs2 0x10 addr. low addr. high data data low data high addr. low data low data high xa1 xa0 bs1 xtal1 xx xx xx abcdeb cdegh f 330 9159a?auto?09/10 atmel ata6614 [preliminary] 5. e: latch data (give pagel a positive pulse). k: repeat 3 through 5 until the entire buffer is filled. l: program eeprom page 1. set bs1 to ?0?. 2. give wr a negative pulse. this starts prog ramming of the eeprom page. rdy/bsy goes low. 3. wait until to rdy/bsy goes high before programming the next page (see figure 6-122 for signal waveforms). figure 6-122. programming the eeprom waveforms 6.27.7.6 reading the flash the algorithm for reading the flash memory is as follows (refer to ?programming the flash? on page 327 for details on command and address loading): 1. a: load command ?0000 0010?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the flash word low byte can now be read at data. 5. set bs1 to ?1?. the flash word high byte can now be read at data. 6. set oe to ?1?. 6.27.7.7 reading the eeprom the algorithm for reading the eeprom memory is as follows (refer to ?programming the flash? on page 327 for details on command and address loading): 1. a: load command ?0000 0011?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the eeprom data byte can now be read at data. 5. set oe to ?1?. rdy/bsy wr oe reset +12v pagel bs2 0x11 addr. high data addr. low data addr. low data xx xa1 xa0 bs1 xtal1 xx agbceb c el k 331 9159a?auto?09/10 atmel ata6614 [preliminary] 6.27.7.8 programming the fuse low bits the algorithm for programming the fuse low bits is as follows (refer to ?programming the flash? on page 327 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. give wr a negative pulse and wait for rdy/bsy to go high. 6.27.7.9 programming the fuse high bits the algorithm for programming the fuse high bits is as follows (refer to ?programming the flash? on page 327 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs1 to ?1? and bs2 to ?0?. this selects high data byte. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. set bs1 to ?0?. this selects low data byte. 6.27.7.10 programming the extended fuse bits the algorithm for programming the extended fuse bits is as follows (refer to ?programming the flash? on page 327 for details on command and data loading): 1. 1. a: load command ?0100 0000?. 2. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. 3. set bs1 to ?0? and bs2 to ?1?. this selects extended data byte. 4. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. 5. set bs2 to ?0?. this selects low data byte. figure 6-123. programming t he fuses waveforms rdy/bsy wr oe reset +12v pagel 0x40 data data xx xa1 xa0 bs1 xtal1 ac 0x40 data xx ac write fuse low byte write fuse high byte 0x40 data xx ac write extended fuse byte bs2 332 9159a?auto?09/10 atmel ata6614 [preliminary] 6.27.7.11 programming the lock bits the algorithm for programming the lock bits is as follows (refer to ?programming the flash? on page 327 for details on command and data loading): 1. a: load command ?0010 0000?. 2. c: load data low byte. bit n = ?0? programs the lock bit. if lb mode 3 is programmed (lb1 and lb2 is programmed), it is not possible to program the boot lock bits by any external programming mode. 3. give wr a negative pulse and wait for rdy/bsy to go high. the lock bits can only be cleared by executing chip erase. 6.27.7.12 reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follows (refer to ?programming the flash? on page 327 for details on command loading): 1. a: load command ?0000 0100?. 2. set oe to ?0?, bs2 to ?0? and bs1 to ?0?. the status of the fuse low bits can now be read at data (?0? means programmed). 3. set oe to ?0?, bs2 to ?1? and bs1 to ?1?. the status of the fuse high bits can now be read at data (?0? means programmed). 4. set oe to ?0?, bs2 to ?1?, and bs1 to ?0?. the status of the extended fuse bits can now be read at data (?0? means programmed). 5. set oe to ?0?, bs2 to ?0? and bs1 to ?1?. the status of the lock bits can now be read at data (?0? means programmed). 6. set oe to ?1?. figure 6-124. mapping between bs1, bs2 and the fuse and lock bits during read 6.27.7.13 reading the signature bytes the algorithm for reading the signature bytes is as follows (refer to ?programming the flash? on page 327 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte (0x00 - 0x02). 3. set oe to ?0?, and bs1 to ?0?. the selected signature byte can now be read at data. 4. set oe to ?1?. lock bits 0 1 bs2 fuse high byte 0 1 bs1 data fuse low byte 0 1 bs2 extended fuse byte 333 9159a?auto?09/10 atmel ata6614 [preliminary] 6.27.7.14 reading the calibration byte the algorithm for reading the calibrati on byte is as follows (refer to ?programming the flash? on page 327 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte, 0x00. 3. set oe to ?0?, and bs1 to ?1?. the calibration byte can now be read at data. 4. set oe to ?1?. 6.27.7.15 parallel programming characteristics for chracteristics of the parallel programming, see ?parallel programming characteristics? on page 348 . 6.27.8 serial downloading both the flash and eeprom memory arrays can be programmed using the serial spi bus while reset is pulled to gnd. the serial interface consists of pins sck, mosi (input) and miso (output). after reset is set low, the programming enable instruction needs to be exe- cuted first before program/erase ope rations can be executed. note, in table 6-136 on page 334 , the pin mapping for spi programming is listed. not all parts use the spi pins dedicated for the internal spi interface. figure 6-125. serial programming and verify (1) notes: 1. if the device is clocked by the internal oscillator, it is no need to connect a clock source to the xtal1 pin. 2. v cc - 0.3v < av cc < v cc + 0.3v, however, av cc should always be within 1.8 - 5.5v when programming the eeprom, an auto-erase cycl e is built into the self-timed program- ming operation (in the serial mode only) and there is no need to first execute the chip erase instruction. the chip erase operation turns the content of every memory location in both the program and eeprom arrays into 0xff. depending on cksel fuses, a valid clock must be present. th e minimum low a nd high peri- ods for the serial clock (sck) input are defined as follows: low: > 2 cpu clock cycles for f ck < 12mhz, 3 cpu clock cycles for f ck 12mhz high: > 2 cpu clock cycles for f ck < 12mhz, 3 cpu clock cycles for f ck 12mhz vcc gnd xtal1 sck miso mosi reset +1.8 - 5.5v avcc +1.8 - 5.5v (2) 334 9159a?auto?09/10 atmel ata6614 [preliminary] 6.27.8.1 serial programming pin mapping 6.27.8.2 serial programming algorithm when writing serial data to the atmel ? atmega48pa/88pa/168pa/328p, data is clocked on the rising edge of sck. when reading data from the atmel atmega48pa/88pa/168pa/328p, data is clocked on the falling edge of sck. see figure 6-127 for timing details. to program and verify the atmel atmega48pa/88pa/168pa/328p in the serial programming mode, the following sequence is recommended (s ee serial programming instruction set in table 6-138 on page 335 ): 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ?0?. in some sys- tems, the programmer can not guarantee that sck is held low during power-up. in this case, reset must be given a positive pulse of at least two cpu clock cycles duration after sck has been set to ?0?. 2. wait for at least 2ms and enable serial programming by sending the programming enable serial instruction to pin mosi. 3. the serial programming instructions will not work if the communication is out of syn- chronization. when in sync. the second byte (0x53), will echo back when issuing the third byte of the programming enable instruction. whether the echo is correct or not, all four bytes of the instruction must be transmitted. if the 0x53 did not echo back, give reset a positive pulse and issue a new programming enable command. 4. the flash is programmed one page at a time. the memory page is loaded one byte at a time by supplying the 6lsb of the address and data together with the load program memory page instruction. to ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. the program memory page is stored by loading the writ e program memory page instruction with the 7msb of the address. if polling (rdy/bsy ) is not used, the user must wait at least t wd_flash before issuing the next page (see table 6-137 ). accessing the serial pro- gramming interface before the flash write op eration completes can result in incorrect programming. 5. a : the eeprom array is programmed one byte at a time by supplying the address and data together with the appropriate write instruction. an eeprom memory location is first automatically erased before new data is written. if polling (rdy/bsy ) is not used, the user must wait at least t wd_eeprom before issuing the next byte (see table 6-137 ). in a chip erased device, no 0xffs in the data file(s) need to be programmed. b : the eeprom array is progra mmed one page at a time. the memory page is loaded one byte at a time by supplying the 6 lsb of the address and data together with the load eeprom memory page instruction. the eeprom me mory page is stored by loading the write eeprom memory page inst ruction with the 7 msb of the address. when using eeprom page access only by te locations loaded with the load eeprom memory page instruction is altered. the remaining locations remain unchanged. table 6-136. pin mapping serial programming symbol pins i/o description mosi pb3 i serial data in miso pb4 o serial data out sck pb5 i serial clock 335 9159a?auto?09/10 atmel ata6614 [preliminary] if polling (rdy/bsy ) is not used, the used must wait at least t wd_eeprom before issuing the next byte (see table 6-137 ). in a chip erased device, no 0xff in the data file(s) need to be programmed. 6. any memory location can be verified by using the read instruction which returns the content at the selected address at serial output miso. 7. at the end of the programming session, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set reset to ?1?. tu r n v cc power off. 6.27.8.3 serial programming instruction set table 6-138 on page 335 and figure 6-126 on page 337 describes the instruction set. table 6-137. typical wait delay before writing the next flash or eeprom location symbol minimum wait delay t wd_flash 4.5 ms t wd_eeprom 3.6 ms t wd_erase 9.0 ms table 6-138. serial programming instruction set (hexadecimal values) instruction/operation instruction format byte 1 byte 2 byte 3 byte4 programming enable $ac $53 $00 $00 chip erase (program memory/eeprom) $ac $80 $00 $00 poll rdy/bsy $f0 $00 $00 data byte out load instructions load extended address byte (1) $4d $00 extended adr $00 load program memory page, high byte $48 $00 adr lsb high data byte in load program memory page, low byte $40 $00 adr lsb low data byte in load eeprom memory page (page access) $c1 $00 0000 000aa data byte in read instructions read program memory, high byte $28 adr msb adr lsb high data byte out read program memory, low byte $20 adr msb adr lsb low data byte out read eeprom memory $a0 0000 00aa aaaa aaaa data byte out read lock bits $58 $00 $00 data byte out read signature byte $30 $00 0000 000aa data byte out read fuse bits $50 $00 $00 data byte out read fuse high bits $58 $08 $00 data byte out read extended fuse bits $50 $08 $00 data byte out 336 9159a?auto?09/10 atmel ata6614 [preliminary] notes: 1. not all instructions are applicable for all parts. 2. a = address. 3. bits are programmed ?0?, unprogrammed ?1?. 4. to ensure future compatibility, unused fuses and lock bits should be unprogrammed (?1?) . 5. refer to the correspondig section for fuse and lock bits, calibration and signature bytes and page size. 6. instructions accessing program memory use a word address. this address may be random within the page range. 7. see htt://www.atmel.com/avr for application notes regarding programming and programmers. if the lsb in rdy/bsy data byte out is ?1?, a program ming operation is still pending. wait until this bit returns ?0? before the ne xt instruction is carried out. within the same page, the low data byte must be loaded prior to the high data byte. after data is l oaded to the page buffer, pr ogram the eeprom page, see figure 6-126 on page 337 . read calibration byte $38 $00 $00 data byte out write instructions (6) write program memory page $4c adr msb adr lsb $00 write eeprom memory $c0 0000 00aa aaaa aaaa data byte in write eeprom memory page (page access) $c2 0000 00aa aaaa aa00 $00 write lock bits $ac $e0 $00 data byte in write fuse bits $ac $a0 $00 data byte in write fuse high bits $ac $a8 $00 data byte in write extended fuse bits $ac $a4 $00 data byte in table 6-138. serial programming instruction set (hexadecimal values) (continued) instruction/operation instruction format byte 1 byte 2 byte 3 byte4 337 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-126. serial programming instruction example 6.27.8.4 spi serial programming characteristics figure 6-127. serial programming waveforms for characteristics of the spi module see ?spi timing characteristics? on page 344. byte 1 byte 2 byte 3 byte 4 adr lsb bit 15 b 0 serial programming instruction program memory/ eeprom memory page 0 page 1 page 2 page n-1 page buffer write program memory page/ write eeprom memory page load program memory page (high/low byte)/ load eeprom memory page (page access) byte 1 byte 2 byte 3 byte 4 bit 15 b 0 adr msb page offset page number ad r m ms sb a a adr r l lsb b msb msb lsb lsb serial clock input (sck) serial data input (mosi) (miso) sample serial data output 338 9159a?auto?09/10 atmel ata6614 [preliminary] 6.28 electrical characteristics 6.28.1 absolute maximum ratings* 6.28.2 dc characteristics operating temperature.................................. -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c voltage on any pin except reset with respect to ground ................................-0.5v to v cc +0.5v voltage on reset with respect to ground......-0.5v to +13.0v maximum operating voltage ............................................ 6.0v dc current per i/o pin ................................................ 40.0ma dc current v cc and gnd pins................................. 200.0ma t a = -40c to 85c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. max. units v il input low voltage, except xtal1 and reset pin v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v -0.5 -0.5 0.2v cc (1) 0.3v cc (1) v v ih input high voltage, except xtal1 and reset pins v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v 0.7v cc (2) 0.6v cc (2) v cc + 0.5 v cc + 0.5 v v il1 input low voltage, xtal1 pin v cc = 1.8v - 5.5v -0.5 0.1v cc (1) v v ih1 input high voltage, xtal1 pin v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v 0.8v cc (2) 0.7v cc (2) v cc + 0.5 v cc + 0.5 v v il2 input low voltage, reset pin v cc = 1.8v - 5.5v -0.5 0.1v cc (1) v v ih2 input high voltage, reset pin v cc = 1.8v - 5.5v 0.9v cc (2) v cc + 0.5 v v il3 input low voltage, reset pin as i/o v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v -0.5 -0.5 0.2v cc (1) 0.3v cc (1) v v ih3 input high voltage, reset pin as i/o v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v 0.7v cc (2) 0.6v cc (2) v cc + 0.5 v cc + 0.5 v v ol output low voltage (3) except reset pin i ol = 20 ma, v cc = 5v i ol = 10 ma, v cc = 3v 0.9 0.6 v v oh output high voltage (4) except reset pin i oh = -20 ma, v cc = 5v i oh = -10 ma, v cc = 3v 4.2 2.3 v i il input leakage current i/o pin v cc = 5.5v, pin low (absolute value) 1a i ih input leakage current i/o pin v cc = 5.5v, pin high (absolute value) 1a r rst reset pull-up resistor 30 60 k r pu i/o pin pull-up resistor 20 50 k 339 9159a?auto?09/10 atmel ata6614 [preliminary] notes: 1. ?max? means the highest value where the pin is guaranteed to be read as low 2. ?min? means the lowest value where t he pin is guaranteed to be read as high 3. although each i/o port can sink more than the test conditions (20ma at v cc = 5v, 10 ma at v cc = 3v) under steady state conditions (non-transient), th e following must be observed: atmel atmega48pa/88pa/168pa/328p: 1] the sum of all i ol , for ports c0 - c5, adc7, adc6 should not exceed 100ma. 2] the sum of all i ol , for ports b0 - b5, d5 - d7, xtal1, xtal2 should not exceed 100ma. 3] the sum of all i ol , for ports d0 - d4, reset should not exceed 100ma. if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test condition. 4. although each i/o port can source more than the test conditions (20ma at v cc = 5v, 10ma at v cc = 3v) under steady state conditions (non-transient), th e following must be observed: atmel atmega48pa/88pa/168pa/328p: 1] the sum of all i oh , for ports c0 - c5, d0- d4, adc7, reset should not exceed 150ma. 2] the sum of all i oh , for ports b0 - b5, d5 - d7, adc6, xtal1, xtal2 should not exceed 150ma. if ii oh exceeds the test condition, v oh may exceed the related specification. pi ns are not guaranteed to source current greater than the listed test condition. 6.28.2.1 atmega48pa dc characteristics notes: 1. values with ?minimizing power consumption? enabled (0xff). 2. typical values at 25c. maximum values are char acterized values and not test limits in production. 3. the current consumption values include input leakage current. v acio analog comparator input offset voltage v cc = 5v v in = v cc /2 <10 40 mv i aclk analog comparator input leakage current v cc = 5v v in = v cc /2 -50 50 na t acid analog comparator propagation delay v cc = 2.7v v cc = 4.0v 750 500 ns t a = -40c to 85c, v cc = 1.8v to 5.5v (unless otherwise noted) (continued) symbol parameter condition min. typ. max. units t a = -40c to 85c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. (2) max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.2 0.5 ma active 4mhz, v cc = 3v 1.2 2.5 ma active 8mhz, v cc = 5v 4.0 9 ma idle 1mhz, v cc = 2v 0.03 0.15 ma idle 4mhz, v cc = 3v 0.21 0.7 ma idle 8mhz, v cc = 5v 0.9 2.7 ma power-save mode (3) 32khz tosc enabled, v cc = 1.8v 0.75 a 32khz tosc enabled, v cc = 3v 0.9 a power-down mode (3) wdt enabled, v cc = 3v 3.9 8 a wdt disabled, v cc = 3v 0.1 2 a 340 9159a?auto?09/10 atmel ata6614 [preliminary] 6.28.2.2 atmega88pa dc characteristics notes: 1. values with ?minimizing power consumption? enabled (0xff). 2. typical values at 25c. maximum values are test limits in production. 3. the current consumption values include input leakage current. 6.28.2.3 atmega168pa dc characteristics notes: 1. values with ?minimizing power consumption? enabled (0xff). 2. typical values at 25c. maximum values are test limits in production. 3. the current consumption values include input leakage current. t a = -40c to 85c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. (2) max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.2 0.5 ma active 4mhz, v cc = 3v 1.2 2.5 ma active 8mhz, v cc = 5v 4.1 9 ma idle 1mhz, v cc = 2v 0.03 0.15 ma idle 4mhz, v cc = 3v 0.18 0.7 ma idle 8mhz, v cc = 5v 0.8 2.7 ma power-save mode (3) 32khz tosc enabled, v cc = 1.8v 0.8 a 32khz tosc enabled, v cc = 3v 0.9 a power-down mode (3) wdt enabled, v cc = 3v 3.9 8 a wdt disabled, v cc = 3v 0.1 2 a t a = -40c to 85c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. (2) max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.2 0.5 ma active 4mhz, v cc = 3v 1.2 2.5 ma active 8mhz, v cc = 5v 4.2 9 ma idle 1mhz, v cc = 2v 0.03 0.15 ma idle 4mhz, v cc = 3v 0.2 0.7 ma idle 8mhz, v cc = 5v 0.9 2.7 power-save mode (3) 32khz tosc enabled, v cc = 1.8v 0.75 a 32khz tosc enabled, v cc = 3v 0.83 a power-down mode (3) wdt enabled, v cc = 3v 4.1 8 a wdt disabled, v cc = 3v 0.1 2 a 341 9159a?auto?09/10 atmel ata6614 [preliminary] 6.28.2.4 atmega328p dc characteristics notes: 1. values with ?minimizing power consumption? enabled (0xff). 2. typical values at 25c. maximum values are test limits in production. 3. the current consumption values include input leakage current. 4. maximum values are characterized values and not test limits in production. 6.28.3 speed grades maximum frequency is dependent on v cc. as shown in figure 6-128 , the maximum frequency vs. v cc curve is linear between 1.8v < v cc < 2.7v and between 2.7v < v cc < 4.5v. figure 6-128. maximum frequency vs. v cc t a = -40c to 85c, v cc = 1.8v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. (2) max. units i cc power supply current (1) active 1mhz, v cc = 2v 0.3 0.5 ma active 4mhz, v cc = 3v 1.7 2.5 ma active 8mhz, v cc = 5v 5.2 9 ma idle 1mhz, v cc = 2v 0.04 0.15 ma idle 4mhz, v cc = 3v 0.3 0.7 ma idle 8mhz, v cc = 5v 1.2 2.7 ma power-save mode (3)(4) 32khz tosc enabled, v cc = 1.8v 0.8 1.6 a 32khz tosc enabled, v cc = 3v 0.9 2.6 a power-down mode (3) wdt enabled, v cc = 3v 4.2 8 a wdt disabled, v cc = 3v 0.1 2 a 4 mhz 1. 8 v 2.7v 4.5v 10 mhz 20 mhz 5.5v sa fe oper a ting are a 342 9159a?auto?09/10 atmel ata6614 [preliminary] 6.28.4 clock characteristics 6.28.4.1 calibrated internal rc oscillator accuracy 6.28.4.2 external clock drive waveforms figure 6-129. external clock drive waveforms 6.28.4.3 external clock drive note: all dc characteristics contained in this datasheet are bas ed on simulation and characterization of other avr microcontroll ers manufactured in the same process technology. these values are preliminary values representing design targets, and will be updated after characterization of actual silicon. table 6-139. calibration accuracy of internal rc oscillator frequency v cc temperature calibration accuracy factory calibration 8.0mhz 3v 25c 10% user calibration 7.3 - 8.1mhz 1.8v - 5.5v -40c - 85c 1% v il1 v ih1 table 6-140. external clock drive symbol parameter v cc = 1.8 - 5.5v v cc = 2.7 - 5.5v v cc = 4.5 - 5.5v units min. max. min. max. min. max. 1/t clcl oscillator frequency 0 4 0 10 0 20 mhz t clcl clock period 250 100 50 ns t chcx high time 100 40 20 ns t clcx low time 100 40 20 ns t clch rise time 2.0 1.6 0.5 s t chcl fall time 2.0 1.6 0.5 s t clcl change in period from one clock cycle to the next 22 2% 343 9159a?auto?09/10 atmel ata6614 [preliminary] 6.28.5 system and reset characteristics notes: 1. values are guidelines only. 2. the power-on reset will not work unless the supply voltage has been below v pot (falling) notes: 1. v bot may be below nominal minimum operating voltage for some devices. for devices where this is the case, the device is tested down to v cc = v bot during the production test. this guarantees that a brown-out reset will occur before v cc drops to a voltage where correct operation of the microcontroller is no longer guaran teed. the test is performed using bodlevel = 110, 101 and 100. table 6-141. reset, brown-out and internal voltage characteristics (1) symbol parameter min typ max units v pot power-on reset threshold voltage (rising) 1.1 1.4 1.6 v power-on reset threshold voltage (falling) (2) 0.6 1.3 1.6 v sr on power-on slope rate 0.01 10 v/ms v rst reset pin threshold voltage 0.2 v cc 0.9 v cc v t rst minimum pulse width on reset pin 2.5 s v hyst brown-out detector hysteresis 50 mv t bod min pulse width on brown-out reset 2 s v bg bandgap reference voltage v cc =2.7 t a =25c 1.0 1.1 1.2 v t bg bandgap reference start-up time v cc =2.7 t a =25c 40 70 s i bg bandgap reference current consumption v cc =2.7 t a =25c 10 a table 6-142. bodlevel fuse coding (1) bodlevel 2:0 fuses min v bot typ v bot max v bot units 111 bod disabled 110 1.7 1.8 2.0 v 101 2.5 2.7 2.9 100 4.1 4.3 4.5 011 reserved 010 001 000 344 9159a?auto?09/10 atmel ata6614 [preliminary] 6.28.6 spi timing characteristics see figure 6-130 and figure 6-131 for details. note: 1. in spi programming mode the minimum sck high/low period is: - 2 t clcl for f ck < 12mhz - 3 t clcl for f ck > 12mhz 2. all dc characteristics contained in this datas heet are based on simulation and characteriza- tion of other avr microcontrollers manufactur ed in the same process technology. these values are preliminary values representing desi gn targets, and will be updated after charac- terization of actual silicon. figure 6-130. spi interface timing requirements (master mode) table 6-143. spi timing parameters description mode min typ max 1 sck period master see table 6-72 ns 2 sck high/low master 50% duty cycle 3 rise/fall time master 3.6 4 setup master 10 5 hold master 10 6 out to sck master 0.5 ? t sck 7 sck to out master 10 8 sck to out high master 10 9ss low to out slave 15 10 sck period slave 4 ? t ck 11 sck high/low (1) slave 2 ? t ck 12 rise/fall time slave 1600 13 setup slave 10 14 hold slave t ck 15 sck to out slave 15 16 sck to ss high slave 20 17 ss high to tri-state slave 10 18 ss low to sck slave 20 mo si (data output) sck (cpol = 1) mi so (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 61 22 3 45 8 7 345 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-131. spi interface timing requirements (slave mode) mi so (data output) sck (cpol = 1) mo si (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 10 11 11 12 13 14 17 15 9 x 16 346 9159a?auto?09/10 atmel ata6614 [preliminary] 6.28.7 2-wire serial interface characteristics table 6-144 describes the requirements for devices connected to the 2-wire serial bus. the atmel ? atmega48pa/88pa/168pa/328p 2-wire serial interface meets or exceeds these requirements under the noted conditions. timing symbols refer to figure 6-132 . notes: 1. in atmel atmega48pa/88pa/168pa/328p, this parameter is characterized and not 100% tested. 2. required only for f scl > 100khz. 3. c b = capacitance of one bus line in pf. 4. f ck = cpu clock frequency 5. this requirement applies to all atmega48pa/88pa/168pa/328p 2- wire serial interface operation. other devices connected to the 2-wire serial bus need only obey the general f scl requirement. table 6-144. 2-wire serial bus requirements symbol parameter condition min max units v il input low-voltage -0.5 0.3 v cc v v ih input high-voltage 0.7 v cc v cc + 0.5 v v hys (1) hysteresis of schmitt trigger inputs 0.05 v cc (2) ?v v ol (1) output low-voltage 3 ma sink current 0 0.4 v t r (1) rise time for both sda and scl 20 + 0.1c b (3)(2) 300 ns t of (1) output fall time from v ihmin to v ilmax 10 pf < c b < 400 pf (3) 20 + 0.1c b (3)(2) 250 ns t sp (1) spikes suppressed by input filter 0 50 (2) ns i i input current each i/o pin 0.1v cc < v i < 0.9v cc -10 10 a c i (1) capacitance for each i/o pin ? 10 pf f scl scl clock frequency f ck (4) > max(16f scl , 250khz) (5) 0 400 khz rp value of pull-up resistor f scl 100 khz f scl > 100khz t hd;sta hold time (repeated) start condition f scl 100khz 4.0 ? s f scl > 100khz 0.6 ? s t low low period of the scl clock f scl 100khz 4.7 ? s f scl > 100khz 1.3 ? s t high high period of the scl clock f scl 100khz 4.0 ? s f scl > 100khz 0.6 ? s t su;sta set-up time for a repeated start condition f scl 100khz 4.7 ? s f scl > 100khz 0.6 ? s t hd;dat data hold time f scl 100khz 0 3.45 s f scl > 100khz 0 0.9 s t su;dat data setup time f scl 100khz 250 ? ns f scl > 100khz 100 ? ns t su;sto setup time for stop condition f scl 100khz 4.0 ? s f scl > 100khz 0.6 ? s t buf bus free time between a stop and start condition f scl 100khz 4.7 ? s f scl > 100khz 1.3 ? s v cc 0,4v ? 3ma ---------------------------- 1000ns c b ------------------- v cc 0,4v ? 3ma ---------------------------- 300ns c b --------------- - 347 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-132. 2-wire serial bus timing 6.28.8 adc characteristics note: 1. av cc absolute min/max: 1.8v/5.5v t su;sta t low t high t low t of t hd;sta t hd;dat t su;dat t su;sto t buf scl sda t r table 6-145. adc characteristics symbol parameter condi tion min typ max units resolution 10 bits absolute accuracy (including inl, dnl, quantization error, gain and offset error) v ref = 4v, v cc = 4v, adc clock = 200khz 2lsb v ref = 4v, v cc = 4v, adc clock = 1mhz 4.5 lsb v ref = 4v, v cc = 4v, adc clock = 200khz noise reduction mode 2lsb v ref = 4v, v cc = 4v, adc clock = 1mhz noise reduction mode 4.5 lsb integral non-linearity (inl) v ref = 4v, v cc = 4v, adc clock = 200khz 0.5 lsb differential non-linearity (dnl) v ref = 4v, v cc = 4v, adc clock = 200khz 0.25 lsb gain error v ref = 4v, v cc = 4v, adc clock = 200khz 2lsb offset error v ref = 4v, v cc = 4v, adc clock = 200khz 2lsb conversion time free running conversion 13 260 s clock frequency 50 1000 khz av cc (1) analog supply voltage v cc - 0.3 v cc + 0.3 v v ref reference voltage 1.0 av cc v v in input voltage gnd v ref v input bandwidth 38.5 khz v int internal voltage reference 1.0 1.1 1.2 v r ref reference input resistance 32 k r ain analog input resistance 100 m 348 9159a?auto?09/10 atmel ata6614 [preliminary] 6.28.9 parallel programming characteristics notes: 1. t wlrh is valid for the write flash, write eepro m, write fuse bits and write lock bits commands. 2. t wlrh_ce is valid for the chip erase command. table 6-146. parallel programming characteristics, v cc = 5v 10% symbol parameter min typ max units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 250 a t dvxh data and control valid before xtal1 high 67 ns t xlxh xtal1 low to xtal1 high 200 ns t xhxl xtal1 pulse width high 150 ns t xldx data and control hold after xtal1 low 67 ns t xlwl xtal1 low to wr low 0 ns t xlph xtal1 low to pagel high 0 ns t plxh pagel low to xtal1 high 150 ns t bvph bs1 valid before pagel high 67 ns t phpl pagel pulse width high 150 ns t plbx bs1 hold after pagel low 67 ns t wlbx bs2/1 hold after wr low 67 ns t plwl pagel low to wr low 67 ns t bvwl bs1 valid to wr low 67 ns t wlwh wr pulse width low 150 ns t wlrl wr low to rdy/bsy low 0 1 s t wlrh wr low to rdy/bsy high (1) 3.7 4.5 ms t wlrh_ce wr low to rdy/bsy high for chip erase (2) 7.5 9 ms t xlol xtal1 low to oe low 0 ns t bvdv bs1 valid to data valid 0 250 ns t oldv oe low to data valid 250 ns t ohdz oe high to data tri-stated 250 ns 349 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-133. parallel programming timing, including some general timing requirements figure 6-134. parallel programming timing, loading sequence with timing requirements (1) note: 1. the timing requirements shown in figure 6-133 (i.e., t dvxh , t xhxl , and t xldx ) also apply to loading operation. figure 6-135. parallel programming timing, reading sequence (within the same page) with timing requirements (1) note: 1. the timing requirements shown in figure 6-133 (i.e., t dvxh , t xhxl , and t xldx ) also apply to reading operation. data & contol (data, xa0/1, bs1, bs2) xtal1 t xhxl t wlwh t dvxh t xldx t plwl t wlrh wr rdy/bsy pagel t phpl t plbx t bvph t xlwl t wlbx t bvwl wlrl xtal1 pagel t plxh xlxh t t xlph addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) load data (low byte) load data (high byte) load data load address (low byte) xtal1 oe addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) read data (low byte) read data (high byte) load address (low byte) t bvdv t oldv t xlol t ohdz 350 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29 typical characteristics the following charts show typical behavior. these figures are not tested during manufacturing. all current consumption measurements are performed with all i/o pins configured as inputs and with internal pull-ups enabled. a square wave generator with rail-to-rail output is used as clock source. all active- and idle current consumption measurements are done with all bits in the prr reg- ister set and thus, the corresponding i/o modules are turned off. also the analog comparator is disabled during these measurements. the ?atmega88pa: supply current of io modules? on page 380 and page 404 shows the additional current consumption compared to i cc active and i cc idle for every i/o module controlled by the power reduction register. see ?power reduction register? on page 67 for details. the power consumption in power-down mode is independent of clock selection. the current consumption is a function of several factors such as: operating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code executed and ambient tempera- ture. the dominating factors are operating voltage and frequency. the current drawn from capacitive loaded pins may be estimated (for one pin) as c l * v cc *f where c l = load capacitance, v cc = operating voltage and f = average switching frequency of i/o pin. the parts are characterized at frequencies higher than test limits. parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. the difference between current consumptio n in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled represents the differential cur- rent drawn by the watchdog timer. 351 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.1 atmega48pa typical characteristics 6.29.1.1 active supply current figure 6-136. atmel ? atmega48pa: active supply current vs. low frequency (0.1-1.0mhz) figure 6-137. atmel atmega48pa: active supply current vs. frequency (1-20mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.2 0.4 0.6 0.8 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 0 2 4 6 8 10 12 0 2 4 6 8 101214161820 frequency (mhz) i cc (ma) 1.8 v 2.7 v 3.3 v 4.0 v 352 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-138. atmel ? atmega48pa: active supply current vs. v cc (internal rc oscillator, 128khz) figure 6-139. atmel atmega48pa: active supply current vs. v cc (internal rc oscillator, 1mhz) 85 c 25 c -40 c 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 353 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-140. atmel ? atmega48pa: active supply current vs. v cc (internal rc oscillator, 8mhz) 6.29.1.2 idle supply current figure 6-141. atmel atmega48pa: idle supply current vs. low frequency (0.1-1.0mhz) 85 c 25 c -40 c 0 1 2 3 4 5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) i cc (ma) 354 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-142. atmel ? atmega48pa: idle supply current vs. frequency (1-20mhz) figure 6-143. atmel atmega48pa: idle supply current vs. v cc (internal rc oscillator, 128khz) 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 3 02468101214161820 frequency (mhz) i cc (ma) 1.8 v 2.7 v 3.3 v 4.0 v 85 c 25 c -40 c 0 0.007 0.014 0.021 0.028 0.035 0.042 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 355 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-144. atmel ? atmega48pa: idle supply current vs. v cc (internal rc oscillator, 1mhz) figure 6-145. atmel atmega48pa: idle supply current vs. vcc (i nternal rc oscillator, 8mhz) 85 c 25 c -40 c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 356 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.1.3 atmega48pa: supply current of io modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules are controlled by the power reduction register. see ?power reduction register? on page 67 for details. it is possible to calculate the typical current consumption based on the numbers from table 6-148 on page 356 for other v cc and frequency settings than listed in table 6-147 on page 356 . 6.29.1.4 example calculate the expected current consumption in idle mode with timer1, adc, and spi enabled at v cc = 2.0v and f = 1mhz. from table 6-148 on page 356 , third column, we see that we need to add 11.2% for the timer1, 22.1% for the adc, and 17.6% for the spi mod- ule. reading from figure 6-141 on page 353 , we find that the idle current consumption is ~0.028ma at v cc = 2.0v and f = 1mhz. the total current consumption in idle mode with timer1, adc, and spi enabled, gives: table 6-147. atmel ? atmega48pa: additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz prusart0 2.9ua 20.7ua 97.4ua prtwi 6.0ua 44.8ua 219.7ua prtim2 5.0ua 34.5ua 141.3ua prtim1 3.6ua 24.4ua 107.7ua prtim0 1.4ua 9.5ua 38.4ua prspi 5.0ua 38.0ua 190.4ua pradc 6.1ua 47.4ua 244.7ua table 6-148. atmel atmega48pa: additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 6-136 on page 351 and figure 6-137 on page 351 ) additional current consumption compared to idle with external clock (see figure 6-141 on page 353 and figure 6-142 on page 354 ) prusart0 1.8% 11.4% prtwi 3.9% 20.6% prtim2 2.9% 15.7% prtim1 2.1% 11.2% prtim0 0.8% 4.2% prspi 3.3% 17.6% pradc 4.2% 22.1% cc total 0.028 ma (1 + 0.112 + 0.221 + 0.176) ? 0.042 ma ? 357 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.1.5 power-down supply current figure 6-146. atmel ? atmega48pa: power-down supply current vs. v cc (watchdog timer disabled) figure 6-147. atmel atmega48pa: power-do wn supply current vs. v cc (watchdog timer enabled) 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 85 c 25 c -40 c 0 2 4 6 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 358 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.1.6 power-save supply current figure 6-148. atmel ? atmega48pa: power-save supply current vs. v cc (watchdog timer disabled and 32khz crystal oscillator running) 6.29.1.7 standby supply current figure 6-149. atmel atmega48pa: standby supply current vs. vcc (watchdog timer disabled) 85 c 25 c -40 c 0 0.4 0.8 1.2 1.6 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 6mhz_xtal 6mhz_res 4mhz_xtal 4mhz_res 450khz_res 2mhz_xtal 2mhz_res 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 1.522.533.544.555.5 v cc (v) i cc (ma) 359 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.1.8 pin pull-up figure 6-150. atmel ? atmega48pa: i/o pin pull-up resistor current vs. input voltage (v cc =1.8v) figure 6-151. atmel atmega48pa: i/o pin pull-up resistor current vs. input voltage (v cc = 2.7 v) 85 c 25 c -40 c 0 10 20 30 40 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 v op (v) i op (ua) 85 c 25 c -40 c 0 10 20 30 40 50 60 70 0 0.5 1 1.5 2 2.5 3 v op (v) i op (ua) 360 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-152. atmel ? atmega48pa: i/o pin pull-up resistor current vs. input voltage (v cc =5v) figure 6-153. atmel atmega48pa: reset pull-up resistor current vs. reset pin voltage (v cc =1.8v) 85 c 25 c -40 c 0 20 40 60 80 100 120 140 012345 v op (v) i op (ua) 85 c 25 c -40 c 0 5 10 15 20 25 30 35 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 v reset (v) i reset (ua) 361 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-154. atmel ? atmega48pa: reset pull-up resistor current vs. reset pin voltage (v cc =2.7v) figure 6-155. atmel atmega48pa: reset pull-up resist or current vs. reset pin voltage (v cc = 5v) 85 c 25 c -40 c 0 10 20 30 40 50 60 0 0.5 1 1.5 2 2.5 3 v reset (v) i reset (ua) 85 c 25 c -40 c 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v reset (v) i reset (ua) 362 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.1.9 pin driver strength figure 6-156. atmel ? atmega48pa: i/o pin output voltage vs. sink current(v cc = 3v) figure 6-157. atmel atmega48pa: i/o pin output voltage vs. sink current(v cc = 5v) 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 048121620 i ol (ma) v ol (v) 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0 4 8 121620 i ol (ma) v ol (v) 363 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-158. atmel ? atmega48pa: i/o pin output voltage vs. source current(v cc = 3v) figure 6-159. atmel atmega48pa: i/o pin output voltage vs. source current(v cc = 5v) 85 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 3.5 048121620 i oh (ma) v oh (v) 85 c 25 c -40 c 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5 0 4 8 12 16 20 i oh (ma) v oh (v) 364 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.1.10 pin threshold and hysteresis figure 6-160. atmel ? atmega48pa: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 6-161. atmel atmega48pa: i/o pin in put threshold voltage vs. v cc (v il , i/o pin read as ?0?) 85 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 85 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 365 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-162. atmel ? atmega48pa: i/o pin input hysteresis vs. v cc figure 6-163. atmel atmega48pa: reset input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) input hysteresis (mv) 85 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 366 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-164. atmel ? atmega48pa: reset input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 6-165. atmel atmega48pa: reset pin input hysteresis vs. v cc 85 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) input hysteresis (mv) 367 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.1.11 bod threshold figure 6-166. atmel ? atmega48pa: bod thresholds vs. temperature (bodlevel is 1.8v) figure 6-167. atmel atmega48pa: bod thresholds vs. temperature (bodlevel is 2.7v) rising vcc falling vcc 1.79 1.8 1.81 1.82 1.83 1.84 1.85 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature (c) threshold (v) rising vcc falling vcc 2.62 2.64 2.66 2.68 2.7 2.72 2.74 2.76 -50-40-30-20-10 0 102030405060708090 temperature (c) threshold (v) 368 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-168. atmel ? atmega48pa: bod thresholds vs. temperature (bodlevel is 4.3v) 6.29.1.12 internal oscilllator speed figure 6-169. atmel atmega48pa: watc hdog oscillator freque ncy vs. temperature rising vcc falling vcc 4.24 4.26 4.28 4.3 4.32 4.34 4.36 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature (c) threshold (v) 5.5 v 4.0 v 3.3 v 2.7 v 104 106 108 110 112 114 116 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature (c) f rc (khz) 369 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-170. atmel ? atmega48pa: watchdog os cillator frequency vs. v cc figure 6-171. atmel atmega48pa: calib rated 8 mhz rc oscilla tor frequency vs. v cc 85 c 25 c -40 c 106 108 110 112 114 116 118 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) f rc (khz) 85 c 25 c -40 c 7.6 7.7 7.8 7.9 8 8.1 8.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) f rc (mhz) 370 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-172. atmel ? atmega48pa: calibra ted 8mhz rc oscillator frequency vs. temperature figure 6-173. atmel atmega48pa: calibra ted 8 mhz rc oscillator frequency vs. osccal value 5.5 v 3.3 v 1.8 v 7.6 7.7 7.8 7.9 8 8.1 8.2 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature (c) f rc (mhz) 85 c 25 c -40 c 0 2 4 6 8 10 12 14 16 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 osccal (x1) f rc (mhz) 371 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.1.13 current consumption of peripheral units figure 6-174. atmel ? atmega48pa: adc current vs. v cc (aref = av cc ) figure 6-175. atmel atmega48pa: analog comparator current vs. v cc 85 c 25 c -40 c 0 50 100 150 200 250 300 350 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 85 c 25 c -40 c 0 10 20 30 40 50 60 70 80 90 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 372 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-176. atmel ? atmega48pa: aref external reference current vs. v cc figure 6-177. atmel atmega48pa: brownout detector current vs. v cc 85 c 25 c -40 c 0 20 40 60 80 100 120 140 160 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 85 c 25 c -40 c 0 8 16 24 32 40 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 373 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-178. atmel ? atmega48pa: programming current vs. v cc 6.29.1.14 current consumption in reset and re set pulsewidth figure 6-179. atmel atmega48pa: reset su pply current vs. low frequency (0.1 - 1.0mhz) 85 c 25 c -40 c 0 1 2 3 4 5 6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) i cc (ma) 374 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-180. atmel ? atmega48pa: reset supply current vs. frequency (1 - 20mhz) figure 6-181. atmel atmega48pa: minimum reset pulse width vs. v cc 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 0 2 4 6 8 10 12 14 16 18 20 frequency (mhz) i cc (ma) 1.8 v 2.7 v 3.3 v 4.0 v 85 c 25 c -40 c 0 200 400 600 800 1000 1200 1400 1600 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) pulsewidth (ns) 375 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.2 atmega88pa typical characteristics 6.29.2.1 active supply current figure 6-182. atmel ? atmega88pa: active supply current vs. low frequency (0.1 - 1.0mhz) figure 6-183. atmel atmega88pa: active supply current vs. frequency (1 - 20mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.2 0.4 0.6 0.8 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 0 2 4 6 8 10 12 0 2 4 6 8 10 12 14 16 18 20 frequency (mhz) i cc (ma) 1.8 v 2.7 v 3.3 v 4.0 v 376 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-184. atmel ? atmega88pa: active supply current vs. v cc (internal rc oscillator, 128khz) figure 6-185. atmel atmega88pa: active supply current vs. v cc (internal rc oscillator, 1mhz) 85 c 25 c -40 c 0 0.03 0.06 0.09 0.12 1.522.533.544.555.5 v cc (v) i cc (ma) 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 377 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-186. atmel ? atmega88pa: active supply current vs. v cc (internal rc oscillator, 8mhz) 6.29.2.2 idle supply current figure 6-187. atmel atmega88pa: idle supply current vs. low frequency (0.1 - 1.0mhz) 85 c 25 c -40 c 0 1 2 3 4 5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.03 0.06 0.09 0.12 0.15 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) i cc (ma) 378 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-188. atmel ? atmega88pa: idle supply current vs. frequency (1 - 20mhz) figure 6-189. atmel atmega88pa: idle supply current vs. v cc (internal rc oscillator, 128khz) 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 02468101214161820 frequency (mhz) i cc (ma) 4.0 v 3.3 v 2.7 v 1.8 v 85 c 25 c -40 c 0 0.01 0.02 0.03 0.04 1.522.533.544.555.5 v cc (v) i cc (ma) 379 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-190. atmel ? atmega88pa: idle supply current vs. v cc (internal rc oscillator, 1mhz) figure 6-191. atmel atmega88pa: idle supply current vs. vcc (i nternal rc oscillator, 8mhz) 85 c 25 c -40 c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 85 c 25 c -40 c 0 0.3 0.6 0.9 1.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 380 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.2.3 atmega88pa: supply current of io modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules are controlled by the power reduction register. see ?power reduction register? on page 67 for details. it is possible to calculate the typical current consumption based on the numbers from table 6-150 on page 380 for other v cc and frequency settings than listed in table 6-149 on page 380 . 6.29.2.4 example calculate the expected current consumption in idle mode with timer1, adc, and spi enabled at v cc = 2.0v and f = 1mhz. from table 6-150 on page 380 , third column, we see that we need to add 13.6% for the timer1, 26.3% for the adc, and 21.5% for the spi mod- ule. reading from figure 6-187 on page 377 , we find that the idle current consumption is ~0.027 ma at v cc = 2.0v and f = 1mhz. the total current consumption in idle mode with timer1, adc, and spi enabled, gives: table 6-149. atmega88pa: additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz prusart0 3.0ua 21.3ua 97.9ua prtwi 6.1ua 45.4ua 219.0ua prtim2 5.2ua 35.2ua 149.5ua prtim1 3.8ua 25.6ua 110.0ua prtim0 1.5ua 9.8ua 39.6ua prspi 5.2ua 40.0ua 199.6ua pradc 6.3ua 48.7ua 247.0ua table 6-150. atmega88pa: additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 6-182 on page 375 and figure 6-183 on page 375 ) additional current consumption compared to idle with external clock (see figure 6-187 on page 377 and figure 6-188 on page 378 ) prusart0 1.8% 11.4% prtwi 3.9% 24.4% prtim2 2.9% 18.6% prtim1 2.1% 13.6% prtim0 0.8% 5.2% prspi 3.5% 21.5% pradc 4.2% 26.3% i cc total 0.027 ma (1 + 0.136 + 0.263 + 0.215) ? 0.043 ma ? 381 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.2.5 power-down supply current figure 6-192. atmel ? atmega88pa: power-down supply current vs. v cc (watchdog timer disabled) figure 6-193. atmel atmega88pa: power-do wn supply current vs. v cc (watchdog timer enabled) 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 85 c 25 c -40 c 0 2 4 6 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 382 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.2.6 power-save supply current figure 6-194. atmel ? atmega88pa: power-save supply current vs. v cc (watchdog timer disabled and 32khz crystal oscillator running) 6.29.2.7 standby supply current figure 6-195. atmel atmega88pa: standby supply current vs. vcc (watchdog timer disabled) watchdog timer di s abled a nd 3 2 khz cry s tal o s cillator running 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) 8 5 c 25 c -40 c 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 6mhz_xtal 6mhz_res 4mhz_xtal 4mhz_res 450khz_res 2mhz_xtal 2mhz_res 383 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.2.8 pin pull-up figure 6-196. atmel ? atmega88pa: i/o pin pull-up resistor current vs. input voltage (v cc =1.8v) figure 6-197. atmel atmega88pa: i/o pin pull-up resistor current vs. input voltage (v cc =2.7v) 85 c 25 c -40 c 0 10 20 30 40 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 v op (v) i op (ua) 85 c 25 c -40 c 0 10 20 30 40 50 60 70 80 0 0.5 1 1.5 2 2.5 3 v op (v) i op (ua) 384 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-198. atmel ? atmega88pa: i/o pin pull-up resistor current vs. input voltage (v cc =5v) figure 6-199. atmel atmega88pa: reset pull-up resistor current vs. reset pin voltage (v cc =1.8v) 85 c 25 c -40 c 0 20 40 60 80 100 120 140 012345 v op (v) i op (ua) 85 c 25 c -40 c 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 v reset (v) i reset (ua) 385 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-200. atmel ? atmega88pa: reset pull-up resistor current vs. reset pin voltage (v cc =2.7v) figure 6-201. atmel atmega88pa: reset pull-up resist or current vs. reset pin voltage (v cc =5v) 85 c 0 10 20 30 40 50 60 0 0.5 1 1.5 2 2.5 3 v reset (v) i reset (ua) -40 c 25 c 85 c -40 c 25 c 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v reset (v) i reset (ua) 386 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.2.9 pin driver strength figure 6-202. atmel ? atmega88pa: i/o pin output voltage vs. sink current (v cc =3v) figure 6-203. atmel atmega88pa: i/o pin output voltage vs. sink current (v cc = 5v) 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 048121620 i ol (ma) v ol (v) 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0 4 8 121620 i ol (ma) v ol (v) 387 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-204. atmel ? atmega88pa: i/o pin output voltage vs. source current (v cc =3v) figure 6-205. atmel atmega88pa: i/o pin output voltage vs. source current (v cc =5v) 85 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 3.5 0 4 8 12 16 20 i oh (ma) v oh (v) 85 c 25 c -40 c 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5 048121620 i oh (ma) v oh (v) 388 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.2.10 pin threshold and hysteresis figure 6-206. atmel ? atmega88pa: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 6-207. atmel atmega88pa: i/o pin in put threshold voltage vs. v cc (v il , i/o pin read as ?0?) 85 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 85 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 389 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-208. atmel ? atmega88pa: i/o pin input hysteresis vs. v cc figure 6-209. atmel atmega88pa: reset input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) input hysteresis (mv) 85 c 25 c -40 c 0 0.3 0.6 0.9 1.2 1.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 390 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-210. atmel ? atmega88pa: reset input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 6-211. atmel atmega88pa: reset pin input hysteresis vs. v cc 85 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) input hysteresis (mv) 391 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.2.11 bod threshold figure 6-212. atmel ? atmega88pa: bod thresholds vs. temperature (bodlevel is 1.8v) figure 6-213. atmel atmega88pa: bod thresholds vs. temperature (bodlevel is 2.7v) rising vcc falling vcc 1.77 1.78 1.79 1.8 1.81 1.82 1.83 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature (c) threshold (v) rising vcc falling vcc 2.64 2.66 2.68 2.7 2.72 2.74 2.76 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature (c) threshold (v) 392 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-214. atmel ? atmega88pa: bod thresholds vs. temperature (bodlevel is 4.3v) 6.29.2.12 internal oscilllator speed figure 6-215. atmel atmega88pa: watc hdog oscillator freque ncy vs. temperature rising vcc falling vcc 4.22 4.24 4.26 4.28 4.3 4.32 4.34 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature (c) threshold (v) 5.5 v 4.0 v 3.3 v 2.7 v 105 106 107 108 109 110 111 112 113 114 -40 -20 0 20 40 60 80 100 temperature (c) f rc (khz) 393 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-216. atmel ? atmega88pa: watchdog os cillator frequency vs. v cc figure 6-217. atmel atmega88pa: calib rated 8 mhz rc oscilla tor frequency vs. v cc 85 c 25 c -40 c 104 106 108 110 112 114 116 1.522.533.544.555.5 v cc (v) f rc (khz) 85 c 25 c -40 c 7.6 7.7 7.8 7.9 8 8.1 8.2 8.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) f rc (mhz) 394 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-218. atmel ? atmega88pa: calibra ted 8mhz rc oscillator frequency vs. temperature figure 6-219. atmel atmega88pa: calibra ted 8mhz rc oscillator frequency vs. osccal value 5.5 v 4.0 v 3.0 v 7.8 7.9 8 8.1 8.2 8.3 -40 -20 0 20 40 60 80 100 temperature (c) f rc (mhz) 85 c 25 c -40 c 0 2 4 6 8 10 12 14 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 osccal (x1) f rc (mhz) 395 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.2.13 current consumption of peripheral units figure 6-220. atmel ? atmega88pa: adc current vs. v cc (aref = av cc ) figure 6-221. atmel atmega88pa: analog comparator current vs. v cc 85 c 25 c -40 c 0 50 100 150 200 250 300 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 85 c 25 c -40 c 0 10 20 30 40 50 60 70 80 90 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 396 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-222. atmel ? atmega88pa: aref external reference current vs. v cc figure 6-223. atmel atmega88pa: brownout detector current vs. v cc 85 c 25 c -40 c 0 20 40 60 80 100 120 140 160 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 85 c 25 c -40 c 0 10 20 30 40 50 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 397 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-224. atmel ? atmega88pa: programming current vs. v cc 6.29.2.14 current consumption in reset and re set pulsewidth figure 6-225. atmel atmega88pa: reset su pply current vs. low frequency (0.1 - 1.0mhz) 85 c 25 c -40 c 0 1 2 3 4 5 6 7 8 1.522.533.544.555.5 v cc (v) i cc (ma) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.02 0.04 0.06 0.08 0.1 0.12 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) i cc (ma) 398 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-226. atmel ? atmega88pa: reset supply current vs. frequency (1 - 20mhz) figure 6-227. atmel atmega88pa: minimum reset pulse width vs. v cc 5.5 v 5.0 v 4.5 v 0 0.4 0.8 1.2 1.6 2 02468101214161820 frequency (mhz) i cc (ma) 1.8 v 2.7 v 4.0 v 3.3 v 85 c 25 c -40 c 0 200 400 600 800 1000 1200 1400 1600 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) pulsewidth (ns) 399 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.3 atmega168pa typical characteristics 6.29.3.1 active supply current figure 6-228. atmel ? atmega168pa: active supply current vs. low frequency (0.1-1.0mhz) figure 6-229. atmel atmega168pa: active supply current vs. frequency (1-20mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.2 0.4 0.6 0.8 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 0 2 4 6 8 10 12 0 2 4 6 8 10 12 14 16 18 20 frequency (mhz) i cc (ma) 1.8 v 4.0 v 3.3 v 2.7 v 400 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-230. atmel ? atmega168pa: active supply current vs. v cc (internal rc oscillator, 128khz) figure 6-231. atmel atmega168pa: active supply current vs. v cc (internal rc oscillator, 1mhz) 85 c 25 c -40 c 0 0.03 0.06 0.09 0.12 0.15 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 401 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-232. atmel ? atmega168pa: active supply current vs. v cc (internal rc oscillator, 8mhz) 6.29.3.2 idle supply current figure 6-233. atmel atmega168pa: idle supply current vs. low frequency (0.1 - 1.0mhz) 25 c -40 c 0 1 2 3 4 5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 85 c 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.03 0.06 0.09 0.12 0.15 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) i cc (ma) 402 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-234. atmel ? atmega168pa: idle supply current vs. frequency (1 - 20mhz) figure 6-235. atmel ? atmega168pa: dle supply current vs. v cc (internal rc oscillator, 128khz) 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 3 02468101214161820 frequency (mhz) i cc (ma) 1.8 v 2.7 v 4.0 v 3.3 v 85 c 25 c -40 c 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 403 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-236. atmel ? atmega168pa: idle supply current vs. v cc (internal rc oscillator, 1mhz) figure 6-237. atmel atmega168pa: idle s upply current vs. vcc (internal rc oscillator, 8mhz) 85 c 25 c -40 c 0 0.05 0.1 0.15 0.2 0.25 0.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 85 c 25 c -40 c 0 0.3 0.6 0.9 1.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 404 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.3.3 atmega168pa supply current of io modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules are controlled by the power reduction register. see ?power reduction register? on page 67 for details. it is possible to calculate the typical current consumption based on the numbers from table 6-152 on page 404 for other v cc and frequency settings than listed in table 6-151 on page 404 . 6.29.3.4 example calculate the expected current consumption in idle mode with timer1, adc, and spi enabled at v cc = 2.0v and f = 1mhz. from table 6-152 on page 404 , third column, we see that we need to add 10.3% for the timer1, 20.3% for the adc, and 17.1% for the spi mod- ule. reading from figure 6-233 on page 401 , we find that the idle current consumption is ~0.027 ma at v cc = 2.0v and f = 1mhz. the total current consumption in idle mode with timer1, adc, and spi enabled, gives: table 6-151. atmel ? atmega168pa: additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz prusart0 2.86ua 20.3ua 52.2ua prtwi 6.00ua 44.1ua 122.0ua prtim2 4.97ua 33.2ua 79.8ua prtim1 3.50ua 23.0ua 55.3ua prtim0 1.43ua 9.2ua 21.4ua prspi 5.01ua 38.6ua 111.4ua pradc 6.34ua 45.7ua 123.6ua table 6-152. atmel atmega168pa: additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 6-228 on page 399 and figure 6-229 on page 399 ) additional current consumption compared to idle with external clock (see figure 6-233 on page 401 and figure 6-234 on page 402 ) prusart0 1.5% 8.9% prtwi 3.2% 19.5% prtim2 2.4% 14.8% prtim1 1.7% 10.3% prtim0 0.7% 4.1% prspi 2.9% 17.1% pradc 3.4% 20.3% i cc total 0.027ma (1 + 0.103 + 0.203 + 0.171) ? 0.040ma ? 405 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.3.5 power-down supply current figure 6-238. atmel ? atmega168pa: power-down supply current vs. v cc (watchdog timer disabled) figure 6-239. atmel atmega168pa: power-do wn supply current vs. v cc (watchdog timer enabled) 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 85 c 25 c -40 c 0 2 4 6 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 406 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.3.6 power-save supply current figure 6-240. atmel ? atmega168pa: power-save supply current vs. v cc (watchdog timer disabled and 32khz crystal oscillator running) 6.29.3.7 standby supply current figure 6-241. atmel atmega168pa: standby supply current vs. vcc (watchdog timer disabled) 85 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 6mhz_xtal 6mhz_res 4mhz_xtal 4mhz_res 450khz_res 2mhz_xtal 2mhz_res 1mhz_res 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (mhz) i cc (ma) 407 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.3.8 pin pull-up figure 6-242. atmel ? atmega168pa: i/o pin pull-up resistor current vs. input voltage (v cc =1.8v) figure 6-243. atmel atmega168pa: i/o pin pull-up resistor current vs. input voltage (v cc =2.7v) 85 c 25 c -40 c 0 10 20 30 40 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 v op (v) i op (ua) 85 c 25 c -40 c 0 10 20 30 40 50 60 70 80 0 0.5 1 1.5 2 2.5 3 v op (v) i op (ua) 408 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-244. atmel ? atmega168pa: i/o pin pull-up resistor current vs. input voltage (v cc =5v) figure 6-245. atmel atmega168pa: reset pull-up resistor current vs. reset pin voltage (v cc =1.8v) 85 c 25 c -40 c 0 20 40 60 80 100 120 140 160 0123456 v op (v) i op (ua) 85 c 25 c -40 c 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 v reset (v) i reset (ua) 409 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-246. atmel ? atmega168pa: reset pull-up resistor current vs. reset pin voltage (v cc =2.7v) figure 6-247. atmel atmega168pa: reset pull-up resistor current vs. reset pin voltage (v cc =5v) 85 c 0 10 20 30 40 50 60 0 0.5 1 1.5 2 2.5 3 v reset (v) i reset (ua) -40 c 25 c 0 20 40 60 80 100 120 012345 v reset (v) i reset (ua) 85 c -40 c 25 c 410 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.3.9 pin driver strength figure 6-248. atmel ? atmega168pa: i/o pin output voltage vs. sink current(v cc = 3v) figure 6-249. atmel atmega168pa: i/o pin output voltage vs. sink current(v cc = 5v) 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 0 4 8 12 16 20 i ol (ma) v ol (v) 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0 4 8 12 16 20 i ol (ma) v ol (v) 411 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-250. atmel ? atmega168pa: i/o pin output voltage vs. source current(v cc = 3v) figure 6-251. atmel atmega168pa: i/o pin output voltage vs. source current(v cc = 5v) 85 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 3.5 048121620 i oh (ma) v oh (v) 85 c 25 c -40 c 4 4.2 4.4 4.6 4.8 5 048121620 i oh (ma) v oh (v) 412 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.3.10 pin threshold and hysteresis figure 6-252. atmel ? atmega168pa: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 6-253. atmel atmega168pa: i/o pin in put threshold voltage vs. v cc (v il , i/o pin read as ?0?) 85 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 85 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 413 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-254. atmel ? atmega168pa: i/o pin input hysteresis vs. v cc figure 6-255. atmel atmega168pa: reset input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) input hysteresis (mv) 85 c 25 c -40 c 0 0.3 0.6 0.9 1.2 1.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 414 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-256. atmel ? atmega168pa: reset input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 6-257. atmel atmega168pa: reset pin input hysteresis vs. v cc 85 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) input hysteresis (mv) 415 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.3.11 bod threshold figure 6-258. atmel ? atmega168pa: bod thresholds vs. temperature (bodlevel is 1.8v) figure 6-259. atmel atmega168pa: bod thresholds vs. temperature (bodlevel is 2.7v) rising vcc falling vcc 1.72 1.74 1.76 1.78 1.8 1.82 1.84 1.86 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature (c) threshold (v) rising vcc falling vcc 2.62 2.64 2.66 2.68 2.7 2.72 2.74 2.76 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature ( c) threshold (v) 416 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-260. atmel ? atmega168pa: bod thresholds vs. temperature (bodlevel is 4.3v) 6.29.3.12 internal oscilllator speed figure 6-261. atmel atmega168pa: watc hdog oscillato r frequency vs . temperature rising vcc falling vcc 4.2 4.22 4.24 4.26 4.28 4.3 4.32 4.34 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature (c) threshold (v) 5.5 v 3.3 v 2.7 v 111 113 115 117 119 121 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 temperature (c) f rc (khz) 417 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-262. atmel ? atmega168pa: watchdog os cillator frequency vs. v cc figure 6-263. atmel atmega168pa: calibrated 8mhz rc oscillator frequency vs. v cc 85 c 25 c -40 c 110 112 114 116 118 120 122 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) f rc (khz) 85 c 25 c -40 c 7.4 7.6 7.8 8 8.2 8,4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) f rc (mhz) 418 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-264. atmel ? atmega168pa: calibrated 8mhz rc oscillator frequency vs. temperature figure 6-265. atmel atmega168pa: calibra ted 8mhz rc oscillator frequency vs. osccal value 5.5 v 5.0 v 2.7 v 1.8 v 7.5 7.6 7.7 7.8 7.9 8 8.1 8.2 8.3 -50-40-30-20-10 0 102030405060708090 temperature (c) f rc (mhz) 85 c 25 c -40 c 0 2 4 6 8 10 12 14 16 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 osccal (x1) f rc (mhz) 419 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.3.13 current consumption of peripheral units figure 6-266. atmel ? atmega168pa: adc current vs. v cc (aref = av cc ) figure 6-267. atmel atmega168pa: analog comparator current vs. v cc 85 c 25 c -40 c 100 150 200 250 300 350 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 85 c 25 c -40 c 30 40 50 60 70 80 90 1.522.533.544.555.5 v cc (v) i cc (ua) 420 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-268. atmel ? atmega168pa: aref external reference current vs. v cc figure 6-269. atmel atmega168pa: brownout detector current vs. v cc 85 c 25 c -40 c 0 20 40 60 80 100 120 140 160 180 1.522.533.544.555.5 v cc (v) i cc (ua) 85 c 25 c -40 c 12 14 16 18 20 22 24 26 1.522.533.544.555.5 v cc (v) i cc (ua) 421 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-270. atmel ? atmega168pa: programming current vs. v cc 6.29.3.14 current consumption in reset and re set pulsewidth figure 6-271. atmel atmega168pa: reset supply current vs. low frequency (0.1 - 1.0mhz) 85 c 25 c -40 c 0 2 4 6 8 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.02 0.04 0.06 0.08 0.1 0.12 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) i cc (ma) 422 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-272. atmel ? atmega168pa: reset supply current vs. frequency (1 - 20mhz) figure 6-273. atmel atmega168pa: minimum reset pulse width vs. v cc 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 02468101214161820 frequency (mhz) i cc (ma) 1.8 v 2.7 v 3.3 v 4.0 v 85 c 25 c -40 c 0 250 500 750 1000 1250 1500 1750 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) pulsewidth (ns) 423 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.4 atmega328p typical characteristics 6.29.4.1 active supply current figure 6-274. atmel ? atmega328p: active supply current vs. low frequency (0.1 - 1.0mhz) figure 6-275. atmel atmega328p: active supply current vs. frequency (1 - 20mhz) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.2 0.4 0.6 0.8 1 1.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 0 2 4 6 8 10 12 14 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v 2.7 v 3 . 3 v 4.0 v 424 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-276. atmel ? atmega328p: active supply current vs. v cc (internal rc oscillator, 128khz) figure 6-277. atmel atmega328p: active supply current vs. v cc (internal rc oscillator, 1mhz) 85 c 25 c -40 c 0 0.04 0.08 0.12 0.16 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 425 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-278. atmel ? atmega328p: active supply current vs. v cc (internal rc oscillator, 8mhz) 6.29.4.2 idle supply current figure 6-279. atmel atmega328p: idle supply current vs. low frequency (0.1 - 1.0mhz) 85 c 25 c -40 c 0 1 2 3 4 5 6 7 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.04 0.08 0.12 0.16 0.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) i cc (ma) 426 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-280. atmel ? atmega328p: idle supply current vs. frequency (1 - 20mhz) figure 6-281. atmel atmega328p: idle supply current vs. v cc (internal rc oscillator, 128khz) 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 3 3.5 4 0 2 4 6 8 10 12 14 16 18 20 frequency (mhz) i cc (ma) 1.8 v 2.7 v 3.3 v 4.0 v , 85 c 25 c -40 c 0 0.01 0.02 0.03 0.04 0.05 0.06 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 427 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-282. atmel ? atmega328p: idle supply current vs. v cc (internal rc oscillator, 1mhz) figure 6-283. atmel atmega328p: idle supp ly current vs. vcc (inter nal rc oscillator, 8mhz) 85 c 25 c -40 c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 8 5 c 25 c -40 c 0 0.4 0. 8 1.2 1.6 2 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 428 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.4.3 atmega328p supply current of io modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules are controlled by the power reduction register. see ?power reduction register? on page 67 for details. it is possible to calculate the typical current consumption based on the numbers from table 6-154 on page 428 for other v cc and frequency settings than listed in table 6-153 on page 428 . 6.29.4.4 example calculate the expected current consumption in idle mode with timer1, adc, and spi enabled at v cc = 2.0v and f = 1mhz. from table 6-154 on page 428 , third column, we see that we need to add 14.5% for the timer1, 22.1% for the adc, and 15.7% for the spi mod- ule. reading from figure 6-280 on page 426 , we find that the idle current consumption is ~0.055ma at v cc = 2.0v and f = 1mhz. the total current consumption in idle mode with timer1, adc, and spi enabled, gives: table 6-153. atmel ? atmega328p: additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz prusart0 3.20a 22.17a 100.25a prtwi 7.34a 46.55a 199.25a prtim2 7.34a 50.79a 224.25a prtim1 6.19a 41.25a 176.25a prtim0 1.89a 14.28a 61.13a prspi 6.94a 43.84a 186.50a pradc 8.66a 61.80a 295.38a table 6-154. atmega328p: additional current consumption (percentage) in active and idle mode prr bit additional current consumption compared to active with external clock (see figure 6-274 on page 423 and figure 6-275 on page 423 ) additional current consumption compared to idle with external clock (see figure 6-279 on page 425 and figure 6-280 on page 426 ) prusart0 1.4 % 7.8% prtwi 3.0 % 16.6 % prtim2 3.3 % 17.8 % prtim1 2.7 % 14.5 % prtim0 0.9 % 4.8 % prspi 2.9 % 15.7 % pradc 4.1 % 22.1 % i cc total 0.045ma (1 + 0.145 + 0.221 + 0.157) ? 0.069ma ? 429 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.4.5 power-down supply current figure 6-284. atmega328p: power-down supply current vs. v cc (watchdog timer disabled) figure 6-285. atmega328p: power-down supply current vs. v cc (watchdog timer enabled) 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 85 c 25 c -40 c 0 1 2 3 4 5 6 7 8 9 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 430 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.4.6 power-save supply current figure 6-286. atmel ? atmega328p: power-save supply current vs. v cc (watchdog timer disabled and 32khz crystal oscillator running) 6.29.4.7 standby supply current figure 6-287. atmel atmega328p: standby supply current vs. vcc (watchdog timer disabled) 25 c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 6mhz_xtal 6mhz_res 4mhz_xtal 4mhz_res 2mhz_xtal 2mhz_res 1mhz_res 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 431 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.4.8 pin pull-up figure 6-288. atmel ? atmega328p: i/o pin pull-up resistor current vs. input voltage (v cc =1.8v) figure 6-289. atmel atmega328p: i/o pin pull-up resistor current vs. input voltage (v cc =2.7v) 85 c 25 c -40 c 0 10 20 30 40 50 60 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 v op (v) i op (ua) 85 c 25 c -40 c 0 10 20 30 40 50 60 70 80 90 0 0.5 1 1.5 2 2.5 3 v op (v) i op (ua) 432 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-290. atmel ? atmega328p: i/o pin pull-up resistor current vs. input voltage (v cc =5v) figure 6-291. atmel atmega328p: reset pull-up resistor current vs. reset pin voltage (v cc =1.8v) 0 20 40 60 80 100 120 140 160 0123456 v op (v) i op (ua) 85 c 25 c -40 c 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 v reset (v) i reset (ua) 85 c 25 c -40 c 433 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-292. atmel ? atmega328p: reset pull-up resistor current vs. reset pin voltage (v cc =2.7v) figure 6-293. atmel atmega328p: reset pull-up resistor current vs. reset pin voltage (v cc =5v) 0 10 20 30 40 50 60 70 0 0.5 1 1.5 2 2.5 3 v reset (v) i reset (ua) 85 c 25 c -40 c 0 20 40 60 8 0 100 120 012 3 456 v re s et (v) i re s et ( u a) 8 5 c 25 c -40 c 434 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.4.9 pin driver strength figure 6-294. atmel ? atmega328p: i/o pin output voltage vs. sink current (v cc = 3v) figure 6-295. atmel atmega328p: i/o pin output voltage vs. sink current (v cc = 5v) 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 0 5 10 15 20 25 i ol (ma) v ol (v) 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0 5 10 15 20 25 i ol (ma) v ol (v) 435 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-296. atmel ? atmega328p: i/o pin output voltage vs. source current (v cc = 3v) figure 6-297. atmel atmega328p: i/o pin output voltage vs. source current(v cc = 5v) 85 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 3.5 0 5 10 15 20 25 i oh (ma) v oh (v) 85 c 25 c -40 c 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5 5.1 0 5 10 15 20 25 i oh (ma) v oh (v) 436 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.4.10 pin threshold and hysteresis figure 6-298. atmel ? atmega328p: i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 6-299. atmel atmega328p: i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0?) , 85 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 3.5 4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 85 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 437 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-300. atmel ? atmega328p: i/o pin input hysteresis vs. v cc figure 6-301. atmel atmega328p: reset input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) input hysteresis (mv) 85 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 438 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-302. atmel ? atmega328p: reset input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 6-303. atmel atmega328p: reset pin input hysteresis vs. v cc 85 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (mv) 439 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.4.11 bod threshold figure 6-304. atmel ? atmega328p: bod thresholds vs. temperature (bodlevel is 1.8v) figure 6-305. atmel atmega328p: bod thresholds vs. temperature (bod level is 2.7v) 1 0 1.75 1.77 1.79 1.81 1.83 1.85 -60 -40 -20 0 20 40 60 80 100 temperature (c) threshold (v) 1 0 2.66 2.68 2.7 2.72 2.74 2.76 2.78 -60 -40 -20 0 20 40 60 80 100 temperature (c) threshold (v) 440 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-306. atmel ? atmega328p: bod thresholds vs. temperature (bodlevel is 4.3v) 6.29.4.12 internal oscilllator speed figure 6-307. atmel atmega328p: watchdog oscilla tor frequency vs . temperature 1 0 4.25 4.3 4.35 4.4 -60 -40 -20 0 20 40 60 80 100 temperature (c) threshold (v) 5.5 v 4.0 v 3.3 v 2.7 v 109 110 111 112 113 114 115 116 117 118 119 -60 -40 -20 0 20 40 60 80 100 temperature (c) f rc (khz) 441 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-308. atmel ? atmega328p: watchdog oscillator frequency vs. v cc figure 6-309. atmel atmega328p: calibrated 8mhz rc oscillator frequency vs. v cc 85 c 25 c -40 c 1.5 2 2.5 3 3.5 4 4.5 5 5.5 (v) f rc (khz) 108 110 112 114 116 118 120 v cc 8 5 c 25 c -40 c 7.4 7.6 7. 8 8 8 .2 8 .4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) f rc (mhz) 442 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-310. atmel ? atmega328p: calibrated 8mhz rc oscillator frequency vs. temperature figure 6-311. atmel atmega328p: calibrated 8mhz rc oscillator frequency vs. osccal value 5.0 v 3.0 v 7.6 7.7 7.8 7.9 8 8.1 8.2 8.3 8.4 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 temperature (c) f rc (mhz) 8 5 c 25 c -40 c 0 2 4 6 8 10 12 14 16 016 3 24 8 64 8 0 96 112 12 8 144 160 176 192 20 8 224 240 256 o s ccal (x1) f rc (mhz) 443 9159a?auto?09/10 atmel ata6614 [preliminary] 6.29.4.13 current consumption of peripheral units figure 6-312. atmel ? atmega328p: adc current vs. v cc (aref = av cc ) figure 6-313. atmel atmega328p: analog comparator current vs. v cc 85 c 25 c -40 c 0 50 100 150 200 250 300 350 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 8 5 c 25 c -40 c 0 20 40 60 8 0 100 120 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) 444 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-314. atmel ? atmega328p: aref external reference current vs. v cc figure 6-315. atmel atmega328p: brownout detector current vs. v cc 8 5 c 25 c -40 c 0 20 40 60 8 0 100 120 140 160 1 8 0 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) 8 5 c 25 c -40 c 0 5 10 15 20 25 3 0 1.5 2 2.5 33 .544.555.5 v cc (v) i cc ( u a) 445 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-316. atmel ? atmega328p: programming current vs. v cc 6.29.4.14 current consumption in reset and re set pulsewidth figure 6-317. atmel atmega328p: reset supply current vs. low frequency (0.1 - 1.0mhz) 8 5 c 25 c -40 c 0 1 2 3 4 5 6 7 8 9 10 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.05 0.1 0.15 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) i cc (ma) 446 9159a?auto?09/10 atmel ata6614 [preliminary] figure 6-318. atmel ? atmega328p: reset supply current vs. frequency (1 - 20mhz) figure 6-319. atmel atmega328p: minimum reset pulse width vs. v cc 5.5 v 5.0 v 4.5 v 0 0.5 1 1.5 2 2.5 3 0 2 4 6 8 10 12 14 16 18 20 frequency (mhz) i cc (ma) 1.8 v 2.7 v 3.3 v 4.0 v 8 5 c 25 c -40 c 0 200 400 600 8 00 1000 1200 1400 1600 1 8 00 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) p u l s ewidth (n s ) 447 9159a?auto?09/10 atmel ata6614 [preliminary] 6.30 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved ? ? ? ? ? ? ? ? (0xfe) reserved ? ? ? ? ? ? ? ? (0xfd) reserved ? ? ? ? ? ? ? ? (0xfc) reserved ? ? ? ? ? ? ? ? (0xfb) reserved ? ? ? ? ? ? ? ? (0xfa) reserved ? ? ? ? ? ? ? ? (0xf9) reserved ? ? ? ? ? ? ? ? (0xf8) reserved ? ? ? ? ? ? ? ? (0xf7) reserved ? ? ? ? ? ? ? ? (0xf6) reserved ? ? ? ? ? ? ? ? (0xf5) reserved ? ? ? ? ? ? ? ? (0xf4) reserved ? ? ? ? ? ? ? ? (0xf3) reserved ? ? ? ? ? ? ? ? (0xf2) reserved ? ? ? ? ? ? ? ? (0xf1) reserved ? ? ? ? ? ? ? ? (0xf0) reserved ? ? ? ? ? ? ? ? (0xef) reserved ? ? ? ? ? ? ? ? (0xee) reserved ? ? ? ? ? ? ? ? (0xed) reserved ? ? ? ? ? ? ? ? (0xec) reserved ? ? ? ? ? ? ? ? (0xeb) reserved ? ? ? ? ? ? ? ? (0xea) reserved ? ? ? ? ? ? ? ? (0xe9) reserved ? ? ? ? ? ? ? ? (0xe8) reserved ? ? ? ? ? ? ? ? (0xe7) reserved ? ? ? ? ? ? ? ? (0xe6) reserved ? ? ? ? ? ? ? ? (0xe5) reserved ? ? ? ? ? ? ? ? (0xe4) reserved ? ? ? ? ? ? ? ? (0xe3) reserved ? ? ? ? ? ? ? ? (0xe2) reserved ? ? ? ? ? ? ? ? (0xe1) reserved ? ? ? ? ? ? ? ? (0xe0) reserved ? ? ? ? ? ? ? ? (0xdf) reserved ? ? ? ? ? ? ? ? (0xde) reserved ? ? ? ? ? ? ? ? (0xdd) reserved ? ? ? ? ? ? ? ? (0xdc) reserved ? ? ? ? ? ? ? ? (0xdb) reserved ? ? ? ? ? ? ? ? (0xda) reserved ? ? ? ? ? ? ? ? (0xd9) reserved ? ? ? ? ? ? ? ? (0xd8) reserved ? ? ? ? ? ? ? ? (0xd7) reserved ? ? ? ? ? ? ? ? (0xd6) reserved ? ? ? ? ? ? ? ? (0xd5) reserved ? ? ? ? ? ? ? ? (0xd4) reserved ? ? ? ? ? ? ? ? (0xd3) reserved ? ? ? ? ? ? ? ? (0xd2) reserved ? ? ? ? ? ? ? ? (0xd1) reserved ? ? ? ? ? ? ? ? (0xd0) reserved ? ? ? ? ? ? ? ? (0xcf) reserved ? ? ? ? ? ? ? ? (0xce) reserved ? ? ? ? ? ? ? ? (0xcd) reserved ? ? ? ? ? ? ? ? (0xcc) reserved ? ? ? ? ? ? ? ? (0xcb) reserved ? ? ? ? ? ? ? ? (0xca) reserved ? ? ? ? ? ? ? ? (0xc9) reserved ? ? ? ? ? ? ? ? (0xc8) reserved ? ? ? ? ? ? ? ? (0xc7) reserved ? ? ? ? ? ? ? ? (0xc6) udr0 usart i/o data register 220 (0xc5) ubrr0h usart baud rate register high 224 (0xc4) ubrr0l usart baud rate register low 224 (0xc3) reserved ? ? ? ? ? ? ? ? (0xc2) ucsr0c umsel01 umsel00 upm01 upm00 usbs0 ucsz01 /udord0 ucsz00 / ucpha0 ucpol0 222/237 (0xc1) ucsr0b rxcie0 txcie0 udrie0 rxen0 txen0 ucsz02 rxb80 txb80 221 (0xc0) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 220 448 9159a?auto?09/10 atmel ata6614 [preliminary] (0xbf) reserved ? ? ? ? ? ? ? ? (0xbe) reserved ? ? ? ? ? ? ? ? (0xbd) twamr twam6 twam5 twam4 twam3 twam2 twam1 twam0 ?269 (0xbc) twcr twint twea twsta twsto twwc twen ?twie 266 (0xbb) twdr 2-wire serial interface data register 268 (0xba) twar twa6 twa5 twa4 tw a3 twa2 twa1 twa0 twgce 269 (0xb9) twsr tws7 tws6 tws5 tws4 tws3 ?twps1twps0 268 (0xb8) twbr 2-wire serial interface bit rate register 266 (0xb7) reserved ? ? ? ? ? ? ? (0xb6) assr ? exclk as2 tcn2ub ocr2aub ocr2bub tcr2aub tcr2bub 190 (0xb5) reserved ? ? ? ? ? ? ? ? (0xb4) ocr2b timer/counter2 output compare register b 189 (0xb3) ocr2a timer/counter2 output compare register a 189 (0xb2) tcnt2 timer/counter2 (8-bit) 188 (0xb1) tccr2b foc2a foc2b ? ? wgm22 cs22 cs21 cs20 187 (0xb0) tccr2a com2a1 com2a0 com2b1 com2b0 ? ?wgm21wgm20 184 (0xaf) reserved ? ? ? ? ? ? ? ? (0xae) reserved ? ? ? ? ? ? ? ? (0xad) reserved ? ? ? ? ? ? ? ? (0xac) reserved ? ? ? ? ? ? ? ? (0xab) reserved ? ? ? ? ? ? ? ? (0xaa) reserved ? ? ? ? ? ? ? ? (0xa9) reserved ? ? ? ? ? ? ? ? (0xa8) reserved ? ? ? ? ? ? ? ? (0xa7) reserved ? ? ? ? ? ? ? ? (0xa6) reserved ? ? ? ? ? ? ? ? (0xa5) reserved ? ? ? ? ? ? ? ? (0xa4) reserved ? ? ? ? ? ? ? ? (0xa3) reserved ? ? ? ? ? ? ? ? (0xa2) reserved ? ? ? ? ? ? ? ? (0xa1) reserved ? ? ? ? ? ? ? ? (0xa0) reserved ? ? ? ? ? ? ? ? (0x9f) reserved ? ? ? ? ? ? ? ? (0x9e) reserved ? ? ? ? ? ? ? ? (0x9d) reserved ? ? ? ? ? ? ? ? (0x9c) reserved ? ? ? ? ? ? ? ? (0x9b) reserved ? ? ? ? ? ? ? ? (0x9a) reserved ? ? ? ? ? ? ? ? (0x99) reserved ? ? ? ? ? ? ? ? (0x98) reserved ? ? ? ? ? ? ? ? (0x97) reserved ? ? ? ? ? ? ? ? (0x96) reserved ? ? ? ? ? ? ? ? (0x95) reserved ? ? ? ? ? ? ? ? (0x94) reserved ? ? ? ? ? ? ? ? (0x93) reserved ? ? ? ? ? ? ? ? (0x92) reserved ? ? ? ? ? ? ? ? (0x91) reserved ? ? ? ? ? ? ? ? (0x90) reserved ? ? ? ? ? ? ? ? (0x8f) reserved ? ? ? ? ? ? ? ? (0x8e) reserved ? ? ? ? ? ? ? ? (0x8d) reserved ? ? ? ? ? ? ? ? (0x8c) reserved ? ? ? ? ? ? ? ? (0x8b) ocr1bh timer/counter1 - output compare register b high byte 164 (0x8a) ocr1bl timer/counter1 - outp ut compare register b low byte 164 (0x89) ocr1ah timer/counter1 - output compare register a high byte 164 (0x88) ocr1al timer/counter1 - output compare register a low byte 164 (0x87) icr1h timer/counter1 - input capture register high byte 164 (0x86) icr1l timer/counter1 - input capture register low byte 164 (0x85) tcnt1h timer/counter1 - counter register high byte 164 (0x84) tcnt1l timer/counter1 - counter register low byte 164 (0x83) reserved ? ? ? ? ? ? ? ? (0x82) tccr1c foc1a foc1b ? ? ? ? ? ?163 (0x81) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 162 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 ? ?wgm11wgm10 160 (0x7f) didr1 ? ? ? ? ? ?ain1dain0d 274 (0x7e) didr0 ? ? adc5d adc4d adc3d adc2d adc1d adc0d 291 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 449 9159a?auto?09/10 atmel ata6614 [preliminary] (0x7d) reserved ? ? ? ? ? ? ? ? (0x7c) admux refs1 refs0 adlar ? mux3 mux2 mux1 mux0 287 (0x7b) adcsrb ?acme ? ? ? adts2 adts1 adts0 290 (0x7a) adcsra aden adsc adate adif adie adps2 adps1 adps0 288 (0x79) adch adc data register high byte 290 (0x78) adcl adc data register low byte 290 (0x77) reserved ? ? ? ? ? ? ? ? (0x76) reserved ? ? ? ? ? ? ? ? (0x75) reserved ? ? ? ? ? ? ? ? (0x74) reserved ? ? ? ? ? ? ? ? (0x73) reserved ? ? ? ? ? ? ? ? (0x72) reserved ? ? ? ? ? ? ? ? (0x71) reserved ? ? ? ? ? ? ? ? (0x70) timsk2 ? ? ? ? ? ocie2b ocie2a toie2 189 (0x6f) timsk1 ? ?icie1 ? ? ocie1b ocie1a toie1 165 (0x6e) timsk0 ? ? ? ? ? ocie0b ocie0a toie0 136 (0x6d) pcmsk2 pcint23 pcint22 pcint21 pcint20 pcint19 pcint18 pcint17 pcint16 99 (0x6c) pcmsk1 ? pcint14 pcint13 pcint12 pcint11 pcint10 pcint9 pcint8 99 (0x6b) pcmsk0 pcint7 pcint6 pcint5 pc int4 pcint3 pcint2 pcint1 pcint0 99 (0x6a) reserved ? ? ? ? ? ? ? ? (0x69) eicra ? ? ? ?isc11isc10isc01isc00 96 (0x68) pcicr ? ? ? ? ? pcie2 pcie1 pcie0 (0x67) reserved ? ? ? ? ? ? ? ? (0x66) osccal oscillator calibration register 62 (0x65) reserved ? ? ? ? ? ? ? ? (0x64) prr prtwi prtim2 prtim0 ? prtim1 prspi prusart0 pradc 67 (0x63) reserved ? ? ? ? ? ? ? ? (0x62) reserved ? ? ? ? ? ? ? ? (0x61) clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 63 (0x60) wdtcsr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 79 0x3f (0x5f) sreg i t h s v n z c 36 0x3e (0x5e) sph ? ? ? ? ? (sp10) 5. sp9 sp8 38 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 38 0x3c (0x5c) reserved ? ? ? ? ? ? ? ? 0x3b (0x5b) reserved ? ? ? ? ? ? ? ? 0x3a (0x5a) reserved ? ? ? ? ? ? ? ? 0x39 (0x59) reserved ? ? ? ? ? ? ? ? 0x38 (0x58) reserved ? ? ? ? ? ? ? ? 0x37 (0x57) spmcsr spmie (rwwsb) 5. ? (rwwsre) 5. blbset pgwrt pgers selfprgen 317 0x36 (0x56) reserved ? ? ? ? ? ? ? ? 0x35 (0x55) mcucr ? bods bodse pud ? ? ivsel ivce 69/93/117 0x34 (0x54) mcusr ? ? ? ? wdrf borf extrf porf 79 0x33 (0x53) smcr ? ? ? ?sm2sm1sm0se 65 0x32 (0x52) reserved ? ? ? ? ? ? ? ? 0x31 (0x51) reserved ? ? ? ? ? ? ? ? 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 272 0x2f (0x4f) reserved ? ? ? ? ? ? ? ? 0x2e (0x4e) spdr spi data register 200 0x2d (0x4d) spsr spif wcol ? ? ? ? ? spi2x 200 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 198 0x2b (0x4b) gpior2 general purpose i/o register 2 51 0x2a (0x4a) gpior1 general purpose i/o register 1 51 0x29 (0x49) reserved ? ? ? ? ? ? ? ? 0x28 (0x48) ocr0b timer/counter0 output compare register b 0x27 (0x47) ocr0a timer/counter0 output compare register a 0x26 (0x46) tcnt0 timer/counter0 (8-bit) 0x25 (0x45) tccr0b foc0a foc0b ? ? wgm02 cs02 cs01 cs00 0x24 (0x44) tccr0a com0a1 com0a0 com0b1 com0b0 ? ?wgm01wgm00 0x23 (0x43) gtccr tsm ? ? ? ? ? psrasy psrsync 169/191 0x22 (0x42) eearh (eeprom address register high byte) 5. 47 0x21 (0x41) eearl eeprom address register low byte 47 0x20 (0x40) eedr eeprom data register 47 0x1f (0x3f) eecr ? ? eepm1 eepm0 eerie eempe eepe eere 47 0x1e (0x3e) gpior0 general purpose i/o register 0 51 0x1d (0x3d) eimsk ? ? ? ? ? ?int1int0 97 0x1c (0x3c) eifr ? ? ? ? ? ? intf1 intf0 97 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 450 9159a?auto?09/10 atmel ata6614 [preliminary] note: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specif ied bit, and can therefore be used on regi sters containing such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructi ons, 0x20 must be added to these addresses. the atmel atmega48pa/88pa/168pa/328p is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions . for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 5. only valid for atmel atmega88pa/168pa. 0x1b (0x3b) pcifr ? ? ? ? ? pcif2 pcif1 pcif0 0x1a (0x3a) reserved ? ? ? ? ? ? ? ? 0x19 (0x39) reserved ? ? ? ? ? ? ? ? 0x18 (0x38) reserved ? ? ? ? ? ? ? ? 0x17 (0x37) tifr2 ? ? ? ? ? ocf2b ocf2a tov2 190 0x16 (0x36) tifr1 ? ?icf1 ? ? ocf1b ocf1a tov1 165 0x15 (0x35) tifr0 ? ? ? ? ? ocf0b ocf0a tov0 0x14 (0x34) reserved ? ? ? ? ? ? ? ? 0x13 (0x33) reserved ? ? ? ? ? ? ? ? 0x12 (0x32) reserved ? ? ? ? ? ? ? ? 0x11 (0x31) reserved ? ? ? ? ? ? ? ? 0x10 (0x30) reserved ? ? ? ? ? ? ? ? 0x0f (0x2f) reserved ? ? ? ? ? ? ? ? 0x0e (0x2e) reserved ? ? ? ? ? ? ? ? 0x0d (0x2d) reserved ? ? ? ? ? ? ? ? 0x0c (0x2c) reserved ? ? ? ? ? ? ? ? 0x0b (0x2b) portd portd7 portd6 portd 5 portd4 portd3 portd2 portd1 portd0 118 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 118 0x09 (0x29) pind pind7 pind6 pind 5 pind4 pind3 pind2 pind1 pind0 118 0x08 (0x28) portc ? portc6 portc5 portc4 portc3 portc2 portc1 portc0 118 0x07 (0x27) ddrc ? ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 118 0x06 (0x26) pinc ? pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 118 0x05 (0x25) portb portb7 portb6 portb 5 portb4 portb3 portb2 portb1 portb0 117 0x04 (0x24) ddrb ddb7 ddb6 ddb 5 ddb4 ddb3 ddb2 ddb1 ddb0 117 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 118 0x02 (0x22) reserved ? ? ? ? ? ? ? ? 0x01 (0x21) reserved ? ? ? ? ? ? ? ? 0x0 (0x20) reserved ? ? ? ? ? ? ? ? address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 451 9159a?auto?09/10 atmel ata6614 [preliminary] 6.31 instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp (1) k direct jump pc knone3 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 call (1) k direct subroutine call pc knone4 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 452 9159a?auto?09/10 atmel ata6614 [preliminary] brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 mnemonics operands description operation flags #clocks 453 9159a?auto?09/10 atmel ata6614 [preliminary] note: 1. these instructions are only available in atmel atmega168pa and atmel atmega328p. pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks 454 9159a?auto?09/10 atmel ata6614 [preliminary] 8. package information 7. ordering information extended type number program memory package moq ATA6614P-PLQW 32kb flash qfn48, 7 7 4,000 pieces ata6614p-plpw 32kb flash qfn48, 7 7 1,000 pieces title drawing no. rev. packa g e drawin g contact: p a ck a gedr a wing s @ a tmel.com 6.54 3 -51 3 0.01-4 common dimen s ion s (unit of me asu re = mm) min nom note max s ymbol 2 expo s ed p a d 5.6x5.6 packa g e: vqfn_7x7_4 8 l 09/22/10 dimen s ion s in mm s pecific a tion s a ccording to din technic a l dr a wing s 0.02 0.05 0.0 a1 7 7.1 6.9 e 0.2 3 0. 3 0.16 b 0.5 b s c e 0.4 0.5 0. 3 l 5.6 5.75 5.45 e2 5.6 5.75 5.45 d2 7 7.1 6.9 d 0.2 0.25 0.15 a 3 0.9 1 0. 8 a top view d 4 8 1 12 pin 1 id e s ide view a 3 a a1 b l a (10:1) bottom view e d2 4 83 7 1 3 1 12 24 25 3 6 e2 a 455 9159a?auto?09/10 atmel ata6614 [preliminary] 9. table of contents general features ........ ................. ................ ................. .............. ............ 1 1 description .......... .............. .............. ............... .............. .............. ............ 1 2 pin configuration .... ................ ................. ................ ................. ............ 2 3 lin system-basis-chip block ............... ................. ................ ............... 5 3.1 features .........................................................................................................5 3.2 description .....................................................................................................5 3.3 functional description ....................................................................................7 3.4 modes of operation ......................................................................................10 3.5 wake-up scenarios from silent or sleep mode ...........................................18 4 absolute maximum ratings ... ................. ................ ................. .......... 21 5 electrical characteristics ..... ................ ................. ................ ............. 22 6 microcontroller block ........... ................ ................. ................ ............. 29 6.1 features .......................................................................................................29 6.2 overview ......................................................................................................31 6.3 resources ....................................................................................................33 6.4 data retention .............................................................................................33 6.5 about code examples .................................................................................33 6.6 atmel avr cpu core ..................................................................................34 6.7 avr memories .............................................................................................42 6.8 system clock and clock options .................................................................52 6.9 power management and sleep modes ........................................................64 6.10 system control and reset ...........................................................................71 6.11 interrupts ......................................................................................................81 6.12 external interrupts ........................................................................................95 6.13 i/o-ports .....................................................................................................100 6.14 8-bit timer/counter0 with pwm .................................................................119 6.15 16-bit timer/counter1 with pwm ...............................................................138 6.16 timer/counter0 and timer/counter1 prescalers .......................................167 6.17 8-bit timer/counter2 with pwm and asynchronous operation ..................170 6.18 spi ? serial peripheral interface ................................................................192 6.19 usart0 .....................................................................................................201 6.20 usart in spi mode ..................................................................................229 456 9159a?auto?09/10 atmel ata6614 [preliminary] 6.21 2-wire serial interface ................................................................................239 6.22 analog comparator ....................................................................................271 6.23 analog-to-digital converter ........................................................................275 6.24 debugwire on-chip debug system ..........................................................292 6.25 self-programming the flash, atmega48pa ..............................................294 6.26 boot loader support ? read-while-write self-programming, atmel atmega88pa, atmega168pa and atmega328p ..........................302 6.27 memory programming ................................................................................319 6.28 electrical characteristics ............................................................................338 6.29 typical characteristics ...............................................................................350 6.30 register summary .....................................................................................447 6.31 instruction set summary ............................................................................451 7 ordering information .......... ................ ................. ................ ............. 454 8 package information ............ ................ ................. ................ ........... 454 9 table of contents ............. .............. ............... .............. .............. ........ 455 atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: (+1)(408) 441-0311 fax: (+1)(408) 487-2600 atmel asia limited unit 01-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (+81) (3) 3523-3551 fax: (+81) (3) 3523-7581 ? 2010 atmel corporation. all rights reserved. / rev.: 9159a?auto?09/10 atmel ? , atmel logo and combinations thereof, avr ? , avr studio ? and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in con nection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellec- tual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the at mel terms and conditions of sales located on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu - lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without limitation, damages for lo ss and profits, business interruption, or loss of information) arising out of the use or inabil ity to use this document, even if atmel has been advised of the possibility of such damages. at mel makes no representations or warranties with respect to the accura cy or completeness of the contents of this document and reserv es the right to make changes to specifications and products descriptions at any time without not ice. atmel does not make any commitment to update the informati on contained herein. unless specif- ically provided otherwise, atmel produc ts are not suitable for, and shall not be used in, automotive applications. atmel produc ts are not intended, authorized, or war- ranted for use as components in applicatio ns intended to support or sustain life. |
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