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1998 data sheet the mark shows major revised points. mos integrated circuit pd70f3003a, 70f3025a, 70f3003a(a) v853 32-bit single-chip microcontrollers document no. u13189ej5v1ds00 (5th edition) date published august 2005 n cp(k) printed in japan description the pd70f3003a, pd70f3025a, and pd70f3003a(a) have a flash memory instead of the internal mask rom of the pd703003a/703004a, pd703025a, and pd703003a(a), respectively. this model is useful for small-scale production of a variety of application sets or early start of production since the program can be written and erased by the user even with the pd70f3003 mounted on the board. detailed function descriptions are provided in the following user? manuals. be sure to read them before designing. v853 hardware user? manual: u10913e v850 series architecture user? manual: u10243e features compatible with pd703003a, 703004a, 703025a, and 703003a(a) can be replaced with mask rom model for mass production of application set pd70f3003a pd703003a, 703004a pd70f3025a pd703025a pd70f3003a(a) pd703003a(a) internal memory flash memory: 128kb ( pd70f3003a, 70f3003a(a)) 256kb ( pd70f3025a) remark for differences among the products, refer to 1. differences between product . ordering information part number package quality grade pd70f3003agc-33-8eu 100-pin plastic lqfp (fine pitch) (14 14) standard pd70f3003agc-33-8eu-a 100-pin plastic lqfp (fine pitch) (14 14) standard pd70f3025agc-33-8eu 100-pin plastic lqfp (fine pitch) (14 14) standard pd70f3025agc-33-8eu-a 100-pin plastic lqfp (fine pitch) (14 14) standard pd70f3003agc(a)-33-8eu 100-pin plastic lqfp (fine pitch) (14 14) special remarks 1. the pd70f3003a and pd70f3003a(a) differ in the quality grade only. 2. products with -a at the end of the part number are lead-free products. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know the specification of the quality grade on the devices and its recommended applications. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information.
pd70f3003a, 70f3025a, 70f3003a(a) 2 data sheet u13189ej5v1ds applications pd70f3003a, 70f3025a: camcorders, vcrs, ppcs, lbps, printers, motor controllers, nc machine tools, mobile telephones, etc. pd70f3003a(a): medical equipment, automotive appliances, etc. pin configuration (top view) 100-pin plastic lqfp (fine pitch) (14 14) pd70f3003agc-33-8eu pd70f3025agc-33-8eu pd70f3003agc-33-8eu-a pd70f3025agc-33-8eu-a pd70f3003agc(a)-33-8eu 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p31/to131 p32/tclr13 p33/ti13 p34/intp130 p35/intp131/so3 p36/intp132/si3 p37/intp133/sck3 p63/a19 p62/a18 p61/a17 p60/a16 v ss v dd p57/ad15 p56/ad14 p55/ad13 p54/ad12 p53/ad11 p52/ad10 p51/ad9 p50/ad8 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p75/ani5 p74/ani4 p73/ani3 p72/ani2 p71/ani1 p70/ani0 ano0 ano1 av ref2 av ref3 p07/intp113/adtrg p06/intp112 p05/intp111 p04/intp110 p03/ti11 p02/tclr11 p01/to111 p00/to110 p117/intp143 p116/intp142 p115/intp141 p114/intp140 p113/ti14 p112/tclr14 p111/to141 p30/to130 p27/sck1 p26/rxd1/si1 p25/txd1/so1 p24/sck0 p23/rxd0/si0 p22/txd0/so0 p21/pwm1 p20/pwm0 nmi v dd v ss p17/intp123/sck2 p16/intp122/si2 p15/intp121/so2 p14/intp120 p13/ti12 p12/tclr12 p11/to121 p10/to120 av dd av ss av ref1 p77/ani7 p76/ani6 p43/ad3 p42/ad2 v ss v dd p41/ad1 p40/ad0 p90/lben p91/uben p92/r/w p93/dstb p94/astb p95/hldak p96/hldro wait v pp mode reset cv dd /cksel x2 x1 cv ss clkout v ss v dd p110/to140 caution connect v pp pin to v ss pin except the case that pd70f3003a, 70f3003a(a) or 70f3025a is used in flash memory programming mode.
pd70f3003a, 70f3025a, 70f3003a(a) 3 data sheet u13189ej5v1ds p40 to p47: port 4 p50 to p57: port 5 p60 to p63: port 6 p70 to p77: port 7 p90 to p96: port 9 p110 to p117: port 11 pwm0, pwm1: pulse width modulation reset: reset r/w: read/write status rxd0, pxd1: receive data sck0 to sck3: serial clock si0 to si3: serial input so0 to so3: serial output to110, to111, to120, to121, to130, to131, to140, to141: timer output tclr11 to tclr14: timer clear ti11 to ti14: timer input txd0, txd1: transmit data uben: upper byte enable wait: wait x1, x2: crystal v dd : power supply v pp : programming power supply v ss : ground pin names a16 to a19: address bus ad0 to ad15: address/data bus adtrg: a/d trigger input ani0 to ani7: analog input ano0, ano1: analog output astb: address strobe av dd : analog v dd av ref1 to av ref3 : analog reference voltage av ss : analog v ss cv dd : power supply for clock generator cv ss : ground for clock generator cksel: clock select clkout : clock output dstb: data strobe hldak: hold acknowledge hldrq: hold request intp110 to intp113, intp120 to intp123, intp130 to intp133, intp140 to intp143: interrupt request from peripherals lben: lower byte enable mode: mode nmi: non-maskable interrupt request p00 to p07: port 0 p10 to p17: port 1 p20 to p27: port 2 p30 to p37: port 3
pd70f3003a, 70f3025a, 70f3003a(a) 4 data sheet u13189ej5v1ds internal block diagram intp110 to intp113 intp120 to intp123 intp130 to intp133 intp140 to intp143 nmi to110, to111 to120, to121 to130, to131 to140, to141 tclr11 to tclr14 ti11 to ti14 so0/txd0 intc rpu csi2 sio brg2 csi3 flash memory note 1 ram note 2 cpu pc 32-bit barrel shifter system register general- purpose register 32 bits 32 alu multiplier 16 16 32 ports p110 to p117 p90 to p96 p70 to p77 p60 to p63 p50 to p57 p40 to p47 p30 to p37 p20 to p27 p10 to p17 p00 to p07 cg bcu instruction queue astb dstb r/w uben lben wait a16 to a19 ad0 to ad15 hldrq hldak cksel clkout x1 x2 mode reset uart0/csi0 brg0 uart1/csi1 brg1 d/a converter a/d converter ani0 to ani7 av ref1 av ss av dd adtrg ano0, ano1 av ref2 , av ref3 si0/rxd0 sck0 so1/txd1 si1/rxd1 sck1 so2 si2 sck2 so3 si3 sck3 pwm pwm0, pwm1 v dd v ss cv dd cv ss v pp notes 1. pd70f3003a, 70f3003a(a): 128 kb pd70f3025a: 256 kb 2. pd70f3003a, 70f3003a(a): 4 kb pd70f3025a: 8 kb
pd70f3003a, 70f3025a, 70f3003a(a) 5 data sheet u13189ej5v1ds contents 1. differences between products 6 2. pin functions 7 2.1 port pins 7 2.2 non-port pins 9 2.3 pin i/o circuits and recommended connection of unused pins 11 3. electrical specifications 14 3.1 normal operation mode 14 3.2 flash memory programming mode 37 4. package drawing 40 5. recommended soldering conditions 41 appendix notes on target system design 43
pd70f3003a, 70f3025a, 70f3003a(a) 6 data sheet u13189ej5v1ds 1. differences between products item pd703003a pd703004a pd703025a pd703003a(a) pd703025a(a) pd70f3003a pd70f3025a pd70f3003a(a) internal rom mask rom flash memory 128 kb 96 kb 256 kb 128 kb 256 kb 128 kb 256 kb 128 kb internal ram 4 kb 8 kb 4 kb 8 kb 4 kb 8 kb 4 kb flash memory none provided programming mode v pp pin none provided quality grade standard special standard special electrical specifications current consumption, etc. differs. (refer to each product data sheets). others noise immunity and noise radiation differ because circuit scale and mask layout differ. caution there are differences in noise immunity and noise radiation between the flash memory version and mask rom version. when pre-producing an application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluation for commercial samples (not engineering samples) of the mask rom version.
pd70f3003a, 70f3025a, 70f3003a(a) 7 data sheet u13189ej5v1ds 2. pin functions 2.1 port pins (1/2) pin name i/o function alternate function p00 i/o port 0 to110 p01 8-bit i/o port. to111 p02 input/output can be specified in 1-bit units. tclr11 p03 ti11 p04 intp110 p05 intp111 p06 intp112 p07 intp113/adtrg p10 i/o port 1 to120 p11 8-bit i/o port. to121 p12 input/output can be specified in 1-bit units. tclr12 p13 ti12 p14 intp120 p15 intp121/so2 p16 intp122/si2 p17 i ntp123/sck2 p20 i/o port 2 pwm0 p21 8-bit i/o port. pwm1 p22 input/output can be specified in 1-bit units. txd0/so0 p23 rxd0/si0 p24 sck0 p25 txd1/so1 p26 rxd1/si1 p27 sck1 p30 i/o port 3 to130 p31 8-bit i/o port. to131 p32 input/output can be specified in 1-bit units. tclr13 p33 ti13 p34 intp130 p35 intp131/so3 p36 intp132/si3 p37 i ntp133/sck3 p40 to p47 i/o port 4 ad0 to ad7 8-bit i/o port. input/output can be specified in 1-bit units. p50 to p57 i/o port 5 ad8 to ad15 8-bit i/o port. input/output can be specified in 1-bit units.
pd70f3003a, 70f3025a, 70f3003a(a) 8 data sheet u13189ej5v1ds (2/2) pin name i/o function alternate function p60 to p63 i/o port 6 a16 to a19 4-bit i/o port. input/output can be specified in 1-bit units. p70 to p77 input port 7 ani0 to ani7 8-bit input port. p90 i/o port 9 lben p91 7-bit i/o port. uben p92 input/output can be specified in 1-bit units. r/w p93 dstb p94 astb p95 hldak p96 hldrq p110 i/o port 11 to140 p111 8-bit i/o port. to141 p112 input/output can be specified in 1-bit units. tclr14 p113 ti14 p114 intp140 p115 intp141 p116 intp142 p117 intp143
pd70f3003a, 70f3025a, 70f3003a(a) 9 data sheet u13189ej5v1ds 2.2 non-port pins (1/2) pin name i/o function alternate function to110 output pulse signal output from timers 11 to 14 p00 to111 p01 to120 p10 to121 p11 to130 p30 to131 p31 to140 p110 to141 p111 tclr11 input external clear signal input for timers 11 to 14 p02 tclr12 p12 tclr13 p32 tclr14 p112 ti11 input external count clock input for timers 11 to 14 p03 ti12 p13 ti13 p33 ti14 p113 intp110 input external maskable interrupt request input and external capture p04 intp111 trigger input for timer 11 p05 intp112 p06 intp113 p07/adtrg intp120 input external maskable interrupt request input and external capture p14 intp121 trigger input for timer 12 p15/so2 intp122 p16/s12 intp123 p17/sck2 intp130 input external maskable interrupt request input and external capture p34 intp131 trigger input for timer 13 p35/so3 intp132 p36/si3 intp133 p37/sck3 intp140 input external maskable interrupt request input and external capture p114 intp141 trigger input for timer 14 p115 intp142 p116 intp143 p117 so0 output serial transmit data output for csi0 to csi3 (3-wire) p22/txd0 so1 p25/txd1 so2 p15/intp121 so3 p35/intp131 si0 input serial receive data output for csi0 to csi3 (3-wire) p23/rxd0 si1 p26/rxd1 si2 p16/intp122 si3 p36/intp132
pd70f3003a, 70f3025a, 70f3003a(a) 10 data sheet u13189ej5v1ds (2/2) pin name i/o function alternate function sck0 i/o serial clock i/o for csi0 to csi3 (3-wire) p24 sck1 p27 sck2 p17/intp123 sck3 p37/intp133 txd0 output serial transmit data output of uart0 to uart1 p22/so0 txd1 p25/so1 rxd0 input serial receive data input of uart0 to uart1 p23/si0 rxd1 p26/si1 pwm0 output pulse signal output of pwm p20 pwm1 p21 ad0 to ad7 i/o 16-bit multiplexed address/data bus when external memory is connected p40 to p47 ad8 to ad15 p50 to p57 a16 to a19 output higher address bus when external memory is connected p60 to p63 lben output lower byte enable signal output of external data bus p90 uben higher byte enable signal output of external data bus p91 r/w output external read/write status output p92 dstb external data strobe signal output p93 astb external address strobe signal output p94 hldak output bus hold acknowledge output p95 hldrq input bus hold request input p96 ani0 to ani7 input analog input to a/d converter p70 to p77 ano0, ano1 output analog output of d/a converter nmi input non-maskable interrupt request input clkout output system clock output cksel input input specifying operation mode of clock generator cv dd wait input control signal input inserting wait state in bus cycle mode input operation mode specification reset input system reset input x1 input system clock resonator connection. input external clock to x1 to x2 supply external clock. adtrg input a/d converter external trigger input p07/intp113 av ref1 input reference voltage input for a/d converter av ref2 input reference voltage input for d/a converter av ref3 av dd positive power supply for a/d converter av ss ground potential for a/d converter cv dd positive power supply for internal clock generator cksel cv ss ground potential for internal clock generator v dd positive power supply v ss ground potential v pp high voltage application pin when program is written/verified
pd70f3003a, 70f3025a, 70f3003a(a) 11 data sheet u13189ej5v1ds 2.3 pin i/o circuits and recommended connection of unused pins table 2-1 shows the i/o circuit type of each pin, and the recommended connections of the unused pins. figure 2-1 shows a partially simplified diagram of each circuit. it is recommended that 1 to 10 k ? resistors be used when connecting to v dd or v ss via a resistor. table 2-1. types of pin i/o circuits and recommended connections of unused pins (1/2) pin name i/o circuit type recommended connection of unused pins p00/to110, p01/to111 5 input: independently connect to v dd or v ss via a resistor. p02/tclr11, p03/ti11, 8 output: leave open. p04/intp110 to p07/intp113/adtrg p10 to to120, p11/to121 5 p12/tclr12, p13/ti12 8 p14/intp120 p15/intp121/so2 p16/intp122/si2 p17/intp123/sck2 p20/pwm0, p21/pwm1 5 p22/txd0/so0 p23/rxd0/si0, p24/sck0 8 p25/txd1/so1 5 p26/rxd1/si1, p27/sck1 8 p30/to130, p31/to131 5 p32/tclr13, p33/ti13 8 p34/intp130 p35/intp131/so3 10-a p36/intp132/si3 p37/intp133/sck3 p40/ad0 to p47/ad7 5 p50/ad8 to p57/ad15 p60/a16 to p63/a19 p70/ani0 to p77/ani7 9 directly connect to v ss . p90/lben 5 input: independently connect to v dd or v ss via a resistor. p91/uben output: leave open. p92/r/w p93/dstb p94/astb p95/hldak p96/hldrq p110/to140, p111/to141 p112/tclr14, p113/ti14 8 p114/intp140 to p117/intp143
pd70f3003a, 70f3025a, 70f3003a(a) 12 data sheet u13189ej5v1ds table 2-1. types of pin i/o circuits and recommended connection of unused pins (2/2) pin name i/o circuit type recommended connection of unused pins ano0, ano1 12 leave open. nmi 2 directly connect to v ss . clkout 3 leave open. wait 1 directly connect to v dd . mode 2 reset cv dd /cksel av ref1 to av ref3 , av ss directly connect to v ss . av dd directly connect to v dd . v pp connect to v ss .
pd70f3003a, 70f3025a, 70f3003a(a) 13 data sheet u13189ej5v1ds figure 2-1. pins i/o circuits type 1 type 5 type 2 type 8 type 3 p-ch n-ch in v dd in schmitt trigger input with hysteresis characteristics p-ch n-ch v dd out p-ch n-ch v dd in/out data output disable input enable p-ch n-ch v dd in/out data output disable type 9 type 10-a type 12 + n-ch p-ch comparator v ref (threshold voltage) input enable in p-ch n-ch v dd in/out p-ch v dd data pull-up enable output disable open drain analog output voltage out p-ch n-ch
pd70f3003a, 70f3025a, 70f3003a(a) 14 data sheet u13189ej5v1ds 3. electrical specifications 3.1 normal operation mode absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd v dd pin ?.5 to +7.0 v cv dd cv dd pin ?.5 to v dd + 0.3 note 1 v cv ss cv ss pin ?.5 to +0.5 v av dd av dd pin ?.5 to v dd + 0.3 note 1 v av ss av ss pin ?.5 to +0.5 v input voltage v i1 note 2 , v dd = 5.0 v 10% ?.5 to v dd + 0.3 note 1 v v i2 v pp pin in flash memory programming mode, ?.5 to +11.0 v v dd = 5.0 v 10% clock input voltage v k x1 pin, v dd = 5.0 v 10% ?.5 to v dd + 1.0 note 1 v output current, low i cl 1 pin 4.0 ma total of all pins 100 ma output current, high i ch 1 pin ?.0 ma total of all pins ?00 ma output voltage v o v dd = 5.0 v 10% ?.5 to v dd + 0.3 note 1 v analog input voltage v ian p70/ani0 to p77/ani7 av dd > v dd ?.5 to v dd + 0.3 note 1 v v dd av dd ?.5 to av dd + 0.3 note 1 v analog reference input voltage av ref av ref1 to av ref3 av dd > v dd ?.5 to v dd + 0.3 note 1 v v dd av dd ?.5 to av dd + 0.3 note 1 v operating ambient temperature t a ?0 to +85 c storage temperature t stg ?5 to +125 c notes 1. be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. 2. x1, p70 to p77, av ref1 to av ref3 , and their alternate-function pins are excluded. cautions 1. avoid direct connections among the ic device output (or i/o) pins and between v dd or v cc and gnd. however, direct connections among open-drain and open-collector pins are possible, as are direct connections to external circuits that have timing designed to prevent output conflict with pins that become high-impedance. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the normal operating ranges of ratings and conditions in which the quality of the product is guaranteed are specified in the following dc characteristics and ac characteristics.
pd70f3003a, 70f3025a, 70f3003a(a) 15 data sheet u13189ej5v1ds capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i fc = 1 mhz 15 pf i/o capacitance c io pins other than tested pin: 0 v 15 pf output capacitance c o 15 pf operating conditions operation mode internal system clock frequency ( ) operating temperature (t a ) supply voltage (v dd ) direct mode, 2 to 33 mhz note 1 ?0 to +85 c 5.0 v 10% pll mode 5 to 33 mhz note 2 ?0 to +85 c 5.0 v 10% notes 1. when a/d converter not used. 2. when a/d converter used. recommended oscillator caution for the resonator selection and oscillator constant of the pd70f3003a(a), customers are requested to apply to the resonator manufacturer for evaluation. (1) ceramic resonator connection (t a = ?0 to +85 c) (a) pd70f3003a x1 x2 c1 c2 rd manufacturer part number oscillation recommended oscillation oscillation frequency circuit constant voltage range stabilization time f xx (mhz) c1 (pf) c2 (pf) r d (w) min. (v) max. (v) (max.) t ost (ms) kyocera pbrc4.00hr 4.0 on-chip on-chip 4.5 5.5 0.10 corporation pbrc5.00hr 5.0 on-chip on-chip 4.5 5.5 0.08 pbrc6.00hr 6.0 on-chip on-chip 4.5 5.5 0.08 pbrc6.60hr 6.6 on-chip on-chip 4.5 5.5 0.08 tdk fcr4.0mc5 4.0 on-chip on-chip 4.5 5.5 0.14 fcr5.0mc5 5.0 on-chip on-chip 4.5 5.5 0.14 fcr6.0mc5 6.0 on-chip on-chip 4.5 5.5 0.11 murata mfg. csts0400mg06 4.0 on-chip on-chip 4.5 5.5 0.12 co., ltd cstcr4m00g05 4.0 on-chip on-chip 4.5 5.5 0.14 csts0600mg06 6.0 on-chip on-chip 4.5 5.5 0.14 cstcr6m00g55-r0 6.0 on-chip on-chip 4.5 5.5 0.18 cautions 1. connect the oscillator as closely to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area indicated by the broken lines. 3. thoroughly evaluate the matching between the pd70f3003a and the resonator.
pd70f3003a, 70f3025a, 70f3003a(a) 16 data sheet u13189ej5v1ds (b) pd70f3025a x1 x2 c1 c2 rd cautions 1. connect the oscillator as closely to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area indicated by the broken lines. 3. thoroughly evaluate the matching between the pd70f3025a and the resonator. (2) external clock input x1 high-speed cmos inverter external clock x2 open cautions 1. put the high-speed cmos inverter as close to the x1 pins as possible. 2. sufficiently evaluate the matching between the pd70f3003a, 70f3025a, or 70f3003a(a), and the high-speed cmos inverter. manufacturer part number oscillation recommended oscillation oscillation frequency circuit constant voltage range stabilization time f xx (mhz) c1 (pf) c2 (pf) r d (w) min. (v) max. (v) (max.) t ost (ms) kyocera pbrc4.00hr 4.0 on-chip on-chip 4.5 5.5 0.12 corporation pbrc5.00hr 5.0 on-chip on-chip 4.5 5.5 0.04 pbrc6.00hr 6.0 on-chip on-chip 4.5 5.5 0.04 pbrc6.60hr 6.6 on-chip on-chip 4.5 5.5 0.04 tdk fcr4.0mc5 4.0 on-chip on-chip 4.5 5.5 0.14 fcr5.0mc5 5.0 on-chip on-chip 4.5 5.5 0.13 fcr6.0mc5 6.0 on-chip on-chip 4.5 5.5 0.13 murata mfg. csts0400mg06 4.0 on-chip on-chip 4.5 5.5 0.12 co., ltd cstcr4m00g55-r0 4.0 on-chip on-chip 4.5 5.5 0.14 csts0600mg06 6.0 on-chip on-chip 4.5 5.5 0.16 cstcr6m00g55-r0 6.0 on-chip on-chip 4.5 5.5 0.19
pd70f3003a, 70f3025a, 70f3003a(a) 17 data sheet u13189ej5v1ds dc characteristics (t a = ?0 to +85 c, v dd = 5.0 v 10%, v ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit input voltage, high v ih except x1 and note 2.2 v dd + 0.3 v note 0.8v dd v dd + 0.3 v input voltage, low v il except x1 and note ?.5 +0.8 v note ?.5 0.2v dd v clock input voltage, high v xh x1 0.8v dd v dd + 0.5 v clock input voltage, low v xl x1 ?.5 0.6 v schmitt trigger input threshold voltage v t + note , rising 3.0 v v t note , falling 2.0 v schmitt trigger input hysteresis width v t + ?v t note 0.5 v output voltage, high v oh i oh = ?.5 ma 0.7v dd v i oh = ?00 av dd ?0.4 v output voltage, low v ol i oc = 2.5 ma 0.45 v input leakage current, high i lih v i = v dd 10 a input leakage current, low i lil v i = 0 v ?0 a output leakage current, high i loh v o = v dd 10 a output leakage current, low i lol v o = 0 v ?0 a software pull-up resistor r p35/intp131/so3, 15 40 90 k ? p36/intp132/si3, p37/intp133/sck3 note p02 to p07, p12 to p17, p23, p24, p26, p27, p32 to p37, p112 to p117, reset, nmi, mode, and their alternate-function pins. remark typ. values are reference values for when t a = 25 c and v dd = 5.0 v.
pd70f3003a, 70f3025a, 70f3003a(a) 18 data sheet u13189ej5v1ds (2/2) parameter symbol conditions min. typ. max. unit supply pd70f3003a, operating i dd1 direct mode 2.2 + 7.5 2.5 + 22 ma current 70f3003a(a) pll mode 2.3 + 9.5 2.6 + 25 ma in halt mode i dd2 direct mode 1.2 + 7.5 1.3 + 15 ma pll mode 1.3 + 9.5 1.4 + 17 ma in idle mode i dd3 direct mode 8 + 300 10 + 500 a pll mode 0.1 + 2 0.2 + 3 ma in stop mode i dd4 cesel = 0, note 1 250 a cesel = 0, note 2 2 200 a cesel = 1, note 1 30 200 a cesel = 1, note 2 30 500 a pd70f3025a operating i dd1 direct mode 2.5 + 8 2.8 + 22.5 ma pll mode 2.6 + 10 2.9 + 25.5 ma in halt mode i dd2 direct mode 1.3 + 7.5 1.4 + 15 ma pll mode 1.3 + 12.5 1.4 + 20 ma in idle mode i dd3 direct mode 8 + 300 10 + 500 a pll mode 0.1 + 2 0.2 + 3 ma in stop mode i dd4 cesel = 0, note 1 250 a cesel = 0, note 2 2 200 a cesel = 1, note 1 60 300 a cesel = 1, note 2 60 500 a notes 1. ?0 c t a +50 c 2. 50 c < t a 85 c remarks 1. typ. values are reference values for when t a = 25 c (except for the conditions in note 2 ) and v dd = 5.0 v. the power supply current does not include av ref1 to av ref3 or the current that flows through software pull-up resistors. 2. : internal system clock frequency
pd70f3003a, 70f3025a, 70f3003a(a) 19 data sheet u13189ej5v1ds data retention characteristics (t a = ?0 to +85 c, v dd = v dddr ) parameter symbol conditions min. typ. max. unit data hold voltage v dddr stop mode 1.5 5.5 v data hold current i dddr pd70f3003a, cesel = 0, note 1 0.4v dddr 50 a 70f3003a(a) cesel = 0, note 2 0.4v dddr 200 a cesel = 1, note 1 6v dddr 200 a cesel = 1, note 2 6v dddr 500 a pd70f3025a cesel = 0, note 1 0.4v dddr 50 a cesel = 0, note 2 0.4v dddr 200 a cesel = 1, note 1 12v dddr 300 a cesel = 1, note 2 12v dddr 500 a supply voltage rise time t rvd 200 s supply voltage fall time t fvd 200 s supply voltage hold time t hvd 0ms (vs. stop mode setting) stop mode release signal input time t drel 0ns data hold input voltage, high v ihdr note 3 0.9v dddr v dddr v data hold input voltage, low v ildr note 3 0 0.1v dddr v notes 1. ?0 c t a +50 c 2. 50 c pd70f3003a, 70f3025a, 70f3003a(a) 20 data sheet u13189ej5v1ds t hvd v dd v dd t fvd t rvd t drel v dd v dddr reset (input) v ihdr nmi (input) (release by falling edge) v ihdr v ildr nmi (input) (release by rising edge) stop mode is set (at fifth clock after psc register has been set).
pd70f3003a, 70f3025a, 70f3003a(a) 21 data sheet u13189ej5v1ds ac characteristics (t a = ?0 to +85 c, v dd = 5.0 v 10%, v ss = 0 v) ac test input test points (a) p02 to p07, p12 to p17, p23, p24, p26, p27, p32 to p37, p112 to p117, reset, nmi, mode, x1, and their alternate-function pins (b) other than (a) ac test output test points load condition c l = 50 pf dut (tested device) caution if the load capacitance exceeds 50 pf due to the circuit configuration, decrease the load capacitance of this device to less then 50 pf by using a buffer. test points 0.8v dd 0.2v dd 0.8v dd 0.2v dd v dd 0 v test points 2.2 v 0.8 v 2.2 v 0.8 v 2.4 v 0.4 v test points 2.2 v 0.8 v 2.2 v 0.8 v
pd70f3003a, 70f3025a, 70f3003a(a) 22 data sheet u13189ej5v1ds (1) clock timing parameter symbol conditions min. max. unit x1 input cycle <1> t cyx direct mode 15 note 1 ns pll mode 151 note 2 note 3 ns (pll lock status) x1 input width, high <2> t wxh direct mode 6 ns pll mode 60 ns x1 input width, low <3> t wxl direct mode 6 ns pll mode 60 ns x1 input rise time <4> t xr direct mode 7 ns pll mode 10 ns x1 input fall time <5> t xf direct mode 7 ns pll mode 10 ns cpu operating frequency note 4 33 mhz clkout output cycle <6> t cyk 30 note 5 ns clkout width, high <7> t wkh 0.5 t ?5 ns clkout width, low <8> t wkl 0.5 t ?5 ns clkout rise time <9> t xr 5 ns clkout fall time <10> t xf 5 ns x1 clkout delay time <11> t dxk direct mode 3 17 ns notes 1. when a/d converter used: 100 ns when a/d converter not used: 250 ns 2. when using a/d converter: the value when = 5 f xx and = f xx are set. setting = 1/2 f xx is prohibited. when not using a/d converter: the value when = 5 f xx , = f xx , and = 1/2 f xx are set. 3. when using a/d converter: 250 ns (when = 5 f xx is set) and 200 ns (when = f xx is set). setting = 1/2 f xx is prohibited. when not using a/d converter: 250 ns (when = 5 f xx , = f xx , and = 1/2 f xx are set). 4. when a/d converter used: 5 mhz when a/d converter not used: 2 mhz 5. when a/d converter used: 200 ns when a/d converter not used: 500 ns remark t = t cyk <1> <2> <4> <11> <5> <6> <7> <9> <10> <8> <3> x1 (input) clkout (output) <11>
pd70f3003a, 70f3025a, 70f3003a(a) 23 data sheet u13189ej5v1ds (2) input wave (a) p02 to p07, p12 to p17, p23, p24, p26, p27, p32 to p37, p112 to p117, reset, nmi, mode, and their alternate-function pins parameter symbol conditions min. max. unit input rise time <12> t ir2 20 ns input fall time <13> t if2 20 ns (b) other than (a) parameter symbol conditions min. max. unit input rise time <14> t ir1 10 ns input fall time <15> t if1 10 ns 2.2 v 0.8 v 2.2 v 0.8 v 2.4 v 0.4 v input signal < 15 > < 14 > 0.8v dd 0.2v dd 0.8v dd 0.2v dd v dd 0 v input signal < 13 > < 12 >
pd70f3003a, 70f3025a, 70f3003a(a) 24 data sheet u13189ej5v1ds (3) output wave (other than clkout) parameter symbol conditions min. max. unit output rise time <16> t or 10 ns output fall time <17> t of 10 ns (4) reset timing parameter symbol conditions min. max. unit reset width, high <18> t wrsh 500 ns reset width, low <19> t wrsl on power appli- 500 + t ost ns cation, or on releasing stop mode except on power 500 ns application, or except on releas- ing stop mode remark t ost : oscillation stabilization time 0.8 v 2.2 v output signal < 16 > < 17 > 2.2 v 0.8 v reset (input) < 18 > < 19 >
pd70f3003a, 70f3025a, 70f3003a(a) 25 data sheet u13189ej5v1ds (5) read timing (1/2) parameter symbol conditions min. max. unit delay time from clkout to address <20> t dka 3 20 ns delay time from clkout to r/w, uben, lben <78> t dka2 2 +13 ns delay time from clkout to address float <21> t fka 3 15 ns delay time from clkout to astb <22> t dkst 3 15 ns delay time from clkout to dstb <23> t dkd 3 15 ns data input setup time (to clkout ) <24> t sidk 5 ns data input hold time (from clkout ) <25> t hkid 5 ns wait setup time (to clkout ) <26> t swtk 5 ns wait hold time (from clkout ) <27> t hkwt 5 ns address hold time (from clkout ) <28> t hka 0 ns address setup time (to astb ) <29> t sast ?0 c t a +70 c 0.5 t ?10 ns 70 c < t a 85 c 0.5 t ?12 ns address hold time (from astb ) <30> t hsta 0.5 t ?10 ns delay time from dstb to address float <31> t fda 0 ns data input setup time (to address) <32> t said ?0 c t a +70 c (2 + n) t 22 ns 70 c < t a 85 c (2 + n) t 25 ns data input setup time (to dstb ) <33> t sdid ?0 c t a +70 c (1 + n) t 20 ns 70 c < t a 85 c (1 + n) t 24 ns delay time from astb to dstb <34> t dstd 0.5 t ?10 ns data input hold time (from dstb ) <35> t hdid 0 ns delay time from dstb to address output <36> t dda (1 + i) t ns delay time from dstb to astb <37> t ddsth 0.5 t ?10 ns delay time from dstb to astb <38> t ddstl (1.5 + i) t ?10 ns dstb low-level width <39> t wdl ?0 c t a +70 c (1 + n) t ?10 ns 70 c < t a 85 c (1 + n) t ?13 ns astb high-level width <40> t wsth t 10 ns wait setup time (to address) <41> t sawt1 n 1, ?0 c t a +70 c 1.5 t ?20 ns n 1, 70 c < t a 85 c 1.5 t ?24 ns <42> t sawt2 n 1, ?0 c t a +70 c (1.5 + n) t ?20 ns n 1, 70 c < t a 85 c (1.5 + n) t ?24 ns wait hold time (from address) <43> t hawt1 n 1 (0.5 + n) t ns <44> t hawt2 n 1 (1.5 + n) t ns wait setup time (to astb ) <45> t sstwt1 n 1, ?0 c t a +70 c t 18 ns n 1, 70 c < t a 85 c t 20 ns <46> t sstwt2 n 1 (1 + n) t ?15 ns wait hold time (from astb ) <47> t hstwt1 n 1 nt ns <48> t hstwt2 n 1 (1 + n) t ns remarks 1. t = t cyk 2. n indicates the number of wait clocks inserted in the bus cycle. the sampling timing differs when the programmable wait state is inserted. 3. i indicates the number of idle states (0 or 1) t be inserted in the read cycle. 4. be sure to observe at least one of data input hold times t hkid (<25>) and t hdid (<35>).
pd70f3003a, 70f3025a, 70f3003a(a) 26 data sheet u13189ej5v1ds (5) read timing (2/2): 1 wait t1 t2 tw t3 clkout (output) a16 to a19 (output) ad0-ad15 (i/o) astb (output) dstb (output) wait (input) < 32 > < 20 > < 78 > < 28 > r/w (output) uben (output) lben (output) < 25 > < 24 > < 21 > a0 to a15 (output) d0 to d15 (input) < 22 > < 29 > < 30 > < 22 > < 35 > < 37 > < 36 > < 23 > < 31 > < 23 > < 40> < 33 > < 34 > < 39 > < 38 > < 26 > < 27 > < 26 > < 47 > < 46 > < 48 > < 27 > < 45 > < 41 > < 44 > < 43 > < 42 > remark broken line indicates high-impedance.
pd70f3003a, 70f3025a, 70f3003a(a) 27 data sheet u13189ej5v1ds (6) write timing (1/2) parameter symbol conditions min. max. unit delay time from clkout to address <20> t dka 3 20 ns delay time from clkout to r/w, uben, lben <78> t dka2 2 +13 ns delay time from clkout to astb <22> t dkst 3 15 ns delay time from clkout to dstb <23> t dkd 3 15 ns wait setup time (to clkout ) <26> t swtk 5 ns wait hold time (from clkout ) <27> t hkwt 5 ns address hold time (from clkout ) <28> t hka 0 ns address setup time (to astb ) <29> t sast ?0 c t a +70 c 0.5 t ?10 ns 70 c < t a 85 c 0.5 t ?12 ns address hold time (from astb ) <30> t hsta 0.5 t ?10 ns delay time from astb to dstb <34> t dstd 0.5 t ?10 ns delay time from dstb to astb <37> t ddsth 0.5 t ?10 ns dstb low-level width <39> t wdl ?0 c t a +70 c (1 + n) t ?10 ns 70 c < t a 85 c (1 + n) t ?13 ns astb high-level width <40> t wsth t 10 ns wait setup time (to address) <41> t sawt1 n 1, ?0 c t a +70 c 1.5 t ?20 ns n 1, 70 c < t a 85 c 1.5 t ?24 ns <42> t sawt2 n 1, ?0 c t a +70 c (1.5 + n) t ?20 ns n 1, 70 c < t a 85 c (1.5 + n) t ?24 ns wait hold time (from address) <43> t hawt1 n 1 (0.5 + n) t ns <44> t hawt2 n 1 (1.5 + n) t ns wait setup time (to astb ) <45> t sstwt1 n 1, ?0 c t a +70 c t 18 ns n 1, 70 c < t a 85 c t 20 ns <46> t sstwt2 n 1 (1 + n) t ?15 ns wait hold time (from astb ) <47> t hstwt1 n 1 nt ns <48> t hstwt2 n 1 (1 + n) t ns address hold time (from clkout ) <49> t dkod ?0 c t a +70 c 20 ns 70 c < t a 85 c 23 ns delay time from dstb to data output <50> t ddod 10 ns data output hold time (from clkout ) <51> t hkod 0 ns data output setup time (to dstb ) <52> t sodd (1 + n) t ?15 ns data output hold time (from dstb ) <53> t hdod t 10 ns remarks 1. t = t cyk 2. n indicates the number of wait clocks inserted in the bus cycle. the sampling timing differs when the programmable wait state is inserted.
pd70f3003a, 70f3025a, 70f3003a(a) 28 data sheet u13189ej5v1ds (6) write timing (2/2): 1 wait t1 t2 tw t3 clkout (output) a16 to a19 (output) ad0-ad15 (i/o) astb (output) dstb (output) wait (input) < 20 > < 28 > r/w (output) uben (output) lben (output) < 78 > < 49 > a0 to a15 (output) d0 to d15 (output) < 22 > < 29 > < 30 > < 22 > < 37 > < 53 > < 23 > < 23 > < 40 > < 52 > < 34 > < 39 > < 26 > < 27 > < 26 > < 47 > < 46 > < 48 > < 27 > < 45 > < 41 > < 44 > < 43 > < 42 > < 51 > remark broken line indicates high-impedance. < 50 >
pd70f3003a, 70f3025a, 70f3003a(a) 29 data sheet u13189ej5v1ds (7) bus hold timing (1/2) parameter symbol conditions min. max. unit hldrq setup time (to clkout ) <54> t shok 5 ns hldrq hold time (from clkout ) <55> t hkhq 5 ns delay time from hldak to clkout <56> t dkha 20 ns hldrq high-level width <57> t whqh t + 10 ns hldak low-level width <58> t whal ?0 c t a +70 c t 10 ns 70 c < t a 85 c t 12 ns delay time from clkout to bus float <59> t dkf 20 ns delay time from hldak to bus output <60> t dhac 3 ns delay time from hldrq to hldak <61> t dhqha1 (2 n + 7.5) t + 20 ns delay time from hldrq to hldak <62> t dhqha2 0.5 t 1.5 t + 20 ns remarks 1. t = t cyk 2. n indicates the number of wait clocks inserted in the bus cycle. the sampling timing differs when the programmable wait state is inserted.
pd70f3003a, 70f3025a, 70f3003a(a) 30 data sheet u13189ej5v1ds (7) bus hold timing (2/2) th th th ti th clkout (output) hldak (output) dstb (output) hldrq (input) astb (output) ad0 to ad15 (i/o) d0 to d15 (input or output) < 55 > < 61 > < 62 > < 57 > < 54 > < 54 > < 56 > < 58 > < 56 > < 60 > note uben (output), lben (output) remark broken line indicates high-impedance. a16 to a19 (output) note < 59 > r/w (output)
pd70f3003a, 70f3025a, 70f3003a(a) 31 data sheet u13189ej5v1ds (8) interrupt timing parameter symbol conditions min. max. unit nmi width, high <63> t wnih 500 ns nmi width, low <64> t wnil 500 ns intpn width, high <65> t with n = 110 to 113, 3 t + 10 ns 120 to 123, 130 to 133, 140 to 143 intpn width, low <66> t witl n = 110 to 113, 3 t + 10 ns 120 to 123, 130 to 133, 140 to 143 remark t = t cyk nmi (input) < 63 > < 64 > intpn (input) < 65 > < 66> remark n = 110 to 113, 120 to 123, 130 to 133, 140 to 143
pd70f3003a, 70f3025a, 70f3003a(a) 32 data sheet u13189ej5v1ds (9) csi timing (1/2) (a) master mode (i) csi0 to csi2 timing parameter symbol conditions min. max. unit sckn cycle <67> t cysk1 output 120 ns sckn high-level width <68> t wskh1 output 0.5 t cysk1 ?20 ns sckn low-level width <69> t wskl1 output 0.5 t cysk1 ?20 ns sin setup time (to sckn ) <70> t ssisk1 30 ns sin hold time (from sckn ) <71> t hsksi1 0 ns son output delay time (from sckn ) <72> t dskso1 18 ns son output hold time (from sckn ) <73> t hskso1 0.5 t cysk1 ?5 ns remark n = 0 to 2 (ii) csi3 timing parameter symbol conditions min. max. unit sck3 cycle <67> t cysk3 output 500 ns sck3 high-level width <68> t wskh3 output 0.5 t cysk3 ?70 ns sck3 low-level width <69> t wskl3 output 0.5 t cysk3 ?70 ns si3 setup time (to sck3 ) <70> t ssisk3 100 ns si3 hold time (from sck3 ) <71> t hsksi3 50 ns so3 output delay time (from sck3 ) <72> t dskso3 r l = 1.5 k ? 150 ns c l = 50 pf so3 output hold time (from sck3 ) <73> t hskso3 0.5 t cysk3 ?5 ns remark r l and c l are the load resistance and load capacitance respectively of the sck3 and so3 output lines. (b) slave mode (i) csi0 to csi2 timing parameter symbol conditions min. max. unit sckn cycle <67> t cysk2 input 120 ns sckn high-level width <68> t wskh2 input 30 ns sckn low-level width <69> t wskl2 input 30 ns sin setup time (to sckn ) <70> t ssisk2 10 ns sin hold time (from sckn ) <71> t hsksi2 10 ns son output delay time (from sckn ) <72> t dskso2 30 ns son output hold time (from sckn ) <73> t hskso2 t wskh2 ns remark n = 0 to 2 r l = 1.5 k ? c l = 50 pf
pd70f3003a, 70f3025a, 70f3003a(a) 33 data sheet u13189ej5v1ds (9) csi timing (2/2) (ii) csi3 timing parameter symbol conditions min. max. unit sck3 cycle <67> t cysk4 input 500 ns sck3 high-level width <68> t wskh4 input 180 ns sck3 low-level width <69> t wskl4 input 180 ns si3 setup time (to sck3 ) <70> t ssisk4 100 ns si3 hold time (from sck3 ) <71> t hsksi4 50 ns so3 output delay time (from sck3 ) <72> t dskso4 r l = 1.5 k ? 150 ns so3 output hold time (from sck3 ) <73> t hskso4 c l = 50 pf t wskh4 ns remark r l and c l are the load resistance and load capacitance respectively of the sck3 and so3 output lines. sckn (i/o) sin (input) son (output) < 67 > < 69 > < 68 > < 70 > < 71 > < 72 > < 73 > input data output data remark 1. the broken line indicates the high-impedance state. 2. n = 0 to 3
pd70f3003a, 70f3025a, 70f3003a(a) 34 data sheet u13189ej5v1ds (10) rpu timing parameter symbol conditions min. max. unit ti1n high-level width <74> t wtih 3 t + 10 ns ti1n low-level width <75> t wtil 3 t + 10 ns tclr1n high-level width <76> t wtch 3 t + 10 ns tclr1n low-level width <77> t wtcl 3 t + 10 ns remark t = t cyk ti1n (input) <74> <75> tclr1n (input) <76> <77> remark n = 1 to 4
pd70f3003a, 70f3025a, 70f3003a(a) 35 data sheet u13189ej5v1ds a/d converter characteristics (t a = ?0 to +85 c, v dd = av dd = 5 v 10%, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit overall error note 1 4.5 v av ref1 av dd 0.4 %fsr 3.5 v av ref1 av dd 0.7 %fsr quantization error 1/2 lsb conversion time t conv 4.5 v av ref1 av dd 60 t cyk 3.5 v av ref1 av dd 60 t cyk sampling time t samp 4.5 v av ref1 av dd 10 t cyk 3.5 v av ref1 av dd 10 t cyk zero-scale error note 1 4.5 v av ref1 av dd 1.5 3.5 lsb 3.5 v av ref1 av dd 1.5 4.5 lsb full-scale error note 1 4.5 v av ref1 av dd 1.5 2.5 lsb 3.5 v av ref1 av dd 1.5 4.5 lsb non-linearity error note 1 4.5 v av ref1 av dd 1.5 2.5 lsb 3.5 v av ref1 av dd 1.5 4.5 lsb analog input v ian ?.3 av dd + 0.3 v voltage note 2 reference voltage av ref1 3.5 av dd v av ref1 current ai ref1 1.2 3.0 ma av dd supply current ai dd 2.3 6.0 ma notes 1. except quantization error. 2. the conversion result is 000h when v ian = 0. converted with 10-bit resolution when 0 < v ian < av ref1 . the conversion result is 3ffh when av ref1 v ian av dd .
pd70f3003a, 70f3025a, 70f3003a(a) 36 data sheet u13189ej5v1ds d/a converter characteristics (t a = ?0 to +85 c, v dd = av dd = 5 v 10%, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit overall error load conditions: 2 m ? , 30 pf 0.8 % av ref2 = v dd av ref3 = 0 load conditions: 2 m ? , 30 pf 1.0 % av ref2 = 0.75 v dd av ref3 = 0.25 v dd load conditions: 4 m ? , 30 pf 0.6 % av ref2 = v dd av ref3 = 0 load conditions: 4 m ? , 30 pf 0.8 % av ref2 = 0.75 v dd av ref3 = 0.25 v dd settling time load conditions: 2 m ? , 30 pf 10 s output resistance ro 8 k ? av ref2 input voltage av ref2 0.75v dd v dd v av ref3 input voltage av ref3 0 0.25v dd v resistance between r airef dacs0, dacs1 = 55h 2 4 k ? av ref2 and av ref3
pd70f3003a, 70f3025a, 70f3003a(a) 37 data sheet u13189ej5v1ds 3.2 flash memory programming mode basic characteristics (t a = 10 to 40 c (when rewriting), t a = ?0 to +85 c (when not rewriting), v dd = av dd = 5 v 10%, v ss = av ss = 0 v)) (1) pd70f3003a (all ranks), 70f3025a (except k, e, p, x rank) parameter symbol conditions min. typ. max. unit operating frequency 10 33 mhz v pp supply voltage v pp1 during flash memory programming 9.7 10.3 10.6 v v ppl v pp low-level detection ?.5 0.2v dd v v ppm v pp , v dd level detection 0.8v dd 1.2v dd v v pph v pp high-voltage level detection 9.7 10.3 10.6 v v dd supply current i do v pp = v pp1 3.0 + 25 ma v pp supply current i pp v pp = 10.3 v 200 ma step erase time t er note 1 0.2 s overall erase time per area t era when the step erase time = 0.2 s, note 2 40 s/area write-back time t wb note 3 5ms number of write-backs per c wb when the write-back time 50 count/write- write-back command = 5 ms, note 4 back command number of erase/write-backs c erwb 16 count step writing time t wt note 5 50 s overall writing time per word t wtw when the step writing time = 50 50 500 s/word s (1 word = 4 bytes), note 6 number of rewrites per area c erwr 1 erase + 1 write after erase 20 count/area = 1 rewrite, note 7 notes 1. the recommended setting value of the step erase time is 0.2 s. 2. the prewrite time prior to erasure and the erase verify time (write-back time) are not included. 3. the recommended setting value of the step erase time is 5 ms. 4. write-back is executed once by the issuance of the write-back command. therefore, the retry count must be the maximum value minus the number of commands issued. 5. the recommended setting value of the step writing time is 50 s. 6. 100 s is added to the actual writing time per word. the internal verify time during and after the writing is not included. 7. when writing initially to shipped products, it is counted as one rewrite for both ?rase to write?and ?rite only? example (p: write, e: erase) shipped product p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites
pd70f3003a, 70f3025a, 70f3003a(a) 38 data sheet u13189ej5v1ds cautions 1. v pp pull-down resistance value (rv pp ) is recommended to be in the range 5 k ? to 15 k ? . 2. set the transfer rate between programmer and device as follows. csi0: 0.2 to 1 mhz uart0: 4,800 to 76,800 bps remarks 1. when the pg-fp3 is used, a time parameter required for writing/erasing by downloading parameter files is automatically set. do not change the settings unless otherwise specified. 2. area 0 = 00000h to 1ffffh, area 1 = 20000h to 3ffffh (area 1 is provided in the pd70f3025a only) 3. the rank is indicated by the 5th character from the left in the lot number. 4. the i rank applies to engineering samples (es) only. the operation of an es is not guaranteed. 5. : internal system clock frequency
pd70f3003a, 70f3025a, 70f3003a(a) 39 data sheet u13189ej5v1ds (2) pd70f3025a (x rank) parameter symbol conditions min. typ. max. unit operating frequency note 1 10 33 mhz v pp supply voltage v pp1 during flash memory programming 9.7 10.3 10.6 v v ppl v pp low-level detection ?.5 0.2v dd v v ppm v pp , v dd level detection 0.8v dd 1.2v dd v v pph v pp high-voltage level detection 9.7 10.3 10.6 v v dd supply current i dd v pp = v pp1 3.0 + 25 ma v pp supply current i pp v pp = 10.3 v 200 ma step erase time t er note 1 2s overall erase time per area t era when the step erase time = 2 s, note 2 40 s/area step writing time t wt note 3 200 s overall writing time per word t wtw when the step writing time = 200 200 2000 s/word s (1 word = 4 bytes), note 4 number of rewrites per area c erwr 1 erase + 1 write after erase 20 count/area = 1 rewrite, note 5 notes 1. the recommended setting value of the step erase time is 2 s. 2. the prewrite time prior to erasure and the erase verify time (write-back time) are not included. 3. the recommended setting value of the step writing time is 200 s. 4. 100 s is added to the actual writing time per word. the internal verify time during and after the writing is not included. 5. when writing initially to shipped products, it is counted as one rewrite for both ?rase to write?and ?rite only? example (p: write, e: erase) shipped product p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites cautions 1. v pp pull-down resistance value (rv pp ) is recommended to be in the range 5 k ? to 15 k ? . 2. set the transfer rate between programmer and device as follows. csi0: 0.2 to 1 mhz uart0: 4,800 to 76,800 bps remarks 1. when the pg-fp3 is used, a time parameter required for writing/erasing by downloading parameter files is automatically set. do not change the settings unless otherwise specified. 2. area 0 = 00000h to 1ffffh, area 1 = 20000h to 3ffffh 3. the rank is indicated by the 5th character from the left in the lot number. 4. the k, e, p, and x rank products do not support handshake mode. the i rank applies to engineering samples (es) only. the operation of an es is not guaranteed. 5. : internal system clock frequency
pd70f3003a, 70f3025a, 70f3003a(a) 40 data sheet u13189ej5v1ds 4. package drawing 100-pin plastic lqfp (fine pitch) (14x14) note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 16.00 0.20 14.00 0.20 0.50 (t.p.) 1.00 j 16.00 0.20 k c 14.00 0.20 i0.08 1.00 0.20 l 0.50 0.20 f1.00 n p q 0.08 1.40 0.05 0.10 0.05 s100gc-50-8eu, 8ea-2 s1 .60 max. h0.22 + 0.05 ? 0.04 m0.17 + 0.03 ? 0.07 r3 + 7 ? 3 1 25 26 50 100 76 75 51 s s n j detail of lead end c d a b r k m l p i s q g f m h
pd70f3003a, 70f3025a, 70f3003a(a) 41 data sheet u13189ej5v1ds 5. recommended soldering conditions the pd70f3003a, 70f3025a, and 70f3003a(a) should be soldered and mounted under the following recommended conditions. for technical information, see the following website. semiconductor device mount manual (http://www.necel.com/pkg/en/mount/index.html) table 5-1. surface mounting type soldering conditions (1) pd70f3003agc-33-8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd70f3025agc-33-8eu: 100-pin plastic lqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-103-3 (at 210 c or higher), count: three times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 to 72 hours) vps package peak temperature: 215 c, time: 25 to 40 seconds vp15-103-3 (at 200 c or higher), count: three times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 to 72 hours) partial heating pin temperature: 300 c max., time 3 seconds max. (per pin row) note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). remark for soldering methods and conditions other than those recommended above, consult an nec electronics sales representative. (2) pd70f3003agc-33-8eu-a: 100-pin plastic lqfp (fine pitch) (14 14) pd70f3025agc-33-8eu-a: 100-pin plastic lqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. ir60-207-3 (at 220 c or higher), count: three times or less, exposure limit: 7 days note (after that, prebake at 125 c for 20 to 72 hours) wave soldering for details,consult an nec electronics sales representative. partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). remarks 1. products with -a at the end of the part number are lead-free products. 2. for soldering methods and conditions other than those recommended above, consult an nec electronics sales representative.
pd70f3003a, 70f3025a, 70f3003a(a) 42 data sheet u13189ej5v1ds (3) pd70f3003agc(a)-33-8eu: 100-pin plastic lqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-103-2 (at 210 c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 to 72 hours) vps package peak temperature: 215 c, time: 25 to 40 seconds vp15-103-2 (at 200 c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 to 72 hours) partial heating pin temperature: 300 c max., time 3 seconds max. (per pin row) note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). remark for soldering methods and conditions other than those recommended above, consult an nec electronics sales representative.
pd70f3003a, 70f3025a, 70f3003a(a) 43 data sheet u13189ej5v1ds appendix notes on target system design the following shows a diagram of the connection conditions between the in-circuit emulator option board and conversion connector. design your system making allowances for conditions such as the form of parts mounted on the target system as shown below. target system note yqsocket100sdn (included with ie-703002-mc) can be inserted here to adjust the height (height: 3.2 mm). nqpack100sd yqpack100sd 132.24 mm note in-circuit emulator option board conversion connector ie-703003-mc-em1 side view t op view connection condition diagram in-circuit emulator ie-703002-mc yqguide target system yqpack100sd, nqpack100sd, yqguide ie-703003-mc-em1 ie-703002-mc pin 1 position 13.3 mm 24 mm 21.58 mm 15.24 mm 75 mm 31.84 mm target system nqpack100sd yqpack100sd ie-703003-mc-em1 connect to ie-703002-mc. yqguide pin 1 position
pd70f3003a, 70f3025a, 70f3003a(a) 44 data sheet u13189ej5v1ds 1 2 3 4 voltage application waveform at input pin w aveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il ( max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
pd70f3003a, 70f3025a, 70f3003a(a) 45 data sheet u13189ej5v1ds related document : pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) data sheet (u13188e) reference materials electrical characteristics for microcomputer (u15170j note ) note this document number is that of japanese version. the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such.
pd70f3003a, 70f3025a, 70f3003a(a) 46 data sheet u13189ej5v1ds regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j05.6 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa?a madrid, spain tel: 091-504 27 87 v?lizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran?aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-265 40 10 ? tyskland filial taeby, sweden tel: 08-63 87 200 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify:
pd70f3003a, 70f3025a, 70f3003a(a) the information in this document is current as of july, 2005. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec e lectronics endeavors to enhance the quality, reliability and safety of nec e lectronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "s tandard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec e lectronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec e lectronics" as used in this statement means nec e lectronics c orporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipm ent (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "s tandard": "s pecial": "s pecific":

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