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sy89230u 3.2ghz precision, lvpecl 3, 5 clock divider precision edge is a registered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com november 2007 m99 99- 110507- a hbwhelp@micrel.com or (408) 955 - 1690 general description the sy89230u is a precision, low jitter 3.2ghz 3, 5 clock divider with a lvpecl output. the differential input includes micrel?s unique, 3 - pin internal termination architecture that allows the input to inte r face to any differentia l signal (ac - or dc - coupled) as small as 100mv (200mv pp ) without any level shifting or termin a tion resistor networks in the signal path. the ou t puts are 800mv, 100k - compatible lvpecl with fast rise/fall times guaranteed to be less than 200ps. the sy89230u operates from a 2.5v 5% or 3.3v 10% supply and is guaranteed over the full industrial temper a ture range of ? 40c to +85c. the sy89230u is part of micrel?s high - speed, precision edge ? product line. all su p port documentation can be found on m i crel?s web site at: www.micrel.com . block diagram precision edge ? features ? accepts a high - speed input and provides a precision 3 and 5 sub - rate, lvpecl output ? g uaranteed ac performance over temperature and supply voltage: ? dc- to >3.2ghz throughput ? < 850ps propagation delay (in - to - q) ? < 200ps rise/fall times ? ultra - low jitter design: ? <1ps rms random jitter ? <1ps rms cycle - to - cycle jitter ? <10ps pp total ji tter (clock) ? <0.7ps rms mux crosstalk induced jitter ? unique patented internal termination and vt pin accepts dc - and ac - coupled inputs (cml, pecl, lvds) ? wide input voltage range v cc to gnd ? 800mv lvpecl output ? 45% to 55% duty cycle ( 3) ? 47% to 53% duty cy cle ( 5) ? 2.5v 5% or 3.3v 10% supply voltage ? - 40c to +85c industrial temperature range ? available in 16 - pin (3mm x 3mm) qfn package applications ? fail - safe clock protection markets ? lan/wan ? enterprise servers ? ate ? test and measurement
micrel, inc. sy89230u november 2007 m9999 - 110507-a hbwhelp@micrel.com or (408) 955 - 1690 2 ordering informatio n (1) part number package type operating range package marking lead finish sy89230umg qfn -16 indu s trial 230u with pb - free bar - line indicator nipdau pb - free sy89230umgtr (2) qfn -16 indu s trial 230u with pb - free bar - line indicator nipdau pb - free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel. pin configuration 16 - pin qfn
micrel, inc. sy89230u november 2007 m9999 - 110507-a hbwhelp@micrel.com or (408) 955 - 1690 3 pin description pin number pin name pin function 1, 4 in, /in differential input: this input pa ir is the differential signal input to the device, which accepts ac - or dc - coupled signal as small as 100mv. the input internally ter minates to a vt pin through 50 ?. note that this input pair will default to an indeterminate state if left open. see ?input interface applications? subsection for more details. 2 vt input termination center - tap: each side of the differential input pair te rminates to the vt pin. the vt pin provides a center - tap for the input (in, /in) to a termination network for maximum interface flexibility. see ?input interface applications? subsection for more details. 3 vref -ac reference voltage: this output biases to v cc ? 1.2v. it is used for ac - coupling inputs in and /in. connect vref - ac directly to the vt pin. bypass with 0.01f low esr capacitor to vcc. due to limited drive capability, the vref - ac pin is only intended to drive its respective vt pin. maximum sink/sou rce current is 0.5ma. for more details, see ?input interface applications? subsection. 5 en single - ended input: this ttl/cmos - compatible input disables and enables the output. it is internally connected to a 25k ? pull - up resistor and will default to a lo gic high state if left open. when disabled, q goes low and /q goes high. en being synchronous, outputs will be enabled/disabled after a rising and a falling edge of the input clock. v th = v cc /2. 6 /mr single - ended input: this ttl/cmos - compatible input, wh en pulled low, asynchronously sets q output low and /q output high. note that this input is internally connected to a 25k ? pull - up resistor and will default to logic high state if left open. v th = v cc /2. 7 nc no connect 8, 13 vcc positive power supply: bypass with 0.1 f in parallel with 0.01 f low esr capacitors as close to the v cc pins as possible. 12, 9 q, /q differenti al output: the lvpecl output swing is typically 800mv and is terminated with 50 ? to v cc - 2v. see the ?truth table? below for the logic function. 10, 11, 14,15 gnd, exposed pad ground: ground and exposed pad must be connected to a ground plane that is the same potential as the ground pins. 16 div_sel single - ended input: this ttl/cmos - compatible input selects divide-by - 3 when pulled low and divide - by - 5 when pulled high. note that this input is internally connected to a 25k ? pull - up resistor and will default to logic high state if left open. v th = v cc /2. truth table inputs outputs div_sel en /mr q /q x x 0 0 1 0 1 1 y 3 y 3 1 1 1 y 5 y 5 x 0 1 0 1
micrel, inc. sy89230u november 2007 m9999 - 110507-a hbwhelp@micrel.com or (408) 955 - 1690 4 absolute maximum ratings (1) supply voltage (v cc ) .......................... ? 0.5v to +4.0v input voltage (v in ) .................................. ? 0.5v to v cc lvpecl out put current (i out ) .................................... continuous ................................................. 50ma surge ........................................................ 100ma current (v t ) source or sink current on v t ????100ma input current source or sink current on (in, /in) ........... 50ma current (v ref -ac ) source/sink current on v ref -ac (4) ............ 0.5ma maximum operating junction temperat ure?..125c lead temperature (soldering, 20 sec.) .......... +260c storage temperature (t s ) .................. ? 65c to 150c operating ratings (2) supply voltage (v cc ) .................. +2.375v to +2.625v ...................................................... +3.0v to +3.6v ambient temperature (t a ) ................ ? 40c to +85c package thermal resistance (3) qfn ( ja ) still - air ..................................................... 75c/w qfn ( jb ) junction - to - board??????????.33c/w dc electrical characteristics (5) t a = ? 40c to +85c, unless otherwise stated. symbol parameter condition min typ max units v cc power supply 2.375 3.0 2.5 3.3 2.625 3.6 v v i cc p ower supply current no load, max v cc 62 85 ma r in input resistance (in -to -v t ) 45 50 55 ? r diff_in differential input resistance (in -to - /in) 90 100 110 ? v ih input high voltage (in, /in) 1.2 v cc v v il input low voltage (in, /in) 0 v ih ? 0.1 v v in input voltage swing (in, /in) see figure 2a. note 6. 0.1 v cc v v diff_in differential input voltage swing |in - /in| see figure 2b. 0.2 v v ref - ac output reference voltage v cc ? 1.3 v cc ? 1.2 v cc ? 1.1 v v t_in voltage from input to v t 1.8 v notes: 1. perm anent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and fun c tional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maxi mu m rating conditions for extended periods may affect device reliability. 2. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the pcb. ja and jb values are determined for a 4 - layer board in still air unless otherwise stated. 4. due to limited drive capability use for input of the same package only. 5. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. 6. v in (max) is specified when v t is floating.
micrel, inc. sy89230u november 2007 m9999 - 110507-a hbwhelp@micrel.com or (408) 955 - 1690 5 lvpecl outputs dc electrical characteristics (7) v cc = 2.5v 5% or 3.3v 10%; r l = 50 ? to v cc - 2v; t a = ? 40c to + 85c, unless otherwise stated. symbol parameter cond ition min typ max units v oh output high voltage q, /q v cc - 1.145 v cc - 0.895 v v ol output low voltage q, /q v cc - 1.945 v cc - 1.695 v v out output voltage swing q, /q see figure 2a. 550 800 950 mv v diff_out differential output voltage swing q, /q see figur e 2b. 1100 1600 mv lvttl/cmos dc electrical characteristics (7) v cc = 2.5v 5% or 3.3v 10%; t a = ? 40c to + 85c, unless otherwise stated. symbol parameter condition min typ max units v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current -125 30 a i il input low current -300 a note: 7. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established .
micrel, inc. sy89230u november 2007 m9999 - 110507-a hbwhelp@micrel.com or (408) 955 - 1690 6 ac electrical characteristics (8) v cc = 2.5v 5% or 3.3v 10%; r l = 50 ? to v cc - 2v; t a = ? 40c to + 85c, unless otherwise stated. symbol parameter condition min typ max units f max maximum input operating frequency v out 200mv 3.2 ghz tw minimum pulse width in, /in 140 ps t pd differential propagation delay in -to -q 450 650 850 ps /mr(h -l) -to -q 250 450 650 ps t rr reset recovery time /mr(l -h) -to -in 400 ps t s en set - up time en -to -in note 9 50 ps t h en hold time in -to -en note 9 250 ps t skew part -to - part skew note 10 300 ps t jitter clock random jitter note 11 1 ps rms cycle -to - cycle jitter note 12 1 ps rms total jitter note 13 10 ps pp t r, t f output rise/fall time (20% to 80%) at full output swing. 90 200 ps output duty cycle( 3) duty cycle(input): 50%; f 3.2ghz, note 14 46 54 % output duty cycle( 5) duty cycle(input): 50%; f 3.2ghz, note 14 47 53 % notes: 8. high - frequency ac - parameters are guaranteed by design and characterization. 9. set - up and hold times apply to synchr onous applications that intend to enable/disable before the next clock cycle. for asynchronous applications, set - up and hold do not apply. 10. part - to - part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 11. random jitter is measured with a k28.7 character pattern, measured at micrel, inc. sy89230u november 2007 m9999 - 110507-a hbwhelp@micrel.com or (408) 955 - 1690 7 functional description output duty cycle equation for a non 50% input, derate the spec by: divide by 3: (0.5 - 3 100 1 x + ) x100, in % divid e by 5: (0.5 - 5 100 2 x + ) x100, in % x = input duty cycle, in % example: if a 45% input duty cycle is applied or x=45, in divide by 3 mode, the spec would expand by 1.67% to 44.3% - 55.7% enable (en) en is a synchronous ttl/cmos - compatible in put that enables/disables the outputs based on the input to this pin. internal 25k ? sxoo - up resistor defaults the input to logic high if left open. input switching threshold is v cc /2. the enable function operates as follows: 1. the enable/disable function is synchronous so that the clock outputs will be enabled following a rising and a falling edge of the input clock when switching from en=low to en=high. however, when switching from en=high to en=low, the clock outputs will be disabled following an input clock rising edge and an output clock falling edge. 2. the enable/disable function always guarantees the full pulse width at the output before the clock outputs are disabled, non - depending on the divider ratio. refer to figure 1b for examples. divider opera tion the divider operation uses both the rising and falling edge of the input clock. for divide by 3, the falling edge of the second input clock cycle will determine the falling edge of the output. for divide by 5, the falling edge of the third input clock cycle. refer to figure 1c.
micrel, inc. sy89230u november 2007 m9999 - 110507-a hbwhelp@micrel.com or (408) 955 - 1690 8 timing diagrams figure 1a. propagation delay
micrel, inc. sy89230u november 2007 m9999 - 110507-a hbwhelp@micrel.com or (408) 955 - 1690 9 figure 1b. enable output timing diagram examples (divide by 3)
micrel, inc. sy89230u november 2007 m9999 - 110507-a hbwhelp@micrel.com or (408) 955 - 1690 10 figure 1c. divider operation timing diagram
micrel, inc. sy89230u november 2007 m9999 - 110507-a hbwhelp@micrel.com or (408) 955 - 1690 11 typical operating characteristics v cc = 3.3v, gnd = 0v, t r / t f 300ps, r l = 50 ? to v cc ? 2v; t a = 25c, unless otherwise stated. functional characteristics v cc = 2.5v, gnd = 0v, v in = 100mv, q = divide by 3, t r /t f 300ps, r l = 50 ? to v cc - 2v; t a = 25c, unless otherwise stated.
micrel, inc. sy89230u november 2007 m9999 - 110507-a hbwhelp@micrel.com or (408) 955 - 1690 12 single- ended and differential swings figure 2a. single - ended voltage swing figure 2b. differential voltage swing input and output stages figure 3a. simplified differential input stage figure 3b. simplified differential output stage
micrel, inc. sy89230u november 2007 m9999 - 110507-a hbwhelp@micrel.com or (408) 955 - 1690 13 inpu t interface applications figure 4a. lvpecl interface (dc - coupled) figure 4b. lvpecl interface (ac - coupled) option: may connect v t to v cc figure 4c. cml interface (dc - coupled) figure 4d. cml interface (ac - coupled) figure 4e. lvds interface (dc - coupled)
micrel, inc. sy89230u november 2007 m9999 - 110507-a hbwhelp@micrel.com or (408) 955 - 1690 14 pecl output interface applications pecl has a high input impedance, a very low output impedance (open emitter), and a small signal swing which results in low emi. pecl is ideal for driving 50? - and 100 ? - controlled impedance transmissio n lines. there are several techniques for terminating the pecl output: parallel termination - thevenin equivalent, parallel termination (3 - resistor), and ac - coupled termination. unused output pairs may be left floating. however, single - ended outputs must be terminated, or balanced. figure 5a. parallel termination - thevenin equivalent figure 5b. parallel termination (3 - resistor) related product and support documentation part number function datasheet link sy89228u 1ghz precision, lvpecl 3, 5 clock divider with fail - safe input and internal termination sy89229u 1ghz precision, lvds 3, 5 clock divider with fail - safe input and internal termination sy89231u 3.2ghz precision, lvds 3, 5 clock divider hbw solutions new products and appl ications www.micrel.com/product - info/products/solutions.shtml
micrel, inc. sy89230u november 2007 m9999 - 110507-a hbwhelp@micrel.com or (408) 955 - 1690 15 package information 16- pin qfn packages notes: 1. package meets level 2 moisture sensitivity classification. 2. all parts are dry - packed before shipment. 3. exposed pad must be soldered to a ground for proper thermal management. micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web h ttp:/www.micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. however, no responsibility is assumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time w ithout notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where mal function of a product can reasonably be expected to result in personal injury. life support d evices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be rea sonably expected to result in a significant injury to the user. a purchaser?s use or sale of micrel products for use in life support appliances, devices or s ystems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages res ulting from such use or sale. ? 2007 micrel, inc.

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