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hcpl-2503 single channel, high speed logic interface optocoupler data sheet features ? data rates to 250 kb/s nrz ? lsttl compatible ? high common mode transient immunity: > 1000 v/s ? 3750 vdc withstand test voltage ? open collector output ? guaranteed performance from temperature: 0 c to 70 c ? safety approval - ul recognized - 3750vrms for 1min (5000vrms for 1 min option 020 devices) per ul1577. - iec/en/din en 60747-5-2 approved - viorm = 630 vpeak for option 060 applications ? high speed logic ground isolation C lsttl-to-lsttl and ttl-to-lsttl ? high voltage isolation ? analog signal ground isolation description the hcpl-2503 optocoupler is specifed for use in lsttl- to-lsttl and ttl-to-lsttl logic interfaces. a nominal 8 ma sink current through the input led will provide enough output current for proper operation of 1 lsttl gate under worst-case conditions when used in the rec - ommended circuits. the ctr of the hcpl-2503 is 15% minimum at i f = 8 ma. the hcpl-2503 contains a light emitting diode and an in - tegrated photon detector with a 3000 vdc withstand test between input and output. separate connection for the photodiode bias and output transistor collector reduce the base-collector capacitance, giving improved speed compared with conventional phototransistor couplers. lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-free product caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. schematic - a 0.1uf bypass capacitor must be connected between 5 and 8. i f shiel d 8 6 5 gnd v cc 2 3 v o i cc v f i o anode cathode + - 7 v b i b *
2 outline drawing 1.080 0.320 (0.043 0.013) 2.54 0.25 (0.100 0.010 ) 0.51 (0.020) min . 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min . 5? typ. 0.254 + 0.076 - 0.05 1 (0.010 + 0.003) - 0.002) 7.62 0.25 (0.300 0.010) 6.35 0.2 5 (0.250 0.010) 9.65 0.25 (0.380 0.010 ) 1.78 (0.070) max. 1.19 (0.047) max. a xxxxz yyww date code dimensions in millimeters and (inches) . 5 6 7 8 4 3 2 1 option code* ul recognitio n ur type number *marking code letter for option numbers "l" = option 020 "v" = option 060 option numbers 300 and 500 not marked. note: floating lead protrusion is 0.25 mm (10 mils) max. 3.56 0.13 (0.140 0.005) 0.635 0.25 (0.025 0.010) 12 ? nom. 9.65 0.25 (0.380 0.010) 0.635 0.130 (0.025 0.005) 7.62 0.25 (0.300 0.010) 5 6 7 8 4 3 2 1 9.65 0.25 (0.380 0.010) 6.350 0.25 (0.250 0.010) 1.016 (0.040) 1.27 (0.050) 10.9 (0.430) 2.0 (0.080) land pattern recommendatio n 1.080 0.320 (0.043 0.013) 3.56 0.13 (0.140 0.005) 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc dimensions in millimeters (inches) . lead coplanarity = 0.10 mm (0.004 inches) . note: floating lead protrusion is 0.25 mm (10 mils) max. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 8-pin dip package 8-pin dip package with gull wing surface mount option 300
3 absolute maximum ratings storage temperature ........................................................................................................................................................... C55 c to +125 c operating temperature ..................................................................................................................................................... C55 c to +100 c lead solder temperature (1.6 mm below seating plane) ............................................................................................ 260 c for 10 s average input current C i f ................................................................................................................................................................ 25 ma [1] peak input current C i f (50% duty cycle, 1 ms pulse width) ................................................................................................ 50 ma [2] peak transient input current C i f (1 s pulse width, 300 pps) .................................................................................................... 1.0 a reverse input voltage C v r (pin 3-2) .......................................................................................................................................................... 5 v input power dissipation ..................................................................................................................................................................... 45 mw [3] average output current C i o (pin 6) ...................................................................................................................................................... 8 ma peak output current C i o ....................................................................................................................................................................... 16 ma emitter-base reverse voltage (pin 5-7) ..................................................................................................................................................... 5 v supply and output voltage C v cc (pin 8-5), v o (pin 6-5) .................................................................................................. C0.5 v to 7 v base current C i b (pin 7) .............................................................................................................................................................................. 5 ma output power dissipation .............................................................................................................................................................. 100 mw [4] notes: 1. derate linearly above +70?c free-air temperature at a rate of 0.8 ma/?c. 2. derate linearly above +70?c free-air temperature at a rate of 1.6 ma/?c. 3. derate linearly above +70?c free-air temperature at a rate of 0.9 mw/?c. 4. derate linearly above +70?c free-air temperature at a rate of 2.0 mw/?c. ordering information hcpl-2503 is ul recognized with 3750 vrms and 5000 vrms (option 020) for 1 minute per ul1577. all devices above listed are approved under csa component acceptance notice #5, file ca 88324. part number option package surface mount gull wing tape & reel ul 5000 vrms/1 minute rating iec/en/din en 60747-5-2 quantity rohs compliant non rohs compliant hcpl-2503 -000e no option 300mil dip-8 50 per tube -300e -300 x x 50 per tube -500e -500 x x x 1000 per reel -020e -020 x 50 per tube -320e -320 x x x 50 per tube -520e -520 x x x x 1000 per reel -060e -060 x 50 per tube -360e -360 x x x 50 per tube -560e -560 x x x x 1000 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: hcpl-2503-000e to order product of 300mil dip package with rohs compliant. example 2: hcpl-2503 to order product of 300mil dip package in tube packaging and non rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. remarks: the notation #xxx is used for existing products, while (new) products launched since 15th july 2001 and rohs compliant option will use -xxxe.
4 recommended pb-free ir profle solder refow temperature profle 0 time (seconds) temperature ( c) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec . 160 c 140 c 150 c peak temp. 245 c pea k temp. 240 c pea k temp. 230 c solderin g tim e 200 c preheating tim e 150 c, 90 + 30 sec. 2.5 c 0.5 c/sec. 3 c + 1 c/- 0.5 c tight typical loos e room temperature preheating rate 3 c + 1 c/- 0.5 c/sec. reflow heating rate 2.5 c 0.5 c/sec. note: non-halide flux should be used. 217 c ramp-do wn 6 c/sec. max. ramp-up 3 c/sec. max. 150 - 200 c 260 +0/-5 c t 25 c to peak 60 to 150 sec. 20-40 sec. time w ithin 5 c of a ctu al peak tempera ture t p t s prehea t 60 to 180 sec . t l t l t smax t smin 25 t p tim e tempera ture no tes: the time fr om 25 c to peak tempera ture = 8 minutes max. t smax = 200 c, t smin = 150 c note: non-halide flux should be used.
5 regulatory information the devices contained in this data sheet have been approved by the following organizations: ul recognized under ul 1577, component recognition program, file e55361. csa approved under csa component acceptance notice #5, file ca 88324. iec/en/din en 60747-5-2 approved under iec 60747-5-2:1997 + a1:2002 en 60747-5-2:2001 + a1:2002 din en 60747-5-2 (vde 0884 teil 2):2003-01 (hcnw and option 060 only) insulation and safety related specifcations 8-pin dip widebody (300 mil) so-8 (400 mil) parameter symbol value value value units conditions minimum external l(101) 7.1 4.9 9.6 mm measured from input terminals air gap (external to output terminals, shortest clearance) distance through air. minimum external l(102) 7.4 4.8 10.0 mm measured from input terminals tracking (external to output terminals, shortest creepage) distance path along body. minimum internal 0.08 0.08 1.0 mm through insulation distance, plastic gap conductor to conductor, usually (internal clearance) the direct distance between the photoemitter and photodetector inside the optocoupler cavity. minimum internal na na 4.0 mm measured from input terminals tracking (internal to output terminals, along creepage) internal cavity. tracking resistance cti 200 200 200 volts din iec 112/vde 0303 part 1 (comparative tracking index) isolation group iiia iiia iiia material group (din vde 0110, 1/89, table 1) option 300 - surface mount classifcation is class a in accordance with cecc 00802.
6 iec/en/din en 60747-5-2 insulation related characteristics (hcpl-2503 o ption 060 only) description symbol characteristic units installation classifcation per din vde 0110/1.89, table 1 for rated mains voltage 300 v rms i-iv for rated mains voltage 450 v rms i-iii climatic classifcation 55/100/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage v iorm 630 v peak input to output test voltage, method b* v iorm x 1.875 = v pr , 100% production test with t m = 1 sec, v pr 1181 v peak partial discharge < 5 pc input to output test voltage, method a* v iorm x 1.5 = v pr , type and sample test, v pr 945 v peak t m = 60 sec, partial discharge < 5 pc highest allowable overvoltage* (transient overvoltage, t ini = 10 sec) v iotm 6000 v peak safety limiting values (maximum values allowed in the event of a failure, also see figure 9, thermal derating curve.) case temperature t s 175 c input current i s,input 230 ma output power p s,output 600 mw insulation resistance at t s , v io = 500 v r s f10 9
7 switching specifcations at t a = 25c v cc = 5 v, i f = 8 ma, r l = 7.5 k ? unless otherwise specifed. parameter symbol min. typ. max. units test conditions fig. note propagation delay t phl 1.0 1.5 s 4,6 8 time to logic low at output propagation delay t plh 1.5 2.5 s 4,6 8 time to logic high at output common mode cm h 1000 v/s i f = 0 ma, v cm = 10 v pCp 7 7,8 transient immunity at logic high level output common mode cm l C1000 v/s v cm = 10 v pCp 7 7,8 transient immunity at logic low level output *all typicals at 25?c. electrical specifcations, lsttl-to-lsttl over recommended temperature (t a = 0?c to +70?c) unless otherwise specifed. parameter symbol min. typ.* max. units test conditions fig. note current transfer ratio ctr 15 22 % i f = 8 ma, v o = 0.5 v, 1 5 v cc = 4.5 v, t a = 25 c 11 15 % i f = 8 ma, v o = 0.5 v, v cc = 4.5 v logic low output v ol 0.2 0.5 v i f = 8 ma, i o = 0.7 ma, voltage v cc = 4.5 v logic low supply i ccl 20 a i f = 8 ma current v o = open, v cc = 5.5 v input forward voltage v f 1.5 1.7 v i f = 8 ma, t a = 25 c 2 temperature coefcient ? v f C1.6 mv/?c i f = 8 ma of forward voltage ? t a
8 switching specifcations at t a = 25c v cc = 5 v, i f = 16 ma, r l = 4.7 k ? unless otherwise specifed. parameter symbol min. typ. max. units test conditions fig. note propagation delay t phl 0.4 1.5 s 4,6 9 time to logic low at output propagation delay t plh 1.5 2.5 s 4,6 9 time to logic high at output common mode cm h 1000 v/s i f = 0 ma, v cm = 10 v pCp 7 7,9 transient immunity at logic high level output common mode cm l C1000 v/s v cm = 10 v pCp 7 7,9 transient immunity at logic low level output *all typicals at 25?c. electrical specifcations, ttl-to-lsttl over recommended temperature (t a = 0?c to +70?c) unless otherwise specifed. parameter symbol min. typ.* max. units test conditions fig. note current transfer ratio ctr 12 18 % i f = 16 ma, v o = 0.5 v, 1 5 v cc = 4.5 v, t a = 25 c 9 13 % i f = 16 ma, v o = 0.5 v, v cc = 4.5 v logic low output v ol 0.2 0.5 v i f = 16 ma, i o = 1.1 ma, voltage v cc = 4.5 v logic low supply i ccl 40 a i f = 16 ma current v o = open, v cc = 5.5 v input forward v f 1.5 1.7 v i f = 16 ma, t a = 25 c 2 voltage temperature ? v f C1.6 mv/?c i f = 16 ma coefcient of forward ? t a voltage
9 electrical specifcations over recommended temperature (t a = 0?c to +70?c) unless otherwise specifed. parameter symbol min. typ.* max. units test conditions fig. note logic high i oh 0.5 na t a = 25 c, i f = 0 ma 5 output current v o = v cc = 5.5 v 50 a i f = 0 ma v o = v cc = 5.5 v logic high i cch 0.05 4 a i f = 0 ma supply current v o = open, v cc = 5.5 v input reverse v r 5 v i f = 10 a, t a = 25 c breakdown voltage input capacitance c in 60 pf f = 1 mhz, v f = 0 v input-output i iCo 1.0 a 45% relative humidity, 6 insulation leakage t = 5s, v iCo = 3000 vdc, current t a = 25 c resistance r iCo 10 12 ? v iCo = 500 vdc 6 (inputCoutput) capacitance c iCo 0.6 pf f = 1 mhz 6 (inputCoutput) *all typicals at 25?c. notes: 5. current transfer ratio is defned as the ratio of output collector current, i/o, to the forward led input current, i f , times 100%. 6. device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 7. common mode transient immunity in logic high level is the maximum tolerable (positive) dv cm /dt on the leading edge of the common mode pulse v cm , to assure that the output will remain in a logic high state (i.e., v o > 2.0 v). common mode transient immunity in logic low level is the maximum tolerable (negative) dv cm /dt on the trailing edge of the common mode pulse signal, v cm , to assure that the output will remain in a logic low state (i.e., v o < 0.8 v). 8. the 7.5 k load represents 1 lsttl until load of 0.36 ma and a 20 k pull-up resistor. 9. the 4.7 k load represents 1 lsttl unit load of 0.36 ma and an 8.2 k pull-up resistor.
10 figure 2. input current vs. forward voltage figure 1. current transfer ratio vs. input current figure 3. current transfer ratio vs. temperature figure 5. logic high output current vs. temperature figure 4. propagation delay vs. temperature figure 6. switching test circuit hcpl-2503 fig 2 v f ? forward voltage ? volts 100 10 0.1 0.01 1.10 1.20 1.30 1.40 i f ? forward current ? ma 1.50 1.0 0.001 1000 i f v f + t a = 25c ? hcpl-2503 fig 3 1.2 0.8 0.6 0.2 0 -60 -20 normalized current transfer ratio t a ? temperature ? c -40 20 40 80 100 v o = 0.5 v v cc = 5.0 v 1.0 0.4 i f = 8 ma i f = 16 ma normalized to t a = 25c 0 6 0 hcpl-2503 fig 4 2.0 1.0 0 -60 -20 t p ? propagation delay ? s t a ? temperature ? c -40 20 40 80 100 i f = 8 ma r l = 7.5 k ? 1.5 0.5 0 6 0 i f = 16 ma r l = 4.7 k ? v cc = 5.0 v t phl t pl h hcpl-2503 fig 5 10 1 0 3 0 i oh ? output current ? na t a ? temperature ? c 10 50 70 100 110 100 40 80 20 60 90 hcpl-2503 fig 6 v o hp 8007 pulse gen. z o = 50 ? t r = 5 ns i f monitor i f r l c l = 15 pf 100 ? 0 t phl t pl h v o i f v ol 1.3 v 1.3 v 5 v +5 v 10% duty cycle 1/f 500 s 8 1 7 2 6 3 5 4 hcpl-2503 fig 1 1.4 1.2 0.8 0.6 0.2 0 0 8 normalized current transfer ratio i f ? input current ? ma 4 1 2 1 6 2 0 2 4 v o = 0.5 v v cc = 5.0 v t a = 25c normalized to i f = 8 ma i f = 16 ma 1.0 0.4
figure 7. test circuit for transient immunity and typical waveforms figure 8. recommended circuits recommended operation the hcpl-2503 optocoupler is specifed for use in lsttl- to-lsttl and ttl-to-lsttl interfaces. the recommended circuits show the interface design and give suggested component values. the input current i f is given as both a nominal value and a range. the range in i f results from the tolerances in v cc and the input resistor r in . the ctr of the optocoupler is given as the minimum hcpl-2503 fig 8 i o r in r l 8 1 7 2 6 3 5 4 v cc2 v cc1 i f hcpl-2503 7404 74ls04 7405 74ls05 74ls04 74ls05 a b a) typical non-inverting circuit i o r in r l 8 1 7 2 6 3 5 4 v cc2 v cc1 i f hcpl-2503 7405 74ls05 74ls04 74ls05 a b b) typical inverting circuit (see note 10) hcpl-2503 fig 7 v o i f r l a hp 8007 pulse gen. v cm + v ff v o v ol v o 0 v 10% 90% 10% 90% switch at a: i = 0 ma f switch at b: i = 16 ma f v cm t r t f 5 v +5 v ? 10 v t r , t f = 8 ns 8 1 7 2 6 3 5 4 b initial value over temperature, taken directly from the electrical specifcations. the value given for i ol (min) is based on the minimum ctr and the minimum i f using worst case values for r l and v cc . the resulting i ol (min) has ample design margin, allowing more than 20% for ctr degradation even under these worst case condi - tions. for additional information on ctr degradation see application note 1002 .
recommended circuit design parameters lsttl-to- ttl-to- parameter symbol lsttl lsttl units comments fig. note input logic low output v ol (a) 0.5 0.4 v maximum voltage C input gate supply voltage C input v cc1 5.0 5.0 v 5% input resistor r in 360 180 ? 5% 8a 430 200 8b input current i f 8 16 ma nominal input current range i f 6.75C10 14.0C20 ma 8a 14.5C20 8b output logic low output v ol (b) 0.5 0.5 v maximum voltage C hcpl-2503 supply voltage C output v cc2 5.0 5.0 v 5% pull-up resistor r l 20 8.2 k ? 5% 11 required current sink i ol 0.61 1.0 ma worst case v cc , 12 for logic low (max) r l , i il (b) hcpl-2503 current ctr 11 9 % minimum t a = 0?c to transfer ratio +70 c logic low output i ol 0.74 1.26 ma worst case v cc , ctr, i f 8a 13 current C hcpl-2503 (min) 1.30 t a = 0 c to +70 c 8b data rate f d 250 250 kb/s nrz, t a = 25 c 14 for product information and a complete list of distributors, please go to our website: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies limited in the united states and other countries. data subject to change. copyright ? 2007 avago technologies limited. all rights reserved. av02-0520en - june 15, 2007 notes: 10. the inverting circuit has higher power consumption and must use open collector gates on the input. 11. the load resistor r l must be large enough to guarantee logic low and small enough to guarantee logic high under worst case conditions: v cc (max) C v ol v cc (min) C v ih (b) i ol (2503) C i il (b) i oh (2503) C i ih (b) the selection of r l is the same for both inverting and non-inverting circuits. 12. the maximum current sink required for logic low is: i ol (max) = i il (b) (max) + i r (max) where i r is the current through r l . 13. the ratio of i ol (min) to i ol (max) gives the design margin for ctr degradation. see application note 1002. 14. the maximum data rate is defned as: 1 f d = bits/second nrz t phl + t plh r l

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