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product information full information about other arcom products is available via the f f a a x x - - o o n n - - d d e e m m a a n n d d s s y y s s t t e e m m , (telephone numbers are listed below), or by contacting our w w e e b b s s i i t t e e in the uk at: w w w w w w . . a a r r c c o o m m . . c c o o . . u u k k or in the us at: w w w w w w . . a a r r c c o o m m c c o o n n t t r r o o l l s s . . c c o o m m u u s s e e f f u u l l c c o o n n t t a a c c t t i i n n f f o o r r m m a a t t i i o o n n c c u u s s t t o o m m e e r r s s u u p p p p o o r r t t s s a a l l e e s s tel: +44 (0)1223 412 428 tel: +44 (0)1223 411 200 fax: +44 (0)1223 403 400 fax: +44 (0)1223 410 457 e-mail: support@arcom.co.uk e-mail sales@arcom.co.uk or for the us e-mail icpsales@arcomcontrols.com page 1 2192-09061-000-000 j489 pcadadio pcadadio multi-function digital/analogue i/o board technical manual u u n n i i t t e e d d k k i i n n g g d d o o m m arcom control systems ltd clifton road cambridge cb1 4wh, uk tel: 01223 411 200 fax: 01223 410 457 fod: 01223 240 600 u u n n i i t t e e d d s s t t a a t t e e s s arcom control systems inc 13510 south oak street kansas city mo 64145 usa tel: 816 941 7025 fax: 816 941 0343 fod: 800 747 1097 f f r r a a n n c c e e arcom control systems centre d?affaires scaldy 23 rue colbert 7885 saint quentin cedex, france tel: 800 90 84 06 fax: 800 90 84 12 fod: 800 90 23 80 g g e e r r m m a a n n y y kostenlose infoline: tel: 0130 824 511 fax: 0130 824 512 fod: 0130 860 449 i i t t a a l l y y numeroverde: fod: 1678 73600 b b e e l l g g i i u u m m groen nummer: tel: 0800 7 3192 fax: 0800 7 3191 n n e e t t h h e e r r l l a a n n d d s s gratis 06 nummer: tel: 06022 11 36 fax: 06022 11 48 the choice of boards or systems is the responsibility of the buyer, and the use to which they are put cannot be the liability of arcom control systems ltd. however, arcom?s sales team is always available to assist you in making your decision. ? 1996 arcom control systems ltd arcom control systems is a subsidiary of fairey group plc. specifications are subject to change without notice and do not form part of any contract. all trademarks recognised. arcom control systems ltd operate a company-wide quality management system which has been certified by the british standards institution (bsi) as compliant with iso9001:1994
manual pcb comments issue a issue b v1 iss 2 v1 iss 2 960731 first released in this format. 9801 15 eco2684. preface packing list this product is shipped as follows: ? board ? user manual ? utility disk if any of the above appear to be missing, please telephone arcom 01223 41 1200. throughout this document / denotes that a signal is active low . all address and data values are in hexadecimal. utility disk this product is shipped with a utility disk which contains: ? pcbus library ? source code (written in 'c') and sample executable files to aid in calibrating the board ? also supplied is a programming resistor which is required for the 0-5v range of the adc handling (esd/packaging) this board contains cmos devices which could be damaged in the event of static electricity being discharged through them. at all times please observe anti-static precautions when handling the board and always unpack and install the board in an anti-static working area. please ensure that should a board need to be returned to arcom, it is adequately packed and if a battery is fitted, that it is isolated. page 2 2192-09061-000-000 j489 pcadadio revision history
page 3 2192-09061-000-000 j489 pcadadio preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 packing list, utility disk, handling (esd/packaging) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 reading from or w riting to the board, base address selection, the i/o pointer scheme . . . . . . . 6 pointer v alue & register function, installing multiple pcadadios . . . . . . . . . . . . . . . . . . . . . . . 7 adc sequence, dac sequence, digital i/os, counter/t imers . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 adc t riggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 links and options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 default link position diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 board functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 user configuration record sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 calibrating the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 calibrating the dacs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 utility disk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 installation for ce compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 circuit diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 contents
page 4 2192-09061-000-000 j489 pcadadio
page 5 2192-09061-000-000 j489 pcadadio introduction the pcadadio is a low-cost, multi-purpose i/o board for pc-compatibles. it has eight dif ferential (pcadadiocd) or 16 single-ended (pcadadiocs) multiplexed analogue inputs, two analogue outputs, 16 digital i/os and three counter-timer channels. the operation of each of these functions is controlled using the pc xt bus and link options. features ? ce compliant design ? 8 dif ferential or 16 single-ended, multiplexed 12-bit adc channels ? 10khz channel-to-channel acquisition rate (buf fered input) ? 100khz repeat rate (back-to-back single channel conversion) ? 10 m s typical conversion rate ? 5v , 10v , 0-5v , 0-10v selectable input ranges ? t wo 12-bit (1-bit accuracy) analogue output channels ? 5v , 0-5v , 0-10v channel-by-channel selectable output ranges ? 10 m s settling time to 12-bit accuracy ? intel 8254-compatible 3-channel counter-timer ? 1 adc timer , 1 interrupt timer , 1 general-purpose timer ? 1mhz master operating frequency ? 16 ttl nibble-configurable digital i/o lines ? input: 1k pulled to 0.8v resistor input low ? output: 24ma at 0-45v , sources from 1k resistor at +5v ? selectable power-up states ? compact i/o addressing scheme (4 bytes) ? 8-bit isa bus interface ? board access user leds: id byte = 2dh ? i/o connector conforms to arcom signal conditioning system (scs) ? operating temperature range, 0 c to +55 c ? power required: 5v @ 330ma (5%) typical, +12v @ 200ma (10%) typical ? mtbf: 172,706 hours (using generic figures from mil-hdbk-217f at ground benign) ? dimensions: 289 x 120 x 25mm ? w eight: 266g getting started ? switch of f pc ? install board in supplied configuration ? switch on pc and observe the leds while it powers up. y ou may see the red led flash once. this simply means that the bios start-up program in your pc is checking through i/o space to see if any boards are there. it is nothing to worry about. on the other hand, if your pc fails to boot or the red led flashes continuously , you will need to change the pcadadio base address. ? run examp-01 (utility disk) ? the green user led should flash the utility disk supplied with pcadadio contains example software to help get you started. pcadadio.exe will run with the standard link settings and displays the adc inputs, scrolls an active bit along the digital i/o and allows setting of the dacs. decrementing ctc data and incrementing interrupt counts are also shown. in order for these to run, it is necessary to add a link to lk2a between pins 9 and 10 on pl3.
page 6 2192-09061-000-000 j489 pcadadio operation reading from or w riting to the board control of the pcadadio is achieved by writing to a pointer register and then accessing a data register to read or write the required function. the pointer register need only be written with a new value if a dif ferent data register is next to be accessed. adc and dac data is handled by a dedicated pair of registers. the board occupies only four bytes of pcbus i/o space. each time the board is accessed, the red led will flash momentarily . base address selection the switches set the address of the lowest of the four bytes of the board control registers (the base address) and the three remaining bytes occupy sequential addresses above this location in pcbus i/o space. therefore, the base address must be set-up on four byte boundaries, i.e sw3 should be set to 0, 4, 8 or c. the address switches should be set to read from left to right (sw1 to sw3) to correspond with the hex switches. for example for address 180hex (the deepest pcbus i/o base address) sw1 is set to 1, sw2 to 8 and sw3 to 0. the i/o pointer scheme t o access a function on the pcadadio, you must set-up the pointer register to point to it. this is achieved by writing a pointer value byte to the i/o base address. once a particular device is pointed at, it can be accessed by writing/reading the relevant access register . the pointer value need not be re-written for every access to the same access register . all control and diagnostic functions, including adc control, are accessed using the byte (8 bit) access register located at base +1. the adc and dac data are accessed using the low and high access registers located at base + 2 and base + 3. this feature can be used to optimise data acquisition using software word access, since this results in two contiguous bus cycles (base + 2 followed by base + 3). there is no need to write a new pointer value before access is made to read adc data. i/o address function read/w rite base base + 1 base + 2 base + 3 pointer register diagnostic and control access byte dac and adc low access byte dac and adc high access byte w rite only read/w rite read/w rite read/w rite
page 7 2192-09061-000-000 j489 pcadadio pointer v alues and register function installing multiple pcadadios this is just like installing a single pcadadio, except that each must be installed at a dif ferent address. the base address must be set in 4-byte boundaries. pointer v alue (hex) read/w rite function register name 00 00 00 00 00 01 02 02 03 03 04 05 06 07 08 09 0a 0b 0c-7f 80 81 read base +1 read base +1 w rite base +1 read base +2 read base +3 w rite base +1 w rite base +2 w rite base +3 w rite base +2 w rite base +3 r/w base +1 r/w base +1 r/w base +1 r/w base +1 w rite base +1 w rite base +1 r/w base +1 r/w base +1 w rite base +1 read base +1 status flag - adc status flag - ctc adc start conversion adc data - low byte adc data - high byte multiplexer channel select daca register daca register dacb register dacb register ctc counter a ctc counter b ctc counter c ctc counter control w ord clear ctc ready digital i/o configuration digital i/o group 2 digital i/o group 3 not used user led board id data bit function 0 1 4-7 0-7 0-3 4-7 0-7 4-7 0-7 0-7 0-7 0-7 0-7 0-3 0-7 0-7 0 0-7 adc ready 0 = conversion completed since last read of adc data - high byte counter-t imer ready 0 = outb has transitioned low-high since clear ctc ready last accessed w riting any data starts conversion ad0-3 adc data from last conversion ad4-1 1 adc data from last conversion multiplexer channel address 0-15 for pcadadiocs 0-7 for pcadadiocd da0-3 daca low data da4-1 1 daca high data db0-3 dacb low data db4-1 1 dacb high data see intel 8254 data sheet see intel 8254 data sheet see intel 8254 data sheet see intel 8254 data sheet w riting any data sets status flag - ctc to 1 and clears ctc interrupt (if enabled) nben0-3 0 = nibble configured as output 1 = nibble configured as input pl7 digital i/o dig0-7 pl7 digital i/o dig8-15 green user led control 0 = led of f 1 = led on reads as 2dh
page 8 2192-09061-000-000 j489 pcadadio adc sequence the pcadadio is shipped calibrated for the 5v range, and requires re-calibration if used on other ranges. the adc may be triggered from three alternative sources, selected by a jumper: ? software trigger , from writing the register ? hardware trigger , from an external ttl input, approximately 1-2 m sec low pulse ? periodic timer , programmed from the on-board ctc in the second two cases an interrupt should be used to signal that a new value is ready . w ith a software trigger all timing can be done from the program using this sequence: ? select channel register and write channel value ? delay for input settling (about 50 m sec) ? select software trigger register and write to trigger (value not defined) ? delay for adc conversion (about 20 m sec) ? select status register and read to check that new value is ready ? read adc data registers dac sequence before writing a 12-bit dac value to the data registers at base + 2 and base + 3, the dac channel must be selected. w rite value 02 to the pointer register for dac a and value 03 for dac b. digital i/os the direction of individual nibbles can be switched by writing to the digital configuration register . access to the individual outputs and inputs is via the digital i/o group 2 and 3 registers. if a nibble is configured as an input a write to the output register will have no ef fect on the input, unless the state of the configuration register is changed to an output. in this case the last value written to the nibble will be transferred to the output. it is therefore important to ensure that the correct value is written to the output register before switching from an input to an output. counter/t imers the pcadadio contains three 16-bit counter/timers in an intel 8254-compatible counter t imer chip (ctc). t o of fer maximum flexibility , the pcadadio has a 10-way connector (pl3) with the facility to link the inputs to external and internal clock sources including the outputs of other counter/timer channels. additionally , channel a can be used to start adc conversion and channel b to generate interrupts on irq2 or 3 when links lk10 and lk4 are selected respectively . counter a should always be programmed in mode 2 which ensures that out a is only active for a single clock cycle (i.e.1 m s when connected to the 1mhz clock). when outc is connected to clka, the time between rising edges on outc must not exceed 6 m s or be less than 250ns. before connecting any inputs to the digital i/os, check that the links (lk12-15) which control the reset state of the individual nibbles are correctly configured as inputs, otherwise damage may occur , either to the pcadadio or external equipment.
page 9 2192-09061-000-000 j489 pcadadio adc t riggering the counter/timer trigger uses channel a and the hardware strobe the /rconv pin on pl1. conversion is started from these sources when out a signal or /rconv are low . t o ensure that the adc does not perform multiple conversions it must be ensured that hardware and ctc trigger pulses are greater than 250ns, but less than 6 m s. maximum data throughput can be obtained by triggering a new conversion before data from the last conversion is read and processed. t o ensure that the adc data registers contain data from the last conversion they must be read within 6 m s of triggering a new conversion. 6 m s max 250ns min /rconv or out a
page 10 2192-09061-000-000 j489 pcadadio links & options default link position diagram lk7 lk3 lk1 b a b a b a b a b a b a b a a b a b a b a b b a lk8 lk12 default link lk17 pl2 pl3 pl1 lk16 lk14 lk15 lk2 lk5 lk6 lk4 lk13 lk9 lk10 lk1 1 a b sw1 sw2 sw3 1 8 0
page 11 2192-09061-000-000 j489 pcadadio board functions throughout this section + indicates a factory set default link. link lk1: pseudo differential ground connection link lk2: adc interrupt selection link lk2 selects an interrupt source for the adc which generates an interrupt signal after conversion is complete and indicates adc data is ready for reading: adc conversion compete is also indicated by the status flag register , whether or not a link is fitted. link lk3: differential/single-ended input selection link lk4: counter/t imer interrupt selection link lk4 selects an interrupt source for the counter/timer channel b. an interrupt will be generated whenever the outb pin of the counter/timer (8254) strobes low to high. ctc outb strobing high is also indicated by the status flag register , whether or not a link is fitted. links lk5, lk6: dac output range links lk5 and lk6 selects the output range for dac1 and dac0 respectively . the range settings are as below: links lk7, lk8 and r15: adc input ranges links lk7, lk8 and r15 select the input range to the adc. the range settings are as below: fit pcadadiocs. fit only if inputs are isolated from 0v a omit pcadadiocd, dif ferential inputs lk2a sends an interrupt at conversion complete to irq2 lk2b sends an interrupt at conversion complete to irq3 a pcadadiocd b pcadadiocs lk4a sends an interrupt to the counter/timer outb to irq2 lk4b sends an interrupt from the counter/timer outb to irq3 + lka -5v to +5v lkb 0v to 5v none 0v to 10v lk7 range lk8 r15 +a -5v to +5v +a +omit a 0v to +10v b omit b -10v to +10v a omit a 0v to +5v b 49.9k under no circumstances should both links be fitted to position b
page 12 2192-09061-000-000 j489 pcadadio link lk9, lk10 and lk1 1: adc t rigger sources these three links enable the three dif ferent adc trigger sources. each trigger source is enabled when a link is fitted. links lk12, lk13, lk14, lk15: digital i/o reset state thee links select the state of the digital i/o lines at reset in nibble (4 bit) groups. lk15 digital i/o lines dig0-3 lk14 digital i/o lines dig4-7 lk13 digital i/o lines dig8-1 1 lk12 digital i/o lines dig12-15 link lk16: counter/t imer channel a clock source link lk16 selects the clock source for counter/timer channel a link lk17: digital i/o reset t est link used for automated board testing of the digital i/os, to ensure they reset into the correct states and should be left in position a. +lk9 fitted enable software triggering lk10 fitted enable hardware triggering lk1 1 fitted enable counter/timer channel a triggering lkxxxa fitted sets the nibble low + lkxxxb fitted sets the nibble high lk16a clocked by the output of counter/timer channel c output + lk16b 1mhz clock please note that only one link should be fitted for reliable operation reset high should be used when the digital i/os are to be used as inputs, otherwise the lines will be driven low as outputs which may cause damage. the link associated with each nibble is shown below .
page 13 2192-09061-000-000 j489 pcadadio user configuration record sheet this sheet may be duplicated pseudo dif ferential ground lk1 adc interrupt lk2 counter/t imer channel a clock lk16 digital i/o reset t est lk17 dif ferential single-ended input lk1 counter/t imer interrupt lk2 dac output lk5 lk6 adc input lk7 lk8 adc t rigger sources lk9 lk10 lk1 1 digital i/o reset state lk12 lk13 lk14 lk15 sw1 sw2 sw3 lk1 pl2 pl3 pl1 lk7 lk3 b a b a b a b a b a b a b a a b a b a b a b b a lk8 lk12 lk17 lk16 lk14 lk15 sw1 sw2 sw3 lk2 lk5 lk6 lk4 lk13 lk9 lk10 lk1 1 a b links base address switches
page 14 2192-09061-000-000 j489 pcadadio calibration calibrating the adc in order to calibrate the adc it is necessary to have a precision digital voltmeter (dvm) with at least 5 digit resolution and a high stability low noise dc signal source. t o monitor adjustments, it is necessary to continually read and display the adc data. there is a program on the utility disk which provides this facility , pcadadio.exe. t wo trim adjusters, vr7 and vr1, are provided for trimming the zero of fset and gain respectively . these trims are for fine-adjusting the standard ranges. unipolar calibration set the necessary links for unipolar mode and the required voltage range. run the screen display software. zero offset adjust 1) set the input voltage to exactly zero. 2) adjust vr7 to give 000 to 001 hex. full scale gain adjust 1) set the input voltage to full scale positive minus 1 lsb:- +4.9985 for the 5v range. +9.9975 for the 10v range. 2) adjust vr1 to give ffe to fff . bipolar calibration set the necessary links for bipolar mode and the required voltage range. run the screen display software. bipolar offset adjust 1) set the input voltage to full scale negative plus 1 lsb:- -4.9975 for the 5v range. -9.995 for the 10v range. 2) adjust vr7 to give 000 to 001 hex. full scale gain adjust 1) set the input voltage to full scale positive minus 1 lsb:- +4.9975 for the 5v range. +9.995 for the 10v range. 2) adjust vr1 to give ffe to fff .
page 15 2192-09061-000-000 j489 pcadadio calibrating the dacs in order to calibrate the dacs it is necessary to have a dvm with at least 5 digit resolution. on the demonstration disk there is a facility useful for calibrating the dacs. this allows each dac to be set to the required value for calibration. a single trim (vr2) is provided to trim the reference voltage used by the dacs. additionally , two trimmers are provided for adjusting the zero of fset and gain of each dac channel. vr5 and vr3 trim the zero of fset and gain of dac channel a and vr6 and vr4 dac channel b respectively . these trims are for fine adjust only within standard ranges. set the necessary links for the required mode and voltage ranges. run the screen display software. put the dvm on the agnd and vref test point and adjust vr2 to read 5.02v . unipolar calibration for dac channel a. zero offset adjust 1) set dac a output to 000 hex. 2) measure between the dac a output on pl1 and analogue ground and adjust vr5 to give 0.000v . full scale gain adjust 1) set the dac a output to 800 hex. 2) measure between the dac a output on pl1 and adjust vr3 to exactly give half scale output (2.500v for the 0v to 5v output and 5.000v for the 0v to 10v output). 3) set dac a to fff hex and check full scale is:- 9.9975 for 0v to 10v range. 4.9985 for the 0v to 5v range. 4) adjust vr3 if necessary . repeat for dac channel b replacing vr5 with vr6, and vr3 with vr4. bipolar calibration for dac channel a. zero offset adjust 1) set dac a output to 000 hex. 2) measure between the dac a output on pl1 and analogue ground and adjust vr5 to give full scale negative i.e. -5.000v . full scale gain adjust 1) set the dac a output to 800 hex. 2) measure between the dac a output on pl1 and adjust vr3 to give half scale output 0.000v . 3) set dac a to fff hex and check full scale is 4.9975v . repeat for dac channel b replacing vr5 and vr6, and vr3 and vr4. note: if the gain adjust trimmers (vr3 & 4) have insufficient range, adjust vr2 to read 5.01v and repeat the calibration procedure.
page 16 2192-09061-000-000 j489 pcadadio utility disk a utility disk containing example software is supplied with the pcadadio to help you get started. readme.txt file the file readme.txt is the first one you should look at. it contains up-to-date information on the whole disk. pcadadio.ini the demonstration program uses a file (pcadadio.ini) which allows the user to initialise the base address, adc and dac ranges, etc. this file may be edited to reflect changes in the board settings. pcadadio.exe this program displays the adc inputs, scrolls an active bit along the digital i/o and allows setting of the dacs. these will all run with the standard link settings. decrementing ctc data and incrementing interrupt counts are also shown. in order for these to run, it is necessary to add a link to lk2a between pins 9 and 10 on pl3 as shown. 10 8 6 4 2 9 7 5 3 1
page 17 2192-09061-000-000 j489 pcadadio connectors pl1. front panel 50-way d-type the pcadadio has two user connectors pl1 and pl3. pl2 is the edge connector on the pcb used to connect to the pc bus. pl1 is located on the board front panel and the pinout is compatible with the arcom signal conditioning system (scs). for this reason the pinout is listed both for the 50-way d-type and a 50-way ribbon cable. the pin locations for these connectors are shown below: ribbon cable no. d-50 pin no. signal t itle 1 1 34 3 2 4 5 6 7 8 9 10 1 1 12 13 14 15 18 2 35 19 3 36 20 4 37 21 5 38 22 0v a pdiff ch0+ ch0-/ch8+ ch1+ ch1-/ch9+ ch2+ ch2-/ch10+ ch3+ ch3-/ch1 1+ 0v a pdiff ch4+ ch4-/ch12+ ch5+ 16 6 ch5-/ch13+ 17 39 ch6+ 18 23 ch6-/ch14+ 19 7 ch7+ 20 40 ch7-/ch15+ 21 24 gnd 22 8 pdiff 23 41 dig0 24 25 dig1 25 9 dig2 26 42 dig3 27 26 10 43 27 1 1 44 28 12 45 29 13 46 30 39 38 37 36 35 34 33 32 31 30 29 28 dig4 dig5 dig6 dig7 gnd dig8 dig9 dig10 dig1 1 dig12 dig13 dig14 14 40 dig15 47 41 0v a 31 42 reserved 15 43 dac0 48 44 dac1 32 45 not used 16 46 not used 49 47 -12v 33 48 +12v 17 49 +5v 50 50 -5v not used
page 18 2192-09061-000-000 j489 pcadadio pl3. 10-way idc header pl3 is used for connecting external signals to buf fered versions of the ctc inputs and outputs for channels b and c. for maximum flexibility the connections have been arranged to allow clock inputs to be linked to the standard 1mhz clock or other channel outputs using jumper links. the pinout of the 10-way header and connections are shown below: 10 8 6 4 2 bclkb boutc bga tec bclk1m +5v 9 7 5 3 1 bclk1m bga teb boutb bclkc gnd
page 19 2192-09061-000-000 j489 pcadadio installation for ce compliance t o maintain compliance with the requirements of the emc directive (89/336/eec), this product must be correctly installed. the pc in which the board is housed must be ce compliant as declared by the pc manufacturer . the external i/o cable should be the arcom cab50ce, or a fully screened cable to the same pattern. 1. remove the cover of the pc observing any additional instructions of the pc manufacturer 2. locate the board in a spare isa slot and press gently but firmly into place 3. ensure that the metal bracket attached to the board is fully seated 4. fit the bracket clamping screw and firmly tighten this on the bracket note: good contact of the bracket to chassis is essential 5. fit the screened i/o cable to the 50-way board connector 6. ensure that the jack screws for the cable connector are tightened (use a screw driver) 7. replace the cover of the pc observing any additional instructions of the pc manufacturer the following standards have been applied to this product: bs en50081-1: 1992 generic emissions standard, residential, commercial, light industry bs en50082-1: 1992 generic immunity standard, residential, commercial, light industry bs en55022 : 1995 ite emissions, class b, limits and methods
page 20 2192-09061-000-000 j489 pcadadio reference t est point locations tp1 tp4 tp3 tp2 tp9 tp7 tp8 tp13 tp14 tp15 tp12 tp1 1 tp10 tp5 tp6 description t est point pcbus irq2 tp1 dac v oltage reference tp2 +5v analogue tp3 pcbus irq3 tp4 analogue + supply (approx. 15v) tp5 analogue - supply (approx. -15v) tp6 adc chip enable tp7 adc status line tp8 analogue ground tp9 digital ground tp10 buf fered reset active low tp1 1 i/o address match tp12 +5v digital tp13 device w rite active low tp14 device read active low tp15
page 21 2192-09061-000-000 j489 pcadadio t rimmer locations function t rimmer adc gain vr1 dac reference v oltage vr2 dac ch a gain vr3 dac ch b gain vr4 dac ch a zero of fset vr5 dac ch b zero of fset vr6 adc zero of fset vr7 vr1 vr2 vr3 vr4 vr5 vr6 vr7
page 22 2192-09061-000-000 j489 pcadadio circuit diagrams
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