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1 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b mx29lv320d t/b datasheet
2 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b contents features ............................................................................................................................................................. 5 general description ..................................................................................................................................... 6 pin configuration ........................................................................................................................................... 7 pin description ................................................................................................................................................. 8 block diagram .................................................................................................................................................. 9 block diagram description ...................................................................................................................... 1 0 block structure ........................................................................................................................................... 1 1 table 1.a: mx29lv320dt sector group architecture ................................................................ 1 1 table 1.b: mx29lv320db sector group architecture ............................................................... 1 3 bus operation ................................................................................................................................................. 1 5 table 2-1. bus operation ...................................................................................................................... 1 5 table 2-2. bus operation ...................................................................................................................... 1 6 functional operation description ....................................................................................................... 1 7 read operation .................................................................................................................................... 1 7 write operation ................................................................................................................................... 1 7 device reset .......................................................................................................................................... 1 7 standby mode ........................................................................................................................................ 1 7 output disable ..................................................................................................................................... 1 7 byte/word selection ......................................................................................................................... 1 8 hardware write protect ................................................................................................................. 1 8 accelerated programming operation ...................................................................................... 1 8 temporary sector group unprotect operation ................................................................. 1 8 sector group protect operation ............................................................................................... 1 8 chip unprotect operation ............................................................................................................... 1 9 automatic select bus operations ................................................................................................ 1 9 sector lock status verification .................................................................................................. 1 9 read silicon id manufacturer code ............................................................................................ 1 9 read silicon id mx29lv320dt code .................................................................................................. 1 9 read silicon id mx29lv320db code ................................................................................................. 1 9 read indicator bit (q7) for security sector ........................................................................... 2 0 inherent data protection ................................................................................................................ 2 0 command completion ......................................................................................................................... 2 0 low vcc write inhibit ......................................................................................................................... 2 0 write pulse "glitch" protection ................................................................................................... 2 0 logical inhibit ....................................................................................................................................... 2 0 power-up sequence ........................................................................................................................... 2 0 power-up write inhibit ...................................................................................................................... 2 1 power supply decoupling ............................................................................................................... 2 1
3 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b command operations ................................................................................................................................... 2 2 table 3. mx29lv320d t/b command definitions ............................................................................ 2 2 automatic programming of the memory array ...................................................................... 2 3 sector erase ........................................................................................................................................ 2 4 chip erase .............................................................................................................................................. 2 5 sector erase suspend ...................................................................................................................... 2 5 sector erase resume ........................................................................................................................ 2 6 automatic select operations ........................................................................................................ 2 6 automatic select command sequence ....................................................................................... 2 6 read manufacturer id or device id ............................................................................................. 2 7 security sector lock status ......................................................................................................... 2 7 verify sector group protection ................................................................................................. 2 7 security sector flash memory region ..................................................................................... 2 7 factory locked: security sector programmed and protected at the factory .... 2 7 factory locked: security sector programmed and protected at the factory .... 2 8 customer lockable: security sector not programmed or protected at the factory .................................................................................................................................................... 2 8 enter and exit security sector .................................................................................................... 2 8 reset operation .................................................................................................................................. 2 9 common flash memory interface (cfi) mode ..................................................................................... 3 0 query command and command flash memory interface (cfi) mode ............................... 3 0 table 4-1. cfi mode: identifcation data values ......................................................................................... 3 0 table 4-2. cfi mode: system interface data values .................................................................................. 3 0 table 4-3. cfi mode: device geometry data values .................................................................................. 3 1 table 4-4. cfi mode: primary vendor-specifc extended query data values ............................................ 3 2 electrical characteristics .................................................................................................................... 3 3 absolute maximum stress ratings ............................................................................................... 3 3 operating temperature and voltage .......................................................................................... 3 3 dc characteristics ............................................................................................................................ 3 4 switching test circuit ...................................................................................................................... 3 5 switching test waveform ............................................................................................................... 3 5 ac characteristics ............................................................................................................................ 3 6 write command operation ......................................................................................................................... 3 7 figure 1. command write operation ................................................................................................ 3 7 read/reset operation ................................................................................................................................. 3 8 figure 2. read timing waveform ........................................................................................................ 3 8 figure 3. reset# timing waveform ................................................................................................... 3 9 erase/program operation ........................................................................................................................ 4 0 figure 4. automatic chip erase timing waveform ...................................................................... 4 0 figure 5. automatic chip erase algorithm flowchart ............................................................ 4 1 figure 6. automatic sector erase timing waveform ................................................................ 4 2 figure 7. automatic sector erase algorithm flowchart .................................................... 4 3
4 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b figure 8. erase suspend/resume flowchart .............................................................................. 4 4 figure 9. automatic program timing waveform .......................................................................... 4 5 figure 10. accelerated program timing diagram ..................................................................... 4 5 figure 11. ce# controlled write timing waveform ................................................................... 4 6 figure 12. automatic programming algorithm flowchart .................................................... 4 7 sector group protect/chip unprotect .............................................................................................. 4 8 figure 13. sector group protect/chip unprotect waveform (reset# control) ............... 4 8 figure 14. in-system sector group protect with reset#=vhv .............................................. 4 9 figure 15. chip unprotect algorithm with reset#=vhv ............................................................ 5 0 table 5. temporary sector group unprotect ........................................................................... 5 1 figure 16. temporary sector group unprotect waveform ................................................. 5 1 figure 17. temporary sector group unprotect flowchart ............................................... 5 2 figure 18. silicon id read timing waveform .................................................................................. 5 3 write operation status .............................................................................................................................. 5 4 figure 19. data# polling timing waveform (during automatic algorithm) ....................... 5 4 figure 20. data# polling algorithm ................................................................................................. 5 5 figure 21. toggle bit timing waveform (during automatic algorithm) ............................ 5 6 figure 22. toggle bit algorithm ........................................................................................................ 5 7 figure 23. byte# timing waveform for read operations (byte# switching from byte mode to word mode) ................................................................................................................................................. 5 8 recommended operating conditions .................................................................................................... 5 9 erase and programming performance ............................................................................................... 6 0 data retention ............................................................................................................................................... 6 0 latch-up characteristics ......................................................................................................................... 6 0 tsop pin capacitance ................................................................................................................................... 6 0 ordering information ................................................................................................................................. 6 1 part name description ................................................................................................................................ 6 2 package information ................................................................................................................................... 6 3 revision history ............................................................................................................................................ 6 7
5 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b 32m-bit [4m x 8 / 2m x 16] 3v supply flash memory features general features ? byte/word switchable - 4,194,304 x 8 / 2,097,152 x 16 ? sector structure - 8k-byte x 8 and 64k-byte x 63 ? extra 64k-byte sector for security - features factory locked and identifable, and customer lockable ? twenty-four sector groups - provides sector group protect function to prevent program or erase operation in the protected sector group - provides chip unprotect function to allow code changing - provides temporary sector group unprotect function for code changing in previously protected sector groups ? power supply operation - vcc 2.7 to 3.6 volt for read, erase, and program operations ? latch-up protected to 100ma from -1v to 1.5 x vcc ? low vcc write inhibit : vcc vlko ? compatible with jedec standard - pinout and software compatible to single power supply flash ? functional compatible with mx29lv320c t/b device performance ? high performance - fast access time: 70ns - fast program time: 11us/word typical utilizing accelerate function - fast erase time: 0.7s/sector, 35s/chip (typical) ? low power consumption - low active read current: 10ma (typical) at 5mhz - low standby current: 5ua (typical) ? typical 100,000 erase/program cycle ? 20 years data retention software features ? erase suspend/ erase resume - suspends sector erase operation to read data from or program data to another sector which is not being erased ? status reply - data# polling & toggle bits provide detection of program and erase operation completion ? support common flash interface (cfi) hardware features ? ready/busy# (ry/by#) output - provides a hardware method of detecting program and erase operation completion ? hardware reset (reset#) input - provides a hardware method to reset the internal state machine to read mode ? wp#/acc input pin - provides accelerated program capability
6 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b package ? 44-pin sop ? 48-pin tsop ? 48-ball tfbga (6 x 8mm) ? 48-ball lfbga (6 x 8mm) ? all pb-free devices are rohs compliant general description mx29lv320dt/b is a 32mbit fash memory that can be organized as 4mbytes of 8 bits each or as 2mbytes of 16 bits each. these devices operate over a voltage range of 2.7v to 3.6v typically using a 3v power supply input. the memory array is divided into 64 equal 64 kilo byte blocks. however, depending on the device being used as a top-boot or bottom-boot device, the top or the bottom frst block is further subdivided into 8 equal 8kbyte blocks. the outermost two sectors at the top or at the bottom are respectively the boot blocks for this device. this fash memory also provides an additional factory lockable or customer lockable 64kbyte sector to provide security feature. the mx29lv320dt/b is offered in a 44-pin sop, a 48-pin tsop and a 48-ball csp(tfbga) jedec standard package. these packages are offered in leaded, as well as lead-free versions that are compliant to the rohs specifcations. the software algorithm used for this device also adheres to the jedec standard for single power supply devices. these fash parts can be programmed in system or on commercially available eprom/flash programmers. separate oe# and ce# (output enable and chip enable) signals are provided to simplify system design. when used with high speed processors, the 70ns read access time of this fash memory permits operation with minimal time lost due to system timing delays. the automatic write algorithm provided on macronix fash memories perform an automatic erase prior to write. the user only needs to provide a write command to the command register. the on-chip state machine automati - cally controls the program and erase functions including all necessary internal timings. since erase and write operations take much longer time than read operations, erase/write can be interrupted to perform read opera - tions in other sectors of the device. for this, erase suspend operation along with erase resume operation are provided. data# polling or toggle bits are used to indicate the end of the erase/write operation. these devices are manufactured at the macronix fabrication facility using the time tested and proven macronix's advanced technology. this proprietary non-epi process provides a very high degree of latch-up protection for stresses up to 100 milliamperes on address and data pins from -1v to 1.5xvcc. with low power consumption and enhanced hardware and software features, this fash memory retains data reli - ably for at least twenty years. erase and programming functions have been tested to meet a typical specifcation of 100,000 cycles of operation.
7 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b pin configuration 48 tsop a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# nc wp#/acc ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 byte# gnd q15/a-1 q7 q14 q6 q13 q5 q12 q4 vcc q11 q3 q10 q2 q9 q1 q8 q0 oe# gnd ce# a0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 44 sop 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 we# a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce# gnd oe# q0 q8 q1 q9 q2 q10 q3 q11 a20 a19 a8 a9 a10 a11 a12 a13 a14 a15 a16 byte# gnd q15/a-1 q7 q14 q6 q13 q5 q12 q4 vcc 48-ball tfbga/lfbga (6mm x 8mm, top view, balls facing down) 6 5 4 3 2 1 a b c d e f g h a9 we# ry/by# a7 a3 a8 re- set# wp#/ acc a17 a4 a10 nc a18 a6 a2 a11 a19 a20 a5 a1 q7 q5 q2 q0 a0 q14 q12 q10 q8 ce# q13 vcc q11 q9 oe# q6 q4 q3 q1 gnd a13 a12 a14 a15 a16 byte# q15/ a-1 gnd
8 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b pin description logic symbol 16 or 8 q0-q15 (a-1) ry/by# a0-a20 vcc gnd ce# oe# we# reset# wp#/acc byte# 21 symbol pin name a0~a20 address input q0~q14 15 data inputs/outputs q15/a-1 q15(data input/output, word mode); a-1(lsb address input, byte mode) ce# chip enable input we# write enable input oe# output enable input byte# word/byte selection input reset# hardware reset pin, active low ry/by# ready/busy output vcc 3.0 volt-only single power supply wp#/acc hardware write protect/acceleration pin gnd device ground nc pin not connected internally note: if customers do not need wp#/acc feature, please connect wp#/acc pin to vcc or let it foating. the w p # / a c c h a s a n i n t e r n a l p u l l - u p w h e n unconnected wp#/acc is at vih.
9 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b block diagram control input logic program/erase high voltage write state machine (wsm) state register flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q15/a-1 a0-am am: msb address ce# oe# we# reset# byte# wp#/acc
10 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b block diagram description the block diagram on page 9 illustrates a simplifed architecture of mx29lv320d t/b. each block in the block diagram represents one or more circuit modules in the real chip used to access, erase, program, and read the memory array.. the "control input logic" block receives input pins ce#, oe#, we#, reset#, byte#, and wp#/acc. it creates internal timing control signals according to the input pins and outputs to the "address latch and buffer" to latch the external address pins a0-am(a20). the internal addresses are output from this block to the main array and decoders composed of "x-decoder", "y-decoder", "y-pass gate", and "flash ar - ray". the x-decoder decodes the word-lines of the fash array, while the y-decoder decodes the bit-lines of the fash array. the bit lines are electrically connected to the "sense amplifier" and "pgm data hv" se - lectively through the y-pass gates. sense amplifers are used to read out the contents of the fash memory, while the "pgm data hv" block is used to selectively deliver high power to bit-lines during programming. the "i/o buffer" controls the input and output on the q0-q15/a-1 pads. during read operation, the i/o buffer receives data from sense amplifers and drives the output pads accordingly. in the last cycle of program command, the i/o buffer transmits the data on q0-q15/a-1 to "program data latch", which controls the high power drivers in "pgm data hv" to selectively program the bits in a word or byte according to the user input pattern. the "program/erase high voltage" block comprises the circuits to generate and deliver the necessary high voltage to the x-decoder, flash array, and "pgm data hv" block. the logic control module com - prises of the "write state machine (wsm)", "state register", "command data decoder", and "command data latch". when the user issues a command by toggling we#, the command on q0-a15/a-1 is latched in the command data latch and is decoded by the command data decoder. the state register receives the command and records the current state of the device. the wsm implements the internal algorithms for pro - gram or erase according to the current command state by controlling each block in the block diagram.
11 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b table 1.a: mx29lv320dt sector group architecture block structure the main fash memory array can be organized as 4m bytes x 8 or as 2m words x 16. the details of the ad - dress ranges and the corresponding sector addresses are shown in table 1. table 1.a shows the sector group architecture for the top boot part, whereas table 1.b shows the sector group architecture for the bottom boot part. the specifc security sector addresses are shown at the bottom off each of these tables. sector group sector size sector sector address a20-a12 address range byte mode (kbytes) word mode (kwords) byte mode (x8) word mode (x16) 1 64 32 sa0 000000xxx 000000h-00ffffh 000000h-07fffh 1 64 32 sa1 000001xxx 010000h-01ffffh 008000h-0ffffh 1 64 32 sa2 000010xxx 020000h-02ffffh 010000h-17fffh 1 64 32 sa3 000011xxx 030000h-03ffffh 018000h-01ffffh 2 64 32 sa4 000100xxx 040000h-04ffffh 020000h-027fffh 2 64 32 sa5 000101xxx 050000h-05ffffh 028000h-02ffffh 2 64 32 sa6 000110xxx 060000h-06ffffh 030000h-037fffh 2 64 32 sa7 000111xxx 070000h-07ffffh 038000h-03ffffh 3 64 32 sa8 001000xxx 080000h-08ffffh 040000h-047fffh 3 64 32 sa9 001001xxx 090000h-09ffffh 048000h-04ffffh 3 64 32 sa10 001010xxx 0a0000h-0affffh 050000h-057fffh 3 64 32 sa11 001011xxx 0b0000h-0bffffh 058000h-05ffffh 4 64 32 sa12 001100xxx 0c0000h-0cffffh 060000h-067fffh 4 64 32 sa13 001101xxx 0d0000h-0dffffh 068000h-06ffffh 4 64 32 sa14 001110xxx 0e0000h-0effffh 070000h-077fffh 4 64 32 sa15 001111xxx 0f0000h-0fffffh 078000h-07ffffh 5 64 32 sa16 010000xxx 100000h-10ffffh 080000h-087fffh 5 64 32 sa17 010001xxx 110000h-11ffffh 088000h-08ffffh 5 64 32 sa18 010010xxx 120000h-12ffffh 090000h-097fffh 5 64 32 sa19 010011xxx 130000h-13ffffh 098000h-09ffffh 6 64 32 sa20 010100xxx 140000h-14ffffh 0a0000h-0a7fffh 6 64 32 sa21 010101xxx 150000h-15ffffh 0a8000h-0affffh 6 64 32 sa22 010110xxx 160000h-16ffffh 0b0000h-0b7fffh 6 64 32 sa23 010111xxx 170000h-17ffffh 0b8000h-0bffffh 7 64 32 sa24 011000xxx 180000h-18ffffh 0c0000h-0c7fffh 7 64 32 sa25 011001xxx 190000h-19ffffh 0c8000h-0cffffh 7 64 32 sa26 011010xxx 1a0000h-1affffh 0d0000h-0d7fffh 7 64 32 sa27 011011xxx 1b0000h-1bffffh 0d8000h-0dffffh 8 64 32 sa28 011100xxx 1c0000h-1cffffh 0e0000h-0e7fffh 8 64 32 sa29 011101xxx 1d0000h-1dffffh 0e8000h-0effffh 8 64 32 sa30 011110xxx 1e0000h-1effffh 0f0000h-0f7fffh 8 64 32 sa31 011111xxx 1f0000h-1fffffh 0f8000h-0fffffh 9 64 32 sa32 100000xxx 200000h-20ffffh 100000h-107fffh 9 64 32 sa33 100001xxx 210000h-21ffffh 108000h-10ffffh 9 64 32 sa34 100010xxx 220000h-22ffffh 110000h-117fffh
12 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b top boot security sector addresses sector group sector size sector sector address a20-a12 address range byte mode (kbytes) word mode (kwords) byte mode (x8) word mode (x16) 9 64 32 sa35 100011xxx 230000h-23ffffh 118000h-11ffffh 10 64 32 sa36 100100xxx 240000h-24ffffh 120000h-127fffh 10 64 32 sa37 100101xxx 250000h-25ffffh 128000h-12ffffh 10 64 32 sa38 100110xxx 260000h-26ffffh 130000h-137fffh 10 64 32 sa39 100111xxx 270000h-27ffffh 138000h-13ffffh 11 64 32 sa40 101000xxx 280000h-28ffffh 140000h-147fffh 11 64 32 sa41 101001xxx 290000h-29ffffh 148000h-14ffffh 11 64 32 sa42 101010xxx 2a0000h-2affffh 150000h-157fffh 11 64 32 sa43 101011xxx 2b0000h-2bffffh 158000h-15ffffh 12 64 32 sa44 101100xxx 2c0000h-2cffffh 160000h-167fffh 12 64 32 sa45 101101xxx 2d0000h-2dffffh 168000h-16ffffh 12 64 32 sa46 101110xxx 2e0000h-2effffh 170000h-177fffh 12 64 32 sa47 101111xxx 2f0000h-2fffffh 178000h-17ffffh 13 64 32 sa48 110000xxx 300000h-30ffffh 180000h-187fffh 13 64 32 sa49 110001xxx 310000h-31ffffh 188000h-18ffffh 13 64 32 sa50 110010xxx 320000h-32ffffh 190000h-197fffh 13 64 32 sa51 110011xxx 330000h-33ffffh 198000h-19ffffh 14 64 32 sa52 110100xxx 340000h-34ffffh 1a0000h-1a7fffh 14 64 32 sa53 110101xxx 350000h-35ffffh 1a8000h-1affffh 14 64 32 sa54 110110xxx 360000h-36ffffh 1b0000h-1b7fffh 14 64 32 sa55 110111xxx 370000h-37ffffh 1b8000h-1bffffh 15 64 32 sa56 111000xxx 380000h-38ffffh 1c0000h-1c7fffh 15 64 32 sa57 111001xxx 390000h-39ffffh 1c8000h-1cffffh 15 64 32 sa58 111010xxx 3a0000h-3affffh 1d0000h-1d7fffh 15 64 32 sa59 111011xxx 3b0000h-3bffffh 1d8000h-1dffffh 16 64 32 sa60 111100xxx 3c0000h-3cffffh 1e0000h-1e7fffh 16 64 32 sa61 111101xxx 3d0000h-3dffffh 1e8000h-1effffh 16 64 32 sa62 111110xxx 3e0000h-3effffh 1f0000h-1f7fffh 17 8 4 sa63 111111000 3f0000h-3f1fffh 1f8000h-1f8fffh 18 8 4 sa64 111111001 3f2000h-3f3fffh 1f9000h-1f9fffh 19 8 4 sa65 111111010 3f4000h-3f5fffh 1fa000h-1fafffh 20 8 4 sa66 111111011 3f6000h-3f7fffh 1fb000h-1fbfffh 21 8 4 sa67 111111100 3f8000h-3f9fffh 1fc000h-1fcfffh 22 8 4 sa68 111111101 3fa000h-3fbfffh 1fd000h-1fdfffh 23 8 4 sa69 111111110 3fc000h-3fdfffh 1fe000h-1fefffh 24 8 4 sa70 111111111 3fe000h-3fffffh 1ff000h-1fffffh sector size sector address a20~a12 address range byte mode (kbytes) word mode (kwords) byte mode (x8) word mode (x16) 64 32 111111xxx 3f0000h-3fffffh 1f8000h-1fffffh
13 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b table 1.b: mx29lv320db sector group architecture sector group sector size sector sector address a20-a12 address range byte mode (kbytes) word mode (kwords) byte mode (x8) word mode (x16) 1 8 4 sa0 000000000 000000h-001fffh 000000h-000fffh 2 8 4 sa1 000000001 002000h-003fffh 001000h-001fffh 3 8 4 sa2 000000010 004000h-005fffh 002000h-002fffh 4 8 4 sa3 000000011 006000h-007fffh 003000h-003fffh 5 8 4 sa4 000000100 008000h-009fffh 004000h-004fffh 6 8 4 sa5 000000101 00a000h-00bfffh 005000h-005fffh 7 8 4 sa6 000000110 00c000h-00dfffh 006000h-006fffh 8 8 4 sa7 000000111 00e000h-00ffffh 007000h-007fffh 9 64 32 sa8 000001xxx 010000h-01ffffh 008000h-00ffffh 9 64 32 sa9 000010xxx 020000h-02ffffh 010000h-017fffh 9 64 32 sa10 000011xxx 030000h-03ffffh 018000h-01ffffh 10 64 32 sa11 000100xxx 040000h-04ffffh 020000h-027fffh 10 64 32 sa12 000101xxx 050000h-05ffffh 028000h-02ffffh 10 64 32 sa13 000110xxx 060000h-06ffffh 030000h-037fffh 10 64 32 sa14 000111xxx 070000h-07ffffh 038000h-03ffffh 11 64 32 sa15 001000xxx 080000h-08ffffh 040000h-047fffh 11 64 32 sa16 001001xxx 090000h-09ffffh 048000h-04ffffh 11 64 32 sa17 001010xxx 0a0000h-0affffh 050000h-057fffh 11 64 32 sa18 001011xxx 0b0000h-0bffffh 058000h-05ffffh 12 64 32 sa19 001100xxx 0c0000h-0cffffh 060000h-067fffh 12 64 32 sa20 001101xxx 0d0000h-0dffffh 068000h-06ffffh 12 64 32 sa21 001110xxx 0e0000h-0effffh 070000h-077fffh 12 64 32 sa22 001111xxx 0f0000h-0fffffh 078000h-07ffffh 13 64 32 sa23 010000xxx 100000h-10ffffh 080000h-087fffh 13 64 32 sa24 010001xxx 110000h-11ffffh 088000h-08ffffh 13 64 32 sa25 010010xxx 120000h-12ffffh 090000h-097fffh 13 64 32 sa26 010011xxx 130000h-13ffffh 098000h-09ffffh 14 64 32 sa27 010100xxx 140000h-14ffffh 0a0000h-0a7fffh 14 64 32 sa28 010101xxx 150000h-15ffffh 0a8000h-0affffh 14 64 32 sa29 010110xxx 160000h-16ffffh 0b0000h-0b7fffh 14 64 32 sa30 010111xxx 170000h-17ffffh 0b8000h-0bffffh 15 64 32 sa31 011000xxx 180000h-18ffffh 0c0000h-0c7fffh 15 64 32 sa32 011001xxx 190000h-19ffffh 0c8000h-0cffffh 15 64 32 sa33 011010xxx 1a0000h-1affffh 0d0000h-0d7fffh 15 64 32 sa34 011011xxx 1b0000h-1bffffh 0d8000h-0dffffh 16 64 32 sa35 011100xxx 1c0000h-1cffffh 0e0000h-0e7fffh 16 64 32 sa36 011101xxx 1d0000h-1dffffh 0e8000h-0effffh 16 64 32 sa37 011110xxx 1e0000h-1effffh 0f0000h-0f7fffh 16 64 32 sa38 011111xxx 1f0000h-1fffffh 0f8000h-0fffffh 17 64 32 sa39 100000xxx 200000h-20ffffh 100000h-107fffh 17 64 32 sa40 100001xxx 210000h-21ffffh 108000h-10ffffh 17 64 32 sa41 100010xxx 220000h-22ffffh 110000h-117fffh
14 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b bottom boot security sector addresses sector group sector size sector sector address a20-a12 address range byte mode (kbytes) word mode (kwords) byte mode (x8) word mode (x16) 17 64 32 sa42 100011xxx 230000h-23ffffh 118000h-11ffffh 18 64 32 sa43 100100xxx 240000h-24ffffh 120000h-127fffh 18 64 32 sa44 100101xxx 250000h-25ffffh 128000h-12ffffh 18 64 32 sa45 100110xxx 260000h-26ffffh 130000h-137fffh 18 64 32 sa46 100111xxx 270000h-27ffffh 138000h-13ffffh 19 64 32 sa47 101000xxx 280000h-28ffffh 140000h-147fffh 19 64 32 sa48 101001xxx 290000h-29ffffh 148000h-14ffffh 19 64 32 sa49 101010xxx 2a0000h-2affffh 150000h-157fffh 19 64 32 sa50 101011xxx 2b0000h-2bffffh 158000h-15ffffh 20 64 32 sa51 101100xxx 2c0000h-2cffffh 160000h-167fffh 20 64 32 sa52 101101xxx 2d0000h-2dffffh 168000h-16ffffh 20 64 32 sa53 101110xxx 2e0000h-2effffh 170000h-177fffh 20 64 32 sa54 101111xxx 2f0000h-2fffffh 178000h-17ffffh 21 64 32 sa55 110000xxx 300000h-30ffffh 180000h-187fffh 21 64 32 sa56 110001xxx 310000h-31ffffh 188000h-18ffffh 21 64 32 sa57 110010xxx 320000h-32ffffh 190000h-197fffh 21 64 32 sa58 110011xxx 330000h-33ffffh 198000h-19ffffh 22 64 32 sa59 110100xxx 340000h-34ffffh 1a0000h-1a7fffh 22 64 32 sa60 110101xxx 350000h-35ffffh 1a8000h-1affffh 22 64 32 sa61 110110xxx 360000h-36ffffh 1b0000h-1b7fffh 22 64 32 sa62 110111xxx 370000h-37ffffh 1b8000h-1bffffh 23 64 32 sa63 111000xxx 380000h-38ffffh 1c0000h-1c7fffh 23 64 32 sa64 111001xxx 390000h-39ffffh 1c8000h-1cffffh 23 64 32 sa65 111010xxx 3a0000h-3affffh 1d0000h-1d7fffh 23 64 32 sa66 111011xxx 3b0000h-3bffffh 1d8000h-1dffffh 24 64 32 sa67 111100xxx 3c0000h-3cffffh 1e0000h-1e7fffh 24 64 32 sa68 111101xxx 3d0000h-3dffffh 1e8000h-1effffh 24 64 32 sa69 111110xxx 3e0000h-3effffh 1f0000h-1f7fffh 24 64 32 sa70 111111xxx 3f0000h-3fffffh 1f8000h-1fffffh sector size sector address a20~a12 address range byte mode (kbytes) word mode (kwords) byte mode (x8) word mode (x16) 64 32 000000xxx 000000h-00ffffh 00000h-07fffh
15 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b notes: 1. all sectors will be unprotected if wp#/acc=vhv. 2. the two outmost boot sectors are protected if wp#/acc=vil. 3. when wp#/acc = vih, the protection conditions of the two outmost boot sectors depend on previous protection conditions."sector/sector block protection and unprotection" describes the protect and unprotect method. 4. q0~q15 are input (din) or output (dout) pins according to the requests of command sequence, sector protection, or data polling algorithm. 5. in word mode (byte#=vih), the addresses are am to a0. in byte mode (byte#=vil), the addresses are am to a-1 (q15). 6. am: msb of address. bus operation table 2-1. bus operation mode select re- set# ce# we# oe# address data (i/o) q0~q7 byte# wp#/ acc vil vih q8~q15 device reset l x x x x highz highz highz l/h standby mode vcc 0.3v vcc 0.3v x x x highz highz highz h output disable h l h h x highz highz highz l/h read mode h l h l ain dout q8-q14= highz q15=a-1 dout l/h write (note1) h l l h ain din din note3 accelerate program h l l h ain din din vhv temporary sector- group unprotect vhv x x x ain din highz din note3 sector-group protect (note2) vhv l l h sector address, a6=l, a1=h, a0=l din, dout x x l/h chip unprotect (note2) vhv l l h sector address, a6=h, a1=h, a0=l din, dout x x note3
16 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b notes: 1. sector unprotected code:00h. sector protected code:01h. 2. factory locked code: 99h. factory unlocked code: 19h. 3. am: msb of address. table 2-2. bus operation item control input am to a12 a11 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 q0~q7 q8~q15 ce# we# oe# sector lock status verifcation l h l sa x v hv x l x h l 01h or 00h (note 1) x read silicon id manufacturer code l h l x x v hv x l x l l c2h x read silicon id mx29lv320dt l h l x x v hv x l x l h a7h 22h(word) x (byte) read silicon id mx29lv320db l h l x x v hv x l x l h a8h 22h(word) x (byte) read indicator bit (q7) for security sector l h l x x v hv x l x h h 99h or 19h (note 2) x
17 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b functional operation description read operation to perform a read operation, the system addresses the desired memory array or status register location by pro - viding its address on the address pins and simultaneously enabling the chip by driving ce# & oe# low, and we# high. after the tce and toa timing requirements have been met, the system can read the contents of the addressed location by reading the data (i/o) pins. if either the ce# or oe# is held high, the outputs will remain tri-stated and no data will appear on the output pins. write operation to perform a write operation, the system provides the desired address on the address pins, enables the chip by asserting ce# low, and disables the data (i/o) pins by holding oe# high. the system then places data to be written on the data (i/o) pins and pulses we# low. the device captures the address information on the falling edge of we# and the data on the rising edge of we#. to see an example, please refer to the timing diagram in figure 1 on page 32. the system is not allowed to write invalid commands (commands not defned in this datasheet) to the device. writing an invalid command may put the device in an undefned state. device reset driving the reset# pin low for a period of trp or more will return the device to read mode. if the device is in the middle of a program or erase operation, the reset operation will take at most a period of tready1 before the device returns to read mode. until the device does returns to read mode, the ry/by# pin will remain low (busy status). when the reset# pin is held at gnd0.3v, the device only consumes standby (isbr) current. however, the de - vice draws larger current if the reset# pin is held at a voltage greater than gnd+0.3v and less than or equal to vil. it is recommended to tie the system reset signal to the reset# pin of the fash memory. this allows the device to be reset with the system and puts it in a state where the system can immediately begin reading boot code from it. standby mode the device enters standby mode whenever the reset# and ce# pins are both held high. while in this mode, we# and oe# will be ignored, all data output pins will be in a high impedance state, and the device will draw minimal (isb) current. output disable while in active mode (reset# high and ce# low), the oe# pin controls the state of the output pins. if oe# is held high, all data (i/o) pins will remain tri-stated. if held low , the byte or word data (i/o) pins will drive data.
18 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b functional operation description (cont'd) byte/word selection the byte# input pin is used to select the organization of the array data and how the data is input/output on the data (i/o) pins. if the byte# pin is held high, word mode will be selected and all 16 data lines (q0 to q15) will be active. if byte# is forced low, byte mode will be active and only data lines q0 to q7 will be active. data lines q8 to q14 will remain in a high impedance state and q15 becomes the a-1 address input pin. hardware write protect by driving the wp#/acc pin low, the outermost two boot sectors are protected from all erase/program opera - tions. if wp#/acc is held high (vih to vcc), these two outermost sectors revert to their previously protected/ unprotected status. accelerated programming operation by applying high voltage (vhv) to the wp#/acc pin, the device will enter the accelerated programming mode. this mode permits the system to skip the normal command unlock sequences and program byte/word locations directly. typically, this mode provides a 30% reduction in overall programming times. during accelerated pro - gramming, the current drawn from the wp#/acc pin is no more than icp1. temporary sector group unprotect operation the system can apply vhv to the reset# pin to place the device in temporary unprotect mode. in this mode, previously protected sectors can be programmed/erased just as though they were unprotected. the device re - turns to normal operation once vhv is removed from the reset# pin and previously protected sectors will once again be protected. sector group protect operation the mx29lv320d t/b provides user programmable protection against program/erase operations for selected sectors. most sectors cannot protected individually. instead, they are bound in groups of four or less called sec - tor-groups. protection is available for individual sector-groups, which includes all member sectors. boot sec - tors are the exception to this rule as they are assigned unique sector-group addresses and can be protected individually without protecting any adjacent sectors or sector-groups. the three sectors adjacent to the boot sectors form a non-standard sector-group. please refer to table 1a and table 1b which show all sector-group assignments. during the protection operation, the sector address of any sector within a sector-group may be used to specify the sector-group being protected. there are two methods available to protect sector-groups. the frst and preferred method is activated by apply - ing vhv on the reset# pin and following the timing in figure 13 and the algorithm shown in figure 14. this is a command operation that can be performed either on an external programmer or in-circuit by the system con - troller. the second method is strictly a bus operation and is entered by asserting vhv on a9 and oe# pins, with a6 and ce# at vil. the protection operation begins at the falling edge of we# and terminates at the rising edge. contact macronix for more details on this method.
19 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b functional operation description (cont'd) chip unprotect operation the chip unprotect operation unprotects all sectors within the device. it is standard procedure and highly recom - mended to protect all sector-groups prior using the chip unprotect operation. this will prevent possible damage to the sector-group protection logic. all sector groups are unprotected when shipped from the factory, so this operation is only necessary if the user has previously protected any sector-groups and wishes to unprotect them now. mx29lv320d t/b provides two methods for unprotecting the entire chip. the frst and preferred method is en - tered by applying vhv on reset# pin and following the timing diagram in figure 13 and using the algorithm shown in figure 15. the second method is entered by asserting vhv on a9 and oe# pins, with a6 at vih and ce# at vil. the protec - tion operation begins at the falling edge of we# and terminates at the rising edge. contact macronix for more details on this method. automatic select bus operations the following fve bus operations require a9 to be raised to vhv. please see automatic select command sequence in the command operations section for details of equivalent command operations that do not require the use of vhv. sector lock status verification to determine the protected state of any sector using bus operations, the system performs a read operation with a9 raised to vhv, the sector address applied to address pins a20 to a12, address pins a6 & a0 held low, and address pin a1 held high. if data bit q0 is low, the sector is not protected, and if q0 is high, the sector is protected. read silicon id manufacturer code to determine the silicon id manufacturer code, the system performs a read operation with a9 raised to vhv and address pins a6, a1, & a0 held low. the macronix id code of c2h should be present on data bits q0 to q7. read silicon id mx29lv320dt code to verify the silicon id mx29lv320dt code, the system performs a read operation with a9 raised to vhv, address pins a6 & a1 held low, and address pin a0 held high. the mx29lv320dt code of a7h should be present on data bits q0 to q7. q15 to q8 will be tri-stated unless word mode is selected. in this case, q15 to q8 will output the value 22h. read silicon id mx29lv320db code to verify the silicon id mx29lv320db code, the system performs a read operation with a9 raised to vhv, address pins a6 & a1 held low, and address pin a0 held high. the mx29lv320dt code of a8h should be present on data bits q0 to q7. q15 to q8 will be tri-stated unless word mode is selected. in this case, q15 to q8 will output the code 22h.
20 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b functional operation description (cont'd) read indicator bit (q7) for security sector to determine if the security sector has been locked at the factory, the system performs a read operation with a9raised to vhv, address pin a6 held low, and address pins a1 & a0 held high. if the security sector has been locked at the factory, the code 99h will be present on data bits q0 to q7. otherwise, the factory unlocked code of 19h will be present. inherent data protection to avoid accidental erasure or programming of the device, the device is automatically reset to read mode during power up. additionally, the following design features protect the device from unintended data corruption. command completion only after the successful completion of the specifed command sets will the device begin its erase or program operation. if any command sequence is interrupted or given an invalid command, the device immediately returns to read mode. low vcc write inhibit the device refuses to accept any write command when vcc is less than vlko. this prevents data from spuriously being altered during power-up, power-down, or temporary power interruptions. the device automatically resets itself when vcc is lower than vlko and write cycles are ignored until vcc is greater than vlko. the system must provide proper signals on control pins after vcc rises above vlko to avoid unintentional program or erase opera - tions. write pulse "glitch" protection ce#, we#, oe# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. logical inhibit a valid write cycle requires both ce# and we# at vil with oe# at vih. write cycle is ignored when either ce# at vih, we# a vih, or oe# at vil. power-up sequence upon power up, the mx29lv320d t/b is placed in read mode. furthermore, program or erase operation will be - gin only after successful completion of specifed command sequences.
21 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b functional operation description (cont'd) power-up write inhibit when we#, ce# is held at vil and oe# is held at vih during power up, the device ignores the frst command on the rising edge of we#. power supply decoupling a 0.1uf capacitor should be connected between the vcc and gnd to reduce the noise effect.
22 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b notes: 1. id 22a7h(top), 22a8h(bottom). 2. it is not allowed to adopt any other code which is not in the above command defnition table. table 3. mx29lv320d t/b command definitions command operations command read mode reset mode automatic select enter security sector region enable manifacture id device id sector factory sector protect verify word byte word byte word byte word byte word byte 1st bus cycle addr addr xxx 555 aaa 555 aaa 555 aaa 555 aaa 555 aaa data data f0 aa aa aa aa aa aa aa aa aa aa 2nd bus cycle addr 2aa 555 2aa 555 2aa 555 2aa 555 2aa 555 data 55 55 55 55 55 55 55 55 55 55 3rd bus cycle addr 555 aaa 555 aaa 555 aaa 555 aaa 555 aaa data 90 90 90 90 90 90 90 90 88 88 4th bus cycle addr x00 x00 x01 x02 x03 x06 (sector) x02 (sector) x04 data c2h c2h id id 99/19 99/19 00/01 00/01 5th bus cycle addr data 6th bus cycle addr data command exit security sector program chip erase sector erase cfi read erase suspend erase resume word byte word byte word byte word byte word byte byte/ word byte/ word 1st bus cycle addr 555 aaa 555 aaa 555 aaa 555 aaa 55 aa xxx xxx data aa aa aa aa aa aa aa aa 98 98 b0 30 2nd bus cycle addr 2aa 555 2aa 555 2aa 555 2aa 555 data 55 55 55 55 55 55 55 55 3rd bus cycle addr 555 aaa 555 aaa 555 aaa 555 aaa data 90 90 a0 a0 80 80 80 80 4th bus cycle addr xxx xxx addr addr 555 aaa 555 aaa data 00 00 data data aa aa aa aa 5th bus cycle addr 2aa 555 2aa 555 data 55 55 55 55 6th bus cycle addr 555 aaa sector sector data 10 10 30 30
23 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b command operations (cont'd) automatic programming of the memory array the mx29lv320d t/b provides the user the ability to program the memory array in byte mode or word mode. as long as the users enters the correct cycle defned in the table 3 (including 2 unlock cycles and the a0h program command), any byte or word data provided on the data lines by the system will automatically be programmed into the array at the specifed location. after the program command sequence has been executed, the internal write state machine (wsm) automatically executes the algorithms and timings necessary for programming and verifcation, which includes generating suit - able program pulses, checking cell threshold voltage margins, and repeating the program pulse if any cells do not pass verifcation or have low margins. the internal controller protects cells that do pass verifcation and mar - gin tests from being over-programmed by inhibiting further program pulses to these passing cells as weaker cells continue to be programmed. with the internal wsm automatically controlling the programming process, the user only needs to enter the pro - gram command and data once. programming will only change the bit status from "1" to "0". it is not possible to change the bit status from "0" to "1" by programming. this can only be done by an erase operation. furthermore, the internal write verifcation only checks and detects errors in cases where a "1" is not successfully programmed to "0". any commands written to the device during programming will be ignored except hardware reset, which will termi - nate the program operation after a period of time no more than tready1. when the embedded program algorithm is complete or the program operation is terminated by a hardware reset, the device will return to read mode. the typical chip program time at room temperature of the mx29lv320d t/b is less than 36 seconds. after the embedded program operation has begun, the user can check for completion by reading the following bits in the status register: *1: when an attempt is made to program a protected sector, the program operation will abort thus preventing any data changes in the protected sector. q7 will output complement data and q6 will toggle briefy (1us or less) be - fore aborting and returning the device to read mode. *2: ry/by# is an open drain output pin and should be connected to vcc through a high value pull-up resistor. erasing the memory array there are two types of erase operations performed on the memory array -- sector erase and chip erase. in the sector erase operation, one or more selected sectors may be erased simultaneously. in the chip erase opera - tion, the complete memory array is erased except for any protected sectors. status q7*1 q6*1 q5 ry/by# *2 in progress q7# toggling 0 0 finished q7 stop toggling 0 1 exceed time limit q7# toggling 1 0
24 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b sector erase the sector erase operation is used to clear data within a sector by returning all of its memory locations to the "1" state. it requires six command cycles to initiate the erase operation. the frst two cycles are "unlock cycles", the third is a confguration cycle, the fourth and ffth are also "unlock cycles", and the sixth cycle is the sector erase command. after the sector erase command sequence has been issued, an internal 50us time-out counter is started. until this counter reaches zero, additional sector addresses and sector erase commands may be is - sued thus allowing multiple sectors to be selected and erased simultaneously. after the 50us time-out counter has expired, no new commands will be accepted and the embedded sector erase operation will begin. note that the 50us timer-out counter is restarted after every erase command sequence. if the user enters any command other than sector erase or erase suspend during the time-out period, the erase operation will abort and the de - vice will return to read mode. after the embedded sector erase operation begins, all commands except erase suspend will be ignored. the only way to interrupt the operation is with an erase suspend command or with a hardware reset. the hardware reset will completely abort the operation and return the device to read mode. the system can determine the status of the embedded sector erase operation by the following methods: note : 1. the q3 status bit is the time-out indicator. when q3=0, the time-out counter has not yet reached zero and a new sector erase command may be issued to specify the address of another sector to be erased. when q3=1, the time-out counter has expired and the sector erase operation has already begun. erase suspend is the only valid command that may be issued once the embedded erase operation is underway . 2. ry/by# is an open drain output pin and should be connected to vcc through a high value pull-up resistor. 3. when an attempt is made to erase only protected sector(s), the program operation will abort thus preventing any data changes in the protected sector(s). q7 will output its complement data and q6 will toggle briefy (100us or less) before aborting and returning the device to read mode. if unprotected sectors are also specifed, however, they will be erased normally and the protected sector(s) will remain unchanged. 4. q2 is a localized indicator showing a specifed sector is undergoing erase operation or not. q2 toggles when user reads at addresses where the sectors are actively being erased (in erase mode) or to be erased (in erase suspend mode). when a sector has been completely erased, q2 stops toggling at the sector even when the device is still in erase operation for remaining selected sectors. at that circumstance, q2 will still toggle when device is read at any other sector that remains to be erased. command operations (cont'd) status q7 q6 q5 q3 (note 1) q2 ry/by# (note 2) time-out period 0 toggling 0 0 toggling 0 in progress 0 toggling 0 1 toggling 0 finished 1 stop toggling 0 1 1 1 exceeded time limit 0 toggling 1 1 toggling 0
25 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b chip erase the chip erase operation is used erase all the data within the memory array. all memory cells containing a "0" will be returned to the erased state of "1". this operation requires 6 write cycles to initiate the action. the frst two cycles are "unlock" cycles, the third is a confguration cycle, the fourth and ffth are also "unlock" cycles, and the sixth cycle initiates the chip erase operation. during the chip erase operation, no other software commands will be accepted, but if a hardware reset is re - ceived or the working voltage is too low, that chip erase will be terminated. after chip erase, the chip will auto - matically return to read mode. the system can determine the status of the embedded chip erase operation by the following methods: *1: ry/by# is an open drain output pin and should be connected to vcc through a high value pull-up resistor. after beginning a sector erase operation, erase suspend is the only valid command that may be issued. if sys - tem issues an erase suspend command during the 50us time-out period following a sector erase command, the time-out period will terminate immediately and the device will enter erase-suspended read mode. if the system issues an erase suspend command after the sector erase operation has already begun, the device will not enter erase-suspended read mode until tready1 time has elapsed. the system can determine if the device has en - tered the erase-suspended read mode through q6, q7, and ry/by#. after the device has entered erase-suspended read mode, the system can read or program any sector(s) ex - cept those being erased by the suspended erase operation. reading any sector being erased or programmed will return the contents of the status register. whenever a suspend command is issued, user must issue a re - sume command and check q6 toggle bit status, before issue another erase command. the system can use the status register bits shown in the following table to determine the current state of the device: sector erase suspend when the device has suspended erasing, user can execute the command sets except sector erase and chip erase, such as read silicon id, sector protect verify, program, cfi query and erase resume. command operations (cont'd) status q7 q6 q5 q3 q2 ry/by# erase suspend read in erase suspended sector 1 no toggle 0 n/a toggle 1 erase suspend read in non-erase suspended sector data data data data data 1 erase suspend program in non-erase suspended sector q7# toggle 0 n/a n/a 0 status q7 q6 q5 q2 ry/by# *1 in progress 0 toggling 0 toggling 0 finished 1 stop toggling 0 1 1 exceed time limit 0 toggling 1 toggling 0
26 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b command operations (cont'd) sector erase resume the sector erase resume command is valid only when the device is in erase-suspended read mode. after erase resumes, the user can issue another ease suspend command, but there should be a 4ms interval be - tween ease resume and the next erase suspend command. if the user enters an infnite suspend-resume loop, or suspend-resume exceeds 1024 times, erase times will increase dramatically . automatic select operations when the device is in read mode, erase-suspended read mode, or cfi mode, the user can issue the automatic select command shown in table 3 (two unlock cycles followed by the automatic select command 90h) to enter automatic select mode. after entering automatic select mode, the user can query the manufacturer id, device id, security sector locked status, or sector-group protected status multiple times without issuing a new automatic select command. while in automatic select mode, issuing a reset command (f0h) will return the device to read mode (or ease- suspended read mode if erase-suspend was active). another way to enter automatic select mode is to use one of the bus operations shown in table 2-2. bus operation. after the high voltage (vhv) is removed from the a9 pin, the device will automatically return to read mode or erase-suspended read mode. automatic select command sequence automatic select mode is used to access the manufacturer id, device id and to verify whether or not secured silicon is locked and whether or not a sector is protected. the automatic select mode has four command cycles. the frst two are unlock cycles, and followed by a specifc command. the fourth cycle is a normal read cycle, and user can read at any address any number of times without entering another command sequence. the reset command is necessary to exit the automatic select mode and back to read array. the following table shows the identifcation code with corresponding address. after entering automatic select mode, no other commands are allowed except the reset command. address (hex) data (hex) representation manufacturer id word x00 c2 byte x00 c2 device id word x01 22a7/22a8 top/bottom boot sector byte x02 a7/a8 top/bottom boot sector secured silicon word x03 99/19 factory locked/unlocked byte x06 99/19 factory locked/unlocked sector protect verify word (sector address) x 02 00/01 unprotected/protected byte (sector address) x 04 00/01 unprotected/protected
27 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b read manufacturer id or device id the manufacturer id (identifcation) is a unique hexadecimal number assigned to each manufacturer by the je - dec committee. each company has its own manufacturer id, which is different from the id of all other compa - nies. the number assigned to macronix is c2h. the device id is a unique hexadecimal number assigned by the manufacturer for each one of the fash devices made by that manufacturer. the above two id types are stored in a 16-bit register on the fash device -- eight bits for each id. this register is normally read by the user or by the programming machine to identify the manufacturer and the specifc device. after entering automatic select mode, performing a read operation with a1 & a0 held low will cause the device to output the manufacturer id on the data i/o (q7 to q0) pins. performing a read operation with a1 low and a0 high will cause the device to output the device id. security sector lock status after entering automatic select mode, the customer can check the lock status of the security sector by perform - ing a read operations with a0 and a1 held high. if the code 99h is read from data pins q7 to q0, the sector has been locked at the factory. if the code 19h is read, the sector has not been locked at the factory. verify sector group protection after entering automatic select mode, performing a read operation with a1 held high and a0 held low and the address of the sector to be checked applied to a20 to a12, data bit q0 will indicate the protected status of the addressed sector. if q0 is high, the sector is protected. conversely, if q0 is low, the sector is unprotected. security sector flash memory region the security sector region is an extra memory space of 64kbytes (32kwords) in length. the security sector can be locked by the factory prior to shipping, or it can be locked by the customer later . factory locked: security sector programmed and protected at the factory in a factory locked device, the security sector is permanently locked before shipping from the factory. the de - vice will have a 16-byte (8-word) esn in the security region. in bottom boot devices, the esn occupies address - es 00000h to 0000fh in byte mode or 00000h to 00007h in word mode. in top boot devices, the exn occupies addresses 3f0000h to 3f000fh in byte mode or 1f800h to 1f8007h in word mode. command operations (cont'd)
28 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b factory locked: security sector programmed and protected at the factory in a factory locked device, the security sector is permanently locked before shipping from the factory. the de - vice will have a 16-byte (8-word) esn in the security region. in bottom boot devices, the esn occupies address - es 00000h to 0000fh in byte mode or 00000h to 00007h in word mode. in top boot devices, the exn occupies addresses 3f0000h to 3f000fh in byte mode or 1f800h to 1f8007h in word mode. customer lockable: security sector not programmed or protected at the factory when the security feature is not required, the security sector can provide an extra sector of memory, which can be read, programmed, and erased with the same endurance limitations specifed for normal sectors. two methods are available for protecting the security sector. note that once the security sector is protected, there is no way to unprotect it and its contents can no longer be altered. the frst protection method requires writing the three-cycle enter security region command followed by the use of the sector-group protect algorithm as illustrated in figure 14-1 with the following exception: the reset# pin may be at either vih or vhv. unlike normal sector-groups, which do require vhv on the reset# pin, the security sector may be permanently locked in-circuit without the use of high voltage. the second protection method also uses the three-cycle enter security region command, but uses bus operations that applies vhv to the a9 and oe# pins with a6, ce#, and we# held low and the sa address applied to a20 to a12. the protection operation begins at the falling edge of we# and terminates at the rising edge. contact macronix for more details on using this method. after the security sector is locked and verifed, the system must write an exit security sector region command, go through a power cycle, or issue a hardware reset to return the device to read normal array mode. enter and exit security sector the device allows the user to access the extra 64k-byte sector identifed as the security sector, which may con - tain a random, 128-bits electronic serial number (esn), or it may contain user data. to access the security sector, the user must issue a three-cycle "enter security sector" command sequence. to exit the security sector and return to normal operation, the user issues the four-cycle "exit security sector" com - mand. before issuing the "exit security sector" command, please ensure the entering of security sector region. command operations (cont'd)
29 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b command operations (cont'd) reset operation in the following situations, executing reset command will reset device back to read mode: ? among erase command sequence (before the full command set is completed) ? sector erase time-out period ? erase fail (while q5 is high) ? among program command sequence (before the full command set is completed, erase-suspended program included) ? program fail (while q5 is high, and erase-suspended program fail is included) ? read silicon id mode ? sector protect verify ? cfi mode while device is at the status of program fail or erase fail (q5 is high), user must issue reset command to reset device back to read array mode. while the device is in read silicon id mode, sector protect verify or cfi mode, user must issue reset command to reset device back to read array mode. when the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ig - nore reset command.
30 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b table 4-1. cfi mode: identifcation data values (all values in these tables are in hexadecimal) table 4-2. cfi mode: system interface data values common flash memory interface (cfi) mode query command and command flash memory interface (cfi) mode mx29lv320d t/b features cfi mode. host system can retrieve the operating characteristics, structure and vendor-specifed information such as identifying information, memory size, byte/word confguration, operating voltages and timing information of this device by cfi mode. the device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h/aah (depending on word/byte mode) any time the device is ready to read array data. the system can read cfi information at the addresses given in table 4. once user enters cfi query mode, user can not issue any other commands except reset command. the reset command is required to exit cfi mode and go back to the mode before entering cfi. the system can write the cfi query command only when the device is in read mode, erase suspend, standby mode or automatic select mode. the cfi unused area is macronix's reserved. description address (h) (word mode) address (h) (byte mode) data (h) query-unique ascii string "qry" 10 20 0051 11 22 0052 12 24 0059 primary vendor command set and control interface id code 13 26 0002 14 28 0000 address for primary algorithm extended query table 15 2a 0040 16 2c 0000 alternate vendor command set and control interface id code 17 2e 0000 18 30 0000 address for alternate algorithm extended query table 19 32 0000 1a 34 0000 description address (h) (word mode) address (h) (byte mode) data (h) vcc supply minimum program/erase voltage 1b 36 0027 vcc supply maximum program/erase voltage 1c 38 0036 vpp supply minimum program/erase voltage 1d 3a 0000 vpp supply maximum program/erase voltage 1e 3c 0000 typical timeout per single word/byte write, 2 n us 1f 3e 0004 typical timeout for maximum-size buffer write, 2 n us 20 40 0000 typical timeout per individual block erase, 2 n ms 21 42 000a typical timeout for full chip erase, 2 n ms 22 44 0000 maximum timeout for word/byte write, 2 n times typical 23 46 0005 maximum timeout for buffer write, 2 n times typical 24 48 0000 maximum timeout per individual block erase, 2 n times typical 25 4a 0004 maximum timeout for chip erase, 2 n times typical 26 4c 0000
31 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b table 4-3. cfi mode: device geometry data values description address (h) (word mode) address (h) (byte mode) data (h) device size = 2 n in number of bytes 27 4e 0016 flash device interface description (02=asynchronous x8/x16) 28 50 0002 29 52 0000 maximum number of bytes in buffer write = 2 n (not support) 2a 54 0000 2b 56 0000 number of erase regions within device 2c 58 0002 index for erase bank area 1 [2e,2d] = # of same-size sectors in region 1-1 [30, 2f] = sector size in multiples of 256-bytes 2d 5a 0007 2e 5c 0000 2f 5e 0020 30 60 0000 index for erase bank area 2 31 62 003e 32 64 0000 33 66 0000 34 68 0001 index for erase bank area 3 35 6a 0000 36 6c 0000 37 6e 0000 38 70 0000 index for erase bank area 4 39 72 0000 3a 74 0000 3b 76 0000 3c 78 0000
32 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b table 4-4. cfi mode: primary vendor-specifc extended query data values description address (h) (word mode) address (h) (byte mode) data (h) query - primary extended table, unique ascii string, pri 40 80 0050 41 82 0052 42 84 0049 major version number, ascii 43 86 0031 minor version number, ascii 44 88 0031 unlock recognizes address (0= recognize, 1= don't recognize) 45 8a 0000 erase suspend (2= to both read and program) 46 8c 0002 sector protect (n= # of sectors/group) 47 8e 0004 temporary sector unprotect (1=supported) 48 90 0001 sector protect/chip unprotect scheme 49 92 0004 simultaneous r/w operation (0=not supported) 4a 94 0000 burst mode (0=not supported) 4b 96 0000 page mode (0=not supported) 4c 98 0000 minimum acc (acceleration) supply (0= not supported), [d7:d4] for volt, [d3:d0] for 100mv 4d 9a 00a5 maximum acc (acceleration) supply (0= not supported), [d7:d4] for volt, [d3:d0] for 100mv 4e 9c 00b5 top/bottom boot block indicator 02h=bottom boot device 03h=top boot device 4f 9e 0002/0003
33 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b absolute maximum stress ratings operating temperature and voltage electrical characteristics note: 1. minimum voltage may undershoot to -2v during transition and for less than 20ns during transitions. 2. maximum voltage may overshoot to vcc+2v during transition and for less than 20ns during transitions. commercial (c) grade surrounding temperature (t a ) 0c to +70c industrial (i) grade surrounding temperature (t a ) -40c to +85c vcc supply voltages vcc range +2.7 v to 3.6 v surrounding temperature with bias -65 o c to +125 o c storage temperature -65 o c to +150 o c voltage range vcc -0.5v to +4.0 v reset#, a9 and oe# -0.5v to +10.5 v the other pins -0.5v to vcc +0.5v output short circuit current (less than one second) 200 ma
34 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b dc characteristics symbol description min. typ. max. remark iilk input leak 1.0ua iilk9 a9 leak 35ua(0~70 c)/ 45ua(-40~85 c) a9=10.5v iolk output leak 1.0ua icr1 read current(5mhz) 10ma 16ma ce#=vil, oe#=vih icr2 read current(1mhz) 2ma 4ma ce#=vil, oe#=vih icw write current 15ma 30ma ce#=vil, oe#=vih, we#=vil isb standby current 5ua 15ua vcc=vcc max, other pin disable isbr reset current 5ua 15ua vcc=vccmax, reset# enable, other pin disable isbs sleep mode current 5ua 15ua icp1 accelerated pgm current, wp#/acc pin (word/byte) 5ma 10ma ce#=vil, oe#=vih icp2 accelerated pgm current, vcc pin, (word/byte) 15ma 30ma ce#=vil, oe#=vih vil input low voltage -0.5v 0.8v vih input high voltage 0.7xvcc vcc+0.3v vhv very high voltage for hardware protect/unprotect/accelerated program/auto select/temporary unprotect 9.5v 10.5v vol output low voltage 0.45v iol=4.0ma voh1 ouput high voltage 0.85xvcc ioh1=-2ma voh2 ouput high voltage vcc-0.4v ioh2=-100ua vlko low vcc lock-out voltage 2.3v 2.5v
35 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b test condition output load : 1 ttl gate output load capacitance,cl : 30pf rise/fall times : 5ns in/out reference levels :1.5v switching test waveform 1.5v 1.5v test points 3.0v 0.0v output input r1=6.2k ohm r2=1.6k ohm switching test circuit tested device diodes=in3064 or equivalent cl r1 vcc 0.1uf r2 +3.3v
36 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b ac characteristics symbol description min. typ. max. unit taa valid data output after address 70 ns tce valid data output after ce# low 70 ns toe valid data output after oe# low 30 ns tdf data output foating after oe# high 30 ns toh output hold time from the earliest rising edge of address, ce#, oe# 0 ns trc read period time 70 ns tsrw latency between read and write operation (*note 1) 45 ns twc write period time 70 ns tcwc command write period time 70 ns tas address setup time 0 ns tah address hold time 45 ns tds data setup time 45 ns tdh data hold time 0 ns tvcs vcc setup time 200 us tcs chip enable setup time 0 ns tch chip enable hold time 0 ns toes output enable setup time 0 ns toeh output enable hold time read 0 ns toggle & data# polling tws we# setup time 0 ns twh we# hold time 0 ns tcep ce# pulse width 45 ns tceph ce# pulse width high 30 ns twp we# pulse width 35 ns twph we# pulse width high 30 ns tbusy program/erase active time by ry/by# 90 ns tghwl read recover time before write 0 ns tghel read recover time before write 0 ns twhwh1 program operation byte 9 300 us twhwh1 program operation word 11 360 us twhwh1 acc program operation (word/byte) 7 210 us twhwh2 sector erase operation 0.7 2 sec tbal sector add hold time 35 50 us * note 1: sampled only, not 100% tested.
37 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b figure 1. command write operation addresses ce# oe# we# din tds ta h data tdh tcs tch tcwc twph twp toes ta s vih vil vih vil vih vil vih vil vih vil va va: valid address write command operation
38 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b read/reset operation figure 2. read timing waveform addresses ce# oe# ta a we# vih vil vih vil vih vil vih vil voh vol high z high z data valid to e toeh tdf tce trc outputs to h add valid tsrw
39 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b figure 3. reset# timing waveform ac characteristics trh trb1 trp2 trp1 tready2 tready1 ry/by# ce#, oe# reset# reset timing not during automatic algorithms reset timing during automatic algorithms ry/by# ce#, oe# trb2 we# reset# item description setup speed unit trp1 reset# pulse width (during automatic algorithms) min 10 us trp2 reset# pulse width (not during automatic algorithms) min 500 ns trh reset# high time before read min 70 ns trb1 ry/by# recovery time (to ce#, oe# go low) min 0 ns trb2 ry/by# recovery time (to we# go low) min 50 ns tready1 reset# pin low (during automatic algorithms) to read or write max 20 us tready2 reset# pin low (not during automatic algorithms) to read or write max 500 ns
40 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b erase/program operation figure 4. automatic chip erase timing waveform twc address oe# ce# 55h 2aah sa 10h in progress complete va va ta s ta h sa: 555h for chip erase tghwl tch twp tds tdh read status last 2 erase command cycle tbusy trb tcs twph we# data ry/by#
41 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b figure 5. automatic chip erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes no data=ffh ? write data 10h address 555h write data 55h address 2aah data# polling algorithm or toggle bit algorithm auto chip erase completed
42 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b figure 6. automatic sector erase timing waveform twc address oe# ce# 55h 2aah sector address 1 sector address 0 30h in progress complete va va 30h sector address n ta s ta h tbal tghwl tch twp tds tdh twhwh2 read status last 2 erase command cycle tbusy trb tcs twph we# data ry/by# 30h
43 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b figure 7. automatic sector erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h write data 30h sector address write data 55h address 2aah data# polling algorithm or toggle bit algorithm auto sector erase completed no last sector to erase ? yes yes no data=ffh ?
44 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b figure 8. erase suspend/resume flowchart start write data b0h toggle bit checking q6 not toggled erase suspend yes no write data 30h continue erase reading or programming end read array or program another erase suspend ? no yes yes no erase resume
45 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b figure 9. automatic program timing waveform address oe# ce# a0h 555h pa pd status dout va va ta s ta h tghwl tch twp tds tdh twhwh1 last 2 read status cycle last 2 program command cycle tbusy trb tcs twph we# data ry/by# figure 10. accelerated program timing diagram wp#/acc 250ns 250ns vhv (9.5v ~ 10.5v) vil or vih vil or vih
46 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b figure 11. ce# controlled write timing waveform address oe# ce# a0h 555h pa pd status dout va va ta s ta h tghwl tcep tds tdh twhwh1 or twhwh2 tbusy tceph we# data ry/by#
47 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b figure 12. automatic programming algorithm flowchart start write data aah address 555h write data 55h address 2aah write program data/address write data a0h address 555h yes read again data: program data? yes auto program completed data# polling algorithm or toggle bit algorithm next address last word to be programed no no
48 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b sector group protect/chip unprotect figure 13. sector group protect/chip unprotect waveform (reset# control) 150us: sector protect 15ms: chip unprotect 1us vhv vih data sa, a6 a1, a0 ce# we# oe# va va va status va: valid address 40h 60h 60h verification reset#
49 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b figure 14. in-system sector group protect with reset#=vhv start retry count=0 reset#=vhv wait 1us write sector address with [a6,a1,a0]:[0,1,0] data: 60h write sector address with [a6,a1,a0]:[0,1,0] data: 40h read at sector address with [a6,a1,a0]:[0,1,0] wait 150us reset plscnt=1 temporary unprotect mode reset#=vih write reset cmd sector protect done device fail temporary unprotect mode retry count +1 first cmd=60h? data=01h? retry count=25? yes yes yes yes no no no no protect another sector?
50 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b figure 15. chip unprotect algorithm with reset#=vhv write [a6,a1,a0]:[1,1,0] data: 60h write [a6,a1,a0]:[1,1,0] data: 40h read [a6,a1,a0]:[1,1,0] wait 15ms temporary unprotect reset#=vih write reset cmd chip unprotect done retry count +1 device fail all sectors protected? data=00h? last sector verified? retry count=1000? yes yes yes no no no yes protect all sectors start retry count=0 reset#=vhv wait 1us temporary unprotect first cmd=60h? yes no no
51 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b figure 16. temporary sector group unprotect waveform table 5. temporary sector group unprotect reset# ce# we# ry/by# trpvhh 10v vhv 0 or vih vil or vih tvhhwl trpvhh program or erase command sequence parameter alt description condition speed unit trpvhh tvidr reset# rise time to vhv and vhv fall time to reset# min 500 ns tvhhwl trsp reset# vhv to we# low min 4 us
52 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b figure 17. temporary sector group unprotect flowchart start apply reset# pin vhv volt enter program or erase mode (1) remove vhv volt from reset# (2) reset# = vih completed temporary sector unprotected mode mode operation completed notes: 1. temporary unprotect all protected sectors vhv=9.5~10.5v. 2. after leaving temporary unprotect mode, the previously protected sectors are again protected.
53 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b figure 18. silicon id read timing waveform ta a tce ta a to e to h to h tdf data out c2h a7h (top boot) a8h (bottom boot) vhv vih vil a9 add ce# a1, a6 oe# we# a0 data out data q0-q7 vih vil vih vil vih vil vih vil vih vil vih vil vih vil
54 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b write operation status figure 19. data# polling timing waveform (during automatic algorithm) tdf tce tch to e toeh to h ce# oe# we# q7 q0-q6 ry/by# tbusy status data status data complement complement true valid data ta a trc address va va high z high z valid data true
55 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b figure 20. data# polling algorithm read q7~q0 at valid address (note 1) read q7~q0 at valid address start q7 = data# ? q5 = 1 ? q7 = data# ? (note 2) fail pass no no no ye s ye s ye s notes: 1. for programming, valid address means program address. for erasing, valid address means erase sectors address. 2. q7 should be rechecked even q5="1" because q7 may change simultaneously with q5.
56 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b figure 21. toggle bit timing waveform (during automatic algorithm) tdf tce tch to e toeh ta a trc to h address ce# oe# we# q6/q2 ry/by# tbusy valid status (first read) valid status (second read) (stops toggling) valid data va va va va : valid address va valid data
57 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b figure 22. toggle bit algorithm notes: 1. read toggle bit twice to determine whether or not it is toggling. 2. recheck toggle bit because it may stop toggling as q5 changes to "1". read q7-q0 twice q5 = 1? read q7~q0 twice program/erase fail write reset cmd program/erase complete q6 toggle ? q6 toggle ? no (note 1) yes no no yes yes start
58 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b figure 23. byte# timing waveform for read operations (byte# switching from byte mode to word mode) ac characteristics word/byte configuration (byte#) tfhqv telfh dout (q0-q7) dout (q0-q14) va dout (q15) ce# oe# byte# q0~q14 q15/a-1 parameter description speed options unit 70 telf/telfh ce# to byte# from l/h max 5 ns tfqz byte# from l to output hiz max 25 ns tfhqv byte# from h to output active min 70 ns
59 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b recommended operating conditions at device power-up ac timing illustrated in figure a is recommended for the supply voltages and the control signals at device power- up. if the timing in the fgure is ignored, the device may not operate correctly . figure a. ac timing at device power-up vcc address ce# we# oe# data tvr taa tr or tf tr or tf tce tf vcc(min) gnd vih vil vih vil vih vil vih vil vih vil voh high z vol wp#/acc valid ouput valid address tvcs tr toe tf tr symbol parameter min. max. unit tvr vcc rise time 20 500000 us/v tr input signal rise time 20 us/v tf input signal fall time 20 us/v tvcs vcc setup time 200 us
60 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b latch-up characteristics erase and programming performance tsop pin capacitance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0v vcc. programming specifca - tions assume checkboard data pattern. 2. maximum values are measured at vcc = 3.0 v, worst case temperature. maximum values are valid up to and including 100,000 program/erase cycles. 3. erase/program cycles comply with jedec jesd-47e & a117a standard. parameter limits units min. typ. max. chip erase time 35 50 sec sector erase time 0.7 2 sec erase/program cycles 100,000 cycles chip programming time byte mode 36 108 sec word mode 24 72 sec accelerated byte/word program time 7 210 us word program time 11 360 us byte programming time 9 300 us min. max. input voltage difference with gnd on all pins except i/o pins -1.0v 10.5v input voltage difference with gnd on all i/o pins -1.0v 1.5 x vcc vcc current -100ma +100ma all pins included except vcc. test conditions: vcc = 3.0v, one pin per testing parameter symbol parameter description test set typ max unit cin2 control pin capacitance vin=0 7.5 9 pf cout output capacitance vout=0 8.5 12 pf cin input capacitance vin=0 6 7.5 pf parameter condition min. max. unit data retention 55?c 20 years data retention
61 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b ordering information * 44-pin sop is only for pachinko socket part no. access time (ns) ball pitch/ ball size package remark mx29lv320dtmc-70g 70 - 44 pin sop pb-free mx29lv320dbmc-70g 70 - 44 pin sop pb-free mx29lv320dtti-70g 70 - 48 pin tsop pb-free mx29lv320dbti-70g 70 - 48 pin tsop pb-free mx29lv320dtxbi-70g 70 0.8mm/0.3mm 48-ball tfbga pb-free mx29lv320dbxbi-70g 70 0.8mm/0.3mm 48-ball tfbga pb-free MX29LV320DTXEI-70G 70 0.8mm/0.4mm 48-ball lfbga pb-free mx29lv320dbxei-70g 70 0.8mm/0.4mm 48-ball lfbga pb-free
62 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b part name description mx 29 lv 70 d t t i g option: g: pb-free package speed: 70: 70ns temperature range: c: commercial (0c to 70c) i: industrial (-40c to 85c) package: boot block type: t: top boot b: bottom boot revision: d density & mode: 320: 32mb, x8/x16 boot block type: lv: 3v device: 29:flash 320 m: sop t: tsop xb: tfbga (0.8mm ball pitch, 0.3mm ball size) xe: lfbga (0.8mm ball pitch, 0.4mm ball size)
63 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b package information
64 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b
65 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b 48-ball tfbga (for mx29lv320d txbi/bxbi)
66 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b 48-ball lfbga (for mx29lv320d txei/bxei)
67 p/n:pm1281 rev. 1.2, oct. 02, 2009 mx29lv320d t/b revision history revision no. description page date 1.0 1. removed "preliminary" p5 aug/14/2008 1.1 1. added tsrw (ac/waveform) p36,38 may/18/2009 2. added pin description note for wp#/acc pin p8 3. added 20 years data retention condition p5-6, 60 4. revised figure 19. data# polling timing waveform p54 1.2 1. modifed sa44/sa45 address p12 oct/02/2009
mx29lv320d t/b 68 m acronix i nternational c o., l td. macronix offces : taiwan headquarters, fab2 macronix, international co., ltd. 16, li-hsin road, science park, hsinchu, taiwan, r.o.c. tel: +886-3-5786688 fax: +886-3-5632888 taipei offce macronix, international co., ltd. 19f, 4, min-chuan e. road, sec. 3, taipei, taiwan, r.o.c. tel: +886-2-2509-3300 fax: +886-2-2509-2200 macronix offces : china macronix (hong kong) co., limited. 702-703, 7/f, building 9, hong kong science park, 5 science park west avenue, sha tin, n.t. tel: +86-852-2607-4289 fax: +86-852-2607-4229 macronix (hong kong) co., limited, suzhou offce no.5, xinghai rd, suzhou industrial park, suzhou china 215021 tel: +86-512-62580888 ext: 3300 fax: +86-512-62586799 macronix (hong kong) co., limited, shenzhen offce room 1401 & 1404, block a, tianan hi-tech plaza tower, che gong miao, futiandistrict, shenzhen prc 518040 tel: +86-755-83433579 fax: +86-755-83438078 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifcations without notice. macronix offces : japan macronix asia limited. nkf bldg. 5f, 1-2 higashida-cho, kawasaki-ku kawasaki-shi, kanagawa pref. 210-0005, japan tel: +81-44-246-9100 fax: +81-44-246-9105 macronix offces : korea macronix asia limited. #906, 9f, kangnam bldg., 1321-4, seocho-dong, seocho-ku, 135-070, seoul, korea tel: +82-02-588-6887 fax: +82-02-588-6828 macronix offces : singapore macronix pte. ltd. 1 marine parade central, #11-03 parkway centre, singapore 449408 tel: +65-6346-5505 fax: +65-6348-8096 macronix offces : europe macronix europe n.v. koningin astridlaan 59, bus 1 1780 wemmel belgium tel: +32-2-456-8020 fax: +32-2-456-8021 macronix offces : usa macronix america, inc. 680 north mccarthy blvd. milpitas, ca 95035, u.s.a. tel: +1-408-262-8887 fax: +1-408-262-8810 macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and mili - tary application. macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of macronix's products in the prohibited applications. copyright? macronix international co., ltd. 2006~2009. all rights reserved. macronix, mxic, mxic logo, mx logo, are trademarks or registered trademarks of macronix international co., ltd.. the names and brands of other companies are for identifcation purposes only and may be claimed as the property of the respective companies.

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