View M62420AFP_3948188.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev.1.0, sep.17.2 003, page 1 of 16 m62420sp/ fp/ afp 2ch electronic volume with tone by i 2 c bus system rej03f0051-0100z rev.1.0 sep.17.2003 description m62420sp/fp/afp is the tone and volume controller which is controlled by i 2 c bus. this ic can apply the broad application because of low noise and distortion. M62420AFP changes the slave address from m62420fp. features ? tone(bass/treble) control and 1 db step volume control are enabled. ? low noise and low distortion . v no = 4.5 vrms, cthd=0.1% max ? controlling by serial data in conformity to the i 2 c bus format . applications ? tv, mini-stereo, etc recommended operating condition ? supply voltage range: 8.5 to 9.5 v (analog) 4.5 to 5.5 v (digital) ? rated supply voltage: 9 v (analog) 5 v (digital) system block diagram volume lch in scl sda rch in lch out rch out i c bus interface volume tone control bass treble tone control bass treble 2 m62420sp/fp
m62420sp/ fp/ afp rev.1.0, sep.17.2 003, page 2 of 16 block diagram and pin configuration dgnd avdd agnd ch1 in ch2 in sda scl out2 bass1 t re1 out1 dvdd simin 1 simout 1 bass2 tre2 simin 2 simout2 reset ref 5678 910 11 12 13 14 15 16 17 18 19 20 1 234 ref ref tone amp1 volamp1 vr1 6.5k s1 s3 s5 s7 vr3 vr5 136k ref 1.8k simamp1 ref tone amp2 volamp2 vr2 s2 s4 s6 s8 vr6 vr4 136k ref 1.8k simamp2 6.5k 6.5k 6.5k i c bus inter face 2 control logic
m62420sp/ fp/ afp rev.1.0, sep.17.2 003, page 3 of 16 pin description pin no. pin name i/o description 1 ref i reference voltage terminal for analog 2 ch1 in i input terminal (ch1) 3 simin1 i pin for capacitor of simulated inductor 1 4 simout 1 o pin for capacitor of simulated inductor 1 5 bass1 i pin for capacitor of ch1-side bass setting 6 tre1 i pin for capacitor of ch1-side treble setting 7 vol out1 o output terminal (ch1) 8 dgnd i digital gnd 9 sda i/o i/o terminal of data i 2 c bus format 10 scl i input terminal of clock i 2 c bus format 11 reset i reset terminal of built-in logic circuit 12 dvdd i vdd for digital circuit 13 agnd i gnd for analog circuit 14 vol out2 o output terminal (ch2) 15 tre2 i pin for capacitor of ch2-side treble setting 16 bass2 i pin for capacitor of ch2-side bass setting 17 simout2 o pin for capacitor of simulated inductor 2 18 simin 2 i pin for capacitor of simulated inductor 2 19 ch2 in i input terminal (ch2) 20 avdd i vcc for analog circuit absolute maximum ratings (ta = 25 c) symbol parameter condition limits unit avdd analog supply voltage 10.0 v dvdd digital supply voltage 7.0 v pd power dissipation ta 25c 750 mw k thermal derating ratio ta > 25c 7.5 mw / c topr operating temperature ?20 to +75 c tstg storage temperature ?40 to +125 c
m62420sp/ fp/ afp rev.1.0, sep.17.2 003, page 4 of 16 thermal derating curves power dissipation pd [mw] ambient temperature ta [?c] 0 200 600 0 25 50 75 100 125 150 750mw 400 800 1000 375mw 275mw 550mw sp fp recommended operating condition (ta = 25 c unless otherwise noted) item symbol condition min typ max unit analog supply voltage avdd 8.5 9.0 9.5 v digital supply voltage dvdd 4.5 5.0 5.5 v h level input voltage (logic circuit) vih 0.7dvdd ? vdd v h level input voltage (logic circuit) vil 0 ? 0.3dvdd v
m62420sp/ fp/ afp rev.1.0, sep.17.2 003, page 5 of 16 electrical characteristics (dc) ( ta = 25c, avdd = 9 v, dvdd = 5 v and tone, bassboost = 0 db unless otherwise noted ) (1) supply voltage item symbol conditions limit unit min. typ. max. analog supply current icc avdd = 9.0 v measure terminal = 20 pin no signal input ? 10 20 ma digital supply current idd dvdd = 5 v measure terminal = 12 pin no signal input ?02 a (2) i/o characteristics item symbol conditions limit unit min. typ. max. maximum input voltage vim 2,19 pin input, 7,14 pin output rl = 10 k, thd = 1%, f = 1 khz att = -6db 2.0 3.2 ? vrms output voltage vodc 7 pin, 14 pin, no signal 4.35 4.5 4.65 v gain gv vin = 0dbm, flat, f = 1 khz 2-7pin 19-14pin gain ?2 0 2 db output noise voltage vono jis-a filter, no signal, rg =10 k ? 7,14 pin ?4.530 vrms total harmonic distortion thd 7 pin, 14 pin f=1khz vo = 0.5 vrms, rl = 10k ? lpf = 30 khz ? 0.05 0.1 % channel separation ct rl = 10 k s:vin = 1 vrms,f=1khz m:rg = 10 k ? , jis-a filter ? ?100 ?70 db (3) tone characteristics item symbol conditions limit unit min. typ. max. gbassb f = 100 hz 9 12 15 db tone control gain (bass) gbassc ?15 ?12 ?9 db gtrebb f = 10 hz 9 12 15 db tone control gain (treble) gtrebc ?15 ?12 ?9 db (4) volume characteristics item symbol conditions limit unit min. typ. max. maximum attenuation attmax ?108 ?100 ?80 db minimum attenuation attmin f = 1khz, vin = 0dbm 2 pin to 7 pin 19 pin to 14pin gain jis-a filter ?1.5 0 1.5 db
m62420sp/ fp/ afp rev.1.0, sep.17.2 003, page 6 of 16 function explanation (1) equivaration circuit of tone control the resonance circuit is able to construct by using built- in amplifier for simulated inductor. (shows the constant as follow) r3 c1 c2 fig2. the equivalent circuit used l. c1 l r3 ( ex ) bass band ( f=100hz ) r1=1.8k ? , r2=136k ? c1=0.47f , c2=0.022f center frequency f0 = 1 / 2 c1 ? c2 ? r1 ? r2 [hz] q = ( c2 ? r2 ) / ( c1 ? r1 ) fig1 is equal to fig2. the following relation is concluded. incide ic r1 (=1.8k ? ) r2 (=136k ? ) simamp fig1. the circuit used simurated inductor. l=c2 ? er1 ? er2 ref ref
m62420sp/ fp/ afp rev.1.0, sep.17.2 003, page 7 of 16 i 2 c bus input data format ( 2 ) sub address sa a a p starting term ( 1 ) slave address ( 2 ) sub address ( 3 ) data ( 1 ) slave address suba6 suba5 suba4 suba3 suba2 suba1 suba0 suba7 empty slot channel2 volume mode 1: on 0: off 1: on 0: off bass level mode treble level mode 1: on 0: off 1: on 0: off input direction acknowledge bit ending term the following sub address is defined at this ic. channel1 volume mode a6 a5 a4 a3 a2 a1 a0 r/w 10000000 m62420sp / fp M62420AFP a6 a5 a4 a3 a2 a1 a0 r/w 10000010 mute mode 1: on 0: off acknowledge bit
m62420sp/ fp/ afp rev.1.0, sep.17.2 003, page 8 of 16 suba3 : 0 suba2 : 0 suba0 : 0 , 1 , 1 volume code the volume control is enabled at following condition. suba1 : 1 , 0 , 1 (either bit is 1) (both bits are 0) * 2db,3db setting is enabled at less than 42db step. d4 d3 d2 d1 d0 att 0db 2db 4db 6db 8db 10db 12db 14db 16db 18db 20db 22db 24db 26db 28db 30db 32db 36db 38db 40db 42db 46db 50db 34db 54db 58db 62db 66db 70db 74db 78db db h l h l h l h l h l h l h l h l h l h l h l h l h l h l h l h l h h l l h h l l h h l l h h l l h h l l h h l l h h l l h h l l h h h h l l l l h h h h l l l l h h h h l l l l h h h h l l l l h h h h h h h h l l l l l l l l h h h h h h h h l l l l l l l l h h h h h h h h h h h h h h h h l l l l l l l l l l l l l l l l d5 d6 att 0db 1db * 2db * 3db h l h l h h l l ( 3 ) -1: volume control
m62420sp/ fp/ afp rev.1.0, sep.17.2 003, page 9 of 16 tone code suba1 : 0 suba0 : 0 suba2 : 0 , 1 , 1 the tone level controlling is enabled at following condition. suba3 : 1 , 0 , 1 (either bit is 1) (both bits are 0) d7 d6 d5 d4 treble 0db -2db -4db -6db -8db -10db -12db h h h h h h l l l l l 2db 4db 6db 8db 10db 12db bass d3 d2 d1 d0 l l h h h h h h l l l l l l l h l l h h l l l h h l l h l h l h l h l h l h l h l h h h h h h l l l l l l l h h h h h h l l l l l l l h l l h h l l l h h l l h l h l h l h l h l h l h l hhhh lhhh hlll non-used code ( 3 ) -2 : tone level control ( 3 ) -3 : mute mode suba4 : 1 suba1 : no definition suba0 : no definition suba3 : no definition suba2 : no definition the mute mode is enabled at following condition.
m62420sp/ fp/ afp rev.1.0, sep.17.2 003, page 10 of 16 data and clock caution s d a (in) s c l s d a (out) 1 2 ~ 7 8 9 s p ack start acknowledge stop start this term is defined by sda(in) falling edge at scl h . this term is defined by sda(in) rising edge at scl h . stop the sda(in) level never change at sck=h except start and stop . the sda(in) is enabled at scl rising edge and h . data transmisson acknowledge transmitter must send h during ninth clock pulse of scl . the case of finished receiving , the receiver replies l synchronized to falling edge of eighth pulse . and restart receiving the transmitted data synchronized to falling edge of ninth pulse .
m62420sp/ fp/ afp rev.1.0, sep.17.2 003, page 11 of 16 bus line timing specification t r, t f t buf t low t high t hd:dat t su:dat sda scl v il v ih v il v ih t hd:sta t su:sta t su:sto ssps parameter symbol min max units min. input low voltage v il ?0.5 1.5 v max. input high voltage v ih 3.0 5.5 v scl clock frequency f scl 0 100 khz time the bus must be free befor e a new transmission can start t buf 4.7 s hold time start condition. after this period the firs t clock pulse is generated t hd:sta 4.0 s the low period of the clock t low 4.7 s the high period of the clock t high 4.0 s set up time for start condition (only relevant for a repeated start condition) t su:sta 4.7 s hold time data t hd:dat 0 s set-up time data t su:dat 250 ns rise time of both sda and scl lines t r 1000 ns fall time of both sda and scl lines t f 300 ns set-up time for stop condition t su:sto 4.0 s
m62420sp/ fp/ afp rev.1.0, sep.17.2 003, page 12 of 16 level diagram volamp1 6.5k ? toneamp1 ref 136k 1.8k ref g1 0db to -db g1 g2 -12db to +12db 6.5k ? ch1 in ch2 in ch1 out ch2 out same to ch1
m62420sp/ fp/ afp rev.1.0, sep.17.2 003, page 13 of 16 logic circuit sda scl shift register level shifter decoder, latch for volume control sub-address latch circuit slave address compare circuit bi-direct control tone amp1 ref volamp1 analog block decoder, latch for tone control acknowledge generator timing generator
m62420sp/ fp/ afp rev.1.0, sep.17.2 003, page 14 of 16 application example mpu vcc agnd dgnd 2.2 f 2.2 f 2.2?f 2.2? 470 f in2 in1 out1 out2 ref ref 0.033 f 0.47 f 0.022 f 4.7k reference circuit example 1.8k 5678 910 11 12 13 14 15 16 17 18 19 20 1 234 ref ref tone amp1 volamp1 vr1 6.5k s1 s3 s5 s7 vr3 vr5 136k ref 1.8k simamp1 ref tone amp2 volamp2 vr2 s2 s4 s6 s8 vr6 vr4 136k ref 1.8k simamp2 6.5k 6.5k 6.5k 0.033 f 0.47 f 0.022 f 1.8k i c bus inter face 2 control logic reference voltage dvdd 1000pf 100k 430 430 4.7k 10k 10k 10k 10k
m62420sp/ fp/ afp rev.1.0, sep.17.2 003, page 15 of 16 package dimensions sop20-p-300-1.27 weight(g) ? jedec code 0.26 eiaj package code lead material cu alloy 20p2n-a plastic 20pin 300mil sop symbol min nom max a a 2 b c d e l l 1 y dimension in millimeters h e a 1 i 2 ? ? .35 0 0 .18 0 .5 12 .2 5 ? .5 7 .4 0 ? ? ? ? .27 1 .1 0 ? .8 1 .4 0 .2 0 .6 12 .3 5 .27 1 .8 7 .6 0 .25 1 ? ? .62 7 ? .2 0 .1 2 ? .5 0 .25 0 .7 12 .4 5 ? .1 8 .8 0 ? .1 0 ? b 2 0.76 ? 0 8 e e 1 20 11 10 1 h e e d e y f a a 2 a 1 l 1 l c e b 2 e 1 i 2 recommended mount pad detail f detail g z z 1 x ? ? z 1 ? 0.585 ? ? ? ? 0.735 0.25 z b x m g mmp
m62420sp/ fp/ afp rev.1.0, sep.17.2 003, page 16 of 16 sdip20-p-300-1.78 weight(g) ? jedec code 1.0 eiaj package code 20p4b plastic 20pin 300mil sdip symbol min nom max a a 2 b b 1 c e d l dimension in millimeters a 1 0.51 ? ? ? 3.3 ? 0.38 0.48 0.58 0.9 1.0 1.3 0.22 0.27 0.34 18.8 19.0 19.2 6.15 6.3 6.45 ? 1.778 ? ? 7.62 ? 3.0 ? ? ? 0 15 ? ? 4.5 e e 1 20 11 10 1 e c e 1 a 2 a 1 b b 1 e la seating plane d lead material alloy 42/cu alloy mmp
? 2003. renesas technolo gy corp., all ri g hts reserved. printed in japan . colo p hon 1.0 keep safet y first in y our circuit desi g ns ! 1. renesas technolo gy corp. puts the maximum effort into makin g semiconductor products better and more reliable, but there is alwa y s the possibilit y that trouble m a y occur with them. trouble with semiconductors ma y lead to personal in j ur y , fire or propert y dama g e . remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placem ent of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas tech nology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technolo gy corp. is necessar y to reprint or reproduce in whole or in part these materials . 7 . if these products or technolo g ies are sub j ect to the japanese export control restrictions, the y must be exported under a license from the japanese g overnment and cannot b e imported into a countr y other than the approved destination. an y diversion or reexport contrar y to the export control laws and re g ulatio n s of japan and/or the countr y of destination is prohibited . 8. please contact renesas technolo gy corp. for further details on these materials or the products contained therein . s ales strate g ic plannin g div. nippon bld g ., 2-6-2, ohte-machi, chi y oda-ku, tok y o 100-0004, japa n htt p ://www.renesas.co m renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500 fax: <1> (408) 382-7501 renesas technology europe limited. dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585 100, fax: <44> (1628) 585 900 renesas technology europe gmbh dornacher str. 3, d-85622 feldkirchen, germany tel: <49> (89) 380 70 0, fax: <49> (89) 929 30 11 renesas technology hong kong ltd. 7/f., north tower, world finance centre, harbour city, canton road, hong kong tel: <852> 2265-6688, fax: <852> 2375-6836 renesas technology taiwan co., ltd. fl 10, #99, fu-hsing n. rd., taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. 26/f., ruijin building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1, harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices

▲Up To Search▲

Price & Availability of M62420AFP

	To Download M62420AFP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .