14-bit registered buffer pc2700-/pc3200-compliant cy2sstv16857 rev 1.0, november 21, 2006 page 1 of 7 2200 laurelwood road, santa clara, ca 95054 tel:(4 08) 855-0555 fax:(408) 855-05 50 www.spectralinear.com features ? differential clock inputs up to 280 mhz ? supports lvttl switchin g levels on the reset pin ? output drivers have controlled edge rates, so no external resistors are required ? two kv esd protection ? latch-up performance exceeds 100 ma: jesd78, class ii ? conforms to jedec std (j esd82-3) for buffered ddr dimms ? 48-pin tssop description this 14-bit registered buffer is designed specifically for 2.3v to 2.7v v dd operation and is characterized for operation from 0c to + 85c. all inputs are compatible with the jedec standard for sstl_2, except the lvcmos reset (reset ) input. all outputs are sstl_2, class ii-compatible. the sstv16857 operates from a differential clock (clk and clk ). data is measured at the crossing of clk going high, and clk going low. when reset is low, the differential input receivers are disabled, and undriven (floati ng) data, clock, and ref voltage inputs are allowed. in addition, when reset is low, all registers are reset and all outputs force to the low state. the lvcmos reset input must always be held at a valid logic high or low level. to ensure defined outputs from the register before a stable clock has been supplied, reset must be held in the low state during power-up. in the ddr registered dimm application, reset is specified to be completely asynchronous with respect to clk and clk . therefore, no timing relationship can be guaranteed between the two. when entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers, thus ensuring no glitches on the output. however, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. as long as the data inputs are low, and the clock is stable during the time from the low-to-high trans ition of reset until the input receivers are fully enabled, the design must ensure that the outputs will remain low. block diagram pin configuration 1d c1 r reset clk clk vref d1 q1 to 13 other channels 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 q1 q2 vss vddq q3 q4 q5 vss vddq q6 q7 vddq vss q8 q9 vddq vss q10 q11 q12 vddq vss q13 q14 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 d1 d2 vss vdd d3 d4 d5 d6 d7 clk clk vdd vss vref reset d8 d9 d10 d11 d12 vdd vss d13 d14 cy2sstv16857
cy2sstv16857 rev 1.0, november 21, 2006 page 2 of 7 pin description pin name i/o type description 34 reset i 3,8,13,17,22,27, 36,46 vss ground ground . 28, 37, 45 vdd power 2.5v nominal supply voltage . 1, 2, 5, 6, 7, 10, 11, 14, 15, 18, 19, 20, 23, 24 q(1:14) o data outputs, sstl_2, class ii output . 25, 26, 29, 30, 31, 32, 33, 40, 41, 42, 43, 44, 47, 48 d(1:14) i data input clocked on the crossing of the rising edge of clk, and the falling edge of clk . 39, 38 clk , clk i/i differential clock input . 4, 8, 12, 16, 21 vddq power power supply voltage quiet, 2.5v nominal . 35 vref i input reference voltage, 1.25v nominal .
cy2sstv16857 rev 1.0, november 21, 2006 page 3 of 7 absolute maximum conditions [1, 2, 3] this device contains circuitry designed to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, v in and v out should be constrained to the range: v ss < (v in or v out ) < v dd . unused inputs must always be tied to an appropriate logic voltage level (either v ss or v dd ). parameter description condition min. max. unit v dd supply voltage [4] non-functional 2.3 2.7 vdc v dd operating voltage [4] functional 2.3 2.7 vdc v in input voltage relative to v ss 0v dd vdc v out output voltage relative to v ss v ddq vdc i out dc output current 50 ma i ik continuous clamp current v i < 0 or v i > v ss 50 ma i ok continuous clamp current v o < 0 ?50 ma i dd/ i ss continuous current through each v dd or v ss 100 ma lu i latch up immunity exceeds spec of 100 ma r ps power supply ripple ripple frequency < 100 khz 150 mvp-p t s temperature, storage non-functional ?65 +150 c t a temperature, operating ambient functional 0 +70 c t j temperature, junction functional 165 c ? jc dissipation, junction to case mil-spec 883e method 1012.1 22.23 c/w ? ja dissipation, junction to ambient jedec (jesd 51) 74.52 c/w ul fl flammability by design and verification v ? 0 grade msl moisture sensitivity by design and verification msl ? 1 grade esd h esd protection (human body model) 2000 v table 1. dc electrical specifications (v dd = temperature = 0c to +85 c) parameter description condition min. typ. max. unit v dd supply voltage pc1600,2100,2700 pc3200 2.5 2.6 2.7 v v ddq output supply voltage pc1600,2100,2700 pc3200 2.5 2.6 2.7 v v ref reference voltage (v ref = v ddq /2) pc1600,2100,2700 pc3200 1.25 1.3 1.35 v v tt termination voltage v ref ? 40 mv v ref v ref +4 0 mv v v ih input voltage, high reset 1.7 v v il input voltage, low reset 0.7 v v ol output voltage, low v dd /v ddq = 2.3v to 2.7v, i ol = 100 a, v dd = 2.3 to 2.7v 0.2 v v dd /v ddq = 2.3v, i ol = 16 ma, v dd =2.3v 0.35 notes: 1. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing i s not required. 2. stresses greater than those listed under absolute maximum rating s may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above th ose indicated in the operational sections of this specificatio n is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 3. all terminals except v dd . 4. v dd /v ddq terminals.
cy2sstv16857 rev 1.0, november 21, 2006 page 4 of 7 v oh output voltage, high v dd /v ddq = 2.3v to 2.7v, i oh = ?100 a, v dd =2.3 to 2.7v v dd ? 0.2 v v dd /v ddq = 2.3v, i oh = ?16 ma 1.95 i il input current data inputs v i = 1.7v or 0.8v, v ref = 1.15v or 1.35v, v dd = 2.7v 5 a v i = 2.7v or 0,v ref = 1.15v or 1.35v, v dd = 2.7v 5 a v i = 1.7v or 0.8v, v ref = 1.15v or 1.35v, v dd = 3.6v 5 a v i = 2.7v or 0 5 a clk, clk v i = 1.7v or 0.8v, v ref = 1.15v or 1.35v 1 a v i = 2.7v or 0, v ref = 1.15v or 1.35v, v dd = 2.7v 1 a reset v i = v dd or v ss , v dd = 2.7v 5 a vref v i = 1.5v or 1.35v, v dd = 2.7 5 a i ih input current, high data inputs only ma. i dd dynamic supply current v i = 1.7v or 0.8v, i o = 0, v dd = 2.7v 90 ma v i = 2.7v or 0, i o = 0, v dd = 2.7v 90 ma c in input pin capacitance reset v i = 1.7v or 0.8v, i o = 0, v dd = 2.7v 3pf clock and data inputs 2.5 2.7 3.5 pf l pin pin inductance all 2.1 4.5 nh table 2. ac input electrical specifications (v dd = 2.5 vdc 5%, temperature = 0c to +85c) parameter description condition v dd = 2.5v 0.2v unit min. max. f in input clock frequency clk, clk 200 mhz p w pulse duration clk, clk high or low 3.3 ns t act differential inputs active time da ta inputs must be low after reset high 22 ns t inact differential inputs inactive time data and clock inputs must be held at valid levels (not floating) after reset low 22 ns t set set-up time fast slew rate, (see notes 5 and 7), data before clk, clk 0.75 ns slow slew rate, (see notes 6 and 7), data before clk, clk 0.9 ns t hold hold time fast slew rate, (see notes 5 and 7), data after clk, clk 0.75 ns slow slew rate (see notes 6 and 7), data after clk, clk 0.9 ns i vpp input voltage, pk?pk 360 mv notes: 5. for data signal input slew rate > 1 v/ns. 6. for data signal input slew rate > 0.5 v/ns and < 1 v/ns. 7. clk, clk signals input slew rates are > 1 v/ns. table 1. dc electrical specifications (v dd = temperature = 0c to +85 c) (continued) parameter description condition min. typ. max. unit
cy2sstv16857 rev 1.0, november 21, 2006 page 5 of 7 output buffer characteristics table 3. ac output el ectrical specifications (v dd = 2.5v vdc 5%, temperature = 0c to +85c) parameter descrip tion condition v dd = 2.5v 0.2v unit min. max. f max 280 t del propagation delay from clk/clk to q q1.12.8ns t phl reset q 4.3 ns t r rise time any q 0.85 4 v/ns t f fall time any q 1.0 4 v/ns table 4. output buffer voltage vs. current (v/i) characteristics voltage (v) pull-down pull-up min i (ma) max i (ma) min i (ma) max i (ma) 00000 0.1 6 13 ?5 ?15 0.2 10 25 ?10 ?27 0.3 15 38 ?15 ?38 0.4 19 49 ?19 ?49 0.5 23 60 ?23 ?60 0.6 27 71 ?28 ?72 0.7 30 81 ?31 ?83 0.8 34 91 ?35 ?96 0.9 36 100 ?38 ?104 1.0 38 108 ?40 ?112 1.1 40 115 ?44 ?120 1.2 42 123 ?46 ?125 1.3 43 130 ?48 ?130 1.4 44 137 ?50 ?134 1.5 44 144 ?51 ?137 1.6 45 150 ?52 ?140 1.7 45 158 ?52 ?143 1.8 45 165 ?52 ?146 1.9 45 172 ?53 ?149 2.0 45 179 ?53 ?152 2.1 46 185 ?53 ?154 2.2 46 191 ?54 ?156 2.3 46 196 ?54 ?157 2.4 46 201 ?54 ?159 2.5 46 206 ?54 ?160 2.6 46 211 ?55 ?161 2.7 46 216 ?55 ?162
cy2sstv16857 rev 1.0, november 21, 2006 page 6 of 7 slew rate the following table describes output-buffer slew-rate charac- teristics that are sufficient to meet the requirements of regis- tered ddr dimm performance an d timings. these character- istics are not necessarily production tested but can be guaranteed by design or characterization. compliance with these rates is not mandatory if it can be adequately demon- strated that alternate characteri stics meet the requirements of the registered ddr dimm application. this information does not necessarily have to appear in the device data sheet. obtain rise and fall time measurements by using the same procedure for obtaining ?ramp? data according to the current wia ibis specification. in particul ar it is very important to note that the following slew rates are specified at the output of the die, without package parasitics in the power, ground or output paths. the measurement points are at 20% and 80%. the slew-rate test load shall be a 50-ohm resistor to gnd for rise and a 50-ohm resistor to v ddq for fall. the dv/dt ratio is reduced to v/ns. test configurations [9, 10] v dd = 2.5v 0.2v timing diagrams notes: 8. cl includes probe and jig capacitance. 9. idd tested with clock and data inputs held at vdd or vss, and io = 0 ma. 10. all input pulses are supplied by generators having the following c haracteristics: prr < 10 mhz, zo = 50 ohm input slew rate = 1 v/ns 20% (unless otherwise specified). 11. the outputs are measured one at a time with one transition per measurement. 12. *vtt = vref = vddq/2. 13. **vih = vref + 350 mv (ac voltage levels). 14. ***vil = vref ? 350 mv (ac voltage levels). table 5. output buffer slew-rate characteristics dv/dt min. max. rise 0.85 v/ns 4 v/ns fall 1.00 v/ns 4 v/ns t su t h vicr vi(pp) timing input data input vref* vref* vil*** vih** figure 1. voltage waveforms set-up and hold times [11, 13, 14] lvcmos reset input idd vdd t inact vdd/2 0 v vdd/2 10% 90% t act iddh iddl figure 2. voltage waveforms enable and disable times low- and high-level enabling [11] vtt t plh t phl vi(pp) voh vol input output vicr vtt vicr figure 3. voltage waveforms propagation delay times [12] t phl voh lvcmos reset input output vdd/2 vtt vih vil vol figure 4. voltage waveforms propagation delay times [11 from output under test cl = 30 pf rl = 50 ohm vtt test point figure 5. load circuit [8] vref* vref* vih** vil*** input t w figure 6. voltage waveforms pulse duration [13, 14]
rev 1.0, november 21, 2006 page 7 of 7 cy2sstv16857 while sli has reviewed all information herein for accuracy and re liability, spectra linear inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. this product i s intended for use in normal commercial applications and is not warranted nor is it inte nded for use in life support, critical medical instruments, o r any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursu ant to additional processing by spectra linear in c., and expressed written agreement by spectra linear inc. spectra linear inc. reserves the righ t to change any circuitry or specification without notice. package drawing and dimensiona ordering information part number package type product flow cy2sstv16857zc 48-pin tssop commercial, 0 to 70 c cy2sstv16857zct 48-pin tssop ?tape and reel commercial, 0 to 70 c CY2SSTV16857ZI 48-pin tssop industrial, ?40 to 85 c CY2SSTV16857ZIt 48-pin tssop ?tape and reel industrial, ?40 to 85 c lead-free cy2sstv16857zxc 48-pin tssop commercial, 0 to 70 c cy2sstv16857zxct 48-pin tssop ?tape and reel commercial, 0 to 70 c cy2sstv16857zxi 48-pin tssop industrial, ?40 to 85 c cy2sstv16857zxit 48-pin tssop ?tape and reel industrial, ?40 to 85 c 1.100[0.043] 0.051[0.002] 0.851[0.033] seating plane 1 24 0.508[0.020] 0.500[0.019] 7.950[0.313] 0.25[0.010] 6.198[0.244] 12.395[0.488] 8.255[0.325] 5.994[0.236] 0.950[0.037] 0.500[0.020] bsc 12.598[0.496] 0.152[0.006] 0.762[0.030] 0-8 dimensions in mm[inches] min. max. max. 0.170[0.006] 0.279[0.011] gauge plane 0.20[0.008] 25 48 0.100[0.003] 0.200[0.008] reference jedec mo-153 package weight 0.33gms part # z4824 standard pkg. zz4824 lead free pkg. 48-lead (240-mil) tssop ii z4824
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