nc pd4 pd1 d0 d1 d2 d3 vcc a7 a8 a9 d4 d5 d6 d7 we a14 cs1 cs3 a16 gnd d16 d17 d18 d19 a10 a11 a12 a13 d20 d21 d22 d23 gnd a19 nc 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 nc pd3 gnd pd2 d8 d9 d10 d11 a0 a1 a2 d12 d13 d14 d15 gnd a15 cs2 cs4 a17 oe d24 d25 d26 d27 a3 a4 a5 vcc a6 d28 d29 d30 d31 a18 a20 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 top view pd2 = pd3 = gnd pd1 = pd4 = open features 2m x 32 sram module sys322000zk-015/020/025 issue 1.2 : april 1999 ? access times of 15/20/25 ns. ? 72 pin zig-zag-in-line package (zip). ? 5 volt supply 10%. ? operating power (32bit mode) 7.60w (max) standby current (cmos) 935mw (max) ? completely static operation. ? equal access and cycle times. ? all inputs and outputs directly ttl compatible. ? on-board supply decoupling capacitors. pin definition description the sys322000zk is a plastic 64mbit static ram module offered in a low profile 72 pin zip package, organised as 2m x 32. the module utilises sixteen 512k x 8 sram's housed in tsop ii packages, surface mounted onto a dual fr4 epoxy pcb construction. four chip selects and the highest order address line are used to independently enable the eight bytes as well as the high or low block of addressable memory space. reading or writing is executed on individual or any combination of multiple bytes. the module also incorporates on-board decoupling. block diagram see page 7. pin functions address inputs a0 - a20 data input/output d0 - d31 chip selects cs1~4 write enable we output enable oe no connect nc power (+5v) v cc ground gnd package details plastic 72 pin zip 11403 west bernado court, suite 100, san diego, ca 92127. tel no: (619) 674 2233, fax no: (619) 674 2230
sys322000zk - 015/020/025 issue 1.2 april 1999 2 parameter symbol test condition min typ max unit i/p leakage current address,oe,we i li 0v < v in < v cc -32 - 32 a output leakage current 8-bit mode i lo cs = v ih, v i/o = gnd to v cc -32 - 32 a operating supply current 32-bit mode i cc1 min. cycle, cs = v il ,v il v cc -0.2v, 0.2 sys322000zk - 015/020/025 issue 1.2 april 1999 3 * input pulse levels: 0v to 3.0v * input rise and fall times: 3ns * input and output timing reference levels: 1.5v * output load: see diagram * v cc =5v10% ac test conditions output load cs oe we data pins supply current mode h x x high impedance i sb1 , i sb2 , i sb3 standby l l h data out i cc1 read l h l data in i cc1 write l l l data in i cc1 write l h h high-impedance i sb1 , i sb2 , i sb3 high-z operation truth table 645 100pf i/o pin 1.76v w notes : h = v ih : l =v il : x = v ih or v il
sys322000zk - 015/020/025 issue 1.2 april 1999 4 015 020 025 parameter symbol min max min max min max write cycle time t wc 15 - 20 - 25 - chip selection to end of write t cw 12 - 15 - 20 - address valid to end of write t aw 12 - 15 - 20 - address setup time t as 0-0-0- write pulse width t wp 10 - 12 - 15 - write recovery time t wr 0-0-0- write to output in high z t whz 0709010 data to write time overlap t dw 8-10-12- data hold from write time t dh 0-0-0- output active from end of write t ow 3-3-3- write cycle 015 020 025 parameter symbol min max min max min max read cycle time t rc 15 - 20 - 25 - address access time t aa -15-20-25 chip select access time t acs -15-20-25 output enable to output valid t oe -7-9-13 output hold from address change t oh 3-3-3- chip selection to output in low z t clz 3-3-3- output enable to output in low z t olz 0-0-0- chip deselection to o/p in high z t chz 0709010 output disable to output in high z t ohz 0709010 read cycle ac operating conditions
sys322000zk - 015/020/025 issue 1.2 april 1999 5 read cycle timing waveform (1,2) write cycle no.1 timing waveform (1,4) t wr(7) as(6) t cw t wp(2) t dw dh aw don't care t t t t t wc ohz(3,9) address oe cs1~4 we dout din high-z high-z ow t (8) data valid oe t acs t clz (4,5) t ohz (3) t t olz aa oh chz (3,4,5) data valid t t t t rc address cs1~4 dout oe don't care. ac read characteristics notes (1) we is high for read cycle. (2) all read cycle timing is referenced from the last valid address to the first transition address. (3) t chz and t ohz are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. (4) at any given temperature and voltage condition, t chz (max) is less than t clz (min) both for a given module and from module to module. (5) these parameters are sampled and not 100% tested.
sys322000zk - 015/020/025 issue 1.2 april 1999 6 write cycle no.2 timing waveform (1,5) ac write characteristics notes (1) all write cycle timing is referenced from the last valid address to the first transition address. (2) all writes occur during the overlap of cs1~4 and we low. (3) if oe, cs1~4, and we are in the read mode during this period, the i/o pins are low impedance state. inputs of opposite phase to the output must not be applied because bus contention can occur. (4) dout is the read data of the new address. (5) oe is continuously low. (6) address is valid prior to or coincident with cs1~4 and we low, too avoid inadvertant writes. (7) cs1~4 or we must be high during address transitions. (8) when cs1~4 are low : i/o pins are in the output state. input signals of opposite phase leading to the output should not be applied. (9) defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. these parameters are sampled and not 100% tested. t aw t cw wr(7) wc as(6) dw dh oh ow whz(3,9) wp(2) don't t t t t t address cs1~4 we dout din t t t t care high-z high-z (4) (8) data valid
sys322000zk - 015/020/025 issue 1.2 april 1999 7 block diagram a0 ~ a18 /oe /we /cs1 /cs2 a19 a20 d0~7 d0~7 d0~7 d0~7 d8~15 d8~15 d8~15 d8~15 d16~23 d16~23 d16~23 d16~23 d24~31 d24~31 d24~31 d24~31 a19 a20 /cs3 /cs4 decoder decoder 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram
sys322000zk - 015/020/025 issue 1.2 april 1999 8 ordering information package information dimensions in mm plastic 72 pin zig-zag-in-line package (zip) 4.00 3.20 8.50 max. 97.80 max. 19.00 max. 2.54 typ. 1.27 typ. note : although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantability or fitness for a particular purpose. our products are subject to a constant process of development. data may be changed at any time without notice. our products are not authorised for use as critical components in life support devices or systems without the express written approval of a company director. speed 015 = 15 ns 020 = 20 ns 025 = 25 ns temperature range blank = commercial temp. i = industrial temp. package zk = plastic 72 pin zip organisation 322000 = 2m x 32 memory type sys = static ram sys322000zki-15
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