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caution: these devices are sensitive to electrostati c discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved 1 ? pinouts hs1-1840rh/883s 28 pin ceramic sidebraze dip case outline d-10,compliant to mil-m-38510 package top view hs9-1840rh/883s 28 pin ceramic sidebraze flatpack case outline f-11a, compliant to mil-m-38510 package top view +vs nc nc in 16 in 15 in 14 in 13 in 12 in 11 in 10 in 9 gnd (+5vs) vref addr a3 out in 8 in 7 in 6 in 5 in 3 in 1 enable addr a0 addr a1 addr a2 -vs in 4 in 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 +vs nc nc in 16 in 15 in 14 in 13 in 12 in 11 in 10 in 9 gnd (+5vs) vref addr a3 out -vs in 8 in 7 in 6 in 5 in 4 in 3 in 2 in 1 enable addr a0 addr a1 addr a2 features ? this circuit is processed in accordance to mil-std-883 and is fully conformant under the provisions of paragraph 1.2.1. ? radiation environment - gamma rate 1 x 10 8 rad(si)/s - gamma dose ( ) 2 x 10 5 rad(si) ? low power consumption ? fast access time 1000ns ? high analog input impedance 500m ? during power loss (open) ? dielectrically isolated device islands ? excellent in hi-rel redundant systems ? break-before-make switching ? no latch-up description the hs-1840rh/883s is a radiation hardened, monolithic 16 channel multip lexer constructed with the intersil linear dielectric isolation cmos process. it is designed to provide a high input impedance to the analog source if device power fails (open) or the analog signal voltage inadvertently exceeds the supply rails during powered operation. excellent for use in redundant applications, since the secondary device can be operated in a standby unpowered mode affording no additional power drain. more significantly, a very high impedance exists between the active and inactive devices preventi ng any interaction. one of sixteen channel selection is controlled by a 4-bit binary address plus an enable-inhibit input which conve- niently controls the on/off operation of several multiplexers in a system. all digital inputs have electrostatic discharge protection. the hs-1840rh/883s has been specifically designed to meet exposure to radiation environments. it is available in a 28 pin ceramic sidebraze dual-in-line package and 28 pin ceramic flatpack. it is guaranteed operational from -55 o c to +125 o c. ( ) september 1997 hs-1840rh/883s rad-hard 16 channel cmos analog multiplexer with high-z analog input protection file number 3022.1 n o t r e c o m m e n d e d f o r n e w d e s i g n s s e e h s - 1 8 4 0 a r h o r c o n t a c t o u r t e c h n i c a l s u p p o r t c e n t e r a t 1 - 8 8 8 - i n t e r s i l o r w w w . i n t e r s i l . c o m / t s c
2 hs-1840rh/883s functional diagram truth table a3 a2 a1 a0 en ?on? channel xxxxh none lllll 1 lllhl 2 llhll 3 llhhl 4 lhlll 5 lhlhl 6 lhhll 7 lhhhl 8 hllll 9 hllhl 10 hlhll 11 hlhhl 12 hhlll 13 hhlhl 14 hhhl l 15 hhhhl 16 p en in 1 out in 16 digital address decoders address input buffer and level shifter multiplex switches 16 a0 a1 a2 p a3 1
3 specifications hs-1840rh/883s absolute maximum ratings reliability information supply voltage between pins 1 and 27 . . . . . . . . . . . . . . . . . . +40v +vsupply to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20v -vsupply to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20v vref to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20v analog input overvoltage: +vs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+25v (power on/off) -vs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25v (power on) digital input overvoltage: +ven, +va . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vref +4v -ven, -va . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd -4v storage temperature range . . . . . . . . . . . . . . . . . -65 o c to +150 o c junction temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c lead temperature (soldering 10s). . . . . . . . . . . . . . . . . . . . . .+275 o thermal resistance . . . . . . . . . . . . . . . . . . ja jc sidebraze package . . . . . . . . . . . . . . . . . 83.1 o c/w 19.1 o c/w flatpack package . . . . . . . . . . . . . . . . . . 49.1 o c/w 16.5 o c/w total power dissipation*: sidebraze dip package . . . . . . . . . . . . . . . . . . . . . . . . . 1600mw ceramic flatpack package . . . . . . . . . . . . . . . . . . . . . . . 1400mw esd classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 * for dip derate 20.4mw/ o c above t a = +95 o c for flatpack derate 18.5mw/ o c above t a = +95 o c caution: stresses above those listed in ?absolute maximum ratings ? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditi ons above those indicated in the operational sections of this specification is not i mplied. operating conditions operating supply voltage ( vsupply) . . . . . . . . . . . . . . . . . . . 15v operating temperature range. . . . . . . . . . . . . . . . -55 o c to +125 o c vref (pin 13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v logic low level (val) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.8v logic high level (vah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.0v table 1. dc electrical performance characteristics device guaranteed and 100% tested. unless otherwise specified: v- = -15v, v+ = +15v, vref = +5v, vah = +4.0v, val = 0.8v parameter symbol conditions group a subgroups temperature limits units min max analog signal range vs 7, 8a, 8b -55 o c, +25 o c, +125 o c -5 +15 v input leakage current, address, or enable pins iah ial measure inputs sequentially ground all unused pins val = 0.8v, vah = 4.0v 1, 2, 3 -55 o c, +25 o c, +125 o c -1000 1000 na leakage current into the source terminal of an ?off? switch +is(off) vs = +10v, all unused inputs and output = -10v, ven = 4v 1+25 o c -10 10 na 2, 3 +125 o c,-55 o c -100 100 na -is(off) vs = -10v, all unused inputs, output = +10v, ven = 4v 1 +25 o c -10 10 na 2, 3 +125 o c, -55 o c -100 100 na leakage current into the source terminal of an ?off? switch with power ?off? +is(off) power off v+, v-, vref, a0, a1, a2, a3,a4, en = gnd, unused inputs tied to gnd, vs = +25v 1+25 o c -50 50 na 2, 3 +125 o c, -55 o c -100 100 na leakage current into the source terminal of an ?off? switch with overvoltage applied +is(off) overvoltage vs = +25v, vd = 0v, ven = 4v all unused inputs tied to gnd 1, 2, 3 -55 o c, +25 o c, +125 o c -1000 1000 na -is(off) overvoltage vs = -25v, vd = 0v, ven = 4v all unused inputs tied to gnd 1, 2, 3 -55 o c, +25 o c, +125 o c -1000 1000 na leakage current into the drain terminal of an ?off? switch +id(off) vd = +10v, ven = 4v all unused inputs = -10v 1+25 o c -10 10 na 2, 3 +125 o c, -55 o c -100 100 na -id(off) vd = -10v, ven = 4v all unused inputs = +10v 1+25 o c -10 10 na 2, 3 +125 o c, -55 o c -100 100 na leakage current into the drain terminal of an ?off? switch with overvoltage applied +id(off) overvoltage vs = +25v, measure vd, ven = 4v, all unused inputs to gnd 1, 2, 3 -55 o c, +25 o c, +125 o c -1000 1000 na -id(off) overvoltage vs = -25v, measure vd, all unused inputs to gnd 1, 2, 3 -55 o c, +25 o c, +125 o c -1000 1000 na
4 specifications hs-1840rh/883s leakage current from an ?on? driver into the switch (drain & source) +id(on) vs = +10v, vd = +10v, ven = 0.8v all unused inputs = -10v 1+25 o c -10 10 na 2, 3 +125 o c, -55 o c -100 100 na -id(on) vs = -10v, vd = -10v, ven = 0.8v, all unused inputs = +10v 1+25 o c -10 10 na 2, 3 +125 o c, -55 o c -100 100 na switch on resistance +15v r(on) vs = +15v, id = -1ma, ven = 0.8v 1, 2, 3 -55 o c, +25 o c, +125 o c 50 1000 ? -5v r(on) vs = -5v, id = +1ma, ven = 0.8v 1, 2, 3 -55 o c, +25 o c, +125 o c 50 4000 ? +5v r(on) vs = +5v, id = -1ma, ven = 0.8v 1, 2, 3 -55 o c, +25 o c, +125 o c 50 2500 ? positive supply current i(+) ven = 0.8v 1, 2, 3 -55 o c, +25 o c, +125 o c -0.5ma negative supply current i(-) ven = 0.8v 1, 2, 3 -55 o c, +25 o c, +125 o c -0.5 - ma positive standby supply current +isby ven = 4.0v 1, 2, 3 -55 o c, +25 o c, +125 o c -0.5ma negative standby supply current -isby ven = 4.0v 1, 2, 3 -55 o c, +25 o c, +125 o c -0.5 - ma table 2. ac electrical performance characteristics device guaranteed and 100% tested. unless otherwise specified: v- = -15v, v+ = +15v, vref = +5v, vah = +4.0v, val = 0.8v parameter symbol conditions group a subgroups temperature limits units min max break-before-make time delay td rl = 1000 ? , cl = 50pf 9 +25 o c25-ns 10, 11 +125 o c, -55 o c5 - ns propagation delay times: address inputs to i/o channels ton(a), toff(a) rl = 10k ? ,cl = 50pf 9 +25 o c - 600 ns 10, 11 +125 o c, -55 o c - 1000 ns enable to i/o ton(en), toff(en) rl = 1000 ? , cl = 50pf 9 +25 o c - 600 ns 10, 11 +125 o c, -55 o c - 1000 ns table 3. electrical performance characteristics device characterized at: v- = -15v, v+ = +15v, vref = +5 v, vah = +4.0v, val = 0.8v, unless otherwise specified parameter symbol conditions note temperature limits units min max capacitance address input ca +vs = -vs = 0v, f = 1mhz 1 +25 o c-7pf capacitance channel input cs(off) +vs = -vs = 0v, f = 1mhz 1 +25 o c-5pf capacitance channel output cd(off) toff(en) +vs = -vs = 0v, f = 1mhz 1 +25 o c - 50 pf off isolation viso ven = 4.0v, f = 200khz, cl = 7pf, rl = 1k ? , vs = 3.0vrms 1+25 o c45-db note: 1. the parameters listed in table 3 are controlled via design or process parameter s and not directly tested. these paramete rs are characterized upon initial design and a fter major process and/or design changes. table 1. dc electrical performance characteristics (continued) device guaranteed and 100% tested. unless otherwise specified: v- = -15v, v+ = +15v, vref = +5v, vah = +4.0v, val = 0.8v parameter symbol conditions group a subgroups temperature limits units min max
5 specifications hs-1840rh/883s table 4. post 200k rad(si) electrical characteristics tested, per mil-std-883. unless otherwise specified: v- = -15v, v+ = +15v, vref = +5v, vah = +4.5v, val = 0.5v parameter symbol conditions group a subgroups temperature limits units min max input leakage current, address, or enable pins iah ial measure inputs sequentially, ground all unused pins 1+25 o c -1000 1000 na leakage current into the source terminal of an ?off? switch +is(off) vs = +10v, all unused inputs & output = -10v, ven = 4.5v 1+25 o c -100 100 na -is(off) vs = -10v, all unused inputs & output = +10v, ven = 4.5v 1+25 o c -100 100 na leakage current into the source terminal of an ?off? switch with power ?off? +is(off) power off v+, v-, vref, a0, a1, a2, a3, a4, en = gnd, unused inputs tied to gnd, vs = +25v 1+25 o c -100 100 na leakage current into the source terminal of an ?off? switch with overvoltage applied +is(off) overvoltage vs = +25v, vd=0v, ven=4.5v all unused inputs tied to gnd 1+25 o c -1500 1500 na -is(off) overvoltage vs = -25v, vd=0v, ven=4.5v all unused inputs tied to gnd 1+25 o c -1500 1500 na leakage current into the drain terminal of an ?off? switch +id(off) vd = +10v, ven = 4.5v all unused inputs = -10v 1+25 o c -100 100 na -id(off) vd = -10v, ven = 4.5v all unused inputs = +10v 1+25 o c -100 100 na leakage current into the drain terminal of an ?off? switch with overvoltage applied +id(off) overvoltage vs = +25v, measure vd, ven = 4.5v all unused inputs to gnd 1+25 o c -1000 1000 na -id(off) overvoltage vs = -25v, measure vd, ven = 4.5v all unused inputs to gnd 1+25 o c -1000 1000 na leakage current from an ?on? driver into the switch (drain & source) +id(on) vs = +10v, vd = +10v, ven = 0.5v all unused inputs = -10v 1+25 o c -100 100 na -id(on) vs = -10v, vd = -10v, ven = 0.5v all unused inputs = +10v 1+25 o c -100 100 na switch on resistance +15v r(on) vs = +15v, id = -1ma, ven = 0.5v 1 +25 o c 50 1000 ? -5v r(on) vs = -5v, id = +1ma, ven = 0.5v 1 +25 o c 50 4000 ? +5v r(on) vs = +5v, id = -1ma, ven = 0.5v 1 +25 o c 50 2500 ? positive supply current i(+) ven = 0.5v 1 +25 o c-0.50ma negative supply current i(-) ven = 0.5v 1 +25 o c -0.50 - ma positive standby supply current +i(sby) ven = 4.5v 1 +25 o c-0.50ma negative standby supply current -i(sby) ven = 4.5v 1 +25 o c -0.50 - ma make-before-break time delay td rl = 1000 ? , cl = 50pf 9 +25 o c5-ns propagation delay times: adress inputs to i/o channels ton (a) toff (a) rl = 10k ? , cl = 50pf 9 +25 o c - 3000 ns enable to i/o ton (en) toff (en) rl = 1000 ? , cl = 50pf 9 +25 o c - 3000 ns
6 specifications hs-1840rh/883s table 5. dc post burn-in delta electrical characteristics guaranteed, per mil-std-883, method 1019. unless otherwise specified: v- = -15v, v+ = +15v, vref = +5v, vah = +4.0v, val = 0.8v parameter symbol conditions group a subgroups temperature limits units min max input leakage current, address, or enable pins iah ial measure inputs sequentially, ground all unused pins 1+25 o c -100 100 na leakage current into the source terminal of an ?off? switch +is(off) vs = +10v, all unused inputs & output = -10v, ven = 4.0v 1+25 o c -20 20 na -is(off) vs = -10v, all unused inputs & output = +10v, ven = 4.0v 1+25 o c -20 20 na leakage current into the drain terminal of an ?off? switch +id(off) vd = +10v, ven = 4.0v all unused inputs = -10v 1+25 o c -20 20 na -id(off) vd = -10v, ven = 4.0v all unused inputs = +10v 1+25 o c -20 20 na leakage current from an ?on? driver into the switch (drain & source) + id(on) vs = +10v, vd = +10v, ven = 0.8v all unused inputs = -10v 1+25 o c -20 20 na -id(on) vs = -10v, vd = -10v, ven = 0.8v all unused inputs = +10v 1+25 o c -20 20 na switch on resistance +15v r(on) vs = +15v, id = -1ma, ven = 0.8v 1+25 o c -150 150 ? -5v r(on) vs = -5v, id = +1ma, ven = 0.8v 1+25 o c -250 250 ? positive supply current i(+) ven = 0.8v 1 +25 o c -50 50 a negative supply current i(-) ven = 0.8v 1 +25 o c -50 50 a positive standby supply current +isby ven = 4.0v 1 +25 o c -50 50 a negative standby supply current -isby ven = 4.0v 1 +25 o c -50 50 a table 6. applicable subgroups conformance groups method q subgroups initial test 100%/5004 1 interim test 100%/5004 1 pda 100%/5004 1 final test 100%/5004 1, 2, 3, 7, 8a, 8b, 9, 10, 11 group a samples/5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11 group b b5 samples/5005 1, 2, 3 others samples/5005 1, 7 group d samples/5005 1, 7 group e, subgroup 2 samples/5005 1, 7
7 hs-1840rh/883s performance characteristi cs and test circuits access time vs. logic level (high) break-before-make delay (topen) enable delay (ton(en), toff(en)) 0.8v 50% 50% ta 4.0v va vout 0v en 0.8v 50 ? 15v, 0v in 1 10k 50pf in 16 in 2 - gnd va a3 a0 vout in 15 a2 a1 0v, 15v 0.8v 50% 50% 4.0v topen vout va en 0.8v 50 ? out +5v in 1 1k 50pf in 16 in 2 - gnd va a3 a0 vout in 15 a2 a1 0.8v output 90% 10% ton(en) toff(en) 4.0v va vout en 50 ? +10v in 1 1k 50pf in 2 - va a3 a0 vout in 16 a2 a1
8 hs-1840rh/883s burn-in/life test circuits dynamic burn-in and life test circuit notes: vs+ = +15.5v 0.5v, vs- = -15.5v 0.5v r = 1k ? 5% c1 = c2 = 0.01 f 10%, 1 each per socket, minimum d1 = d2 = 1n4002, 1 each per board, minimum input signals: square wave, 50% duty cycle, 0v to 15v peak 10% f1 = 100khz; f2 = f1/2; f3 = f1/4; f4 = f1/8; f5 = f1/16 notes: 1. the above test circuits ar e utilized for all package types 2. the dynamic test circuit is utilized for all life testing static burn-in test circuit notes: r = 1k ? 5%, 1 / 4 w c1 = c2 = 0.01 f minimum, 1 each per socket, minimum vs+ = 15.5v 0.5v, vs- = -15.5v 0.5v, vr = 15.5 0.5v irradiation circuit 28 pin dip note: all irradiation testing is performed in the 28 pin dip package r r gnd +vs r 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 f4 f3 f1 f5 f2 -vs 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 r r r gnd vr +vs r -vs 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1k ? +15v +1v +5v nc nc -15v
9 hs-1840rh/883s schematic diagrams address input buffer and level shifter address decoder mul tiplex switch n n n v- n p v+ n p n p p p level shifter add in. 200 ? v d1 d2 r1 n n n n p ppp r5 r6 r7 r8 r2 r3 r4 overvoltage protection level shifted address to decode p level shifted address to decode v ref ref +v enable ppp p p n a0 or a 0 a1 or a 1 a2 or a 2 v- to switch n n n n a3 or a 3 out in v- v+ p nn p p s d from decode
10 hs-1840rh/883s intersil - space level product flow sem - traceable to diffusion method 2018 wafer lot acceptance method 5007 internal visual inspection (note 1) gamma radiation assurance tests method 1019 100% nondestructive bond pull method 2023 customer pre-cap visual inspection (notes 1, 2) temperature cycling method 1010 condition c constant acceleration method 2001 y1 30kg particle impact noise detection method 2020, condition a 20g marking and serialization x-ray inspection method 2012 initial electrical tests (t0) static burn-in 72 hour, +125 o c method 1015 condition a room temperature electrical tests (t1) burn-in delta calculation (t0-t1) pda calculation 3% functional 5% subgroups 1, 7, ? dynamic burn-in 240 hours, +125 o c method 1015 condition d electrical tests subgroups 1, 7, 9 (t2) burn-in delta calculation (t0 - t2) pda calculation 3% functional 5% subgroups 1, 7, ? electrical test +125 o c, -55 o c alternate group a inspection method 5005 fine and gross leak tests method 1014 customer source inspection (note 2) group b inspection (notes 2, 4) method 5005 group d inspection (notes 2, 4) method 5005 external visual inspection method 2009 data package generation (note 3) notes: 1. visual inspection is performed to mil-std-883 method 2010, condition a. 2. these steps are optional, and should be li sted on the purchase order if required. 3. data package contains: assem bly attributes (post seal) test attributes (includes group a) -55 o c, +25 o c, +125 o c shippable serial number list radiation testing certificate of conformance wafer lot acceptance report (includes sem report) x-ray report and film test variables data, dc test and telqv +25 o c initial test +25 o c interim test 1 +25 o c interim test 2 +25 o c delta over burn-in 4. group b data package contains attributes data pulse variables data, dc test and te 2hqv. group d data package contains attribu tes only.
11 hs-1840rh/883s metallization topology die dimensions: 110 x 159 x 11mils metallization: type: al thickness: 12.5k ? 2k ? glassivation: type: sio 2 thickness: 8k ? 1k ? die attach: material: gold eutectic temperature: sidebrazed ceramic dip - 460 o c (max) flatpack - 460 o c (max) worst case current density: 1.90e04a/cm 2 lead temperature (10 seconds soldering): <275 o c process: cmos-di metallization mask layout hs-1840rh/883s in7 in6 in5 in4 in3 in2 in1 enable a0 a1 a2 a3 vref gnd in8 -v out +v in16 in15 in14 in13 in12 in11 in10 in9

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