a0~a18 /oe /we /cs d0~7 512k x 8 sram 512k x 8 sram decoder a19 /cs /cs 512k x 8 sram /cs 512k x 8 sram /cs a20 address inputs a0 ~ a20 data input/output d0 ~ d7 chip select cs write enable we output enable oe power (+5v) v cc ground gnd package details sys82000fk - 020/025/35 block diagram pin functions pin definition description features issue 1.2 : february 2000 2m x 8 sram module 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 top view a0 a1 a2 a3 a4 cs d0 d1 vcc gnd d2 d3 we a5 a6 a7 a8 a9 a20 a19 a18 a17 a16 oe d7 d6 gnd vcc d5 d4 a15 a14 a13 a12 a11 a10 the sys82000fk is a plastic 16mbit static ram module housed in a jedec standard 36 pin dual in-line package organised as 2mx8. the module utilises 512kx8 sram's housed in soj packages, and uses double sided surface mount techniques, buried decoder and dual board construction to achieve a very high density module, emulating the 16mbit monolithic pinout. access times of 20 to 35 ns are available. the oe pin allows faster access times than address access during a read cycle. ? access times of 20/25/35 ns. ? 36 pin jedec standard dual-in-line package. ? 5 volt supply 10%. ? low power dissipation: average (min cycle) 2.15w (max). standby ( -l version cmos ) 220mw (max). ? completely static operation. ? low voltage v cc data retention. ? equal access and cycle times. ? on-board supply decoupling capacitors. plastic 36 pin 0.6" dual-in-line package.(dip) 11403 west bernado court, suite 100, san diego, ca 92127. tel no: (001) 858 674 2233, fax no: (001) 858 674 2230
sys82000fk - 20/25/35 issue 1.2 february 2000 2 parameter symbol test condition min typ max unit i/p leakage current address,oe,we i li 0v < v in < v cc -20 - 20 a output leakage current i lo cs = v ih, v i/o = gnd to v cc , oe=v ih -20 - 20 a operating supply current i cc1 min. cycle, cs = v il ,v il v cc -0.2v, 0.2 sys82000fk - 20/25/35 issue 1.2 february 2000 3 * input pulse levels: 0v to 3.0v * input rise and fall times: 5ns * input and output timing reference levels: 1.5v * output load: see diagram * v cc =5v10% ac test conditions output load operation truth table 645 100pf i/o pin 1.76v w parameter symbol test condition min typ max unit v cc for data retention v dr cs > v cc -0.2v 2.0 - - v data retention current i ccdr1 2.0 < vcc < 5.5v,cs >vcc-0.2 - - 2.4 ma chip deselect to data retention time t cdr see retention waveform 0 - - ns operation recovery time t r see retention waveform t rc --ms notes (1) figures are measured over the comercial temp range. low v cc data retention characteristics - l version only notes : h = v ih : l =v il : x = v ih or v il cs oe we data pins supply current mode h x x high impedance i sb1 , i sb2 standby l l h data out i cc1 read l x l data in i cc1 write l h h high-impedance i sb1 , i sb2 high-z
sys82000fk - 20/25/35 issue 1.2 february 2000 4 write cycle -20 -25 -35 parameter symbol min max min max min max unit write cycle time t wc 20-25-35-ns chip selection to end of write t cw 15-17-20-ns address valid to end of write t aw 15-17-20-ns address setup time t as 0-0-0-ns write pulse width t wp 15-17-20-ns write recovery time t wr 0-0-3-ns write to output in high z t whz 09010015ns data to write time overlap t dw 10-12-20-ns data hold from write time t dh 0-0-0-ns output active from end of write t ow 3-5-5-ns ac operating conditions read cycle -020 -025 -035 parameter symbol min max min max min max unit read cycle time t rc 20-25-35-ns address access time t aa -20-25-35ns chip select access time t acs -20-25-35ns output enable to output valid t oe -10-12-14ns output hold from address change t oh 3-3-5-ns chip selection to output in low z t clz 0-0-0-ns output enable to output in low z t olz 0-0-0-ns chip deselection to o/p in high z t chz 09010012ns output disable to output in high z t ohz 09010012ns
sys82000fk - 20/25/35 issue 1.2 february 2000 5 read cycle timing waveform (1,2) write cycle no.1 timing waveform (1,4) t wr(7) as(6) t cw t wp(2) t dw dh aw don't care t t t t t wc ohz(3,9) address oe cs we dout din high-z high-z ow t (8) data valid oe t acs t clz (4,5) t ohz (3) t t olz aa oh chz (3,4,5) data valid t t t t rc address cs dout oe don't care. ac read characteristics notes (1) we is high for read cycle. (2) all read cycle timing is referenced from the last valid address to the first transition address. (3) t chz and t ohz are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. (4) at any given temperature and voltage condition, t chz (max) is less than t clz (min) both for a given module and from module to module. (5) these parameters are sampled and not 100% tested.
sys82000fk - 20/25/35 issue 1.2 february 2000 6 write cycle no.2 timing waveform (1,5) t r t cdr 4.5v 2.2v 4.5v 2.2v 0v data retention mode vcc cs v dr cs > vcc -0.2v data retention waveform ac write characteristics notes (1) all write cycle timing is referenced from the last valid address to the first transition address. (2) all writes occur during the overlap of cs and we low. (3) if oe, cs, and we are in the read mode during this period, the i/o pins are low impedance state. inputs of opposite phase to the output must not be applied because bus contention can occur. (4) dout is the read data of the new address. (5) oe is continuously low. (6) address is valid prior to or coincident with cs and we low, too avoid inadvertant writes. (7) cs or we must be high during address transitions. (8) when cs is low : i/o pins are in the output state. input signals of opposite phase leading to the output should not be applied. (9) defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. these parameters are sampled and not 100% tested. t aw t cw wr(7) wc as(6) dw dh oh ow whz(3,9) wp(2) don't t t t t t address cs we dout din t t t t care high-z high-z (4) (8) data valid
sys82000fk - 20/25/35 issue 1.2 february 2000 7 49.53 typ. 15.24 typ. 15.92 typ. 2.54 typ. 10.20 max 3.50+/-0.50 package information dimensions in mm ordering information sys82000fkli - 35 speed 020 = 20 ns 025 = 25 ns 35 = 35 ns temperature range blank = commercial temperature i = industrial temperature power consumption blank = standard part l = low power part package fk = plastic 36 pin 0.6" dip organization 82000 = 2m x 8 memory type sys = static ram plastic 36 pin 0.6" dual-in-line (dip) note : although this data is believed to be accurate, the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. our products are subject to a constant process of development. data may be changed at any time without notice. products are not authorised for use as critical components in life support devices without the express written approval of a company director
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