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1 a, low dropout, cmos linear regulator adp1706/adp1707/adp1708 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features maximum output current: 1 a input voltage range: 2.5 v to 5.5 v low shutdown current: <1 a low dropout voltage: 345 mv @ 1 a load initial accuracy: 1% accuracy over line, load, and temperature: 2.5% 16 fixed output voltage options with soft start: 0.75 v to 3.3 v (adp1706) 16 fixed output voltage options with tracking 0.75 v to 3.3 v (adp1707) adjustable output voltage option: 0.8 v to 5.0 v (adp1708) stable with small 4.7 f ceramic output capacitor excellent load/line transient response current limit and thermal overload protection logic-controlled enable available in an 8-lead, exposed paddle soic and 3 mm 3 mm, 8-lead exposed paddle lfcsp applications notebook computers memory components telecommunications equipment network equipment dsp/fpga/microprocessor supplies instrumentation equipment/data acquisition systems typical application circuits ss 1 sense 2 out 3 out 4 en 8 gnd 7 in 6 in 5 adp1706 10nf v out = 3.3v v in = 5v 4.7f 4.7f 06640-001 figure 1. adp1706 with fixed output voltage, 3.3 v adp1707 trk 1 sense 2 out 3 out 4 en 8 gnd 7 in 6 in 5 v out v trk v in = 5v 4.7f 4.7f 3 2 1 0 12345 v out (v) v trk (v) 06640-003 figure 2. adp1707 with output voltage tracking a dp1708 adj 1 sense 2 out 3 out 4 en 8 gnd 7 in 6 in 5 v out = 0.8v(1 + r1/r2) v in = 5v 4.7f 4.7f r1 r2 06640-002 figure 3. adp1708 with adjustable output voltage, 0.8 v to 5.0 v general description the adp1706/adp1707/adp1708 are cmos, low dropout linear regulators that operate from 2.5 v to 5.5 v and provide up to 1 a of output current. using an advanced proprietary architecture, they provide high power supply rejection and achieve excellent line and load transient response with a small 4.7 f ceramic output capacitor. the adp1706/adp1707 are available in 16 fixed output volt- age options. the adp1708 is available in an adjustable version, which allows output voltages that range from 0.8 v to 5.0 v via an external divider. the adp1706 allows an external soft start capacitor to be connected to program the start-up time; the adp1707 and adp1708 contain internal soft start capacitors that give a typical start-up time of 100 s. the adp1707 includes a tracking feature that allows the output to follow an external voltage rail or reference. the adp1706/adp1707/adp1708 are available in an 8-lead, exposed paddle soic package and an 8-lead, 3 mm 3 mm exposed paddle lfcsp, making them not only very compact solutions but also providing excellent thermal performance for applications requiring up to 1 a of output current in a small, low profile footprint.
adp1706/adp1707/adp1708 rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 applications....................................................................................... 1 typical application circuits............................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 absolute maximum ratings............................................................ 5 thermal resistance ...................................................................... 5 esd caution.................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 10 soft start function (adp1706) ................................................ 10 adjustable output voltage (adp1708)................................... 11 track mode (adp1707) ............................................................ 11 enable feature ............................................................................ 11 application information................................................................ 12 capacitor selection .................................................................... 12 voltage tracking applications.................................................. 12 current limit and thermal overload protection ................. 12 thermal considerations............................................................ 13 pcb layout considerations...................................................... 15 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 17 revision history 6/07revision 0: initial version
adp1706/adp1707/adp1708 rev. 0 | page 3 of 20 specifications v in = (v out + 0.6 v) or 2.5 v (whichever is greater), i out = 10 ma, c in = c out = 4.7 f, t a = 25c, unless otherwise noted. table 1. parameter symbol test conditions min typ max unit input voltage range v in t j = C40c to +125c 2.5 5.5 v operating supply current i gnd i out = 0 ma 50 a i out = 100 ma 310 a i out = 100 ma, t j = ?40c to +125c 390 a i out = 1 a 1.2 ma i out = 1 a, t j = ?40c to +125c 1.55 ma shutdown current i gnd-sd en = gnd 0.1 a en = gnd, t j = ?40c to +125c 1.0 a output voltage accuracy v out i out = 10 ma ?1 +1 % i out = 100 a to 1 a ?1.5 +1.5 % fixed output voltage accuracy (adp1706 and adp1707) 100 a < i out < 1 a, t j = ?40c to +125c ?2.5 +2.5 % v out i out = 10 ma 0.792 0.8 0.808 v i out = 100 a to 1 a 0.788 0.812 v adjustable output voltage accuracy (adp1708) 1 100 a < i out < 1 a, t j = ?40c to +125c 0.780 0.820 v line regulation ?v out /?v in v in = (v out + 0.6 v) to 5.5 v, t j = ?40c to +125c ?0.1 +0.1 %/ v load regulation 2 ?v out /?i out i out = 10 ma to 1 a, t j = ?40c to +125c 0.001 %/ma dropout voltage 3 v dropout i out = 100 ma, v out 3.3 v 33 mv i out = 100 ma, v out 3.3 v, t j = ?40c to +125c 55 mv i out = 1 a, v out 3.3 v 345 mv i out = 1 a, v out 3.3 v, t j = ?40c to +125c 600 mv i out = 100 ma, 2.5 v v out < 3.3 v 35 mv i out = 100 ma, 2.5 v v out < 3.3 v, t j = ?40c to +125c 60 mv i out = 1 a, 2.5 v v out < 3.3 v 365 mv i out = 1 a, 2.5 v v out < 3.3 v, t j = ?40c to +125c 630 mv start-up time 4 t start-up adp1707 and adp1708 100 s adp1706 c ss = 10 nf 7.3 ms current limit threshold 5 i limit 1.1 1.5 1.8 a thermal shutdown thermal shutdown threshold ts sd t j rising 150 c thermal shutdown hysteresis ts sd-hys 15 c soft start source current (adp1706) ss i-source ss = gnd 0.6 1.1 1.6 a v out to v trk accuracy (adp1707) v trk-error 0 v v trk (0.5 v out (nom) ), v out (nom) 1.8 v, t j = ?40c to +125c ?40 +40 mv 0 v v trk (0.5 v out (nom) ), v out (nom) > 1.8 v, t j = ?40c to +125c ?60 +60 mv en input en input logic high v ih 2.5 v v in 5.5 v 1.8 v en input logic low v il 2.5 v v in 5.5 v 0.4 v en input leakage current v i-leakage en = in or gnd 0.1 1 a adj input bias current (adp1708) adj i-bias 30 100 na sense input bias current sns i-bias 4 a
adp1706/adp1707/adp1708 rev. 0 | page 4 of 20 parameter symbol test conditions min typ max unit output noise out noise 10 hz to 100 khz, v out = 0.75 v 125 v rms 10 hz to 100 khz, v out = 3.3 v 450 v rms power supply rejection ratio psrr 1 khz, v out = 0.75 v 70 db 1 khz, v out = 3.3 v 56 db 1 accuracy when out is connected directly to adj. when out voltage is set by external feedback resistors, absolute accuracy in a djust mode depends on the tolerances of resistors used. 2 based on an end-point ca lculation using 10 ma and 1 a loads. see figure 11 for typical load regulation performance for loads l ess than 10 ma. 3 dropout voltage is defined as the input-to-output voltage differe ntial when the input voltage is set to the nominal output vol tage. this applies only for output voltages above 2.5 v. 4 start-up time is defined as the time between the rising edge of en to out being at 95% of its nominal value. 5 current limit threshold is defi ned as the current at which the output voltage dr ops to 90% of the specif ied typical value. for example, the current limit for a 1.0 v output voltage is defined as the curre nt that causes the output voltage to drop to 90% of 1.0 v, or 0.9 v.
adp1706/adp1707/adp1708 rev. 0 | page 5 of 20 absolute maximum ratings table 2. parameter rating in to gnd ?0.3 v to +6 v out to gnd C0.3 v to in en to gnd C0.3 v to +6 v ss/adj/trk to gnd C0.3 v to +6 v sense to gnd C0.3 v to +6 v storage temperature range C65c to +150c operating junction temperature range C40c to +125c soldering conditions jedec j-std-020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja unit 8-lead soic (exposed paddle) 58 c/w 8-lead 3 mm 3 mm lfcsp (exposed paddle) 66 c/w esd caution
adp1706/adp1707/adp1708 rev. 0 | page 6 of 20 pin configurations and function descriptions en 1 gnd 2 in 3 in 4 ss 8 sense 7 out 6 out 5 adp1706 top view (not to scale) 06640-004 adp1706 top view (not to scale) pin 1 indicator 1 en 2 g nd 3 in 4 in 7 sense 8ss 6out 5out 06640-007 figure 4. 8-lead soic, adp1706 figure 5. 8-lead lfcsp, adp1706 en 1 gnd 2 in 3 in 4 trk 8 sense 7 out 6 out 5 adp1707 top view (not to scale) 06640-006 pin 1 indicator 1 en 2 g nd 3 in 4 in 7sense 8trk 6out 5out top view (not to scale) adp1707 06640-009 figure 6. 8-lead soic, adp1707 figure 7. 8-lead lfcsp, adp1707 en 1 gnd 2 in 3 in 4 adj 8 sense 7 out 6 out 5 adp1708 top view (not to scale) 06640-005 pin 1 indicator 1 en 2 gnd 3 in 4 in 7 sense 8 adj 6out 5out adp1708 top view (not to scale) 06640-008 figure 8. 8-lead soic, adp1708 figure 9. 8-lead lfcsp, adp1708 table 4. pin function descriptions adp1706 pin o. adp1707 pin o. adp170 pin o. nemonic description 1 1 1 en enable input. drive en high to turn on th e regulator; drive it low to turn off the regulator. for automatic startup, connect en to in. 2 2 2 gnd ground. 3, 4 3, 4 3, 4 in regulator input supply. bypass in to gnd with a 4.7 f or greater capacitor. 5, 6 5, 6 5, 6 out regulated output voltage. bypass out to gnd with a 4.7 f or greater capacitor. 7 7 7 sense sense. measures the actual output voltage at the load and feeds it to the error amplifier. connect sense as close as possible to the load to minimize the effect of ir drop between the regulator output and the load. 8 n/a n/a ss soft start. a capacitor connected to this pin determines the soft start time. n/a 8 n/a trk track. the output follows the voltage applied at the trk pin. see the theory of operation section for a more detailed description. n/a n/a 8 adj adjust. a resistor divider from out to adj sets the output voltage. ep ep ep ep the exposed pad on the bottom of the soic package and the lfcsp package. ep enhances thermal performance and is elec trically connected to gnd inside the package. user is recommended to connect ep to the ground plane on the board.
adp1706/adp1707/adp1708 rev. 0 | page 7 of 20 typical performance characteristics v in = 3.8 v, i out = 100 ma, c in = 4.7 f, c out = 4.7 f, t a = 25c, unless otherwise noted. ?40 10 60 110 t j (c) v out (v) 3.24 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 i load = 100a i load = 10ma i load = 100ma i load = 500ma i load = 1a 06640-010 i load = 300ma figure 10. output voltage vs. junction temperature 0.1 1000 i load (ma) v out (v) 1 10 100 3.270 3.275 3.280 3.285 3.290 3.295 3.300 3.305 3.310 3.315 06640-011 figure 11. output voltage vs. load current 3.8 4.2 4.6 5.0 5.4 v in (v) v out (v) 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 i load = 300ma i load = 100ma i load = 10ma i load = 100a i load = 1a i load = 500ma 06640-012 figure 12. output voltage vs. input voltage ?40 10 60 110 t j (c) i gnd (a) 0 1400 1200 1000 800 600 400 200 i load = 10ma i load = 100a i load = 100ma i load = 300ma i load = 500ma i load = 1a 06640-013 figure 13. ground current vs. junction temperature 0.1 1000 i load (ma) 11 01 0 0 i gnd (a) 0 1400 1200 1000 800 600 400 200 06640-014 figure 14. ground current vs. load current 2100 0 3.6 4.0 4.4 4.8 5.2 v in (v) i gnd (a) 1800 1500 1200 900 600 300 i load = 100a i load = 10ma i load = 100ma i load = 300ma i load = 500ma i load = 1a 06640-015 figure 15. ground current vs. input voltage
adp1706/adp1707/adp1708 rev. 0 | page 8 of 20 400 0 10 1000 i load (ma) v dropout (mv) 100 350 300 250 200 150 100 50 06640-017 figure 16. dropout voltage vs. load current 3.4 2.5 3.0 4.0 v in (v) v out (v) 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 3.2 3.4 3.6 3.8 i load = 10ma i load = 100ma i load = 300ma i load = 500ma i load = 750ma i load = 1a 06640-018 figure 17. output voltage vs. input voltage (in dropout) 2500 0 3.0 4.0 v in (v) i gnd (a) 3.2 3.4 3.6 3.8 2000 1500 1000 500 i load = 1a i load = 750ma i load = 500ma i load = 300ma i load = 100ma i load = 10ma 06640-019 figure 18. ground current vs. input voltage (in dropout) v out 50mv/di v time (20s/div) v in = 3.8v v out = 1.6v c in = 4.7f c out = 4.7f 06640-020 load switched from 50ma to 950ma and back to 50ma figure 19. load transient response, c in = 4.7 f, c out = 4.7 f v out 50mv/di v time (20 s/div) v in = 3.8v v out = 1.6v c in = 22 f c out = 22 f 06640-021 load switched from 50ma to 950ma and back to 50ma figure 20. load transient response, c in = 22 f, c out = 22 f 20mv/di v 2v/di v time (100 s/div) v out = 3.3v c in = 4.7 f c out = 4.7 f i load = 1a v in step from 4v to 5v v out 06640-022 figure 21. line transient response
adp1706/adp1707/adp1708 rev. 0 | page 9 of 20 c ss (nf) ramp-up time (ms) 18 0 02 ? 5 40 ?55 2.7 3.2 3.7 4.2 4.7 v in (v) psrr (db) 16 14 12 10 8 6 4 2 51 01 52 0 06640-023 figure 22. output voltage ramp-up ti me vs. soft start capacitor value 0 ?90 10 10m frequency (hz) psrr (db) 100 1k 10k 100k 1m ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 v ripple = 50mv v in = 5v v out = 3.3v c out = 4.7 f i load = 300ma i load = 200ma i load = 100ma i load = 10ma i load = 1ma i load = 100a 06640-024 figure 23. adp1706 power supply rejection ratio vs. frequency 0 ?90 10 10m frequency (hz) psrr (db) 100 1k 10k 100k 1m ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 v ripple = 50mv v in = 5v v out = 0.8v c out = 4.7 f i load = 300ma i load = 200ma i load = 100ma i load = 10ma i load = 1ma i load = 100a 06640-025 figure 24. adp1708 power supply rejection ratio vs. frequency ?45 ?50 v out = 2.4v v out = 1.6v v out = 0.8v v ripple = 50mv i load = 10ma c out = 4.7 f frequency = 10khz 06640-026 figure 25. adp1708 power supply rejection ratio vs. input voltage ? 35 ?55 0.8 4.3 v out (v) psrr (db) ?40 ?45 ?50 1.3 1.8 2.3 2.8 3.3 3.8 v ripple = 50mv v in = 5v i load = 10ma c out = 4.7 f frequency = 10khz 06640-027 figure 26. adp1708 power supply rejection ratio vs. output voltage
adp1706/adp1707/adp1708 rev. 0 | page 10 of 20 theory of operation the adp1706/adp1707/adp1708 are low dropout linear regulators that use an advanced, proprietary architecture to provide high power supply rejection ratio (psrr) and excellent line and load transient response with a small 4.7 f ceramic output capacitor. all devices operate from a 2.5 v to 5.5 v input rail and provide up to 1 a of output current. supply current in shutdown mode is typically 100 na. soft start reference current limit thermal protect shutdown gnd out sense adj/ trk/ ss in en 06640-016 figure 27. internal block diagram internally, the adp1706/adp1707/adp1708 consist of a reference, an error amplifier, a feedback voltage divider, and a pmos pass transistor. output current is delivered via the pmos pass device, which is controlled by the error amplifier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. if the feedback voltage is lower than the reference voltage, the gate of the pmos device is pulled lower, allowing more current to pass and increasing the output voltage. if the feedback voltage is higher than the reference voltage, the gate of the pmos device is pulled higher, allowing less current to pass and decreasing the output voltage. the adp1706/adp1707 are available in 16 fixed output voltage options between 0.75 v and 3.3 v. the adp1706 allows for connection of an external soft start capacitor, which controls the output voltage ramp during startup. the adp1707 features a trk pin that allows the output voltage to follow the voltage at this pin. the adp1708 is available in an adjustable version with an output voltage that can be set to between 0.8 v and 5.0 v by an external voltage divider. all devices are controlled by an enable pin (en). soft start function (adp1706) for applications that require a controlled startup, the adp1706 provides a programmable soft start function. the programma- ble soft start is useful for reducing inrush current upon startup and for providing voltage sequencing. to implement a soft start, connect a small ceramic capacitor from ss to gnd. upon startup, a 1.2 a current source charges this capacitor. the adp1706 start-up output voltage is limited by the voltage at ss, providing a smooth ramp-up to the nominal output voltage. the soft start time is calculated by t ss = v ref ( c ss / i ss ) (1) where: t ss is the soft start period. v ref is the 0.8 v reference voltage. c ss is the soft start capacitance from ss to gnd. i ss is the current sourced from ss (1.2 a). when the adp1706 is disabled (using en), the soft start capacitor is discharged to gnd through an internal 100 resistor. time (2ms/div) v in = 5v v out = 3.3v c out = 4.7 f c ss = 10nf i load = 1a 1v/di v 1 2v/di v 2 en out 06640-028 figure 28. out ramp-up with ex ternal soft start capacitor the adp1707 and adp1708 have no pins for soft start; therefore, the function is switched to an internal soft start capacitor, which sets the soft start ramp-up period to approxi- mately 48 s. note that the ramp-up period is the time it takes out to go from 0% to 90% of the nominal value and is different from the start-up time in table 1 , which is the time between the rising edge of en to out being at 90% of the nominal value. for the worst-case output voltage of 5 v, using the suggested 4.7 f output capacitor, the resulting input inrush current is approximately 490 ma, which is less than the maximum 1 a load current. time (20s/div) v in = 5v v out = 1.6v c out = 4.7 f i load = 10ma 1v/di v 1 2v/di v 2 en out 06640-029 figure 29. out ramp-up wi th internal soft start
adp1706/adp1707/adp1708 rev. 0 | page 11 of 20 v trk (v) v out (v) adjustable output voltage (adp1708) the adp1708 can have its output voltage set over a 0.8 v to 5.0 v range. the output voltage is set by connecting a resistive voltage divider from out to adj. the output voltage is calculated by v out = 0.8 v (1 + r1 / r2 ) (2) where: r1 is the resistor from out to adj. r2 is the resistor from adj to gnd. the maximum bias current into adj is 100 na, so for less than 0.5% error due to the bias current, use values less than 60 k for r2. track mode (adp1707) the adp1707 includes a tracking mode feature. as shown in figure 30 , if the voltage applied at the trk pin is less than the nominal output voltage, out is equal to the voltage at trk. otherwise, out regulates to its nominal output value. 4.0 0 05 . 0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 06640-030 v in = 3.8v v out = 3.3v i load = 10ma figure 30. adp1707 output voltage vs. tracking voltage for example, consider an adp1707 with a nominal output voltage of 3.3 v. if the voltage applied to its trk pin is greater than 3.3 v, out maintains a nominal output voltage of 3.3 v. if the voltage applied to trk is reduced below 3.3 v, out tracks this voltage. out can track the trk pin voltage from the nominal value all the way down to 0 v. a voltage divider is present from trk to the error amplifier input with a divider ratio equal to the divider from out to the error amplifier, which sets the output voltage equal to the tracking voltage. both divider ratios are set by postpackage trim, depending on the desired output voltage. enable feature the adp1706/adp1707/adp1708 use the en pin to enable and disable the out pin under normal operating conditions. as shown in figure 31 , when a rising voltage on en crosses the active threshold, out turns on. when a falling voltage on en crosses the inactive threshold, out turns off. time (10ms/div) v in = 5v v out = 1.6v c out = 4.7 f i load = 10ma 500mv/di v en out 06640-031 figure 31. adp1706 typical en pin operation as shown in figure 31 , the en pin has hysteresis built in. this prevents on/off oscillations that can occur due to noise on the en pin as it passes through the threshold points. the en pin active/inactive thresholds are derived from the in voltage. therefore, these thresholds vary when changing the input voltage. figure 32 shows typical en active/inactive thresholds when the input voltage varies from 2.5 v to 5.5 v. 1.4 0.5 2.50 5.50 v in (v) typical en thresholds (v) 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 en active 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 en inactive hysteresis 06640-032 figure 32. typical en pin thresholds vs. input voltage
adp1706/adp1707/adp1708 rev. 0 | page 12 of 20 application information capacitor selection output capacitor the adp1706/adp1707/adp1708 are designed for operation with small, space-saving ceramic capacitors, but they function with most commonly used capacitors as long as care is taken with the effective series resistance (esr) value. the esr of the output capacitor affects stability of the ldo control loop. a minimum of 4.7 f capacitance with an esr of 500 m or less is recommended to ensure stability of the adp1706/adp1707/adp1708. transient response to changes in load current is also affected by output capacitance. using a larger value of output capacitance improves the transient response of the adp1706/adp1707/adp1708 to large changes in load current. figure 33 and figure 34 show the transient responses for output capacitance values of 4.7 f and 22 f, respectively. time (2 s/div) v in = 3.8v v out = 1.6v c in = 4.7 f c out = 4.7 f 50mv/di v v out response to load step from 50ma to 950ma 06640-033 figure 33. output transient response, c out = 4.7 f time (2 s/div) v in = 3.8v v out = 1.6v c in = 22 f c out = 22 f 50mv/di v v out response to load step from 50ma to 950ma 06640-034 figure 34. output transient response, c out = 22 f input bypass capacitor connecting a 4.7 f capacitor from the in pin to gnd reduces the circuit sensitivity to the printed circuit board (pcb) layout, especially when long input traces, or high source impedance, is encountered. if greater than 4.7 f of output capacitance is required, it is recommended that the input capacitor be increased to match it. input and output capacitor properties any good quality ceramic capacitors can be used with the adp1706/adp1707/adp1708, as long as they meet the minimum capacitance and maximum esr requirements. ceramic capacitors are manufactured with a variety of dielec- trics, each with different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended. y5v and z5u dielectrics are not recommended, due to their poor temperature and dc bias characteristics. voltage tracking applications ss trk in en in en out out ratio voltage trackin g gnd gnd core rail ratio tracking i/o power rail time v out 2.5v 1.2v 1.2v 2.5v 5v r1 r2 adp1706-2.5 adp1707-1.2 06640-042 figure 35. voltage tracking feature using adp1707 figure 35 shows an application where the adp1707 tracking feature is used. an adp1706 powers the i/o of a microproces- sor and an adp1707 powers the core. at startup, the output of the adp1706 ramps to 2.5 v, which is divided down via a voltage divider (r1 and r2) to a lower voltage at the trk pin of the adp1707. the output of the adp1707 thus follows the trk pin and ramps up steadily to 1.2 v. this implementation ensures that the core of the processor powers up after the i/o. current limit and thermal overload protection the adp1706/adp1707/adp1708 are protected against damage due to excessive power dissipation by current and thermal overload protection circuits. the adp1706/adp1707/ adp1708 are designed to reach current limit when the output load reaches 1.5 a (typical). when the output load exceeds 1.5 a, the output voltage is reduced to maintain a constant current limit.
adp1706/adp1707/adp1708 rev. 0 | page 13 of 20 thermal overload protection is included, which limits the junction temperature to a maximum of 150c (typical). under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature starts to rise above 150c, the output is turned off, reducing the output current to zero. when the junction temperature drops below 135c (typical), the output is turned on again and output current is restored to its nominal value. consider the case where a hard short from out to ground occurs. at first, the adp1706/adp1707/adp1708 reach current limit so that only 1.5 a is conducted into the short. if self-heating of the junction becomes great enough to cause its temperature to rise above 150c, thermal shutdown activates, turning off the output and reducing the output current to zero. as the junction temperature cools and drops below 135c, the output turns on and conducts 1.5 a into the short, again causing the junction temperature to rise above 150c. this thermal oscillation between 135c and 150c causes a current oscillation between 1.5 a and 0 a that continues as long as the short remains at the output. current and thermal limit protections are intended to protect the device against accidental overload conditions. for reliable operation, device power dissipation should be externally limited so junction temperatures do not exceed 125c. thermal considerations to guarantee reliable operation, the junction temperature of the adp1706/adp1707/adp1708 must not exceed 125c. to ensure that the junction temperature stays below this maximum value, the user needs to be aware of the parameters that contrib- ute to junction temperature changes. these parameters include ambient temperature, power dissipation in the power device, and thermal resistance between the junction and ambient air ( ja ). the ja value is dependent on the package assembly compounds used and the amount of copper to which the gnd pins of the package are soldered on the pcb. table 5 shows typical ja values of the 8-lead soic and 8-lead lfcsp for various pcb copper sizes. table 5. typical ja values copper size (mm 2 ) ja (c/w), soic ja (c/w), lfcsp 0 1 57.6 65.9 50 53.1 62.3 100 52.3 61.2 300 51.3 59.7 500 51.3 59.4 1 device soldered to minimum size pin traces. the junction temperature of the adp1706/adp1707/adp1708 can be calculated by t j = t a + ( p d ja ) (3) where: t a is the ambient temperature. p d is the power dissipation in the die, given by p d = [( v in C v out ) i load ] + ( v in i gnd ) (4) where: i load is the load current. i gnd is the ground current. v in and v out are the input and output voltages, respectively. power dissipation due to ground current is quite small and can be ignored. therefore, the junction temperature equation simplifies to the following: t j = t a + {[( v in C v out ) i load ] ja } (5) as shown in equation 5, for a given ambient temperature, input-to-output voltage differential, and continuous load current, a minimum copper size requirement exists for the pcb to ensure the junction temperature does not rise above 125c. figure 36 to figure 41 show junction temperature calculations for different ambient temperatures, load currents, v in to v out differentials, and areas of pcb copper. 140 0 0.5 5.0 v in ? v out (v) t j (c) 120 100 80 60 40 20 1.01.52.02.53.03.54.04.5 1ma 10ma 100ma 300ma 500ma 750ma 1a (load current) max t j (do not operate above this point) 06640-035 figure 36. 500 mm 2 of pcb copper, t a = 25c, soic
adp1706/adp1707/adp1708 rev. 0 | page 14 of 20 140 0 0.5 5.0 v in ? v out (v) t j (c) 120 100 80 60 40 20 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1ma 10ma 100ma 300ma 500ma 750ma 1a (load current) max t j (do not operate above this point) 06640-036 figure 37. 100 mm 2 of pcb copper, t a = 25c, soic 140 0 0.5 5.0 v in ? v out (v) t j (c) 120 100 80 60 40 20 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1ma 10ma 100ma 300ma 500ma 750ma 1a (load current) max t j (do not operate above this point) 06640-037 figure 38. 0 mm 2 of pcb copper, t a = 25c, soic 140 0 0.5 5.0 v in ? v out (v) t j (c) 120 100 80 60 40 20 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1ma 10ma 100ma 300ma 500ma 750ma 1a (load current) max t j (do not operate above this point) 06640-038 figure 39. 500 mm 2 of pcb copper, t a = 25c, lfcsp 140 0 0.5 5.0 v in ? v out (v) t j (c) 120 100 80 60 40 20 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1ma 10ma 100ma 300ma 500ma 750ma 1a (load current) max t j (do not operate above this point) 06640-039 figure 40. 100 mm 2 of pcb copper, t a = 25c, lfcsp 140 0 0.5 5.0 v in ? v out (v) t j (c) 120 100 80 60 40 20 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1ma 10ma 100ma 300ma 500ma 750ma 1a (load current) max t j (do not operate above this point) 06640-040 figure 41. 0 mm 2 of pcb copper, t a = 25c, lfcsp
adp1706/adp1707/adp1708 rev. 0 | page 15 of 20 pcb layout considerations heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the adp1706/adp1707/adp1708. however, as can be seen from table 5 , a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. the adp1706/adp1707/adp1708 feature an exposed pad on the bottom of both the soic and lfcsp packages to improve thermal performance. because the exposed pad is electrically connected to gnd inside the package, it is recommended that it also be connected to the ground plane on the pcb with a sufficient amount of copper. here are a few general tips when designing pcbs: ? place the input capacitor as close as possible to the in and gnd pins. ? place the output capacitor as close as possible to the out and gnd pins. ? for the adp1706, place the soft start capacitor as close as possible to the ss pin. ? connect the load as close as possible to the out and sense pins. use of 0402 or 0603 size capacitors and resistors achieves the smallest possible footprint solution on boards where area is limited. gnd gnd gnd gnd en adj/trk/ss vin vout j1 r2 r1 u1 c1 c2 c3 adp1706/adp1707/adp1708 soic8 analog devices 06640-041 figure 42. example pcb layout
adp1706/adp1707/adp1708 rev. 0 | page 16 of 20 outline dimensions compliant to jedec standards ms-012-a a controlling dimensions are in millimeter; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. 060506- a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.050) 0.40 (0.016) 0.50 (0.020) 0.25 (0.010) 45 8 0 1.75 (0.069) 1.35 (0.053) 1.65 (0.065) 1.25 (0.049) seating plane 85 4 1 5.00 (0.197) 4.90 (0.193) 4.80 (0.189) 4.00 (0.157) 3.90 (0.154) 3.80 (0.150) 1.27 (0.05) bsc 6.20 (0.244) 6.00 (0.236) 5.80 (0.228) 0.51 (0.020) 0.31 (0.012) coplanarity 0.10 top view 3.098 (0.122) bottom view (pins up) 2.41 (0.095) 0.10 (0.004) max figure 43. 8-lead standard small outline package, with expose pad [soic_n_ep] narrow body (rd-8-2) dimensions shown in millimeters and (inches) 0 61507-b 1 exposed pa d (bottom view) 0.50 bsc pin 1 indicator 0.50 0.40 0.30 top view 12 max 0.70 max 0.65 typ 0.90 max 0.85 nom 0.05 max 0.01 nom 0.20 ref 1.89 1.74 1.59 4 1.60 1.45 1.30 3.25 3.00 sq 2.75 2.95 2.75 sq 2.55 5 8 pin 1 indicator seating plane 0.30 0.23 0.18 0.60 max 0.60 max figure 44. 8-lead frame chip scale package [lfcsp_vd] 3 mm 3 mm body, very thin, dual lead (cp-8-2) dimensions shown in millimeters
adp1706/adp1707/adp1708 rev. 0 | page 17 of 20 ordering guide model temperature range output voltage (v) pa ckage description package option branding adp1706ardz-0.75r7 1 C40c to +125c 0.75 8-lead soic_n_ep rd-8-2 adp1706ardz-0.8-r7 1 C40c to +125c 0.8 8-lead soic_n_ep rd-8-2 adp1706ardz-0.85r7 1 C40c to +125c 0.85 8-lead soic_n_ep rd-8-2 adp1706ardz-0.9-r7 1 C40c to +125c 0.9 8-lead soic_n_ep rd-8-2 adp1706ardz-0.95r7 1 C40c to +125c 0.95 8-lead soic_n_ep rd-8-2 adp1706ardz-1.0-r7 1 C40c to +125c 1.0 8-lead soic_n_ep rd-8-2 adp1706ardz-1.05r7 1 C40c to +125c 1.05 8-lead soic_n_ep rd-8-2 adp1706ardz-1.1-r7 1 C40c to +125c 1.1 8-lead soic_n_ep rd-8-2 adp1706ardz-1.15r7 1 C40c to +125c 1.15 8-lead soic_n_ep rd-8-2 adp1706ardz-1.2-r7 1 C40c to +125c 1.2 8-lead soic_n_ep rd-8-2 adp1706ardz-1.3-r7 1 C40c to +125c 1.3 8-lead soic_n_ep rd-8-2 adp1706ardz-1.5-r7 1 C40c to +125c 1.5 8-lead soic_n_ep rd-8-2 adp1706ardz-1.8-r7 1 C40c to +125c 1.8 8-lead soic_n_ep rd-8-2 adp1706ardz-2.5-r7 1 C40c to +125c 2.5 8-lead soic_n_ep rd-8-2 adp1706ardz-3.0-r7 1 C40c to +125c 3.0 8-lead soic_n_ep rd-8-2 adp1706ardz-3.3-r7 1 C40c to +125c 3.3 8-lead soic_n_ep rd-8-2 adp1706acpz-0.75r7 1 C40c to +125c 0.75 8-lead lfcsp_vd cp-8-2 l62 adp1706acpz-0.8-r7 1 C40c to +125c 0.8 8-lead lfcsp_vd cp-8-2 l63 adp1706acpz-0.85r7 1 C40c to +125c 0.85 8-lead lfcsp_vd cp-8-2 l64 adp1706acpz-0.9-r7 1 C40c to +125c 0.9 8-lead lfcsp_vd cp-8-2 l6j adp1706acpz-0.95r7 1 C40c to +125c 0.95 8-lead lfcsp_vd cp-8-2 l68 adp1706acpz-1.0-r7 1 C40c to +125c 1.0 8-lead lfcsp_vd cp-8-2 l65 adp1706acpz-1.05r7 1 C40c to +125c 1.05 8-lead lfcsp_vd cp-8-2 l67 adp1706acpz-1.1-r7 1 C40c to +125c 1.1 8-lead lfcsp_vd cp-8-2 l66 adp1706acpz-1.15r7 1 C40c to +125c 1.15 8-lead lfcsp_vd cp-8-2 l69 adp1706acpz-1.2-r7 1 C40c to +125c 1.2 8-lead lfcsp_vd cp-8-2 l6a adp1706acpz-1.3-r7 1 C40c to +125c 1.3 8-lead lfcsp_vd cp-8-2 l6c adp1706acpz-1.5-r7 1 C40c to +125c 1.5 8-lead lfcsp_vd cp-8-2 l6d adp1706acpz-1.8-r7 1 C40c to +125c 1.8 8-lead lfcsp_vd cp-8-2 l6h adp1706acpz-2.5-r7 1 C40c to +125c 2.5 8-lead lfcsp_vd cp-8-2 l6e adp1706acpz-3.0-r7 1 C40c to +125c 3.0 8-lead lfcsp_vd cp-8-2 l6f adp1706acpz-3.3-r7 1 C40c to +125c 3.3 8-lead lfcsp_vd cp-8-2 l6g adp1707ardz-0.75r7 1 C40c to +125c 0.75 8-lead soic_n_ep rd-8-2 adp1707ardz-0.8-r7 1 C40c to +125c 0.8 8-lead soic_n_ep rd-8-2 adp1707ardz-0.85r7 1 C40c to +125c 0.85 8-lead soic_n_ep rd-8-2 adp1707ardz-0.9-r7 1 C40c to +125c 0.9 8-lead soic_n_ep rd-8-2 adp1707ardz-0.95r7 1 C40c to +125c 0.95 8-lead soic_n_ep rd-8-2 adp1707ardz-1.0-r7 1 C40c to +125c 1.0 8-lead soic_n_ep rd-8-2 adp1707ardz-1.05r7 1 C40c to +125c 1.05 8-lead soic_n_ep rd-8-2 adp1707ardz-1.1-r7 1 C40c to +125c 1.1 8-lead soic_n_ep rd-8-2 adp1707ardz-1.15r7 1 C40c to +125c 1.15 8-lead soic_n_ep rd-8-2 adp1707ardz-1.2-r7 1 C40c to +125c 1.2 8-lead soic_n_ep rd-8-2 adp1707ardz-1.3-r7 1 C40c to +125c 1.3 8-lead soic_n_ep rd-8-2 adp1707ardz-1.5-r7 1 C40c to +125c 1.5 8-lead soic_n_ep rd-8-2 adp1707ardz-1.8-r7 1 C40c to +125c 1.8 8-lead soic_n_ep rd-8-2 adp1707ardz-2.5-r7 1 C40c to +125c 2.5 8-lead soic_n_ep rd-8-2 adp1707ardz-3.0-r7 1 C40c to +125c 3.0 8-lead soic_n_ep rd-8-2 adp1707ardz-3.3-r7 1 C40c to +125c 3.3 8-lead soic_n_ep rd-8-2
adp1706/adp1707/adp1708 rev. 0 | page 18 of 20 model temperature range output voltage (v) pa ckage description package option branding adp1707acpz-0.75r7 1 C40c to +125c 0.75 8-lead lfcsp_vd cp-8-2 l6p adp1707acpz-0.8-r7 1 C40c to +125c 0.8 8-lead lfcsp_vd cp-8-2 l6q adp1707acpz-0.85r7 1 C40c to +125c 0.85 8-lead lfcsp_vd cp-8-2 l6r adp1707acpz-0.9-r7 1 C40c to +125c 0.9 8-lead lfcsp_vd cp-8-2 l6s adp1707acpz-0.95r7 1 C40c to +125c 0.95 8-lead lfcsp_vd cp-8-2 l6t adp1707acpz-1.0-r7 1 C40c to +125c 1.0 8-lead lfcsp_vd cp-8-2 l6u adp1707acpz-1.05r7 1 C40c to +125c 1.05 8-lead lfcsp_vd cp-8-2 l6v adp1707acpz-1.1-r7 1 C40c to +125c 1.1 8-lead lfcsp_vd cp-8-2 l6w adp1707acpz-1.15r7 1 C40c to +125c 1.15 8-lead lfcsp_vd cp-8-2 l6x adp1707acpz-1.2-r7 1 C40c to +125c 1.2 8-lead lfcsp_vd cp-8-2 l6y adp1707acpz-1.3-r7 1 C40c to +125c 1.3 8-lead lfcsp_vd cp-8-2 l6z adp1707acpz-1.5-r7 1 C40c to +125c 1.5 8-lead lfcsp_vd cp-8-2 l70 adp1707acpz-1.8-r7 1 C40c to +125c 1.8 8-lead lfcsp_vd cp-8-2 l71 adp1707acpz-2.5-r7 1 C40c to +125c 2.5 8-lead lfcsp_vd cp-8-2 l72 adp1707acpz-3.0-r7 1 C40c to +125c 3.0 8-lead lfcsp_vd cp-8-2 l73 adp1707acpz-3.3-r7 1 C40c to +125c 3.3 8-lead lfcsp_vd cp-8-2 l74 adp1708ardz-r7 1 C40c to +125c 0.8 to 5.0 8-lead soic_n_ep rd-8-2 adp1708acpz-r7 1 C40c to +125c 0.8 to 5.0 8-lead lfcsp_vd cp-8-2 l7p adp1706-3.3-evalz 1 3.3 evaluation board adp1707-3.3-evalz 1 3.3 evaluation board adp1708-evalz 1 adjustable, but set to 1.6 v evaluation board 1 z = rohs compliant part.
adp1706/adp1707/adp1708 rev. 0 | page 19 of 20 notes
adp1706/adp1707/adp1708 rev. 0 | page 20 of 20 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06640-0-6/07(0)

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