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si9140 vishay siliconix document number: 70026 s-40699?rev. h, 19-apr-04 www.vishay.com 1 mp controller for high performance process power supplies features runs on 3.3- or 5-v supplies adjustable, high precision output voltage high frequency operation (>1 mhz) high efficiency synchronous switching full set of protection circuitry 2000-v esd rating (si9140cq/dq) description siliconix? si9140 buck converter ic is a high-performance, surface-mount switchmode controller made to power the new generation of low-voltage, high-performance micro- processors. the si9140 has an input voltage range of 3 to 6.5 v to simplify power supply designs in desktop pcs. its high-frequency switching capability and wide bandwidth feedback loop provide tight, absolute static and transient load regulation. circuits using the si9140 can be implemented with low-profile, inexpensive inductors, and will dramatically minimize power supply output and processor decoupling capacitance. the si9140 is designed to meet the stringent regulation requirements of new and future high-frequency microprocessors, while improving the overall efficiency in new ?green? systems. today?s state-of-the-art microprocessors run at frequencies over 100 mhz. processor clock speeds are going up and so are current requirements, but operating voltages are going down. these simultaneous changes have made dedicated, high-frequency, point-of-use buck converters an essential part of any system design. these point-of-use converters must operate at higher frequencies and provide wider feedback bandwidths than existing converters, which typically operate at less than 250 khz and have feedback bandwidths of less than 50 khz. the si9140?s 100-khz feedback loop bandwidth ensures a minimum improvement of one-half the required output/decoupling capacitance, resulting in a tremendous reduction in board size and cost of implementation. with the microprocessing power of any pc representing an investment of hundreds of dollars, designers need to ensure that the reliable operation of the processor will not be af fected by the power supply. the si9140 provides this assurance. a demo board, the si9140db, is available. SI9140CQ-T1 and si9140dq-t1 are available in lead free. application circuit c osc r6 13 u1 si9140 14 15 16 2 3 4 1 10 11 12 5 6 7 9 8 c7 r5 dr v dd v s v good d s comp uvlo set fb ni v ref enable gnd r osc c6 c5 c4 c9 r9 r8 r7 c3 + c2 pgnd mon c8 2 x si4435dy 2 x si4410dy r3 power-good r2 r1 r4 c1 v in v ccp + r12 0.1% c10 r11 r10 0.1% r13 l1 d1 v out c osc
si9140 vishay siliconix www.vishay.com 2 document number: 70026 s-40699?rev. h, 19-apr-04 absolute maximum ratings voltages referenced to gnd. v dd , v s 8 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p gnd 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dd to v s ? 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . linear inputs ? 0.3 v to v dd +0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . logic inputs ? 0.3 v to v dd +0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peak output drive current 350 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature ? 65 to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating junction temperature 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation (package)a 16-pin soic (y suffix) \b 900 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-pin tssop (q suffix) c 925 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . thermal impedance ( ja ) 16-pin soic (y suffix) 140 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-pin tssop (q suffix) 135 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating temperature c suffix 0 to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d suffix ? 40 to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes a. device mounted with all leads soldered or welded to pc board. b. derate 7.2 mw/ c above 25 c. c. derate 7.4 mw/ c above 25 c. * exposure to absolute maximum rating conditions for extended periods may affect device reliability. stresses above absolute maximum rating may cause permanent . damage. functional operation at conditions other than the operating conditions specified is not implied. only one absolute max imum rating should be applied at any one time recommended operating range voltages referenced to gnd. v dd 3 v to 6.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s 3 v to 6.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . f osc 20 khz to 2 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . r osc 5 k to 250 k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c osc 47 pf to 200 pf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . linear inputs 0 to v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital inputs 0 to v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ref load resistance >150 k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . specifications test conditions unless otherwise specified a 3 v v dd 6.5 v, v dd = v s limits c suffix 0 to 70 c d suffix ? 40 to 85 c parameter symbol 3 v v dd 6 . 5 v , v dd = v s gnd = p gnd min b typ max b unit reference output voltage v ref i ref = ? 10 a 1.455 1.545 v output voltage v ref t a = 25 c 1.477 1.50 1.523 v oscillator maximum frequency c f max v dd = 5 v, c osc = 47 pf, r osc = 5.0 k 2.0 accuracy f osc v dd = 5 v c osc = 100 pf, r osc = 7.50 k , t a = 25 c 0.85 1.0 1.15 mhz r osc voltage v rosc 1.0 v voltage stability c f/f 4 v v dd 6 v, ref to 5 v, t a = 25 c ? 8 8 % temperature stability c f/f referenced to 25 c 5 % error amplifier (c osc = gnd, osc disabled) input bias current i fb v ni = v ref , v fb = 1.0 v ? 1.0 1.0 a open loop voltage gain a vol 47 55 db offset voltage v os v ni = v ref ? 15 0 15 mv unity gain bandwidth c bw 10 mhz output current i ea source (v fb = 1 v, ni = v ref ) ? 2.0 ? 1.0 ma output current i ea sink (v fb = 2 v, ni = v ref ) 0.4 0.8 ma power supply rejection c p srr 3 v < v dd < 6.5 v 60 db uvlo set voltage monitor under voltage lockout v uvlohl uvlo set high to low 0.85 1.0 1.15 v under voltage lockout v uvlolh uvlo set low to high 1.2 v hysteresis v hys v uvlolh ? v uvlohl 175 mv
si9140 vishay siliconix document number: 70026 s-40699?rev. h, 19-apr-04 www.vishay.com 3 specifications limits c suffix 0 to 70 c d suffix ? 40 to 85 c test conditions unless otherwise specified a 3 v v dd 6.5 v, v dd = v s gnd = p gnd parameter unit max b typ min b test conditions unless otherwise specified a 3 v v dd 6.5 v, v dd = v s gnd = p gnd symbol uvlo set voltage monitor uvlo input current i uvlo(set) v uvlo = 0 to v dd ? 100 100 na output drive (d r and d s ) output high v oltage v oh v s = v dd = 5 v, i out = ? 10 ma 4.7 4.8 v output low voltage v ol v s = v dd = 5 v, i out = 10 ma 0.2 0.3 v peak output current i source v s = v dd = 5 v, v out = 0 v ? 380 ? 260 ma peak output current i sink v s = v dd = 5 v, v out = 5 v 200 300 ma break-before-make t bbm v dd = 6.5 v 40 ns logic enable t urn-on delay t den enable delay to output, en lh , v dd = 5 v 1.5 s enable logic low v enl 0.2 v dd v enable logic high v enh 0.8 v dd v enable input current i en enable = 0 to v dd ? 1.0 1.0 a v good comparator (voltage-good comparator) input offset voltage v os v in common mode voltage = v ref v dd = 5 v ? 45 0 45 mv input hysteresis v inhys v in common mode voltage = v ref , v dd = 5 v 10 mv input bias current i bmon v in = v ref , v dd = 5 v ? 1 0 1 a output sink i i sink v out = 5 v, v dd = 5 v 6 9 ma output low voltage v ol i out = 2 ma, v dd = 5 v 350 500 mv supply supply current?normal mode i dd f osc = 1 mhz, r osc = 7.50 k 1.6 2.3 ma supply current?standby mode i dd enable < 0.4 v 250 330 a notes a. 100 pf includes c stray on c osc . b. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data s heet. c. guaranteed by design, not subject to production testing. typical characteristics (25 c unless otherwise noted) 1.480 1.485 1.490 1.495 1.500 1.505 1.510 ? 50 ? 25 0 25 50 75 100 125 v ref vs. t emperature (v) ref v t ? temperature ( c) v dd = 3 v 1.485 1.490 1.495 1.500 1.505 1.510 1.515 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 v ref vs. supply v oltage v dd ? supply voltage (v) (v) ref v v ref with 10 a load v dd = 6 v
si9140 vishay siliconix www.vishay.com 4 document number: 70026 s-40699?rev. h, 19-apr-04 typical characteristics (25 c unless otherwise noted) 100 200 300 400 500 600 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 100 200 300 400 500 600 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 1.0 1.2 1.4 1.6 1.8 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 phase (deg) gain (db) 1.485 1.490 1.495 1.500 1.505 1.510 1.515 0 5 10 15 20 25 30 3.0, 3.6 v v ref vs. load current v ref ? sourcing current ( a) (v) ref v 5.0 v 6.5 v error amplifier gain and phase f ? frequency (mhz) 80 0 ? 30 ? 60 ? 90 ? 120 ? 150 60 40 20 0 ? 20 ? 40 0.0001 0.001 0.01 0.1 1 10 100 gain phase 25 c supply current vs. supply voltage and t emperature normal current (ma) v dd ? supply voltage (v) c l = 10 pf f = 1 mhz 0 c 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 standby current vs. supply voltage and t emperature a) standby current ( v dd ? supply voltage (v) t a = 85 c 25 c 210 230 220 240 250 260 70 c 0 c ? 40 c t a = 85 c 70 c ? 40 c dr sourcing current vs. supply v oltage dr sourcing current (ma) v dd ? supply voltage (v) dr sinking current vs. supply v oltage dr sinking current (ma) v dd ? supply voltage (v)
si9140 vishay siliconix document number: 70026 s-40699?rev. h, 19-apr-04 www.vishay.com 5 typical characteristics (25 c unless otherwise noted) 100 200 300 400 500 600 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 100 200 300 400 500 600 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 0.01 0.10 1.00 10.00 0.8 0.9 1.0 1.1 1.2 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 switching frequency vs. supply v oltage switching frequency (mhz) v dd ? supply voltage (v) r osc = 7.50 k c osc = 100 pf frequency vs. r osc /c osc c osc ? capacitance (pf) switching frequency (mhz) 4.99 k 12.1 k 24.9 k 49.9 k 100 k 249 k 40 300 200 ds sourcing vs. supply v oltage ds sourcing current (ma) v dd ? supply voltage (v) ds sinking current vs. supply v oltage ds sinking current (ma) v dd ? supply voltage (v) 115 135 155 175 195 215 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 20 30 40 50 60 70 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 enable turn-off delay to output uvlo hysteresis vs. supply v oltage output delay (ns) v dd ? su pp l y volta g e ( v ) v dd ? su pp l y volta g e ( v ) uvlo hysteresis (mv)
si9140 vishay siliconix www.vishay.com 6 document number: 70026 s-40699?rev. h, 19-apr-04 typical characteristics (25 c unless otherwise noted) 0 4 8 12 16 20 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 v good sinking current vs. suppl y voltage power good sinking current (ma) v dd ? supply voltage (v) pin configurations and ordering information 13 v dd v s mon d r v good d s comp pgnd fb ni v ref uvlo set c osc gnd r osc soic-16 14 15 16 2 3 4 1 10 11 12 5 6 7 9 8 top view enable 16 15 14 13 1 2 3 4 12 11 10 9 5 6 7 8 tssop-16 top view v dd v s mon d r v good d s comp pgnd fb ni v ref uvlo set c osc gnd r osc enable 13 ordering information?soic-16 part number temperature range si9140cy si9140cy-t1 0 to 70 c si9140cy-t1?e3 si9140dy si9140dy-t1 ? 40 to 85 c si9140dy-t1?e3 ordering informationtssop-16 part number temperature range si9140cq SI9140CQ-T1 0 to 70 c SI9140CQ-T1?e3 si9140dq si9140dq-t1 ? 40 to 85 c si9140dq-t1?e3
si9140 vishay siliconix document number: 70026 s-40699?rev. h, 19-apr-04 www.vishay.com 7 pin description pin 1: v dd the positive power supply for all functional blocks except output driver. a bypass capacitor of 0.1 f (minimum) is recommended. pin 2: mon non-inverting input of a comparator. inverting input is tied internally to reference voltage. this comparator is typically used to monitor the output voltage and to flag the processor when the output voltage falls out of regulation. pin 3: v good this is an open drain output. it will be held at ground when the voltage at mon (pin 2) is less than the internal reference. an external pull-up resistor will pull this pin high if the mon pin (pin 2) is higher than the v ref . (refer to pin 2 description.) pin 4: comp this pin is the output of the error amplifier. a compensation network is connected from this pin to the fb pin to stabilize the system. this pin drives one input of the internal pulse width modulation comparator. pin 5: fb the inverting input of the error amplifier. an external resistor divider is connected to this pin to set the regulated output voltage. the compensation network is also connected to this pin. pin 6: ni the non-inverting input of the error amplifier. in normal operation it is externally connected to v ref or an external reference. pin 7: v ref this pin supplies a 1.5-v reference. pin 8: gnd (ground) pin 9: enable a logic high on this pin allows normal operation. a logic low places the chip in the standby mode. in standby mode normal operation is disabled, supply current is reduced, the oscillator stops and d s goes high while d r goes low. pin 10: r osc a resistor connected from this pin to ground sets the oscillator?s capacitor c osc , charge and discharge current. see the oscillator section of the description of operation. pin 11: c osc an external capacitor is connected to this pin to set the oscillator frequency. f osc 0.75 r osc c osc (at v dd = 5.0 v) pin 12: uvlo set this pin will place the chip in the standby mode if the uvlo set voltage drops below 1.2 v. once the uvlo set voltage exceeds 1.2 v, the chip operates normally. there is a built-in hysteresis of 165 mv. pin 13: p gnd the negative return for the v s supply. pin 14: d s this cmos push-pull output pin drives the external p-channel mosfet. this pin will be high in the standby mode. a break-before-make function between d s and d r is built-in. pin 15: d r this cmos push-pull output pin drives the external n-channel mosfet. this pin will be low in the standby mode. a break-before-make function between the d s and d r is built-in. pin 16: v s the positive terminal of the power supply which powers the cmos output drivers. a bypass capacitor is required.
si9140 vishay siliconix www.vishay.com 8 document number: 70026 s-40699?rev. h, 19-apr-04 functional block diagram ? + uvlo set comp c osc fb ni v s d s p gnd gnd v uvlo oscillator v ref 1.5-v reference generator r osc enable v dd uvlo error amp logic and bbm control ? + driver d r driver p gnd v s v s p gnd ? + mon v ref v good v ref v uvlo timing waveforms d s t bbm d r v cosc v comp enable 1.5 v 0 v 5 v 1 v
si9140 vishay siliconix document number: 70026 s-40699?rev. h, 19-apr-04 www.vishay.com 9 description of operation schematics of the si9140 dc-to-dc conversion solutions for high-performance pc microprocessors are shown in figure 1 and 2 respectively. these solutions are geared to meet the extremely demanding transient regulation and power requirements of these new microprocessors at minimal cost and with a minimal parts count. the two solutions are nearly identical, except for slight variations in output voltage, load transient amplitude, and specified power. figure 3 is a schematic diagram for a 3.3-v logic converter. r6 4.99 k 13 u1 si9140 14 15 16 2 3 4 1 10 11 12 5 6 7 9 8 c7 0.1 f r5 240 k dr v dd v s v good d s comp uvlo set fb ni v ref enable c osc gnd r osc c6 0.1 f c5, 180 pf c4, 5.6 pf c9 220 pf r9 11 k r8 40.2 k r7 100 k c3 0.1 f + c2 3 x 330 f 6.3v os-con pgnd mon c8 1 f 2 x si4435dy 2 x si4410dy r3 100 power-good r2 10 k r1 20 k r4 24.9 k c1 2 x 220 f 10 v os-con v ccp + r12 13.3 k, 0.1% c10, 180 pf r11, 4.7 k 2.9 v (v out ) r10 14.2 k 0.1% r13 10 k figure 1. 2.9 v @ 10 a l1 1.5 h d1 d1fs4 5 v (v in ) coiltronics ctx07-12877 power-good figure 2. 2.5 v @ 8.5 a r6 4.99 k 13 u1 si9140 14 15 16 2 3 4 1 10 11 12 5 6 7 9 8 c7 0.1 f r5 240 k dr v dd v s v good d s comp uvlo set fb ni v ref enable c osc gnd r osc c6 0.1 f c5, 180 pf c4, 5.6 pf c9 220 pf r9 11 k r8 40.2 k r7 100 k c3 0.1 f + c2 3 x 330 f 6.3v os-con pgnd mon c8 1 f 2 x si4435dy si4410dy r3 100 r2 10 k r1 20 k r4 40.2 k c1 2 x 220 f 10 v os-con v ccp + r12 13.3 k, 0.1% c10, 180 pf r11, 4.7 k 2.5 v (v out ) r10 20 k 0.1% r13 10 k l1 1.5 h d1 d1fs4 5 v (v in ) coiltronics ctx07-12877
si9140 vishay siliconix www.vishay.com 10 document number: 70026 s-40699?rev. h, 19-apr-04 figure 3. 3.3 v@ 5 a r6 4.99 k 13 u1 si9140 14 15 16 2 3 4 1 10 11 12 5 6 7 9 8 c7 0.1 f r5 16.2 k dr v dd v s v good d s comp uvlo set fb ni v ref enable c osc gnd r osc c6 0.1 f c5, 1000 pf c4, 330 pf c9 220 pf r9 20 k r8 40.2 k r7 100 k c3 0.1 f + c2 3 x 330 f tps tantalum pgnd mon c8 1 f si4435dy si4410dy r3 100 c1 2 x 220 f tps tantalum + r12, 13.3 k c10 1000 pf r11 4.7 k 3.3 v (v out ) r10 11 k r13 10 k l1 10 h d1 d1fs4 5 v (v in ) coiltronics ctx07-12891 figure 4. 1.5-v converter for gtl + bus @ 5 a r6 4.99 k 13 u1 si9140 14 15 16 2 3 4 1 10 11 12 5 6 7 9 8 c7 0.1 f r5 16.2 k dr v dd v s v good d s comp uvlo set fb ni v ref enable c osc gnd r osc c6 0.1 f c5, 1000 pf c4, 330 pf c9 220 pf r9 20 k r8 40.2 k r7 100 k c3 0.1 f + c2 3 x 330 f tps tantalum pgnd mon c8 1 f si4435dy si4410dy r3 100 c1 2 x 220 f tps tantalum 5 v (v in ) + r12, 13.3 k 1.5 v (v out ) r13 10 k l1 10 h d1 d1fs4 coiltronics ctx07-12891 c10 1000 pf r11 4.7 k figure 4 is a schematic diagram of a converter which produces 1.5 v for a gtl bus. each of these dc-to-dc converters has four major sections: pwm controller?regulates the output voltage switch and synchronous rectification mosfets?delivers the power to the load inductor?filters and stores the energy input/output capacitor?filters the ripple
si9140 vishay siliconix document number: 70026 s-40699?rev. h, 19-apr-04 www.vishay.com 11 the functions of each circuit are explained in detail below. design equations are provided to optimize each application circuit. pwm controller there are generally two types of controllers, voltage mode or current mode. in voltage mode control, an error voltage is generated by comparing the output voltage to the reference voltage. the error voltage is then compared to an artificial ramp, and the result is the duty cycle necessary to regulate the output voltage. in current mode, an actual inductor current is used, in place of the artificial ramp, to sense the voltage across the current sense resistor. the logic and timing sequence for voltage mode control is shown in figure 5. the si9140 offers voltage mode control, which is better suited for applications requiring both fast transient response and high output current. current mode control requires a current sense resistor to monitor the inductor current. a 10-m sense resistor in a 10-a design will dissipate 1 w, decreasing ef ficiency by 3.5%. such a design would require a 2-w resistor to satisfy derating criteria, besides requiring additional boar d space. voltage mode control is a second-order lc system and has a faster natural transient response compared to current mode control (first-order rc system). current mode has the advantage of providing an inherently good line regulation. but the situations where line voltage is fixed, as in the point-of-use conversion for microprocessors, this feature is wasted. current mode control also provides automatic pulse-to-pulse current limiting. this feature requires a current sense resistor as stated above. these characteristics make voltage mode control ideal for high-end microprocessor power supplies. figure 5. voltage mode logic and timing diagram osc comp d s d r the error amplifier of the pwm controller plays a major role in determining the output voltage, stability, and the transient response of the power supply. in the si9140, the non-inverting input of the error amplifier is available for use with an external precision reference for tighter tolerance regulation. with a two-pair lead-lag compensation network, it is easy to create a stable 100-khz closed loop converter with the si9140 error amplifier. the si9140 achieves the 5- s transient response by generating a 100-khz closed-loop bandwidth. this is pos sible only by switching above 400 khz and utilizing an error amplifier with at least a 10-mhz bandwidth. the si9140 controller has a 25-mhz unity gain bandwidth error amplifier. the switching frequency must be at least four times greater than the desired closed-loop bandwidth to prevent oscillation. to respond to the stimuli, the error amplifier bandwidth needs to be at least 10 times larger than the desired bandwidth. figure 6. 100-khz bw synchronous buck converter gain phase frequency (hz) gain (db) phase (deg) the si9140 solution requires only three 330- f os-con capacitors on the output of power supply to meet the 10-a transient requirement. other converter solutions on the market with 20- to 50-khz closed loop bandwidths typically require two to five times the output capacitance specified above to match the si9140?s performance. the theoretical issues and analytical steps involved in compensating a feedback network are beyond the scope of this application note. however, to ease the converter design for today?s high-performance microprocessors, typical component values for the feedback network are provided in table 1 for various combinations of output capacitance. figure 6 shows the bode plot (frequency domain) of the 2.9-v converter shown schematically in figure 1.
si9140 vishay siliconix www.vishay.com 12 document number: 70026 s-40699?rev. h, 19-apr-04 table 1. feedback network component values total output and decoupling capacitance c4 c5 r5 3 x 330 f a os-con . . . . . . . . . 6 x 100 f b tantalum . . . . . . . . . 25 x 1 f b ceramic . . . . . . . . . . 5.6 pf 180 pf 240 k 2 x 330 f a os-con . . . . . . . . . 4 x 100 f b tantalum . . . . . . . . . 25 x 1 f b ceramic . . . . . . . . . . 10 pf 220 pf 200 k 3 x 330 f a tantalum . . . . . . . . . 4 x 100 f b tantalum . . . . . . . . . 25 x 1 f b ceramic . . . . . . . . . . 10 pf 100 pf 100 k a. power supply output capacitance. b. processor decoupling capacitance. figure 7 is the measured transient response (time domain) for the 10-a step response. the measured transient response shows the processor voltage regulating to 70 mv, well within the 0.145-v regulation. the si9140?s switching frequency is determined by the external r osc and c osc values, allowing designers to set the switching frequency of their choice. for applications where space is the main constraint, the switching frequency can be set as high as 2 mhz to minimize inductor and output capacitor size. in applications where ef ficiency is the main concern, the switching frequency can be set low to maximize battery life. the switching frequency for high-performance processors applications circuits are set for 400 khz. the equation for switching frequency is: f osc 0.75 r osc c osc (at v dd = 5.0 v) the precision reference is set at 1.5 v 1.5%. the reference is capable of sourcing up to 1 ma. the combination of 1.5% reference and 3.5% transient load regulation safely complies with the 5% regulation requirement. if additional margin is desired, an external precision reference can be used in place of the internal 1.5-v reference. switching and synchronous rectification mosfets the synchronous gate drive outputs of si9140 pwm controller drive the high-side p-channel switch mosfet and the low-side n-channel synchronous rectifier mosfet. the physical difference between the non-synchronous to synchronous rectification requires an additional mosfet across the free-wheeling diode (d1). the inductor current will reach 0 a if the peak-to-peak inductor current equals twice the output current. in synchronous rectification mode, current is allowed to flow backwards from the inductor (l1) through the synchronous mosfet (q3) and to the output capacitor (c2) once the current reaches 0 a. refer to schematic on figure 1. in non-synchronous rectification, the diode (d1) prevents the current from flowing in the reverse direction. this minor difference has a drastic af fect on the performance of a power supply. by allowing the current to flow in the reverse direction, it preserves the continuous inductor current mode, maintaining the wide converter bandwidth and improving efficiency. also, maintaining the continuous current mode during light load to full load guarantees consistent transient response throughout a wide range of load conditions. the transition from stop clock and auto halt to active mode is a perfect example. the microprocessor current can vary from 0.5 a to 10 a or greater during these transitions. if the converter were to operate in discontinuous current mode during the stop clock and auto halt modes, the transfer function of the converter would be different compared to operation in the active mode. in discontinuous current mode, the converter bandwidth can be 10 to 15 times lower than the continuous current mode (figure 8). therefore, the response time will also be 10 to 15 times slower, violating the microprocessor?s regulator requirements. this could result in unreliable operation of the microprocessor. figure 7. a) transient response from 0- to 10-a step load b) transient response from 10- to 0-a step load mp voltage mp current 2.9 v 10 a 0 a 5 a
si9140 vishay siliconix document number: 70026 s-40699?rev. h, 19-apr-04 www.vishay.com 13 for these reasons, synchronous rectification is a must in today?s microprocessors power supply design. pulse- skipping modes are undesirable in high-performance microprocessor power supplies, especially when the minimum load current is as high as 500 ma. this pulse-skipping mode disables the synchronous rectification during light load and generates a random noise spectrum which may produce emi problems. siliconix? trenchfet technology has resulted in 20-m n-channel (si4410dy) and 35-m p-channel (si4435dy) mosfets in the so-8 surface-mount package. these little foot products totally eliminate the need for an external heatsink. figure 8. non-synchronous converter bw gain phase frequency (hz) gain (db) phase (deg) worst case current of 10 a can be handled with two paralleled si4435dy and two paralleled si4410dy mosfets, which results in the efficiency levels shown in figure 9. figure 9. efficiency 80 85 90 95 100 0246810 efficiency (%) i out (a) v in = 5 v v out = 2.9 v good electrical designs must provide an adequate margin for the specification, but they should not be grossly overdesigned to lower costs. little foot power mosfets allow designers to balance cost and performance considerations without sacrificing either. if the design requires only an 8.5-a continuous current, for example, one si4410dy can be eliminated. table 2 shows the number of mosfets r equired to handle the various output current levels of today?s high- performance microprocessors. for other output power levels, the equations below should be used to calculate the power handling capab ility of the mosfet. table 2. converter requirements (figures 1, 2, and 3) i o (a) maxi- mum quantity high-side p-channel si4435dy quantity low-side n-channel si4410dy quantity input (c1-c3) capacitor os-con 220 f 5 a 1 1 1 8.5 a 2 1 2 10 a 2 2 2 14.5 a 3 2 3
si9140 vishay siliconix www.vishay.com 14 document number: 70026 s-40699?rev. h, 19-apr-04 p dissipation in switch i rms sw 2 r sw q sw v in f osc 2 i pp v o c f osc 2 i rmssw = switch rms current r sw = switch on resistance i rmsrect = synchronous rectifier rms current r rect = synchronous rectifier on resistance q sw = total gate charge of switch q rect = total gate charge of synchronous rectifier v in = input voltage v o = output voltage i o = output current f osc = switching frequency = efficiency c = crossover time i rms sw i peak 2 i pp 2 i peak i pp v o 3 v in
i pp = i peak + i i v o 2 l f osc v in i peak p in ?(0.5 v o i) v o p in v o i o i peak i pp p dissipation in synchronous rectification i rms rect 2 r rect q rect v in f osc 2 i rms rect i peak 2 i pp 2 i peak i pp (v in ?v o ) 3 v in
i o 0 a current time inductor the size and value of the inductor are critical in meeting overall circuit dimensional requirements and in assuring proper transient voltage regulation. the size of the core is determined by the output power, the material of the core, and the operating frequency. to handle higher output power, the core must be larger. luckily, a higher switching frequency will lower the inductance value, decreasing the core size. how ever, a higher switching frequency can also mean greater core loss. in applications where the dc flux density is high and the ac flux density swing is only 100 to 200 gauss, the core loss will be negligible compared to the wire loss. kool mu is the best material to use at 500 khz to deliver 30 w in the minimum volume. ferrite has a lower core cost and loss at this frequency, but the core size is fairly large. if the power supply is designed on the motherboard and space is not a critical issue, ferrite is a better choice. the higher switching frequency reduces the core size by decreasing the amount of energy that must be stored between switching periods. it also accelerates the transient response to the load by decreasing the inductance value. the inductance is calculated with following equation:
si9140 vishay siliconix document number: 70026 s-40699?rev. h, 19-apr-04 www.vishay.com 15 l v o 2 v in i f osc i = desired output current ripple. typically i = 25% of maximum output current. finally, the time required to ramp up the current in the inductor can be reduced with smaller inductance. a quick response from the power supply relaxes the decoupling capacitance required at the microprocessor, reducing the overall solution cost and size. input capacitor the input capacitor?s function is to filter the raw power and serve as the local power source to eliminate power-up and transient surge failures. the type and characteristics of input capacitors are determined by the input power and inductance of the step-down converter. the ripple current handling requirement usually dominates the selection criteria. the capacitance required to maintain regulation will automatically be achieved once it meets the ripple current requirement. the following equation calculates the ripple current of the input capacitor: i ripple i rmssw 2 ?i in 2
an aluminum-electrolytic capacitor from sanyo (os-con), avx (tps tantalum), or nichicon (pl series) should be used in high-power (30-w) applications to handle the ripple current. the sanyo capacitor is smaller and handles higher ripple current than nichicon, but at higher cost than the nichicon product. the avx tantalum capacitor has the best capacitance and current handling capability per volume ratio, but it takes extra surface area compared to os-con or pl series. the tps capacitors, lead time and cost have increased drastically in the recent past due to high demand, causing designers to shy away from the tps tantalum capacitors. nichicon capacitors can be used to provide an economical solution if space is available or a large bulk capacitance is already present on the input line. the number of sanyo (os-con) input capacitors required to handle various output currents are specified in table 2. output capacitor to regulate the microprocessor?s input voltage within 145 mv during 10-a load transients, a large output capacitance with low esr is required. the output capacitor of the power supply and decoupling capacitors at the microprocessor must hold up the processor voltage until the power supply responds to the change. even with fastest known switching solution, it still takes three 330- f os-con capacitors to handle the load transient. if it weren?t for the 10-a load transient, the output capacitor would not need a low esr value. the fundamental output ripple current in a continuous step-down converter is much lower than the input ripple current. maintaining voltage regulation during transients requires an esr in the range of 30 m . for microprocessors with lower transient requirements, the number of output and decoupling capacitors can be reduced. the lower transient requirements also allows greater consideration for tantalum or nichicon pl series capacitors. conclusion the si9140 synchronous buck controller?s ability to switch up to 1 mhz combined with a 25-mhz error amplifier provides the best solution in powering high- performance microprocessors. the high switching frequency reduces inductor size without compromising output ripple voltage. the wide converter bandwidth generated with the help of a 25-mhz error amplifier reduces the amount of decoupling capacitors required to handle the extreme transient requirement. the si9140?s synchronous fixed-frequency operation eliminates the pulse skipping mode that generates random unpredictable emi/emc problems in desktop and notebook computers. the synchronous rectification also allows the converter to operate in continuous current mode, independent of output load current. this preserves the wide closed-loop converter bandwidth required to meet the transient demand of the microprocessor as it transitions from stop clock and auto halt to active mode. the synchronous rectification improves the efficiency of the converter by substituting the much smaller i 2 r mosfet loss for the vi diode loss. the need for heatsinking is eliminated by using low r ds(on) trenchfet s (si4410dy and si4435dy).
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all leads 0.101 mm 0.004 in e h c d e b a1 l 4 3 12 8 7 56 13 14 16 15 9 10 12 11 package information vishay siliconix document number: 72807 28-jan-04 www.vishay.com 1 soic (narrow): 16-lead (power ic only) jedec part number: ms-012 millimeters inches dim min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.38 0.51 0.015 0.020 c 0.18 0.23 0.007 0.009 d 9.80 10.00 0.385 0.393 e 3.80 4.00 0.149 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 l 0.50 0.93 0.020 0.037 0 8 0 8 ecn: s-40080?rev. a, 02-feb-04 dwg: 5912
vishay siliconix package information document number: 74417 23-oct-06 www.vishay.com 1 symbols dimensions in millimeters min nom max a - 1.10 1.20 a1 0.05 0.10 0.15 a2 - 1.00 1.05 b 0.22 0.28 0.38 c - 0.127 - d 4.90 5.00 5.10 e 6.10 6.40 6.70 e1 4.30 4.40 4.50 e-0.65- l 0.50 0.60 0.70 l1 0.90 1.00 1.10 y--0.10 1036 ecn: s-61920-rev. d, 23-oct-06 dwg: 5624 tssop: 16-lead
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