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march 1997 ml6510 * series programmable adaptive clock manager (pacman?) 1 system block diagram general description the ml6510 (super pacman?) is a programmable adaptive clock manager which offers an ideal solution for managing high speed synchronous clock distribution in next generation, high speed personal computer and workstation system designs. it provides eight channels of deskew buffers that adaptively compensate for clock skew using only a single trace. the input clock can be either ttl or pecl, selected by a bit in the control register. frequency multiplication or division is possible using the m&n divider ratio, within the maximum frequency limit. 0.5x, 1x, 2x and 4x clocks can be easily realized. the ml6510 is implemented using a low jitter pll with on-chip loop filter. the ml6510 deskew buffers adaptively compensate for clock skew on pc boards. an internal skew sense circuit is used to sense the skew caused by the pcb trace and load delays. the sensing is done by detecting a reflection from the load and the skew is corrected adaptively via a unique phase control delay circuit to provide low load-to-load skew, at the end of the pcb traces. additionally, the ml6510 supports pecl reference clock outputs for use in the generation of clock trees with m inimal part-to-part skew. the chip configuration can be programmed to generate the desired output frequency using the internal rom or an external serial eeprom or a standard two-wire serial microprocessor interface. * so me pa ck ag es a re ob so l ete features n input clocks can be either ttl or pecl with low input to output clock phase error n 8 independent, automatically deskewed clock outputs with up to 5ns of on-board deskew range (10ns round trip) n controlled edge rate ttl-compatible cmos clock outputs capable of driving 40 w pcb traces n 10 to 80mhz (6510-80) or 10 to 130mhz (6510-130) input and output clock frequency range n less than 500ps skew between inputs at the device loads n small-swing reference clock outputs for minimizing part-to-part skew n frequency multiplication or division is possible using the m&n divider ratio n lock output indicates pll and deskew buffer lock n test mode operation allows pll and deskew buffer bypass for board debug n supports industry standard processors like pentium,? mips, sparc,? powerpc,? alpha,? etc. cpu cache ram local bus memory bus cache controller memory bus controller ml6510 clk clock out to components 8 clock subsystem clock in
2 ml6510 block diagram m n clk inl pll phase detector clk0 (to remote chip) fb0 (from remote chip) clk1 fb1 fb7 clk7 zero delay max delay deskew buffer 0 deskew buffer 1 deskew buffer 7 maximum delay programming and control logic reset lock md in r0mmsb mclk md out max delay zero delay voltage controlled delay drive circuit sense circuit r clk inh ref clock rclkh rclkl fb6 dgnd6 clk6 dvcc67 clk7 dgnd7 fb7 rommsb avcc2 agnd2 clk inl clk3 dvcc23 clk2 dgnd2 fb2 fb1 dgnd1 clk1 dvcc01 clk0 dgnd0 18 19 20 21 22 dgnd3 fb3 agnd1 avcc1 fb4 dgnd4 clk4 dvcc45 clk5 dgnd5 fb5 fb0 md in md out mclk reset lock agnd3 avcc3 rclkl rclkh clk inh 23 28 7 8 9 10 11 12 13 14 15 16 17 65432 39 38 37 36 35 34 33 32 31 30 29 140 27 41 26 42 25 43 24 44 ml6510 44-lead plcc (q44) top view pin connection
3 ml6510 pin description pin number name description 32 rommsb msb of the internal rom address. tie to gnd if not used. see section on programming the ml6510. 20 md out programming pin. see section on programming the ml6510. 19 md in programming pin. see section on programming the ml6510. 21 mclk programming pin. see section on programming the ml6510. 22 reset reset all internal circuits. asserted polarity is low. 23 lock indicates when the pll and deskew buffers have locked. asserted polarity is high. 28 clk inh input clock pins. for ttl clock reference use clk inh pin 29 clk inl shorted to the clk inl pin. for pecl clock reference drive pins differentially. input clock type is selected by the cs bit in the shift register. 16,14,9,7, clk[0C7] clock outputs 44, 42, 37, 35 18,12,11,5, fb[0C7] clock feedback inputs for the deskew buffers 2, 40, 39, 33 3,31 avcc[1C3] analog circuitry supply pins, separated from noisy digital supply pins to 25 provide isolation. all supplies are nominally +5v. 4, 30, 24 agnd[1C3] analog circuitry ground pins 15 dvcc01 digital supply pin for clk0 and clk1 output buffers. nominally +5v. 8 dvcc23 digital supply pin for clk2 and clk3 output buffers. nominally +5v. 43 dvcc45 digital supply pin for clk4 and clk5 output buffers. nominally +5v. 36 dvcc67 digital supply pin for clk6 and clk7 output buffers. nominally +5v. 17, 13, 10, 6, dgnd[0C7] digital ground pins for clk [0C7] output buffers. each clock output buffer has 1, 41, 38, 34 its own ground pin to avoid crosstalk and ground bounce problems. 26 rclkl differential reference clock output used to minimize 27 rclkh part-to-part skew when building clock trees with other pacman integrated circuits.
4 ml6510 absolute maximum ratings vcc supply voltage range ............................ C0.3v to 6v input voltage range .................................... C0.3v to vcc output current clk[0C7] ........................................................ 70ma all other outputs ............................................. 10ma junction temperature .............................................. 150 c storage temperature ................................ C65 c to 150 c thermal resistance ( q ja ) ....................................... 54 c/w electrical characteristics the following specifications apply over the recommended operating conditions of dvcc = avcc = 5v 5% and ambient temperature between 0 c and 70 c. loading conditions are specified individually (note 1) symbol parameter conditions min typ max unit supply dvccxx supply current for each pair f clkx = 0 50 m a of clock outputs c l = 20pf, z o = 50 w 40 60 ma f out = 80mhz iavcc1 static supply current, avcc1 pin 100 120 ma iavcc2 static supply current, avcc2 pin 35 40 ma iavcc3 static supply current, avcc3 pin 1 2 ma low frequency inputs and outputs (rommsb, md out , md in , mclk, reset , lock) v ih high level input voltage dvcc C 0.5 v v il low level input voltage dgnd + 0.5 v v oh high level output voltage, i oh = C100 m a dvcc C 0.5 v mclk and mdin v ol low level output voltage, i ol = +200 m a dgnd + 0.5 v mclk and mdin v oh high level output voltage, i oh = C100 m a 2.4 v lock output i oh = C10 m a dvcc C 0.5 v v ol low level output voltage, i ol = +1 ma 0.4 v lock output i in static input current 10 m a c in input capacitance 5 pf high frequency inputs and outputs (clk inh , clk inl , fb[0-7], clk[0-7]) v ih high level input voltage cs = 0 (ttl input clock) 2.0 v cs = 1 (pecl input clock) avcc C 1.165 avcc C 0.88 v v il low level input voltage cs = 0 (ttl input clock) 0.8 v cs = 1 (pecl input clock) avcc C 1.810 avcc C 1.475 v v icm common mode input voltage cs = 1 (pecl input clock) 2.0 avcc C 0.4 v range for pecl reference clocks i ih high level input current v ih = 2.4v 100 m a i il low level input current v il = 0.4v C400 m a v oh high level output voltage i oh = C60ma 2.4 v v ol low level output voltage i ol = +60ma 0.4 v
5 ml6510 electrical characteristics (continued) symbol parameter conditions min typ max unit ac characteristics rise time, fall time and duty cycle are measured for a generic load; (see load conditions section). t r rise time, load [0-7] output 0.8 ? 2.0v, 80mhz 150 1500 ps t f fall time, load [0-7] output 2.0 ? 0.8v, 80mhz 150 1500 ps f in input frequency, clk in pin 10 80 mhz f out output frequency , clk [0-7] ml6510-80 10 80 mhz output ml6510-130 (note 2) 10 130 mhz f vco pll vco operating frequency 80 160 mhz dc output duty cycle measured at device load, at 1.5v 40 60 % t jitter output jitter cycle-to-cycle 75 ps peak-to-peak 150 ps t lock pll and deskew lock time after programming is complete 11 ms skew characteristics all skew measurements are made at the load, at 1.5v threshold each output load can vary independently within the specified range for a generic load (see load conditions section). t skewr output to output rising 500 ps edge skew, all clocks t skewf output to output output clock frequency 3 50mhz 1.5 ns falling edge skew t skewio clk in input to any n = m = 0 600 ps load [0-7] output rising edge skew n 3 2, m 3 2 1.25 ns t range round trip delay clkx to fbx output frequency < 50mhz 0 10 ns pin; output clk period = t clk output frequency 3 50mhz 0 t clk /2 t skewb output-to-output rising providing first (see load 250 ps edge skew, between matched conditions) order matching loads order matching between outputs part-to-part skew characteristics skew measured at the loads, at 1.5v threshold. reference clock output pins drive clock input pins of another ml6510. t pp1 total load-to-load skew between slave chip cs = 1, cm = 1 and 1 ns multiple chips interfaced with n = 0, m = 0; rclk outputs to reference clock pins. clk in inputs distance less than 2" t pp2 total load-to-load skew between slave chip cs = 1, cm = 1 and 1 ns multiple chips interfaced with n 3 2, m 3 2; rclk outputs to reference clock pins. clk in inputs distance less than 2" programming timing characteristics t reset reset assertion pulse 50 ns width t a1 aux mode mclk high time 2000 ns t a2 aux mode mclk low time 2000 ns t a3 aux mode md out data 10 ns hold time t a4 aux mode md out data 10 ns setup time t a5 aux mode mclk period 5000 ns
6 ml6510 electrical characteristics (continued) symbol parameter conditions min typ max unit programming timing characteristics (continued) t m1 main mode mclk high time 900 ns t m2 main mode mclk low time 900 ns t m3 main mode mclk period 1800 ns t m4 main mode 900 ns mclk to md out valid (eeprom read time) note 1: limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions. note 2: if ml6510-130 is used in a master-slave mode, the maximum operating frequency is 120mhz. ml6510 configured with bit cm = 0: ttl input clock load [0-7] 1st order match load [0-7] with no 1st order match t skewf t skewb t skewio t skewr pecl input clocks or or clk inh clk inl v icm avcc ?0.4v 2.0 v note: all skew is measured at the device load input pin, not at the ml6510 clock output pin. skew is always a positive number, r egardless of which edge is leading and which is trailing.
7 ml6510 load[0-7] load[8-15] t pp1 or t pp2 t skewr (or t skewb ) t skewr (or t skewb ) rclkh rclkl ml6510 clk inh clk inl ml6510 slave chip (cm=1, cs=1) distance <2" load[0-7] load[8-15] ? ? ? y ? ? ? t ? ? ? y ? ? ? t pcb trace impedance z 0 = 50 w lumped c l 20pf fbx clkx ml6510-130 first-order matched loads ml6510-130 generic load r2 one way trip delay < t range /2 pcb trace impedance z 0 = 50 w lumped c lx 20pf fbx clkx load load r2 r3 length l x pcb trace impedance z 0 = 50 w lumped c ly 20pf fby clky load r2 r3 one way trip delay < t range /2 length l y |c lx ?c ly | < 5pf |l x ?l y | < 4" z ox = z oy r3 pcb trace impedance z 0 = 50 w lumped c l 20pf fbx clkx ml6510-80 first-order matched loads ml6510-80 generic load r1 one way trip delay < t range /2 pcb trace impedance z 0 = 50 w lumped c lx 20pf fbx clkx load load r1 length l x pcb trace impedance z 0 = 50 w lumped c ly 20pf fby clky load r1 one way trip delay < t range /2 length l y |c lx ?c ly | < 5pf |l x ?l y | < 4" z ox = z oy ac/skew characteristics load conditions
8 ml6510 functional description micro linears ml6510 is the first clock chip to use a feedback mechanism to adaptively (on a real time basis), eliminate clock skew in high speed personal computer and workstation system designs. figure 1 shows a basic configuration of the ml6510 in a system. the skew problem results due to the delaying of clock signals in the system, as shown in figure 2. clock skew results from variation in factors like trace length, pcb trace characteristics, load capacitance, parasitic capacitance, temperature and supply variations, etc. figure 2 shows a representation of the clock skew problem from a timing perspective. it shows a worst case example where the clock signal is delayed so much that its rising edge completely misses the data it is intended to strobe. using a clock deskew mechanism, this problem can be eliminated and the strobe with the appropriate setup and hold times with respect to the data bus can be generated. the ml6510 has eight deskew buffers, each with its own independent the reflection and error correction circuit. the deskew buffer eliminates skew by using the reflection from a remote chip to measure the clock error and then corrects it by generating the appropriate skew to the clock output to compensate. eight individually deskewed copies of the clock are provided by the ml6510. the deskew buffers compensate internally for board-level skew caused by the pcb trace length variations and device load variations. this is accomplished by sensing the round trip delay via a reflected signal, and then delaying or advancing the clock edge so that all 8 output clocks arrive at their loads in phase. each of the eight clock lines can have any length pcb trace (up to 5ns each way or 1/4th of the output clock period, whichever is smaller) and the device loads can vary from line to line. the ml6510 will automatically compensate for these variations, keeping the device load clocks in phase. although ml6510 will compensate for skew caused by loading, excessive capacitive loading can cause rise/fall time degradation at the load. cascading one ml6510 to another ml6510 should be done using the pecl reference clock outputs, to minimize part-to-part skew. clock regeneration the programmable adaptive clock deskew can function in a clock regeneration mode to assist in building clock trees or to expand the number of deskewed clock lines. in this mode, it has the ability to do clock multiplication or division as well, while maintaining low skew between write signal clock at remote chip data at remote chip write signal clock at remote chip data at remote chip data data t s t h figure 2. the skew problem. cpu micro linear ml6510 clock chip remote chip clock #0 feedback #0 clock #1 feedback #1 clock #7 feedback #7 data clock generator clock in figure 1. basic system configuration using the ml6510.
9 ml6510 phase detector ? (m + 1) [ ? 1 to 64] loop filter vco 80-160 mhz ? 2 r maximum delay 1 0 cm bit ? (n + 1) [ ? 1 to ? 128] clk inh clk inl cs bit ttl to ecl 1 0 sys_clk to deskew buffers ecl input buffer 1 0 test rclkh rclkl example: generating a 2x clock input frequency = 33 mhz set r = 01 (output range 40 C 80 mhz), n = 5 (0000101), m = 2 (000010), m/s = 0 ff n m mhz mhz vco ref r = + () + () ? ? = ? ? = 12 1 33 62 3 132 1 f out = f vco /2 r = 132 mhz/2 1 = 66 mhz example: generating a 1x clock input frequency = 66 mhz set r = 01 (output range 40C80 mhz), set m = 0 (000000), n = 0 (0000000), m/s = 0 f mhz mhz vco = ? ? = 66 12 1 132 1 f out = f vco /2 r = 132 mhz/2 1 = 66 mhz for doing frequency multiplication and division, keep m 3 2 and n 3 2 for the lowest skew between input clock and output clock. several configurations for doing frequency multiplication and division are included in the 8 configurations stored in the on-chip rom (see programming the ml6510). figure 3. ml6510 clock generation block diagram. input clock and output clocks. it can thus generate a 2x or 4x or 0.5x frequency multiplication or division from input to output (e.g. 33 mhz input, 66 mhz output or 66 mhz input, 33 mhz output, etc.). it also can generate a 1x frequency output. the vco frequency is defined by: ff n m vco ref r = + () + () ? ? 12 1 and the output frequency is still given by: f out = f vco /2 r r1 r0 input/output range 0 0 80-130 mhz 0 1 40C80 mhz 1 0 20C40 mhz 1 1 10C20 mhz note: r implies r1, r0; for -80 version, not valid: defaults to r = 01 the vco still must remain in the range 80C160 mhz, and the minimum phase detector input frequency is 625khz = (80 mhz/128). thus the product of (n + 1) and 2 r should be limited to 128: (n + 1) x 2 r 128 to make sure that the phase detector inputs remain above the minimum frequency.
10 ml6510 adaptive deskew buffers each copy of the clock is driven by an adaptive deskew buffer. the deskew buffer compensates for skew time automatically in accordance to the flight time delay it senses from the reflection on the transmission line. figure 4 shows the simplified functional block diagram of the deskew circuit. the phase of the sense signal and the driver signal is presented to a three-input phase comparator and compared with the reference signal. the phase comparator then controls the voltage controlled delay in the output drive line to match the delay of the fixed reference delay line. therefore, the sum of the delay of the driver circuit, pcb trace delay, rise time delay at the load and the adjustable delay will always equal the fixed maximum delay. the sense circuit has an internal level detect such that any skew caused by loading is also accounted for. since the delay of the circuit is matched for the entire loop, the phase of all the drivers are in close alignment at the inputs of the load. clock in fixed max delay phase detector sense drive voltage controlled delay load figure 4. deskew circuit block diagram. load conditions the ml6510 has been designed to drive the wide range of load conditions that are encountered in a high frequency system. the eight output clock loads can each vary within a range of trace length and lumped capacitive load, and the ml6510 will maintain the low skew characteristics specified in electrical characteristics. the clock skew can be further minimized by providing some first-order matching between any two loads that require particularly well- matched clocks. the ml6510-80 produces a 5v swing at the load and requires a single external termination resistor for each output. the ml6510-130 produces a 3v swing at the load and requires two external termination resistors for each output. the fb input pin is connected to the other side of the termination resistor r1 or r2, with a short connection. termination resistor valves should be chosen as follows: rz r z r z 121533 000 === . trace resistor impedance values z0 r1 r2 r3 40 w 40 60 120 50 w 50 75 150 63 w 63 95 189
11 ml6510 pcb trace impedance z 0 = 40 w to 65 w lumped c l 20pf fbx clkx ml6510-130 first-order matched loads ml6510-130 generic load r2 one way trip delay < t range /2 pcb trace impedance z 0 = 40 w to 65 w lumped c lx 20pf fbx clkx load load r2 r3 length l x pcb trace impedance z 0 = 40 w to 65 w lumped c ly 20pf fby clky load r2 r3 one way trip delay < t range /2 length l y |c lx ?c ly | < 5pf |l x ?l y | < 4" z ox = z oy r3 pcb trace impedance z 0 = 40 w to 65 w lumped c l 20pf fbx clkx ml6510-80 first-order matched loads ml6510-80 generic load r1 one way trip delay < t range /2 pcb trace impedance z 0 = 40 w to 65 w lumped c lx 20pf fbx clkx load load r1 length l x pcb trace impedance z 0 = 40 w to 65 w lumped c ly 20pf fby clky load r1 one way trip delay < t range /2 length l y |c lx ?c ly | < 5pf |l x ?l y | < 4" z ox = z oy external input clocks the external input clock to the ml6510 can be either a differential pseudo-ecl clock or a single-ended ttl clock. this is selected using the cs bit in the serial shift register. for the single-ended ttl clock tie the clk inh and clk inl pins together. the ml6510 ensures that there is a well- defined phase difference between the input and output clocks. reset and lock when reset is de-asserted, the internal programming logic will become active, loading in the configuration bits (see programming the ml6510). once the configuration is loaded, the pll will lock onto the reference signal, and then the deskew blocks will adapt to the load conditions. when all eight output clocks are stable and deskewed, lock will be asserted. the asserted polarity of lock is high. thus, lock can be used to indicate that the system is ready, or it can be used to drive the reset input of another pacman in a clock tree. chip vcc reset lock t reset t lock t lock program in the configuration program in the configuration y t y t 0 5v reset may be reasserted at any time to reset the chip operations. following a reset assertion of valid pulse width (see programming electrical characteristics), the ml6510 must again be loaded with a configuration, then it will re-lock and reassert lock when all eight clock outputs are stable and deskewed.
12 ml6510 programming the ml6510 the configuration of the ml6510 is programmed by loading 18 (ml6510-80) or 19 (ml6510-130) bits into the configuration shift register. to load these bits, the user has 3 options: main, aux or rom modes. which mode is used is determined by the logic level on the md in pin when reset is deasserted. if md in is tied high, the ml6510 will assume aux mode; if its tied low, rom mode. if md in is high-impedance (i.e. tied to the input of an eeprom), it will assume main mode. 1. main mode in this mode, the ml6510 will read the configuration bits from an external serial eeprom, such as the 93c46, using the industry standard 3-wire serial i/o protocol. the serial eeprom should be a 1k organized in 64 x 16 bits and the pacman will read the configuration bits out of the two least significant 16-bit words. to use this mode, simply connect the eeprom serial data input pin to md in (ml6510 pin 19), the eeprom serial data output pin to md out (ml6510 pin 20), and the eeprom serial data clock pin to mclk (ml6510 pin 21) and cs pin for the eeprom should be tied to the reset signal. after power up, when reset is deasserted, the ml6510 will automatically generate the address and clock to read out the configuration bits. refer main mode waveform in figure 5. 1k serial eeprom (64 x 16 bit) ml6510 clock opcodes address data clk data in data out mclk md in md out reset rommsb reset cs main mode configuration. 2. aux mode when md in is tied to vcc, programming the ml6510 will occur via the aux mode. this mode shifts the configuration bits into the shift register directly from the md out pin. the first 18 (ml6510-80) or 19 (ml6510- 130) clock rising edges provided externally on the mclk pin after reset is deasserted will be used to load the shift register data, which should be provided on the md out pin. see figure 6. m processor ml6510 clock vcc data mclk md in md out rommsb aux mode configuration. 3. rom mode when md in is tied to gnd, programming the ml6510 will occur via the rom mode. this mode reads the configuration bits directly from an on chip rom. the selection of one of the eight preset configuration codes is accomplished by means of the pins rommsb, mclk and md out as shown in tables 1 and 2. the test mode configur ation (code 7) is enabled when the test bit is set. in this mode the pll is bypassed for low frequency testing. codes 0-2 are used when the ml6510 clock inputs are driven from another pacmans reference clock outputs. code 3 is used when zero phase error is desired between input and load clocks. rom address bits ml6510 mclk md out md in rommsb rom 8 x 19 bit to shift register serial data in ? ? y ? ? t rom mode configuration. 01 02 03 04 05 06 07 08 09 10 11 12 ?? 25 mclk (driven by ml6510) sb 1 op1 1 md in (driven by ml6510) op0 0 md out (driven by eeprom) ?? d15 d14 d0 a5 0 a4 0 a3 0 a2 0 a1 0 a0 0 t m4 t m1 t m2 t m3 26 27 13 d13 d15 d14 ? ? y ? ? t 2 bits at address 1 ? ? ? ? ? ? y ? ? ? ? ? ? ? t 16 bits data at adddress 0 (28) (d13) (3 bits for ml6510-130) figure 5. main mode waveforms.
13 ml6510 table 2: ml6510-130 rom codes selection bits input output configuration code freq freq code description rommsb mclk md out (mhz) (mhz) cs cm r1, r0 m n ddsk test 0 pecl input clock, 1x mode 0 0 0 80-130 80-130 1 1 00 0 0 0 0 1 pecl input clock, 0.5x mode 0 0 1 80-160 40-80 1 1 01 5 2 0 0 2 pecl input clock, 2x mode 0 1 0 40-65 80-130 1 1 00 2 5 0 0 3 pecl input clock, 1x mode 0 1 1 80-130 80-130 1 0 00 0 0 0 0 4 ttl input clock, 1x mode 1 0 0 80-130 80-130 0 0 00 0 0 0 0 5 ttl input clock, 0.5x mode 1 0 1 80-130 40-65 0 0 01 5 2 0 0 6 ttl input clock, 2x mode 1 1 0 40-65 80-130 0 0 00 2 5 0 0 7 test mode, ttl input clock 1 1 1 0-50 0-50 0 1 table 1: ml6510-80 rom codes selection bits input output configuration code freq freq code description rommsb mclk md out (mhz) (mhz) cs cm r1, r0 m n test 0 pecl input clock, 1x mode 0 0 0 40-80 40-80 1 1 01 0 0 0 1 pecl input clock, 0.5x mode 0 0 1 40-80 20-40 1 1 10 5 2 0 2 pecl input clock, 2x mode 0 1 0 20-40 40-80 1 1 01 2 5 0 3 pecl input clock, 1x mode 0 1 1 40-80 40-80 1 0 01 0 0 0 4 ttl input clock, 1x mode 1 0 0 40-80 40-80 0 0 01 0 0 0 5 ttl input clock, 0.5x mode 1 0 1 40-80 20-40 0 0 10 5 2 0 6 ttl input clock, 2x mode 1 1 0 20-40 40-80 0 0 01 2 5 0 7 test mode, ttl input clock 1 1 1 0-50 0-50 0 1 figure 6. aux mode waveform. mclk (input to ml6510) md out (input to ml6510) t a1 t a2 t a5 18 02 01 m5 n0 t a3 t a4 m4
14 ml6510 register definitions register size function n 7 bit this register is used to define the ratio for the desired frequency of the primary clock. r 2 bit this register defines the frequency of the primary clocks, clk [0-7]. cm 1 bit set cm = 1 when the pecl input reference clock is from another 6510 reference clock output. set cm = 0 if the clock reference is ttl or pecl from an external source and minimum phase error between input and output is desired. cs 1 bit cs = 0 selects ttl input clock, cs = 1 selects pecl input clock. test 1 bit when set to 1, the pll is bypassed for low frequency testing. m 6 bit this register is used to define the ratio for the desired frequency of the primary clock. ddsk 1 bit when ddsk is set to 1, deskew is disabled. the chip will provide low skew clocks at the chip output pins, but trace length variations will not be compensated. when ddsk is set to 0, normal deskew will provide low skew clocks at the loads. this bit is only for ml6510-130. ml6510-80 shift register chain n1 n2 n3 n4 n5 n6 msb r0 lsb r1 msb cs m0 lsb test m1 m2 m3 m4 m5 msb n0 lsb serial data in (from eeprom, or m processor, or internal rom) cm ml6510-130 shift register chain n1 n2 n3 n4 n5 n6 msb r0 lsb r1 msb cs m0 lsb test m1 m2 m3 m4 m5 msb n0 lsb serial data in (from eeprom, or m processor, or internal rom) cm ddsk
15 ml6510 applications zero skew clock generation the most advantageous feature of using pacman is its ability to deliver multiple copies of the clock to the load with very low skew. because of its unique ability in deskewing, trace length and load consideration are no longer critical in board design. because of the unique deskewing scheme, neither the trace length nor the device loads need to be equal. this is true for loads, <20pf. higher loads can be driven if they are placed close to the clock chip, to guarantee signal integrity. clock driver t o ? s 2 t o ? s 3 t o ? s 1 t s 1 t s 2 t s 3 t s 0t s 0t s 0 one device load two device load three device load low skew clock distribution clock distribution design is usually not a trivial task, especially when multiple clock chips are needed. by using closely grouped pacmans, 16 or more clock lines can be created with low part-to-part skew. additional groups of clocks can be clustered and driven from deskewed clock lines, to minimize the number of long- distance clock lines. clk2 clk0 clk1 ml6510 ml6510 clk0 clk1 clk2 clk2 clk0 clk1 ml6510 clk3 ?? ?? ? to remote group of clustered loads board to board synchronization distribution of the synchronous clock could present significant difficulty at high frequency. with the system clock generated by the ml6510, a zero skew clock delivery to a backplane is now possible. by using the ml6510 slave chip or the ml6510 in slave mode at the receiver end, a near zero delay clock link can be accomplished between the mother board and the satellite boards. because the pacman has frequency doubling capability, a lower frequency signal can be used to route across a back plane. ml6510 ml6510 (slave mode) example configuration shown in figure 7 is an example configuration using two ml6510-80 chips in tandem to generate eight 66 mhz clocks and eight 33mhz low-skew clocks from a 66mhz input reference. this requires only the termination resistors. configurations are loaded from the internal rom. pcb traces 0 to 15 are each 50 w impedance and the load capacitances c l0 -c l15 are 0 to 20pf each. no trace length matching is required among separate clock outputs. all traces are shown with a series termination at the output. if ml6510-130s are used in a master slave mode the maximum operating frequency will be 120mhz. load[0-7] load[8-15] 33 mhz t skewr (or t skewb ) t pp2 t skewr (or t skewb )
16 ml6510 figure 7. example use of two ml6510-80 to generate multiple frequency clocks. first ml6510-80 generates eight 66mhz clocks while second ml6510-80 takes 66mhz small-swing reference from the first chip and generates eight 33mhz clocks. load0 c l0 66 mhz clk0 fb0 clk1 fb1 clk7 fb7 system reset low reset rommsb mclk md in md out vcc ml6510-80 ttl 1x mode clk inh clk inl 66mhz ttl reference lock rclkh rclkl reset rommsb mclk md in md out lock all_clock_ready ml6510-80 pecl 0.5x mode clk0 fb0 clk1 fb1 clk7 fb7 clk inh clk inl vcc 50 load1 c l1 66 mhz pcb trace 1 50 load7 c l7 66 mhz 50 load8 c l8 33 mhz 50 load9 c l9 33 mhz pcb trace 9 50 load15 33 mhz 50 c l15 66mhz pcb trace 15 pcb trace 8 pcb trace 7 pcb trace 0
18 ml6510 physical dimensions inches (millimeters) 0.100 - 0.112 (2.54 - 2.84) pin 1 id seating plane 0.685 - 0.695 (17.40 - 17.65) 0.650 - 0.656 (16.51 - 16.66) 0.013 - 0.021 (0.33 - 0.53) 0.165 - 0.180 (4.06 - 4.57) 1 0.650 - 0.656 (16.51 - 16.66) 0.685 - 0.695 (17.40 - 17.65) 12 23 34 0.590 - 0.630 (14.99 - 16.00) 0.025 - 0.045 (0.63 - 1.14) (radius) 0.050 bsc (1.27 bsc) 0.009 - 0.011 (0.23 - 0.28) 0.042 - 0.056 (1.07 - 1.42) 0.042 - 0.048 (1.07 - 1.22) 0.026 - 0.032 (0.66 - 0.81) 0.500 bsc (12.70 bsc) package: q44 44-pin plcc 0.148 - 0.156 (3.76 - 3.96)
1 8 ml6510 micro linear reserves the right to make changes to any product herein to improve reliability, function or design. micro linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. the circuits contained in this data sheet are offered as possible applications only. micro linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. the customer is urged to consult with appropriate legal counsel before deciding on a particular application. ds 65 10 -01 2092 concourse drive san jose, ca 95131 tel: 408/433-5200 fax: 408/432-0295 ordering information part number temperature range package ML6510CQ-80 0 c to 70 c 44-pin plcc (q44) ml6510cq-13 0 0 c to 7 0 c 44-pin plcc (q44) ( o bso le te ) ? micro linear 1997 is a registered trademark of micro linear corporation products described in this document may be covered by one or more of the following patents, u.s.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; japan: 2598946. other patents are pending.

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