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IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 1/ 25 features ? excellent matching and technical reliability thanks to system-on-chip design with integrated photodiodes ? gray code scanning (11 digital tracks pitched at 400 m) ? sine/cosine analog track with electronic calibration ? diff. sine/cosine outputs with 1024 cpr (amplitude: 500 mv) ? position value of up to 16 bits through 6-bit interpolation ? quadrature signals with 1024, 2048, 4096, 8192, 16384 cpr ? index signal in phase with b low ? 14-bit parallel position data output ? serial data readout in 1 s cycles at 16 mhz clock frequency ? spi interface for con?guration and position data output ? 3.3 v-compatible spi and i/o ports ? led current control for a constant receive power (50 ma highside driver, sin 2 +cos 2 or sum) ? permanent parity monitoring of the internal ram bits ? alarm for con?guration and illumination errors (end of life) ? temperature range from -40c to 110c ? small outline, 30-pin optobga package for smt ? illumination: ic-sn85 blcc sn1c (850 nm encoder led) ? code discs: lng1s 42-1024 (1024 ppr, ? 42 mm/18 mm), lng2s 25-512 (512 ppr, ? 24.8 mm/2 mm) applications ? optical position sensors ? linear scales ? absolute, incremental, and parallel encoders ? motor feedback systems packages 30-pin optobga 7.6 mm x 7.1 mm x 1.7 mm block diagram copyright ? 2011 ic-haus http://www.ichaus.com p r e l i m i n a r y p r e l i m i n a r y
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 2/ 25 description IC-LNG is an optoelectronic encoder ic for absolute linear and angle measuring systems, such as glass scales and encoders. photodiodes, ampli?ers, and comparators, the entire signal conditioning unit, and interfaces for position data output have been mono- lithically integrated into the device. an integrated led current control with a driver stage allows a transmitting led to be directly connected (e.g. ic-sn85). the optical receive power is kept constant by the control unit, regardless of tempera- ture and aging effects. the receive power setpoint can be programmed. should the led current control exit its operating range, this is indicated at the error message output (end-of-life alarm at pin err). the photocurrent offset and photocurrent amplitude of the analog sine/cosine signals can be calibrated. these calibrated voltage signals are lead out to pins psin, nsin, pcos, and ncos and are used by the integrated 6-bit interpolator. IC-LNG synchronizes the interpolator and singleturn data to form a contiguous gray-coded position data word. a shift register or spi interface are available for position data output. IC-LNG also outputs incre- mental a/b/z signals, the resolution of which can be programmed. after startup IC-LNG is con?gured using the spi in- terface. to make connection to a 3.3 v microcon- troller easier, all digital i/o ports, including the spi, can be run on 3.3 v. test currents can be applied to test pins tps, tns, tpc, and tnc to simulate photocurrents. allocation to various tracks can be selected as required, en- abling a full function test of the ic with the exception of the sensors. p r e l i m i n a r y p r e l i m i n a r y
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 3/ 25 contents packages 4 absolute maximum ratings 6 thermal data 6 electrical characteristics 7 operating conditions: spi interface 10 operating conditions: shift register 11 configuration parameters 12 operating modes 14 spi interface 15 general protocol description . . . . . . . . . 15 activate . . . . . . . . . . . . . . . . . . . . 15 sensor data transmission . . . . . . . . . . . 16 sensor data status . . . . . . . . . . . . . . . 16 register status/data . . . . . . . . . . . . 17 read register (cont.) . . . . . . . . . . . . 17 write to register (cont.) . . . . . . . . . . 17 signal conditioning 19 synchronization 20 parallel encoder mode 20 shift register output 21 incremental output 22 led current control 23 error monitoring . . . . . . . . . . . . . . . . 23 alarm output 23 test functions 24 p r e l i m i n a r y p r e l i m i n a r y
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 4/ 25 packages pin configuration obga lnb2c (7.6 mm x 7.1 mm) pin functions no. name function a1 sck spi clock input a2 vdd + 3 v to +5.5 v i/o ports supply voltage a3 gnd i/o ports ground a4 led led current control (highside output) a5 vdda + 4 v to +5.5 v supply voltage a6 gnda ground b1 cs spi chip select b2 miso spi data output b3 mosi spi data input b4 pcos analog voltage output pcos b5 nsin analog voltage output nsin b6 psin analog voltage output psin pin functions no. name function c1 incz incremental output z / parallel output bit 11 c2 tns test input nsin / parallel output bit 12 c3 tnc test input ncos / parallel output bit 13 c4 tps test input psin / parallel output bit 1 c5 tpc test input pcos / parallel output bit 0 c6 ncos analog voltage output ncos d1 dout shift register data output / parallel output bit 8 d2 din shift register data input / parallel output bit 9 d3 nsl shift register load / parallel output bit 10 d4 incb incremental output b / parallel output bit 3 d5 inca incremental output a / parallel output bit 2 d6 err alarm message output, high active e1 n.c. e2 po6 parallel output bit 6 e3 clk shift register clock input / parallel output bit 7 e4 n.c. e5 po5 parallel output bit 5 e6 pok power ok indication / parallel output bit 4 n.c. pin not connected p r e l i m i n a r y p r e l i m i n a r y a b c d e 1 2 3 4 5 6
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 5/ 25 pad layout pad functions no. name function 1 gnd i/o ports ground 2 vdd + 3 v to +5.5 v i/o ports supply voltage 3 sck spi clock input 4 mosi spi data input 5 miso spi data output 6 cs spi chip select 7 tnc test input ncos / parallel output bit 13 8 tns test input nsin / parallel output bit 12 9 incz incremental output z / parallel output bit 11 10 nsl shift register load / parallel output bit 10 11 din shift register data input / parallel output bit 9 12 dout shift register data output / parallel output bit 8 13 clk shift register clock input / parallel output bit 7 14 po6 parallel output bit 6 15 po5 parallel output bit 5 16 pok power ok indication / parallel output bit 4 17 incb incremental output b / parallel output bit 3 18 inca incremental output a / parallel output bit 2 19 err alarm message output, high active 20 tps test input psin / parallel output bit 1 21 tpc test input pcos / parallel output bit 0 22 ncos analog voltage output ncos 23 pcos analog voltage output pcos 24 nsin analog voltage output nsin 25 psin analog voltage output psin 26 led led current control (highside output) 27 vdda + 4 v to +5.5 v supply voltage 28 gnda ground p r e l i m i n a r y p r e l i m i n a r y 2600 450 230 200 30 270 110 80 110 5480 80 320 75 55 da1 da2 da3 da4 da5 dpsin da6 dpcos dncos dnsin da7 da8 da10 da9 da11
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 6/ 25 absolute maximum ratings maximum ratings do not constitute permissible operating conditions; functionality is not guaranteed. exceeding the maximum ratings can damage the device. item symbol parameter conditions unit no. min. max. g001 vdda voltage at vdda -0.3 6 v g002 vdd voltage at vdd -0.3 vdda+0.3 v g003 v(gnd) voltage at gnd -0.3 0.3 v g004 v() voltage at led, pcos, ncos, psin, nsin, tpc, tnc, tps, tns -0.3 vdda+0.3 v g005 v() voltage at inca, incb, incz, err, clk, dout, din, nsl, cs, mosi, miso, sck, po6, po5, pok, tpc, tnc, tps, tns -0.3 vdd+0.3 v g006 i(vdda) current in vdda -100 100 ma g007 i(vdd) current in vdd -50 50 ma g008 i(gnd) current in gnd -20 20 ma g009 i(led) current in led -100 20 ma g010 i() current in inca, incb, incz, err, clk, dout, din, nsl, cs, mosi, miso, sck, po6, po5, pok -60 60 ma g011 i() current in pcos, ncos, psin, nsin, tpc, tnc, tps, tns -35 35 ma g012 vd() esd susceptibility at all pins hbm, 100 pf discharged through 1.5 k
2 kv g013 tj chip-temperature -40 125 c g014 ts storage temperature range see package speci?cation thermal data operating conditions: vdda = 4 v to 5.5 v, vdd = 3 v to 5.5 v item symbol parameter conditions unit no. min. typ. max. t01 ta operating ambient temperature range see package speci?cation all voltages are referenced to ground unless otherwise stated. all currents ?owing into the device pins are positive; all currents ?owing out of the device pins are negative. p r e l i m i n a r y p r e l i m i n a r y
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 7/ 25 electrical characteristics operating conditions: vdda = 4 v to 5.5 v, vdd = 3 v to 5.5 v, gnda = gnd, tj = -40c to 125c, unless otherwise speci?ed. item symbol parameter conditions unit no. min. typ. max. total device 001 vdda permissible supply voltage 4.0 5.0 5.5 v 002 vdd permissible i/o supply voltage vdd vdda 3.0 5.5 v 003 vdda, vdd permissible residual ripple at 150 khz 10 mv 004 i() supply current in vdda and vdd (total sum) without currents i(led) and i(err), tj = 27c 15 40 ma 005 vcz()hi clamp voltage hi at vdd, gnd, vdda, gnda, miso, dout, inca, incb, incz, po5, po6, pok, tns, tps, tnc, tpc, ncos, nsin, pcos, psin, err, led i() = 4 ma 11 v 006 vc()hi clamp voltage hi at clk, din, nsl, inca, incb, incz, err, miso, dout, pok, p05, p06, tps, tns, tpc, tnc vc()hi = v() v(vdd), i() = 4 ma 0.3 1.2 v 007 vc()hi clamp voltage hi at cs, mosi, sck vc()hi = v() v(vdd), i() = 4 ma 1.2 2.2 v 008 vc()lo clamp voltage lo at all pins i() = -4 ma -1.2 -0.3 v 009 vs()hi saturation voltage hi at po6, po5, pok, clk, dout, din, nsl, miso, tpc, tnc, tps, tns vs()hi = vdd - v() 400 mv vdd = 3 to 4 v, i() = 2.5 ma vdd = 4 to 5.5 v, i() = 3.5 ma 010 isc()hi short-circuit current hi at po6, po5, pok, clk, dout, din, nsl, miso, tpc, tnc, tps, tns -100 -4 ma 011 vs()lo saturation voltage lo at po6, po5, pok, clk, dout, din, nsl, miso, tpc, tnc, tps, tns vdd = 3 to 4 v, l() = 2.5 ma 400 mv vdd = 4 to 5.5 v, l() = 3.5 ma 012 isc()lo short-circuit current lo at po6, po5, pok, clk, dout, din, nsl, miso, tpc, tnc, tps, tns 4 100 ma photodiodes 101 se( ) spectral application range se( ) = 0.1 x s( )max 400 1000 nm 102 s( )max spectral sensitivity = 690 nm 0.45 a/w 103 asc() radiant sensitive area dpsin, dnsin, dpcos, dncos 0.45 x 0.2 mm2 0.09 mm2 104 ad() radiant sensitive area digital da1 to da11 0.2 x 0.32 mm2 0.064 mm2 photocurrent ampli?er 201 iph() permissible photocurrent range 0 200 na 202 z() equivalent transimpedance gain z() = vout() / iph() 1.8 3.0 4.2 m
203 z()pn transimpedance gain matching of an ampli?er pair p-channel versus corresponding n-channel -0.2 0.2 % 204 fhc() upper cut-off frequency (-3db) without led current control 120 300 500 khz 205 vr() ratio reference voltage digital tracks (vcomp) to sum of analog tracks vr () = vcomp vpsi + vnsi + vpci + vnci 0.25 206 vhys() digital tracks hysteresis 15 25 40 mv 207 gr() coarse gain range gr = 0x00 1 gr = 0x01 1.33 gr = 0x02 1.6 gr = 0x03 2 p r e l i m i n a r y p r e l i m i n a r y
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 8/ 25 electrical characteristics operating conditions: vdda = 4 v to 5.5 v, vdd = 3 v to 5.5 v, gnda = gnd, tj = -40c to 125c, unless otherwise speci?ed. item symbol parameter conditions unit no. min. typ. max. 208 vref reference voltage of photocur- rent ampli?ers 0.6 0.8 1 v 209 vd()sc analog track dark signal voltage versus vref vd()sc = v() - vref -20 20 mv 210 vd()dig digital track dark signal voltage versus vref vd()dig = v() - vref -35 35 mv signal conditioning 301 gsmin, gcmin adjustable gain min gs, gc = 0x00 1 302 gsmax, gcmax adjustable gain max gs, gc = 0x3f 2 303 gdiff differential gain calibration accuracy 6 bit calibration -0.5 0.5 lsb 304 omin offset calibration min osp, osn, ocp, ocn = 0x00 43 45 47 %vdda 305 omax offset calibration max osp, osn, ocp, ocn = 0x7f 53 55 57 %vdda 306 odiff differential offset calibration accuracy 7 bit calibration 0.02 0.08 0.12 %vdda analog voltage outputs psin, nsin, pcos, ncos 401 vdc() dc output voltage offset adjusted to vddah 47 50 53 %vdda 402 vpk() permissible signal amplitude dc level = vdda/2 0.5 0.6 v 403 i()mx permissible output current -1 1 ma 404 ri() output impedance i() = -1 to 1 ma 75 200
led current control, error message err 501 imx() permissible led current -100 0 ma 502 iop() led current control range errs (internal) = 0, v(led) > vs(led) -50 -1 ma 503 vs() saturation voltage at led vs() = v(vdda) - v(led), tj = -40c to 100c, i() = -50 ma 1 v tj = 100c to 125c, i() = -45 ma 1 v 504 tr() current rise time led at led i(led): 0 % ! 90 % 0.8 1.5 ms 505 tset() current settling time of control loop at led amplitude at psin, nsin, pcos and ncos from 50 % to 100 % of setpoint 300 s 506 vs()hi saturation voltage hi at err vs()hi = vdd - v(err) 400 mv vdd = 3 v to 4 v, i() = 2.5 ma vdd = 4 v to 5.5 v, i() = 3.5 ma 507 isc()hi short-circuit current hi in err -100 -4 ma 508 vs()lo saturation voltage lo at err vdd = 3 v to 4 v, l() = 2.5 ma 400 mv vdd = 4 v to 5.5 v, l() = 3.5 ma 509 isc()lo short-circuit current lo in err 4 100 ma interpolator 701 aaabs absolute angle accuracy referenced to one sin/cos period -5 5 deg 702 aarel relative angle accuracy referenced to one ab period, see figure 1 -10 10 % 703 aahys angle hysteresis referenced to one sin/cos period 1 7 deg 704 tw()hi duty cycle referenced to ab period t, see figure 1 50 % 705 t ab phase a versus b see figure 1 25 % incremental outputs inca, incb, incz 801 vs()hi saturation voltage hi vs()hi = vdd - v() 400 mv vdd = 3 v to 4 v, i() = 2.5 ma vdd = 4 v to 5.5 v, i() = 3.5 ma 802 isc()hi short-circuit current hi -100 -4 ma 803 vs()lo saturation voltage lo vdd = 3 v to 4 v, l() = 2.5 ma 400 mv vdd = 4 v to 5.5 v, l() = 3.5 ma 804 isc()lo short-circuit current lo 4 100 ma 805 tr() rise time cl = 30 pf, v(): 10% ! 90% vdd 30 ns 806 tf() fall time cl = 30 pf, v(): 90% ! 10% vdd 30 ns p r e l i m i n a r y p r e l i m i n a r y
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 9/ 25 electrical characteristics operating conditions: vdda = 4 v to 5.5 v, vdd = 3 v to 5.5 v, gnda = gnd, tj = -40c to 125c, unless otherwise speci?ed. item symbol parameter conditions unit no. min. typ. max. spi interface sck, cs, miso, mosi 901 ?n() permissible input frequency at sck 10 mhz 902 vt()hi threshold voltage hi at sck, cs, mosi 2 v 903 vt()lo threshold voltage lo at sck, cs, mosi 0.8 v 904 vt()hys hysteresis at sck, cs, mosi vt() = vt()hi - vt()lo 40 100 mv 905 ipu() pull-up current at sck, mosi v() = 0 v to vdd - 1 v vdd = 3 v to 4 v -65 -25 -5 a vdd = 4 v to 5.5 v -120 -60 -10 a 906 vpu() pull-up voltage at sck, mosi vpu() = vdd - v(), 400 mv vdd = 3 v to 4 v, i() = -3 a vdd = 4 v to 5.5 v, i() = -5 a 907 ipd() pull-down current at cs v() = 1 v . . . vdd vdd = 3 v to 4 v 5 25 80 a vdd = 4 v to 5.5 v 8 60 150 a 908 vpd() pull-down voltage at cs vdd = 3 v to 4 v, i() = 3 a 400 mv vdd = 4 v to 5.5 v, i() = 5 a 909 t co propagation delay: miso hi after falling edge cs see figure 2 30 ns 910 t so propagation delay: miso stable after clock edge sck see figure 2 30 ns shift register clk, nsl, dout, din a01 ?n() permissible input frequency at clk 16 mhz a02 t no propagation delay: dout after falling edge nsl see figure 3 20 ns a03 t co propagation delay: dout stable after clock edge clk see figure 3 20 ns a04 vt()hi threshold voltage hi at clk, nsl, din 2 v a05 vt()lo threshold voltage lo at clk, nsl, din 0.8 v a06 vt()hys hysteresis at clk, nsl, din vt() = vt()hi - vt()lo 40 100 mv a07 ipu() pull-up-current at clk, nsl v() = 0 v to vdd - 1 v vdd = 3 v to 4 v -65 -25 -5 a vdd = 4 v to 5.5 v -120 -60 -10 a a08 vpu() pull-up-voltage at clk, nsl vpu() = vdd-v(), 400 mv vdd = 3 v to 4 v, i() = -3 a vdd = 4 v to 5.5 v, i() = -5 a a09 ipd() pull-down current at din v() = 1 v to vdd vdd = 3 v to 4 v 5 25 80 a vdd = 4 v 5.5 v 8 60 150 a a10 vpd() pull-down-voltage at din vdd = 3 v to 4 v, i() = 3 a 400 mv vdd = 4 v to 5.5 v, i() = 5 a parallel output bit 0 to bit 13 (parameter epg = 0x1) b01 vs()hi saturation voltage hi vs()hi = vdd - v() 400 mv vdd = 3 v to 4 v, i() = 2.5 ma, vdd = 4 v to 5.5 v, i() = 3.5 ma b02 isc()hi short-circuit current hi -100 -4 ma b03 vs()lo saturation voltage lo vdd = 3 v to 4 v, i() = 2.5 ma, 400 mv vdd = 4 v to 5.5 v, i() = 3.5 ma b04 isc()lo short-circuit current lo 4 100 ma b05 tr() rise time cl = 30 pf, v(): 10% ! 90% vdd 30 ns b06 tf() fall time cl = 30 pf, v(): 90% ! 10% vdd 30 ns p r e l i m i n a r y p r e l i m i n a r y
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 10/ 25 electrical characteristics operating conditions: vdda = 4 v to 5.5 v, vdd = 3 v to 5.5 v, gnda = gnd, tj = -40c to 125c, unless otherwise speci?ed. item symbol parameter conditions unit no. min. typ. max. power-on-reset pok c01 vddaon turn-on threshold vdda, power-on-reset vdda increasing, pok: lo ! hi 3.6 3.8 4.0 v c02 vddaoff turn-off threshold vdda, power-down-reset vdda decreasing, pok: hi ! lo 3.3 3.5 3.7 v c03 vddahys hysteresis vdda vddahys = vddaon - vddaoff 0.2 0.3 v figure 1: de?nition of the relative angle accuracy operating conditions: spi interface operating conditions: vdda = 4 v to 5.5 v, vdd = 3 v to 5.5 v, gnda = gnd, tj = -40c to 125c, unless otherwise speci?ed. item symbol parameter conditions unit no. min. max. i001 t sck permissible clock period 1/?n(sck) i002 t cs setup time: cs hi before sck hi ! lo 50 ns i003 t co propagation delay: miso hi after cs hi ! lo (elec. char. no. 909) i004 t is setup time: mosi stable before sck lo ! hi 50 ns i005 t si hold time: mosi stable after sck lo ! hi 50 ns i006 t so propagation delay: mosi stable after clock edge sck (elec. char. no. 910) i007 t cc hold time: between cs hi ! lo and cs lo ! hi 500 ns figure 2: spi interface timing p r e l i m i n a r y p r e l i m i n a r y aarel aarel t t whi t ab sck cs mosi miso t cc t cs t co t is t si t so t sck
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 11/ 25 operating conditions: shift register operating conditions: vdda = 4 v to 5.5 v, vdd = 3 v to 5.5 v, gnda = gnd, tj = -40c to 125c, unless otherwise speci?ed. item symbol parameter conditions unit no. min. max. i101 t clk permissible clock period 1/?n(clk) i102 t nc setup time: nsl lo before clk lo ! hi 30 ns i103 t no propagation delay: dout stable after nsl hi ! lo (elec. char. no. a02) i104 t co propagation delay: dout stable after clock edge clk (elec. char. no. a03) i105 t ic setup time: din stable before clk lo ! hi 30 ns i106 t ci hold time: din stable after clk lo ! hi 30 ns i107 t nn wait time: between nsl lo ! hi and nsl hi ! lo 60 ns figure 3: shift register timing p r e l i m i n a r y p r e l i m i n a r y clk nsl dout din t nn t nc t ic t ci t no t co t clk t no
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 12/ 25 configuration parameters operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . page 14 epg: operating mode selection spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 15 opcode: instructions ractive: activate register communication pactive: activate sensor data communication svalid: sensor data valid status: spi status information signal conditioning . . . . . . . . . . . . . . . . . . . . . . . . page 19 gr: gain range (all tracks) gs: sin gain osp: psin offset osn: nsin offset gc: cos gain ocp: pcos offset ocn: ncos offset synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . page 20 nsync: synchronization parallel encoder mode . . . . . . . . . . . . . . . . . . . . . page 20 epg: operating mode selection shift register output . . . . . . . . . . . . . . . . . . . . . . . page 21 src: shift register length sta: sin/cos resolution dir: code inversion incremental output . . . . . . . . . . . . . . . . . . . . . . . . page 22 inc: incremental output led current control . . . . . . . . . . . . . . . . . . . . . . . .page 23 lcset: control mode and setpoint internal error signals . . . . . . . . . . . . . . . . . . . . . . page 23 errs: led control range error errp: parity error test functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 24 ta: test modes tmux: multiplexer test signal register map adr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 signal conditioning 0x00 p0 C gs(5:0) 0x01 p1 C gc(5:0) 0x02 p2 osp(6:0) 0x03 p3 osn(6:0) 0x04 p4 ocp(6:0) 0x05 p5 ocn(6:0) led current control 0x06 p6 lcset(6:0) output 0x07 p7 nsync dir epg C gr(1:0) 0x08 p8 inc(2:0) sta src(2:0) test functions 0x09 p9 C ta(1:0) tmux(3:0) 0x0a pa C 0x0b pb C 0x0c pc C 0x0d pd C 0x0e pe C 0x0f pf C bit 7: parity bit (supplemented to an even number of ones) table 6: register layout p r e l i m i n a r y p r e l i m i n a r y
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 13/ 25 the con?guration registers in the internal ram are constantly monitored by a parity check. bit 7 of each address is the parity bit (p0-pf) and is supplemented to an even number of ones. the unused bits are also monitored. a parity error is signaled at pin err (high active). addresses in IC-LNG range from addresses 0x00 to 0x0f. as only the lower nibble of the address byte is evaluated, with addresses that are greater than 0x0f the device then returns to address range 0x00-0x0f. after the system enable (power-on reset, pin pok lo ! hi) the registers are initialized as follows: address reset value 0x00 - 0x01 0xa0 0x02 - 0x05 0xc0 0x06 0xa0 0x07 0x81 0x08 0x96 0x09 - 0x0f 0x00 table 7: register reset values p r e l i m i n a r y p r e l i m i n a r y
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 14/ 25 operating modes IC-LNG has two operating modes. these are selected using register bit epg. epg add. 0x07, bit 4 0 interface mode 1 parallel encoder mode table 8: operating mode selection in interface mode a shift register is provided for sensor data readout and an incremental interface with an in- dex signal for the output of encoder quadrature signals at a con?gurable resolution. a power-on signal at pin pok indicates that the system is enabled (pok = hi). in parallel encoder mode the sensor data is output as a 14-bit, parallel data word in gray code. for this purpose all the relevant pins are recon?gured as out- puts. table 9 shows the pin functions for the respec- tive operating mode (see also parallel encoder mode on page 20 ). the spi interface for device con?guration can also be used for position data readout and is available in both operating modes. pin dependent on pin vdd vdda interface mode parallel encoder mode gnd x i/o pins ground i/o pins ground vdd x +3 v to + 5.5 v i/o pins +3 v to + 5.5 v i/o pins supply voltage supply voltage sck x spi clock spi clock mosi x spi data input spi data input miso x spi data output spi data output cs x spi chip select spi chip select tnc x test input ncos parallel output 13 tns x test input nsin parallel output 12 incz x incremental output z parallel output 11 nsl x load shift register parallel output 10 din x shift register data input parallel output 9 dout x shift register data output parallel output 8 clk x shift register clock parallel output 7 nsl x load shift register parallel output 6 po5 x parallel output 5 parallel output 5 pok x power ok indication parallel output 4 incb x incremental output b parallel output 3 inca x incremental output a parallel output 2 err x alarm message output alarm message output tps x test input psin parallel output 1 tpc x test input pcos parallel output 0 ncos x voltage output ncos voltage output ncos pcos x voltage output pcos voltage output pcos nsin x voltage output nsin voltage output nsin psin x voltage output psin voltage output psin led x led current control (highside output) led current control (highside output) vdda x +4 v to + 5.5 v supply voltage +4 v to + 5.5 v supply voltage gnda x ground ground table 9: pin functions depending on operating mode p r e l i m i n a r y p r e l i m i n a r y
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 15/ 25 spi interface figure 4: spi transmission, taking the read register opcode as an example (cont.) general protocol description IC-LNGs spi interface is implemented as an spi slave and supports spi modes 0 and 3, meaning the idle time at sck can be 0 or 1. data is always accepted on a rising edge at sck. the idle time of the miso line is 1; on a rising edge at cs the mosi signal is switched through to the miso signal. data is sent byte by byte with the msb (most signif- icant bit) ?rst. each data transmission starts when a 1-byte opcode is sent by the spi master (table 10 ). opcode code description 0xb0 activate 0xa6 sensor data transmission 0xf5 sensor data status 0x8a read register (cont.) 0xcf write to register (cont.) 0xad register status/data table 10: instructions / opcodes spi data transmission for register readout takes place as follows (figure 4 ): 1. the master initializes a transmission by a rising edge at cs. 2. IC-LNG transfers the level from mosi to miso. 3. the master transmits the opcode and address adr through mosi; IC-LNG immediately outputs opcode and adr through miso. 4. IC-LNG transmits the data requested according to the address. 5. the master ends the command by a falling edge at cs. 6. IC-LNG switches its miso output to 1. opcode description activate IC-LNGs register and sensor data channels can be switched on and off using the activate command. the command causes all slaves to zero their rac- tive and pactive register and to loop-in this register data between the mosi and miso data stream. the register and sensor or actuator data channels can be switched on and off using the following data bytes. after a power-on IC-LNGs sensor data channel is de- activated (pactive = 0) and the register communica- tion is activated (ractive = 1). figure 5: setting activate: ractive/pactive (several slaves) bytes fail, valid, busy, and dismiss in the sta- tus byte are reset by the activate command (ta- ble 14 ). ractive code description 0 register communication deactivated 1 register communication activated table 11: register communication if ractive is not set, on commands read regis- ter (cont.), write to register (cont.) and reg- ister status/data the error bit is set in the spi interface status byte (table 14 ), indicating that the command has not been carried out. the slave imme- diately outputs the data at miso which has been sent by the master through mosi. p r e l i m i n a r y p r e l i m i n a r y sclk mosi miso cs op7 op6 op5 op4 op3 op2 op1 op0 op7 op6 op5 op4 op3 op2 op1 op0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 db7 db6 db5 db4 db3 db2 db1 db0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 rapa 0-4 8 cycles sclk mosi miso cs op op rapa 5-7 ...
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 16/ 25 pactive code description 0 sensor data channel deactivated 1 sensor data channel activated table 12: sensor data via spi if pactive is not set, on commands sensor data sta- tus or sensor data transmission the error bit is set in the status byte (table 14 ), indicating that the command has not been carried out. the slave imme- diately outputs the data at miso which has been sent by the master through mosi. if only one slave is connected up with one register and one sensor data channel, it must be ensured that the ractive and pactive bits are last in the data byte (figure 6 ). nb: if the slaves are connected in a chain (full duplex chain), with this command the master can determine the number of connected register and sensor data channels. to this end it can send a 1 after the opcode, which is repeated at miso after the number of register and sensor data channels (figure 6 ). figure 6: setting activate: ractive/pactive (one slave) sensor data transmission IC-LNG samples its position data on the ?rst rising edge at sclk if cs is switched to 1 (req). the sensor data shift register is looped-in between signals mosi and miso for spi communication and can then be clocked out. the size of the sensor data shift regis- ter must be set to 16 bits (cf. section on shift register output, page 21 ). if invalid data is sampled in the shift register, the er- ror bit is set in the status byte (table 14 ) and ze- roes are output as the data word. figure 7: sdad transmission: read sd with command sensor data transmission the master can not only read sensor data (sd) out from the slave; at the same time it can also transmit actuator data (ad) to the slave. IC-LNG ignores the transmitted actuator data. figure 8: sdad transmission: read sd, write ad sensor data status should the master not know the processing time, it can request sensor data using the command sensor data status . IC-LNG does not need any processing time; therefore, svalid is always valid. the command causes 1. all slaves activated with pactive to switch their svalid register between mosi and miso. 2. the next request for sensor data, triggered on the ?rst rising edge at sclk when cs has again been set to 1, is ignored by the slave. the end of conversion is signaled by svalid (sv). with this command the master can poll to the end of conversion. the sensor data is readout on the com- mand sensor data transmission . p r e l i m i n a r y p r e l i m i n a r y sclk mosi miso cs 1 0 ractive / pactive vector 0 0 0 0 ra pa op op 8 cycles 1 0 0 0 0 0 0 0 sd1 8 cycles sclk mosi miso cs op op sd2 ... req sd1 8 cycles sclk mosi miso cs op op sd2 ... ad1 ad2 ... req
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 17/ 25 svalid code description 0 sensor data invalid 1 sensor data valid table 13: svalid figure 9: sdad status if only one slave is connected, the relevant svalid bit is placed at bit position 7 in the svalid byte. figure 10: sdad status (one slave) register status/data the status of the last register communication or the last data transmission can be queried using the register status/data command. the status byte contains the information summarized in table 14 . status bit name description of the status report 7 error opcode invalid. sensor data was invalid on readout 6..4 - reserved 3 dismiss address refused 2 fail data request has failed 1 busy slave is busy with a request 0 valid data is valid nb display logic: 1 = true, 0 = false table 14: spi status information all status bits are updated with each register access. the error bit is the exception to the rule; this bit signals whether an error occurred during the last com- munication with the spi interface or not. the master transmits the opcode register sta- tus/data . IC-LNG immediately passes the opcode on to miso. IC-LNG then transmits the status byte and a data byte. the data byte is not available in IC-LNG and is thus not de?ned. figure 11: register status/data read register (cont.) the master transmits the opcode read register (cont.) . start address adr, from which point data is to be read, is transmitted in the 2nd byte. the slave immediately outputs the opcode and address and then transmits data1. the internal address counter is in- cremented after each data package. if an error occurs during register readout (cont.), i.e. the address is invalid, the requested data was not valid on data byte clocking, etc., the internal address counter is incremented no further and the fail error bit is set in the status byte (table 14 ). figure 12: read register (cont.) write to register (cont.) the master transmits the opcode write to register (cont.) . start address adr, from which point succes- sive data data1-datan is to be written, is transmitted in the 2nd byte. the slave immediately outputs the opcode, address, and data at miso. the slave incre- ments its internal address counter after each datan data package. p r e l i m i n a r y p r e l i m i n a r y sv 0-7 8 cycles sclk mosi miso cs op op sv 8-15 ... req sclk mosi miso cs 0 0 svalid vector 0 0 0 0 0 0 op op 8 cycles 0 0 0 0 0 0 sv 0 0 req status 8 cycles sclk mosi miso cs op op data adr 8 cycles sclk mosi miso cs op op data1 ... data2 adr
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 18/ 25 if an error occurs during a write to register (cont.), i.e. the address is invalid, writing of the last address data has not ?nished, etc., the internal address counter is incremented no further and the fail error bit is set in the status byte (table 14 ). figure 13: write to register (cont.) p r e l i m i n a r y p r e l i m i n a r y adr 8 cycles sclk mosi miso cs op op data1 data2 ... adr data1 data2 ...
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 19/ 25 signal conditioning IC-LNG has various parameters for signal conditioning. the gain of the digital tracks and the analog track can both be set using parameter gr. a gain factor of 1.33 (gr = 0x01) can be used for most applications. gr add. 0x07, bit 1:0 code gain factor 0x00 1.0 0x01 1.33 0x02 1.6 0x03 2.0 table 15: gain range (all tracks) the sine/cosine signals can be calibrated in ampli- tude and offset (figure 14 ). to this end the led current control must be programmed to sum con- trol (lcset(6) = 1) and the internal calibration signals switched to analog outputs psin, nsin, pcos, and ncos (ta = 0x1). figure 14: sine/cosine signal calibration to calibrate the sine signals tmux must be pro- grammed to 0x0d. the amplitude of signals psin and nsin can then be calibrated using parameter gs. the target amplitude is 500 mvp. gs add. 0x00, bit 5:0 code gain factor 0x00 1.0 0x01 1.01 ... 1+ gs 0.0053 1 gs 0.0053 0x3f 2.0 table 16: psin and nsin gain the offsets of psin and nsin can be calibrated sep- arately using parameters osp and osn. the offset of signal psin must be calibrated to reference signal vddah. this signal is available in test mode at pin ncos. the offset of signal nsin must then be cali- brated to the calibrated offset of signal psin. osp add. 0x02, bit 6:0 code offset value 0x00 0.45 vdda 0x01 0.4508 vdda ... (0.45 + osp 0.1 127 ) vdda 0x7f 0.55 vdda table 17: psin offset osn add. 0x03, bit 6:0 code offset value 0x00 0.45 vdda 0x01 0.4508 vdda ... (0.45 + osn 0.1 127 ) vdda 0x7f 0.55 vdda table 18: nsin offset to calibrate the cosine signals tmux must be pro- grammed to 0x0e. the amplitude of signals pcos and ncos can then be calibrated to the same amplitude as that of the sine signals using parameter gs. gc add. 0x01, bit 5:0 code gain factor 0x00 1.0 0x01 1.01 ... 1+ gc 0.0053 1 gc 0.0053 0x3f 2.0 table 19: pcos and ncos gain the offsets of pcos and ncos can be calibrated sep- arately using parameters ocp and ocn. the offset of signal pcos must be calibrated to reference signal vddah. this signal is available in test mode at pin ncos. the offset of signal ncos must then be cali- brated to the calibrated offset of signal pcos. ocp add. 0x04, bit 6:0 code offset value 0x00 0.45 vdda 0x01 0.4508 vdda ... (0.45 + ocp 0.1 127 ) vdda 0x7f 0.55 vdda table 20: pcos offset p r e l i m i n a r y p r e l i m i n a r y psin nsin pcos ncos gnda vpx vnx vddah vddah vnx vpx t a = 0x1 tmux = 0x0d or tmux = 0x0e (x = s, c)
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 20/ 25 ocn add. 0x05, bit 6:0 code offset value 0x00 0.45 vdda 0x01 0.4508 vdda ... (0.45 + ocn 0.1 127 ) vdda 0x7f 0.55 vdda table 21: ncos offset the signal path of the sin/cos tracks is shown in fig- ure 15 with the conditioning unit. figure 15: sin/cos signal path synchronization IC-LNG synchronizes the digital tracks to the interpo- lator. nsync can be used to deactivate synchronization to check the adjustment or for code discs not in gray code. the comparated signals of the digital tracks are then output. nsync add. 0x07, bit 6 0 synchronization activated 1 synchronization deactivated table 22: synchronization parallel encoder mode in parallel encoder mode an absolute position data word with a width of 14 bits is output in parallel. this position data word consists of the 11 bits of the digital tracks and of 3 bits interpolated from the analog track. the position data is output in gray code. parallel en- coder mode is activated by parameter epg (see also operating modes on page 14 ). epg add. 0x07, bit 4 0 interface mode 1 parallel encoder mode table 23: selecting the operating mode p r e l i m i n a r y p r e l i m i n a r y
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 21/ 25 shift register output in interface mode (epg = 0) IC-LNG provides a shift register for the readout of position data. in order to be able to use this shift register the spi interface sen- sor data channel must be deactivated by command activate with pactive = 0 (table 12 ). after a power-on the shift register in IC-LNG is active. the position data is output in gray code with the msb ?rst. this msb is output in real time at the shift reg- ister output (pin dout) when nsl = 1. when nsl = 0 the position data is stored in the shift register and can then be output serially with rising edge clk. the position data readout process is shown in figure 16 . external data can be read into IC-LNG through shift register input pin din. this is output after the position data. for example, IC-LNGs pin err can be con- nected to pin din to link the alarm output to the po- sition data. the length of the shift register and the number of data bits used can be selected using parameter src, de- pending on the set sin/cos resolution. sta add. 0x08, bit 3 0 1024 sin/cos cycles 1 512 sin/cos cycles table 24: sin/cos resolution src add. 0x08, bit 2:0 code shift register length data bits for sta = 0 data bits for sta = 1 0x0 16 bits 16 15 0x1 16 bits 16 15 0x2 16 bits 15 14 0x3 16 bits 14 13 0x4 16 bits 13 12 0x5 16 bits 12 11 0x6 14 bits 13 12 0x7 14 bits 12 11 table 25: shift register length the msb of the position data can be inverted by pa- rameter dir (code inversion). dir add. 0x07, bit 5 0 no code inversion 1 code inversion table 26: code inversion figure 16: shift register output (epg = 0) p r e l i m i n a r y p r e l i m i n a r y clk nsl dout msb msb-1 msb-2 lsb din
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 22/ 25 incremental output at pins inca and incb either incremental signals with interpolation factors of 1 to 16 or internal digital signals are output. selection is made using parameter inc. inc add. 0x08, bit 6:4 0x00 interpolation factor 1 0x01 interpolation factor 2 0x02 interpolation factor 4 0x03 interpolation factor 8 0x04 interpolation factor 16 0x05 digital test 0x06 ic-haus test 1 0x07 ic-haus test 2 table 27: incremental output at pin incz a zero pulse is output which is suitable for the selected interpolation factor. the zero pulse is symmetrical to the falling edge of the msb signal on the digital tracks and is half an incremental cycle long gated with b low. the phase relationship between the sin/cos signals and the incremental signals is shown in figure 17 . output in digital test and ic-haus test modes is de- scribed in the section on test functions on page 24 . figure 17: sin/cos and abz phase relationship p r e l i m i n a r y p r e l i m i n a r y inca incb msb (d11) incz incz inca incb inc=0x00 inc=0x01 msb (d11) psin pcos
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 23/ 25 led current control the optical receive power of the sine/cosine sensors is kept constant by the integrated led control unit, re- gardless of the temperature and ageing effects of the led. the type of control can be selected using param- eter lcset(6), the possible options being sum control or square control. so that the internal interpolator is always optimally controlled in all operating conditions, square control should be used. sum control should be used for signal conditioning. lcset(6) add. 0x06, bit 6 0 square control (sum of the amplitude squares) 1 sum control (dc control prop. to vr()) table 28: control mode the setpoint for the control can be con?gured using parameter lcset(5:0). lcset(5:0) add. 0x06, bit 5:0 code lcset(6) = 0 lcset(6) = 1 0x00 0.240 vp 0.140 v 0x01 0.243 vp 0.142 v ... 0.24 vp 1 i 0.0125 0.14 v 1 i 0.0125 0x3f 1.1 vp 0.640 v table 29: control setpoint error monitoring IC-LNGs led current control range is monitored. should the led current control exit its control range, internal error errs is set to 1. this error signal is or- gated with IC-LNGs errp alarm (parity check) and output at error output err (cf. section on the alarm output). alarm output IC-LNG has an alarm or error output to indicate exist- ing errors. if an error occurs, pin err is set to 1. IC-LNGs led current control range is monitored. should the led current control exit its control range, internal error errs is set to 1. if the parity check signals an error in the ram area, internal error errp is set to 1. figure 18: alarm output p r e l i m i n a r y p r e l i m i n a r y err gnd vdd 3 1 errs errp error message
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 24/ 25 test functions ta addr. 0x09; bit 5:4 code output at sin/cos 0x0 normal operation 0x1 test signals (cf. table 31 ) 0x2 ic-haus test 0x3 ic-haus test table 30: test modes tmux add. 0x09, bit 3:0 code psin nsin pcos ncos 0x00 vpsi vnsi vpci vnci 0x01 vpsi vth a1 vref ... vpsi vth a(tmux) vref 0x0b vpsi vth a11 vref 0x0c vrefps vrefns vrefpc vrefnc 0x0d psin nsin pcos vddah 0x0e pcos ncos psin vddah 0x0f C C C C table 31: test signal multiplexer for analog signals tmux add. 0x09, bit 3:0 code inca incb 0x00 d09 d0 0x01 d1 d0 ... d(tmux) d0 0x0b d11 d0 0x0c i3 d0 0x0d i2 d0 0x0e i1 d0 0x0f i0 d0 table 32: test signal multiplexer for digital signals in the digital test synchronized data is output when nysnc = 0; when nsync = 1 the comparator outputs of tracks 1-11 are output to d1-d11. inc add. 0x08, bit 6:4 code inca incb 0x06 xall d0 table 33: ic-haus test 1 inc add. 0x08, bit 6:4 code inca incb 0x07 tp npor table 34: ic-haus test 2 ic-haus expressly reserves the right to change its products and/or speci?cations. an info letter gives details as to any amendments and additions made to the relevant current speci?cations on our internet website www.ichaus.de/infoletter ; this letter is generated automatically and shall be sent to registered users by email. copying C even as an excerpt C is only permitted with ic-haus approval in writing and precise reference to source. ic-haus does not warrant the accuracy, completeness or timeliness of the speci?cation and does not assume liability for any errors or omissions in these materials. the data speci?ed is intended solely for the purpose of product description. no representations or warranties, either express or implied, of merchantability, ?tness for a particular purpose or of any other nature are made hereunder with respect to information/speci?cation or the products to which information refers and no guarantee with respect to compliance to the intended use is given. in particular, this also applies to the stated possible applications or areas of applications of the product. ic-haus conveys no patent, copyright, mask work right or other trade mark right to this product. ic-haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. as a general rule our developments, ips, principle circuitry and range of integrated circuits are suitable and speci?cally designed for appropriate use in technical applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. in principle the range of use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued annually by the bureau of statistics in wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in hanover (hannover-messe). we understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations of patent law. our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can be put to. p r e l i m i n a r y p r e l i m i n a r y
IC-LNG 16-bit opto encoder with spi and serial / parallel outputs rev a1, page 25/ 25 ordering information type package options order designation IC-LNG 30-pin optobga, 7.6 mm x 7.1 mm, thickness 1.7 mm standard reticle lng1r IC-LNG obga lnb2c-1r IC-LNG 30-pin optobga, 7.6 mm x 7.1 mm, thickness 1.7 mm standard reticle lng2r IC-LNG obga lnb2c-2r IC-LNG 30-pin optobga, 7.6 mm x 7.1 mm, thickness 1.7 mm reticle on request IC-LNG obga lnb2c-xr IC-LNG optoqfn package under preparation suitable encoder discs: 1024 ppr od / id ? 42.0 / 18.0 mm glass 1 mm lng1sz 42-1024 512 ppr od / id ? 24.8 / 2.0 mm glass 1 mm lng2s 25-512 for technical support, information about prices and terms of delivery please contact: ic-haus gmbh tel.: +49 (61 35) 92 92-0 am kuemmerling 18 fax: +49 (61 35) 92 92-192 d-55294 bodenheim web: http://www.ichaus.com germany e-mail: sales@ichaus.com appointed local distributors: http://www.ichaus.com/sales_partners p r e l i m i n a r y p r e l i m i n a r y

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