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d?a?t?a?b?o?o?k samsung v samsung asic kg80/KGM80 0.5 m m 5v/3.3v gate array cell library april 1997
kg80/KGM80 0.5 m m 5v/3.3v gate array cell library data book ? 1997 samsung electronics co., ltd. all rights reserved. no part of this document may be reproduced, in any form or by any means, without the prior written consent of the publisher. samsung assumes no responsibility for any errors resulting from the use of the information contained herein, nor does it convey any license under the patent rights of samsung or others. samsung reserves the right to make changes in its products or product specification to improve function or design at any time, without notice. sec, kg80 and KGM80 are trademarks of samsung electronics co., ltd. verilog is a registered trademark of cadence design systems, inc. viewlogic is a registered trademark of viewlogic systems, inc. mentor is a registered trademark or mentor graphics co. synopsys is a registered trademark of synopsys, inc. gards is a registered trademark of silvar-lisco. head office samsung electronics co., ltd lsi division, asic team san #24, nongseo-ree, kiheung-eup, yongin-shi, kyunggi-do, korea tel 02-760-6500 (hot line) fax 02-760-6499 printed in the republic of korea marketing team samsung electronics co., ltd semiconductor sales division, lsi export team 15th fl., severance bldg. 84-11, 5-ka, namdaemoon-ro, chung-ku, seoul, korea tel 02-259-4988 fax 02-259-2494
sec asic iii kg80/KGM80 introduction this databook contains information about kg80/KGM80, 0.5 m m 5v/3.3v dlm/tlm gate array cell library developed by sec (samsung electronics corporation). the library basically contains various kinds of internal and i/o cells and soft-macros which are used for developing asic (application specific integrated circuit). it also includes a design kit helping designers to work in a workstation platform, and all sorts of design environments needed for an automatic chip design. there are six chapters in this databook: chapter 1 introduction to kg80/KGM80 chapter 2 electrical characteristics chapter 3 internal macrocells chapter 4 input/output cells chapter 5 memory compilers chapter 6 jtag boundary scans. in this databook each cell is followed by its ac electrical characteristics, and these characteristic values are almost equal when the corresponding cell is operated in a real chip. the purpose of this databook is to prevent any misuse or misapplication of kg80/KGM80 cell library by providing precise information about the cell list, electrical data, directions for use, and matters demanding special attention.
kg80/KGM80 iv sec asic table of contents 1 introduction to kg80/KGM80 library description ........................................................................................................................1-1 features ........................................................................................................................................1-1 cae support .................................................................................................................................1-2 product family ..............................................................................................................................1-2 internal macrocells ...............................................................................................................1-2 macrofunctions .....................................................................................................................1-2 megafunctions ......................................................................................................................1-2 memory compilers ...............................................................................................................1-2 input/output cells.................................................................................................................1-3 v dd /v ss rules and guidelines .....................................................................................................1-5 power dissipation..........................................................................................................................1-7 propagation delays .......................................................................................................................1-9 delay model ..................................................................................................................................1-13 testability design methodology.....................................................................................................1-14 maximum fanouts .........................................................................................................................1-15 product line-up ............................................................................................................................1-21 packages.......................................................................................................................................1-21 dedicated corner v dd /v ss pads ..................................................................................................1-22 external design interface considerations .....................................................................................1-23 crystal oscillator considerations ..................................................................................................1-29 2 electrical characteristics dc electrical characteristics.........................................................................................................2-1 input buffer dc curves .................................................................................................................2-3 output drive capabilities...............................................................................................................2-5 3 internal macrocells overview .......................................................................................................................................3-1 summary tables ...........................................................................................................................3-2 logic cells ad2/ad2d2...................................................................................................................................3-11 ad3/ad3d3...................................................................................................................................3-13 ad4/ad4d2...................................................................................................................................3-16
sec asic v kg80/KGM80 ad5/ad5d2...................................................................................................................................3-19 nd2/nd2d2 ..................................................................................................................................3-22 nd3/nd3d2 ..................................................................................................................................3-24 nd4/nd4d2 ..................................................................................................................................3-27 nd5/nd5d2 ..................................................................................................................................3-30 nd6/nd6d2 ..................................................................................................................................3-33 nd8/nd8d2 ..................................................................................................................................3-38 nr2/nr2d2 ..................................................................................................................................3-43 nr3/nr3d2 ..................................................................................................................................3-45 nr4/nr4d2 ..................................................................................................................................3-48 nr5/nr5d2 ..................................................................................................................................3-51 nr6/nr6d2 ..................................................................................................................................3-54 nr8/nr8d2 ..................................................................................................................................3-59 or2/or2d2 ..................................................................................................................................3-64 or3/or3d3 ..................................................................................................................................3-66 or4/or4d2 ..................................................................................................................................3-69 or5/or5d2 ..................................................................................................................................3-72 xn2/xn2d2...................................................................................................................................3-76 xn3/xn3d3...................................................................................................................................3-78 xo2/xo2d2 ..................................................................................................................................3-81 xo3/xo3d3 ..................................................................................................................................3-83 ao21/ao21d2...............................................................................................................................3-86 ao211/ao211d2...........................................................................................................................3-89 ao22/ao22d2...............................................................................................................................3-92 ao22a/ao22d2a..........................................................................................................................3-95 ao222/ao222d2...........................................................................................................................3-98 ao222a/ao222d2a......................................................................................................................3-103 ao33/ao33d2...............................................................................................................................3-106 ao333/ao333d2...........................................................................................................................3-111 oa21/oa21d2 ..............................................................................................................................3-116 oa211/oa211d2 ..........................................................................................................................3-119 oa22/oa22d2 ..............................................................................................................................3-122 oa22a/oa22d2a..........................................................................................................................3-125 oa2222/oa2222d2 ......................................................................................................................3-128 dl(1/2/3/4/5/10)d2/dl(1/2/3/4/5/10)d4 ........................................................................................3-133 iv/ivd2/ivd3/ivd4/ivd6/ivd8 ......................................................................................................3-139 iva/ivd2a/ivd3a/ivd4a...............................................................................................................3-143 ivcd(11/13)/ivcd(22/26)/ivcd44................................................................................................3-146 ivt/ivtd2/ivtd4/ivtd8 ...............................................................................................................3-150 ivtn/ivtnd2/ivtnd4/ivtnd8.....................................................................................................3-154 nid/nid2/nid3/nid4/nid6/nid8 ..................................................................................................3-158 nit/nitd2/nitd4/nitd8 ..............................................................................................................3-162 nitn/nitnd2/nitnd4/nitnd8 ....................................................................................................3-166
kg80/KGM80 vi sec asic flip-flops fd1/fd1d2 ...................................................................................................................................3-173 fd1cs/fd1csd2 .........................................................................................................................3-176 fd1s/fd1sd2 ..............................................................................................................................3-180 fd1q/fd1qd2 .............................................................................................................................3-183 fd1x2 ...........................................................................................................................................3-185 fd1x4 ...........................................................................................................................................3-187 yfd1/yfd1d2 ..............................................................................................................................3-190 fd2/fd2d2 ...................................................................................................................................3-193 fd2cs/fd2csd2 .........................................................................................................................3-196 fd2s/fd2sd2 ..............................................................................................................................3-200 fd2q/fd2qd2 .............................................................................................................................3-203 fd2x2 ...........................................................................................................................................3-205 fd2x4 ...........................................................................................................................................3-208 yfd2/yfd2d2 ..............................................................................................................................3-211 fd2t/fd2td2...............................................................................................................................3-214 fd2tcs/fd2tcsd2.....................................................................................................................3-217 fd2ts/fd2tsd2 ..........................................................................................................................3-222 fd3/fd3d2 ...................................................................................................................................3-226 fd3cs/fd3csd2 .........................................................................................................................3-229 fd3s/fd3sd2 ..............................................................................................................................3-233 fd3q/fd3qd2 .............................................................................................................................3-236 fd3x2 ...........................................................................................................................................3-238 fd3x4 ...........................................................................................................................................3-241 yfd3/yfd3d2 ..............................................................................................................................3-244 fd4/fd4d2 ...................................................................................................................................3-247 fd4cs/fd4csd2 .........................................................................................................................3-251 fd4s/fd4sd2 ..............................................................................................................................3-257 fd4q/fd4qd2 .............................................................................................................................3-261 fd4x2 ...........................................................................................................................................3-264 fd4x4 ...........................................................................................................................................3-267 yfd4/yfd4d2 ..............................................................................................................................3-272 fd5/fd5d2 ...................................................................................................................................3-275 fd5s/fd5sd2 ..............................................................................................................................3-278 fd5x4 ...........................................................................................................................................3-281 fd6/fd6d2 ...................................................................................................................................3-284 fd6s/fd6sd2 ..............................................................................................................................3-287 fd7/fd7d2 ...................................................................................................................................3-290 fd7s/fd7sd2 ..............................................................................................................................3-293 fd8/fd8d2 ...................................................................................................................................3-296 fd8s/fd8sd2 ..............................................................................................................................3-300 fds2/fds2d2 ..............................................................................................................................3-304 fds2cs/fds2csd2 ....................................................................................................................3-307
sec asic vii kg80/KGM80 fds2s/fds2sd2..........................................................................................................................3-311 fds3/fds3d2 ..............................................................................................................................3-314 fg1 ...............................................................................................................................................3-317 fg1x4 ...........................................................................................................................................3-319 fg2 ...............................................................................................................................................3-324 fg2x4 ...........................................................................................................................................3-327 fj1/fj1d2.....................................................................................................................................3-332 fj1s/fj1sd2 ................................................................................................................................3-335 fj2/fj2d2.....................................................................................................................................3-338 fj2s/fj2sd2 ................................................................................................................................3-341 fj4/fj4d2.....................................................................................................................................3-345 fj4s/fj4sd2 ................................................................................................................................3-349 ft2/ft2d2 ....................................................................................................................................3-353 ft3/ft3d2 ....................................................................................................................................3-356 latches ld1/ld1d2 ...................................................................................................................................3-361 ld1s/ld1sd2...............................................................................................................................3-364 ld1q/ld1qd2 ..............................................................................................................................3-369 ld1x4/ld1x4d2...........................................................................................................................3-372 yld1/yld1d2...............................................................................................................................3-381 ld1a .............................................................................................................................................3-384 ld1b .............................................................................................................................................3-386 ld2/ld2d2 ...................................................................................................................................3-389 ld2q/ld2qd2 ..............................................................................................................................3-394 yld2/yld2d2...............................................................................................................................3-397 ld3/ld3d2 ...................................................................................................................................3-402 ld4/ld4d2 ...................................................................................................................................3-407 ld5/ld5d2 ...................................................................................................................................3-412 ld5s/ld5sd2...............................................................................................................................3-415 ld5x4/ld5x4d2...........................................................................................................................3-420 ld6/ld6d2 ...................................................................................................................................3-429 ld7/ld7d2 ...................................................................................................................................3-434 ld8/ld8d2 ...................................................................................................................................3-439 lds2 .............................................................................................................................................3-444 lds6 .............................................................................................................................................3-447 ls0/ls0d2 ....................................................................................................................................3-450 ls1 ................................................................................................................................................3-453 ls2 ................................................................................................................................................3-456 bus holder busholder ................................................................................................................................3-459
kg80/KGM80 viii sec asic internal clock drivers ck2/ck4/ck6/ck8/ck12 .............................................................................................................3-460 decoders dc4 ...............................................................................................................................................3-464 dc4i ..............................................................................................................................................3-467 dc8i ..............................................................................................................................................3-470 adders fa/fad2 ........................................................................................................................................3-478 ha/had2.......................................................................................................................................3-483 multiplexers mx2/mx2d3 ..................................................................................................................................3-487 mx2x4 ..........................................................................................................................................3-490 ymx2/ymx2d2 .............................................................................................................................3-495 mx2i/mx2id2 ................................................................................................................................3-498 mx2ia/mx2id2a ...........................................................................................................................3-501 mx2ix4 .........................................................................................................................................3-504 mx3i/mx3id2 ................................................................................................................................3-509 mx4/mx4d2 ..................................................................................................................................3-512 ymx4/ymx4d2 .............................................................................................................................3-517 mx5/mx5d2 ..................................................................................................................................3-522 mx8/mx8d2 ..................................................................................................................................3-527 ymx8/ymx8d2 .............................................................................................................................3-533 4 input/output cells overview .......................................................................................................................................4-1 summary tables ...........................................................................................................................4-2 input buffers pvic/pvicd/pvicu........................................................................................................................4-9 pvil/pvild/pvilu .........................................................................................................................4-13 pvis/pvisd/pvisu ........................................................................................................................4-16 pvit/pvitd/pvitu .........................................................................................................................4-20 output buffers pvobyz .........................................................................................................................................4-24 pvodyz .........................................................................................................................................4-41 pvotyz ..........................................................................................................................................4-64
sec asic ix kg80/KGM80 bi-directional buffers pvbadyz/pvbaudyz .....................................................................................................................4-98 pvbatyz/pvbadtyz/pvbautyz .....................................................................................................4-98 input clock drivers psckdcy/psckdcdy/psckdcuy.............................................................................................4-100 psckdly/psckdldy/psckdluy...............................................................................................4-107 psckdsy/psckdsdy/psckdsuy .............................................................................................4-111 psckdty/psckdtdy/psckdtuy ..............................................................................................4-118 oscillators psoscm(1/2/3/4/5/6) ...................................................................................................................4-122 pci buffers psipcia/plsipcia/psipcia3/phsipcia ....................................................................................4-132 psopcia/plsopcia/psopcia3/phsopcia.............................................................................4-133 psipciau......................................................................................................................................4-134 psopciau ....................................................................................................................................4-135 pcmcia buffers pvic(5/3) ......................................................................................................................................4-139 pvil(d/u)(5/3)/pvit(d/u)(5/3)......................................................................................................4-139 pvob(4/8/12)(5/3).........................................................................................................................4-140 pvod(4/8/12)(5/3) ........................................................................................................................4-140 pvot(4/8/12)(5/3) .........................................................................................................................4-141 pvot(8/12)sm(5/3).......................................................................................................................4-141 pvbtt(4/8/12)(5/3) .......................................................................................................................4-142 pvbtdt8sm/pvbct8sm(5/3) .....................................................................................................4-142 cardbus i/o buffers pvitcbu .......................................................................................................................................4-146 pvotcbu/pvotcckcbu/pvotcvscbu ...................................................................................4-147 pvodcckcbu..............................................................................................................................4-148 pvbttcbu/pvbtcckcbu/pvbtcvscbu ..................................................................................4-149 pvbdcckcbu ..............................................................................................................................4-150 plscb ..........................................................................................................................................4-151 voltage detector (under development) vdet.............................................................................................................................................4-152 power pads vdd(5/3)(i/p/o/ip/oi/op/t) ..........................................................................................................4-153 vss(5/3)(i/p/o/ip/oi/op/t)...........................................................................................................4-153
kg80/KGM80 x sec asic 5 memory compilers overview .......................................................................................................................................5-1 rom ..............................................................................................................................................5-2 ram ..............................................................................................................................................5-7 1r1w dpram ..............................................................................................................................5-13 1rw1r dpram............................................................................................................................5-19 fifo ..............................................................................................................................................5-27 multiplier ........................................................................................................................................5-29 6 jtag boundary scans overview .......................................................................................................................................6-1 boundary scan architecture .........................................................................................................6-2 boundary scan register macrocells .............................................................................................6-4 jtbi1 ....................................................................................................................................6-5 jtck.....................................................................................................................................6-12 jtin1 ....................................................................................................................................6-14 jtint1..................................................................................................................................6-18 jtout1 ................................................................................................................................6-24 jtag tap controller macrofunction..............................................................................................6-28 instruction register/decoder macrofunction .................................................................................6-31 implementation of ieee p1149.1/jtag ........................................................................................6-32 system clock considerations .......................................................................................................6-32
introduction to kg80/KGM80 1
table of contents library description....................................................................................................... 1-1 features....................................................................................................................... 1-1 cae support................................................................................................................ 1-2 product family ............................................................................................................. 1-2 internal macrocells.............................................................................................. 1-2 macrofunctions.................................................................................................... 1-2 megafunctions..................................................................................................... 1-2 memory compilers.............................................................................................. 1-2 input/output cells ............................................................................................... 1-3 v dd /v ss rules and guidelines .................................................................................... 1-5 power dissipation ........................................................................................................ 1-7 propagation delays ..................................................................................................... 1-9 delay model ................................................................................................................. 1-13 testability design methodology ................................................................................... 1-14 maximum fanouts ....................................................................................................... 1-15 product line-up........................................................................................................... 1-21 packages ..................................................................................................................... 1-21 dedicated corner v dd /v ss pads................................................................................. 1-22 external design interface considerations ................................................................... 1-23 crystal oscillator considerations................................................................................. 1-29
introduction to kg80/KGM80 library description sec asic 1-1 kg80/KGM80 library description sec asic offers kg80 5v gate array family and KGM80 3.3v gate array family. kg80 and KGM80 are 0.5 m m cmos processes supporting double-layer or triple-layer metal interconnection options. the gate array is a kind of design methods. in this design method, all processes before a metal wiring have been completed in a masterslice, and the remaining processes from a metal wiring will be added on the prepared masterslice to form a user-specitc circuit. the gate array is used world-widely because of its short period of products development. with the regard to the mixed using of 5v and 3.3v, 5v-to-3.3v and 3.3v-to-5v convertible cells having level shifters inside themselves are provided in addition to the existing normal input/output cells. moreover, the other interface cells (cmos, ttl and schmitt trigger) are fully equipped for your wide selection. in order to ensure the product reliability, we eftciently prevent any possible noise, esd and latch-up. various kinds of memory compiler, macrofunction and megafunction cells may satisfy the complicated design requirements and offer convenience to users. there are 14 kinds of masterslices provided (they are preliminary), therefore, you can choose the most appropriate masterslice according to the gate count and pin number of the product. every work operation in a design ?ow has been systematized and automated, and each stage is designed to go through enough reviews and veritcations. it makes the design work easier and faster, and prevents any errors or mistakes possible through a design ?ow. features q kg80: 5volt gate array library KGM80: 3.3volt gate array library q mixed 5v/3.3v i/o interface q 0.5 m m 5v hcmos channelless technology e double and triple layer metal options q high basic cell usages e 42,400 to 1,250,000 total number of gates e maximum usage: 70% for triple layer metal e maximum usage: 40% for double layer metal q high speed e 0.2 ns (for kg80) and 0.3ns (for KGM80) delay of 2-input nand with fanout = 2 q fully contgurable ram,rom and dpram e up to 9k-bit ram available e up to 36k-bit rom available e up to 9k-bit dpram available q contgurable fifo and multiplier available q operating temperature (t a ) e commercial range: 0?c to +70?c e industrial range: e40?c to +85?c q esd and latch-up protection e esd: 2000v (min.) e latch-up: 300ma (min.) q selectable output current drive capability e 1/2/4/8/12/16/20/24ma available for 5v e 1/2/4/6/8/10/12/16ma available for 3.3v q ttl, cmos, lvttl, lvcmos and schmitt trigger i/os q x-tal oscillators q pci, pcmcia buffers q gtl, ntl, cardbus, scsi, pecl under-developed q various package options q fully integrated cad software support e verilog, viewlogic, mentor and synopsys
cae support introduction to kg80/KGM80 kg80/KGM80 1-2 sec asic cae support kg80/KGM80 supports popular design platforms and environments such as verilog, viewlogic, mentor and synopsys for front-end logic design capture and simulation, and gate ensemble and gards for back-end placement and routing. for a high simulation accuracy, kg80/KGM80 uses a proprietary delay calculator. cell delay calculations are based on a matrix of delay parameters for each macrocell, and signal interconnection delay is based on the rc tree analysis. product family kg80/KGM80 library include the following design elements: (a) internal macrocells (b) input/output cells (c) macrofunctions (d) megafunctions (e) memory compilers (f) jtag boundary scans. < internal macrocells > macrocells are the lowest level of logic functions such as nand, nor and ?ip-?op used for logic designs. there are about 300 different types of internal macrocells. they usually come in two levels of drive strength (1x and 2x). these macrocells have many levels of representationslogic symbol, logic model, timing model, transistor schematic, hspice netlist, physical layout, and placement and routing model. < macrofunctions > macrofunctions are netlists of logic function which have the complexity of a standard msi circuit. macrofunctions are logic building blocks. there are 44 kinds of 74xx (ttl) compatible functions in this library. < megafunctions > megafunctions are also netlists of logic function, but with a high logic complexity of a standard lsi circuit. multipliers, barrel shifters, 82xx intel functions, etc. are supported in this library. < memory compilers> memory compilers of kg80/KGM80 consist of asynchronous rom, single-port ram, dual-port rams, ram-based fifo and multiplier generators. there are two types of dual-port rams; one read one write dpram and one read/write one read dpram.
introduction to kg80/KGM80 product family sec asic 1-3 kg80/KGM80 < input/output cells > there are about one thousand different i/o buffers. each i/o cell is implemented solely on the basic i/o cell architecture which forms the periphery of the masterslice. a test logic is provided to enable the ef?cient parametric (threshold voltage) testing on input buffers including cmos and ttl level converters, schmitt trigger input buffers, clock drivers and oscillator buffers. pull-up and pull-down resistors are optional features. three basic types of output buffers (non-inverting, tri-state and open drain) are available in a range of driving capabilities from 1ma to 24ma for 5v drive and 1ma to 16ma for 3.3v drive.two levels of slew rate controls are provided for each buffer type (except 1ma and 2ma buffers) to reduce output power/ground bus noise and signal ringing, especially in simultaneous switching outputs. bi-directional buffers are combinations of input buffers and output buffers (tri-state or open drain) in a single unit. the i/o structure has been fully characterized for esd protection and latch-up resistance. for users convenience, kg80/KGM80 library provides with three options of pull-down and pull-up resistances respectively. they are 50k w , 100k w , and 200k w (the default value is 100k w ). i/o cell drive options to provide designers with the greater ?exibility, each i/o buffer can be selected among various current levels (e.g., 1ma, 2ma, ..., 24ma). the choice of current-level for i/o buffers affects their propagation delay and current noise. the slew rate control helps decrease the system noise and output signal overshoot/undershoot caused by the switching of output buffers. the output edge rate can be slowed down by selecting the high slew rate control cells. kg80/KGM80 provides three different sets of output slew rate controls. only one i/o slot is required for any slew rate control options. 5v/3.3v mixed i/o cells when designers intend to make transitions from 5v supplies to low voltage system, kg80 offers a solution of interfacing problems encountered in mixed 5v/3v environment. this solution provides great ?exibility to different devices communicating each other. pci and pcmcia buffers are also available in this solution. you can see this in the following ?gure. figure 1-1. 5v/3.3v mixed i/o cells in kg80 in KGM80, level shifters are available to provide internal 3v core with great ?exibility when it interfaces with a 5v device. refer to the ?gure below. figure 1-2. 5v/3.3v mixed i/o cells in KGM80 pci buffers in addition to input, output, bi-directional, slew rate controlled and schmitt trigger i/o buffers, sec asic now offers pci (peripheral component interconnect) i/o buffers. pci is expected to be better suited to the more complex and feature-rich design than the existing local bus standards. 5v, 3.3v and universal pci buffers are included in the library. 3.3v level shifter 5v internal 5v kg80 i/o cells 3.3v level shifter 5v kg80 i/o cells operation 3.3v 5v internal 3.3v KGM80 i/o cells 3.3v 5v KGM80 i/o cells level shifter level shifter operation
product family introduction to kg80/KGM80 kg80/KGM80 1-4 sec asic cardbus buffers cardbus i/o buffers have 3.3v 32-bit bus width and 33mhz of transmission speed. they are for external cardbus type of extension card of notebook pc. pecl sec asics pecl (positive emitter coupled logic) buffer having 155mhz operating frequency is suited to atm interface. it supports two voltage source modes; 5v and 3.3v. the voltage swing level is about 0.8v, being similar to that of ecl, and the external terminator is needed. its main features are the same as ecl; low noise, high speed and single ended/differential function. in case of differential transmission, the external terminator is shown in the following ?gure. figure 1-3. twisted pair termination techniques gtl (gunning transceiver logic) gtl and gtl+ interface i/os are useful for implementing highly reliable system, satisfying fast and low-powered signal transfers and reducing noise in a switching circuitry. in all 0.5 m m cell libraries in sec asic, gtl interface is fully supported. figure 1-4. gtl interface lvttl/lvcmos low voltage ttl and low voltage cmos i/o buffers have various kinds of applications as normal ttl and cmos i/o sets. their key features are low voltage swing and low noise. input voltage level is 5v compatible. output high voltage is 2.4v ~ 3.5v in lvttl and vddC0.2v in lvcmos. scsi scsi is widely used to extend peripherals, requires external terminator. sec asic supports scsi-3 fast-20 parallel interface and scsi-3 parallel interface only in kg80. both of them have fail-safe function. scsi buffer is two times as big as normal buffers. r pd r pd r 1 v ee v ee z o r 1 = z o standard twisted pair termination r 1 r 1 v tt v tt z o r 1 = z o /2 parallel twisted pair termination r 1 r 2 v ee z o r 1 = z o /2 thevenin twisted pair termination r 3 v t v t logic rcvr vref logic rcvr vref logic rcvr vref r t r t
introduction to kg80/KGM80 vdd/vss rules and guidelines sec asic 1-5 kg80/KGM80 pcmcia pcmcia (personnel computer memory card industry association) buffers guarantees an accurate logic level even when the internal or external voltage source level of a chip changes between 5v and 3.3v. this buffers are designed for 16-bit external extension card of notebook pc. lvds lvds (low voltage differential signals) buffer for sci (scalable coherent interface) system, shown in the following ?gure, enables high speed i/o interface with sec asics high frequency pll. this structure is designed for high speed point-to-point unidirectional interface. its main characteristics are much the same as ecls differential mode; low noise generation, high noise immunity and low level signalling. figure 1-5. lvds interface v dd /v ss rules and guidelines there are three types of v dd and v ss in kg80/KGM80, each with its related bus and pad cells. to support the use of mixed voltage, two different v dd types are needed for 5v and 3.3v respectively. (1) core logic C vssi, vdd5i (for 5v) (2) input buffers (usable when requested) C vssp, vdd5p (for 5v), vdd3p (for 3.3v) (3) output buffers C vsso, vdd5o (for 5v), vdd3o (for 3.3v) the number of v dd and v ss pads required for a speci?c design depends on the following factors: ? number of input and output buffers ? number of simultaneous switching inputs ? number of simultaneous switching outputs ? number of used gates and simultaneous switching gates ? operating frequency of the design. core logic v ss bus and vssi pad allocation guidelines the purpose of these guidelines is to ensure that v dd /v ss bounce caused by a simultaneous gate switching is kept to minimum. the voltage bounce on the power bus can have a negative impact on a gate-switching speed and even on the functionality of macrocells like ?ip-?ops and latches in an extreme case. because of variations in package inductance, the number of v dd /v ss pads required for a speci?c design is the function of the operating frequency of a chip, i.e., designs operating at high frequency should use more v dd /v ss pads. ?v dd bus width and pad requirements are half of v ss . ?v dd /v ss buses and pads should be distributed evenly in the core and on all sides of the chip. ? whenever possible, at least one vssi pad should be used on each side of the chip. ? the total number of core logic v dd pads required is half of vssi. 100 w a v oa v ob b a? b? v ia v ib v gpd receiver interconnect driver
vdd/vss rules and guidelines introduction to kg80/KGM80 kg80/KGM80 1-6 sec asic the number of vssi pads required for a design can be calculated from the following expression: g x s x f x 2.00eC5 ,where g = total number of used gates, s = % of simultaneous switching gates, f = switching frequency in mhz. input buffer v dd /v ss pad allocation guidelines these guidelines ensure that an adequate input threshold voltage margin is maintained during a switching. ? one vssp is required to support 32 input buffers, and one input buffer v dd can support up to 64 inputs. ? for simultaneous switching inputs, one vssp pad is required for every 20 inputs, and one input buffer v dd pad for every 40 inputs. ? input buffer v ss /v dd pads should be placed in such a way that they equally divide the input buffers on either side. table 1-1. minimum input buffer vss/vdd for kg80/KGM80 device types gives the absolute minimum requirement for each device type. table 1-1. minimum input buffer v ss /v dd for kg80/KGM80 device types output buffer v dd /v ss pad allocation guidelines the number of vsso pads required for a device can be calculated from the following expressions. in 5v ? (i ol simultaneous switching outputs ) / 40 + ? (i ol normal outputs ) / 64 in 3.3v ? (i ol simultaneous switching outputs ) / 50 + ? (i ol normal outputs ) / 80 the total number of output buffer v dd pads required is half of vsso. output buffer v ss /v dd pads should be placed in such a way that output buffers are equally divided on either side. devices input buffer v ss input buffer v dd kg8563d 2 1 kg8144d 3 2 kg8244d 4 2 kg8444d 4 2
introduction to kg80/KGM80 power dissipation sec asic 1-7 kg80/KGM80 power dissipation estimation of power dissipation in cmos circuit cmos circuits have been traditionally considered to consume low power since they draw very small amount of current in a steady state. however, the recent revolution in a cmos technology that allows very high gate density has changed the way the power dissipation should be understood. the power dissipation in a cmos circuit is affected by various factors such as the number of gates, a switching frequency, the loading on the output of a gate, and so on. power dissipation is important when designers decide the amount of necessary power supply current for the device to operate in safety. propagation delays and a reliability of the device also depend on the power dissipation which determines the temperature at which the die operates. to obtain a high speed and a reliability, designers must estimate the power dissipation of the device accurately and determine the appropriate environments including packages and system cooling methods. this section describes the concept of two types of power dissipation (static and dynamic) in a cmos circuit, the method of calculating them in the sec kg80/KGM80 library, and ?nally their relationship with a temperature. static (dc) power dissipation there are two types of static or dc current contributing to the total static power dissipation in cmos circuits. one is the leakage current of the gates resulted by a reverse bias between a well and a substrate region. there is no dc current path from power to ground in a cmos because one of the transistor pair is always off, therefore, no static current except the leakage current ?ows through the internal gates of the device. the amount of this leakage current is, however, in the range of tens of nano amperes, which is negligible. the other is dc current that ?ows through the input and output buffers when the circuit is interfaced with other devices, especially ttl. the current of pull-up/pull-down transistor included in the input buffers is about 50 m a typically, which is also negligible. therefore, only dc current that the output buffers source or sink has to be counted to estimate the total static power dissipation. dc power dissipation of ttl output and bi-directional buffers is determined by the following formula: p dc_ttl_ output = ? (v ol x i ol x t l ) + ? ((v dd e v oh ) x i oh x t h ) ,where t h = t high / t, t l + t h = 1. dynamic (ac) power dissipation when a cmos gate changes its state, it draws switching current as a result of charging or discharging of a node capacitance, c l . the energy associated with the switching current for a node capacitance, c l , is 1 / 2 x (c l x v dd 2 ) ,where v dd is a power supply voltage. the switching occurs twice per cycle for periodic signals: once for charging a capacitance and once for discharging it. hence, the dynamic power dissipation due to the switching current is the energy divided by the clock period and multiplied by the factor of two, or c l x v dd x v dd / t ,where t is a clock period. as shown above, it is quite straight forward to calculate the dynamic power dissipation for a single gate. the dynamic power dissipation for an entire chip is, however, much more complicated to estimate since it depends on the degree of switching activity of the circuit. sec has found that the degree of switching activity is 20% on the average and recommends to use this number to estimate the total dynamic power dissipation.
power dissipation introduction to kg80/KGM80 kg80/KGM80 1-8 sec asic power dissipation in kg80/KGM80 this section describes the equations on how to estimate the power dissipation in kg80/KGM80. as explained in the previous section, the total power dissipation (p total ) consists of static power dissipation (p dc ) and dynamic power dissipation (p ac ). p total = p dc + p ac since only output buffers contribute to the static power dissipation, p dc = p dc_output ,where p dc output is the static power dissipated when output buffers source or sink. the dynamic power dissipation is caused by three components: input buffers (p ac_input ), output buffers (p ac_output ), and internal cells (p ac_internal ). p ac = p ac_ input + p ac_output + p ac_internal each term mentioned above is characterized by the following equations: in kg80, p dc_output = 150 x i ol x n_output [ m w] p ac_input = 23 x n_input x f x s [ m w] p ac_output = 25 x n_output x f x s x c [ m w] p ac_internal = 2.3 x n_internal x f x s [ m w] in KGM80, p dc_output = 150 x i ol x n_output [ m w] p ac_input = 9.8 x n_input x f x s [ m w] p ac_output = 25 x n_output x f x s x c [ m w] p ac_internal = 1.2 x n_internal x f x s [ m w] ,where i ol is source and sink current of output buffers in ma, n_output is the number of output buffers used, n_input is the number of input buffers used, n_internal is the number of internal cells used, f is the maximum operation frequency in mhz, s is the estimated degree of a switching activity (typically 0.2), c is the output load capacitance in pf. temperature and power dissipation the total power dissipation, p total can be used to ?nd out the device temperature by the following equation: q ja = (t j e t a ) / p total ,where q ja is the thermal impedance, t j is the junction temperature of the device, t a is the ambient temperature. thermal impedances of the sec packages are given in the following table. the junction temperature, obtained by multiplying p total by the appropriate q ja and adding t a , determines the derating factor for the propagation delays and also indicates the reliability measures. hence, designers can achieve the desired derating factor and reliability targets by choosing appropriate packages and system cooling methods. table 1-2. thermal impedances of sec packages maximum junction temperature (t j ) the allowable maximum junction temperatures for plastic and ceramic packages are as follows: junction temperature for plastic package 125 c junction temperature for ceramic package 150 c. qfp pin number 64 80 100 120 160 208 240 q ja [ c/w] 60 60 60 50 50 40 40
introduction to kg80/KGM80 propagation delays sec asic 1-9 kg80/KGM80 propagation delays interconnection wire length, temperature and supply voltage are the chief factors affecting propagation delays. wire length load the loading due to interconnection wire length can be estimated with the following expression. the result is given in terms of number of equivalent standard loads. c wl = c fo ,where c fo = number of fanouts in a standard load, a = area of block size in mm 2 , c wl = number of equivalent standard loads due to an interconnection, e.g., c fo = 7 (standard load), a = 25mm 2 , c wl = 5.8 (standard load). temperature and supply voltage the next ?gure describes propagation delay correction factors (k t , k v ) as a function of on-chip junction temperature (t j ) as well as supply voltage (v dd ). as a result of increasing cmos power dissipation, ambient and junction temperature are generally not the same. the temperature of the die inside the package (junction temperature, t j ), is calculated using chip power dissipation and the thermal resistance to ambient temperature ( q ja ) of the package. information on package thermal performance can be obtained from sec application engineers. figure 1-6. effect of temperature and supply voltage on propagation delay 0.049 a 0.48 + () 0.079 a 0.33 + + temperature (t j ) k t 1.10 1.07 1.00 0.96 0.90 C40 0 70 25 85 1.16 125 ( c) supply voltage (v dd ) 1.08 1.00 0.94 4.5 5.0 5.5 (volt) k v 1.04 0.97 4.75 5.25 1.24 1.00 3.0 3.6 (volt) k v 1.10 0.92 2.7 3.3 kg80/KGM80 kg80 KGM80
propagation delays introduction to kg80/KGM80 kg80/KGM80 1-10 sec asic best and worst case conditions a circuit should be designed to operate properly within a given speci?cation level, either commercial or industrial. it is recommended that circuits be simulated for best case, normal case, and worst case conditions at each speci?cation level. the following expressions also allow for the effect of process variation on circuit performance. best case: t bc = k pbc x k t x k v x t nom = k bc x t nom worst case: t wc = k pwc x k t x k v x t nom = k wc x t nom ,where t bc = best case propagation delay t wc = worst case propagation delay t nom = normal propagation delay (t j = 25 o c, v dd = 5v and typical process) k pwc = worst case process correction factor k pbc = best case process correction factor with above equations, we can calculate the multipliers of k wc and k bc as follows. table 1-3. kg80 best case delay table 1-4. kg80 worst case delay table 1-5. KGM80 best case delay table 1-6. KGM80 worst case delay derating factors of kg80/KGM80 the multipliers can be applied to nominal delay data in order to estimate the effects of supply voltage, temperature and process. nominal data are provided for conditions of v dd = 5v, t a = 25 c and typical process. the derating factors of kg80/KGM80 are as follows. table 1-7. kg80/KGM80 process derating factor table 1-8. kg80 temperature derating factor table 1-9. KGM80 temperature derating factor table 1-10. kg80 voltage derating factor (k v ) table 1-11. KGM80 voltage derating factor (k v ) application best case delay parameter k bc v dd t j proc. industrial 5.5v C40 o c min. 0.51 commercial 5.25v 0 o c min. 0.56 application worst case delay parameter k wc v dd t j proc. industrial 4.5v 125 o c max. 1.75 commercial 4.75v 115 o c max. 1.66 application best case delay parameter k bc v dd t j proc. industrial 3.6v C40 o c min. 0.50 commercial 3.6v 0 o c max. 0.53 application worst case delay parameter k wc v dd t j proc. industrial 2.7v 125 o c max. 2.02 commercial 3.0v 115 o c max. 1.77 process factor (k p ) slow typ. fast 1.40 1.00 0.60 temp. ( o c) 125 85 70 25 0 C40 k t 1.16 1.10 1.07 1.00 0.96 0.90 temp. ( o c) 125 85 70 25 0 C40 k t 1.15 1.09 1.07 1.00 0.96 0.90 voltage (v) 5.5 5.25 5 4.75 4.5 k v 0.94 0.97 1.00 1.04 1.08 voltage (v) 3.6 3.3 3.0 2.7 k v 0.92 1.00 1.10 1.24
introduction to kg80/KGM80 propagation delays sec asic 1-11 kg80/KGM80 timing parameters this section discusses issues involving timing parameters for primitive cells. rise / fall times the de?nition of rise time (t r ) and fall time (t f ) is shown in the following ?gure. figure 1-7. rise and fall times setup / hold times setup time (t su ) is a minimum period in which the input data to a ?ip-?op or a latch must be stable before the active edge of the clock occurs. hold time (t hd ) is a minimum period in which the input data to a ?ip-?op or a latch must remain stable after the active edge of the clock has occurred. the next ?gure shows the relationship between setup and hold times for a standard ?ip-?op triggered on the rising edge of the clock. figure 1-8. setup and hold times minimum pulse widths minimum clock pulse widths (t pwh , t pwl ) are the time intervals during a clock signal is high or low, so that it ensures proper operation of a ?ip-?op or a latch. figure 1-9. minimum pulse width recovery times recovery time (t rc ) is the minimum time after an asynchronous pin is disabled that an active clock edge will propagate data from input to output. if the active edge or clock occurs before the speci?ed recovery time, the input data will not propagate. figure 1-10. recovery time t r t f 10% 90% 90% 10% v dd d ck t su t hd d ck q t pwh d rb ck q t rc
propagation delays introduction to kg80/KGM80 kg80/KGM80 1-12 sec asic propagation delays a delay for a macrocell is considered to be a rising delay (t plh ) if the signal on the output pin is rising. for a rising input and a rising output, the rising delay is the interval between the times the input becomes 50% of supply voltage (v dd ) and the output becomes 50% of v dd . if the input is falling and the output is rising, the rising delay is the interval between the times the input falls to 50% of v dd and the output rises to 50% of v dd . the converse is true for a falling delay (t phl ). figure 1-11. propagation delay proper use of buffers figure 1-12. average gate delay in kg80 shows the average propagation delays of an internal inverter (iv), an 8x inverter (ivd8), a normal clock driver (ck2), and a high clock driver (ck12) in kg80. note that transistors uses in i/o slots are larger and have on channel resistance about one order of magnitude lower than those of the n and p channel transistors in primitive cells. this makes them likely candidates for use as buffers for high fanout signals. for example, ck2 and ck12 buffers require one i/o slot location. both can be used as high fanout internal buffers. figure 1-12. average gate delay in kg80 one caution, emphasized in figure 1-13. use of i/o slot for an internal buffer, shows that if you route to a buffer that uses an i/o slot from an internal element and back into internal logic, the additional wiring needed could increase propagation delays materially. higher drive strength internal cells may be more appropriate than i/o slot buffers. realize also that using i/o slot cells for internal buffering removes those locations for use as external i/os and uses two wiring channels, thereby increasing routability congestion on masterslice products. figure 1-13. use of i/o slot for an internal buffer 50% 50% t plh 50% 50% t plh 50% 50% t phl 50% 50% t phl v dd 1.5 1.0 0.5 0 10 40 80 160 320 fanout [number] iv ivd8 ck2 ck12 average delay [ns] clock driver using i/o slot high fanout long wire
introduction to kg80/KGM80 delay model sec asic 1-13 kg80/KGM80 delay model the asic timing characteristics consist of the following components: ? cell propagation delay from input to output transitions based on input waveform slope, fanout loads and distributed interconnection wire resistance and capacitance. ? interconnection wire delay across the metal lines. ? timing requirement parameters such as setup time, hold time, recovery time, skew time, minimum pulse width, etc. ? derating factors for junction temperature, power supply voltage, and process variations. timing model for kg80/KGM80 focuses on how to characterize cell propagation delay time accurately. to accomplish this goal, 2-dimensional table look-up delay model has been adopted. the index variables of this table are input waveform slope and output load capacitance. see the ?gure below. sec asic design automation system supports an n-dimensional table model even though we adopted 2-dimensional model for our 0.5 m m cell-based products. figure 1-14. 2-dimensional table delay model the table 1-12. table delay model example shows an example of this model for 2-input nand cell. the data in this table are high-to-low transition delay times from one of the two input pins to output pin. the number of points and values of the index variables can differ for each cell. table 1-12. table delay model example notice that 4-by-4 table is used. delay values between grid points and beyond this table are determined by linear interpolation and extrapolation methods. this general table delay model provides great ?exibility as well as high accuracy since extensive software revisions are not required when a cell library is updated. the other timing components such as interconnection wire delay, timing requirement parameters and derating factors are characterized in a commonly-accepted way in industry. the delay time due to the interconnection wire can be separated into two components. one is the signal propagation delay time across the metal lines. this delay time component is computed through conventional rc analysis based on ? -model. the other is an additional delay on the driving cell due to the wire load. the traditional way to compute this is based on the lumped capacitance model, ignoring wire resistance. for sub-micron technology, this approximation cannot be accepted any more. the wire resistance has a shielding effect on the driving cell from load capacitances. an effective capacitance c eff , a single capacitance approximating distributed interconnection wire resistance and capacitance, is derived, as illustrated in the following tgure. the compensation factor k, extracted for each cell, is a function of the length of interconnection wires and the layout topology. all these effects are merged to determine the effective capacitance and this value is used as an index of the table delay model. figure 1-15. concept of effect capacitance propagation delay [ns] input waveform slope [ns] load cap [pf] 1.5 1.0 0.5 1.0 2.0 3.0 0.4 0.8 1.2 0.03 0.13 0.53 1.32 0.10 0.07 0.14 0.42 0.97 0.30 0.08 0.17 0.45 1.02 0.80 0.06 0.18 0.51 1.07 1.60 0.01 0.18 0.60 1.18 c eff = f (k, cload) cap. slope
testability design methodology introduction to kg80/KGM80 kg80/KGM80 1-14 sec asic the ?gure below summarizes the features of sec asics delay model. 2-dimensional table delay model for output loading and input waveform slope effects is used. the slopes (t r , t f ) and delay times (t plh , t phl ) of all cell instances are calculated recursively. the input waveform slope of each primary input pad and the loading capacitance of each primary output pad can be assigned individually or by default. a pin to pin delays of cells and interconnection wires are supported. ? the effect of distributed interconnection wire resistance and capacitance on cell delay is analysed using the effective capacitance concept. figure 1-16. features of delay model testability design methodology scan design ? multiplexed scan ?ip-?op that minimizes the area or delay overhead needed to implement scan design ? automated design rules checking, scan insertion, and test pattern generation ? high fault coverage on synchronous designs boundary-scan ? ieee std 1149.1 ? 5 types of jtag boundary-scan cells ? boundary-scan description language (bsdl) description for board testing ? combination with internal scan design s1 s3 s2 co1 co2 co3 ck q d a_y b_y ? ? a mux scannable register device identity register bypass register instruction register ta p controller system logic tdi tms tck tdo test access port mux boundary scan path
introduction to kg80/KGM80 maximum fanouts sec asic 1-15 kg80/KGM80 maximum fanouts internal macrocells the maximum fanouts for kg80/KGM80 primitive cells are as follows. note that these fanout limitation values are calculated when the rise and fall times of the input signal is 0.40ns. depending on the rise and fall times, the maximum fanout limitations can be varied case by case. in the following table the maximum fanout values for all pins of kg80/KGM80 internal macrocells are listed. table 1-13. maximum fanouts of internal macrocells (when t r /t f = 0.40ns) cell name output pin maximum fanout kg80 KGM80 logic cells ad2 y 22 34 ad2d2 y 46 70 ad3 y 22 34 ad3d3 y 69 103 ad4 y 22 34 ad4d2 y 44 68 ad5 y 22 34 ad5d2 y 44 65 nd2 y 22 34 nd2d2 y 48 72 nd3 y 20 33 nd3d2 y 44 70 nd4 y 15 26 nd4d2 y 32 53 nd5 y 11 19 nd5d2 y 23 40 nd6 y 22 34 nd6d2 y 45 69 nd8 y 22 34 nd8d2 y 45 69 nr2 y 11 17 nr2d2 y 24 35 nr3 y 6 9 nr3d2 y 14 21 nr4 y 5 7 nr4d2 y 10 14 nr5 y 22 34 nr5d2 y 45 70 nr6 y 22 34 nr6d2 y 70 104 nr8 y 21 33 nr8d2 y 46 71 or2 y 22 34 or2d2 y 45 69 or3 y 22 34 or3d3 y 71 106 or4 y 21 33 or4d2 y 45 68 or5 y 21 33 or5d2 y 45 68 xn2 y 22 34 xn2d2 y 46 70 xn3 y 22 34 xn3d3 y 69 104 xo2 y 22 34 xo2d2 y 46 70 xo3 y 22 34 xo3d3 y 70 106 ao21 y 11 16 ao21d2 y 22 32 ao211 y 6 9 ao211d2 y 13 20 ao22 y 10 15 ao22d2 y 45 70 ao22a y 10 15 ao22d2a y 45 69 ao222 y 5 8 ao222d2 y 46 70 ao222a y 7 11 ao222d2a y 46 70 ao33 y 9 14 ao33d2 y 46 70 ao333 y 2 5 ao333d2 y 46 71 oa21 y 11 16 oa21d2 y 24 34 oa211 y 11 16 oa211d2 y 23 34 oa22 y 10 15 oa22d2 y 21 32 cell name output pin maximum fanout kg80 KGM80
maximum fanouts introduction to kg80/KGM80 kg80/KGM80 1-16 sec asic oa22a y 11 16 oa22d2a y 24 35 oa2222 y 22 34 oa2222d2 y 46 71 dl1d2 y 48 90 dl1d4 y 103 148 dl2d2 y 50 90 dl2d4 y 104 155 dl3d2 y 49 89 dl3d4 y 102 177 dl4d2 y 48 87 dl4d4 y 98 146 dl5d2 y 48 87 dl5d4 y 98 147 dl10d2 y 50 90 dl10d4 y 105 154 iv y 22 34 ivd2 y 49 74 ivd3 y 76 114 ivd4 y 100 153 ivd6 y 149 229 ivd8 y 189 294 iva y 51 76 ivd2a y 105 161 ivd3a y 152 238 ivd4a y 191 296 ivcd11 all pins 21 34 ivcd13 y 19 31 yn 76 114 ivcd22 y 46 70 yn 49 74 ivcd26 y 40 64 yn 151 229 ivcd44 y 100 143 yn 100 153 ivt y 29 50 ivtd2 y 62 105 ivtd4 y 131 203 ivtd8 y 259 405 ivtn y 28 49 ivtnd2 y 61 103 ivtnd4 y 127 203 ivtnd8 y 252 405 cell name output pin maximum fanout kg80 KGM80 nid y 22 34 nid2 y 46 69 nid3 y 69 107 nid4 y 97 142 nid6 y 133 219 nid8 y 155 301 nit y 29 50 nitd2 y 62 106 nitd4 y 129 203 nitd8 y 259 399 nitn y 29 50 nitnd2 y 60 103 nitnd4 y 126 203 nitnd8 y 259 428 flip-flops fd1 all pins 22 34 fd1d2 all pins 46 71 fd1cs all pins 22 34 fd1csd2 q 45 69 qn 46 70 fd1s all pins 22 34 fd1sd2 all pins 46 71 fd1q q 22 34 fd1qd2 q 46 70 fd1x2 all pins 22 34 fd1x4 all pins 22 34 yfd1 q 21 33 qn 20 32 yfd1d2 q 43 68 qn 42 66 fd2 all pins 22 34 fd2d2 all pins 46 71 fd2cs all pins 22 34 fd2csd2 q 45 70 qn 46 71 fd2s all pins 22 34 fd2sd2 all pins 46 71 fd2q q 22 34 fd2qd2 q 46 70 fd2x2 all pins 22 34 fd2x4 all pins 22 34 yfd2 q 21 33 qn 20 32 cell name output pin maximum fanout kg80 KGM80
introduction to kg80/KGM80 maximum fanouts sec asic 1-17 kg80/KGM80 yfd2d2 q 44 68 qn 41 65 fd2t q 17 33 z1740 fd2td2 q 34 69 z3476 fd2tcs q 21 33 z2240 fd2tcsd2 q 43 67 z4276 fd2ts q 21 33 z2140 fd2tsd2 q 43 69 z4376 fd3 all pins 22 34 fd3d2 all pins 46 70 fd3cs all pins 22 34 fd3csd2 q 46 70 qn 45 69 fd3s all pins 22 34 fd3sd2 all pins 46 71 fd3q q 22 34 fd3qd2 q 46 70 fd3x2 all pins 22 34 fd3x4 all pins 22 34 yfd3 q 21 33 qn 19 30 yfd3d2 q 42 67 qn 39 62 fd4 all pins 22 34 fd4d2 all pins 46 70 fd4cs all pins 22 34 fd4csd2 q 46 70 qn 45 69 fd4s all pins 22 34 fd4sd2 all pins 46 70 fd4q q 22 34 fd4qd2 q 45 70 fd4x2 all pins 22 34 fd4x4 all pins 22 34 yfd4 q 20 32 qn 19 30 cell name output pin maximum fanout kg80 KGM80 yfd4d2 q 43 68 qn 38 61 fd5 all pins 22 34 fd5d2 all pins 46 70 fd5s all pins 22 34 fd5sd2 all pins 46 70 fd5x4 all pins 22 34 fd6 all pins 22 34 fd6d2 all pins 46 70 fd6s all pins 22 34 fd6sd2 all pins 46 70 fd7 all pins 22 34 fd7d2 all pins 46 70 fd7s all pins 22 34 fd7sd2 all pins 46 70 fd8 all pins 22 34 fd8d2 all pins 46 70 fd8s all pins 22 34 fd8sd2 all pins 46 70 fds2 all pins 22 34 fds2d2 all pins 46 70 fds2cs all pins 22 34 fds2csd2 all pins 46 70 fds2s all pins 22 34 fds2sd2 q 46 71 qn 46 70 fds3 all pins 22 34 fds3d2 all pins 45 70 fg1 all pins 22 34 fg1x4 all pins 22 34 fg2 all pins 22 34 fg2x4 all pins 22 34 fj1 all pins 22 34 fj1d2 all pins 46 70 fj1s all pins 22 34 fj1sd2 all pins 46 71 fj2 all pins 22 34 fj2d2 all pins 46 70 fj2s all pins 22 34 fj2sd2 all pins 46 70 fj4 all pins 22 34 fj4d2 all pins 45 70 fj4s all pins 22 34 cell name output pin maximum fanout kg80 KGM80
maximum fanouts introduction to kg80/KGM80 kg80/KGM80 1-18 sec asic fj4sd2 all pins 45 70 ft2 all pins 22 34 ft2d2 all pins 46 70 ft3 all pins 22 34 ft3d2 all pins 46 70 latches ld1 all pins 22 34 ld1d2 all pins 46 71 ld1s all pins 22 34 ld1sd2 all pins 46 71 ld1q q 22 34 ld1qd2 q 44 70 ld1x4 all pins 22 34 ld1x4d2 all pins 46 70 yld1 q 20 32 qn 22 34 yld1d2 q 41 66 qn 44 69 ld1a q 22 34 ld1b all pins 21 32 ld2 all pins 22 34 ld2d2 all pins 46 70 ld2q q 22 34 ld2qd2 q 45 70 yld2 q 19 30 qn 21 33 yld2d2 q 39 62 qn 44 68 ld3 all pins 22 34 ld3d2 all pins 45 70 ld4 all pins 22 34 ld4d2 q 45 70 qn 44 70 ld5 all pins 22 34 ld5d2 all pins 46 70 ld5s all pins 22 34 ld5sd2 all pins 46 71 ld5x4 all pins 22 34 ld5x4d2 all pins 46 70 ld6 all pins 22 34 ld6d2 all pins 46 70 ld7 all pins 22 34 ld7d2 all pins 45 70 cell name output pin maximum fanout kg80 KGM80 ld8 all pins 22 34 ld8d2 q 45 70 qn 44 70 lds2 all pins 22 34 lds6 all pins 22 34 ls0 all pins 21 34 ls0d2 all pins 46 70 ls1 all pins 10 15 ls2 all pins 21 33 bus holder busholder y 10,000 10,000 internal clock drivers ck2 y fig 1-17 (a) fig 1-18 (a) ck4 y fig 1-17 (b) fig 1-18 (b) ck6 y C fig 1-18 (c) ck8 y fig 1-17 (c) fig 1-18 (d) ck12 y fig 1-17 (d) C decoders dc4 all pins 22 34 dc4i all pins 22 34 dc8i all pins 22 34 adders fa all pins 22 34 fad2 all pins 46 70 ha all pins 22 34 had2 all pins 46 71 multiplexers mx2 y 22 34 mx2d3 y 69 106 mx2x4 all pins 22 34 ymx2 y 22 34 ymx2d2 y 44 69 mx2i yn 11 16 mx2id2 yn 46 70 mx2ia yn 11 16 mx2id2a yn 46 70 mx2ix4 all pins 15 22 mx3i yn 22 34 mx3id2 yn 46 70 mx4 y 22 34 mx4d2 y 45 69 ymx4 y 22 34 ymx4d2 y 45 70 cell name output pin maximum fanout kg80 KGM80
introduction to kg80/KGM80 maximum fanouts sec asic 1-19 kg80/KGM80 i/o cells the maximum fanouts for 5v and 3.3v i/o cells are as follows when the rise and fall times of the input signal is 0.40ns. the graphs for fanout vs. frequency curve of kg80/KGM80 internal/input clock drivers are shown in the next page. table 1-14. maximum fanouts of i/o cells (when t r /t f = 0.40ns) mx5 y 22 34 mx5d2 y 46 70 mx8 y 22 34 mx8d2 y 44 67 ymx8 y 22 34 ymx8d2 y 45 70 cell name output pin maximum fanouts kg80 KGM80 pic po 43 67 y 111 216 picd po 43 67 y 114 222 picu po 43 67 y 115 205 pil pild po 43 C y 132 C pilu po 43 C y 133 C pis po 43 67 y 88 287 pisd po 43 67 y 86 237 pisu po 43 67 y 86 329 pitb po 43 C y87C plic po 32 C y 141 C plicd po 32 C y 152 C plicu po 32 C y 145 C cell name output pin maximum fanout kg80 KGM80 plis po 32 C y 168 C plisd po 32 C y 174 C plisu po 32 C y 118 C phic po C 55 y C 220 phicd po C 55 y C 223 phicu po C 55 y C 216 phil po C 55 y C 211 phild po C 55 y C 244 philu po C 55 y C 210 phis po C 55 y C 204 phisd po C 55 y C 225 phisu po C 55 y C 227 phit phitd po C 55 y C 225 phitu po C 55 y C 232 psckdab2 y fig 1-17 (a) fig 1-18 (a) psckdab4 y fig 1-17 (b) fig 1-18 (b) psckdab6 y C fig 1-18 (c) psckdab8 y fig 1-17 (c) fig 1-18 (d) psckdab12 y fig 1-17 (d) C psoscm1 psoscm2 pady 530 1214 yn 527 1198 psoscm3 pady 1052 2430 yn 264 600 psoscm4 pady 2022 4850 yn 2337 5347 psoscm5 pady 3011 7359 yn 524 1194 psoscm6 pady 4025 9982 yn 2335 5344 cell name output pin maximum fanouts kg80 KGM80
maximum fanouts introduction to kg80/KGM80 kg80/KGM80 1-20 sec asic figure 1-17. fanout (sl) vs. frequency curve of kg80 clock drivers figure 1-18. fanout (sl) vs. frequency curve of KGM80 clock drivers (a) psckdab2 ck2 (b) psckdab4 ck4 (c) psckdab8 ck8 (d) psckdab12 ck12 (a) psckdab2 ck2 (b) psckdab4 ck4 (c) psckdab6 ck6 (d) psckdab8 ck8
introduction to kg80/KGM80 product line-up sec asic 1-21 kg80/KGM80 product line-up (the information below is preliminar y, and can be changed or added by sec asic.) table 1-15. kg80/KGM80 masterslices (100 m m pad pitch) notes: 1. usable gates are estimated; the actual number of usable gates is design-dependent. 2. i/o pads can be used as v dd /v ss pads. 3. each clock driver cell occupies one i/o slot. 4. total pad count includes the corner power pads. packages (the information below is preliminar y, therefore, when you choose a package type for your product, or if you want to use the other types of packages, please contact to sec asic.) table 1-16. package options note : o-marked packages are fully guaranteed by sec asic, and a-marked are available but not guaranteed since they are not completed passed bonding rule test. device total gates usable gates total pads dlm tlm kg8563d 56,950 22,800 31,300 100 kg8144d 145,306 51,000 73,000 160 kg8244d 242,604 73,000 109,000 208 kg8444d 443,190 111,000 177,000 280 type dip sdip sop plcc qfp pin master 2 4 2 8 4 0 4 2 2 4 2 8 3 0 3 2 4 0 4 2 4 8 5 4 6 4 2 8 3 2 2 8 3 2 4 4 6 8 8 4 4 4 4 8 6 0 6 4 8 0 1 0 0 1 2 8 1 3 2 1 6 0 2 0 8 2 4 0 kg8563d a a a o o o o o a a a a a a a o o o a a o o o o o o a kg8144d o a o a a a o a o o o o a o o o o a o kg8244d o a o o a o o o o o o o kg8444d o o o o o o o 0
dedicated corner vdd/vss pads introduction to kg80/KGM80 kg80/KGM80 1-22 sec asic dedicated corner v dd /v ss pads the corner pads shown in the following ?gure are well-suited for double bonding purposes. pad 1 and pad 2 can be bonded to the same package pin. unlike normal i/o pads, these pads can only be used for v dd /v ss listed in table 1-17. use of corner pads. figure 1-19. v dd /v ss corner pads notes: 1. there is no dedicated corner vssi pad. therefore, internal v ss must be supplied using i/o pad type cell. 2. corner pads are used to reduce the power/ground noise when some parts of the design cause noise problem especially while the other parts keep quiet. table 1-17. use of corner pads 1 2 3 4 8 7 6 5 9 10 11 12 16 15 14 13 1 vsso 2 vsso 3 vssi 4 vssi 5 vddi 6 vddi 7 vdd5o 8 vdd5o 9 vdd3o 10 vdd3o 11 vssi 12 vssi 13 vddi 14 vddi 15 vsso 16 vsso
introduction to kg80/KGM80 external design interface considerations sec asic 1-23 kg80/KGM80 external design interface considerations this section brie?y describes what you should consider when chips interface with outside world especially for a noise protection. input buffer usually there are three types of input receivers in asic libraries; ttl input buffer, cmos input buffer, and various schmitt trigger input buffers. ttl input buffer has relatively poor noise characteristics because of its shifted logic threshold voltage. cmos input buffer is better than ttl against a noise because the logic threshold voltage is near 2.5volt. if an input signal has relatively large noise spikes, it could cause an unwanted input signal. when an input signal is very noisy, the noise can be ?ltered by using a schmitt trigger input buffer. as shown in figure 1-20. effect of schmitt trigger input buffer, schmitt trigger input buffers have two different input thresholds for positive- and negative-going signals. this hysteresis between positive- and negative-going voltage signals can ?lter a noisy signal to a wanted one. according to applications, the most suitable one can be chosen among the various schmitt trigger input buffers having different levels of threshold voltage. figure 1-20. effect of schmitt trigger input buffer output pad cell as incoming signals to a chip have a noise, the noise can also be induced by the operation of the chip itself. there are several sources of a noise, but the greatest singular source of a noise is the switching of an output with high capacitive load. (a) input signal with heavy noise (b) after ttl input buffer of which logic (c) after schmitt trigger of which positive- and v t v t v t vin vout vin vout vt+ vtC vt unwanted signal caused by noise noise spike noise spike threshold is vt negative-going threshold voltages are vt+ and vtC
external design interface considerations introduction to kg80/KGM80 kg80/KGM80 1-24 sec asic figure 1-21. simple model of output pad cell figure 1-21. simple model of output pad cell shows the simple model of an output driver considering the external interface. l1 and l2 are parasitic inductances of the package and c l is an output load. vout will fall as vin rises and the current i ?ows through n-transistor discharging the loaded charge (v dd c l ). the details of this operations are described in figure 1-22. ground bounce phenomenon. the important phenomenon which can be observed in this tgure is that the voltage level vn shifts relative to the system ground. vn is the ground of the chip. this phenomenon is called as a ground bounce that is the chip reference shift caused by the external inductance and the transient current ?ow to the ground. the amount of voltage level shifted by the ground bounce is vn = -l (di / dt) when the output driver makes a low-to-high transition, the similar noise problem is generated on the power. figure 1-22. ground bounce phenomenon i c l : bonding pad l2 l1 vin system ground system power supply vout r l (a) vin (b) vout (c) i (d) vn t t t t i = C c l (dvout / dt) vn = l1 (di / dt)
introduction to kg80/KGM80 external design interface considerations sec asic 1-25 kg80/KGM80 the following graphs show typical ac characteristics of non-slew and slew-rate output drives in kg80/KGM80. using the slew-rate control, you can reduce the switching noise. figure 1-23. ac characteristics of non-slew and slew rate output drives 1 w input v dd 2nh 1 w 2nh pa d 2nh 1 w ground bouncing voltage vs. time 0.000 time 2.500n 7.500n 12.50n 17.50n 20.00n volt -13.81m 0.000 12.50m 25.00m 37.50m 50.00m 62.50m 75.00m 86.43m pob8 pob8sm 0.000 time 2.500n 7.500n 12.50n 17.50n 20.00n volt -36.43m -25.00m 0.000 25.00m 50.00m 75.00m 100.0m 125.0m 140.7m pob12 pob12sm pob12sh < test condition >
external design interface considerations introduction to kg80/KGM80 kg80/KGM80 1-26 sec asic ground bouncing voltage vs. time 0.000 time 2.500n 7.500n 12.50n 17.50n 20.00n volt -88.49m -50.00m 0.000 50.00m 100.0m 150.0m 200.0m 220.4m pob16 pob16sm pob16sh 0.000 time 2.500n 7.500n 12.50n 17.50n 20.00n volt -225.7m -100.0m 0.000 100.0m 200.0m 300.0m 370.7m pob24 pob24sm pob24sh 0.000 time 2.500n 7.500n 12.50n 17.50n 20.00n volt -168.0m -100.0m -50.00m -7.451n 50.00m 100.0m 150.0m 200.0m 250.0m 317.2m pob20 pob20sm pob20sh
introduction to kg80/KGM80 external design interface considerations sec asic 1-27 kg80/KGM80 simultaneous switching outputs (ssos) if several output drivers switch from high to low simultaneously, the ground bouncing level becomes quite large because the current ?owing through the inductance l is the total sum of the transient current of each output driver. the amount of total current and the level of ground bounce are proportional to the number of ssos. this ground bounce can cause two types of problems, a noise margin reduction and a generation of noise spike on the output pad. noise margin reduction the ground bounce can cause a noise margin reduction when the same ground bus is used for both input buffers and output drivers as shown in figure 1-25. the figure of ssos. the noise margin reduction can be explained using the circuit in the same ?gure. as you can see, if outputs switch from high to low simultaneously, it results in a ground bounce or the rise of the chip ground level relative to system ground. the rise appears as the input voltage vin_a is below v ih causing false triggering of the input buffer. vin is, in this case, not the same as vin_a. note that vin is measured relative to the system ground, while vin_a is measured relative to the local device ground. this phenomenon is shown in figure 1-24. noise margin reduction due to ssos. for a low-to-high transition, it is the low input levels (v il ) that are affected. figure 1-24. noise margin reduction due to ssos noise spike generation on stable output if input and output power buses are separated, the problem of a noise margin reduction in the input buffer can be solved. however, ground bounce can cause another problem in spite of using separated power and ground bus. the figure 1-26. noise spike induced by ground bounce shows a common octal driver application where ground bounce spikes will be observable on the one stable output. if the spike is considered as high by another chip, this ground bounce may upset that operation of interfacing device or cause system logic errors. vin_a v ih v il v ss 2.0v 0.8v figure 1-25. the figure of ssos i c l i c l i c l i c l nxi vin vin_a system ground input receiver ssos chip ground (vn) chip power internal logic
external design interface considerations introduction to kg80/KGM80 kg80/KGM80 1-28 sec asic for example, suppose c l = 100pf, v dd = 3.3volt, t f = 5ns. from figure 1-22. ground bounce phenomenon, the maximum current ?ow occurs at time 0.5 t f . then approximately, i = c l (dv / dt) @ c l ( d v / d t), and i (max) = 100 10 -12 {5 / (2.5 10 -9 )} = 200 [ma]. if the number of ssos is 5, and l is 4nh, vn = l (di / dt) n @ l ( d i / d t) n by approximation, vn (max) = 4 10 -9 {0.200 / (2.5 10 -9 )} 5 = 1.60 [volt]. from this calculation, 1.60v of noise spike is expected. this is about logic threshold voltage of ttl. this numerical estimate clearly shows that power bus noise control is one of the fundamental problems in a high-speed cmos vlsi design. it is an important design consideration to prevent the noise from affecting the integrity of the logic operation of a chip. figure 1-26. noise spike induced by ground bounce how to protect ground bounce? the fundamental solution to the ground bounce problem is to reduce the inductance of the package. however, in the boundary of a given packaging technology, the following guidelines can be used for reducing ground bounce: (1) if possible, use separate power and ground buses for input buffers and output drivers. (2) the number of ground and power pads should not be less than the required number of pads. (3) if the design is not so much sensitive to speed, use slew rate control, i.e., increase switching time, to reduce the value of di / dt of an output driver. sec supports two levels of slew rate controlled output buffers, sm and sh. you can see this effect in the following ?gure. figure 1-27. effect on reducing peak current with slew-rate control (4) if you cannot use a slew rate cell because of the speed requirement, you can stagger the output driver as shown in figure 1-28. effect on reducing peak current with staggering output drivers. this is not a general-purpose solution. it makes sense only when special relief in timing requirements exists from a system architecture. noise spike l i t t t t 3 ssos 3 ssos v i v i
introduction to kg80/KGM80 crystal oscillator considerations sec asic 1-29 kg80/KGM80 figure 1-28. effect on reducing peak current with staggering output drivers (5) high-drive outputs should be close to v ss pins. ssos should be placed particularly close to v ss pins. (6) ssos should be appropriately placed in groups belonging to given v ss pins. (7) noise-sensitive signals such as clock, asynchronous clear and preset should be located away from ssos and high-drive outputs. also, assign them to pins with low inductance and resistance, preferably near v ss , if one is available away from ssos or high-drive outputs. (8) place ssos on low inductance pins, such as those located on the inner rows or middle positions of pgas. (9) clock, preset and clear inputs must not be placed on the corners of a package, especially when the array is packaged in dip. (10)output signals to be used as clock, preset or clear for other devices must be kept away from ssos and close to v ss pin. these guidelines assist you in choosing the best package(s) for the application. furthermore, the recommendations about pinout results in reliable and predictable devices that minimizes harmful dc and ac effects on the system. crystal oscillator considerations overview kg80/KGM80 contains a circuit commonly referred to as an on-chip oscillator. the on-chip circuit itself is not an oscillator but an ampli?er which is suitable for being used as the ampli?er part of a feedback oscillator. with proper selection of off-chip components, this oscillator circuit performs better than any other types of clock oscillators. it is very important to select suitable off-chip components to work with the on-chip oscillator circuitry. it should be noted, however, that sec cannot assume the responsibility of writing speci?cations for the off-chip components of the complete oscillator circuit, nor of guaranteeing the performance of the ?nished design in production, anymore than a transistor manufacturer, whose data sheets show a number of suggested ampli?er circuits, can assume responsibility for the operation, in production, of any of them. we are often asked why we dont publish a list of required crystal or ceramic resonator speci?cations, and recommend values for the other off-chip components. this has been done in the past, but sometimes with consequences that were not intended. suppose we suggest a maximum crystal resistance of 30ohms for some given frequency. then your crystal supplier tells you the 30ohm crystals are going to cost twice as much as 50ohm crystals. fearing that sec will not guarantee operation with 50ohm crystals, you order the expensive ones. in fact, sec guarantees only what is embodied within an sec product. besides, there is no reason why 50ohm crystals couldnt be used, if the other off-chip components are suitably adjusted. should we recommend values for the other off-chip components? should we do for 50ohm crystals or 30ohm crystals? with respect to what should we optimize their selection? should we minimize start-up time or maximize frequency stability? in many applications, neither start-up time nor frequency stability is particularly critical, and our recommendations are only restricting your system to unnecessary tolerances. it all depends on the application. t t t t 3 ssos v i v i
crystal oscillator considerations introduction to kg80/KGM80 kg80/KGM80 1-30 sec asic oscillator design considerations asic designers have a number of options for clocking the system. the main decision is whether to use the on-chip oscillator or an external oscillator. if the choice is to use the on-chip oscillator, what kinds of external components are to use an external oscillator, what type of oscillator would it be? the decisions have to be based on both economic and technical requirements. in this section we will discuss some of the factors that should be considered. on-chip oscillator in most cases, the on-chip ampli?er with the appropriate external components provides the most economical solution to the clocking problem. exceptions may arise in server environments when frequency tolerances are tighter than about 0.01%. the external components that commonly used for cmos gate oscillator are a positive reactance (normal crystal oscillator), two capacitors, c1 and c2, and two resistor rf and rx as shown in the ?gure below. figure 1-29. cmos oscillator crystal specifications speci?cations for an appropriate crystal are not very critical, unless the frequency is. any fundamental-mode crystal of medium or better quality can be used. we are often asked what maximum crystal resistance should be speci?ed. the best answer to that question is the lower the better, but use what is available. the crystal resistance will have some effect on start-up time and steady-state amplitude, but not so much that it cant be compensated for by appropriate selection of the capacitances, c1 and c2. similar questions are asked about speci?cations of load capacitance and shunt capacitance. the best advice we can give is to understand what these parameters mean and how they affect the operation of the circuit (that being the purpose of this application note), and then to decide for yourself if such speci?cations are meaningful in your frequency tolerances are tighter than about 0.1%. part of the problem is that crystal manufacturers are accustomed to talking ppm tolerances with radio engineers and simply wont take your order until youve ?lled out their list of frequency tolerance requirements, both for yourself and to the crystal manufacturer. dont pay for 0.003% crystals if your actual frequency tolerance is 1%. oscillation frequency the oscillation frequency is determined 99.5% by the crystal and up to about 0.5% by the circuit external to the crystal. the on-chip ampli?er has little effect on the frequency, which is as it should be, since the ampli?er parameterizes temperature and process dependent. the in?uence of the on-chip ampli?er on the frequency is by means of its input and output (pin-to-ground) capacitances, which parallel c1 and c2, and the pada-to-pady (pin-to-pin) capacitance, which parallels the crystal. the input and pin-to-pin capacitances are about 7pf each. internal phase deviations capacitance of 25 to 30pf. these deviations from the ideal have less effect in the positive reactance oscillator (with the inverting ampli?er) than in a comparable series resonant oscillator (with the non-inverting ampli?er) for two reasons: ?rst, the effect of the output capacitor; second, the positive reactance oscillator is less sensitive, frequency-wise, to such phase errors. c1 c2 rx rf pada pady feedback inside of a chip amplifier
introduction to kg80/KGM80 crystal oscillator considerations sec asic 1-31 kg80/KGM80 c1 / c2 selection optimal values for the capacitors c1 and c2 depend on whether a quartz crystal or ceramic resonator is being used, and also on application-speci?c requirements on start-up time and frequency tolerance. start-up time is sometimes more critical in microcontroller systems than frequency stability, because of various reset and initialization requirements. less commonly, accuracy of the oscillator frequency is also critical, for example, when the oscillator is being used as a time base. as a general rule, fast start-up and stable frequency tend to pull the oscillator design in opposite directions. considerations of both start-up time and frequency stability over temperature suggest that c1 and c2 should be about equal and at least 20pf. (but they dont have to be either.) increasing the value of these capacitances above some 40 or 50pf improves frequency stability. it also tends to increase the start-up time. these is a maximum value (several hundred ph, depending on the value of r1 of the quartz or ceramic resonator) above which the oscillator wont start up at all. if the on-chip ampli?er is a simple inverter, the user can select values for c1 and c2 between some 20 and 100pf, depending on whether start-up time or frequency stability is the more critical parameter in a speci?c application. rf / rx selection a cmos inverter might work better in this application since a large rf (1mega-ohm) can be used to hold the inverter in its linear region. logic gates tend to have a fairly low output resistance, which testabilizes the oscillator. for that reason a resistor rx (several k-ohm) is often added to the feedback network, as shown in figure 1-29. cmos oscillator. at higher frequencies a 20 or 30pf capacitor is sometimes used in the rx position, to compensate for some of the internal propagation delay. pin capacitance internal pin-to-ground and pin-to-pin capacitances, and pada and pady have some effect on the oscillator. these capacitances are normally taken to be in the range of 5 to 10pf, but they are extremely dif?cult to evaluate. any measurement of one such capacitance necessarily include effects from the others. one advantage of the positive reactance oscillator is that the pin-to ground cap. is paralleled by an external bulk capacitance, so a precise determination of their value is unnecessary. we would suggest that there is little justi?cation for more precision than to assign them a value of 7pf (pada-to-ground and pada-to-pady). this value is probably not in error by more than 3 or 4pf. the pady-to-ground cap. is not entirely a pin capacitance, but more like an equivalent output capacitance of some 25 to 30pf, having to include the effect of internal phase delays. this value varies to some extent with temperature, process, and frequency. placement of components noise glitches arising at pada or pady pins at the wrong time can cause a miscount in the internal clock-generating circuitry. these kinds of glitches can be produced through capacitive coupling between the oscillator components and pcb traces carrying digital signals with fast rise and fall times. for this reason, the oscillator components should be mounted close to the chip and have short, direct traces to the pada, pady, and v ss pins. if possible, use dedicated v ss and v dd pin for only crystal feedback ampli?er.
crystal oscillator considerations introduction to kg80/KGM80 kg80/KGM80 1-32 sec asic troubleshooting oscillator problems the ?rst thing to consider in case of dif?culty is that there may be signi?cant differences in stray caps between the test jig and the actual application, particularly if the actual application is on a multi-layer board. noise glitches, that are not present in the test jig but are in the application board, are another possibility. capacitive coupling between the oscillator circuitry and other signal has already been mentioned as a source of miscounts in the internal clocking circuitry. inductive coupling is also doubtful, if there is strong current nearby. these problems are a function of the pcb layout. surrounding oscillator components with quit traces (for example, vcc and ground) will alleviate capacitive coupling to signals having fast transition time. to minimize inductive coupling, the pcb layout should minimize the areas of the loops formed by oscillator components. the loops demanding to be checked are as follows: pada through the resonator to pady; pada through c1 to the v ss pin; pady through c2 to the v ss pin. it is not unusual to ?nd that the ground ends of c1 and c2 eventually connect up to the v ss pin only after looping around the farthest ends of the board. not good. finally, it should not be overlooked that software problems sometimes imitate the symptoms of a slow-starting oscillator or incorrect frequency. never underestimate the perversity of a software problem.
electrical characteristics 2
contents dc electrical characteristics ......................................................................................... 2-1 input buffer dc curves.................................................................................................. 2-3 output drive capabilities ............................................................................................... 2-5
electrical characteristics dc electrical characteristics sec asic 2-1 kg80/KGM80 dc electrical characteristics v dd = 5v 5%, t a = 0 to 70 c notes: 1. type b1 means 1ma output driver cells, and type b24 means 24ma output driver cells. 2. this value depends on the customer design. symbol parameter condition min max unit v ih high level input voltage v ttl interface 2.0 ttl schmitt trigger 2.1 cmos interface 0.7v dd cmos schmitt trigger 4.0 v il low level input voltage v ttl interface 0.8 ttl schmitt trigger 0.8 cmos interface 0.3v dd cmos schmitt trigger 1.0 i ih high level input current m a input buffer v in = v dd e10 10 input buffer with pull-down 10 200 i il low level input current m a input buffer v in = v ss e10 10 input buffer with pull-up e200 e10 v oh high level output voltage v type b1 to b24 note1 i oh = e1 m av dd e 0.05 type b1 i oh = e1ma 2.4 type b2 i oh = e2ma type b4 i oh = e4ma type b8 i oh = e8ma type b12 i oh = e12ma type b16 i oh = e16ma type b20 i oh = e20ma type b24 i oh = e24ma v ol low level output voltage v type b1 to b24 i ol = 1 m a 0.05 type b1 i ol = 1ma 0.4 type b2 i ol = 2ma type b4 i ol = 4ma type b8 i ol = 8ma type b12 i ol = 12ma type b16 i ol = 16ma type b20 i ol = 20ma type b24 i ol = 24ma i oz tri-state output leakage current v out =v ss or v dd e10 10 m a i dd quiescent supply current v in = v ss or v dd 100 note2 m a
dc electrical characteristics electrical characteristics kg80/KGM80 2-2 sec asic v dd = 3.3v 10%, t a = 0 to 70 c symbol parameter condition min max unit v ih high level input voltage v cmos interface 0.7v dd cmos schmitt trigger 2.1 v il low level input voltage v cmos interface 0.3v dd cmos schmitt trigger 0.8 i ih high level input current m a input buffer v in = v dd e10 10 input buffer with pull-down 10 200 i il low level input current m a input buffer v in = v ss e10 10 input buffer with pull-up e200 e10 v oh high level output voltage v type b1 to b16 i oh = e1 m av dd e 0.05 type b1 i oh = e0.5ma 2.4 type b2 i oh = e1ma type b4 i oh = e2ma type b6 i oh = e3ma type b8 i oh = e4ma type b10 i oh = e5ma type b12 i oh = e6ma type b16 i oh = e8ma v ol low level output voltage v type b1 to b16 i ol = 1 m a 0.05 type b1 i ol = 1ma 0.4 type b2 i ol = 2ma type b4 i ol = 4ma type b6 i ol = 6ma type b8 i ol = 8ma type b10 i ol = 10ma type b12 i ol = 12ma type b16 i ol = 16ma absolute maximum ratings recommended operating conditions symbol parameter ratingtd unit v dd dc supply voltage C0.3 to 7 v v in dc input voltage C0.3 to v dd + 0.3 i in dc input current 10 ma t stg storage temperature e40 to 125 c symbol parameter rating unit v dd dc supply voltage 5v 4.75 to 5.25 v 3.3v 3.0 to 3.6 t a commercial temperature 0 to 70 c industrial temperature e40 to 85
electrical characteristics input buffer dc curves sec asic 2-3 kg80/KGM80 input buffer dc curves input buffer transfer curves v dd = 5v, t a = 25 c, typical process v dd = 3.3v, t a = 25 c, typical process input clock drivers transfer curves v dd = 5v, t a = 25 c, typical process v dd = 3.3v, t a = 25 c, typical process 0.0 vin [v] 1.0 2.0 3.0 4.0 5.0 vout [v] 0.0 1.0 2.0 3.0 4.0 5.0 cmos 0.0 vin [v] 1.0 2.0 3.0 4.0 5.0 vout [v] 0.0 1.0 2.0 3.0 4.0 5.0 ttl 0.0 vin [v] 1.0 2.0 3.0 4.0 5.0 vout [v] 0.0 1.0 2.0 3.0 4.0 5.0 cmos schmitt trigger 0.0 vin [v] 1.0 2.0 3.0 4.0 5.0 vout [v] 0.0 1.0 2.0 3.0 4.0 5.0 ttl schmitt trigger cmos cmos schmitt trigger 0.0 vin [v] 1.0 2.0 3.0 3.3 vout [v] 0.0 1.0 2.0 3.0 4.0 5.0 0.0 vin [v] 1.0 2.0 3.0 3.300 vout [v] 0.0 1.0 2.0 3.0 4.0 5.0 0.0 vin [v] 1.0 2.0 3.0 4.0 5.0 vout [v] 0.0 1.0 2.0 3.0 4.0 5.0 0.0 vin [v] 1.0 2.0 3.0 4.0 5.0 vout [v] 0.0 1.0 2.0 3.0 4.0 5.0 0.0 vin [v] 1.0 2.0 3.0 4.0 5.0 vout [v] 0.0 1.0 2.0 3.0 4.0 5.0 0.0 vin [v] 1.0 2.0 3.0 4.0 5.0 vout [v] 0.0 1.0 2.0 3.0 4.0 5.0 cmos ttl cmos schmitt trigger ttl schmitt trigger cmos cmos schmitt trigger 0.0 vin [v] 0.5 1.0 1.5 2.0 2.5 3.0 3.3 vout [v] 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.3 0.0 vin [v] 0.5 1.0 1.5 2.0 2.5 3.0 3.3 vout [v] 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.3
input buffer dc curves electrical characteristics kg80/KGM80 2-4 sec asic input buffer pull-down/pull-up characteristics v dd = 5v, t a = 25 c, typical process v dd = 3.3v, t a = 25 c, typical process 0.0 vin [v] 1.0 2.0 3.0 4.0 5.0 ids [ua] 0.0 10.0 20.0 30.0 40.0 51.1 0.0 vin [v] 1.0 2.0 3.0 4.0 5.0 ids [ua] 0.0 10.0 20.0 30.0 40.0 50.1 pull-down pull-up 0.0 vin [v] 1.0 2.0 3.0 3.3 ids [ua] 0.0 2.5 5.0 7.5 10.0 12.5 15.0 18.1 0.0 vin [v] 1.0 2.0 3.0 3.3 ids [ua] 0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 19.0 pull-down pull-up
electrical characteristics output drive capabilities sec asic 2-5 kg80/KGM80 output drive capabilities iv characteristics v dd = 5v, t a = 25 c, typical process v dd = 3.3v, t a = 25 c, typical process 0.0 vout [v] 1.0 2.0 3.0 4.0 5.0 ioh [ma] 0.0 25 50 75 100 125 150 157 pob1 pob2 pob4 pob8 pob12 pob16 pob20 pob24 p-tr characteristics 0.0 vout [v] 1.0 2.0 3.0 4.0 5.0 iol [ma] 0.0 25 50 75 100 125 150 175 185 pob1 pob2 pob4 pob8 pob12 pob16 pob20 pob24 n-tr characteristics 0.0 vout [v] 1.0 2.0 3.0 3.3 ioh [ma] 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 75.8 plob1 plob2 plob4 plob6 plob8 plob12 plob16 p-tr characteristics 0.0 vout [v] 1.0 2.0 3.0 3.3 iol [ma] 0.0 12.5 25.0 37.5 50.0 62.5 75.0 87.5 100 109 plob1 plob2 plob4 plob6 plob8 plob12 plob16 n-tr characteristics
internal macrocells 3
contents overview ............................................................................................................................ 3-1 summary tables................................................................................................................. 3-2 logic cells.......................................................................................................................... 3-7 flip-flops............................................................................................................................ 3-170 latches............................................................................................................................... 3-359 bus holder.......................................................................................................................... 3-459 internal clock drivers ......................................................................................................... 3-460 decoders ............................................................................................................................ 3-463 adders ................................................................................................................................ 3-477 multiplexers ........................................................................................................................ 3-486
internal macrocells overview sec asic 3-1 kg80/KGM80 overview the third chapter contains data sheets of logic cells, ?ip-?ops, latches, bus holder, internal clock drivers, decoders, adders and multiplexers. the electrical characteristics of each cell follows its basic cell data. summary tables in the following pages list the whole kg80/KGM80 internal macrocells by the type and show their reference page numbers for your convenience. moreover, you can ?nd the more detailed description tables on the leading pages of each category.
summary tables internal macrocells kg80/KGM80 3-2 sec asic summary tables logic cells cell type cell name page and cell ad2/ad2d2 3-11 ad3/ad3d3 3-13 ad4/ad4d2 3-16 ad5/ad5d2 3-19 nand cell nd2/nd2d2 3-22 nd3/nd3d2 3-24 nd4/nd4d2 3-27 nd5/nd5d2 3-30 nd6/nd6d2 3-33 nd8/nd8d2 3-38 nor cell nr2/nr2d2 3-43 nr3/nr3d2 3-45 nr4/nr4d2 3-48 nr5/nr5d2 3-51 nr6/nr6d2 3-54 nr8/nr8d2 3-59 or cell or2/or2d2 3-64 or3/or3d3 3-66 or4/or4d2 3-69 or5/or5d2 3-72 exclusive-nor cell xn2/xn2d2 3-76 xn3/xn3d3 3-78 exclusive-or cell xo2/xo2d2 3-81 xo3/xo3d3 3-83 combinational cell of and and nor ao21/ao21d2 3-86 ao211/ao211d2 3-89 ao22/ao22d2 3-92 ao22a/ao22d2a 3-95 ao222/ao222d2 3-98 ao222a/ao222d2a 3-103 ao33/ao33d2 3-106 ao333/ao333d2 3-111
internal macrocells summary tables sec asic 3-3 kg80/KGM80 flip-flops combinational cell of or and nand oa21/oa21d2 3-116 oa211/oa211d2 3-119 oa22/oa22d2 3-122 oa22a/oa22d2a 3-125 oa2222/oa2222d2 3-128 delay cell dl(1/2/3/4/5/10)d2/dl(1/2/3/4/5/10)d4 3-133 inverter iv/ivd2/ivd3/ivd4/ivd6/ivd8 3-139 iva/ivd2a/ivd3a/ivd4a 3-143 ivcd(11/13)/ivcd(22/26)/ivcd44 3-146 inverting tri-state buffer ivt/ivtd2/ivtd4/ivtd8 3-150 ivtn/ivtnd2/ivtnd4/ivtnd8 3-154 non-inverting buffer nid/nid2/nid3/nid4/nid6/nid8 3-158 nit/nitd2/nitd4/nitd8 3-162 nitn/nitnd2/nitnd4/nitnd8 3-166 cell type cell name page d flip-flop fd1/fd1d2 3-173 fd1cs/fd1csd2 3-176 fd1s/fd1sd2 3-180 fd1q/fd1qd2 3-183 fd1x2 3-185 fd1x4 3-187 yfd1/yfd1d2 3-190 d flip-flop with reset fd2/fd2d2 3-193 fd2cs/fd2csd2 3-196 fd2s/fd2sd2 3-200 fd2q/fd2qd2 3-203 fd2x2 3-205 fd2x4 3-208 yfd2/yfd2d2 3-211 d flip-flop with reset, tri-state output fd2t/fd2td2 3-214 fd2tcs/fd2tcsd2 3-217 fd2ts/fd2tsd2 3-222 cell type cell name page
summary tables internal macrocells kg80/KGM80 3-4 sec asic d flip-flop with set fd3/fd3d2 3-226 fd3cs/fd3csd2 3-229 fd3s/fd3sd2 3-233 fd3q/fd3qd2 3-236 fd3x2 3-238 fd3x4 3-241 yfd3/yfd3d2 3-244 d flip-flop with reset, set fd4/fd4d2 3-247 fd4cs/fd4csd2 3-251 fd4s/fd4sd2 3-257 fd4q/fd4qd2 3-261 fd4x2 3-264 fd4x4 3-267 yfd4/yfd4d2 3-272 d flip-flop with negative edge trigger fd5/fd5d2 3-275 fd5s/fd5sd2 3-278 fd5x4 3-281 fd6/fd6d2 3-284 fd6s/fd6sd2 3-287 fd7/fd7d2 3-290 fd7s/fd7sd2 3-293 fd8/fd8d2 3-296 fd8s/fd8sd2 3-300 d flip-flop with synchronous clear fds2/fds2d2 3-304 fds2cs/fds2csd2 3-307 fds2s/fds2sd2 3-311 fds3/fds3d2 3-314 d flip-flop with ck enable fg1 3-317 fg1x4 3-319 fg2 3-324 fg2x4 3-327 cell type cell name page
internal macrocells summary tables sec asic 3-5 kg80/KGM80 latches jk flip-flop fj1/fj1d2 3-332 fj1s/fj1sd2 3-335 fj2/fj2d2 3-338 fj2s/fj2sd2 3-341 fj4/fj4d2 3-345 fj4s/fj4sd2 3-349 toggle flip-flop ft2/ft2d2 3-353 ft3/ft3d2 3-356 cell type cell name page d latch with active high ld1/ld1d2 3-361 ld1s/ld1sd2 3-364 ld1q/ld1qd2 3-369 ld1x4/ld1x4d2 3-372 yld1/yld1d2 3-381 ld1a 3-384 ld1b 3-386 d latch with active high, reset ld2/ld2d2 3-389 ld2q/ld2qd2 3-394 yld2/yld2d2 3-397 ld3/ld3d2 3-402 ld4/ld4d2 3-407 d latch with active low ld5/ld5d2 3-412 ld5s/ld5sd2 3-415 ld5x4/ld5x4d2 3-420 ld6/ld6d2 3-429 ld7/ld7d2 3-434 ld8/ld8d2 3-439 d latch with synchronous clear lds2 3-444 lds6 3-447 sr latch ls0/ls0d2 3-450 ls1 3-453 ls2 3-456 cell type cell name page
summary tables internal macrocells kg80/KGM80 3-6 sec asic bus holder internal clock drivers decoders adders multiplexers cell type cell name page bus holder busholder 3-459 cell type cell name page kg80 KGM80 internal clock driver ck(2/4/8/12) ck(2/4/6/8) 3-460 cell type cell name page non-inverting decoder dc4 3-464 inverting decoder dc4i 3-467 dc8i 3-470 cell type cell name page full adder fa/fad2 3-478 half adder ha/had2 3-483 cell type cell name page 2 > 1 non-inverting mux mx2/mx2d3 3-487 mx2x4 3-490 ymx2/ymx2d2 3-495 2 > 1 inverting mux mx2i/mx2id2 3-498 mx2ia/mx2id2a 3-501 mx2ix4 3-504 3 > 1 inverting mux mx3i/mx3id2 3-509 4 > 1 non-inverting mux mx4/mx4d2 3-512 ymx4/ymx4d2 3-517 5 > 1 non-inverting mux mx5/mx5d2 3-522 8 > 1 non-inverting mux mx8/mx8d2 3-527 ymx8/ymx8d2 3-533
sec asic 3-7 kg80/KGM80 logic cells cell list cell name function description ad2 2-input and ad2d2 2-input and with 2x drive ad3 3-input and ad3d3 3-input and with 3x drive ad4 4-input and ad4d2 4-input and with 2x drive ad5 5-input and ad5d2 5-input and with 2x drive nd2 2-input nand nd2d2 2-input nand with 2x drive nd3 3-input nand nd3d2 3-input nand with 2x drive nd4 4-input nand nd4d2 4-input nand with 2x drive nd5 5-input nand nd5d2 5-input nand with 2x drive nd6 6-input nand nd6d2 6-input nand with 2x drive nd8 8-input nand nd8d2 8-input nand with 2x drive nr2 2-input nor nr2d2 2-input nor with 2x drive nr3 3-input nor nr3d2 3-input nor with 2x drive nr4 4-input nor nr4d2 4-input nor with 2x drive nr5 5-input nor nr5d2 5-input nor with 2x drive nr6 6-input nor nr6d2 6-input nor with 2x drive nr8 8-input nor nr8d2 8-input nor with 2x drive or2 2-input or or2d2 2-input or with 2x drive
kg80/KGM80 3-8 sec asic logic cells cell list (continued) or3 3-input or or3d3 3-input or with 3x drive or4 4-input or or4d2 4-input or with 2x drive or5 5-input or or5d2 5-input or with 2x drive xn2 2-input exclusive-nor xn2d2 2-input exclusive-nor with 2x drive xn3 3-input exclusive-nor xn3d3 3-input exclusive-nor with 3x drive xo2 2-input exclusive-or xo2d2 2-input exclusive-or with 2x drive xo3 3-input exclusive-or xo3d3 3-input exclusive-or with 3x drive ao21 2-and into 2-nor ao21d2 2-and into 2-nor with 2x drive ao211 2-and into 3-nor ao211d2 2-and into 3-nor with 2x drive ao22 two 2-ands into 2-nor ao22d2 two 2-ands into 2-nor with 2x drive ao22a 2-and and 2-nor into 2-nor ao22d2a 2-and and 2-nor into 2-nor with 2x drive ao222 three 2-ands into 3-nor ao222d2 three 2-ands into 3-nor with 2x drive ao222a inverting 2-of-3 majority ao222d2a inverting 2-of-3 majority with 2x drive ao33 two 3-ands into 2-nor ao33d2 two 3-ands into 2-nor with 2x drive ao333 three 3-ands into 3-nor ao333d2 three 3-ands into 3-nor with 2x drive oa21 2-or into 2-nand oa21d2 2-or into 2-nand with 2x drive oa211 2-or into 3-nand oa211d2 2-or into 3-nand with 2x drive cell name function description
sec asic 3-9 kg80/KGM80 oa22 two 2-ors into 2-nand oa22d2 two 2-ors into 2-nand with 2x drive oa22a 2-or and 2-nand into 2-nand oa22d2a 2-or and 2-nand into 2-nand with 2x drive oa2222 four 2-ors into 4-nand oa2222d2 four 2-ors into 4-nand with 2x drive dl1d2 1ns delay cell with 2x drive dl1d4 1ns delay cell with 4x drive dl2d2 2ns delay cell with 2x drive dl2d4 2ns delay cell with 4x drive dl3d2 3ns delay cell with 2x drive dl3d4 3ns delay cell with 4x drive dl4d2 4ns delay cell with 2x drive dl4d4 4ns delay cell with 4x drive dl5d2 5ns delay cell with 2x drive dl5d4 5ns delay cell with 4x drive dl10d2 10ns delay cell with 2x drive dl10d4 10ns delay cell with 4x drive iv inverter ivd2 inverter with 2x drive ivd3 inverter with 3x drive ivd4 inverter with 4x drive ivd6 inverter with 6x drive ivd8 inverter with 8x drive iva inverter with 2x p-transistor, 1x n-transistor ivd2a inverter with 4x p-transistor, 2x n-transistor ivd3a inverter with 6x p-transistor, 3x n-transistor ivd4a inverter with 8x p-transistor, 4x n-transistor ivcd11 1x inverter into 1x inverter ivcd13 1x inverter into 3x inverter ivcd22 2x inverter into 2x inverter ivcd26 2x inverter into 6x inverter ivcd44 4x inverter into 4x inverter ivt inverting tri-state buffer with enable high cell name function description logic cells cell list (continued)
kg80/KGM80 3-10 sec asic ivtd2 inverting tri-state buffer with enable high, 2x drive ivtd4 inverting tri-state buffer with enable high, 4x drive ivtd8 inverting tri-state buffer with enable high, 8x drive ivtn inverting tri-state buffer with enable low ivtnd2 inverting tri-state buffer with enable low, 2x drive ivtnd4 inverting tri-state buffer with enable low, 4x drive ivtnd8 inverting tri-state buffer with enable low, 8x drive nid non-inverting buffer nid2 non-inverting buffer with 2x drive nid3 non-inverting buffer with 3x drive nid4 non-inverting buffer with 4x drive nid6 non-inverting buffer with 6x drive nid8 non-inverting buffer with 8x drive nit non-inverting tri-state buffer with enable high nitd2 non-inverting tri-state buffer with enable high, 2x drive nitd4 non-inverting tri-state buffer with enable high, 4x drive nitd8 non-inverting tri-state buffer with enable high, 8x drive nitn non-inverting tri-state buffer with enable low nitnd2 non-inverting tri-state buffer with enable low, 2x drive nitnd4 non-inverting tri-state buffer with enable low, 4x drive nitnd8 non-inverting tri-state buffer with enable low, 8x drive cell name function description logic cells cell list (continued)
sec asic 3-11 kg80/KGM80 ad2/ad2d2 2-input and with 1x/2x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ad2 kg80 ad2d2 input load (sl) gate count kg80 ad2 ad2d2 ad2 ad2d2 abab 0.9 0.8 0.9 0.8 2.0 2.0 KGM80 ad2 ad2d2 ad2 ad2d2 abab 1.0 1.0 1.0 1.0 2.0 2.0 a b y [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.28 0.19 + 0.043*sl 0.19 + 0.041*sl 0.19 + 0.042*sl t phl 0.27 0.21 + 0.028*sl 0.22 + 0.025*sl 0.23 + 0.023*sl t r 0.28 0.10 + 0.086*sl 0.10 + 0.089*sl 0.09 + 0.090*sl t f 0.16 0.09 + 0.037*sl 0.08 + 0.040*sl 0.07 + 0.042*sl b to y t plh 0.27 0.18 + 0.043*sl 0.18 + 0.041*sl 0.18 + 0.042*sl t phl 0.30 0.24 + 0.030*sl 0.26 + 0.025*sl 0.27 + 0.023*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.038*sl 0.09 + 0.039*sl 0.08 + 0.041*sl yy () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.25 0.20 + 0.024*sl 0.21 + 0.021*sl 0.22 + 0.020*sl t phl 0.26 0.23 + 0.018*sl 0.24 + 0.014*sl 0.25 + 0.012*sl t r 0.18 0.09 + 0.043*sl 0.09 + 0.043*sl 0.08 + 0.044*sl t f 0.13 0.09 + 0.021*sl 0.09 + 0.019*sl 0.09 + 0.020*sl b to y t plh 0.24 0.19 + 0.023*sl 0.20 + 0.021*sl 0.20 + 0.021*sl t phl 0.29 0.25 + 0.020*sl 0.26 + 0.015*sl 0.28 + 0.012*sl t r 0.18 0.09 + 0.043*sl 0.09 + 0.042*sl 0.08 + 0.044*sl t f 0.14 0.09 + 0.021*sl 0.10 + 0.019*sl 0.09 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = truth table aby 000 010 100 111
kg80/KGM80 3-12 sec asic ad2/ad2d2 2-input and with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ad2 KGM80 ad2d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.36 0.26 + 0.053*sl 0.27 + 0.050*sl 0.27 + 0.050*sl t phl 0.35 0.28 + 0.032*sl 0.30 + 0.025*sl 0.32 + 0.023*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.19 0.11 + 0.042*sl 0.11 + 0.041*sl 0.09 + 0.043*sl b to y t plh 0.36 0.26 + 0.053*sl 0.26 + 0.050*sl 0.27 + 0.050*sl t phl 0.39 0.32 + 0.033*sl 0.35 + 0.025*sl 0.37 + 0.023*sl t r 0.35 0.15 + 0.104*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.041*sl 0.12 + 0.041*sl 0.10 + 0.042*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.32 0.27 + 0.029*sl 0.28 + 0.026*sl 0.29 + 0.025*sl t phl 0.34 0.30 + 0.021*sl 0.31 + 0.015*sl 0.34 + 0.012*sl t r 0.23 0.12 + 0.050*sl 0.12 + 0.053*sl 0.11 + 0.054*sl t f 0.15 0.10 + 0.024*sl 0.11 + 0.021*sl 0.11 + 0.020*sl b to y t plh 0.32 0.26 + 0.030*sl 0.27 + 0.026*sl 0.28 + 0.025*sl t phl 0.38 0.33 + 0.022*sl 0.35 + 0.015*sl 0.38 + 0.013*sl t r 0.23 0.13 + 0.050*sl 0.12 + 0.052*sl 0.11 + 0.054*sl t f 0.16 0.11 + 0.024*sl 0.12 + 0.020*sl 0.12 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-13 kg80/KGM80 ad3/ad3d3 3-input and with 1x/3x drive logic symbol cell data input load (sl) gate count kg80 ad3 ad3d3 ad3 ad3d3 abcabc 1.0 0.9 0.9 0.8 0.8 0.9 2.0 3.0 KGM80 ad3 ad3d3 ad3 ad3d3 abcabc 1.0 1.0 1.0 1.0 1.0 1.0 2.0 3.0 a b c y truth table abcy 0xx0 x0x0 xx00 1111
kg80/KGM80 3-14 sec asic ad3/ad3d3 3-input and with 1x/3x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ad3 kg80 ad3d3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.34 0.25 + 0.045*sl 0.26 + 0.042*sl 0.26 + 0.042*sl t phl 0.28 0.22 + 0.030*sl 0.23 + 0.025*sl 0.25 + 0.023*sl t r 0.29 0.12 + 0.085*sl 0.11 + 0.088*sl 0.10 + 0.089*sl t f 0.17 0.10 + 0.037*sl 0.09 + 0.040*sl 0.08 + 0.041*sl b to y t plh 0.34 0.25 + 0.045*sl 0.26 + 0.042*sl 0.26 + 0.041*sl t phl 0.31 0.25 + 0.032*sl 0.26 + 0.025*sl 0.28 + 0.023*sl t r 0.29 0.12 + 0.084*sl 0.11 + 0.088*sl 0.10 + 0.089*sl t f 0.18 0.10 + 0.038*sl 0.10 + 0.039*sl 0.09 + 0.041*sl c to y t plh 0.34 0.25 + 0.045*sl 0.26 + 0.042*sl 0.27 + 0.041*sl t phl 0.34 0.28 + 0.033*sl 0.29 + 0.026*sl 0.31 + 0.024*sl t r 0.29 0.12 + 0.085*sl 0.11 + 0.088*sl 0.10 + 0.089*sl t f 0.19 0.11 + 0.039*sl 0.11 + 0.039*sl 0.10 + 0.040*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.38 0.35 + 0.018*sl 0.35 + 0.016*sl 0.36 + 0.015*sl t phl 0.31 0.28 + 0.014*sl 0.29 + 0.011*sl 0.30 + 0.010*sl t r 0.22 0.16 + 0.026*sl 0.16 + 0.028*sl 0.15 + 0.028*sl t f 0.15 0.12 + 0.015*sl 0.12 + 0.013*sl 0.12 + 0.013*sl b to y t plh 0.38 0.34 + 0.018*sl 0.35 + 0.016*sl 0.36 + 0.015*sl t phl 0.34 0.31 + 0.015*sl 0.31 + 0.012*sl 0.33 + 0.010*sl t r 0.21 0.16 + 0.026*sl 0.16 + 0.028*sl 0.15 + 0.029*sl t f 0.16 0.13 + 0.015*sl 0.13 + 0.014*sl 0.14 + 0.013*sl c to y t plh 0.38 0.34 + 0.018*sl 0.35 + 0.016*sl 0.36 + 0.015*sl t phl 0.36 0.33 + 0.016*sl 0.34 + 0.012*sl 0.36 + 0.010*sl t r 0.22 0.16 + 0.027*sl 0.16 + 0.027*sl 0.15 + 0.029*sl t f 0.17 0.14 + 0.015*sl 0.15 + 0.014*sl 0.15 + 0.013*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-15 kg80/KGM80 ad3/ad3d3 3-input and with 1x/3x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ad3 KGM80 ad3d3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.46 0.34 + 0.057*sl 0.36 + 0.051*sl 0.37 + 0.050*sl t phl 0.37 0.30 + 0.034*sl 0.32 + 0.026*sl 0.35 + 0.023*sl t r 0.38 0.17 + 0.104*sl 0.16 + 0.106*sl 0.14 + 0.108*sl t f 0.20 0.11 + 0.043*sl 0.11 + 0.041*sl 0.11 + 0.042*sl b to y t plh 0.47 0.36 + 0.057*sl 0.37 + 0.051*sl 0.38 + 0.050*sl t phl 0.41 0.34 + 0.035*sl 0.37 + 0.026*sl 0.40 + 0.023*sl t r 0.38 0.17 + 0.103*sl 0.16 + 0.106*sl 0.14 + 0.108*sl t f 0.21 0.12 + 0.042*sl 0.12 + 0.041*sl 0.11 + 0.042*sl c to y t plh 0.48 0.37 + 0.056*sl 0.39 + 0.051*sl 0.40 + 0.050*sl t phl 0.46 0.38 + 0.037*sl 0.41 + 0.027*sl 0.45 + 0.024*sl t r 0.38 0.17 + 0.104*sl 0.16 + 0.106*sl 0.14 + 0.108*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.040*sl 0.13 + 0.042*sl *g 1 sl 3 *g 2 3 sl 11 *g 3 11 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.51 0.46 + 0.023*sl 0.47 + 0.020*sl 0.49 + 0.018*sl t phl 0.42 0.39 + 0.016*sl 0.40 + 0.012*sl 0.43 + 0.010*sl t r 0.28 0.20 + 0.039*sl 0.21 + 0.035*sl 0.21 + 0.035*sl t f 0.18 0.15 + 0.017*sl 0.15 + 0.015*sl 0.16 + 0.014*sl b to y t plh 0.52 0.47 + 0.023*sl 0.48 + 0.020*sl 0.50 + 0.018*sl t phl 0.46 0.43 + 0.018*sl 0.44 + 0.013*sl 0.47 + 0.010*sl t r 0.28 0.20 + 0.038*sl 0.21 + 0.035*sl 0.21 + 0.035*sl t f 0.19 0.16 + 0.017*sl 0.16 + 0.015*sl 0.18 + 0.014*sl c to y t plh 0.53 0.49 + 0.023*sl 0.50 + 0.020*sl 0.52 + 0.018*sl t phl 0.50 0.47 + 0.018*sl 0.48 + 0.013*sl 0.51 + 0.010*sl t r 0.28 0.20 + 0.039*sl 0.21 + 0.035*sl 0.21 + 0.035*sl t f 0.21 0.18 + 0.018*sl 0.18 + 0.015*sl 0.20 + 0.013*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-16 sec asic ad4/ad4d2 4-input and with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 ad4 ad4d2 ad4 ad4d2 abcdabcd 0.9 0.9 0.9 0.8 0.9 0.9 0.9 0.8 3.0 3.0 KGM80 ad4 ad4d2 ad4 ad4d2 abcdabcd 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 3.0 3.0 a b c y d truth table abcdy 0xxx0 x0xx0 xx0x0 xxx00 11111
sec asic 3-17 kg80/KGM80 ad4/ad4d2 4-input and with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ad4 kg80 ad4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.42 0.32 + 0.048*sl 0.33 + 0.043*sl 0.34 + 0.042*sl t phl 0.30 0.24 + 0.031*sl 0.25 + 0.026*sl 0.26 + 0.024*sl t r 0.32 0.15 + 0.085*sl 0.15 + 0.087*sl 0.14 + 0.088*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.040*sl 0.09 + 0.041*sl b to y t plh 0.43 0.33 + 0.048*sl 0.34 + 0.043*sl 0.36 + 0.042*sl t phl 0.33 0.26 + 0.033*sl 0.28 + 0.026*sl 0.29 + 0.024*sl t r 0.32 0.15 + 0.084*sl 0.15 + 0.086*sl 0.14 + 0.088*sl t f 0.19 0.11 + 0.039*sl 0.11 + 0.039*sl 0.10 + 0.041*sl c to y t plh 0.44 0.35 + 0.048*sl 0.36 + 0.043*sl 0.37 + 0.042*sl t phl 0.36 0.29 + 0.035*sl 0.31 + 0.027*sl 0.32 + 0.024*sl t r 0.32 0.15 + 0.086*sl 0.15 + 0.086*sl 0.14 + 0.088*sl t f 0.20 0.12 + 0.040*sl 0.12 + 0.039*sl 0.11 + 0.040*sl d to y t plh 0.44 0.34 + 0.048*sl 0.36 + 0.043*sl 0.37 + 0.042*sl t phl 0.37 0.30 + 0.035*sl 0.32 + 0.028*sl 0.34 + 0.024*sl t r 0.32 0.15 + 0.085*sl 0.15 + 0.086*sl 0.14 + 0.088*sl t f 0.21 0.13 + 0.041*sl 0.13 + 0.039*sl 0.13 + 0.040*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.39 0.33 + 0.027*sl 0.34 + 0.023*sl 0.35 + 0.022*sl t phl 0.28 0.25 + 0.018*sl 0.26 + 0.014*sl 0.27 + 0.013*sl t r 0.25 0.17 + 0.039*sl 0.16 + 0.043*sl 0.16 + 0.043*sl t f 0.14 0.10 + 0.020*sl 0.11 + 0.019*sl 0.10 + 0.020*sl b to y t plh 0.40 0.34 + 0.027*sl 0.35 + 0.023*sl 0.36 + 0.022*sl t phl 0.31 0.27 + 0.020*sl 0.28 + 0.015*sl 0.30 + 0.013*sl t r 0.25 0.17 + 0.039*sl 0.16 + 0.043*sl 0.16 + 0.043*sl t f 0.16 0.11 + 0.022*sl 0.12 + 0.019*sl 0.11 + 0.020*sl c to y t plh 0.41 0.36 + 0.026*sl 0.37 + 0.023*sl 0.37 + 0.022*sl t phl 0.34 0.30 + 0.020*sl 0.31 + 0.016*sl 0.33 + 0.013*sl t r 0.25 0.17 + 0.041*sl 0.16 + 0.043*sl 0.16 + 0.043*sl t f 0.17 0.12 + 0.021*sl 0.13 + 0.019*sl 0.13 + 0.020*sl d to y t plh 0.41 0.36 + 0.026*sl 0.36 + 0.023*sl 0.37 + 0.022*sl t phl 0.35 0.31 + 0.021*sl 0.32 + 0.016*sl 0.34 + 0.014*sl t r 0.25 0.17 + 0.039*sl 0.16 + 0.043*sl 0.16 + 0.043*sl t f 0.18 0.14 + 0.021*sl 0.14 + 0.020*sl 0.14 + 0.019*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-18 sec asic ad4/ad4d2 4-input and with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ad4 KGM80 ad4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.56 0.44 + 0.062*sl 0.47 + 0.052*sl 0.49 + 0.050*sl t phl 0.40 0.33 + 0.035*sl 0.35 + 0.027*sl 0.38 + 0.024*sl t r 0.42 0.20 + 0.108*sl 0.21 + 0.105*sl 0.19 + 0.107*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.042*sl 0.12 + 0.042*sl b to y t plh 0.59 0.47 + 0.062*sl 0.49 + 0.052*sl 0.52 + 0.050*sl t phl 0.44 0.37 + 0.036*sl 0.39 + 0.027*sl 0.43 + 0.024*sl t r 0.42 0.21 + 0.107*sl 0.21 + 0.105*sl 0.19 + 0.107*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.041*sl 0.13 + 0.042*sl c to y t plh 0.63 0.50 + 0.061*sl 0.53 + 0.052*sl 0.56 + 0.050*sl t phl 0.49 0.41 + 0.038*sl 0.44 + 0.028*sl 0.48 + 0.024*sl t r 0.42 0.21 + 0.108*sl 0.21 + 0.105*sl 0.19 + 0.107*sl t f 0.24 0.15 + 0.045*sl 0.16 + 0.041*sl 0.15 + 0.041*sl d to y t plh 0.63 0.51 + 0.062*sl 0.53 + 0.052*sl 0.56 + 0.050*sl t phl 0.51 0.43 + 0.040*sl 0.46 + 0.028*sl 0.51 + 0.024*sl t r 0.42 0.21 + 0.107*sl 0.21 + 0.105*sl 0.19 + 0.107*sl t f 0.25 0.16 + 0.045*sl 0.17 + 0.041*sl 0.16 + 0.041*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.51 0.44 + 0.033*sl 0.46 + 0.029*sl 0.49 + 0.026*sl t phl 0.38 0.34 + 0.020*sl 0.35 + 0.015*sl 0.38 + 0.013*sl t r 0.32 0.21 + 0.056*sl 0.22 + 0.053*sl 0.22 + 0.052*sl t f 0.17 0.12 + 0.023*sl 0.13 + 0.021*sl 0.14 + 0.020*sl b to y t plh 0.54 0.47 + 0.034*sl 0.49 + 0.029*sl 0.52 + 0.026*sl t phl 0.42 0.38 + 0.022*sl 0.39 + 0.016*sl 0.42 + 0.013*sl t r 0.32 0.21 + 0.057*sl 0.22 + 0.053*sl 0.22 + 0.052*sl t f 0.18 0.14 + 0.023*sl 0.14 + 0.021*sl 0.15 + 0.020*sl c to y t plh 0.58 0.51 + 0.034*sl 0.52 + 0.029*sl 0.55 + 0.026*sl t phl 0.46 0.42 + 0.023*sl 0.44 + 0.017*sl 0.47 + 0.013*sl t r 0.32 0.21 + 0.056*sl 0.22 + 0.053*sl 0.22 + 0.052*sl t f 0.20 0.15 + 0.024*sl 0.16 + 0.021*sl 0.17 + 0.020*sl d to y t plh 0.58 0.51 + 0.034*sl 0.53 + 0.029*sl 0.56 + 0.026*sl t phl 0.49 0.44 + 0.024*sl 0.46 + 0.017*sl 0.50 + 0.014*sl t r 0.32 0.21 + 0.057*sl 0.22 + 0.053*sl 0.22 + 0.052*sl t f 0.21 0.16 + 0.024*sl 0.17 + 0.021*sl 0.18 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-19 kg80/KGM80 ad5/ad5d2 5-input and with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 ad5 ad5d2 ad5 ad5d2 abcdeabcde 0.5 0.6 0.6 0.8 0.7 0.5 0.6 0.6 0.8 0.7 4.0 5.0 KGM80 ad5 ad5d2 ad5 ad5d2 abcdeabcde 0.7 0.8 0.8 0.8 0.9 0.7 0.8 0.8 0.9 0.9 4.0 5.0 b c d y e a truth table abcdey 0xxxx0 x0xxx0 xx0xx0 xxx0x0 xxxx00 111111
kg80/KGM80 3-20 sec asic ad5/ad5d2 5-input and with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ad5 kg80 ad5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.49 0.39 + 0.052*sl 0.40 + 0.045*sl 0.42 + 0.042*sl t phl 0.31 0.24 + 0.033*sl 0.26 + 0.026*sl 0.28 + 0.024*sl t r 0.35 0.18 + 0.086*sl 0.18 + 0.086*sl 0.17 + 0.087*sl t f 0.18 0.10 + 0.041*sl 0.10 + 0.040*sl 0.09 + 0.041*sl b to y t plh 0.51 0.41 + 0.052*sl 0.42 + 0.045*sl 0.44 + 0.042*sl t phl 0.34 0.27 + 0.034*sl 0.29 + 0.027*sl 0.31 + 0.024*sl t r 0.35 0.18 + 0.086*sl 0.18 + 0.086*sl 0.17 + 0.087*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.040*sl 0.11 + 0.040*sl c to y t plh 0.54 0.44 + 0.052*sl 0.45 + 0.045*sl 0.47 + 0.042*sl t phl 0.37 0.30 + 0.036*sl 0.32 + 0.027*sl 0.34 + 0.024*sl t r 0.35 0.18 + 0.086*sl 0.18 + 0.086*sl 0.17 + 0.087*sl t f 0.20 0.12 + 0.041*sl 0.13 + 0.040*sl 0.12 + 0.040*sl d to y t plh 0.55 0.45 + 0.052*sl 0.47 + 0.045*sl 0.48 + 0.042*sl t phl 0.38 0.31 + 0.037*sl 0.33 + 0.028*sl 0.36 + 0.025*sl t r 0.35 0.18 + 0.085*sl 0.18 + 0.086*sl 0.17 + 0.087*sl t f 0.22 0.13 + 0.042*sl 0.14 + 0.039*sl 0.13 + 0.040*sl e to y t plh 0.56 0.46 + 0.052*sl 0.48 + 0.045*sl 0.50 + 0.042*sl t phl 0.40 0.32 + 0.038*sl 0.35 + 0.029*sl 0.37 + 0.025*sl t r 0.35 0.18 + 0.086*sl 0.18 + 0.086*sl 0.17 + 0.087*sl t f 0.23 0.14 + 0.043*sl 0.15 + 0.039*sl 0.15 + 0.040*sl [y ypp , , , , ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.51 0.45 + 0.031*sl 0.46 + 0.025*sl 0.48 + 0.023*sl t phl 0.31 0.27 + 0.020*sl 0.28 + 0.016*sl 0.30 + 0.013*sl t r 0.30 0.22 + 0.042*sl 0.22 + 0.042*sl 0.21 + 0.043*sl t f 0.16 0.11 + 0.022*sl 0.12 + 0.020*sl 0.12 + 0.020*sl b to y t plh 0.53 0.47 + 0.030*sl 0.48 + 0.025*sl 0.50 + 0.023*sl t phl 0.34 0.30 + 0.021*sl 0.31 + 0.016*sl 0.32 + 0.014*sl t r 0.30 0.22 + 0.041*sl 0.22 + 0.042*sl 0.21 + 0.043*sl t f 0.17 0.12 + 0.022*sl 0.13 + 0.020*sl 0.13 + 0.020*sl c to y t plh 0.56 0.50 + 0.030*sl 0.52 + 0.025*sl 0.53 + 0.023*sl t phl 0.37 0.32 + 0.022*sl 0.33 + 0.017*sl 0.36 + 0.014*sl t r 0.30 0.22 + 0.040*sl 0.22 + 0.042*sl 0.21 + 0.043*sl t f 0.18 0.14 + 0.023*sl 0.14 + 0.020*sl 0.15 + 0.019*sl d to y t plh 0.57 0.51 + 0.030*sl 0.53 + 0.025*sl 0.54 + 0.022*sl t phl 0.38 0.34 + 0.023*sl 0.35 + 0.017*sl 0.37 + 0.014*sl t r 0.30 0.22 + 0.043*sl 0.22 + 0.042*sl 0.21 + 0.043*sl t f 0.19 0.15 + 0.023*sl 0.15 + 0.020*sl 0.16 + 0.019*sl e to y t plh 0.59 0.53 + 0.030*sl 0.54 + 0.025*sl 0.56 + 0.023*sl t phl 0.40 0.35 + 0.024*sl 0.36 + 0.018*sl 0.39 + 0.015*sl t r 0.30 0.21 + 0.043*sl 0.22 + 0.042*sl 0.21 + 0.043*sl t f 0.21 0.16 + 0.024*sl 0.17 + 0.020*sl 0.17 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-21 kg80/KGM80 ad5/ad5d2 5-input and with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ad5 KGM80 ad5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.67 0.53 + 0.067*sl 0.57 + 0.055*sl 0.62 + 0.050*sl t phl 0.42 0.34 + 0.037*sl 0.37 + 0.027*sl 0.41 + 0.024*sl t r 0.46 0.23 + 0.113*sl 0.25 + 0.105*sl 0.24 + 0.106*sl t f 0.21 0.12 + 0.046*sl 0.13 + 0.042*sl 0.13 + 0.042*sl b to y t plh 0.71 0.58 + 0.066*sl 0.61 + 0.055*sl 0.66 + 0.050*sl t phl 0.46 0.38 + 0.038*sl 0.41 + 0.028*sl 0.45 + 0.024*sl t r 0.46 0.23 + 0.112*sl 0.25 + 0.105*sl 0.24 + 0.106*sl t f 0.23 0.14 + 0.046*sl 0.15 + 0.041*sl 0.14 + 0.042*sl c to y t plh 0.77 0.64 + 0.066*sl 0.67 + 0.055*sl 0.72 + 0.050*sl t phl 0.51 0.43 + 0.040*sl 0.46 + 0.029*sl 0.51 + 0.024*sl t r 0.46 0.23 + 0.112*sl 0.25 + 0.105*sl 0.24 + 0.106*sl t f 0.24 0.15 + 0.046*sl 0.16 + 0.041*sl 0.16 + 0.041*sl d to y t plh 0.79 0.66 + 0.066*sl 0.69 + 0.055*sl 0.74 + 0.050*sl t phl 0.53 0.45 + 0.042*sl 0.48 + 0.029*sl 0.53 + 0.025*sl t r 0.46 0.23 + 0.112*sl 0.25 + 0.105*sl 0.24 + 0.106*sl t f 0.26 0.16 + 0.046*sl 0.18 + 0.041*sl 0.17 + 0.041*sl e to y t plh 0.82 0.69 + 0.066*sl 0.71 + 0.055*sl 0.76 + 0.050*sl t phl 0.56 0.47 + 0.044*sl 0.51 + 0.030*sl 0.56 + 0.025*sl t r 0.46 0.23 + 0.112*sl 0.25 + 0.105*sl 0.24 + 0.106*sl t f 0.27 0.18 + 0.047*sl 0.19 + 0.041*sl 0.19 + 0.041*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.70 0.62 + 0.037*sl 0.64 + 0.031*sl 0.68 + 0.027*sl t phl 0.43 0.39 + 0.023*sl 0.40 + 0.017*sl 0.44 + 0.014*sl t r 0.38 0.26 + 0.059*sl 0.28 + 0.054*sl 0.29 + 0.052*sl t f 0.19 0.14 + 0.025*sl 0.15 + 0.022*sl 0.16 + 0.021*sl b to y t plh 0.74 0.67 + 0.037*sl 0.68 + 0.031*sl 0.73 + 0.027*sl t phl 0.47 0.42 + 0.024*sl 0.44 + 0.017*sl 0.48 + 0.014*sl t r 0.38 0.26 + 0.058*sl 0.27 + 0.054*sl 0.29 + 0.052*sl t f 0.20 0.15 + 0.026*sl 0.16 + 0.022*sl 0.18 + 0.020*sl c to y t plh 0.80 0.73 + 0.037*sl 0.74 + 0.031*sl 0.79 + 0.027*sl t phl 0.52 0.47 + 0.025*sl 0.49 + 0.018*sl 0.53 + 0.014*sl t r 0.38 0.26 + 0.058*sl 0.27 + 0.054*sl 0.29 + 0.052*sl t f 0.22 0.17 + 0.025*sl 0.18 + 0.022*sl 0.20 + 0.020*sl d to y t plh 0.82 0.75 + 0.037*sl 0.77 + 0.031*sl 0.81 + 0.027*sl t phl 0.54 0.49 + 0.026*sl 0.51 + 0.019*sl 0.55 + 0.014*sl t r 0.38 0.26 + 0.058*sl 0.27 + 0.054*sl 0.29 + 0.052*sl t f 0.23 0.18 + 0.026*sl 0.19 + 0.022*sl 0.21 + 0.020*sl e to y t plh 0.85 0.77 + 0.037*sl 0.79 + 0.031*sl 0.83 + 0.027*sl t phl 0.57 0.51 + 0.028*sl 0.54 + 0.019*sl 0.58 + 0.015*sl t r 0.38 0.26 + 0.058*sl 0.27 + 0.054*sl 0.29 + 0.052*sl t f 0.25 0.20 + 0.027*sl 0.21 + 0.022*sl 0.23 + 0.020*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 11, *grou p 3 : 11 < sl < < = =
kg80/KGM80 3-22 sec asic nd2/nd2d2 2-input nand with 1x/2x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nd2 kg80 nd2d2 input load (sl) gate count kg80 nd2 nd2d2 nd2 nd2d2 abab 0.9 0.9 1.7 1.7 1.0 2.0 KGM80 nd2 nd2d2 nd2 nd2d2 abab 1.0 1.0 2.1 2.0 1.0 2.0 a b y [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.22 0.12 + 0.046*sl 0.14 + 0.040*sl 0.13 + 0.041*sl t phl 0.15 0.06 + 0.045*sl 0.08 + 0.034*sl 0.09 + 0.034*sl t r 0.32 0.17 + 0.075*sl 0.15 + 0.084*sl 0.12 + 0.088*sl t f 0.28 0.17 + 0.059*sl 0.16 + 0.061*sl 0.13 + 0.065*sl b to y t plh 0.24 0.16 + 0.042*sl 0.16 + 0.040*sl 0.16 + 0.041*sl t phl 0.14 0.05 + 0.041*sl 0.07 + 0.035*sl 0.07 + 0.034*sl t r 0.36 0.21 + 0.075*sl 0.19 + 0.083*sl 0.15 + 0.088*sl t f 0.27 0.16 + 0.056*sl 0.14 + 0.062*sl 0.11 + 0.066*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.17 0.11 + 0.027*sl 0.12 + 0.021*sl 0.13 + 0.020*sl t phl 0.10 0.05 + 0.026*sl 0.06 + 0.021*sl 0.09 + 0.017*sl t r 0.24 0.16 + 0.037*sl 0.16 + 0.039*sl 0.14 + 0.042*sl t f 0.22 0.16 + 0.032*sl 0.16 + 0.029*sl 0.15 + 0.031*sl b to y t plh 0.21 0.16 + 0.023*sl 0.17 + 0.020*sl 0.17 + 0.020*sl t phl 0.10 0.05 + 0.024*sl 0.06 + 0.019*sl 0.07 + 0.017*sl t r 0.29 0.22 + 0.036*sl 0.21 + 0.039*sl 0.19 + 0.042*sl t f 0.21 0.15 + 0.026*sl 0.15 + 0.029*sl 0.13 + 0.031*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = truth table aby 001 011 101 110
sec asic 3-23 kg80/KGM80 nd2/nd2d2 2-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nd2 KGM80 nd2d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.26 0.15 + 0.055*sl 0.16 + 0.049*sl 0.16 + 0.050*sl t phl 0.18 0.08 + 0.048*sl 0.11 + 0.038*sl 0.12 + 0.037*sl t r 0.38 0.19 + 0.097*sl 0.17 + 0.105*sl 0.13 + 0.108*sl t f 0.30 0.17 + 0.068*sl 0.16 + 0.070*sl 0.13 + 0.073*sl b to y t plh 0.30 0.19 + 0.051*sl 0.20 + 0.049*sl 0.20 + 0.050*sl t phl 0.17 0.09 + 0.044*sl 0.10 + 0.038*sl 0.11 + 0.037*sl t r 0.43 0.23 + 0.098*sl 0.21 + 0.105*sl 0.18 + 0.108*sl t f 0.29 0.15 + 0.067*sl 0.14 + 0.071*sl 0.11 + 0.074*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.19 0.13 + 0.031*sl 0.15 + 0.026*sl 0.16 + 0.025*sl t phl 0.12 0.07 + 0.027*sl 0.09 + 0.021*sl 0.12 + 0.018*sl t r 0.28 0.18 + 0.046*sl 0.17 + 0.051*sl 0.15 + 0.053*sl t f 0.23 0.15 + 0.038*sl 0.17 + 0.034*sl 0.15 + 0.035*sl b to y t plh 0.25 0.20 + 0.028*sl 0.21 + 0.025*sl 0.21 + 0.025*sl t phl 0.14 0.09 + 0.025*sl 0.10 + 0.020*sl 0.12 + 0.019*sl t r 0.34 0.24 + 0.049*sl 0.24 + 0.051*sl 0.21 + 0.053*sl t f 0.21 0.15 + 0.034*sl 0.15 + 0.034*sl 0.12 + 0.036*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-24 sec asic nd3/nd3d2 3-input nand with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 nd3 nd3d2 nd3 nd3d2 abcabc 0.9 0.8 0.8 1.7 1.7 1.7 2.0 3.0 KGM80 nd3 nd3d2 nd3 nd3d2 abcabc 1.0 1.0 1.0 2.0 2.0 1.9 2.0 3.0 a b c y truth table abcy 0xx1 x0x1 xx01 1110
sec asic 3-25 kg80/KGM80 nd3/nd3d2 3-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nd3 kg80 nd3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.24 0.15 + 0.044*sl 0.15 + 0.041*sl 0.15 + 0.041*sl t phl 0.22 0.12 + 0.048*sl 0.13 + 0.044*sl 0.13 + 0.045*sl t r 0.37 0.22 + 0.075*sl 0.20 + 0.084*sl 0.17 + 0.088*sl t f 0.40 0.23 + 0.083*sl 0.22 + 0.089*sl 0.19 + 0.092*sl b to y t plh 0.26 0.18 + 0.041*sl 0.18 + 0.041*sl 0.18 + 0.041*sl t phl 0.22 0.12 + 0.048*sl 0.13 + 0.045*sl 0.13 + 0.045*sl t r 0.41 0.26 + 0.075*sl 0.24 + 0.084*sl 0.21 + 0.088*sl t f 0.39 0.23 + 0.082*sl 0.21 + 0.090*sl 0.18 + 0.093*sl c to y t plh 0.29 0.21 + 0.041*sl 0.21 + 0.041*sl 0.21 + 0.041*sl t phl 0.22 0.12 + 0.047*sl 0.13 + 0.045*sl 0.13 + 0.045*sl t r 0.47 0.32 + 0.076*sl 0.30 + 0.083*sl 0.27 + 0.088*sl t f 0.38 0.21 + 0.084*sl 0.19 + 0.091*sl 0.17 + 0.094*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.17 0.12 + 0.027*sl 0.13 + 0.021*sl 0.14 + 0.020*sl t phl 0.14 0.08 + 0.029*sl 0.10 + 0.024*sl 0.11 + 0.022*sl t r 0.26 0.19 + 0.035*sl 0.18 + 0.039*sl 0.16 + 0.042*sl t f 0.29 0.21 + 0.040*sl 0.20 + 0.041*sl 0.18 + 0.044*sl b to y t plh 0.21 0.16 + 0.023*sl 0.17 + 0.020*sl 0.17 + 0.020*sl t phl 0.15 0.09 + 0.027*sl 0.10 + 0.024*sl 0.11 + 0.022*sl t r 0.31 0.24 + 0.036*sl 0.23 + 0.039*sl 0.21 + 0.042*sl t f 0.28 0.20 + 0.040*sl 0.20 + 0.041*sl 0.17 + 0.045*sl c to y t plh 0.23 0.19 + 0.022*sl 0.19 + 0.020*sl 0.19 + 0.020*sl t phl 0.14 0.09 + 0.025*sl 0.10 + 0.023*sl 0.10 + 0.022*sl t r 0.36 0.28 + 0.036*sl 0.28 + 0.039*sl 0.26 + 0.042*sl t f 0.26 0.18 + 0.039*sl 0.17 + 0.043*sl 0.16 + 0.045*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-26 sec asic nd3/nd3d2 3-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nd3 KGM80 nd3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.29 0.19 + 0.052*sl 0.20 + 0.049*sl 0.20 + 0.050*sl t phl 0.27 0.17 + 0.054*sl 0.17 + 0.051*sl 0.17 + 0.051*sl t r 0.47 0.27 + 0.100*sl 0.25 + 0.105*sl 0.22 + 0.108*sl t f 0.47 0.28 + 0.097*sl 0.27 + 0.102*sl 0.23 + 0.105*sl b to y t plh 0.33 0.23 + 0.050*sl 0.23 + 0.049*sl 0.23 + 0.050*sl t phl 0.28 0.18 + 0.054*sl 0.18 + 0.051*sl 0.18 + 0.051*sl t r 0.51 0.31 + 0.100*sl 0.30 + 0.106*sl 0.27 + 0.109*sl t f 0.46 0.27 + 0.098*sl 0.25 + 0.103*sl 0.23 + 0.105*sl c to y t plh 0.37 0.27 + 0.051*sl 0.27 + 0.050*sl 0.28 + 0.050*sl t phl 0.30 0.19 + 0.054*sl 0.20 + 0.051*sl 0.20 + 0.051*sl t r 0.59 0.39 + 0.100*sl 0.37 + 0.105*sl 0.34 + 0.108*sl t f 0.45 0.25 + 0.099*sl 0.24 + 0.104*sl 0.22 + 0.105*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.21 0.15 + 0.031*sl 0.16 + 0.025*sl 0.17 + 0.025*sl t phl 0.17 0.11 + 0.031*sl 0.12 + 0.026*sl 0.13 + 0.025*sl t r 0.30 0.21 + 0.045*sl 0.20 + 0.051*sl 0.17 + 0.053*sl t f 0.32 0.22 + 0.050*sl 0.23 + 0.049*sl 0.20 + 0.051*sl b to y t plh 0.27 0.21 + 0.027*sl 0.22 + 0.025*sl 0.22 + 0.025*sl t phl 0.20 0.14 + 0.030*sl 0.15 + 0.026*sl 0.16 + 0.026*sl t r 0.37 0.27 + 0.047*sl 0.26 + 0.051*sl 0.24 + 0.053*sl t f 0.31 0.22 + 0.047*sl 0.21 + 0.050*sl 0.19 + 0.052*sl c to y t plh 0.30 0.24 + 0.027*sl 0.25 + 0.025*sl 0.25 + 0.025*sl t phl 0.20 0.15 + 0.029*sl 0.15 + 0.026*sl 0.16 + 0.026*sl t r 0.43 0.33 + 0.049*sl 0.32 + 0.051*sl 0.30 + 0.053*sl t f 0.30 0.20 + 0.047*sl 0.19 + 0.051*sl 0.18 + 0.052*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-27 kg80/KGM80 nd4/nd4d2 4-input nand with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 nd4 nd4d2 nd4 nd4d2 abcdabcd 0.9 0.9 0.8 0.9 1.7 1.7 1.7 1.7 2.0 4.0 KGM80 nd4 nd4d2 nd4 nd4d2 abcdabcd 1.0 1.0 1.0 1.0 2.1 2.0 1.9 1.9 2.0 4.0 a b c y d truth table abcdy 0xxx1 x0xx1 xx0x1 xxx01 11110
kg80/KGM80 3-28 sec asic nd4/nd4d2 4-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nd4 kg80 nd4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.23 0.14 + 0.046*sl 0.15 + 0.041*sl 0.15 + 0.041*sl t phl 0.24 0.13 + 0.056*sl 0.13 + 0.054*sl 0.12 + 0.055*sl t r 0.36 0.20 + 0.076*sl 0.18 + 0.084*sl 0.16 + 0.088*sl t f 0.48 0.27 + 0.107*sl 0.25 + 0.115*sl 0.22 + 0.119*sl b to y t plh 0.25 0.17 + 0.043*sl 0.17 + 0.041*sl 0.17 + 0.041*sl t phl 0.25 0.13 + 0.058*sl 0.14 + 0.055*sl 0.13 + 0.056*sl t r 0.40 0.24 + 0.077*sl 0.23 + 0.084*sl 0.20 + 0.088*sl t f 0.48 0.27 + 0.107*sl 0.25 + 0.116*sl 0.22 + 0.119*sl c to y t plh 0.28 0.20 + 0.042*sl 0.20 + 0.041*sl 0.20 + 0.042*sl t phl 0.26 0.15 + 0.059*sl 0.15 + 0.056*sl 0.15 + 0.056*sl t r 0.45 0.30 + 0.076*sl 0.28 + 0.083*sl 0.25 + 0.088*sl t f 0.47 0.25 + 0.110*sl 0.23 + 0.117*sl 0.21 + 0.120*sl d to y t plh 0.30 0.21 + 0.042*sl 0.21 + 0.042*sl 0.22 + 0.042*sl t phl 0.26 0.15 + 0.057*sl 0.15 + 0.056*sl 0.15 + 0.056*sl t r 0.50 0.34 + 0.079*sl 0.33 + 0.083*sl 0.30 + 0.087*sl t f 0.46 0.23 + 0.113*sl 0.22 + 0.118*sl 0.21 + 0.120*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.18 0.13 + 0.026*sl 0.14 + 0.021*sl 0.14 + 0.020*sl t phl 0.17 0.11 + 0.031*sl 0.12 + 0.027*sl 0.12 + 0.027*sl t r 0.27 0.20 + 0.037*sl 0.19 + 0.039*sl 0.17 + 0.042*sl t f 0.37 0.26 + 0.053*sl 0.26 + 0.055*sl 0.24 + 0.058*sl b to y t plh 0.22 0.17 + 0.023*sl 0.18 + 0.020*sl 0.18 + 0.021*sl t phl 0.19 0.13 + 0.031*sl 0.14 + 0.028*sl 0.14 + 0.028*sl t r 0.33 0.25 + 0.035*sl 0.24 + 0.039*sl 0.23 + 0.042*sl t f 0.37 0.26 + 0.051*sl 0.25 + 0.056*sl 0.24 + 0.058*sl c to y t plh 0.24 0.19 + 0.022*sl 0.20 + 0.021*sl 0.20 + 0.021*sl t phl 0.20 0.14 + 0.031*sl 0.14 + 0.028*sl 0.15 + 0.028*sl t r 0.37 0.30 + 0.037*sl 0.29 + 0.039*sl 0.28 + 0.042*sl t f 0.36 0.25 + 0.052*sl 0.24 + 0.056*sl 0.22 + 0.059*sl d to y t plh 0.26 0.21 + 0.022*sl 0.21 + 0.021*sl 0.21 + 0.021*sl t phl 0.21 0.15 + 0.030*sl 0.15 + 0.029*sl 0.15 + 0.028*sl t r 0.42 0.35 + 0.038*sl 0.34 + 0.040*sl 0.33 + 0.042*sl t f 0.34 0.23 + 0.054*sl 0.23 + 0.057*sl 0.21 + 0.059*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-29 kg80/KGM80 nd4/nd4d2 4-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nd4 KGM80 nd4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.29 0.18 + 0.053*sl 0.19 + 0.050*sl 0.19 + 0.050*sl t phl 0.30 0.17 + 0.066*sl 0.17 + 0.065*sl 0.17 + 0.065*sl t r 0.44 0.24 + 0.099*sl 0.23 + 0.105*sl 0.19 + 0.109*sl t f 0.58 0.32 + 0.128*sl 0.31 + 0.133*sl 0.28 + 0.136*sl b to y t plh 0.32 0.22 + 0.051*sl 0.23 + 0.050*sl 0.23 + 0.050*sl t phl 0.32 0.19 + 0.067*sl 0.20 + 0.065*sl 0.20 + 0.065*sl t r 0.49 0.29 + 0.099*sl 0.27 + 0.106*sl 0.24 + 0.109*sl t f 0.58 0.32 + 0.128*sl 0.31 + 0.134*sl 0.28 + 0.136*sl c to y t plh 0.37 0.26 + 0.051*sl 0.27 + 0.050*sl 0.27 + 0.050*sl t phl 0.36 0.22 + 0.067*sl 0.23 + 0.065*sl 0.23 + 0.065*sl t r 0.56 0.36 + 0.099*sl 0.35 + 0.105*sl 0.31 + 0.108*sl t f 0.57 0.31 + 0.130*sl 0.30 + 0.135*sl 0.28 + 0.136*sl d to y t plh 0.39 0.28 + 0.053*sl 0.29 + 0.051*sl 0.30 + 0.050*sl t phl 0.36 0.23 + 0.067*sl 0.24 + 0.065*sl 0.24 + 0.065*sl t r 0.62 0.42 + 0.101*sl 0.41 + 0.105*sl 0.37 + 0.108*sl t f 0.56 0.30 + 0.132*sl 0.29 + 0.135*sl 0.28 + 0.136*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.22 0.16 + 0.030*sl 0.18 + 0.025*sl 0.18 + 0.025*sl t phl 0.22 0.15 + 0.036*sl 0.16 + 0.032*sl 0.15 + 0.032*sl t r 0.33 0.23 + 0.049*sl 0.23 + 0.051*sl 0.20 + 0.053*sl t f 0.44 0.31 + 0.064*sl 0.31 + 0.065*sl 0.29 + 0.067*sl b to y t plh 0.28 0.23 + 0.027*sl 0.23 + 0.025*sl 0.23 + 0.025*sl t phl 0.26 0.19 + 0.036*sl 0.20 + 0.033*sl 0.20 + 0.033*sl t r 0.40 0.30 + 0.048*sl 0.29 + 0.051*sl 0.27 + 0.053*sl t f 0.44 0.31 + 0.062*sl 0.30 + 0.066*sl 0.29 + 0.067*sl c to y t plh 0.31 0.26 + 0.026*sl 0.26 + 0.025*sl 0.26 + 0.025*sl t phl 0.28 0.21 + 0.035*sl 0.22 + 0.033*sl 0.22 + 0.033*sl t r 0.45 0.36 + 0.048*sl 0.35 + 0.051*sl 0.33 + 0.053*sl t f 0.43 0.30 + 0.064*sl 0.30 + 0.066*sl 0.28 + 0.067*sl d to y t plh 0.34 0.28 + 0.027*sl 0.28 + 0.026*sl 0.29 + 0.025*sl t phl 0.30 0.23 + 0.034*sl 0.24 + 0.033*sl 0.24 + 0.033*sl t r 0.52 0.42 + 0.050*sl 0.42 + 0.051*sl 0.40 + 0.053*sl t f 0.42 0.29 + 0.064*sl 0.29 + 0.067*sl 0.28 + 0.068*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-30 sec asic nd5/nd5d2 5-input nand with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 nd5 nd5d2 nd5 nd5d2 abcdeabcde 0.5 0.6 0.6 0.8 0.7 1.1 1.1 1.3 1.5 1.4 3.0 5.0 KGM80 nd5 nd5d2 nd5 nd5d2 abcdeabcde 0.7 0.8 0.8 0.9 0.9 1.3 1.6 1.6 1.7 1.7 3.0 5.0 b c d y e a truth table abcdey 0xxxx1 x0xxx1 xx0xx1 xxx0x1 xxxx01 111110
sec asic 3-31 kg80/KGM80 nd5/nd5d2 5-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nd5 kg80 nd5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.26 0.17 + 0.043*sl 0.18 + 0.041*sl 0.17 + 0.041*sl t phl 0.33 0.20 + 0.063*sl 0.19 + 0.066*sl 0.19 + 0.066*sl t r 0.42 0.27 + 0.079*sl 0.25 + 0.085*sl 0.23 + 0.089*sl t f 0.69 0.41 + 0.139*sl 0.40 + 0.143*sl 0.37 + 0.147*sl b to y t plh 0.28 0.20 + 0.041*sl 0.20 + 0.041*sl 0.20 + 0.041*sl t phl 0.35 0.22 + 0.066*sl 0.22 + 0.067*sl 0.21 + 0.067*sl t r 0.47 0.31 + 0.078*sl 0.29 + 0.085*sl 0.27 + 0.088*sl t f 0.69 0.41 + 0.138*sl 0.40 + 0.144*sl 0.39 + 0.146*sl c to y t plh 0.31 0.23 + 0.042*sl 0.23 + 0.041*sl 0.23 + 0.042*sl t phl 0.38 0.24 + 0.067*sl 0.24 + 0.067*sl 0.24 + 0.067*sl t r 0.52 0.36 + 0.079*sl 0.35 + 0.084*sl 0.32 + 0.088*sl t f 0.69 0.41 + 0.141*sl 0.40 + 0.145*sl 0.39 + 0.146*sl d to y t plh 0.33 0.24 + 0.043*sl 0.24 + 0.042*sl 0.25 + 0.042*sl t phl 0.39 0.25 + 0.067*sl 0.25 + 0.067*sl 0.26 + 0.067*sl t r 0.57 0.41 + 0.079*sl 0.40 + 0.084*sl 0.37 + 0.088*sl t f 0.68 0.40 + 0.141*sl 0.39 + 0.145*sl 0.38 + 0.147*sl e to y t plh 0.34 0.25 + 0.045*sl 0.26 + 0.043*sl 0.26 + 0.042*sl t phl 0.40 0.27 + 0.068*sl 0.27 + 0.068*sl 0.27 + 0.067*sl t r 0.62 0.46 + 0.081*sl 0.45 + 0.085*sl 0.43 + 0.088*sl t f 0.68 0.39 + 0.143*sl 0.39 + 0.145*sl 0.38 + 0.147*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.21 0.16 + 0.024*sl 0.17 + 0.021*sl 0.17 + 0.021*sl t phl 0.25 0.19 + 0.031*sl 0.18 + 0.032*sl 0.18 + 0.033*sl t r 0.34 0.27 + 0.031*sl 0.25 + 0.040*sl 0.23 + 0.043*sl t f 0.53 0.40 + 0.067*sl 0.39 + 0.070*sl 0.38 + 0.072*sl b to y t plh 0.24 0.20 + 0.022*sl 0.20 + 0.020*sl 0.20 + 0.020*sl t phl 0.28 0.21 + 0.033*sl 0.21 + 0.033*sl 0.21 + 0.033*sl t r 0.38 0.31 + 0.038*sl 0.30 + 0.040*sl 0.28 + 0.043*sl t f 0.54 0.40 + 0.069*sl 0.40 + 0.070*sl 0.39 + 0.072*sl c to y t plh 0.27 0.22 + 0.020*sl 0.22 + 0.021*sl 0.23 + 0.021*sl t phl 0.30 0.23 + 0.034*sl 0.23 + 0.034*sl 0.23 + 0.034*sl t r 0.43 0.36 + 0.038*sl 0.35 + 0.040*sl 0.34 + 0.042*sl t f 0.54 0.40 + 0.069*sl 0.39 + 0.071*sl 0.38 + 0.072*sl d to y t plh 0.28 0.24 + 0.022*sl 0.24 + 0.021*sl 0.24 + 0.021*sl t phl 0.32 0.25 + 0.034*sl 0.25 + 0.034*sl 0.25 + 0.034*sl t r 0.48 0.41 + 0.039*sl 0.40 + 0.041*sl 0.39 + 0.042*sl t f 0.53 0.39 + 0.070*sl 0.39 + 0.071*sl 0.38 + 0.073*sl e to y t plh 0.30 0.25 + 0.023*sl 0.25 + 0.022*sl 0.26 + 0.022*sl t phl 0.33 0.26 + 0.035*sl 0.26 + 0.034*sl 0.26 + 0.034*sl t r 0.53 0.45 + 0.040*sl 0.45 + 0.041*sl 0.44 + 0.042*sl t f 0.52 0.38 + 0.071*sl 0.38 + 0.072*sl 0.37 + 0.073*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 7, *grou p 3 : 7 < sl < < = =
kg80/KGM80 3-32 sec asic nd5/nd5d2 5-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nd5 KGM80 nd5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.34 0.23 + 0.050*sl 0.24 + 0.050*sl 0.24 + 0.050*sl t phl 0.43 0.27 + 0.078*sl 0.27 + 0.079*sl 0.27 + 0.079*sl t r 0.56 0.36 + 0.102*sl 0.34 + 0.106*sl 0.32 + 0.109*sl t f 0.88 0.56 + 0.163*sl 0.55 + 0.166*sl 0.53 + 0.168*sl b to y t plh 0.37 0.27 + 0.050*sl 0.27 + 0.050*sl 0.27 + 0.050*sl t phl 0.47 0.32 + 0.079*sl 0.32 + 0.079*sl 0.32 + 0.079*sl t r 0.61 0.40 + 0.102*sl 0.39 + 0.106*sl 0.36 + 0.109*sl t f 0.89 0.56 + 0.164*sl 0.56 + 0.166*sl 0.54 + 0.167*sl c to y t plh 0.42 0.31 + 0.051*sl 0.32 + 0.050*sl 0.32 + 0.050*sl t phl 0.53 0.37 + 0.080*sl 0.37 + 0.079*sl 0.38 + 0.079*sl t r 0.68 0.48 + 0.101*sl 0.46 + 0.106*sl 0.43 + 0.109*sl t f 0.89 0.56 + 0.164*sl 0.56 + 0.166*sl 0.54 + 0.167*sl d to y t plh 0.44 0.34 + 0.052*sl 0.34 + 0.051*sl 0.35 + 0.050*sl t phl 0.55 0.39 + 0.080*sl 0.40 + 0.079*sl 0.40 + 0.079*sl t r 0.74 0.54 + 0.101*sl 0.52 + 0.105*sl 0.49 + 0.108*sl t f 0.89 0.56 + 0.164*sl 0.55 + 0.166*sl 0.54 + 0.167*sl e to y t plh 0.47 0.36 + 0.055*sl 0.36 + 0.052*sl 0.38 + 0.051*sl t phl 0.58 0.42 + 0.080*sl 0.42 + 0.079*sl 0.42 + 0.079*sl t r 0.81 0.61 + 0.102*sl 0.60 + 0.106*sl 0.57 + 0.108*sl t f 0.88 0.55 + 0.165*sl 0.55 + 0.167*sl 0.54 + 0.167*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.28 0.22 + 0.027*sl 0.23 + 0.025*sl 0.23 + 0.025*sl t phl 0.33 0.26 + 0.037*sl 0.25 + 0.039*sl 0.25 + 0.039*sl t r 0.44 0.34 + 0.050*sl 0.33 + 0.052*sl 0.32 + 0.053*sl t f 0.69 0.53 + 0.082*sl 0.53 + 0.082*sl 0.52 + 0.083*sl b to y t plh 0.32 0.27 + 0.025*sl 0.27 + 0.025*sl 0.27 + 0.025*sl t phl 0.39 0.31 + 0.040*sl 0.31 + 0.040*sl 0.31 + 0.039*sl t r 0.49 0.39 + 0.050*sl 0.39 + 0.052*sl 0.37 + 0.053*sl t f 0.71 0.54 + 0.081*sl 0.54 + 0.082*sl 0.53 + 0.083*sl c to y t plh 0.36 0.31 + 0.026*sl 0.31 + 0.025*sl 0.31 + 0.025*sl t phl 0.43 0.35 + 0.040*sl 0.36 + 0.040*sl 0.36 + 0.040*sl t r 0.56 0.46 + 0.050*sl 0.46 + 0.051*sl 0.44 + 0.053*sl t f 0.71 0.54 + 0.081*sl 0.54 + 0.082*sl 0.53 + 0.083*sl d to y t plh 0.39 0.33 + 0.027*sl 0.34 + 0.026*sl 0.34 + 0.025*sl t phl 0.47 0.39 + 0.040*sl 0.39 + 0.040*sl 0.39 + 0.040*sl t r 0.63 0.53 + 0.050*sl 0.53 + 0.052*sl 0.51 + 0.053*sl t f 0.70 0.54 + 0.081*sl 0.54 + 0.083*sl 0.53 + 0.083*sl e to y t plh 0.41 0.35 + 0.028*sl 0.35 + 0.027*sl 0.37 + 0.026*sl t phl 0.49 0.41 + 0.040*sl 0.41 + 0.040*sl 0.41 + 0.040*sl t r 0.70 0.59 + 0.051*sl 0.59 + 0.052*sl 0.58 + 0.053*sl t f 0.70 0.53 + 0.082*sl 0.53 + 0.083*sl 0.52 + 0.083*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 11, *grou p 3 : 11 < sl < < = =
sec asic 3-33 kg80/KGM80 nd6/nd6d2 6-input nand with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 nd6 nd6d2 nd6 nd6d2 abcdefabcdef 0.5 0.5 0.7 0.8 0.8 0.5 0.5 0.5 0.7 0.8 0.8 0.5 5.0 5.0 KGM80 nd6 nd6d2 nd6 nd6d2 abcdefabcdef 1.0 1.0 1.0 0.9 0.9 0.7 1.0 1.0 1.0 0.9 0.9 0.7 5.0 5.0 b c d y e a f truth table abcdefy 0xxxxx1 x0xxxx1 xx0xxx1 xxx0xx1 xxxx0x1 xxxxx01 1111110
kg80/KGM80 3-34 sec asic nd6/nd6d2 6-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nd6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.39 0.31 + 0.043*sl 0.31 + 0.042*sl 0.31 + 0.041*sl t phl 0.45 0.38 + 0.033*sl 0.40 + 0.026*sl 0.42 + 0.024*sl t r 0.26 0.09 + 0.089*sl 0.08 + 0.089*sl 0.08 + 0.091*sl t f 0.19 0.10 + 0.042*sl 0.11 + 0.040*sl 0.10 + 0.041*sl b to y t plh 0.42 0.34 + 0.041*sl 0.34 + 0.042*sl 0.34 + 0.042*sl t phl 0.45 0.38 + 0.033*sl 0.40 + 0.027*sl 0.42 + 0.024*sl t r 0.26 0.08 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.19 0.10 + 0.042*sl 0.11 + 0.040*sl 0.11 + 0.041*sl c to y t plh 0.45 0.37 + 0.041*sl 0.37 + 0.042*sl 0.37 + 0.042*sl t phl 0.45 0.39 + 0.033*sl 0.40 + 0.027*sl 0.42 + 0.024*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.18 0.10 + 0.042*sl 0.10 + 0.041*sl 0.10 + 0.041*sl d to y t plh 0.48 0.39 + 0.041*sl 0.39 + 0.041*sl 0.39 + 0.042*sl t phl 0.47 0.41 + 0.033*sl 0.42 + 0.027*sl 0.44 + 0.024*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.08 + 0.091*sl t f 0.19 0.10 + 0.042*sl 0.10 + 0.041*sl 0.10 + 0.041*sl e to y t plh 0.45 0.36 + 0.042*sl 0.36 + 0.041*sl 0.36 + 0.042*sl t phl 0.47 0.41 + 0.033*sl 0.42 + 0.027*sl 0.44 + 0.024*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.08 + 0.091*sl t f 0.19 0.10 + 0.042*sl 0.11 + 0.041*sl 0.10 + 0.041*sl f to y t plh 0.42 0.33 + 0.041*sl 0.33 + 0.041*sl 0.33 + 0.042*sl t phl 0.47 0.41 + 0.033*sl 0.42 + 0.027*sl 0.44 + 0.024*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.040*sl 0.10 + 0.041*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-35 kg80/KGM80 nd6/nd6d2 6-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nd6d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.38 0.34 + 0.021*sl 0.34 + 0.021*sl 0.34 + 0.021*sl t phl 0.48 0.44 + 0.021*sl 0.45 + 0.016*sl 0.46 + 0.014*sl t r 0.18 0.09 + 0.041*sl 0.09 + 0.044*sl 0.08 + 0.045*sl t f 0.18 0.13 + 0.023*sl 0.14 + 0.021*sl 0.14 + 0.020*sl b to y t plh 0.41 0.37 + 0.021*sl 0.37 + 0.021*sl 0.37 + 0.021*sl t phl 0.48 0.44 + 0.021*sl 0.45 + 0.016*sl 0.46 + 0.014*sl t r 0.18 0.10 + 0.040*sl 0.09 + 0.044*sl 0.08 + 0.045*sl t f 0.18 0.13 + 0.022*sl 0.14 + 0.020*sl 0.14 + 0.020*sl c to y t plh 0.44 0.40 + 0.021*sl 0.40 + 0.021*sl 0.40 + 0.021*sl t phl 0.48 0.44 + 0.021*sl 0.45 + 0.016*sl 0.47 + 0.014*sl t r 0.18 0.10 + 0.040*sl 0.09 + 0.044*sl 0.08 + 0.045*sl t f 0.18 0.13 + 0.022*sl 0.14 + 0.021*sl 0.14 + 0.020*sl d to y t plh 0.47 0.43 + 0.021*sl 0.43 + 0.021*sl 0.43 + 0.021*sl t phl 0.50 0.46 + 0.021*sl 0.47 + 0.016*sl 0.49 + 0.014*sl t r 0.18 0.10 + 0.041*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.18 0.13 + 0.023*sl 0.14 + 0.021*sl 0.14 + 0.020*sl e to y t plh 0.44 0.39 + 0.021*sl 0.40 + 0.021*sl 0.39 + 0.021*sl t phl 0.50 0.46 + 0.021*sl 0.47 + 0.016*sl 0.49 + 0.014*sl t r 0.18 0.10 + 0.042*sl 0.10 + 0.043*sl 0.08 + 0.045*sl t f 0.18 0.13 + 0.023*sl 0.14 + 0.021*sl 0.14 + 0.020*sl f to y t plh 0.40 0.36 + 0.021*sl 0.36 + 0.021*sl 0.36 + 0.021*sl t phl 0.50 0.46 + 0.021*sl 0.47 + 0.016*sl 0.49 + 0.014*sl t r 0.18 0.10 + 0.039*sl 0.09 + 0.044*sl 0.08 + 0.045*sl t f 0.18 0.13 + 0.023*sl 0.14 + 0.020*sl 0.14 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-36 sec asic nd6/nd6d2 6-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nd6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.53 0.43 + 0.050*sl 0.43 + 0.050*sl 0.43 + 0.050*sl t phl 0.63 0.56 + 0.038*sl 0.59 + 0.028*sl 0.63 + 0.024*sl t r 0.33 0.12 + 0.106*sl 0.12 + 0.109*sl 0.11 + 0.109*sl t f 0.23 0.13 + 0.046*sl 0.15 + 0.042*sl 0.15 + 0.042*sl b to y t plh 0.57 0.47 + 0.050*sl 0.47 + 0.050*sl 0.47 + 0.050*sl t phl 0.65 0.57 + 0.038*sl 0.60 + 0.028*sl 0.64 + 0.024*sl t r 0.34 0.12 + 0.106*sl 0.12 + 0.109*sl 0.11 + 0.109*sl t f 0.23 0.14 + 0.046*sl 0.15 + 0.042*sl 0.15 + 0.042*sl c to y t plh 0.62 0.51 + 0.051*sl 0.52 + 0.050*sl 0.52 + 0.050*sl t phl 0.66 0.58 + 0.037*sl 0.61 + 0.028*sl 0.65 + 0.024*sl t r 0.34 0.13 + 0.105*sl 0.12 + 0.109*sl 0.11 + 0.109*sl t f 0.23 0.13 + 0.046*sl 0.15 + 0.042*sl 0.15 + 0.042*sl d to y t plh 0.65 0.55 + 0.051*sl 0.55 + 0.050*sl 0.55 + 0.050*sl t phl 0.70 0.63 + 0.038*sl 0.66 + 0.028*sl 0.70 + 0.024*sl t r 0.34 0.13 + 0.105*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.23 0.13 + 0.047*sl 0.15 + 0.042*sl 0.15 + 0.042*sl e to y t plh 0.60 0.50 + 0.051*sl 0.50 + 0.050*sl 0.51 + 0.050*sl t phl 0.69 0.61 + 0.038*sl 0.64 + 0.028*sl 0.68 + 0.024*sl t r 0.34 0.13 + 0.106*sl 0.12 + 0.109*sl 0.11 + 0.109*sl t f 0.23 0.14 + 0.046*sl 0.15 + 0.042*sl 0.15 + 0.042*sl f to y t plh 0.56 0.46 + 0.051*sl 0.46 + 0.050*sl 0.46 + 0.050*sl t phl 0.68 0.60 + 0.038*sl 0.63 + 0.028*sl 0.67 + 0.024*sl t r 0.34 0.13 + 0.106*sl 0.12 + 0.109*sl 0.11 + 0.109*sl t f 0.23 0.14 + 0.047*sl 0.15 + 0.042*sl 0.15 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-37 kg80/KGM80 nd6/nd6d2 6-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nd6d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.52 0.47 + 0.026*sl 0.47 + 0.025*sl 0.47 + 0.025*sl t phl 0.69 0.64 + 0.024*sl 0.66 + 0.018*sl 0.70 + 0.014*sl t r 0.24 0.13 + 0.051*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.22 0.17 + 0.025*sl 0.18 + 0.022*sl 0.20 + 0.021*sl b to y t plh 0.56 0.51 + 0.026*sl 0.51 + 0.025*sl 0.51 + 0.025*sl t phl 0.70 0.65 + 0.024*sl 0.67 + 0.018*sl 0.71 + 0.014*sl t r 0.24 0.14 + 0.051*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.22 0.17 + 0.027*sl 0.18 + 0.022*sl 0.20 + 0.021*sl c to y t plh 0.61 0.56 + 0.026*sl 0.56 + 0.025*sl 0.56 + 0.025*sl t phl 0.72 0.67 + 0.025*sl 0.68 + 0.018*sl 0.72 + 0.014*sl t r 0.24 0.14 + 0.051*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.22 0.17 + 0.026*sl 0.18 + 0.022*sl 0.20 + 0.021*sl d to y t plh 0.64 0.59 + 0.026*sl 0.59 + 0.025*sl 0.59 + 0.025*sl t phl 0.76 0.71 + 0.025*sl 0.73 + 0.018*sl 0.77 + 0.014*sl t r 0.24 0.14 + 0.052*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.22 0.17 + 0.025*sl 0.18 + 0.022*sl 0.20 + 0.021*sl e to y t plh 0.59 0.54 + 0.026*sl 0.54 + 0.025*sl 0.54 + 0.025*sl t phl 0.75 0.70 + 0.024*sl 0.72 + 0.018*sl 0.76 + 0.014*sl t r 0.24 0.14 + 0.051*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.22 0.17 + 0.025*sl 0.18 + 0.022*sl 0.20 + 0.021*sl f to y t plh 0.55 0.50 + 0.026*sl 0.50 + 0.025*sl 0.50 + 0.025*sl t phl 0.74 0.69 + 0.024*sl 0.70 + 0.018*sl 0.74 + 0.014*sl t r 0.24 0.14 + 0.051*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.22 0.17 + 0.025*sl 0.18 + 0.022*sl 0.20 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-38 sec asic nd8/nd8d2 8-input nand with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 nd8 nd8d2 nd8 nd8d2 abcdefghabcdefgh 0.5 0.6 0.6 0.8 0.7 0.6 0.7 0.5 0.5 0.6 0.6 0.8 0.7 0.6 0.6 0.5 6.0 6.0 KGM80 nd8 nd8d2 nd8 nd8d2 abcdefghabcdefgh 1.0 1.0 1.0 1.0 0.9 0.8 0.8 0.7 1.0 1.0 1.0 1.0 0.9 0.8 0.8 0.7 6.0 6.0 c d e y f b g a h truth table abcdefghy 0xxxxxxx1 x0xxxxxx1 xx0xxxxx1 xxx0xxxx1 xxxx0xxx1 xxxxx0xx1 xxxxxx0x1 xxxxxxx01 111111110
sec asic 3-39 kg80/KGM80 nd8/nd8d2 8-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.38 0.30 + 0.041*sl 0.30 + 0.042*sl 0.30 + 0.042*sl t phl 0.48 0.41 + 0.033*sl 0.43 + 0.027*sl 0.45 + 0.024*sl t r 0.26 0.10 + 0.081*sl 0.08 + 0.090*sl 0.08 + 0.091*sl t f 0.19 0.11 + 0.041*sl 0.11 + 0.041*sl 0.10 + 0.041*sl b to y t plh 0.41 0.33 + 0.041*sl 0.33 + 0.042*sl 0.33 + 0.042*sl t phl 0.49 0.43 + 0.033*sl 0.44 + 0.027*sl 0.46 + 0.024*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.08 + 0.091*sl t f 0.19 0.11 + 0.042*sl 0.11 + 0.040*sl 0.10 + 0.041*sl c to y t plh 0.44 0.36 + 0.041*sl 0.36 + 0.042*sl 0.36 + 0.042*sl t phl 0.51 0.44 + 0.033*sl 0.46 + 0.027*sl 0.47 + 0.024*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.19 0.10 + 0.042*sl 0.11 + 0.041*sl 0.11 + 0.041*sl d to y t plh 0.46 0.38 + 0.042*sl 0.38 + 0.041*sl 0.37 + 0.042*sl t phl 0.50 0.44 + 0.033*sl 0.45 + 0.027*sl 0.47 + 0.024*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.08 + 0.091*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.040*sl 0.10 + 0.041*sl e to y t plh 0.49 0.41 + 0.041*sl 0.41 + 0.041*sl 0.41 + 0.042*sl t phl 0.54 0.47 + 0.033*sl 0.49 + 0.027*sl 0.51 + 0.024*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.19 0.11 + 0.042*sl 0.11 + 0.040*sl 0.10 + 0.041*sl f to y t plh 0.48 0.39 + 0.041*sl 0.39 + 0.041*sl 0.39 + 0.042*sl t phl 0.54 0.48 + 0.033*sl 0.49 + 0.027*sl 0.51 + 0.024*sl t r 0.27 0.09 + 0.086*sl 0.09 + 0.090*sl 0.08 + 0.091*sl t f 0.19 0.11 + 0.041*sl 0.11 + 0.040*sl 0.11 + 0.041*sl g to y t plh 0.45 0.36 + 0.041*sl 0.36 + 0.041*sl 0.36 + 0.042*sl t phl 0.53 0.46 + 0.033*sl 0.48 + 0.027*sl 0.50 + 0.024*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.08 + 0.091*sl t f 0.19 0.11 + 0.041*sl 0.11 + 0.040*sl 0.10 + 0.041*sl h to y t plh 0.42 0.33 + 0.041*sl 0.33 + 0.042*sl 0.33 + 0.042*sl t phl 0.52 0.45 + 0.033*sl 0.47 + 0.027*sl 0.48 + 0.024*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.08 + 0.091*sl t f 0.19 0.11 + 0.041*sl 0.11 + 0.040*sl 0.10 + 0.041*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-40 sec asic nd8/nd8d2 8-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nd8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.37 0.33 + 0.021*sl 0.33 + 0.021*sl 0.33 + 0.021*sl t phl 0.51 0.46 + 0.021*sl 0.47 + 0.016*sl 0.49 + 0.014*sl t r 0.18 0.10 + 0.040*sl 0.09 + 0.044*sl 0.08 + 0.045*sl t f 0.18 0.13 + 0.023*sl 0.14 + 0.020*sl 0.14 + 0.020*sl b to y t plh 0.40 0.36 + 0.021*sl 0.36 + 0.021*sl 0.36 + 0.021*sl t phl 0.52 0.48 + 0.021*sl 0.49 + 0.016*sl 0.51 + 0.014*sl t r 0.18 0.09 + 0.041*sl 0.09 + 0.044*sl 0.08 + 0.045*sl t f 0.18 0.14 + 0.023*sl 0.14 + 0.021*sl 0.15 + 0.020*sl c to y t plh 0.43 0.39 + 0.021*sl 0.39 + 0.021*sl 0.39 + 0.021*sl t phl 0.53 0.49 + 0.021*sl 0.50 + 0.016*sl 0.52 + 0.014*sl t r 0.18 0.10 + 0.040*sl 0.09 + 0.044*sl 0.08 + 0.045*sl t f 0.18 0.13 + 0.023*sl 0.14 + 0.021*sl 0.14 + 0.020*sl d to y t plh 0.45 0.41 + 0.021*sl 0.41 + 0.021*sl 0.41 + 0.021*sl t phl 0.53 0.49 + 0.021*sl 0.50 + 0.016*sl 0.52 + 0.014*sl t r 0.18 0.09 + 0.043*sl 0.09 + 0.043*sl 0.08 + 0.045*sl t f 0.18 0.13 + 0.022*sl 0.14 + 0.021*sl 0.14 + 0.020*sl e to y t plh 0.48 0.44 + 0.021*sl 0.44 + 0.021*sl 0.44 + 0.021*sl t phl 0.57 0.52 + 0.021*sl 0.53 + 0.017*sl 0.55 + 0.014*sl t r 0.18 0.10 + 0.041*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.18 0.14 + 0.022*sl 0.14 + 0.021*sl 0.14 + 0.020*sl f to y t plh 0.47 0.42 + 0.021*sl 0.43 + 0.020*sl 0.42 + 0.021*sl t phl 0.57 0.52 + 0.021*sl 0.54 + 0.017*sl 0.55 + 0.014*sl t r 0.18 0.10 + 0.043*sl 0.10 + 0.043*sl 0.09 + 0.045*sl t f 0.18 0.14 + 0.022*sl 0.14 + 0.021*sl 0.14 + 0.020*sl g to y t plh 0.43 0.39 + 0.021*sl 0.39 + 0.021*sl 0.39 + 0.021*sl t phl 0.55 0.51 + 0.021*sl 0.52 + 0.016*sl 0.54 + 0.014*sl t r 0.18 0.10 + 0.042*sl 0.09 + 0.043*sl 0.09 + 0.044*sl t f 0.18 0.14 + 0.023*sl 0.14 + 0.020*sl 0.15 + 0.020*sl h to y t plh 0.40 0.36 + 0.021*sl 0.36 + 0.021*sl 0.36 + 0.021*sl t phl 0.54 0.50 + 0.021*sl 0.51 + 0.016*sl 0.53 + 0.014*sl t r 0.18 0.10 + 0.040*sl 0.09 + 0.043*sl 0.08 + 0.045*sl t f 0.18 0.14 + 0.022*sl 0.14 + 0.021*sl 0.14 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-41 kg80/KGM80 nd8/nd8d2 8-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.52 0.42 + 0.051*sl 0.42 + 0.050*sl 0.42 + 0.050*sl t phl 0.67 0.59 + 0.037*sl 0.62 + 0.028*sl 0.66 + 0.024*sl t r 0.34 0.13 + 0.106*sl 0.12 + 0.109*sl 0.11 + 0.109*sl t f 0.23 0.14 + 0.046*sl 0.15 + 0.042*sl 0.15 + 0.042*sl b to y t plh 0.56 0.46 + 0.050*sl 0.46 + 0.050*sl 0.46 + 0.050*sl t phl 0.70 0.62 + 0.038*sl 0.65 + 0.028*sl 0.69 + 0.024*sl t r 0.34 0.13 + 0.106*sl 0.12 + 0.109*sl 0.11 + 0.109*sl t f 0.23 0.14 + 0.045*sl 0.15 + 0.042*sl 0.15 + 0.042*sl c to y t plh 0.61 0.51 + 0.051*sl 0.51 + 0.050*sl 0.51 + 0.050*sl t phl 0.73 0.66 + 0.038*sl 0.68 + 0.028*sl 0.72 + 0.024*sl t r 0.34 0.13 + 0.106*sl 0.12 + 0.109*sl 0.11 + 0.109*sl t f 0.23 0.14 + 0.046*sl 0.15 + 0.042*sl 0.15 + 0.042*sl d to y t plh 0.63 0.53 + 0.050*sl 0.53 + 0.050*sl 0.53 + 0.050*sl t phl 0.74 0.66 + 0.038*sl 0.69 + 0.028*sl 0.73 + 0.024*sl t r 0.34 0.13 + 0.106*sl 0.12 + 0.109*sl 0.11 + 0.109*sl t f 0.23 0.14 + 0.046*sl 0.15 + 0.042*sl 0.15 + 0.042*sl e to y t plh 0.68 0.58 + 0.050*sl 0.58 + 0.050*sl 0.58 + 0.050*sl t phl 0.80 0.73 + 0.038*sl 0.76 + 0.028*sl 0.80 + 0.024*sl t r 0.34 0.14 + 0.105*sl 0.12 + 0.108*sl 0.12 + 0.109*sl t f 0.23 0.15 + 0.045*sl 0.15 + 0.042*sl 0.15 + 0.042*sl f to y t plh 0.66 0.55 + 0.050*sl 0.55 + 0.050*sl 0.56 + 0.050*sl t phl 0.80 0.72 + 0.038*sl 0.75 + 0.028*sl 0.79 + 0.024*sl t r 0.34 0.13 + 0.105*sl 0.12 + 0.108*sl 0.12 + 0.109*sl t f 0.24 0.14 + 0.046*sl 0.16 + 0.042*sl 0.15 + 0.042*sl g to y t plh 0.61 0.51 + 0.051*sl 0.51 + 0.050*sl 0.51 + 0.050*sl t phl 0.76 0.69 + 0.038*sl 0.72 + 0.028*sl 0.76 + 0.024*sl t r 0.34 0.13 + 0.106*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.23 0.14 + 0.046*sl 0.15 + 0.042*sl 0.15 + 0.042*sl h to y t plh 0.57 0.46 + 0.051*sl 0.47 + 0.050*sl 0.47 + 0.050*sl t phl 0.74 0.66 + 0.038*sl 0.69 + 0.028*sl 0.73 + 0.024*sl t r 0.34 0.13 + 0.106*sl 0.12 + 0.108*sl 0.12 + 0.109*sl t f 0.23 0.14 + 0.046*sl 0.15 + 0.042*sl 0.15 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-42 sec asic nd8/nd8d2 8-input nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nd8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.50 0.45 + 0.026*sl 0.45 + 0.025*sl 0.46 + 0.025*sl t phl 0.72 0.68 + 0.025*sl 0.69 + 0.018*sl 0.73 + 0.014*sl t r 0.24 0.13 + 0.051*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.23 0.17 + 0.025*sl 0.18 + 0.022*sl 0.20 + 0.021*sl b to y t plh 0.55 0.50 + 0.026*sl 0.50 + 0.025*sl 0.50 + 0.025*sl t phl 0.75 0.70 + 0.025*sl 0.72 + 0.018*sl 0.76 + 0.014*sl t r 0.24 0.14 + 0.050*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.23 0.17 + 0.026*sl 0.18 + 0.022*sl 0.20 + 0.021*sl c to y t plh 0.60 0.55 + 0.026*sl 0.55 + 0.025*sl 0.55 + 0.025*sl t phl 0.79 0.74 + 0.024*sl 0.76 + 0.018*sl 0.80 + 0.014*sl t r 0.24 0.13 + 0.051*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.23 0.17 + 0.025*sl 0.18 + 0.022*sl 0.20 + 0.021*sl d to y t plh 0.62 0.57 + 0.026*sl 0.57 + 0.025*sl 0.57 + 0.025*sl t phl 0.79 0.74 + 0.025*sl 0.76 + 0.018*sl 0.80 + 0.014*sl t r 0.24 0.14 + 0.050*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.23 0.18 + 0.025*sl 0.18 + 0.022*sl 0.20 + 0.021*sl e to y t plh 0.67 0.62 + 0.026*sl 0.62 + 0.025*sl 0.62 + 0.025*sl t phl 0.86 0.81 + 0.025*sl 0.83 + 0.018*sl 0.87 + 0.014*sl t r 0.24 0.14 + 0.051*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.23 0.18 + 0.026*sl 0.19 + 0.022*sl 0.21 + 0.021*sl f to y t plh 0.64 0.59 + 0.026*sl 0.59 + 0.025*sl 0.60 + 0.025*sl t phl 0.86 0.81 + 0.025*sl 0.83 + 0.018*sl 0.87 + 0.014*sl t r 0.24 0.14 + 0.051*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.23 0.18 + 0.026*sl 0.19 + 0.022*sl 0.21 + 0.021*sl g to y t plh 0.59 0.54 + 0.026*sl 0.55 + 0.025*sl 0.55 + 0.025*sl t phl 0.82 0.77 + 0.025*sl 0.79 + 0.018*sl 0.83 + 0.014*sl t r 0.24 0.14 + 0.052*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.23 0.18 + 0.026*sl 0.19 + 0.022*sl 0.21 + 0.021*sl h to y t plh 0.55 0.50 + 0.026*sl 0.50 + 0.025*sl 0.50 + 0.025*sl t phl 0.79 0.74 + 0.025*sl 0.76 + 0.018*sl 0.80 + 0.014*sl t r 0.24 0.14 + 0.051*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.23 0.18 + 0.026*sl 0.19 + 0.022*sl 0.21 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-43 kg80/KGM80 nr2/nr2d2 2-input nor with 1x/2x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nr2 kg80 nr2d2 input load (sl) gate count kg80 nr2 nr2d2 nr2 nr2d2 abab 0.5 0.7 1.1 1.5 1.0 2.0 KGM80 nr2 nr2d2 nr2 nr2d2 abab 1.0 1.0 2.1 1.9 1.0 2.0 y a b [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.31 0.17 + 0.068*sl 0.17 + 0.069*sl 0.16 + 0.070*sl t phl 0.10 0.02 + 0.040*sl 0.05 + 0.027*sl 0.08 + 0.023*sl t r 0.51 0.20 + 0.154*sl 0.19 + 0.159*sl 0.16 + 0.163*sl t f 0.22 0.14 + 0.040*sl 0.15 + 0.036*sl 0.13 + 0.038*sl b to y t plh 0.31 0.17 + 0.068*sl 0.17 + 0.069*sl 0.16 + 0.071*sl t phl 0.12 0.05 + 0.037*sl 0.07 + 0.026*sl 0.09 + 0.023*sl t r 0.51 0.21 + 0.152*sl 0.19 + 0.159*sl 0.17 + 0.162*sl t f 0.25 0.18 + 0.036*sl 0.17 + 0.037*sl 0.17 + 0.038*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.23 0.16 + 0.036*sl 0.17 + 0.033*sl 0.16 + 0.034*sl t phl 0.06 0.01 + 0.024*sl 0.03 + 0.017*sl 0.05 + 0.014*sl t r 0.34 0.19 + 0.074*sl 0.19 + 0.077*sl 0.17 + 0.080*sl t f 0.18 0.13 + 0.024*sl 0.14 + 0.020*sl 0.16 + 0.017*sl b to y t plh 0.24 0.17 + 0.036*sl 0.17 + 0.034*sl 0.17 + 0.035*sl t phl 0.08 0.04 + 0.022*sl 0.06 + 0.016*sl 0.07 + 0.013*sl t r 0.35 0.20 + 0.073*sl 0.19 + 0.077*sl 0.17 + 0.080*sl t f 0.22 0.17 + 0.022*sl 0.17 + 0.021*sl 0.21 + 0.015*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = truth table aby 001 010 100 110
kg80/KGM80 3-44 sec asic nr2/nr2d2 2-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nr2 KGM80 nr2d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.39 0.21 + 0.092*sl 0.21 + 0.093*sl 0.20 + 0.094*sl t phl 0.13 0.05 + 0.037*sl 0.08 + 0.026*sl 0.11 + 0.023*sl t r 0.69 0.28 + 0.201*sl 0.27 + 0.206*sl 0.24 + 0.208*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.039*sl 0.12 + 0.041*sl b to y t plh 0.42 0.23 + 0.094*sl 0.23 + 0.094*sl 0.23 + 0.094*sl t phl 0.15 0.08 + 0.035*sl 0.10 + 0.025*sl 0.13 + 0.023*sl t r 0.69 0.29 + 0.200*sl 0.27 + 0.206*sl 0.25 + 0.208*sl t f 0.25 0.17 + 0.041*sl 0.17 + 0.039*sl 0.14 + 0.041*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.28 0.18 + 0.049*sl 0.19 + 0.046*sl 0.18 + 0.047*sl t phl 0.08 0.04 + 0.023*sl 0.05 + 0.016*sl 0.09 + 0.012*sl t r 0.46 0.26 + 0.099*sl 0.25 + 0.102*sl 0.24 + 0.103*sl t f 0.17 0.12 + 0.024*sl 0.13 + 0.020*sl 0.13 + 0.019*sl b to y t plh 0.33 0.23 + 0.050*sl 0.24 + 0.047*sl 0.24 + 0.047*sl t phl 0.11 0.07 + 0.021*sl 0.08 + 0.015*sl 0.12 + 0.012*sl t r 0.47 0.27 + 0.096*sl 0.26 + 0.101*sl 0.24 + 0.103*sl t f 0.21 0.17 + 0.022*sl 0.18 + 0.019*sl 0.17 + 0.019*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-45 kg80/KGM80 nr3/nr3d2 3-input nor with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 nr3 nr3d2 nr3 nr3d2 abcabc 0.5 0.7 0.7 1.0 1.4 0.14 2.0 3.0 KGM80 nr3 nr3d2 nr3 nr3d2 abcabc 1.0 1.0 1.0 2.1 2.0 1.9 2.0 3.0 y a b c truth table abcy 0001 1xx0 x1x0 xx10
kg80/KGM80 3-46 sec asic nr3/nr3d2 3-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nr3 kg80 nr3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.47 0.28 + 0.097*sl 0.27 + 0.100*sl 0.26 + 0.101*sl t phl 0.13 0.07 + 0.033*sl 0.09 + 0.025*sl 0.10 + 0.023*sl t r 0.97 0.51 + 0.232*sl 0.50 + 0.236*sl 0.49 + 0.238*sl t f 0.25 0.18 + 0.036*sl 0.17 + 0.038*sl 0.16 + 0.039*sl b to y t plh 0.52 0.32 + 0.100*sl 0.32 + 0.101*sl 0.31 + 0.102*sl t phl 0.16 0.09 + 0.032*sl 0.11 + 0.024*sl 0.12 + 0.023*sl t r 0.99 0.53 + 0.230*sl 0.52 + 0.235*sl 0.50 + 0.236*sl t f 0.28 0.21 + 0.034*sl 0.21 + 0.038*sl 0.20 + 0.039*sl c to y t plh 0.53 0.32 + 0.102*sl 0.32 + 0.102*sl 0.32 + 0.102*sl t phl 0.16 0.10 + 0.030*sl 0.11 + 0.026*sl 0.12 + 0.024*sl t r 0.99 0.52 + 0.231*sl 0.51 + 0.235*sl 0.50 + 0.236*sl t f 0.31 0.23 + 0.041*sl 0.24 + 0.036*sl 0.22 + 0.039*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.31 0.22 + 0.046*sl 0.22 + 0.049*sl 0.21 + 0.050*sl t phl 0.07 0.03 + 0.022*sl 0.04 + 0.017*sl 0.07 + 0.013*sl t r 0.58 0.35 + 0.114*sl 0.35 + 0.116*sl 0.34 + 0.118*sl t f 0.19 0.15 + 0.022*sl 0.15 + 0.018*sl 0.15 + 0.019*sl b to y t plh 0.35 0.25 + 0.050*sl 0.25 + 0.050*sl 0.24 + 0.051*sl t phl 0.09 0.05 + 0.020*sl 0.06 + 0.016*sl 0.09 + 0.013*sl t r 0.60 0.37 + 0.113*sl 0.37 + 0.115*sl 0.35 + 0.117*sl t f 0.22 0.19 + 0.019*sl 0.19 + 0.018*sl 0.19 + 0.018*sl c to y t plh 0.37 0.27 + 0.051*sl 0.27 + 0.051*sl 0.27 + 0.051*sl t phl 0.10 0.06 + 0.022*sl 0.07 + 0.016*sl 0.09 + 0.013*sl t r 0.59 0.37 + 0.114*sl 0.36 + 0.116*sl 0.35 + 0.118*sl t f 0.25 0.21 + 0.020*sl 0.21 + 0.019*sl 0.22 + 0.018*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-47 kg80/KGM80 nr3/nr3d2 3-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nr3 KGM80 nr3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.66 0.38 + 0.138*sl 0.38 + 0.138*sl 0.38 + 0.139*sl t phl 0.17 0.10 + 0.032*sl 0.13 + 0.024*sl 0.14 + 0.023*sl t r 1.43 0.82 + 0.307*sl 0.81 + 0.309*sl 0.82 + 0.308*sl t f 0.26 0.19 + 0.039*sl 0.18 + 0.040*sl 0.16 + 0.042*sl b to y t plh 0.78 0.50 + 0.140*sl 0.51 + 0.140*sl 0.51 + 0.139*sl t phl 0.19 0.13 + 0.031*sl 0.15 + 0.024*sl 0.16 + 0.023*sl t r 1.45 0.85 + 0.302*sl 0.83 + 0.307*sl 0.82 + 0.308*sl t f 0.30 0.22 + 0.039*sl 0.22 + 0.039*sl 0.20 + 0.042*sl c to y t plh 0.82 0.54 + 0.141*sl 0.54 + 0.140*sl 0.55 + 0.139*sl t phl 0.20 0.14 + 0.031*sl 0.15 + 0.025*sl 0.17 + 0.024*sl t r 1.45 0.84 + 0.303*sl 0.83 + 0.307*sl 0.82 + 0.308*sl t f 0.32 0.25 + 0.038*sl 0.24 + 0.040*sl 0.22 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.41 0.28 + 0.067*sl 0.27 + 0.069*sl 0.27 + 0.069*sl t phl 0.10 0.06 + 0.020*sl 0.07 + 0.015*sl 0.11 + 0.012*sl t r 0.84 0.53 + 0.152*sl 0.53 + 0.154*sl 0.52 + 0.155*sl t f 0.19 0.14 + 0.023*sl 0.15 + 0.019*sl 0.15 + 0.020*sl b to y t plh 0.51 0.37 + 0.070*sl 0.37 + 0.070*sl 0.37 + 0.070*sl t phl 0.13 0.09 + 0.019*sl 0.10 + 0.015*sl 0.13 + 0.012*sl t r 0.87 0.57 + 0.149*sl 0.56 + 0.152*sl 0.54 + 0.154*sl t f 0.23 0.18 + 0.022*sl 0.19 + 0.019*sl 0.18 + 0.020*sl c to y t plh 0.58 0.44 + 0.072*sl 0.44 + 0.070*sl 0.45 + 0.070*sl t phl 0.13 0.09 + 0.020*sl 0.10 + 0.015*sl 0.14 + 0.012*sl t r 0.86 0.57 + 0.149*sl 0.56 + 0.152*sl 0.54 + 0.154*sl t f 0.25 0.21 + 0.022*sl 0.22 + 0.020*sl 0.21 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-48 sec asic nr4/nr4d2 4-input nor with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 nr4 nr4d2 nr4 nr4d2 abcdabcd 0.5 0.7 0.7 0.7 1.1 1.3 1.4 1.5 2.0 4.0 KGM80 nr4 nr4d2 nr4 nr4d2 abcdabcd 1.0 1.0 1.0 1.0 2.1 1.9 1.9 1.9 2.0 4.0 y a b c d truth table abcdy 00001 1xxx0 x1xx0 xx1x0 xxx10
sec asic 3-49 kg80/KGM80 nr4/nr4d2 4-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nr4 kg80 nr4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.50 0.24 + 0.126*sl 0.23 + 0.130*sl 0.22 + 0.132*sl t phl 0.11 0.04 + 0.037*sl 0.07 + 0.026*sl 0.09 + 0.023*sl t r 1.12 0.51 + 0.308*sl 0.50 + 0.312*sl 0.50 + 0.312*sl t f 0.23 0.15 + 0.040*sl 0.16 + 0.037*sl 0.15 + 0.039*sl b to y t plh 0.55 0.29 + 0.130*sl 0.29 + 0.132*sl 0.28 + 0.133*sl t phl 0.13 0.06 + 0.035*sl 0.08 + 0.025*sl 0.10 + 0.023*sl t r 1.15 0.54 + 0.304*sl 0.53 + 0.309*sl 0.52 + 0.310*sl t f 0.26 0.18 + 0.036*sl 0.18 + 0.037*sl 0.17 + 0.039*sl c to y t plh 0.61 0.35 + 0.134*sl 0.35 + 0.134*sl 0.35 + 0.134*sl t phl 0.14 0.07 + 0.036*sl 0.09 + 0.026*sl 0.11 + 0.024*sl t r 1.16 0.55 + 0.302*sl 0.54 + 0.308*sl 0.52 + 0.310*sl t f 0.28 0.21 + 0.036*sl 0.21 + 0.038*sl 0.20 + 0.039*sl d to y t plh 0.63 0.36 + 0.135*sl 0.36 + 0.135*sl 0.37 + 0.134*sl t phl 0.14 0.06 + 0.037*sl 0.09 + 0.026*sl 0.11 + 0.024*sl t r 1.15 0.55 + 0.303*sl 0.53 + 0.309*sl 0.52 + 0.310*sl t f 0.30 0.22 + 0.038*sl 0.22 + 0.039*sl 0.21 + 0.039*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.35 0.23 + 0.059*sl 0.22 + 0.064*sl 0.21 + 0.065*sl t phl 0.07 0.03 + 0.022*sl 0.04 + 0.017*sl 0.07 + 0.013*sl t r 0.80 0.50 + 0.152*sl 0.49 + 0.155*sl 0.48 + 0.157*sl t f 0.19 0.14 + 0.021*sl 0.15 + 0.019*sl 0.16 + 0.018*sl b to y t plh 0.43 0.29 + 0.066*sl 0.29 + 0.066*sl 0.29 + 0.066*sl t phl 0.10 0.06 + 0.021*sl 0.07 + 0.016*sl 0.09 + 0.012*sl t r 0.85 0.55 + 0.149*sl 0.54 + 0.153*sl 0.53 + 0.155*sl t f 0.22 0.19 + 0.019*sl 0.19 + 0.017*sl 0.18 + 0.020*sl c to y t plh 0.48 0.34 + 0.068*sl 0.35 + 0.067*sl 0.35 + 0.067*sl t phl 0.10 0.06 + 0.021*sl 0.07 + 0.017*sl 0.10 + 0.012*sl t r 0.85 0.56 + 0.148*sl 0.55 + 0.152*sl 0.53 + 0.154*sl t f 0.25 0.21 + 0.020*sl 0.21 + 0.018*sl 0.20 + 0.019*sl d to y t plh 0.50 0.36 + 0.068*sl 0.36 + 0.068*sl 0.37 + 0.067*sl t phl 0.10 0.06 + 0.022*sl 0.07 + 0.016*sl 0.09 + 0.013*sl t r 0.85 0.55 + 0.148*sl 0.54 + 0.153*sl 0.53 + 0.154*sl t f 0.26 0.21 + 0.022*sl 0.22 + 0.020*sl 0.23 + 0.019*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-50 sec asic nr4/nr4d2 4-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nr4 KGM80 nr4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.68 0.31 + 0.182*sl 0.31 + 0.184*sl 0.30 + 0.184*sl t phl 0.14 0.07 + 0.035*sl 0.10 + 0.025*sl 0.12 + 0.023*sl t r 1.61 0.79 + 0.411*sl 0.79 + 0.412*sl 0.82 + 0.408*sl t f 0.24 0.15 + 0.042*sl 0.16 + 0.039*sl 0.13 + 0.042*sl b to y t plh 0.81 0.43 + 0.186*sl 0.43 + 0.185*sl 0.44 + 0.185*sl t phl 0.16 0.10 + 0.033*sl 0.12 + 0.025*sl 0.14 + 0.023*sl t r 1.66 0.85 + 0.402*sl 0.84 + 0.407*sl 0.83 + 0.408*sl t f 0.27 0.19 + 0.039*sl 0.19 + 0.039*sl 0.16 + 0.042*sl c to y t plh 0.96 0.58 + 0.189*sl 0.59 + 0.186*sl 0.59 + 0.185*sl t phl 0.17 0.10 + 0.035*sl 0.13 + 0.025*sl 0.15 + 0.024*sl t r 1.66 0.86 + 0.401*sl 0.85 + 0.407*sl 0.83 + 0.408*sl t f 0.29 0.21 + 0.042*sl 0.22 + 0.039*sl 0.19 + 0.042*sl d to y t plh 1.00 0.62 + 0.189*sl 0.63 + 0.186*sl 0.64 + 0.185*sl t phl 0.17 0.10 + 0.035*sl 0.12 + 0.026*sl 0.14 + 0.024*sl t r 1.66 0.86 + 0.402*sl 0.85 + 0.407*sl 0.83 + 0.408*sl t f 0.30 0.22 + 0.042*sl 0.22 + 0.041*sl 0.21 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.45 0.28 + 0.085*sl 0.26 + 0.091*sl 0.25 + 0.092*sl t phl 0.10 0.06 + 0.020*sl 0.07 + 0.015*sl 0.11 + 0.012*sl t r 1.16 0.75 + 0.206*sl 0.75 + 0.207*sl 0.75 + 0.207*sl t f 0.19 0.14 + 0.023*sl 0.15 + 0.020*sl 0.15 + 0.020*sl b to y t plh 0.64 0.45 + 0.095*sl 0.46 + 0.093*sl 0.46 + 0.093*sl t phl 0.13 0.09 + 0.019*sl 0.10 + 0.015*sl 0.13 + 0.012*sl t r 1.25 0.85 + 0.198*sl 0.84 + 0.202*sl 0.83 + 0.204*sl t f 0.23 0.19 + 0.022*sl 0.19 + 0.019*sl 0.19 + 0.020*sl c to y t plh 0.77 0.58 + 0.096*sl 0.58 + 0.094*sl 0.59 + 0.093*sl t phl 0.13 0.09 + 0.020*sl 0.11 + 0.015*sl 0.14 + 0.012*sl t r 1.26 0.86 + 0.198*sl 0.85 + 0.202*sl 0.83 + 0.204*sl t f 0.25 0.21 + 0.022*sl 0.22 + 0.020*sl 0.21 + 0.020*sl d to y t plh 0.82 0.62 + 0.096*sl 0.63 + 0.094*sl 0.64 + 0.093*sl t phl 0.13 0.09 + 0.020*sl 0.10 + 0.015*sl 0.14 + 0.012*sl t r 1.25 0.86 + 0.198*sl 0.85 + 0.202*sl 0.83 + 0.204*sl t f 0.26 0.22 + 0.022*sl 0.22 + 0.020*sl 0.22 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-51 kg80/KGM80 nr5/nr5d2 5-input nor with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 nr5 nr5d2 nr5 nr5d2 abcdeabcde 0.5 0.7 0.7 0.6 0.8 0.5 08 0.9 0.9 0.9 4.0 5.0 KGM80 nr5 nr5d2 nr5 nr5d2 abcdeabcde 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 4.0 5.0 y b c d e a truth table abcdey 000001 1xxxx0 x1xxx0 xx1xx0 xxx1x0 xxxx10
kg80/KGM80 3-52 sec asic nr5/nr5d2 5-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nr5 kg80 nr5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.57 0.49 + 0.043*sl 0.49 + 0.041*sl 0.49 + 0.042*sl t phl 0.27 0.21 + 0.028*sl 0.22 + 0.024*sl 0.23 + 0.023*sl t r 0.28 0.11 + 0.087*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.15 0.08 + 0.038*sl 0.07 + 0.041*sl 0.06 + 0.042*sl b to y t plh 0.60 0.51 + 0.043*sl 0.51 + 0.042*sl 0.51 + 0.042*sl t phl 0.29 0.24 + 0.028*sl 0.25 + 0.024*sl 0.25 + 0.023*sl t r 0.28 0.11 + 0.087*sl 0.10 + 0.089*sl 0.09 + 0.090*sl t f 0.15 0.08 + 0.037*sl 0.07 + 0.041*sl 0.06 + 0.042*sl c to y t plh 0.62 0.53 + 0.043*sl 0.54 + 0.041*sl 0.53 + 0.042*sl t phl 0.31 0.25 + 0.028*sl 0.26 + 0.024*sl 0.27 + 0.023*sl t r 0.28 0.10 + 0.087*sl 0.10 + 0.089*sl 0.09 + 0.090*sl t f 0.15 0.07 + 0.039*sl 0.07 + 0.041*sl 0.06 + 0.042*sl d to y t plh 0.49 0.40 + 0.043*sl 0.40 + 0.042*sl 0.40 + 0.042*sl t phl 0.28 0.22 + 0.030*sl 0.23 + 0.024*sl 0.24 + 0.023*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl e to y t plh 0.48 0.40 + 0.043*sl 0.40 + 0.042*sl 0.40 + 0.042*sl t phl 0.31 0.25 + 0.030*sl 0.26 + 0.024*sl 0.27 + 0.023*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.54 0.49 + 0.026*sl 0.50 + 0.022*sl 0.51 + 0.021*sl t phl 0.27 0.23 + 0.019*sl 0.24 + 0.015*sl 0.26 + 0.013*sl t r 0.20 0.12 + 0.043*sl 0.12 + 0.042*sl 0.11 + 0.043*sl t f 0.12 0.08 + 0.022*sl 0.08 + 0.020*sl 0.08 + 0.020*sl b to y t plh 0.54 0.49 + 0.026*sl 0.50 + 0.022*sl 0.51 + 0.021*sl t phl 0.29 0.26 + 0.019*sl 0.27 + 0.015*sl 0.28 + 0.013*sl t r 0.20 0.12 + 0.042*sl 0.12 + 0.043*sl 0.11 + 0.044*sl t f 0.13 0.08 + 0.021*sl 0.09 + 0.020*sl 0.08 + 0.020*sl c to y t plh 0.55 0.50 + 0.026*sl 0.51 + 0.022*sl 0.52 + 0.021*sl t phl 0.29 0.25 + 0.021*sl 0.27 + 0.015*sl 0.28 + 0.013*sl t r 0.20 0.12 + 0.041*sl 0.12 + 0.043*sl 0.11 + 0.043*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl d to y t plh 0.55 0.50 + 0.026*sl 0.51 + 0.022*sl 0.52 + 0.021*sl t phl 0.32 0.28 + 0.020*sl 0.29 + 0.015*sl 0.31 + 0.013*sl t r 0.20 0.12 + 0.042*sl 0.12 + 0.043*sl 0.11 + 0.043*sl t f 0.14 0.09 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.020*sl e to y t plh 0.49 0.44 + 0.026*sl 0.45 + 0.023*sl 0.46 + 0.021*sl t phl 0.32 0.28 + 0.022*sl 0.29 + 0.016*sl 0.31 + 0.014*sl t r 0.20 0.12 + 0.042*sl 0.12 + 0.042*sl 0.11 + 0.044*sl t f 0.15 0.11 + 0.023*sl 0.11 + 0.020*sl 0.12 + 0.020*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 7, *grou p 3 : 7 < sl < < = =
sec asic 3-53 kg80/KGM80 nr5/nr5d2 5-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nr5 KGM80 nr5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.80 0.69 + 0.052*sl 0.70 + 0.050*sl 0.70 + 0.050*sl t phl 0.38 0.32 + 0.030*sl 0.33 + 0.024*sl 0.34 + 0.023*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.107*sl 0.13 + 0.109*sl t f 0.18 0.09 + 0.043*sl 0.09 + 0.042*sl 0.08 + 0.043*sl b to y t plh 0.87 0.77 + 0.052*sl 0.77 + 0.050*sl 0.78 + 0.050*sl t phl 0.40 0.34 + 0.030*sl 0.36 + 0.024*sl 0.37 + 0.023*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.107*sl 0.13 + 0.109*sl t f 0.18 0.09 + 0.042*sl 0.09 + 0.042*sl 0.08 + 0.043*sl c to y t plh 0.94 0.83 + 0.052*sl 0.84 + 0.050*sl 0.84 + 0.050*sl t phl 0.41 0.35 + 0.030*sl 0.37 + 0.024*sl 0.38 + 0.023*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.107*sl 0.13 + 0.109*sl t f 0.18 0.09 + 0.042*sl 0.10 + 0.042*sl 0.08 + 0.043*sl d to y t plh 0.65 0.55 + 0.052*sl 0.55 + 0.050*sl 0.56 + 0.050*sl t phl 0.40 0.33 + 0.031*sl 0.35 + 0.025*sl 0.37 + 0.023*sl t r 0.36 0.15 + 0.105*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.19 0.11 + 0.041*sl 0.10 + 0.041*sl 0.09 + 0.043*sl e to y t plh 0.67 0.57 + 0.053*sl 0.58 + 0.050*sl 0.58 + 0.050*sl t phl 0.42 0.36 + 0.031*sl 0.38 + 0.025*sl 0.39 + 0.023*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.19 0.10 + 0.041*sl 0.11 + 0.041*sl 0.09 + 0.043*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.74 0.67 + 0.033*sl 0.69 + 0.027*sl 0.71 + 0.025*sl t phl 0.39 0.35 + 0.022*sl 0.36 + 0.016*sl 0.40 + 0.013*sl t r 0.26 0.15 + 0.055*sl 0.16 + 0.052*sl 0.15 + 0.053*sl t f 0.15 0.10 + 0.023*sl 0.11 + 0.021*sl 0.12 + 0.021*sl b to y t plh 0.76 0.69 + 0.033*sl 0.71 + 0.027*sl 0.73 + 0.025*sl t phl 0.42 0.37 + 0.022*sl 0.39 + 0.016*sl 0.42 + 0.013*sl t r 0.26 0.15 + 0.054*sl 0.16 + 0.052*sl 0.15 + 0.053*sl t f 0.15 0.10 + 0.026*sl 0.11 + 0.021*sl 0.12 + 0.021*sl c to y t plh 0.75 0.69 + 0.033*sl 0.70 + 0.027*sl 0.73 + 0.025*sl t phl 0.43 0.38 + 0.024*sl 0.40 + 0.016*sl 0.44 + 0.013*sl t r 0.26 0.15 + 0.056*sl 0.16 + 0.052*sl 0.15 + 0.053*sl t f 0.16 0.12 + 0.024*sl 0.13 + 0.021*sl 0.13 + 0.020*sl d to y t plh 0.78 0.71 + 0.033*sl 0.72 + 0.028*sl 0.75 + 0.025*sl t phl 0.46 0.41 + 0.023*sl 0.43 + 0.016*sl 0.46 + 0.013*sl t r 0.26 0.15 + 0.056*sl 0.16 + 0.052*sl 0.15 + 0.053*sl t f 0.17 0.12 + 0.024*sl 0.13 + 0.021*sl 0.13 + 0.020*sl e to y t plh 0.66 0.59 + 0.033*sl 0.61 + 0.028*sl 0.63 + 0.025*sl t phl 0.46 0.41 + 0.025*sl 0.43 + 0.017*sl 0.47 + 0.013*sl t r 0.26 0.15 + 0.056*sl 0.16 + 0.052*sl 0.15 + 0.053*sl t f 0.18 0.13 + 0.026*sl 0.14 + 0.021*sl 0.15 + 0.020*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 11, *grou p 3 : 11 < sl < < = =
kg80/KGM80 3-54 sec asic nr6/nr6d2 6-input nor with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 nr6 nr6d2 nr6 nr6d2 abcdefabcdef 0.6 0.8 0.9 0.9 0.9 0.9 0.6 0.8 0.9 0.9 0.9 0.9 5.0 6.0 KGM80 nr6 nr6d2 nr6 nr6d2 abcdefabcdef 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 6.0 y b c d e a f truth table abcdefy 0000001 1xxxxx0 x1xxxx0 xx1xxx0 xxx1xx0 xxxx1x0 xxxxx10
sec asic 3-55 kg80/KGM80 nr6/nr6d2 6-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nr6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.54 0.45 + 0.045*sl 0.46 + 0.042*sl 0.46 + 0.042*sl t phl 0.27 0.22 + 0.028*sl 0.22 + 0.025*sl 0.23 + 0.023*sl t r 0.29 0.12 + 0.086*sl 0.12 + 0.088*sl 0.10 + 0.090*sl t f 0.16 0.08 + 0.039*sl 0.08 + 0.040*sl 0.07 + 0.042*sl b to y t plh 0.54 0.45 + 0.045*sl 0.46 + 0.042*sl 0.46 + 0.042*sl t phl 0.30 0.24 + 0.030*sl 0.25 + 0.025*sl 0.26 + 0.023*sl t r 0.29 0.12 + 0.084*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.16 0.08 + 0.039*sl 0.08 + 0.041*sl 0.07 + 0.042*sl c to y t plh 0.56 0.47 + 0.045*sl 0.48 + 0.042*sl 0.48 + 0.042*sl t phl 0.30 0.24 + 0.031*sl 0.25 + 0.025*sl 0.27 + 0.023*sl t r 0.29 0.12 + 0.086*sl 0.12 + 0.088*sl 0.10 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl d to y t plh 0.56 0.47 + 0.045*sl 0.48 + 0.042*sl 0.48 + 0.042*sl t phl 0.33 0.26 + 0.031*sl 0.28 + 0.025*sl 0.29 + 0.023*sl t r 0.29 0.12 + 0.086*sl 0.12 + 0.088*sl 0.10 + 0.090*sl t f 0.17 0.09 + 0.038*sl 0.09 + 0.040*sl 0.08 + 0.042*sl e to y t plh 0.57 0.48 + 0.045*sl 0.49 + 0.042*sl 0.49 + 0.041*sl t phl 0.33 0.26 + 0.032*sl 0.28 + 0.026*sl 0.30 + 0.023*sl t r 0.29 0.12 + 0.086*sl 0.11 + 0.088*sl 0.11 + 0.089*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.040*sl 0.10 + 0.041*sl f to y t plh 0.57 0.48 + 0.045*sl 0.49 + 0.042*sl 0.49 + 0.041*sl t phl 0.35 0.29 + 0.033*sl 0.30 + 0.026*sl 0.32 + 0.024*sl t r 0.29 0.12 + 0.086*sl 0.12 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.10 + 0.041*sl 0.11 + 0.040*sl 0.10 + 0.040*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-56 sec asic nr6/nr6d2 6-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nr6d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.56 0.52 + 0.021*sl 0.53 + 0.017*sl 0.54 + 0.015*sl t phl 0.32 0.28 + 0.018*sl 0.29 + 0.015*sl 0.31 + 0.013*sl t r 0.20 0.14 + 0.026*sl 0.14 + 0.028*sl 0.14 + 0.028*sl t f 0.15 0.11 + 0.021*sl 0.11 + 0.020*sl 0.11 + 0.020*sl b to y t plh 0.56 0.51 + 0.021*sl 0.52 + 0.017*sl 0.54 + 0.015*sl t phl 0.35 0.31 + 0.019*sl 0.32 + 0.015*sl 0.33 + 0.013*sl t r 0.20 0.15 + 0.026*sl 0.15 + 0.027*sl 0.14 + 0.028*sl t f 0.15 0.11 + 0.021*sl 0.11 + 0.020*sl 0.11 + 0.020*sl c to y t plh 0.57 0.53 + 0.021*sl 0.54 + 0.017*sl 0.55 + 0.015*sl t phl 0.35 0.31 + 0.019*sl 0.32 + 0.015*sl 0.34 + 0.013*sl t r 0.20 0.15 + 0.028*sl 0.15 + 0.027*sl 0.14 + 0.028*sl t f 0.16 0.12 + 0.021*sl 0.12 + 0.020*sl 0.12 + 0.020*sl d to y t plh 0.57 0.53 + 0.021*sl 0.54 + 0.017*sl 0.55 + 0.015*sl t phl 0.37 0.33 + 0.019*sl 0.34 + 0.015*sl 0.36 + 0.013*sl t r 0.20 0.15 + 0.027*sl 0.15 + 0.027*sl 0.14 + 0.028*sl t f 0.16 0.12 + 0.023*sl 0.12 + 0.019*sl 0.12 + 0.020*sl e to y t plh 0.59 0.54 + 0.021*sl 0.55 + 0.017*sl 0.56 + 0.015*sl t phl 0.38 0.34 + 0.021*sl 0.35 + 0.016*sl 0.37 + 0.014*sl t r 0.20 0.15 + 0.026*sl 0.14 + 0.028*sl 0.14 + 0.028*sl t f 0.18 0.13 + 0.023*sl 0.14 + 0.019*sl 0.14 + 0.019*sl f to y t plh 0.58 0.54 + 0.021*sl 0.55 + 0.017*sl 0.56 + 0.015*sl t phl 0.40 0.36 + 0.021*sl 0.37 + 0.016*sl 0.39 + 0.014*sl t r 0.20 0.15 + 0.027*sl 0.14 + 0.027*sl 0.14 + 0.028*sl t f 0.18 0.14 + 0.022*sl 0.14 + 0.019*sl 0.14 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-57 kg80/KGM80 nr6/nr6d2 6-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nr6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.74 0.63 + 0.056*sl 0.64 + 0.051*sl 0.65 + 0.050*sl t phl 0.38 0.32 + 0.032*sl 0.34 + 0.025*sl 0.36 + 0.023*sl t r 0.38 0.17 + 0.104*sl 0.17 + 0.106*sl 0.15 + 0.108*sl t f 0.19 0.10 + 0.044*sl 0.10 + 0.042*sl 0.09 + 0.043*sl b to y t plh 0.76 0.65 + 0.056*sl 0.66 + 0.051*sl 0.68 + 0.050*sl t phl 0.41 0.35 + 0.032*sl 0.36 + 0.025*sl 0.39 + 0.023*sl t r 0.38 0.17 + 0.105*sl 0.17 + 0.106*sl 0.15 + 0.108*sl t f 0.19 0.10 + 0.042*sl 0.10 + 0.042*sl 0.09 + 0.043*sl c to y t plh 0.76 0.65 + 0.056*sl 0.67 + 0.051*sl 0.68 + 0.050*sl t phl 0.43 0.36 + 0.034*sl 0.38 + 0.026*sl 0.41 + 0.023*sl t r 0.38 0.18 + 0.104*sl 0.17 + 0.106*sl 0.15 + 0.108*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.041*sl 0.10 + 0.042*sl d to y t plh 0.79 0.67 + 0.056*sl 0.69 + 0.051*sl 0.70 + 0.050*sl t phl 0.45 0.39 + 0.034*sl 0.41 + 0.026*sl 0.43 + 0.023*sl t r 0.38 0.18 + 0.103*sl 0.17 + 0.106*sl 0.15 + 0.108*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.041*sl 0.10 + 0.042*sl e to y t plh 0.78 0.67 + 0.056*sl 0.68 + 0.051*sl 0.69 + 0.050*sl t phl 0.47 0.40 + 0.036*sl 0.42 + 0.026*sl 0.46 + 0.023*sl t r 0.38 0.18 + 0.104*sl 0.17 + 0.106*sl 0.15 + 0.108*sl t f 0.22 0.13 + 0.043*sl 0.14 + 0.040*sl 0.12 + 0.042*sl f to y t plh 0.80 0.69 + 0.057*sl 0.71 + 0.051*sl 0.72 + 0.050*sl t phl 0.50 0.42 + 0.036*sl 0.45 + 0.026*sl 0.48 + 0.023*sl t r 0.38 0.18 + 0.104*sl 0.17 + 0.106*sl 0.15 + 0.108*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.040*sl 0.13 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-58 sec asic nr6/nr6d2 6-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nr6d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.76 0.71 + 0.025*sl 0.73 + 0.020*sl 0.76 + 0.018*sl t phl 0.46 0.42 + 0.022*sl 0.43 + 0.016*sl 0.46 + 0.013*sl t r 0.25 0.17 + 0.037*sl 0.18 + 0.035*sl 0.18 + 0.035*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.021*sl 0.15 + 0.021*sl b to y t plh 0.79 0.74 + 0.025*sl 0.75 + 0.020*sl 0.78 + 0.018*sl t phl 0.48 0.44 + 0.022*sl 0.46 + 0.016*sl 0.49 + 0.013*sl t r 0.25 0.17 + 0.037*sl 0.18 + 0.035*sl 0.18 + 0.035*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.021*sl 0.15 + 0.021*sl c to y t plh 0.78 0.73 + 0.025*sl 0.75 + 0.020*sl 0.78 + 0.018*sl t phl 0.50 0.46 + 0.023*sl 0.47 + 0.017*sl 0.51 + 0.013*sl t r 0.25 0.18 + 0.037*sl 0.18 + 0.035*sl 0.19 + 0.034*sl t f 0.19 0.15 + 0.025*sl 0.15 + 0.021*sl 0.17 + 0.020*sl d to y t plh 0.81 0.76 + 0.025*sl 0.77 + 0.020*sl 0.80 + 0.018*sl t phl 0.53 0.48 + 0.023*sl 0.50 + 0.017*sl 0.53 + 0.013*sl t r 0.25 0.18 + 0.037*sl 0.18 + 0.035*sl 0.19 + 0.034*sl t f 0.19 0.15 + 0.025*sl 0.15 + 0.021*sl 0.17 + 0.020*sl e to y t plh 0.80 0.75 + 0.025*sl 0.77 + 0.020*sl 0.80 + 0.018*sl t phl 0.54 0.50 + 0.024*sl 0.51 + 0.017*sl 0.55 + 0.014*sl t r 0.25 0.18 + 0.037*sl 0.18 + 0.035*sl 0.19 + 0.035*sl t f 0.21 0.16 + 0.025*sl 0.17 + 0.021*sl 0.19 + 0.020*sl f to y t plh 0.83 0.78 + 0.025*sl 0.79 + 0.020*sl 0.82 + 0.018*sl t phl 0.57 0.52 + 0.024*sl 0.54 + 0.017*sl 0.58 + 0.014*sl t r 0.25 0.18 + 0.036*sl 0.18 + 0.035*sl 0.19 + 0.034*sl t f 0.21 0.16 + 0.025*sl 0.17 + 0.021*sl 0.19 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-59 kg80/KGM80 nr8/nr8d2 8-input nor with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 nr8 nr8d2 nr8 nr8 d2 abcde fghabcde fgh 0.6 0.7 0.7 0.7 0.9 0.9 0.9 0.8 0.6 0.8 0.8 0.7 0.9 0.9 0.9 0.8 6.0 6.0 KGM80 nr8 nr8d2 nr8 nr8 d2 abcde fghabcde fgh 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 6.0 6.0 y c d e f b g a h truth table abcdefghy 000000001 1xxxxxxx0 x1xxxxxx0 xx1xxxxx0 xxx1xxxx0 xxxx1xxx0 xxxxx1xx0 xxxxxx1x0 xxxxxxx10
kg80/KGM80 3-60 sec asic nr8/nr8d2 8-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nr8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.66 0.58 + 0.042*sl 0.58 + 0.042*sl 0.58 + 0.042*sl t phl 0.29 0.24 + 0.026*sl 0.25 + 0.024*sl 0.25 + 0.023*sl t r 0.34 0.17 + 0.086*sl 0.16 + 0.089*sl 0.15 + 0.090*sl t f 0.18 0.09 + 0.041*sl 0.09 + 0.041*sl 0.08 + 0.042*sl b to y t plh 0.71 0.63 + 0.043*sl 0.63 + 0.041*sl 0.63 + 0.042*sl t phl 0.31 0.26 + 0.026*sl 0.27 + 0.024*sl 0.27 + 0.023*sl t r 0.34 0.17 + 0.086*sl 0.16 + 0.089*sl 0.15 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.042*sl 0.09 + 0.042*sl c to y t plh 0.77 0.68 + 0.042*sl 0.68 + 0.042*sl 0.69 + 0.041*sl t phl 0.33 0.28 + 0.026*sl 0.28 + 0.024*sl 0.29 + 0.023*sl t r 0.34 0.17 + 0.086*sl 0.16 + 0.089*sl 0.15 + 0.090*sl t f 0.18 0.10 + 0.040*sl 0.09 + 0.042*sl 0.09 + 0.042*sl d to y t plh 0.78 0.70 + 0.042*sl 0.70 + 0.042*sl 0.70 + 0.042*sl t phl 0.33 0.28 + 0.026*sl 0.28 + 0.024*sl 0.29 + 0.023*sl t r 0.34 0.17 + 0.086*sl 0.16 + 0.089*sl 0.15 + 0.090*sl t f 0.18 0.10 + 0.040*sl 0.09 + 0.041*sl 0.09 + 0.042*sl e to y t plh 0.65 0.56 + 0.043*sl 0.57 + 0.041*sl 0.56 + 0.042*sl t phl 0.31 0.26 + 0.028*sl 0.27 + 0.024*sl 0.27 + 0.023*sl t r 0.34 0.17 + 0.086*sl 0.16 + 0.089*sl 0.15 + 0.090*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.041*sl 0.09 + 0.042*sl f to y t plh 0.69 0.61 + 0.043*sl 0.61 + 0.042*sl 0.61 + 0.041*sl t phl 0.34 0.28 + 0.028*sl 0.29 + 0.024*sl 0.30 + 0.023*sl t r 0.34 0.17 + 0.086*sl 0.16 + 0.088*sl 0.15 + 0.090*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.041*sl 0.10 + 0.042*sl g to y t plh 0.75 0.66 + 0.043*sl 0.67 + 0.041*sl 0.67 + 0.042*sl t phl 0.35 0.30 + 0.027*sl 0.31 + 0.024*sl 0.31 + 0.023*sl t r 0.34 0.17 + 0.086*sl 0.16 + 0.089*sl 0.15 + 0.090*sl t f 0.19 0.11 + 0.040*sl 0.10 + 0.041*sl 0.10 + 0.042*sl h to y t plh 0.77 0.68 + 0.043*sl 0.68 + 0.041*sl 0.68 + 0.042*sl t phl 0.35 0.30 + 0.027*sl 0.31 + 0.024*sl 0.31 + 0.023*sl t r 0.34 0.17 + 0.087*sl 0.16 + 0.088*sl 0.15 + 0.090*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.040*sl 0.09 + 0.042*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-61 kg80/KGM80 nr8/nr8d2 8-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nr8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.64 0.59 + 0.024*sl 0.60 + 0.021*sl 0.60 + 0.021*sl t phl 0.28 0.24 + 0.018*sl 0.25 + 0.014*sl 0.26 + 0.012*sl t r 0.19 0.11 + 0.040*sl 0.10 + 0.043*sl 0.10 + 0.043*sl t f 0.12 0.08 + 0.021*sl 0.08 + 0.020*sl 0.08 + 0.020*sl b to y t plh 0.69 0.64 + 0.023*sl 0.65 + 0.021*sl 0.65 + 0.021*sl t phl 0.30 0.26 + 0.018*sl 0.27 + 0.014*sl 0.28 + 0.012*sl t r 0.19 0.11 + 0.041*sl 0.10 + 0.043*sl 0.10 + 0.043*sl t f 0.12 0.08 + 0.021*sl 0.08 + 0.020*sl 0.08 + 0.020*sl c to y t plh 0.75 0.70 + 0.024*sl 0.70 + 0.021*sl 0.71 + 0.021*sl t phl 0.31 0.28 + 0.018*sl 0.29 + 0.014*sl 0.30 + 0.012*sl t r 0.19 0.11 + 0.040*sl 0.10 + 0.043*sl 0.10 + 0.043*sl t f 0.12 0.08 + 0.021*sl 0.08 + 0.020*sl 0.08 + 0.020*sl d to y t plh 0.76 0.71 + 0.024*sl 0.72 + 0.021*sl 0.73 + 0.021*sl t phl 0.31 0.28 + 0.018*sl 0.29 + 0.014*sl 0.30 + 0.012*sl t r 0.19 0.11 + 0.041*sl 0.10 + 0.043*sl 0.10 + 0.044*sl t f 0.12 0.08 + 0.022*sl 0.08 + 0.020*sl 0.09 + 0.019*sl e to y t plh 0.62 0.57 + 0.024*sl 0.57 + 0.022*sl 0.58 + 0.021*sl t phl 0.29 0.26 + 0.019*sl 0.27 + 0.015*sl 0.28 + 0.013*sl t r 0.19 0.11 + 0.041*sl 0.10 + 0.043*sl 0.10 + 0.043*sl t f 0.13 0.09 + 0.021*sl 0.09 + 0.020*sl 0.09 + 0.020*sl f to y t plh 0.66 0.61 + 0.025*sl 0.62 + 0.022*sl 0.63 + 0.021*sl t phl 0.32 0.28 + 0.020*sl 0.29 + 0.015*sl 0.31 + 0.013*sl t r 0.19 0.11 + 0.041*sl 0.11 + 0.042*sl 0.10 + 0.044*sl t f 0.13 0.09 + 0.023*sl 0.09 + 0.019*sl 0.09 + 0.020*sl g to y t plh 0.72 0.67 + 0.024*sl 0.68 + 0.022*sl 0.68 + 0.021*sl t phl 0.33 0.29 + 0.019*sl 0.30 + 0.015*sl 0.32 + 0.013*sl t r 0.19 0.11 + 0.041*sl 0.11 + 0.042*sl 0.10 + 0.043*sl t f 0.13 0.09 + 0.022*sl 0.09 + 0.020*sl 0.09 + 0.020*sl h to y t plh 0.73 0.69 + 0.024*sl 0.69 + 0.022*sl 0.70 + 0.021*sl t phl 0.33 0.29 + 0.019*sl 0.31 + 0.015*sl 0.32 + 0.013*sl t r 0.19 0.11 + 0.041*sl 0.11 + 0.042*sl 0.10 + 0.044*sl t f 0.13 0.09 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.019*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-62 sec asic nr8/nr8d2 8-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nr8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.94 0.84 + 0.051*sl 0.84 + 0.050*sl 0.84 + 0.050*sl t phl 0.41 0.35 + 0.027*sl 0.36 + 0.024*sl 0.37 + 0.023*sl t r 0.46 0.25 + 0.103*sl 0.24 + 0.107*sl 0.22 + 0.109*sl t f 0.21 0.13 + 0.040*sl 0.13 + 0.042*sl 0.11 + 0.043*sl b to y t plh 1.06 0.96 + 0.051*sl 0.96 + 0.050*sl 0.96 + 0.050*sl t phl 0.43 0.38 + 0.027*sl 0.39 + 0.024*sl 0.40 + 0.023*sl t r 0.46 0.25 + 0.104*sl 0.24 + 0.107*sl 0.22 + 0.109*sl t f 0.21 0.13 + 0.043*sl 0.13 + 0.042*sl 0.11 + 0.043*sl c to y t plh 1.21 1.11 + 0.051*sl 1.11 + 0.050*sl 1.11 + 0.050*sl t phl 0.45 0.39 + 0.028*sl 0.40 + 0.024*sl 0.41 + 0.023*sl t r 0.46 0.25 + 0.104*sl 0.24 + 0.107*sl 0.22 + 0.109*sl t f 0.21 0.13 + 0.042*sl 0.13 + 0.042*sl 0.11 + 0.043*sl d to y t plh 1.25 1.15 + 0.051*sl 1.15 + 0.050*sl 1.15 + 0.050*sl t phl 0.45 0.39 + 0.028*sl 0.40 + 0.024*sl 0.41 + 0.023*sl t r 0.46 0.25 + 0.104*sl 0.24 + 0.107*sl 0.22 + 0.109*sl t f 0.21 0.13 + 0.042*sl 0.13 + 0.042*sl 0.12 + 0.043*sl e to y t plh 0.91 0.81 + 0.051*sl 0.82 + 0.050*sl 0.82 + 0.050*sl t phl 0.44 0.39 + 0.029*sl 0.40 + 0.024*sl 0.41 + 0.023*sl t r 0.46 0.25 + 0.104*sl 0.24 + 0.107*sl 0.22 + 0.109*sl t f 0.22 0.14 + 0.042*sl 0.14 + 0.041*sl 0.12 + 0.043*sl f to y t plh 1.03 0.93 + 0.052*sl 0.93 + 0.050*sl 0.94 + 0.050*sl t phl 0.47 0.41 + 0.029*sl 0.42 + 0.024*sl 0.44 + 0.023*sl t r 0.46 0.25 + 0.104*sl 0.24 + 0.107*sl 0.22 + 0.109*sl t f 0.22 0.14 + 0.041*sl 0.14 + 0.041*sl 0.12 + 0.043*sl g to y t plh 1.18 1.08 + 0.052*sl 1.08 + 0.050*sl 1.08 + 0.050*sl t phl 0.48 0.43 + 0.029*sl 0.44 + 0.024*sl 0.45 + 0.023*sl t r 0.46 0.25 + 0.103*sl 0.24 + 0.107*sl 0.23 + 0.109*sl t f 0.22 0.14 + 0.041*sl 0.14 + 0.041*sl 0.13 + 0.043*sl h to y t plh 1.22 1.12 + 0.052*sl 1.12 + 0.050*sl 1.12 + 0.050*sl t phl 0.49 0.43 + 0.029*sl 0.44 + 0.024*sl 0.45 + 0.023*sl t r 0.46 0.25 + 0.104*sl 0.24 + 0.107*sl 0.23 + 0.109*sl t f 0.22 0.14 + 0.041*sl 0.14 + 0.041*sl 0.12 + 0.043*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-63 kg80/KGM80 nr8/nr8d2 8-input nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nr8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.91 0.84 + 0.030*sl 0.86 + 0.026*sl 0.87 + 0.025*sl t phl 0.39 0.35 + 0.020*sl 0.37 + 0.015*sl 0.39 + 0.012*sl t r 0.24 0.14 + 0.051*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.14 0.09 + 0.025*sl 0.10 + 0.021*sl 0.11 + 0.021*sl b to y t plh 1.03 0.97 + 0.030*sl 0.98 + 0.026*sl 0.99 + 0.025*sl t phl 0.42 0.38 + 0.021*sl 0.39 + 0.015*sl 0.42 + 0.012*sl t r 0.24 0.14 + 0.051*sl 0.14 + 0.052*sl 0.12 + 0.053*sl t f 0.14 0.09 + 0.024*sl 0.10 + 0.021*sl 0.11 + 0.021*sl c to y t plh 1.17 1.11 + 0.030*sl 1.13 + 0.026*sl 1.14 + 0.025*sl t phl 0.43 0.39 + 0.021*sl 0.41 + 0.015*sl 0.44 + 0.012*sl t r 0.24 0.14 + 0.051*sl 0.14 + 0.052*sl 0.12 + 0.053*sl t f 0.15 0.10 + 0.025*sl 0.11 + 0.021*sl 0.11 + 0.020*sl d to y t plh 1.22 1.16 + 0.030*sl 1.17 + 0.026*sl 1.18 + 0.025*sl t phl 0.43 0.39 + 0.021*sl 0.41 + 0.015*sl 0.44 + 0.012*sl t r 0.24 0.14 + 0.051*sl 0.14 + 0.052*sl 0.12 + 0.053*sl t f 0.15 0.10 + 0.025*sl 0.11 + 0.021*sl 0.11 + 0.021*sl e to y t plh 0.86 0.80 + 0.031*sl 0.82 + 0.026*sl 0.83 + 0.025*sl t phl 0.42 0.38 + 0.023*sl 0.40 + 0.016*sl 0.43 + 0.013*sl t r 0.24 0.14 + 0.052*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.12 + 0.020*sl f to y t plh 0.98 0.92 + 0.031*sl 0.94 + 0.026*sl 0.95 + 0.025*sl t phl 0.45 0.40 + 0.023*sl 0.42 + 0.016*sl 0.46 + 0.013*sl t r 0.24 0.14 + 0.052*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.16 0.11 + 0.024*sl 0.12 + 0.021*sl 0.12 + 0.020*sl g to y t plh 1.13 1.07 + 0.031*sl 1.08 + 0.026*sl 1.09 + 0.025*sl t phl 0.47 0.42 + 0.023*sl 0.44 + 0.016*sl 0.47 + 0.013*sl t r 0.24 0.14 + 0.053*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.020*sl 0.12 + 0.020*sl h to y t plh 1.17 1.11 + 0.031*sl 1.12 + 0.026*sl 1.14 + 0.025*sl t phl 0.47 0.42 + 0.023*sl 0.44 + 0.016*sl 0.48 + 0.013*sl t r 0.24 0.14 + 0.053*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.16 0.11 + 0.024*sl 0.12 + 0.020*sl 0.13 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-64 sec asic or2/or2d2 2-input or with 1x/2x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 or2 kg80 or2d2 input load (sl) gate count kg80 or2 or2d2 or2 or2d2 abab 0.5 0.7 0.5 0.7 2.0 2.0 KGM80 or2 or2d2 or2 or2d2 abab 1.0 1.0 1.0 1.0 2.0 2.0 y a b [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.21 0.13 + 0.041*sl 0.12 + 0.041*sl 0.12 + 0.042*sl t phl 0.34 0.27 + 0.032*sl 0.29 + 0.027*sl 0.31 + 0.024*sl t r 0.27 0.09 + 0.087*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.19 0.10 + 0.041*sl 0.10 + 0.041*sl 0.10 + 0.041*sl b to y t plh 0.23 0.15 + 0.042*sl 0.15 + 0.041*sl 0.15 + 0.042*sl t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.30 + 0.024*sl t r 0.27 0.10 + 0.083*sl 0.08 + 0.090*sl 0.08 + 0.091*sl t f 0.19 0.10 + 0.041*sl 0.10 + 0.041*sl 0.10 + 0.041*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.20 0.16 + 0.021*sl 0.16 + 0.021*sl 0.16 + 0.021*sl t phl 0.36 0.32 + 0.020*sl 0.33 + 0.016*sl 0.34 + 0.014*sl t r 0.18 0.10 + 0.043*sl 0.10 + 0.043*sl 0.09 + 0.045*sl t f 0.17 0.13 + 0.023*sl 0.13 + 0.020*sl 0.13 + 0.020*sl b to y t plh 0.22 0.18 + 0.021*sl 0.18 + 0.021*sl 0.18 + 0.021*sl t phl 0.36 0.32 + 0.020*sl 0.32 + 0.016*sl 0.34 + 0.014*sl t r 0.18 0.10 + 0.041*sl 0.10 + 0.043*sl 0.09 + 0.045*sl t f 0.18 0.13 + 0.023*sl 0.14 + 0.020*sl 0.14 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = truth table aby 000 011 101 111
sec asic 3-65 kg80/KGM80 or2/or2d2 2-input or with 1x/2x drive lswitching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 or2 KGM80 or2d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.28 0.18 + 0.050*sl 0.18 + 0.050*sl 0.18 + 0.050*sl t phl 0.44 0.37 + 0.037*sl 0.39 + 0.028*sl 0.43 + 0.024*sl t r 0.34 0.13 + 0.106*sl 0.12 + 0.109*sl 0.11 + 0.109*sl t f 0.23 0.13 + 0.047*sl 0.15 + 0.042*sl 0.15 + 0.042*sl b to y t plh 0.31 0.21 + 0.051*sl 0.21 + 0.050*sl 0.21 + 0.050*sl t phl 0.46 0.39 + 0.037*sl 0.41 + 0.028*sl 0.45 + 0.024*sl t r 0.34 0.13 + 0.106*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.23 0.13 + 0.047*sl 0.15 + 0.042*sl 0.15 + 0.042*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.27 0.22 + 0.026*sl 0.22 + 0.025*sl 0.22 + 0.025*sl t phl 0.49 0.44 + 0.024*sl 0.46 + 0.018*sl 0.50 + 0.014*sl t r 0.24 0.14 + 0.051*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.22 0.17 + 0.026*sl 0.18 + 0.022*sl 0.20 + 0.021*sl b to y t plh 0.29 0.24 + 0.026*sl 0.24 + 0.025*sl 0.25 + 0.025*sl t phl 0.51 0.46 + 0.024*sl 0.48 + 0.018*sl 0.52 + 0.014*sl t r 0.24 0.14 + 0.050*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.22 0.17 + 0.025*sl 0.18 + 0.022*sl 0.19 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-66 sec asic or3/or3d3 3-input or with 1x/3x drive logic symbol cell data input load (sl) gate count kg80 or3 or3d3 or3 or3d3 abcabc 0.5 0.7 0.7 0.5 0.7 0.7 2.0 3.0 KGM80 or3 or3d3 or3 or3d3 abcabc 1.0 1.0 1.0 1.0 1.0 1.0 2.0 3.0 y a b c truth table abcy 0000 1xx1 x1x1 xx11
sec asic 3-67 kg80/KGM80 or3/or3d3 3-input or with 1x/3x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 or3 kg80 or3d3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.22 0.14 + 0.041*sl 0.14 + 0.041*sl 0.14 + 0.042*sl t phl 0.42 0.34 + 0.039*sl 0.36 + 0.030*sl 0.39 + 0.026*sl t r 0.27 0.10 + 0.084*sl 0.08 + 0.090*sl 0.08 + 0.091*sl t f 0.23 0.14 + 0.045*sl 0.15 + 0.042*sl 0.16 + 0.041*sl b to y t plh 0.25 0.16 + 0.042*sl 0.16 + 0.041*sl 0.16 + 0.042*sl t phl 0.44 0.36 + 0.040*sl 0.39 + 0.030*sl 0.42 + 0.026*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.24 0.15 + 0.043*sl 0.15 + 0.042*sl 0.17 + 0.041*sl c to y t plh 0.26 0.18 + 0.042*sl 0.18 + 0.041*sl 0.17 + 0.042*sl t phl 0.47 0.39 + 0.040*sl 0.41 + 0.030*sl 0.44 + 0.026*sl t r 0.27 0.11 + 0.083*sl 0.09 + 0.089*sl 0.09 + 0.090*sl t f 0.24 0.15 + 0.044*sl 0.15 + 0.042*sl 0.16 + 0.041*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.23 0.20 + 0.015*sl 0.20 + 0.014*sl 0.21 + 0.014*sl t phl 0.51 0.47 + 0.019*sl 0.48 + 0.015*sl 0.50 + 0.013*sl t r 0.17 0.11 + 0.029*sl 0.11 + 0.027*sl 0.10 + 0.029*sl t f 0.27 0.23 + 0.018*sl 0.23 + 0.016*sl 0.25 + 0.014*sl b to y t plh 0.25 0.22 + 0.015*sl 0.23 + 0.014*sl 0.23 + 0.014*sl t phl 0.54 0.50 + 0.019*sl 0.51 + 0.015*sl 0.53 + 0.013*sl t r 0.17 0.11 + 0.027*sl 0.11 + 0.028*sl 0.10 + 0.029*sl t f 0.27 0.23 + 0.018*sl 0.24 + 0.016*sl 0.25 + 0.015*sl c to y t plh 0.27 0.24 + 0.015*sl 0.24 + 0.014*sl 0.24 + 0.014*sl t phl 0.56 0.52 + 0.019*sl 0.53 + 0.015*sl 0.55 + 0.013*sl t r 0.17 0.12 + 0.026*sl 0.12 + 0.027*sl 0.11 + 0.029*sl t f 0.27 0.23 + 0.018*sl 0.24 + 0.016*sl 0.25 + 0.014*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-68 sec asic or3/or3d3 3-input or with 1x/3x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 or3 KGM80 or3d3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.30 0.20 + 0.051*sl 0.20 + 0.050*sl 0.20 + 0.050*sl t phl 0.58 0.49 + 0.046*sl 0.52 + 0.033*sl 0.59 + 0.027*sl t r 0.34 0.13 + 0.105*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.30 0.19 + 0.051*sl 0.21 + 0.045*sl 0.24 + 0.042*sl b to y t plh 0.33 0.23 + 0.051*sl 0.23 + 0.050*sl 0.23 + 0.050*sl t phl 0.65 0.56 + 0.047*sl 0.60 + 0.033*sl 0.66 + 0.027*sl t r 0.34 0.14 + 0.104*sl 0.13 + 0.108*sl 0.11 + 0.109*sl t f 0.30 0.20 + 0.052*sl 0.22 + 0.044*sl 0.24 + 0.042*sl c to y t plh 0.34 0.24 + 0.052*sl 0.24 + 0.050*sl 0.25 + 0.050*sl t phl 0.72 0.63 + 0.046*sl 0.67 + 0.033*sl 0.73 + 0.027*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.30 0.20 + 0.052*sl 0.22 + 0.044*sl 0.24 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.31 0.27 + 0.018*sl 0.27 + 0.017*sl 0.28 + 0.017*sl t phl 0.76 0.71 + 0.023*sl 0.73 + 0.018*sl 0.77 + 0.014*sl t r 0.21 0.15 + 0.034*sl 0.14 + 0.035*sl 0.13 + 0.036*sl t f 0.35 0.31 + 0.022*sl 0.32 + 0.018*sl 0.34 + 0.016*sl b to y t plh 0.33 0.29 + 0.019*sl 0.30 + 0.017*sl 0.30 + 0.017*sl t phl 0.83 0.79 + 0.023*sl 0.80 + 0.018*sl 0.85 + 0.014*sl t r 0.22 0.15 + 0.033*sl 0.15 + 0.035*sl 0.13 + 0.036*sl t f 0.35 0.31 + 0.023*sl 0.32 + 0.018*sl 0.34 + 0.016*sl c to y t plh 0.34 0.30 + 0.019*sl 0.31 + 0.017*sl 0.32 + 0.017*sl t phl 0.91 0.86 + 0.023*sl 0.87 + 0.018*sl 0.92 + 0.014*sl t r 0.22 0.15 + 0.034*sl 0.15 + 0.035*sl 0.14 + 0.036*sl t f 0.35 0.31 + 0.021*sl 0.32 + 0.018*sl 0.34 + 0.016*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-69 kg80/KGM80 or4/or4d2 4-input or with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 or4 or4d2 or4 or4d2 abcdabcd 0.6 0.7 0.6 0.8 0.6 0.7 0.6 0.8 3.0 4.0 KGM80 or4 or4d2 or4 or4d2 abcdabcd 1.1 1.0 1.0 1.1 1.0 1.0 1.0 1.0 3.0 4.0 y a b c d truth table abcdy 00000 1xxx1 x1xx1 xx1x1 xxx11
kg80/KGM80 3-70 sec asic or4/or4d2 4-input or with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 or4 kg80 or4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.21 0.13 + 0.042*sl 0.13 + 0.042*sl 0.13 + 0.042*sl t phl 0.38 0.29 + 0.042*sl 0.31 + 0.036*sl 0.32 + 0.034*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.090*sl 0.08 + 0.091*sl t f 0.25 0.12 + 0.065*sl 0.12 + 0.066*sl 0.11 + 0.067*sl b to y t plh 0.24 0.15 + 0.042*sl 0.15 + 0.042*sl 0.15 + 0.042*sl t phl 0.38 0.29 + 0.042*sl 0.31 + 0.036*sl 0.32 + 0.035*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.26 0.13 + 0.065*sl 0.12 + 0.066*sl 0.11 + 0.067*sl c to y t plh 0.23 0.15 + 0.041*sl 0.15 + 0.042*sl 0.15 + 0.042*sl t phl 0.37 0.30 + 0.039*sl 0.30 + 0.036*sl 0.31 + 0.034*sl t r 0.31 0.14 + 0.085*sl 0.13 + 0.089*sl 0.12 + 0.091*sl t f 0.25 0.11 + 0.066*sl 0.11 + 0.066*sl 0.10 + 0.068*sl d to y t plh 0.26 0.17 + 0.041*sl 0.17 + 0.042*sl 0.17 + 0.042*sl t phl 0.37 0.29 + 0.040*sl 0.30 + 0.036*sl 0.31 + 0.035*sl t r 0.31 0.14 + 0.084*sl 0.13 + 0.089*sl 0.12 + 0.090*sl t f 0.25 0.12 + 0.065*sl 0.11 + 0.066*sl 0.10 + 0.068*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.21 0.17 + 0.021*sl 0.17 + 0.021*sl 0.17 + 0.021*sl t phl 0.40 0.35 + 0.025*sl 0.36 + 0.021*sl 0.37 + 0.019*sl t r 0.19 0.11 + 0.041*sl 0.11 + 0.043*sl 0.09 + 0.045*sl t f 0.22 0.16 + 0.032*sl 0.16 + 0.033*sl 0.16 + 0.032*sl b to y t plh 0.23 0.19 + 0.021*sl 0.19 + 0.021*sl 0.19 + 0.021*sl t phl 0.40 0.35 + 0.025*sl 0.36 + 0.021*sl 0.37 + 0.019*sl t r 0.20 0.11 + 0.041*sl 0.11 + 0.042*sl 0.09 + 0.045*sl t f 0.22 0.16 + 0.032*sl 0.16 + 0.032*sl 0.16 + 0.032*sl c to y t plh 0.23 0.19 + 0.021*sl 0.19 + 0.021*sl 0.19 + 0.021*sl t phl 0.40 0.35 + 0.023*sl 0.36 + 0.020*sl 0.37 + 0.018*sl t r 0.24 0.16 + 0.041*sl 0.16 + 0.042*sl 0.15 + 0.044*sl t f 0.21 0.15 + 0.030*sl 0.15 + 0.032*sl 0.14 + 0.033*sl d to y t plh 0.26 0.21 + 0.021*sl 0.21 + 0.021*sl 0.22 + 0.021*sl t phl 0.40 0.35 + 0.024*sl 0.36 + 0.020*sl 0.37 + 0.018*sl t r 0.25 0.16 + 0.041*sl 0.16 + 0.042*sl 0.15 + 0.044*sl t f 0.22 0.15 + 0.032*sl 0.15 + 0.031*sl 0.14 + 0.033*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-71 kg80/KGM80 or4/or4d2 4-input or with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 or4 KGM80 or4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.29 0.19 + 0.051*sl 0.19 + 0.050*sl 0.19 + 0.050*sl t phl 0.50 0.40 + 0.050*sl 0.42 + 0.040*sl 0.45 + 0.037*sl t r 0.34 0.13 + 0.105*sl 0.12 + 0.109*sl 0.12 + 0.109*sl t f 0.31 0.16 + 0.075*sl 0.17 + 0.072*sl 0.16 + 0.073*sl b to y t plh 0.32 0.21 + 0.051*sl 0.22 + 0.050*sl 0.22 + 0.050*sl t phl 0.52 0.42 + 0.050*sl 0.45 + 0.040*sl 0.48 + 0.038*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.32 0.17 + 0.074*sl 0.17 + 0.072*sl 0.16 + 0.073*sl c to y t plh 0.32 0.22 + 0.051*sl 0.22 + 0.050*sl 0.23 + 0.050*sl t phl 0.49 0.40 + 0.046*sl 0.42 + 0.039*sl 0.44 + 0.038*sl t r 0.40 0.19 + 0.104*sl 0.18 + 0.108*sl 0.17 + 0.109*sl t f 0.30 0.15 + 0.071*sl 0.15 + 0.073*sl 0.14 + 0.074*sl d to y t plh 0.35 0.24 + 0.051*sl 0.25 + 0.050*sl 0.25 + 0.050*sl t phl 0.51 0.42 + 0.046*sl 0.44 + 0.039*sl 0.46 + 0.038*sl t r 0.40 0.19 + 0.104*sl 0.18 + 0.108*sl 0.17 + 0.109*sl t f 0.30 0.16 + 0.071*sl 0.15 + 0.073*sl 0.14 + 0.074*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.28 0.23 + 0.026*sl 0.23 + 0.025*sl 0.23 + 0.025*sl t phl 0.54 0.48 + 0.030*sl 0.50 + 0.024*sl 0.54 + 0.020*sl t r 0.25 0.15 + 0.051*sl 0.14 + 0.053*sl 0.13 + 0.054*sl t f 0.28 0.20 + 0.039*sl 0.21 + 0.036*sl 0.22 + 0.036*sl b to y t plh 0.31 0.25 + 0.027*sl 0.26 + 0.025*sl 0.26 + 0.025*sl t phl 0.57 0.51 + 0.030*sl 0.53 + 0.024*sl 0.56 + 0.020*sl t r 0.25 0.15 + 0.050*sl 0.14 + 0.053*sl 0.13 + 0.054*sl t f 0.28 0.21 + 0.039*sl 0.21 + 0.036*sl 0.22 + 0.036*sl c to y t plh 0.32 0.27 + 0.026*sl 0.27 + 0.025*sl 0.27 + 0.025*sl t phl 0.55 0.49 + 0.028*sl 0.51 + 0.023*sl 0.53 + 0.020*sl t r 0.31 0.21 + 0.051*sl 0.21 + 0.053*sl 0.19 + 0.054*sl t f 0.26 0.19 + 0.036*sl 0.19 + 0.036*sl 0.19 + 0.036*sl d to y t plh 0.34 0.29 + 0.026*sl 0.29 + 0.025*sl 0.30 + 0.025*sl t phl 0.57 0.52 + 0.028*sl 0.53 + 0.023*sl 0.56 + 0.020*sl t r 0.32 0.22 + 0.051*sl 0.21 + 0.053*sl 0.20 + 0.054*sl t f 0.26 0.19 + 0.037*sl 0.19 + 0.036*sl 0.19 + 0.036*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-72 sec asic or5/or5d2 5-input or with 1x/2x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 or5 input load (sl) gate count kg80 or5 or5d2 or5 or5d2 abcdeabcde 0.6 0.7 0.7 0.6 0.7 0.6 0.7 0.7 0.6 0.7 4.0 5.0 KGM80 or5 or5d2 or5 or5d2 abcdeabcde 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 4.0 5.0 y b c d e a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.26 0.18 + 0.042*sl 0.18 + 0.041*sl 0.17 + 0.042*sl t phl 0.52 0.41 + 0.053*sl 0.44 + 0.042*sl 0.47 + 0.038*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.34 0.20 + 0.069*sl 0.21 + 0.066*sl 0.21 + 0.066*sl b to y t plh 0.29 0.20 + 0.043*sl 0.21 + 0.041*sl 0.20 + 0.042*sl t phl 0.56 0.45 + 0.053*sl 0.48 + 0.042*sl 0.51 + 0.037*sl t r 0.28 0.11 + 0.087*sl 0.10 + 0.088*sl 0.08 + 0.091*sl t f 0.34 0.21 + 0.067*sl 0.21 + 0.066*sl 0.21 + 0.066*sl c to y t plh 0.29 0.21 + 0.042*sl 0.21 + 0.042*sl 0.21 + 0.042*sl t phl 0.57 0.46 + 0.053*sl 0.49 + 0.042*sl 0.52 + 0.038*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.089*sl 0.09 + 0.090*sl t f 0.34 0.21 + 0.067*sl 0.21 + 0.066*sl 0.21 + 0.066*sl d to y t plh 0.23 0.15 + 0.042*sl 0.15 + 0.042*sl 0.15 + 0.042*sl t phl 0.37 0.30 + 0.039*sl 0.30 + 0.036*sl 0.31 + 0.035*sl t r 0.31 0.14 + 0.085*sl 0.13 + 0.089*sl 0.12 + 0.091*sl t f 0.24 0.11 + 0.066*sl 0.11 + 0.067*sl 0.10 + 0.068*sl e to y t plh 0.26 0.17 + 0.041*sl 0.17 + 0.041*sl 0.17 + 0.042*sl t phl 0.37 0.29 + 0.040*sl 0.30 + 0.036*sl 0.31 + 0.035*sl t r 0.31 0.14 + 0.084*sl 0.13 + 0.089*sl 0.12 + 0.090*sl t f 0.25 0.12 + 0.065*sl 0.11 + 0.066*sl 0.10 + 0.068*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = truth table abcdey 000000 1xxxx1 x1xxx1 xx1xx1 xxx1x1 xxxx11
sec asic 3-73 kg80/KGM80 or5/or5d2 5-input or with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 or5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.25 0.21 + 0.022*sl 0.21 + 0.021*sl 0.21 + 0.021*sl t phl 0.54 0.48 + 0.032*sl 0.49 + 0.026*sl 0.52 + 0.022*sl t r 0.20 0.11 + 0.040*sl 0.11 + 0.043*sl 0.10 + 0.044*sl t f 0.32 0.25 + 0.036*sl 0.26 + 0.033*sl 0.26 + 0.032*sl b to y t plh 0.28 0.23 + 0.022*sl 0.23 + 0.021*sl 0.24 + 0.021*sl t phl 0.59 0.53 + 0.032*sl 0.54 + 0.025*sl 0.57 + 0.022*sl t r 0.20 0.12 + 0.041*sl 0.11 + 0.043*sl 0.10 + 0.044*sl t f 0.33 0.26 + 0.035*sl 0.26 + 0.033*sl 0.27 + 0.032*sl c to y t plh 0.28 0.24 + 0.023*sl 0.24 + 0.021*sl 0.24 + 0.021*sl t phl 0.60 0.53 + 0.031*sl 0.55 + 0.026*sl 0.57 + 0.022*sl t r 0.20 0.12 + 0.039*sl 0.11 + 0.043*sl 0.10 + 0.045*sl t f 0.33 0.25 + 0.036*sl 0.26 + 0.033*sl 0.27 + 0.032*sl d to y t plh 0.23 0.19 + 0.021*sl 0.19 + 0.021*sl 0.19 + 0.021*sl t phl 0.40 0.35 + 0.023*sl 0.36 + 0.020*sl 0.37 + 0.018*sl t r 0.24 0.16 + 0.041*sl 0.16 + 0.043*sl 0.14 + 0.044*sl t f 0.21 0.15 + 0.029*sl 0.15 + 0.032*sl 0.14 + 0.033*sl e to y t plh 0.26 0.21 + 0.021*sl 0.21 + 0.021*sl 0.22 + 0.021*sl t phl 0.40 0.35 + 0.024*sl 0.36 + 0.020*sl 0.37 + 0.018*sl t r 0.25 0.16 + 0.041*sl 0.16 + 0.043*sl 0.15 + 0.044*sl t f 0.21 0.15 + 0.031*sl 0.15 + 0.032*sl 0.14 + 0.033*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-74 sec asic or5/or5d2 5-input or with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 or5 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.35 0.24 + 0.051*sl 0.25 + 0.050*sl 0.25 + 0.050*sl t phl 0.72 0.59 + 0.065*sl 0.63 + 0.049*sl 0.72 + 0.041*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.43 0.27 + 0.080*sl 0.29 + 0.074*sl 0.32 + 0.072*sl b to y t plh 0.38 0.28 + 0.051*sl 0.28 + 0.050*sl 0.28 + 0.050*sl t phl 0.84 0.71 + 0.065*sl 0.75 + 0.049*sl 0.84 + 0.041*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.44 0.27 + 0.081*sl 0.29 + 0.074*sl 0.32 + 0.072*sl c to y t plh 0.39 0.28 + 0.053*sl 0.29 + 0.050*sl 0.29 + 0.050*sl t phl 0.88 0.75 + 0.065*sl 0.79 + 0.049*sl 0.87 + 0.041*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.108*sl 0.13 + 0.109*sl t f 0.44 0.27 + 0.081*sl 0.29 + 0.074*sl 0.32 + 0.072*sl d to y t plh 0.32 0.22 + 0.051*sl 0.22 + 0.050*sl 0.22 + 0.050*sl t phl 0.49 0.40 + 0.046*sl 0.42 + 0.040*sl 0.44 + 0.038*sl t r 0.40 0.19 + 0.105*sl 0.18 + 0.109*sl 0.17 + 0.109*sl t f 0.29 0.15 + 0.072*sl 0.15 + 0.073*sl 0.14 + 0.074*sl e to y t plh 0.35 0.24 + 0.051*sl 0.25 + 0.050*sl 0.25 + 0.050*sl t phl 0.51 0.42 + 0.046*sl 0.44 + 0.040*sl 0.46 + 0.038*sl t r 0.40 0.19 + 0.104*sl 0.18 + 0.108*sl 0.17 + 0.109*sl t f 0.30 0.15 + 0.071*sl 0.15 + 0.073*sl 0.14 + 0.074*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-75 kg80/KGM80 or5/or5d2 5-input or with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 or5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.33 0.28 + 0.028*sl 0.28 + 0.025*sl 0.29 + 0.025*sl t phl 0.79 0.71 + 0.040*sl 0.73 + 0.030*sl 0.79 + 0.024*sl t r 0.25 0.15 + 0.051*sl 0.14 + 0.053*sl 0.13 + 0.054*sl t f 0.42 0.33 + 0.043*sl 0.34 + 0.039*sl 0.37 + 0.037*sl b to y t plh 0.36 0.31 + 0.027*sl 0.31 + 0.025*sl 0.32 + 0.025*sl t phl 0.91 0.83 + 0.040*sl 0.86 + 0.030*sl 0.92 + 0.024*sl t r 0.26 0.16 + 0.050*sl 0.15 + 0.053*sl 0.14 + 0.054*sl t f 0.42 0.33 + 0.043*sl 0.35 + 0.038*sl 0.37 + 0.037*sl c to y t plh 0.37 0.32 + 0.028*sl 0.32 + 0.026*sl 0.33 + 0.025*sl t phl 0.95 0.87 + 0.040*sl 0.89 + 0.030*sl 0.95 + 0.024*sl t r 0.26 0.17 + 0.047*sl 0.15 + 0.053*sl 0.14 + 0.054*sl t f 0.42 0.33 + 0.043*sl 0.35 + 0.038*sl 0.37 + 0.037*sl d to y t plh 0.32 0.27 + 0.026*sl 0.27 + 0.025*sl 0.27 + 0.025*sl t phl 0.55 0.49 + 0.027*sl 0.50 + 0.023*sl 0.53 + 0.020*sl t r 0.31 0.21 + 0.052*sl 0.21 + 0.053*sl 0.19 + 0.054*sl t f 0.26 0.19 + 0.037*sl 0.19 + 0.036*sl 0.19 + 0.037*sl e to y t plh 0.34 0.29 + 0.026*sl 0.29 + 0.025*sl 0.30 + 0.025*sl t phl 0.57 0.51 + 0.027*sl 0.53 + 0.023*sl 0.55 + 0.020*sl t r 0.32 0.21 + 0.051*sl 0.21 + 0.053*sl 0.20 + 0.054*sl t f 0.26 0.19 + 0.036*sl 0.19 + 0.036*sl 0.19 + 0.037*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-76 sec asic xn2/xn2d2 2-input exclusive-nor with 1x/2x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 xn2 kg80 xn2d2 input load (sl) gate count kg80 xn2 xn2d2 xn2 xn2d2 abab 0.9 1.7 0.9 1.7 3.0 4.0 KGM80 xn2 xn2d2 xn2 xn2d2 abab 1.0 2.0 1.0 2.0 3.0 4.0 y a b [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.50 0.41 + 0.043*sl 0.41 + 0.041*sl 0.41 + 0.042*sl t phl 0.41 0.34 + 0.039*sl 0.36 + 0.030*sl 0.39 + 0.025*sl t r 0.27 0.11 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.23 0.14 + 0.046*sl 0.15 + 0.040*sl 0.15 + 0.040*sl b to y t plh 0.37 0.29 + 0.043*sl 0.29 + 0.041*sl 0.29 + 0.042*sl t phl 0.31 0.24 + 0.033*sl 0.26 + 0.027*sl 0.28 + 0.025*sl t r 0.27 0.10 + 0.087*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.18 0.09 + 0.044*sl 0.10 + 0.042*sl 0.10 + 0.041*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.49 0.44 + 0.023*sl 0.45 + 0.021*sl 0.45 + 0.021*sl t phl 0.42 0.37 + 0.024*sl 0.38 + 0.019*sl 0.40 + 0.016*sl t r 0.20 0.11 + 0.042*sl 0.11 + 0.043*sl 0.10 + 0.044*sl t f 0.21 0.15 + 0.026*sl 0.16 + 0.022*sl 0.17 + 0.020*sl b to y t plh 0.36 0.32 + 0.023*sl 0.32 + 0.021*sl 0.32 + 0.021*sl t phl 0.31 0.27 + 0.021*sl 0.28 + 0.017*sl 0.30 + 0.015*sl t r 0.20 0.11 + 0.042*sl 0.11 + 0.043*sl 0.10 + 0.044*sl t f 0.16 0.11 + 0.026*sl 0.12 + 0.022*sl 0.12 + 0.021*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = truth table aby 001 010 100 111
sec asic 3-77 kg80/KGM80 xn2/xn2d2 2-input exclusive-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 xn2 KGM80 xn2d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.66 0.56 + 0.053*sl 0.57 + 0.050*sl 0.57 + 0.050*sl t phl 0.56 0.47 + 0.047*sl 0.51 + 0.031*sl 0.58 + 0.025*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.107*sl 0.12 + 0.109*sl t f 0.28 0.19 + 0.050*sl 0.21 + 0.042*sl 0.22 + 0.040*sl b to y t plh 0.49 0.38 + 0.052*sl 0.39 + 0.050*sl 0.39 + 0.050*sl t phl 0.41 0.33 + 0.038*sl 0.36 + 0.029*sl 0.40 + 0.025*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.107*sl 0.12 + 0.109*sl t f 0.22 0.13 + 0.049*sl 0.14 + 0.043*sl 0.15 + 0.042*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.66 0.60 + 0.029*sl 0.61 + 0.026*sl 0.62 + 0.025*sl t phl 0.58 0.52 + 0.030*sl 0.54 + 0.021*sl 0.60 + 0.016*sl t r 0.26 0.16 + 0.052*sl 0.15 + 0.052*sl 0.14 + 0.054*sl t f 0.27 0.20 + 0.031*sl 0.22 + 0.024*sl 0.25 + 0.021*sl b to y t plh 0.47 0.42 + 0.029*sl 0.43 + 0.026*sl 0.44 + 0.025*sl t phl 0.43 0.38 + 0.025*sl 0.40 + 0.019*sl 0.44 + 0.015*sl t r 0.26 0.16 + 0.052*sl 0.16 + 0.052*sl 0.14 + 0.054*sl t f 0.21 0.15 + 0.030*sl 0.17 + 0.024*sl 0.19 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-78 sec asic xn3/xn3d3 3-input exclusive-nor with 1x/3x drive logic symbol cell data input load (sl) gate count kg80 xn3 xn3d3 xn3 xn3d3 abcabc 1.2 0.8 1.8 1.2 0.8 1.8 5.0 6.0 KGM80 xn3 xn3d3 xn3 xn3d3 abcabc 2.1 1.0 2.2 2.2 1.0 2.2 5.0 6.0 y a b c truth table abcy 0001 0010 0100 0111 1000 1011 1101 1110
sec asic 3-79 kg80/KGM80 xn3/xn3d3 3-input exclusive-nor with 1x/3x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 xn3 kg80 xn3d3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.40 0.31 + 0.047*sl 0.32 + 0.043*sl 0.33 + 0.042*sl t phl 0.33 0.25 + 0.037*sl 0.27 + 0.031*sl 0.29 + 0.027*sl t r 0.29 0.12 + 0.089*sl 0.12 + 0.088*sl 0.11 + 0.089*sl t f 0.20 0.10 + 0.051*sl 0.11 + 0.046*sl 0.13 + 0.043*sl b to y t plh 0.67 0.58 + 0.043*sl 0.59 + 0.041*sl 0.59 + 0.041*sl t phl 0.69 0.61 + 0.037*sl 0.63 + 0.028*sl 0.66 + 0.025*sl t r 0.28 0.11 + 0.083*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.045*sl 0.13 + 0.040*sl 0.13 + 0.040*sl c to y t plh 0.56 0.47 + 0.043*sl 0.48 + 0.041*sl 0.48 + 0.041*sl t phl 0.56 0.49 + 0.037*sl 0.51 + 0.028*sl 0.54 + 0.025*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.08 + 0.090*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.040*sl 0.13 + 0.040*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.41 0.37 + 0.021*sl 0.38 + 0.016*sl 0.39 + 0.015*sl t phl 0.33 0.30 + 0.018*sl 0.30 + 0.016*sl 0.32 + 0.013*sl t r 0.21 0.16 + 0.026*sl 0.15 + 0.028*sl 0.15 + 0.029*sl t f 0.18 0.13 + 0.023*sl 0.14 + 0.020*sl 0.15 + 0.018*sl b to y t plh 0.68 0.65 + 0.018*sl 0.65 + 0.015*sl 0.66 + 0.014*sl t phl 0.71 0.67 + 0.018*sl 0.68 + 0.014*sl 0.70 + 0.012*sl t r 0.18 0.13 + 0.026*sl 0.12 + 0.028*sl 0.12 + 0.028*sl t f 0.18 0.15 + 0.019*sl 0.15 + 0.016*sl 0.16 + 0.014*sl c to y t plh 0.57 0.53 + 0.018*sl 0.54 + 0.015*sl 0.55 + 0.014*sl t phl 0.58 0.55 + 0.018*sl 0.55 + 0.014*sl 0.57 + 0.012*sl t r 0.18 0.13 + 0.026*sl 0.12 + 0.028*sl 0.12 + 0.028*sl t f 0.18 0.15 + 0.019*sl 0.15 + 0.016*sl 0.16 + 0.014*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-80 sec asic xn3/xn3d3 3-input exclusive-nor with 1x/3x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 xn3 KGM80 xn3d3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.53 0.41 + 0.059*sl 0.43 + 0.051*sl 0.45 + 0.050*sl t phl 0.43 0.34 + 0.044*sl 0.37 + 0.033*sl 0.43 + 0.028*sl t r 0.38 0.16 + 0.108*sl 0.17 + 0.106*sl 0.15 + 0.108*sl t f 0.25 0.14 + 0.057*sl 0.16 + 0.049*sl 0.21 + 0.044*sl b to y t plh 0.95 0.84 + 0.053*sl 0.85 + 0.050*sl 0.85 + 0.050*sl t phl 0.97 0.88 + 0.044*sl 0.92 + 0.030*sl 0.97 + 0.025*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.12 + 0.109*sl t f 0.26 0.16 + 0.049*sl 0.18 + 0.042*sl 0.19 + 0.041*sl c to y t plh 0.78 0.68 + 0.053*sl 0.69 + 0.050*sl 0.69 + 0.050*sl t phl 0.79 0.70 + 0.044*sl 0.74 + 0.030*sl 0.80 + 0.025*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.26 0.16 + 0.049*sl 0.18 + 0.042*sl 0.19 + 0.041*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.54 0.49 + 0.024*sl 0.50 + 0.020*sl 0.53 + 0.018*sl t phl 0.48 0.43 + 0.024*sl 0.44 + 0.019*sl 0.49 + 0.015*sl t r 0.26 0.18 + 0.038*sl 0.19 + 0.036*sl 0.20 + 0.035*sl t f 0.24 0.18 + 0.030*sl 0.20 + 0.023*sl 0.25 + 0.019*sl b to y t plh 0.97 0.92 + 0.022*sl 0.93 + 0.018*sl 0.95 + 0.017*sl t phl 1.01 0.96 + 0.023*sl 0.98 + 0.016*sl 1.02 + 0.012*sl t r 0.23 0.16 + 0.036*sl 0.16 + 0.034*sl 0.16 + 0.035*sl t f 0.24 0.20 + 0.023*sl 0.21 + 0.018*sl 0.24 + 0.015*sl c to y t plh 0.80 0.75 + 0.022*sl 0.76 + 0.018*sl 0.78 + 0.017*sl t phl 0.83 0.79 + 0.023*sl 0.80 + 0.017*sl 0.85 + 0.012*sl t r 0.23 0.15 + 0.036*sl 0.16 + 0.034*sl 0.15 + 0.035*sl t f 0.24 0.19 + 0.023*sl 0.21 + 0.018*sl 0.24 + 0.015*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-81 kg80/KGM80 xo2/xo2d2 2-input exclusive-or with 1x/2x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 xo2 kg80 xo2d2 input load (sl) gate count kg80 xo2 xo2d2 xo2 xo2d2 abab 0.9 1.2 0.9 1.1 3.0 4.0 KGM80 xo2 xo2d2 xo2 xo2d2 abab 1.0 2.0 1.0 2.0 3.0 4.0 y a b [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.50 0.41 + 0.043*sl 0.41 + 0.041*sl 0.41 + 0.042*sl t phl 0.41 0.33 + 0.040*sl 0.36 + 0.030*sl 0.39 + 0.025*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.088*sl 0.08 + 0.090*sl t f 0.23 0.14 + 0.045*sl 0.15 + 0.040*sl 0.15 + 0.040*sl b to y t plh 0.37 0.28 + 0.043*sl 0.29 + 0.042*sl 0.29 + 0.042*sl t phl 0.30 0.24 + 0.033*sl 0.25 + 0.028*sl 0.27 + 0.025*sl t r 0.27 0.10 + 0.087*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.18 0.09 + 0.045*sl 0.10 + 0.042*sl 0.10 + 0.041*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.49 0.44 + 0.023*sl 0.45 + 0.021*sl 0.45 + 0.021*sl t phl 0.41 0.36 + 0.024*sl 0.38 + 0.019*sl 0.40 + 0.015*sl t r 0.20 0.12 + 0.040*sl 0.11 + 0.043*sl 0.10 + 0.044*sl t f 0.20 0.15 + 0.026*sl 0.16 + 0.022*sl 0.17 + 0.020*sl b to y t plh 0.36 0.31 + 0.023*sl 0.32 + 0.022*sl 0.32 + 0.021*sl t phl 0.30 0.26 + 0.021*sl 0.27 + 0.017*sl 0.29 + 0.015*sl t r 0.20 0.11 + 0.043*sl 0.11 + 0.043*sl 0.10 + 0.044*sl t f 0.16 0.11 + 0.026*sl 0.11 + 0.023*sl 0.12 + 0.022*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = truth table aby 000 011 101 110
kg80/KGM80 3-82 sec asic xo2/xo2d2 2-input exclusive-or with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 xo2 KGM80 xo2d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.66 0.56 + 0.053*sl 0.56 + 0.050*sl 0.57 + 0.050*sl t phl 0.56 0.46 + 0.048*sl 0.51 + 0.032*sl 0.58 + 0.025*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.107*sl 0.12 + 0.109*sl t f 0.28 0.18 + 0.050*sl 0.21 + 0.042*sl 0.22 + 0.040*sl b to y t plh 0.48 0.38 + 0.053*sl 0.39 + 0.050*sl 0.39 + 0.050*sl t phl 0.40 0.32 + 0.038*sl 0.35 + 0.029*sl 0.39 + 0.025*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.107*sl 0.12 + 0.109*sl t f 0.22 0.12 + 0.050*sl 0.14 + 0.043*sl 0.15 + 0.042*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.65 0.59 + 0.029*sl 0.60 + 0.026*sl 0.61 + 0.025*sl t phl 0.57 0.51 + 0.030*sl 0.53 + 0.021*sl 0.59 + 0.016*sl t r 0.26 0.15 + 0.052*sl 0.15 + 0.052*sl 0.14 + 0.054*sl t f 0.26 0.20 + 0.031*sl 0.22 + 0.024*sl 0.25 + 0.021*sl b to y t plh 0.47 0.41 + 0.030*sl 0.42 + 0.026*sl 0.43 + 0.025*sl t phl 0.42 0.37 + 0.025*sl 0.39 + 0.019*sl 0.43 + 0.015*sl t r 0.26 0.15 + 0.053*sl 0.16 + 0.052*sl 0.14 + 0.054*sl t f 0.21 0.15 + 0.030*sl 0.16 + 0.024*sl 0.19 + 0.022*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-83 kg80/KGM80 xo3/xo3d3 3-input exclusive-or with 1x/3x drive logic symbol icell data input load (sl) gate count kg80 xo3 xo3d3 xo3 xo3d3 abcabc 1.7 0.9 1.7 1.7 0.9 1.7 5.0 6.0 KGM80 xo3 xo3d3 xo3 xo3d3 abcabc 2.0 1.0 2.0 2.0 1.0 2.0 5.0 6.0 y a b c truth table abcy 0000 0011 0101 0110 1001 1010 1100 1111
kg80/KGM80 3-84 sec asic xo3/xo3d3 3-input exclusive-or with 1x/3x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 xo3 kg80 xo3d3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.37 0.28 + 0.043*sl 0.29 + 0.041*sl 0.29 + 0.042*sl t phl 0.31 0.24 + 0.034*sl 0.25 + 0.027*sl 0.27 + 0.025*sl t r 0.27 0.10 + 0.087*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.18 0.09 + 0.043*sl 0.10 + 0.042*sl 0.10 + 0.041*sl b to y t plh 0.67 0.58 + 0.043*sl 0.59 + 0.041*sl 0.59 + 0.041*sl t phl 0.68 0.61 + 0.036*sl 0.63 + 0.028*sl 0.65 + 0.025*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.20 0.12 + 0.043*sl 0.12 + 0.041*sl 0.13 + 0.040*sl c to y t plh 0.55 0.47 + 0.043*sl 0.47 + 0.041*sl 0.47 + 0.042*sl t phl 0.56 0.48 + 0.036*sl 0.50 + 0.028*sl 0.53 + 0.025*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.08 + 0.090*sl t f 0.20 0.12 + 0.043*sl 0.12 + 0.040*sl 0.12 + 0.041*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.37 0.33 + 0.018*sl 0.34 + 0.015*sl 0.35 + 0.014*sl t phl 0.32 0.29 + 0.017*sl 0.29 + 0.014*sl 0.31 + 0.011*sl t r 0.17 0.12 + 0.027*sl 0.12 + 0.028*sl 0.11 + 0.029*sl t f 0.16 0.12 + 0.019*sl 0.13 + 0.016*sl 0.14 + 0.015*sl b to y t plh 0.68 0.65 + 0.017*sl 0.65 + 0.015*sl 0.66 + 0.014*sl t phl 0.70 0.67 + 0.018*sl 0.68 + 0.014*sl 0.69 + 0.012*sl t r 0.18 0.13 + 0.026*sl 0.12 + 0.028*sl 0.12 + 0.028*sl t f 0.18 0.15 + 0.019*sl 0.15 + 0.016*sl 0.16 + 0.014*sl c to y t plh 0.57 0.53 + 0.018*sl 0.54 + 0.015*sl 0.54 + 0.014*sl t phl 0.58 0.54 + 0.018*sl 0.55 + 0.014*sl 0.57 + 0.012*sl t r 0.18 0.12 + 0.026*sl 0.12 + 0.028*sl 0.12 + 0.028*sl t f 0.18 0.15 + 0.019*sl 0.15 + 0.016*sl 0.16 + 0.014*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-85 kg80/KGM80 xo3/xo3d3 3-input exclusive-or with 1x/3x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 xo3 KGM80 xo3d3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.48 0.38 + 0.053*sl 0.39 + 0.050*sl 0.39 + 0.050*sl t phl 0.41 0.33 + 0.038*sl 0.36 + 0.029*sl 0.40 + 0.025*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.107*sl 0.12 + 0.109*sl t f 0.22 0.12 + 0.049*sl 0.14 + 0.043*sl 0.15 + 0.042*sl b to y t plh 0.95 0.84 + 0.053*sl 0.85 + 0.050*sl 0.85 + 0.050*sl t phl 0.96 0.87 + 0.043*sl 0.91 + 0.030*sl 0.97 + 0.025*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.26 0.16 + 0.049*sl 0.18 + 0.042*sl 0.18 + 0.041*sl c to y t plh 0.78 0.67 + 0.053*sl 0.68 + 0.050*sl 0.68 + 0.050*sl t phl 0.78 0.69 + 0.043*sl 0.73 + 0.030*sl 0.78 + 0.025*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.26 0.16 + 0.050*sl 0.18 + 0.042*sl 0.19 + 0.041*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.48 0.44 + 0.022*sl 0.45 + 0.018*sl 0.47 + 0.017*sl t phl 0.45 0.41 + 0.021*sl 0.42 + 0.016*sl 0.46 + 0.012*sl t r 0.22 0.15 + 0.034*sl 0.15 + 0.035*sl 0.15 + 0.035*sl t f 0.21 0.16 + 0.023*sl 0.18 + 0.018*sl 0.21 + 0.016*sl b to y t plh 0.97 0.92 + 0.022*sl 0.93 + 0.018*sl 0.95 + 0.017*sl t phl 1.00 0.96 + 0.023*sl 0.98 + 0.016*sl 1.02 + 0.012*sl t r 0.23 0.16 + 0.035*sl 0.16 + 0.035*sl 0.16 + 0.035*sl t f 0.24 0.19 + 0.023*sl 0.21 + 0.018*sl 0.24 + 0.015*sl c to y t plh 0.79 0.75 + 0.022*sl 0.76 + 0.018*sl 0.78 + 0.017*sl t phl 0.82 0.77 + 0.023*sl 0.79 + 0.016*sl 0.83 + 0.012*sl t r 0.23 0.16 + 0.036*sl 0.16 + 0.034*sl 0.16 + 0.035*sl t f 0.24 0.19 + 0.023*sl 0.21 + 0.018*sl 0.24 + 0.015*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-86 sec asic ao21/ao21d2 2-and into 2-nor with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 ao21 ao21d2 ao21 ao21d2 abcabc 0.5 0.5 0.7 1.1 1.1 1.5 2.0 2.0 KGM80 ao21 ao21d2 ao21 ao21d2 abcabc 1.0 1.0 1.0 2.0 2.0 1.9 2.0 2.0 a b y c truth table abcy xx10 0x01 x001 11x0
sec asic 3-87 kg80/KGM80 ao21/ao21d2 2-and into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ao21 kg80 ao21d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.32 0.18 + 0.067*sl 0.18 + 0.070*sl 0.17 + 0.071*sl t phl 0.16 0.07 + 0.045*sl 0.09 + 0.034*sl 0.10 + 0.034*sl t r 0.57 0.27 + 0.152*sl 0.25 + 0.159*sl 0.22 + 0.163*sl t f 0.30 0.18 + 0.059*sl 0.18 + 0.062*sl 0.15 + 0.065*sl b to y t plh 0.36 0.23 + 0.067*sl 0.22 + 0.069*sl 0.21 + 0.070*sl t phl 0.15 0.06 + 0.041*sl 0.08 + 0.035*sl 0.08 + 0.034*sl t r 0.64 0.33 + 0.152*sl 0.32 + 0.159*sl 0.29 + 0.163*sl t f 0.28 0.17 + 0.056*sl 0.15 + 0.063*sl 0.13 + 0.066*sl c to y t plh 0.40 0.26 + 0.070*sl 0.26 + 0.071*sl 0.25 + 0.071*sl t phl 0.15 0.09 + 0.030*sl 0.11 + 0.025*sl 0.12 + 0.023*sl t r 0.63 0.32 + 0.156*sl 0.31 + 0.160*sl 0.29 + 0.163*sl t f 0.29 0.20 + 0.044*sl 0.22 + 0.035*sl 0.19 + 0.039*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.26 0.20 + 0.034*sl 0.19 + 0.034*sl 0.19 + 0.035*sl t phl 0.12 0.07 + 0.025*sl 0.09 + 0.020*sl 0.11 + 0.016*sl t r 0.43 0.28 + 0.075*sl 0.28 + 0.078*sl 0.26 + 0.080*sl t f 0.25 0.19 + 0.030*sl 0.19 + 0.029*sl 0.18 + 0.031*sl b to y t plh 0.31 0.25 + 0.033*sl 0.25 + 0.034*sl 0.24 + 0.035*sl t phl 0.12 0.07 + 0.022*sl 0.08 + 0.019*sl 0.09 + 0.017*sl t r 0.52 0.37 + 0.074*sl 0.36 + 0.077*sl 0.34 + 0.080*sl t f 0.23 0.18 + 0.028*sl 0.17 + 0.030*sl 0.16 + 0.032*sl c to y t plh 0.34 0.27 + 0.035*sl 0.27 + 0.035*sl 0.26 + 0.035*sl t phl 0.13 0.09 + 0.018*sl 0.10 + 0.014*sl 0.11 + 0.012*sl t r 0.51 0.36 + 0.077*sl 0.35 + 0.079*sl 0.34 + 0.080*sl t f 0.24 0.20 + 0.018*sl 0.20 + 0.019*sl 0.21 + 0.018*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-88 sec asic ao21/ao21d2 2-and into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ao21 KGM80 ao21d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.42 0.23 + 0.092*sl 0.23 + 0.094*sl 0.23 + 0.094*sl t phl 0.20 0.10 + 0.046*sl 0.13 + 0.038*sl 0.13 + 0.037*sl t r 0.78 0.37 + 0.202*sl 0.36 + 0.207*sl 0.34 + 0.208*sl t f 0.33 0.19 + 0.067*sl 0.19 + 0.070*sl 0.15 + 0.073*sl b to y t plh 0.49 0.30 + 0.093*sl 0.30 + 0.093*sl 0.30 + 0.094*sl t phl 0.19 0.10 + 0.043*sl 0.12 + 0.038*sl 0.13 + 0.037*sl t r 0.87 0.46 + 0.202*sl 0.45 + 0.207*sl 0.44 + 0.209*sl t f 0.31 0.17 + 0.067*sl 0.16 + 0.071*sl 0.14 + 0.074*sl c to y t plh 0.58 0.39 + 0.095*sl 0.39 + 0.094*sl 0.39 + 0.094*sl t phl 0.19 0.13 + 0.031*sl 0.15 + 0.025*sl 0.16 + 0.023*sl t r 0.88 0.47 + 0.202*sl 0.46 + 0.207*sl 0.44 + 0.208*sl t f 0.29 0.21 + 0.039*sl 0.21 + 0.039*sl 0.18 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.35 0.25 + 0.046*sl 0.25 + 0.047*sl 0.25 + 0.047*sl t phl 0.16 0.11 + 0.025*sl 0.12 + 0.020*sl 0.14 + 0.018*sl t r 0.61 0.41 + 0.100*sl 0.41 + 0.102*sl 0.39 + 0.104*sl t f 0.27 0.20 + 0.036*sl 0.21 + 0.034*sl 0.19 + 0.035*sl b to y t plh 0.43 0.34 + 0.047*sl 0.34 + 0.047*sl 0.33 + 0.047*sl t phl 0.16 0.12 + 0.022*sl 0.13 + 0.020*sl 0.14 + 0.019*sl t r 0.72 0.52 + 0.100*sl 0.52 + 0.102*sl 0.50 + 0.104*sl t f 0.26 0.19 + 0.034*sl 0.19 + 0.034*sl 0.17 + 0.036*sl c to y t plh 0.50 0.40 + 0.048*sl 0.40 + 0.047*sl 0.40 + 0.047*sl t phl 0.16 0.13 + 0.017*sl 0.13 + 0.014*sl 0.16 + 0.012*sl t r 0.72 0.52 + 0.100*sl 0.52 + 0.102*sl 0.50 + 0.104*sl t f 0.25 0.21 + 0.020*sl 0.21 + 0.019*sl 0.20 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-89 kg80/KGM80 ao211/ao211d2 2-and into 3-nor with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 ao211 ao211d2 ao211 ao211d2 abcdabcd 0.5 0.5 0.6 0.7 1.1 1.1 1.3 1.5 2.0 4.0 KGM80 ao211 ao211d2 ao211 ao211d2 abcdabcd 1.0 1.0 1.0 1.0 2.0 2.0 1.9 1.9 2.0 4.0 a b y c d truth table abcdy 11xx0 xx1x0 xxx10 x0001 0x001
kg80/KGM80 3-90 sec asic ao211/ao211d2 2-and into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ao211 kg80 ao211d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.42 0.23 + 0.097*sl 0.22 + 0.100*sl 0.21 + 0.101*sl t phl 0.17 0.08 + 0.043*sl 0.10 + 0.034*sl 0.11 + 0.034*sl t r 0.90 0.44 + 0.229*sl 0.43 + 0.237*sl 0.41 + 0.238*sl t f 0.31 0.20 + 0.058*sl 0.19 + 0.062*sl 0.17 + 0.065*sl b to y t plh 0.48 0.29 + 0.097*sl 0.28 + 0.100*sl 0.27 + 0.101*sl t phl 0.15 0.07 + 0.040*sl 0.09 + 0.035*sl 0.09 + 0.034*sl t r 1.00 0.54 + 0.231*sl 0.52 + 0.237*sl 0.51 + 0.238*sl t f 0.30 0.18 + 0.059*sl 0.17 + 0.063*sl 0.15 + 0.066*sl c to y t plh 0.57 0.37 + 0.101*sl 0.36 + 0.102*sl 0.36 + 0.102*sl t phl 0.16 0.10 + 0.031*sl 0.12 + 0.025*sl 0.13 + 0.023*sl t r 1.02 0.56 + 0.231*sl 0.55 + 0.235*sl 0.53 + 0.236*sl t f 0.28 0.21 + 0.035*sl 0.21 + 0.037*sl 0.19 + 0.040*sl d to y t plh 0.58 0.37 + 0.102*sl 0.37 + 0.102*sl 0.37 + 0.102*sl t phl 0.17 0.11 + 0.029*sl 0.12 + 0.025*sl 0.13 + 0.024*sl t r 1.02 0.55 + 0.232*sl 0.54 + 0.235*sl 0.53 + 0.236*sl t f 0.31 0.23 + 0.041*sl 0.24 + 0.037*sl 0.22 + 0.039*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.30 0.21 + 0.045*sl 0.20 + 0.049*sl 0.19 + 0.050*sl t phl 0.12 0.06 + 0.026*sl 0.08 + 0.020*sl 0.10 + 0.016*sl t r 0.62 0.40 + 0.114*sl 0.39 + 0.115*sl 0.37 + 0.118*sl t f 0.24 0.18 + 0.032*sl 0.18 + 0.030*sl 0.17 + 0.032*sl b to y t plh 0.37 0.27 + 0.048*sl 0.27 + 0.049*sl 0.26 + 0.050*sl t phl 0.11 0.07 + 0.022*sl 0.07 + 0.019*sl 0.09 + 0.017*sl t r 0.74 0.51 + 0.112*sl 0.51 + 0.116*sl 0.49 + 0.118*sl t f 0.22 0.17 + 0.028*sl 0.16 + 0.030*sl 0.15 + 0.032*sl c to y t plh 0.45 0.35 + 0.051*sl 0.35 + 0.051*sl 0.35 + 0.051*sl t phl 0.13 0.09 + 0.019*sl 0.10 + 0.015*sl 0.12 + 0.012*sl t r 0.76 0.53 + 0.114*sl 0.53 + 0.116*sl 0.51 + 0.117*sl t f 0.24 0.20 + 0.020*sl 0.20 + 0.017*sl 0.20 + 0.019*sl d to y t plh 0.46 0.36 + 0.051*sl 0.36 + 0.051*sl 0.36 + 0.051*sl t phl 0.13 0.10 + 0.018*sl 0.11 + 0.014*sl 0.12 + 0.012*sl t r 0.76 0.53 + 0.114*sl 0.52 + 0.116*sl 0.51 + 0.118*sl t f 0.26 0.22 + 0.019*sl 0.22 + 0.019*sl 0.23 + 0.018*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-91 kg80/KGM80 ao211/ao211d2 2-and into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ao211 KGM80 ao211d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.57 0.30 + 0.138*sl 0.29 + 0.139*sl 0.29 + 0.139*sl t phl 0.21 0.12 + 0.045*sl 0.14 + 0.037*sl 0.15 + 0.037*sl t r 1.29 0.68 + 0.308*sl 0.67 + 0.310*sl 0.69 + 0.308*sl t f 0.35 0.22 + 0.066*sl 0.21 + 0.070*sl 0.17 + 0.073*sl b to y t plh 0.68 0.40 + 0.138*sl 0.40 + 0.139*sl 0.40 + 0.139*sl t phl 0.20 0.12 + 0.042*sl 0.13 + 0.038*sl 0.14 + 0.037*sl t r 1.43 0.81 + 0.308*sl 0.81 + 0.310*sl 0.83 + 0.309*sl t f 0.33 0.20 + 0.067*sl 0.18 + 0.072*sl 0.16 + 0.074*sl c to y t plh 0.87 0.59 + 0.141*sl 0.59 + 0.140*sl 0.60 + 0.139*sl t phl 0.20 0.14 + 0.030*sl 0.16 + 0.024*sl 0.17 + 0.023*sl t r 1.47 0.86 + 0.303*sl 0.85 + 0.307*sl 0.84 + 0.308*sl t f 0.30 0.22 + 0.039*sl 0.22 + 0.039*sl 0.20 + 0.042*sl d to y t plh 0.91 0.63 + 0.142*sl 0.63 + 0.140*sl 0.64 + 0.139*sl t phl 0.21 0.14 + 0.031*sl 0.16 + 0.025*sl 0.18 + 0.023*sl t r 1.46 0.86 + 0.304*sl 0.85 + 0.307*sl 0.84 + 0.308*sl t f 0.32 0.25 + 0.038*sl 0.24 + 0.040*sl 0.22 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.38 0.26 + 0.064*sl 0.24 + 0.069*sl 0.24 + 0.070*sl t phl 0.15 0.10 + 0.026*sl 0.11 + 0.021*sl 0.14 + 0.018*sl t r 0.89 0.58 + 0.154*sl 0.58 + 0.154*sl 0.57 + 0.155*sl t f 0.26 0.19 + 0.036*sl 0.19 + 0.034*sl 0.17 + 0.035*sl b to y t plh 0.51 0.37 + 0.069*sl 0.37 + 0.069*sl 0.37 + 0.069*sl t phl 0.15 0.11 + 0.023*sl 0.12 + 0.020*sl 0.13 + 0.019*sl t r 1.06 0.75 + 0.153*sl 0.75 + 0.155*sl 0.74 + 0.155*sl t f 0.24 0.17 + 0.034*sl 0.17 + 0.034*sl 0.15 + 0.036*sl c to y t plh 0.71 0.56 + 0.072*sl 0.57 + 0.070*sl 0.57 + 0.070*sl t phl 0.16 0.13 + 0.017*sl 0.14 + 0.014*sl 0.16 + 0.012*sl t r 1.10 0.81 + 0.149*sl 0.80 + 0.152*sl 0.78 + 0.154*sl t f 0.25 0.21 + 0.020*sl 0.21 + 0.019*sl 0.20 + 0.020*sl d to y t plh 0.75 0.60 + 0.072*sl 0.61 + 0.071*sl 0.61 + 0.070*sl t phl 0.17 0.13 + 0.018*sl 0.14 + 0.014*sl 0.17 + 0.012*sl t r 1.10 0.80 + 0.150*sl 0.80 + 0.152*sl 0.78 + 0.154*sl t f 0.27 0.23 + 0.021*sl 0.23 + 0.020*sl 0.23 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-92 sec asic ao22/ao22d2 two 2-ands into 2-nor with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 ao22 ao22d2 ao22 ao22d2 abcdabcd 0.5 0.5 0.7 0.7 0.6 0.5 0.7 0.7 2.0 4.0 KGM80 ao22 ao22d2 ao22 ao22d2 abcdabcd 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 2.0 4.0 c d a b y truth table abcdy 11xx0 xx110 0x0x1 0xx01 x0x01 x00x1
sec asic 3-93 kg80/KGM80 ao22/ao22d2 two 2-ands into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ao22 kg80 ao22d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.36 0.22 + 0.068*sl 0.22 + 0.070*sl 0.21 + 0.071*sl t phl 0.17 0.08 + 0.043*sl 0.11 + 0.034*sl 0.11 + 0.034*sl t r 0.63 0.32 + 0.155*sl 0.31 + 0.160*sl 0.29 + 0.163*sl t f 0.34 0.23 + 0.056*sl 0.21 + 0.062*sl 0.19 + 0.065*sl b to y t plh 0.40 0.26 + 0.068*sl 0.26 + 0.070*sl 0.25 + 0.070*sl t phl 0.16 0.08 + 0.040*sl 0.09 + 0.035*sl 0.09 + 0.034*sl t r 0.70 0.40 + 0.153*sl 0.38 + 0.160*sl 0.36 + 0.164*sl t f 0.32 0.21 + 0.056*sl 0.19 + 0.063*sl 0.17 + 0.066*sl c to y t plh 0.41 0.27 + 0.072*sl 0.27 + 0.071*sl 0.27 + 0.072*sl t phl 0.22 0.15 + 0.036*sl 0.15 + 0.035*sl 0.16 + 0.034*sl t r 0.64 0.33 + 0.155*sl 0.32 + 0.160*sl 0.30 + 0.163*sl t f 0.39 0.26 + 0.062*sl 0.27 + 0.062*sl 0.24 + 0.065*sl d to y t plh 0.45 0.31 + 0.071*sl 0.31 + 0.071*sl 0.31 + 0.071*sl t phl 0.21 0.13 + 0.038*sl 0.14 + 0.035*sl 0.14 + 0.034*sl t r 0.71 0.39 + 0.157*sl 0.39 + 0.160*sl 0.37 + 0.163*sl t f 0.37 0.25 + 0.061*sl 0.24 + 0.064*sl 0.22 + 0.067*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.49 0.45 + 0.022*sl 0.45 + 0.020*sl 0.45 + 0.021*sl t phl 0.35 0.32 + 0.017*sl 0.33 + 0.014*sl 0.34 + 0.012*sl t r 0.18 0.10 + 0.041*sl 0.09 + 0.043*sl 0.08 + 0.045*sl t f 0.13 0.09 + 0.021*sl 0.09 + 0.019*sl 0.09 + 0.020*sl b to y t plh 0.54 0.49 + 0.021*sl 0.50 + 0.021*sl 0.49 + 0.021*sl t phl 0.34 0.31 + 0.018*sl 0.31 + 0.014*sl 0.32 + 0.012*sl t r 0.18 0.10 + 0.039*sl 0.09 + 0.043*sl 0.09 + 0.044*sl t f 0.13 0.09 + 0.021*sl 0.09 + 0.020*sl 0.09 + 0.020*sl c to y t plh 0.54 0.50 + 0.021*sl 0.50 + 0.020*sl 0.50 + 0.021*sl t phl 0.42 0.38 + 0.017*sl 0.39 + 0.014*sl 0.40 + 0.012*sl t r 0.18 0.11 + 0.038*sl 0.09 + 0.044*sl 0.09 + 0.044*sl t f 0.13 0.09 + 0.021*sl 0.09 + 0.019*sl 0.09 + 0.020*sl d to y t plh 0.59 0.55 + 0.021*sl 0.55 + 0.021*sl 0.55 + 0.020*sl t phl 0.40 0.37 + 0.017*sl 0.38 + 0.014*sl 0.38 + 0.012*sl t r 0.18 0.10 + 0.041*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.13 0.09 + 0.021*sl 0.09 + 0.019*sl 0.09 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-94 sec asic ao22/ao22d2 two 2-ands into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ao22 KGM80 ao22d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.48 0.29 + 0.094*sl 0.29 + 0.094*sl 0.29 + 0.094*sl t phl 0.21 0.11 + 0.046*sl 0.14 + 0.038*sl 0.14 + 0.037*sl t r 0.87 0.46 + 0.204*sl 0.45 + 0.208*sl 0.44 + 0.209*sl t f 0.38 0.25 + 0.064*sl 0.23 + 0.070*sl 0.20 + 0.073*sl b to y t plh 0.55 0.36 + 0.093*sl 0.36 + 0.094*sl 0.36 + 0.094*sl t phl 0.20 0.11 + 0.043*sl 0.13 + 0.038*sl 0.14 + 0.037*sl t r 0.96 0.56 + 0.204*sl 0.55 + 0.208*sl 0.54 + 0.209*sl t f 0.36 0.23 + 0.066*sl 0.21 + 0.071*sl 0.19 + 0.074*sl c to y t plh 0.61 0.41 + 0.096*sl 0.42 + 0.095*sl 0.42 + 0.094*sl t phl 0.28 0.20 + 0.042*sl 0.21 + 0.038*sl 0.22 + 0.037*sl t r 0.89 0.49 + 0.201*sl 0.47 + 0.207*sl 0.46 + 0.208*sl t f 0.44 0.30 + 0.067*sl 0.30 + 0.071*sl 0.27 + 0.073*sl d to y t plh 0.68 0.49 + 0.096*sl 0.49 + 0.094*sl 0.49 + 0.094*sl t phl 0.27 0.19 + 0.042*sl 0.20 + 0.038*sl 0.21 + 0.037*sl t r 0.98 0.57 + 0.203*sl 0.56 + 0.207*sl 0.55 + 0.208*sl t f 0.42 0.28 + 0.070*sl 0.28 + 0.072*sl 0.26 + 0.074*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.69 0.63 + 0.026*sl 0.64 + 0.025*sl 0.64 + 0.025*sl t phl 0.49 0.45 + 0.019*sl 0.46 + 0.015*sl 0.48 + 0.012*sl t r 0.24 0.14 + 0.051*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.16 0.11 + 0.022*sl 0.12 + 0.021*sl 0.12 + 0.020*sl b to y t plh 0.76 0.71 + 0.026*sl 0.71 + 0.025*sl 0.71 + 0.025*sl t phl 0.48 0.44 + 0.019*sl 0.45 + 0.015*sl 0.48 + 0.012*sl t r 0.24 0.14 + 0.050*sl 0.14 + 0.053*sl 0.12 + 0.054*sl t f 0.16 0.11 + 0.024*sl 0.12 + 0.020*sl 0.12 + 0.020*sl c to y t plh 0.81 0.76 + 0.026*sl 0.76 + 0.025*sl 0.77 + 0.025*sl t phl 0.57 0.53 + 0.020*sl 0.54 + 0.015*sl 0.57 + 0.012*sl t r 0.24 0.14 + 0.050*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.16 0.11 + 0.023*sl 0.12 + 0.020*sl 0.12 + 0.021*sl d to y t plh 0.89 0.84 + 0.026*sl 0.84 + 0.025*sl 0.84 + 0.025*sl t phl 0.56 0.52 + 0.020*sl 0.53 + 0.015*sl 0.56 + 0.012*sl t r 0.24 0.14 + 0.050*sl 0.14 + 0.053*sl 0.12 + 0.054*sl t f 0.16 0.11 + 0.023*sl 0.12 + 0.020*sl 0.12 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-95 kg80/KGM80 ao22a/ao22d2a 2-and and 2-nor into 2-nor with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 ao22a ao22d2a ao22a ao22d2a abcdabcd 0.9 0.8 0.9 0.9 0.9 0.9 0.9 0.9 4.0 5.0 KGM80 ao22a ao22d2a ao22a ao22d2a abcdabcd 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 4.0 5.0 c d a b y truth table abcdy 11xx0 xx000 other states 1
kg80/KGM80 3-96 sec asic ao22a/ao22d2a 2-and and 2-nor into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ao22a kg80 ao22d2a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.36 0.22 + 0.068*sl 0.22 + 0.070*sl 0.21 + 0.071*sl t phl 0.17 0.09 + 0.043*sl 0.11 + 0.035*sl 0.11 + 0.034*sl t r 0.64 0.33 + 0.155*sl 0.32 + 0.160*sl 0.30 + 0.163*sl t f 0.34 0.23 + 0.056*sl 0.22 + 0.061*sl 0.18 + 0.066*sl b to y t plh 0.40 0.27 + 0.068*sl 0.26 + 0.070*sl 0.25 + 0.071*sl t phl 0.16 0.08 + 0.040*sl 0.09 + 0.035*sl 0.09 + 0.034*sl t r 0.71 0.40 + 0.154*sl 0.39 + 0.160*sl 0.36 + 0.164*sl t f 0.32 0.21 + 0.055*sl 0.19 + 0.063*sl 0.17 + 0.066*sl c to y t plh 0.43 0.29 + 0.074*sl 0.29 + 0.072*sl 0.29 + 0.072*sl t phl 0.37 0.29 + 0.037*sl 0.30 + 0.035*sl 0.30 + 0.034*sl t r 0.63 0.32 + 0.160*sl 0.31 + 0.162*sl 0.31 + 0.163*sl t f 0.34 0.21 + 0.067*sl 0.21 + 0.067*sl 0.20 + 0.068*sl d to y t plh 0.48 0.33 + 0.073*sl 0.33 + 0.072*sl 0.34 + 0.071*sl t phl 0.38 0.30 + 0.037*sl 0.31 + 0.035*sl 0.31 + 0.035*sl t r 0.70 0.38 + 0.160*sl 0.38 + 0.162*sl 0.37 + 0.163*sl t f 0.34 0.21 + 0.066*sl 0.20 + 0.068*sl 0.20 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.49 0.45 + 0.021*sl 0.45 + 0.021*sl 0.45 + 0.021*sl t phl 0.35 0.32 + 0.017*sl 0.33 + 0.014*sl 0.34 + 0.012*sl t r 0.18 0.10 + 0.042*sl 0.10 + 0.043*sl 0.08 + 0.045*sl t f 0.13 0.09 + 0.020*sl 0.10 + 0.019*sl 0.09 + 0.020*sl b to y t plh 0.54 0.49 + 0.022*sl 0.50 + 0.021*sl 0.50 + 0.020*sl t phl 0.34 0.31 + 0.017*sl 0.31 + 0.014*sl 0.33 + 0.012*sl t r 0.18 0.11 + 0.039*sl 0.10 + 0.043*sl 0.09 + 0.045*sl t f 0.13 0.09 + 0.021*sl 0.09 + 0.019*sl 0.09 + 0.020*sl c to y t plh 0.56 0.51 + 0.022*sl 0.52 + 0.020*sl 0.52 + 0.021*sl t phl 0.56 0.52 + 0.018*sl 0.53 + 0.014*sl 0.54 + 0.012*sl t r 0.18 0.10 + 0.041*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.13 0.10 + 0.018*sl 0.09 + 0.019*sl 0.09 + 0.020*sl d to y t plh 0.61 0.57 + 0.021*sl 0.57 + 0.020*sl 0.57 + 0.021*sl t phl 0.57 0.53 + 0.018*sl 0.54 + 0.014*sl 0.55 + 0.012*sl t r 0.18 0.10 + 0.042*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.13 0.09 + 0.020*sl 0.09 + 0.019*sl 0.09 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-97 kg80/KGM80 ao22a/ao22d2a 2-and and 2-nor into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ao22a KGM80 ao22d2a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.49 0.30 + 0.094*sl 0.30 + 0.094*sl 0.30 + 0.094*sl t phl 0.21 0.12 + 0.046*sl 0.14 + 0.038*sl 0.14 + 0.037*sl t r 0.89 0.48 + 0.204*sl 0.47 + 0.208*sl 0.46 + 0.209*sl t f 0.38 0.25 + 0.065*sl 0.24 + 0.070*sl 0.20 + 0.073*sl b to y t plh 0.55 0.37 + 0.093*sl 0.37 + 0.094*sl 0.37 + 0.094*sl t phl 0.20 0.11 + 0.043*sl 0.13 + 0.038*sl 0.14 + 0.037*sl t r 0.98 0.57 + 0.204*sl 0.56 + 0.208*sl 0.55 + 0.209*sl t f 0.36 0.23 + 0.066*sl 0.22 + 0.071*sl 0.19 + 0.074*sl c to y t plh 0.65 0.46 + 0.097*sl 0.46 + 0.095*sl 0.47 + 0.094*sl t phl 0.46 0.38 + 0.041*sl 0.38 + 0.038*sl 0.39 + 0.038*sl t r 0.89 0.48 + 0.205*sl 0.47 + 0.208*sl 0.47 + 0.208*sl t f 0.41 0.27 + 0.071*sl 0.27 + 0.073*sl 0.25 + 0.074*sl d to y t plh 0.73 0.53 + 0.096*sl 0.54 + 0.094*sl 0.54 + 0.094*sl t phl 0.47 0.39 + 0.042*sl 0.40 + 0.039*sl 0.41 + 0.037*sl t r 0.98 0.57 + 0.206*sl 0.57 + 0.208*sl 0.56 + 0.208*sl t f 0.41 0.27 + 0.073*sl 0.26 + 0.074*sl 0.25 + 0.074*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.69 0.64 + 0.026*sl 0.64 + 0.025*sl 0.64 + 0.025*sl t phl 0.49 0.45 + 0.019*sl 0.46 + 0.015*sl 0.49 + 0.012*sl t r 0.24 0.14 + 0.049*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.16 0.11 + 0.022*sl 0.12 + 0.020*sl 0.12 + 0.021*sl b to y t plh 0.77 0.71 + 0.026*sl 0.72 + 0.025*sl 0.72 + 0.025*sl t phl 0.48 0.44 + 0.019*sl 0.45 + 0.015*sl 0.48 + 0.012*sl t r 0.24 0.14 + 0.050*sl 0.14 + 0.053*sl 0.12 + 0.054*sl t f 0.16 0.11 + 0.023*sl 0.12 + 0.021*sl 0.12 + 0.020*sl c to y t plh 0.86 0.80 + 0.026*sl 0.81 + 0.025*sl 0.81 + 0.025*sl t phl 0.74 0.70 + 0.020*sl 0.72 + 0.015*sl 0.74 + 0.012*sl t r 0.24 0.14 + 0.050*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.16 0.12 + 0.022*sl 0.12 + 0.021*sl 0.12 + 0.021*sl d to y t plh 0.93 0.88 + 0.026*sl 0.89 + 0.025*sl 0.89 + 0.025*sl t phl 0.76 0.72 + 0.019*sl 0.73 + 0.015*sl 0.76 + 0.012*sl t r 0.24 0.14 + 0.050*sl 0.14 + 0.053*sl 0.12 + 0.054*sl t f 0.16 0.11 + 0.023*sl 0.12 + 0.020*sl 0.12 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-98 sec asic ao222/ao222d2 three 2-ands into 3-nor with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 ao222 ao222d2 ao222 ao222d2 abcdefabcdef 0.9 0.9 0.5 0.8 0.5 0.8 0.9 0.9 0.5 0.8 0.5 0.8 3.0 5.0 KGM80 ao222 ao222d2 ao222 ao222d2 abcdefabcdef 1.0 1.0 1.0 1.0 0.9 0.9 1.0 1.0 1.0 1.0 0.9 0.9 3.0 5.0 c d a b y e f truth table abcdefy 11xxxx0 xx11xx0 xxxx110 other states 1
sec asic 3-99 kg80/KGM80 ao222/ao222d2 three 2-ands into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ao222 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.54 0.34 + 0.100*sl 0.33 + 0.101*sl 0.33 + 0.102*sl t phl 0.20 0.12 + 0.040*sl 0.13 + 0.034*sl 0.13 + 0.034*sl t r 1.13 0.66 + 0.235*sl 0.65 + 0.238*sl 0.64 + 0.239*sl t f 0.40 0.28 + 0.057*sl 0.27 + 0.062*sl 0.25 + 0.065*sl b to y t plh 0.60 0.40 + 0.100*sl 0.40 + 0.100*sl 0.39 + 0.101*sl t phl 0.18 0.10 + 0.038*sl 0.11 + 0.034*sl 0.11 + 0.034*sl t r 1.22 0.75 + 0.235*sl 0.75 + 0.238*sl 0.74 + 0.239*sl t f 0.38 0.26 + 0.057*sl 0.25 + 0.064*sl 0.23 + 0.066*sl c to y t plh 0.66 0.46 + 0.104*sl 0.46 + 0.103*sl 0.46 + 0.103*sl t phl 0.25 0.18 + 0.036*sl 0.18 + 0.034*sl 0.18 + 0.034*sl t r 1.16 0.70 + 0.232*sl 0.69 + 0.235*sl 0.68 + 0.236*sl t f 0.44 0.32 + 0.060*sl 0.32 + 0.063*sl 0.30 + 0.066*sl d to y t plh 0.73 0.52 + 0.103*sl 0.52 + 0.102*sl 0.52 + 0.102*sl t phl 0.23 0.16 + 0.037*sl 0.16 + 0.035*sl 0.17 + 0.034*sl t r 1.26 0.79 + 0.233*sl 0.79 + 0.235*sl 0.78 + 0.237*sl t f 0.43 0.30 + 0.062*sl 0.30 + 0.064*sl 0.28 + 0.067*sl e to y t plh 0.71 0.50 + 0.105*sl 0.50 + 0.104*sl 0.51 + 0.103*sl t phl 0.27 0.19 + 0.038*sl 0.20 + 0.036*sl 0.20 + 0.035*sl t r 1.16 0.70 + 0.232*sl 0.69 + 0.235*sl 0.68 + 0.236*sl t f 0.51 0.39 + 0.060*sl 0.38 + 0.063*sl 0.36 + 0.066*sl f to y t plh 0.77 0.56 + 0.103*sl 0.56 + 0.103*sl 0.57 + 0.102*sl t phl 0.25 0.18 + 0.039*sl 0.18 + 0.036*sl 0.19 + 0.035*sl t r 1.26 0.79 + 0.234*sl 0.78 + 0.235*sl 0.78 + 0.236*sl t f 0.48 0.36 + 0.063*sl 0.35 + 0.065*sl 0.34 + 0.067*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-100 sec asic ao222/ao222d2 three 2-ands into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ao222d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.65 0.60 + 0.023*sl 0.61 + 0.020*sl 0.61 + 0.021*sl t phl 0.39 0.35 + 0.017*sl 0.36 + 0.014*sl 0.37 + 0.012*sl t r 0.19 0.11 + 0.039*sl 0.11 + 0.043*sl 0.10 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.019*sl 0.09 + 0.020*sl b to y t plh 0.71 0.66 + 0.022*sl 0.67 + 0.021*sl 0.67 + 0.020*sl t phl 0.38 0.34 + 0.017*sl 0.35 + 0.014*sl 0.36 + 0.012*sl t r 0.20 0.12 + 0.039*sl 0.11 + 0.043*sl 0.10 + 0.044*sl t f 0.13 0.09 + 0.021*sl 0.09 + 0.019*sl 0.08 + 0.021*sl c to y t plh 0.74 0.70 + 0.023*sl 0.70 + 0.020*sl 0.70 + 0.021*sl t phl 0.45 0.41 + 0.018*sl 0.42 + 0.014*sl 0.43 + 0.012*sl t r 0.19 0.12 + 0.039*sl 0.11 + 0.043*sl 0.10 + 0.044*sl t f 0.13 0.10 + 0.019*sl 0.10 + 0.019*sl 0.09 + 0.020*sl d to y t plh 0.80 0.76 + 0.023*sl 0.76 + 0.021*sl 0.76 + 0.020*sl t phl 0.43 0.40 + 0.018*sl 0.40 + 0.014*sl 0.41 + 0.012*sl t r 0.20 0.12 + 0.039*sl 0.11 + 0.042*sl 0.10 + 0.044*sl t f 0.13 0.09 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl e to y t plh 0.82 0.77 + 0.022*sl 0.78 + 0.021*sl 0.78 + 0.020*sl t phl 0.49 0.45 + 0.018*sl 0.46 + 0.014*sl 0.47 + 0.012*sl t r 0.19 0.11 + 0.041*sl 0.11 + 0.042*sl 0.10 + 0.044*sl t f 0.13 0.10 + 0.020*sl 0.10 + 0.019*sl 0.09 + 0.020*sl f to y t plh 0.88 0.84 + 0.022*sl 0.84 + 0.021*sl 0.84 + 0.020*sl t phl 0.47 0.43 + 0.018*sl 0.44 + 0.014*sl 0.45 + 0.012*sl t r 0.20 0.12 + 0.041*sl 0.11 + 0.042*sl 0.10 + 0.044*sl t f 0.13 0.10 + 0.019*sl 0.10 + 0.019*sl 0.09 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-101 kg80/KGM80 ao222/ao222d2 three 2-ands into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ao222 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.78 0.50 + 0.140*sl 0.50 + 0.139*sl 0.50 + 0.139*sl t phl 0.23 0.15 + 0.044*sl 0.16 + 0.038*sl 0.17 + 0.037*sl t r 1.62 1.00 + 0.311*sl 0.99 + 0.312*sl 1.03 + 0.309*sl t f 0.45 0.32 + 0.066*sl 0.31 + 0.070*sl 0.28 + 0.073*sl b to y t plh 0.88 0.60 + 0.139*sl 0.60 + 0.139*sl 0.60 + 0.139*sl t phl 0.23 0.14 + 0.042*sl 0.15 + 0.038*sl 0.16 + 0.037*sl t r 1.76 1.13 + 0.312*sl 1.13 + 0.312*sl 1.17 + 0.309*sl t f 0.44 0.30 + 0.066*sl 0.29 + 0.072*sl 0.27 + 0.074*sl c to y t plh 1.04 0.76 + 0.143*sl 0.76 + 0.140*sl 0.77 + 0.140*sl t phl 0.31 0.23 + 0.040*sl 0.24 + 0.038*sl 0.25 + 0.037*sl t r 1.68 1.07 + 0.304*sl 1.07 + 0.307*sl 1.06 + 0.308*sl t f 0.52 0.38 + 0.067*sl 0.37 + 0.071*sl 0.35 + 0.073*sl d to y t plh 1.15 0.87 + 0.141*sl 0.87 + 0.140*sl 0.88 + 0.139*sl t phl 0.30 0.22 + 0.041*sl 0.23 + 0.038*sl 0.24 + 0.037*sl t r 1.82 1.21 + 0.305*sl 1.20 + 0.307*sl 1.19 + 0.308*sl t f 0.50 0.36 + 0.069*sl 0.36 + 0.072*sl 0.34 + 0.074*sl e to y t plh 1.13 0.85 + 0.143*sl 0.85 + 0.141*sl 0.86 + 0.139*sl t phl 0.33 0.25 + 0.042*sl 0.26 + 0.040*sl 0.27 + 0.038*sl t r 1.68 1.07 + 0.304*sl 1.07 + 0.307*sl 1.06 + 0.308*sl t f 0.59 0.45 + 0.069*sl 0.44 + 0.071*sl 0.42 + 0.073*sl f to y t plh 1.24 0.95 + 0.141*sl 0.96 + 0.140*sl 0.96 + 0.139*sl t phl 0.32 0.24 + 0.043*sl 0.25 + 0.040*sl 0.26 + 0.038*sl t r 1.82 1.20 + 0.306*sl 1.20 + 0.307*sl 1.19 + 0.308*sl t f 0.57 0.43 + 0.071*sl 0.43 + 0.072*sl 0.41 + 0.074*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-102 sec asic ao222/ao222d2 three 2-ands into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ao222d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.96 0.91 + 0.027*sl 0.91 + 0.025*sl 0.91 + 0.025*sl t phl 0.54 0.50 + 0.020*sl 0.51 + 0.015*sl 0.54 + 0.012*sl t r 0.26 0.16 + 0.049*sl 0.15 + 0.052*sl 0.13 + 0.054*sl t f 0.16 0.12 + 0.022*sl 0.12 + 0.020*sl 0.12 + 0.020*sl b to y t plh 1.07 1.01 + 0.027*sl 1.02 + 0.025*sl 1.02 + 0.025*sl t phl 0.53 0.49 + 0.019*sl 0.50 + 0.015*sl 0.53 + 0.012*sl t r 0.26 0.16 + 0.051*sl 0.16 + 0.052*sl 0.14 + 0.054*sl t f 0.16 0.11 + 0.024*sl 0.13 + 0.020*sl 0.13 + 0.020*sl c to y t plh 1.17 1.12 + 0.027*sl 1.13 + 0.025*sl 1.13 + 0.025*sl t phl 0.61 0.57 + 0.020*sl 0.58 + 0.015*sl 0.61 + 0.012*sl t r 0.26 0.16 + 0.049*sl 0.15 + 0.052*sl 0.13 + 0.054*sl t f 0.16 0.12 + 0.022*sl 0.12 + 0.020*sl 0.12 + 0.021*sl d to y t plh 1.28 1.23 + 0.028*sl 1.23 + 0.025*sl 1.24 + 0.025*sl t phl 0.60 0.56 + 0.020*sl 0.57 + 0.015*sl 0.59 + 0.012*sl t r 0.26 0.16 + 0.051*sl 0.16 + 0.051*sl 0.14 + 0.054*sl t f 0.16 0.12 + 0.023*sl 0.12 + 0.020*sl 0.12 + 0.020*sl e to y t plh 1.32 1.27 + 0.028*sl 1.27 + 0.025*sl 1.27 + 0.025*sl t phl 0.65 0.61 + 0.020*sl 0.63 + 0.015*sl 0.65 + 0.012*sl t r 0.26 0.16 + 0.049*sl 0.15 + 0.052*sl 0.13 + 0.054*sl t f 0.16 0.12 + 0.023*sl 0.12 + 0.020*sl 0.12 + 0.020*sl f to y t plh 1.43 1.38 + 0.027*sl 1.38 + 0.025*sl 1.38 + 0.025*sl t phl 0.64 0.60 + 0.020*sl 0.62 + 0.015*sl 0.64 + 0.012*sl t r 0.26 0.16 + 0.049*sl 0.16 + 0.052*sl 0.14 + 0.054*sl t f 0.16 0.12 + 0.023*sl 0.13 + 0.020*sl 0.13 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-103 kg80/KGM80 ao222a/ao222d2a inverting 2-of-3 majority with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 ao222a ao222d2a ao222a ao222d2a abcabc 1.1 1.4 1.5 1.2 1.4 1.5 3.0 5.0 KGM80 ao222a ao222d2a ao222a ao222d2a abcabc 2.1 2.0 2.0 2.1 2.1 2.0 3.0 5.0 a b y c truth table abcy 11x0 1x10 x110 00x1 0x01 x001
kg80/KGM80 3-104 sec asic ao222a/ao222d2a inverting 2-of-3 majority with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ao222a kg80 ao222d2a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.49 0.31 + 0.090*sl 0.31 + 0.089*sl 0.32 + 0.088*sl t phl 0.23 0.15 + 0.042*sl 0.17 + 0.035*sl 0.17 + 0.035*sl t r 0.90 0.51 + 0.195*sl 0.50 + 0.198*sl 0.49 + 0.199*sl t f 0.40 0.28 + 0.061*sl 0.28 + 0.064*sl 0.26 + 0.066*sl b to y t plh 0.52 0.35 + 0.085*sl 0.34 + 0.085*sl 0.34 + 0.086*sl t phl 0.24 0.16 + 0.041*sl 0.17 + 0.038*sl 0.18 + 0.036*sl t r 0.91 0.52 + 0.196*sl 0.52 + 0.198*sl 0.51 + 0.199*sl t f 0.44 0.31 + 0.063*sl 0.31 + 0.065*sl 0.29 + 0.067*sl c to y t plh 0.58 0.41 + 0.087*sl 0.41 + 0.086*sl 0.41 + 0.086*sl t phl 0.22 0.13 + 0.043*sl 0.15 + 0.038*sl 0.16 + 0.036*sl t r 0.89 0.51 + 0.192*sl 0.50 + 0.196*sl 0.49 + 0.198*sl t f 0.44 0.31 + 0.063*sl 0.30 + 0.065*sl 0.29 + 0.067*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.60 0.56 + 0.022*sl 0.56 + 0.020*sl 0.56 + 0.021*sl t phl 0.43 0.40 + 0.018*sl 0.41 + 0.014*sl 0.42 + 0.012*sl t r 0.19 0.11 + 0.040*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.13 0.09 + 0.021*sl 0.09 + 0.019*sl 0.09 + 0.020*sl b to y t plh 0.63 0.59 + 0.023*sl 0.59 + 0.020*sl 0.59 + 0.020*sl t phl 0.45 0.41 + 0.017*sl 0.42 + 0.014*sl 0.43 + 0.012*sl t r 0.19 0.11 + 0.038*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.13 0.09 + 0.021*sl 0.10 + 0.019*sl 0.09 + 0.020*sl c to y t plh 0.71 0.67 + 0.022*sl 0.67 + 0.021*sl 0.67 + 0.020*sl t phl 0.42 0.39 + 0.018*sl 0.40 + 0.014*sl 0.41 + 0.012*sl t r 0.19 0.11 + 0.040*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.13 0.09 + 0.019*sl 0.09 + 0.019*sl 0.09 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-105 kg80/KGM80 ao222a/ao222d2a inverting 2-of-3 majority with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ao222a KGM80 ao222d2a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.73 0.48 + 0.126*sl 0.49 + 0.121*sl 0.51 + 0.119*sl t phl 0.29 0.20 + 0.044*sl 0.22 + 0.039*sl 0.23 + 0.038*sl t r 1.30 0.78 + 0.256*sl 0.78 + 0.258*sl 0.78 + 0.258*sl t f 0.47 0.34 + 0.068*sl 0.33 + 0.071*sl 0.30 + 0.074*sl b to y t plh 0.81 0.57 + 0.122*sl 0.58 + 0.120*sl 0.59 + 0.118*sl t phl 0.30 0.21 + 0.045*sl 0.22 + 0.041*sl 0.25 + 0.039*sl t r 1.30 0.80 + 0.253*sl 0.79 + 0.257*sl 0.78 + 0.258*sl t f 0.51 0.36 + 0.072*sl 0.36 + 0.073*sl 0.35 + 0.074*sl c to y t plh 0.90 0.66 + 0.118*sl 0.67 + 0.117*sl 0.67 + 0.116*sl t phl 0.28 0.19 + 0.047*sl 0.21 + 0.041*sl 0.23 + 0.039*sl t r 1.28 0.77 + 0.251*sl 0.76 + 0.255*sl 0.75 + 0.257*sl t f 0.51 0.36 + 0.073*sl 0.36 + 0.073*sl 0.36 + 0.074*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.91 0.86 + 0.027*sl 0.86 + 0.025*sl 0.86 + 0.025*sl t phl 0.59 0.55 + 0.020*sl 0.57 + 0.015*sl 0.59 + 0.012*sl t r 0.25 0.15 + 0.050*sl 0.14 + 0.053*sl 0.12 + 0.054*sl t f 0.16 0.11 + 0.023*sl 0.12 + 0.020*sl 0.12 + 0.020*sl b to y t plh 1.03 0.98 + 0.026*sl 0.98 + 0.025*sl 0.98 + 0.025*sl t phl 0.60 0.56 + 0.020*sl 0.57 + 0.015*sl 0.60 + 0.012*sl t r 0.25 0.15 + 0.050*sl 0.14 + 0.052*sl 0.13 + 0.054*sl t f 0.16 0.12 + 0.022*sl 0.12 + 0.020*sl 0.12 + 0.021*sl c to y t plh 1.11 1.06 + 0.026*sl 1.07 + 0.025*sl 1.07 + 0.025*sl t phl 0.58 0.55 + 0.020*sl 0.56 + 0.015*sl 0.58 + 0.012*sl t r 0.25 0.15 + 0.049*sl 0.14 + 0.053*sl 0.12 + 0.054*sl t f 0.16 0.12 + 0.023*sl 0.12 + 0.020*sl 0.12 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-106 sec asic ao33/ao33d2 two 3-ands into 2-nor with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 ao33 ao33d2 ao33 ao33d2 abcdefabcdef 0.5 0.5 0.8 0.5 0.5 0.8 0.5 0.6 0.8 0.5 0.6 0.8 3.0 5.0 KGM80 ao33 ao33d2 ao33 ao33d2 abcdefabcdef 1.0 1.0 1.0 0.9 0.8 0.9 1.0 1.0 1.0 0.9 0.8 0.9 3.0 5.0 y a b c d e f truth table abcdefy 111xxx0 xxx1110 other states 1
sec asic 3-107 kg80/KGM80 ao33/ao33d2 two 3-ands into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ao33 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.43 0.29 + 0.071*sl 0.29 + 0.071*sl 0.29 + 0.071*sl t phl 0.24 0.15 + 0.048*sl 0.15 + 0.045*sl 0.15 + 0.045*sl t r 0.79 0.48 + 0.156*sl 0.47 + 0.161*sl 0.45 + 0.163*sl t f 0.53 0.37 + 0.081*sl 0.35 + 0.089*sl 0.33 + 0.092*sl b to y t plh 0.49 0.35 + 0.071*sl 0.35 + 0.071*sl 0.35 + 0.071*sl t phl 0.25 0.15 + 0.049*sl 0.16 + 0.046*sl 0.17 + 0.045*sl t r 0.88 0.57 + 0.157*sl 0.56 + 0.161*sl 0.54 + 0.163*sl t f 0.53 0.36 + 0.085*sl 0.34 + 0.090*sl 0.32 + 0.093*sl c to y t plh 0.53 0.39 + 0.070*sl 0.39 + 0.071*sl 0.38 + 0.071*sl t phl 0.24 0.15 + 0.049*sl 0.15 + 0.047*sl 0.16 + 0.045*sl t r 0.95 0.64 + 0.155*sl 0.63 + 0.160*sl 0.61 + 0.163*sl t f 0.51 0.34 + 0.085*sl 0.33 + 0.091*sl 0.31 + 0.094*sl d to y t plh 0.49 0.34 + 0.073*sl 0.35 + 0.072*sl 0.35 + 0.072*sl t phl 0.32 0.23 + 0.044*sl 0.23 + 0.045*sl 0.23 + 0.045*sl t r 0.80 0.49 + 0.156*sl 0.48 + 0.160*sl 0.47 + 0.162*sl t f 0.60 0.43 + 0.086*sl 0.42 + 0.089*sl 0.40 + 0.093*sl e to y t plh 0.55 0.40 + 0.072*sl 0.40 + 0.072*sl 0.41 + 0.071*sl t phl 0.33 0.23 + 0.047*sl 0.24 + 0.046*sl 0.24 + 0.045*sl t r 0.89 0.57 + 0.157*sl 0.56 + 0.161*sl 0.55 + 0.163*sl t f 0.59 0.42 + 0.087*sl 0.41 + 0.091*sl 0.39 + 0.093*sl f to y t plh 0.59 0.44 + 0.072*sl 0.44 + 0.072*sl 0.44 + 0.071*sl t phl 0.32 0.23 + 0.047*sl 0.23 + 0.046*sl 0.23 + 0.045*sl t r 0.95 0.64 + 0.158*sl 0.63 + 0.160*sl 0.62 + 0.163*sl t f 0.58 0.41 + 0.089*sl 0.40 + 0.092*sl 0.39 + 0.094*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-108 sec asic ao33/ao33d2 two 3-ands into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ao33d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.57 0.52 + 0.021*sl 0.53 + 0.020*sl 0.52 + 0.021*sl t phl 0.46 0.43 + 0.018*sl 0.44 + 0.014*sl 0.45 + 0.012*sl t r 0.19 0.10 + 0.041*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.14 0.10 + 0.019*sl 0.10 + 0.019*sl 0.10 + 0.020*sl b to y t plh 0.61 0.57 + 0.022*sl 0.57 + 0.020*sl 0.57 + 0.021*sl t phl 0.46 0.43 + 0.018*sl 0.44 + 0.014*sl 0.45 + 0.012*sl t r 0.19 0.11 + 0.038*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.14 0.10 + 0.019*sl 0.10 + 0.019*sl 0.10 + 0.019*sl c to y t plh 0.67 0.62 + 0.022*sl 0.63 + 0.020*sl 0.62 + 0.020*sl t phl 0.47 0.43 + 0.018*sl 0.44 + 0.014*sl 0.45 + 0.012*sl t r 0.19 0.11 + 0.040*sl 0.10 + 0.043*sl 0.10 + 0.044*sl t f 0.14 0.10 + 0.020*sl 0.10 + 0.019*sl 0.10 + 0.019*sl d to y t plh 0.65 0.61 + 0.022*sl 0.61 + 0.020*sl 0.61 + 0.021*sl t phl 0.57 0.54 + 0.018*sl 0.54 + 0.014*sl 0.56 + 0.012*sl t r 0.19 0.11 + 0.039*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.15 0.11 + 0.018*sl 0.11 + 0.019*sl 0.10 + 0.020*sl e to y t plh 0.70 0.65 + 0.023*sl 0.66 + 0.020*sl 0.66 + 0.020*sl t phl 0.57 0.53 + 0.018*sl 0.54 + 0.014*sl 0.56 + 0.012*sl t r 0.19 0.11 + 0.038*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.15 0.11 + 0.021*sl 0.11 + 0.019*sl 0.10 + 0.020*sl f to y t plh 0.75 0.71 + 0.022*sl 0.71 + 0.020*sl 0.71 + 0.020*sl t phl 0.57 0.54 + 0.018*sl 0.54 + 0.014*sl 0.56 + 0.012*sl t r 0.19 0.11 + 0.041*sl 0.11 + 0.043*sl 0.10 + 0.044*sl t f 0.15 0.11 + 0.019*sl 0.11 + 0.019*sl 0.11 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-109 kg80/KGM80 ao33/ao33d2 two 3-ands into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ao33 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.62 0.43 + 0.096*sl 0.43 + 0.095*sl 0.44 + 0.094*sl t phl 0.29 0.19 + 0.054*sl 0.19 + 0.052*sl 0.20 + 0.051*sl t r 1.12 0.72 + 0.204*sl 0.71 + 0.207*sl 0.70 + 0.208*sl t f 0.58 0.39 + 0.097*sl 0.38 + 0.102*sl 0.34 + 0.105*sl b to y t plh 0.72 0.53 + 0.095*sl 0.53 + 0.094*sl 0.53 + 0.094*sl t phl 0.32 0.21 + 0.055*sl 0.22 + 0.052*sl 0.22 + 0.052*sl t r 1.24 0.83 + 0.205*sl 0.83 + 0.208*sl 0.82 + 0.208*sl t f 0.65 0.45 + 0.099*sl 0.44 + 0.103*sl 0.41 + 0.105*sl c to y t plh 0.78 0.59 + 0.096*sl 0.59 + 0.094*sl 0.60 + 0.094*sl t phl 0.32 0.21 + 0.055*sl 0.21 + 0.053*sl 0.22 + 0.052*sl t r 1.34 0.93 + 0.204*sl 0.92 + 0.208*sl 0.91 + 0.208*sl t f 0.64 0.44 + 0.100*sl 0.43 + 0.104*sl 0.41 + 0.105*sl d to y t plh 0.74 0.54 + 0.097*sl 0.55 + 0.095*sl 0.56 + 0.094*sl t phl 0.41 0.30 + 0.054*sl 0.31 + 0.052*sl 0.31 + 0.051*sl t r 1.13 0.73 + 0.202*sl 0.72 + 0.207*sl 0.70 + 0.208*sl t f 0.66 0.46 + 0.100*sl 0.45 + 0.103*sl 0.43 + 0.105*sl e to y t plh 0.84 0.64 + 0.096*sl 0.65 + 0.095*sl 0.66 + 0.094*sl t phl 0.44 0.33 + 0.053*sl 0.33 + 0.052*sl 0.34 + 0.051*sl t r 1.25 0.84 + 0.204*sl 0.83 + 0.207*sl 0.82 + 0.208*sl t f 0.65 0.45 + 0.102*sl 0.44 + 0.104*sl 0.43 + 0.105*sl f to y t plh 0.90 0.71 + 0.097*sl 0.71 + 0.095*sl 0.72 + 0.094*sl t phl 0.44 0.33 + 0.054*sl 0.33 + 0.052*sl 0.34 + 0.051*sl t r 1.35 0.94 + 0.203*sl 0.93 + 0.207*sl 0.92 + 0.208*sl t f 0.64 0.44 + 0.103*sl 0.43 + 0.104*sl 0.42 + 0.105*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-110 sec asic ao33/ao33d2 two 3-ands into 2-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ao33d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.83 0.77 + 0.026*sl 0.78 + 0.025*sl 0.78 + 0.025*sl t phl 0.63 0.59 + 0.020*sl 0.60 + 0.015*sl 0.63 + 0.012*sl t r 0.25 0.15 + 0.050*sl 0.14 + 0.052*sl 0.12 + 0.054*sl t f 0.17 0.13 + 0.023*sl 0.13 + 0.020*sl 0.14 + 0.020*sl b to y t plh 0.90 0.85 + 0.026*sl 0.85 + 0.025*sl 0.85 + 0.025*sl t phl 0.64 0.60 + 0.020*sl 0.61 + 0.015*sl 0.64 + 0.012*sl t r 0.25 0.15 + 0.050*sl 0.14 + 0.052*sl 0.13 + 0.054*sl t f 0.17 0.13 + 0.023*sl 0.13 + 0.020*sl 0.13 + 0.020*sl c to y t plh 1.00 0.94 + 0.027*sl 0.95 + 0.025*sl 0.95 + 0.025*sl t phl 0.65 0.61 + 0.020*sl 0.63 + 0.015*sl 0.66 + 0.012*sl t r 0.25 0.16 + 0.049*sl 0.15 + 0.052*sl 0.13 + 0.054*sl t f 0.17 0.13 + 0.022*sl 0.13 + 0.020*sl 0.13 + 0.020*sl d to y t plh 1.00 0.94 + 0.026*sl 0.95 + 0.025*sl 0.95 + 0.025*sl t phl 0.77 0.73 + 0.020*sl 0.74 + 0.015*sl 0.77 + 0.013*sl t r 0.25 0.15 + 0.050*sl 0.14 + 0.053*sl 0.12 + 0.054*sl t f 0.18 0.13 + 0.024*sl 0.14 + 0.020*sl 0.14 + 0.020*sl e to y t plh 1.08 1.02 + 0.026*sl 1.03 + 0.025*sl 1.03 + 0.025*sl t phl 0.78 0.74 + 0.021*sl 0.76 + 0.015*sl 0.79 + 0.012*sl t r 0.25 0.15 + 0.049*sl 0.14 + 0.052*sl 0.13 + 0.054*sl t f 0.18 0.13 + 0.023*sl 0.14 + 0.020*sl 0.14 + 0.020*sl f to y t plh 1.17 1.12 + 0.027*sl 1.12 + 0.025*sl 1.12 + 0.025*sl t phl 0.80 0.76 + 0.020*sl 0.77 + 0.015*sl 0.80 + 0.012*sl t r 0.25 0.15 + 0.049*sl 0.15 + 0.052*sl 0.13 + 0.054*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.020*sl 0.14 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-111 kg80/KGM80 ao333/ao333d2 three 3-ands into 3-nor with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 ao333 ao333 abcdefgh i 0.5 0.5 0.8 0.5 0.5 0.8 0.5 0.6 0.7 5.0 ao333d2 ao333d2 abcdefgh i 0.5 0.5 0.7 0.5 0.5 0.8 0.5 0.6 0.7 7.0 KGM80 ao333 ao333 abcdefgh i 1.0 1.0 1.0 0.9 0.8 0.9 0.9 0.8 0.9 5.0 ao333d2 ao333d2 abcdefgh i 1.0 1.0 1.0 0.9 0.8 0.9 0.9 0.8 0.9 7.0 d f a c y g i e b h truth table abcdefgh i y 111xxxxxx0 xxx111xxx0 xxxxxx 1110 other states 1
kg80/KGM80 3-112 sec asic ao333/ao333d2 three 3-ands into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ao333 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.74 0.53 + 0.102*sl 0.53 + 0.102*sl 0.53 + 0.102*sl t phl 0.31 0.22 + 0.047*sl 0.22 + 0.046*sl 0.22 + 0.045*sl t r 1.64 1.16 + 0.237*sl 1.15 + 0.240*sl 1.16 + 0.240*sl t f 0.71 0.55 + 0.084*sl 0.53 + 0.090*sl 0.51 + 0.093*sl b to y t plh 0.79 0.59 + 0.102*sl 0.59 + 0.102*sl 0.59 + 0.102*sl t phl 0.31 0.22 + 0.047*sl 0.22 + 0.046*sl 0.22 + 0.046*sl t r 1.73 1.25 + 0.238*sl 1.25 + 0.240*sl 1.25 + 0.239*sl t f 0.71 0.53 + 0.086*sl 0.52 + 0.091*sl 0.50 + 0.094*sl c to y t plh 0.87 0.67 + 0.102*sl 0.67 + 0.102*sl 0.67 + 0.102*sl t phl 0.31 0.22 + 0.048*sl 0.22 + 0.047*sl 0.23 + 0.045*sl t r 1.86 1.38 + 0.238*sl 1.38 + 0.240*sl 1.38 + 0.239*sl t f 0.69 0.52 + 0.088*sl 0.51 + 0.092*sl 0.49 + 0.094*sl d to y t plh 0.94 0.73 + 0.105*sl 0.73 + 0.104*sl 0.74 + 0.103*sl t phl 0.40 0.31 + 0.049*sl 0.31 + 0.047*sl 0.32 + 0.046*sl t r 1.69 1.22 + 0.233*sl 1.22 + 0.235*sl 1.21 + 0.236*sl t f 0.89 0.72 + 0.085*sl 0.71 + 0.089*sl 0.68 + 0.093*sl e to y t plh 1.03 0.82 + 0.104*sl 0.82 + 0.103*sl 0.83 + 0.103*sl t phl 0.42 0.32 + 0.049*sl 0.32 + 0.047*sl 0.33 + 0.046*sl t r 1.81 1.35 + 0.233*sl 1.34 + 0.235*sl 1.34 + 0.236*sl t f 0.87 0.70 + 0.088*sl 0.69 + 0.091*sl 0.68 + 0.093*sl f to y t plh 1.09 0.88 + 0.104*sl 0.88 + 0.103*sl 0.88 + 0.103*sl t phl 0.41 0.31 + 0.049*sl 0.32 + 0.047*sl 0.32 + 0.046*sl t r 1.91 1.44 + 0.234*sl 1.44 + 0.235*sl 1.43 + 0.236*sl t f 0.87 0.69 + 0.089*sl 0.68 + 0.092*sl 0.67 + 0.093*sl g to y t plh 1.02 0.81 + 0.106*sl 0.81 + 0.104*sl 0.82 + 0.103*sl t phl 0.44 0.34 + 0.051*sl 0.34 + 0.049*sl 0.35 + 0.047*sl t r 1.69 1.23 + 0.232*sl 1.22 + 0.235*sl 1.21 + 0.236*sl t f 1.00 0.82 + 0.086*sl 0.82 + 0.090*sl 0.80 + 0.093*sl h to y t plh 1.10 0.89 + 0.104*sl 0.90 + 0.104*sl 0.90 + 0.103*sl t phl 0.45 0.35 + 0.052*sl 0.36 + 0.049*sl 0.37 + 0.047*sl t r 1.82 1.35 + 0.234*sl 1.34 + 0.235*sl 1.34 + 0.236*sl t f 0.99 0.81 + 0.089*sl 0.80 + 0.092*sl 0.79 + 0.094*sl i to y t plh 1.16 0.95 + 0.104*sl 0.96 + 0.103*sl 0.96 + 0.103*sl t phl 0.44 0.34 + 0.051*sl 0.35 + 0.049*sl 0.36 + 0.047*sl t r 1.91 1.44 + 0.233*sl 1.44 + 0.235*sl 1.43 + 0.236*sl t f 0.98 0.80 + 0.090*sl 0.79 + 0.093*sl 0.78 + 0.094*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-113 kg80/KGM80 ao333/ao333d2 three 3-ands into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ao333d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.77 0.73 + 0.022*sl 0.73 + 0.021*sl 0.73 + 0.021*sl t phl 0.52 0.49 + 0.018*sl 0.50 + 0.014*sl 0.51 + 0.012*sl t r 0.20 0.12 + 0.040*sl 0.12 + 0.042*sl 0.11 + 0.044*sl t f 0.15 0.10 + 0.022*sl 0.11 + 0.019*sl 0.11 + 0.019*sl b to y t plh 0.83 0.78 + 0.023*sl 0.79 + 0.021*sl 0.79 + 0.021*sl t phl 0.52 0.49 + 0.018*sl 0.49 + 0.014*sl 0.51 + 0.012*sl t r 0.21 0.13 + 0.040*sl 0.12 + 0.042*sl 0.11 + 0.044*sl t f 0.15 0.11 + 0.018*sl 0.11 + 0.019*sl 0.11 + 0.019*sl c to y t plh 0.90 0.85 + 0.023*sl 0.85 + 0.021*sl 0.86 + 0.021*sl t phl 0.52 0.48 + 0.018*sl 0.49 + 0.014*sl 0.51 + 0.012*sl t r 0.21 0.13 + 0.040*sl 0.13 + 0.042*sl 0.12 + 0.044*sl t f 0.15 0.11 + 0.018*sl 0.11 + 0.019*sl 0.11 + 0.019*sl d to y t plh 0.97 0.92 + 0.023*sl 0.93 + 0.021*sl 0.93 + 0.020*sl t phl 0.64 0.60 + 0.018*sl 0.61 + 0.014*sl 0.63 + 0.012*sl t r 0.20 0.13 + 0.040*sl 0.12 + 0.042*sl 0.11 + 0.044*sl t f 0.15 0.12 + 0.018*sl 0.12 + 0.019*sl 0.12 + 0.019*sl e to y t plh 1.05 1.00 + 0.023*sl 1.01 + 0.021*sl 1.01 + 0.021*sl t phl 0.65 0.61 + 0.018*sl 0.62 + 0.014*sl 0.64 + 0.012*sl t r 0.21 0.13 + 0.040*sl 0.12 + 0.043*sl 0.12 + 0.043*sl t f 0.15 0.12 + 0.020*sl 0.12 + 0.019*sl 0.12 + 0.019*sl f to y t plh 1.10 1.06 + 0.023*sl 1.06 + 0.021*sl 1.06 + 0.021*sl t phl 0.64 0.61 + 0.018*sl 0.62 + 0.015*sl 0.63 + 0.012*sl t r 0.21 0.13 + 0.040*sl 0.13 + 0.042*sl 0.12 + 0.043*sl t f 0.15 0.11 + 0.020*sl 0.12 + 0.019*sl 0.12 + 0.019*sl g to y t plh 1.04 1.00 + 0.022*sl 1.00 + 0.021*sl 1.00 + 0.020*sl t phl 0.69 0.66 + 0.018*sl 0.67 + 0.015*sl 0.68 + 0.012*sl t r 0.21 0.13 + 0.038*sl 0.12 + 0.043*sl 0.11 + 0.044*sl t f 0.16 0.12 + 0.019*sl 0.12 + 0.019*sl 0.12 + 0.019*sl h to y t plh 1.12 1.08 + 0.023*sl 1.08 + 0.021*sl 1.08 + 0.021*sl t phl 0.70 0.67 + 0.019*sl 0.68 + 0.015*sl 0.69 + 0.012*sl t r 0.21 0.13 + 0.041*sl 0.13 + 0.042*sl 0.12 + 0.043*sl t f 0.16 0.12 + 0.020*sl 0.12 + 0.018*sl 0.12 + 0.019*sl i to y t plh 1.18 1.13 + 0.023*sl 1.14 + 0.021*sl 1.14 + 0.021*sl t phl 0.70 0.66 + 0.018*sl 0.67 + 0.015*sl 0.68 + 0.013*sl t r 0.21 0.13 + 0.040*sl 0.13 + 0.042*sl 0.12 + 0.044*sl t f 0.16 0.12 + 0.018*sl 0.12 + 0.019*sl 0.12 + 0.019*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-114 sec asic ao333/ao333d2 three 3-ands into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ao333 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 1.12 0.83 + 0.142*sl 0.84 + 0.140*sl 0.85 + 0.139*sl t phl 0.37 0.26 + 0.054*sl 0.26 + 0.054*sl 0.28 + 0.052*sl t r 2.39 1.76 + 0.314*sl 1.76 + 0.314*sl 1.80 + 0.310*sl t f 0.90 0.70 + 0.098*sl 0.69 + 0.102*sl 0.66 + 0.105*sl b to y t plh 1.22 0.94 + 0.141*sl 0.94 + 0.140*sl 0.95 + 0.139*sl t phl 0.38 0.27 + 0.054*sl 0.27 + 0.054*sl 0.29 + 0.052*sl t r 2.53 1.90 + 0.314*sl 1.90 + 0.314*sl 1.94 + 0.310*sl t f 0.89 0.69 + 0.099*sl 0.68 + 0.103*sl 0.66 + 0.105*sl c to y t plh 1.36 1.08 + 0.141*sl 1.08 + 0.140*sl 1.09 + 0.139*sl t phl 0.39 0.28 + 0.054*sl 0.28 + 0.054*sl 0.30 + 0.052*sl t r 2.72 2.09 + 0.314*sl 2.09 + 0.313*sl 2.13 + 0.310*sl t f 0.88 0.68 + 0.101*sl 0.67 + 0.104*sl 0.66 + 0.105*sl d to y t plh 1.52 1.23 + 0.143*sl 1.24 + 0.141*sl 1.25 + 0.140*sl t phl 0.49 0.38 + 0.058*sl 0.38 + 0.055*sl 0.41 + 0.053*sl t r 2.48 1.87 + 0.304*sl 1.87 + 0.306*sl 1.85 + 0.308*sl t f 1.12 0.92 + 0.098*sl 0.91 + 0.102*sl 0.88 + 0.105*sl e to y t plh 1.67 1.38 + 0.142*sl 1.39 + 0.141*sl 1.40 + 0.140*sl t phl 0.52 0.41 + 0.059*sl 0.42 + 0.055*sl 0.44 + 0.053*sl t r 2.66 2.05 + 0.305*sl 2.05 + 0.307*sl 2.04 + 0.308*sl t f 1.11 0.91 + 0.099*sl 0.91 + 0.103*sl 0.89 + 0.105*sl f to y t plh 1.77 1.49 + 0.142*sl 1.49 + 0.140*sl 1.50 + 0.139*sl t phl 0.52 0.41 + 0.058*sl 0.41 + 0.055*sl 0.44 + 0.053*sl t r 2.80 2.19 + 0.305*sl 2.18 + 0.307*sl 2.17 + 0.308*sl t f 1.11 0.90 + 0.101*sl 0.90 + 0.103*sl 0.88 + 0.105*sl g to y t plh 1.65 1.37 + 0.143*sl 1.37 + 0.141*sl 1.39 + 0.140*sl t phl 0.53 0.41 + 0.062*sl 0.42 + 0.058*sl 0.46 + 0.054*sl t r 2.49 1.88 + 0.303*sl 1.87 + 0.306*sl 1.86 + 0.308*sl t f 1.27 1.07 + 0.099*sl 1.06 + 0.103*sl 1.03 + 0.105*sl h to y t plh 1.80 1.52 + 0.143*sl 1.52 + 0.141*sl 1.53 + 0.140*sl t phl 0.56 0.44 + 0.062*sl 0.45 + 0.058*sl 0.49 + 0.054*sl t r 2.67 2.06 + 0.305*sl 2.05 + 0.307*sl 2.04 + 0.308*sl t f 1.26 1.06 + 0.101*sl 1.05 + 0.103*sl 1.04 + 0.105*sl i to y t plh 1.90 1.62 + 0.142*sl 1.62 + 0.140*sl 1.63 + 0.140*sl t phl 0.56 0.44 + 0.062*sl 0.45 + 0.058*sl 0.49 + 0.054*sl t r 2.80 2.19 + 0.305*sl 2.19 + 0.307*sl 2.17 + 0.308*sl t f 1.25 1.05 + 0.103*sl 1.04 + 0.104*sl 1.04 + 0.105*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-115 kg80/KGM80 ao333/ao333d2 three 3-ands into 3-nor with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ao333d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 1.19 1.13 + 0.028*sl 1.14 + 0.025*sl 1.15 + 0.025*sl t phl 0.70 0.66 + 0.020*sl 0.67 + 0.015*sl 0.70 + 0.012*sl t r 0.27 0.17 + 0.051*sl 0.17 + 0.051*sl 0.15 + 0.053*sl t f 0.18 0.13 + 0.023*sl 0.14 + 0.020*sl 0.14 + 0.020*sl b to y t plh 1.29 1.24 + 0.028*sl 1.25 + 0.025*sl 1.25 + 0.025*sl t phl 0.71 0.67 + 0.021*sl 0.68 + 0.015*sl 0.71 + 0.013*sl t r 0.28 0.18 + 0.049*sl 0.17 + 0.051*sl 0.15 + 0.053*sl t f 0.18 0.13 + 0.023*sl 0.14 + 0.020*sl 0.14 + 0.020*sl c to y t plh 1.41 1.36 + 0.029*sl 1.36 + 0.025*sl 1.37 + 0.025*sl t phl 0.72 0.68 + 0.021*sl 0.69 + 0.015*sl 0.72 + 0.013*sl t r 0.28 0.18 + 0.050*sl 0.18 + 0.051*sl 0.16 + 0.053*sl t f 0.18 0.13 + 0.024*sl 0.14 + 0.020*sl 0.14 + 0.020*sl d to y t plh 1.57 1.52 + 0.028*sl 1.52 + 0.025*sl 1.53 + 0.025*sl t phl 0.86 0.81 + 0.021*sl 0.83 + 0.015*sl 0.86 + 0.013*sl t r 0.27 0.17 + 0.050*sl 0.17 + 0.051*sl 0.14 + 0.053*sl t f 0.19 0.14 + 0.024*sl 0.15 + 0.020*sl 0.15 + 0.020*sl e to y t plh 1.72 1.66 + 0.028*sl 1.67 + 0.025*sl 1.68 + 0.025*sl t phl 0.89 0.84 + 0.021*sl 0.86 + 0.015*sl 0.89 + 0.013*sl t r 0.28 0.18 + 0.050*sl 0.17 + 0.051*sl 0.15 + 0.053*sl t f 0.18 0.14 + 0.025*sl 0.15 + 0.020*sl 0.15 + 0.020*sl f to y t plh 1.82 1.76 + 0.028*sl 1.77 + 0.025*sl 1.78 + 0.025*sl t phl 0.88 0.84 + 0.021*sl 0.86 + 0.015*sl 0.89 + 0.013*sl t r 0.28 0.18 + 0.051*sl 0.18 + 0.051*sl 0.16 + 0.053*sl t f 0.18 0.14 + 0.024*sl 0.15 + 0.020*sl 0.15 + 0.020*sl g to y t plh 1.71 1.65 + 0.028*sl 1.66 + 0.025*sl 1.66 + 0.025*sl t phl 0.92 0.88 + 0.021*sl 0.89 + 0.016*sl 0.92 + 0.013*sl t r 0.27 0.17 + 0.049*sl 0.17 + 0.052*sl 0.15 + 0.053*sl t f 0.19 0.14 + 0.023*sl 0.15 + 0.020*sl 0.15 + 0.020*sl h to y t plh 1.85 1.80 + 0.028*sl 1.81 + 0.025*sl 1.81 + 0.025*sl t phl 0.95 0.90 + 0.021*sl 0.92 + 0.015*sl 0.95 + 0.013*sl t r 0.28 0.18 + 0.050*sl 0.17 + 0.051*sl 0.15 + 0.053*sl t f 0.19 0.15 + 0.021*sl 0.15 + 0.020*sl 0.16 + 0.020*sl i to y t plh 1.95 1.89 + 0.028*sl 1.90 + 0.025*sl 1.91 + 0.025*sl t phl 0.95 0.90 + 0.021*sl 0.92 + 0.015*sl 0.95 + 0.013*sl t r 0.28 0.18 + 0.050*sl 0.18 + 0.051*sl 0.16 + 0.053*sl t f 0.19 0.15 + 0.022*sl 0.15 + 0.020*sl 0.15 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-116 sec asic oa21/oa21d2 2-or into 2-nand with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 oa21 oa21d2 oa21 oa21d2 abcabc 0.5 0.7 0.8 1.1 1.4 1.7 2.0 3.0 KGM80 oa21 oa21d2 oa21 oa21d2 abcabc 1.0 1.0 1.0 2.0 1.9 2.0 2.0 3.0 y c a b truth table abcy 1x10 x110 00x1 xx01
sec asic 3-117 kg80/KGM80 oa21/oa21d2 2-or into 2-nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 oa21 kg80 oa21d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.32 0.19 + 0.068*sl 0.18 + 0.069*sl 0.18 + 0.071*sl t phl 0.16 0.07 + 0.044*sl 0.10 + 0.034*sl 0.10 + 0.034*sl t r 0.56 0.26 + 0.152*sl 0.24 + 0.159*sl 0.22 + 0.163*sl t f 0.30 0.19 + 0.058*sl 0.18 + 0.062*sl 0.15 + 0.065*sl b to y t plh 0.32 0.19 + 0.069*sl 0.18 + 0.070*sl 0.18 + 0.071*sl t phl 0.18 0.10 + 0.040*sl 0.11 + 0.034*sl 0.12 + 0.034*sl t r 0.56 0.26 + 0.152*sl 0.24 + 0.159*sl 0.22 + 0.162*sl t f 0.35 0.23 + 0.059*sl 0.22 + 0.061*sl 0.20 + 0.065*sl c to y t plh 0.29 0.21 + 0.039*sl 0.21 + 0.040*sl 0.20 + 0.041*sl t phl 0.19 0.11 + 0.038*sl 0.12 + 0.035*sl 0.13 + 0.034*sl t r 0.42 0.26 + 0.080*sl 0.25 + 0.085*sl 0.22 + 0.089*sl t f 0.31 0.20 + 0.058*sl 0.18 + 0.064*sl 0.16 + 0.067*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.24 0.17 + 0.036*sl 0.17 + 0.034*sl 0.17 + 0.035*sl t phl 0.11 0.05 + 0.027*sl 0.07 + 0.020*sl 0.09 + 0.017*sl t r 0.38 0.24 + 0.073*sl 0.23 + 0.077*sl 0.21 + 0.080*sl t f 0.23 0.16 + 0.034*sl 0.17 + 0.029*sl 0.16 + 0.031*sl b to y t plh 0.25 0.18 + 0.036*sl 0.18 + 0.035*sl 0.18 + 0.035*sl t phl 0.14 0.09 + 0.024*sl 0.10 + 0.019*sl 0.11 + 0.017*sl t r 0.38 0.24 + 0.073*sl 0.23 + 0.078*sl 0.21 + 0.080*sl t f 0.28 0.23 + 0.029*sl 0.22 + 0.030*sl 0.22 + 0.030*sl c to y t plh 0.24 0.20 + 0.021*sl 0.20 + 0.020*sl 0.20 + 0.020*sl t phl 0.14 0.10 + 0.021*sl 0.11 + 0.019*sl 0.12 + 0.017*sl t r 0.32 0.24 + 0.038*sl 0.23 + 0.041*sl 0.22 + 0.042*sl t f 0.26 0.18 + 0.036*sl 0.20 + 0.028*sl 0.17 + 0.032*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-118 sec asic oa21/oa21d2 2-or into 2-nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 oa21 KGM80 oa21d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.43 0.24 + 0.093*sl 0.24 + 0.094*sl 0.24 + 0.094*sl t phl 0.20 0.11 + 0.046*sl 0.13 + 0.038*sl 0.14 + 0.037*sl t r 0.77 0.37 + 0.201*sl 0.36 + 0.206*sl 0.33 + 0.208*sl t f 0.33 0.20 + 0.067*sl 0.19 + 0.070*sl 0.16 + 0.073*sl b to y t plh 0.45 0.27 + 0.094*sl 0.26 + 0.094*sl 0.27 + 0.094*sl t phl 0.23 0.14 + 0.043*sl 0.16 + 0.037*sl 0.16 + 0.037*sl t r 0.77 0.37 + 0.201*sl 0.36 + 0.206*sl 0.34 + 0.208*sl t f 0.38 0.25 + 0.066*sl 0.24 + 0.070*sl 0.20 + 0.073*sl c to y t plh 0.37 0.27 + 0.049*sl 0.27 + 0.050*sl 0.27 + 0.050*sl t phl 0.25 0.16 + 0.042*sl 0.18 + 0.038*sl 0.18 + 0.037*sl t r 0.53 0.32 + 0.102*sl 0.31 + 0.106*sl 0.28 + 0.109*sl t f 0.35 0.22 + 0.067*sl 0.20 + 0.072*sl 0.19 + 0.074*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.31 0.21 + 0.048*sl 0.22 + 0.047*sl 0.21 + 0.047*sl t phl 0.14 0.08 + 0.027*sl 0.10 + 0.021*sl 0.12 + 0.018*sl t r 0.52 0.32 + 0.099*sl 0.31 + 0.102*sl 0.29 + 0.103*sl t f 0.25 0.17 + 0.037*sl 0.18 + 0.034*sl 0.16 + 0.035*sl b to y t plh 0.35 0.25 + 0.049*sl 0.26 + 0.047*sl 0.26 + 0.047*sl t phl 0.18 0.12 + 0.025*sl 0.14 + 0.020*sl 0.15 + 0.019*sl t r 0.52 0.32 + 0.098*sl 0.31 + 0.102*sl 0.30 + 0.103*sl t f 0.31 0.24 + 0.032*sl 0.24 + 0.034*sl 0.22 + 0.035*sl c to y t plh 0.30 0.25 + 0.025*sl 0.25 + 0.025*sl 0.25 + 0.025*sl t phl 0.19 0.15 + 0.023*sl 0.16 + 0.020*sl 0.17 + 0.019*sl t r 0.39 0.29 + 0.049*sl 0.28 + 0.052*sl 0.27 + 0.053*sl t f 0.27 0.21 + 0.034*sl 0.20 + 0.035*sl 0.19 + 0.036*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-119 kg80/KGM80 oa211/oa211d2 2-or into 3-nand with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 oa211 oa211d2 oa211 oa211d2 abcdabcd 0.5 0.7 0.8 0.9 1.1 1.4 1.7 1.7 2.0 4.0 KGM80 oa211 oa211d2 oa211 oa211d2 abcdabcd 1.0 1.0 1.0 1.0 2.0 1.9 2.0 1.9 2.0 4.0 y c a b d truth table abcdy 1x110 x1110 00xx1 xx0x1 xxx01
kg80/KGM80 3-120 sec asic oa211/oa211d2 2-or into 3-nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 oa211 kg80 oa211d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.33 0.19 + 0.068*sl 0.19 + 0.070*sl 0.18 + 0.071*sl t phl 0.20 0.10 + 0.050*sl 0.12 + 0.044*sl 0.11 + 0.045*sl t r 0.58 0.27 + 0.152*sl 0.26 + 0.159*sl 0.23 + 0.163*sl t f 0.39 0.23 + 0.083*sl 0.22 + 0.088*sl 0.19 + 0.092*sl b to y t plh 0.33 0.19 + 0.070*sl 0.19 + 0.071*sl 0.19 + 0.071*sl t phl 0.23 0.13 + 0.047*sl 0.14 + 0.044*sl 0.13 + 0.045*sl t r 0.58 0.27 + 0.153*sl 0.26 + 0.159*sl 0.24 + 0.162*sl t f 0.45 0.28 + 0.084*sl 0.28 + 0.087*sl 0.24 + 0.092*sl c to y t plh 0.29 0.21 + 0.041*sl 0.21 + 0.041*sl 0.20 + 0.041*sl t phl 0.25 0.16 + 0.047*sl 0.16 + 0.045*sl 0.16 + 0.045*sl t r 0.43 0.27 + 0.078*sl 0.26 + 0.085*sl 0.23 + 0.089*sl t f 0.42 0.26 + 0.084*sl 0.24 + 0.091*sl 0.22 + 0.093*sl d to y t plh 0.31 0.23 + 0.041*sl 0.23 + 0.041*sl 0.23 + 0.041*sl t phl 0.24 0.15 + 0.047*sl 0.15 + 0.045*sl 0.16 + 0.045*sl t r 0.47 0.31 + 0.079*sl 0.30 + 0.084*sl 0.27 + 0.089*sl t f 0.41 0.24 + 0.086*sl 0.23 + 0.092*sl 0.21 + 0.094*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.26 0.19 + 0.035*sl 0.19 + 0.035*sl 0.18 + 0.035*sl t phl 0.15 0.09 + 0.028*sl 0.10 + 0.024*sl 0.12 + 0.022*sl t r 0.43 0.28 + 0.073*sl 0.27 + 0.078*sl 0.26 + 0.080*sl t f 0.31 0.23 + 0.039*sl 0.22 + 0.042*sl 0.21 + 0.045*sl b to y t plh 0.27 0.20 + 0.037*sl 0.20 + 0.035*sl 0.20 + 0.035*sl t phl 0.19 0.14 + 0.026*sl 0.14 + 0.022*sl 0.14 + 0.023*sl t r 0.43 0.28 + 0.074*sl 0.27 + 0.078*sl 0.26 + 0.080*sl t f 0.38 0.31 + 0.039*sl 0.30 + 0.042*sl 0.29 + 0.044*sl c to y t plh 0.25 0.20 + 0.021*sl 0.21 + 0.020*sl 0.20 + 0.020*sl t phl 0.21 0.16 + 0.025*sl 0.17 + 0.023*sl 0.17 + 0.023*sl t r 0.34 0.27 + 0.038*sl 0.26 + 0.041*sl 0.25 + 0.042*sl t f 0.36 0.27 + 0.042*sl 0.27 + 0.044*sl 0.26 + 0.046*sl d to y t plh 0.27 0.23 + 0.020*sl 0.23 + 0.020*sl 0.23 + 0.021*sl t phl 0.21 0.16 + 0.025*sl 0.16 + 0.023*sl 0.17 + 0.023*sl t r 0.39 0.31 + 0.039*sl 0.31 + 0.040*sl 0.30 + 0.042*sl t f 0.34 0.26 + 0.041*sl 0.25 + 0.045*sl 0.24 + 0.046*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-121 kg80/KGM80 oa211/oa211d2 2-or into 3-nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 oa211 KGM80 oa211d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.44 0.25 + 0.094*sl 0.25 + 0.094*sl 0.25 + 0.094*sl t phl 0.25 0.14 + 0.055*sl 0.15 + 0.051*sl 0.15 + 0.051*sl t r 0.80 0.39 + 0.201*sl 0.38 + 0.206*sl 0.36 + 0.208*sl t f 0.46 0.26 + 0.098*sl 0.25 + 0.102*sl 0.22 + 0.105*sl b to y t plh 0.47 0.28 + 0.095*sl 0.28 + 0.094*sl 0.28 + 0.094*sl t phl 0.29 0.18 + 0.053*sl 0.19 + 0.051*sl 0.19 + 0.051*sl t r 0.80 0.39 + 0.201*sl 0.38 + 0.206*sl 0.36 + 0.208*sl t f 0.52 0.33 + 0.096*sl 0.32 + 0.101*sl 0.28 + 0.105*sl c to y t plh 0.37 0.27 + 0.050*sl 0.27 + 0.050*sl 0.28 + 0.050*sl t phl 0.34 0.23 + 0.054*sl 0.23 + 0.052*sl 0.24 + 0.051*sl t r 0.54 0.34 + 0.101*sl 0.32 + 0.106*sl 0.30 + 0.109*sl t f 0.50 0.30 + 0.100*sl 0.30 + 0.103*sl 0.28 + 0.105*sl d to y t plh 0.40 0.30 + 0.051*sl 0.31 + 0.050*sl 0.31 + 0.050*sl t phl 0.33 0.23 + 0.054*sl 0.23 + 0.052*sl 0.24 + 0.051*sl t r 0.59 0.39 + 0.101*sl 0.38 + 0.106*sl 0.35 + 0.109*sl t f 0.50 0.29 + 0.101*sl 0.29 + 0.104*sl 0.27 + 0.105*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.34 0.25 + 0.047*sl 0.25 + 0.047*sl 0.24 + 0.047*sl t phl 0.19 0.13 + 0.030*sl 0.14 + 0.026*sl 0.15 + 0.026*sl t r 0.60 0.40 + 0.100*sl 0.39 + 0.102*sl 0.37 + 0.104*sl t f 0.36 0.26 + 0.048*sl 0.26 + 0.050*sl 0.24 + 0.051*sl b to y t plh 0.39 0.30 + 0.048*sl 0.30 + 0.047*sl 0.30 + 0.047*sl t phl 0.25 0.19 + 0.029*sl 0.19 + 0.026*sl 0.20 + 0.026*sl t r 0.60 0.40 + 0.099*sl 0.39 + 0.102*sl 0.37 + 0.104*sl t f 0.45 0.36 + 0.047*sl 0.35 + 0.049*sl 0.33 + 0.051*sl c to y t plh 0.32 0.27 + 0.025*sl 0.27 + 0.025*sl 0.27 + 0.025*sl t phl 0.29 0.23 + 0.029*sl 0.24 + 0.027*sl 0.24 + 0.026*sl t r 0.43 0.32 + 0.050*sl 0.32 + 0.052*sl 0.30 + 0.053*sl t f 0.43 0.33 + 0.048*sl 0.33 + 0.051*sl 0.31 + 0.052*sl d to y t plh 0.36 0.31 + 0.025*sl 0.31 + 0.025*sl 0.31 + 0.025*sl t phl 0.29 0.24 + 0.028*sl 0.24 + 0.027*sl 0.25 + 0.026*sl t r 0.49 0.39 + 0.050*sl 0.38 + 0.052*sl 0.37 + 0.053*sl t f 0.42 0.32 + 0.050*sl 0.32 + 0.051*sl 0.31 + 0.052*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-122 sec asic oa22/oa22d2 two 2-ors into 2-nand with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 oa22 oa22d2 oa22 oa22d2 abcdabcd 0.5 0.7 0.5 0.7 1.0 1.4 1.1 1.5 2.0 4.0 KGM80 oa22 oa22d2 oa22 oa22d2 abcdabcd 1.0 1.0 1.0 1.0 2.0 1.9 2.0 1.9 2.0 4.0 c d y a b truth table abcdy 00xx1 xx001 1xx10 x1x10 1x1x0 x11x0
sec asic 3-123 kg80/KGM80 oa22/oa22d2 two 2-ors into 2-nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 oa22 kg80 oa22d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.35 0.21 + 0.069*sl 0.20 + 0.071*sl 0.20 + 0.071*sl t phl 0.19 0.11 + 0.041*sl 0.12 + 0.034*sl 0.12 + 0.034*sl t r 0.68 0.37 + 0.152*sl 0.36 + 0.159*sl 0.33 + 0.163*sl t f 0.33 0.21 + 0.061*sl 0.20 + 0.063*sl 0.18 + 0.066*sl b to y t plh 0.35 0.21 + 0.070*sl 0.20 + 0.071*sl 0.21 + 0.071*sl t phl 0.21 0.13 + 0.037*sl 0.14 + 0.034*sl 0.14 + 0.034*sl t r 0.68 0.37 + 0.152*sl 0.36 + 0.159*sl 0.33 + 0.162*sl t f 0.38 0.26 + 0.057*sl 0.25 + 0.061*sl 0.22 + 0.065*sl c to y t plh 0.43 0.29 + 0.068*sl 0.29 + 0.070*sl 0.29 + 0.070*sl t phl 0.19 0.12 + 0.038*sl 0.13 + 0.035*sl 0.13 + 0.034*sl t r 0.72 0.40 + 0.156*sl 0.39 + 0.160*sl 0.38 + 0.163*sl t f 0.31 0.19 + 0.059*sl 0.18 + 0.064*sl 0.16 + 0.067*sl d to y t plh 0.43 0.29 + 0.069*sl 0.29 + 0.070*sl 0.29 + 0.071*sl t phl 0.21 0.14 + 0.037*sl 0.15 + 0.035*sl 0.15 + 0.034*sl t r 0.72 0.41 + 0.156*sl 0.40 + 0.160*sl 0.38 + 0.163*sl t f 0.35 0.24 + 0.054*sl 0.22 + 0.064*sl 0.20 + 0.067*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.26 0.19 + 0.035*sl 0.19 + 0.035*sl 0.19 + 0.036*sl t phl 0.14 0.09 + 0.024*sl 0.10 + 0.019*sl 0.13 + 0.016*sl t r 0.52 0.37 + 0.072*sl 0.36 + 0.077*sl 0.34 + 0.079*sl t f 0.27 0.21 + 0.030*sl 0.21 + 0.030*sl 0.19 + 0.032*sl b to y t plh 0.27 0.19 + 0.038*sl 0.20 + 0.035*sl 0.20 + 0.036*sl t phl 0.17 0.13 + 0.022*sl 0.14 + 0.018*sl 0.14 + 0.017*sl t r 0.52 0.37 + 0.074*sl 0.37 + 0.076*sl 0.34 + 0.080*sl t f 0.31 0.26 + 0.028*sl 0.25 + 0.030*sl 0.25 + 0.031*sl c to y t plh 0.35 0.28 + 0.035*sl 0.28 + 0.034*sl 0.28 + 0.035*sl t phl 0.15 0.11 + 0.022*sl 0.11 + 0.019*sl 0.12 + 0.017*sl t r 0.53 0.37 + 0.077*sl 0.37 + 0.078*sl 0.36 + 0.080*sl t f 0.25 0.19 + 0.033*sl 0.19 + 0.029*sl 0.17 + 0.032*sl d to y t plh 0.36 0.29 + 0.035*sl 0.29 + 0.035*sl 0.28 + 0.035*sl t phl 0.18 0.14 + 0.020*sl 0.14 + 0.018*sl 0.15 + 0.017*sl t r 0.53 0.38 + 0.076*sl 0.37 + 0.079*sl 0.36 + 0.080*sl t f 0.29 0.23 + 0.028*sl 0.23 + 0.031*sl 0.21 + 0.032*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-124 sec asic oa22/oa22d2 two 2-ors into 2-nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 oa22 KGM80 oa22d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.45 0.26 + 0.095*sl 0.26 + 0.095*sl 0.27 + 0.094*sl t phl 0.24 0.15 + 0.043*sl 0.17 + 0.037*sl 0.17 + 0.037*sl t r 0.95 0.55 + 0.199*sl 0.53 + 0.206*sl 0.51 + 0.208*sl t f 0.37 0.24 + 0.066*sl 0.23 + 0.071*sl 0.20 + 0.073*sl b to y t plh 0.48 0.28 + 0.096*sl 0.29 + 0.095*sl 0.29 + 0.095*sl t phl 0.26 0.18 + 0.042*sl 0.19 + 0.038*sl 0.20 + 0.037*sl t r 0.95 0.55 + 0.200*sl 0.53 + 0.206*sl 0.51 + 0.208*sl t f 0.42 0.28 + 0.067*sl 0.27 + 0.070*sl 0.24 + 0.073*sl c to y t plh 0.61 0.42 + 0.094*sl 0.42 + 0.094*sl 0.42 + 0.094*sl t phl 0.26 0.17 + 0.041*sl 0.18 + 0.038*sl 0.19 + 0.037*sl t r 0.99 0.59 + 0.203*sl 0.58 + 0.207*sl 0.57 + 0.208*sl t f 0.35 0.21 + 0.068*sl 0.20 + 0.072*sl 0.19 + 0.074*sl d to y t plh 0.63 0.45 + 0.094*sl 0.45 + 0.094*sl 0.45 + 0.094*sl t phl 0.28 0.20 + 0.041*sl 0.21 + 0.038*sl 0.21 + 0.037*sl t r 1.00 0.59 + 0.204*sl 0.58 + 0.207*sl 0.57 + 0.208*sl t f 0.39 0.26 + 0.068*sl 0.25 + 0.072*sl 0.23 + 0.074*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.32 0.23 + 0.048*sl 0.23 + 0.048*sl 0.23 + 0.048*sl t phl 0.18 0.13 + 0.025*sl 0.14 + 0.020*sl 0.16 + 0.019*sl t r 0.73 0.54 + 0.097*sl 0.53 + 0.101*sl 0.50 + 0.103*sl t f 0.29 0.22 + 0.035*sl 0.23 + 0.034*sl 0.21 + 0.036*sl b to y t plh 0.36 0.27 + 0.049*sl 0.27 + 0.048*sl 0.27 + 0.048*sl t phl 0.22 0.17 + 0.023*sl 0.18 + 0.020*sl 0.19 + 0.019*sl t r 0.73 0.54 + 0.097*sl 0.53 + 0.101*sl 0.51 + 0.103*sl t f 0.35 0.28 + 0.034*sl 0.28 + 0.034*sl 0.27 + 0.035*sl c to y t plh 0.49 0.39 + 0.047*sl 0.39 + 0.047*sl 0.39 + 0.047*sl t phl 0.20 0.16 + 0.023*sl 0.16 + 0.020*sl 0.18 + 0.019*sl t r 0.73 0.53 + 0.101*sl 0.52 + 0.103*sl 0.51 + 0.104*sl t f 0.27 0.21 + 0.033*sl 0.20 + 0.035*sl 0.19 + 0.036*sl d to y t plh 0.53 0.43 + 0.047*sl 0.43 + 0.047*sl 0.44 + 0.047*sl t phl 0.24 0.19 + 0.022*sl 0.20 + 0.020*sl 0.21 + 0.019*sl t r 0.73 0.53 + 0.101*sl 0.53 + 0.102*sl 0.51 + 0.104*sl t f 0.33 0.26 + 0.032*sl 0.25 + 0.035*sl 0.24 + 0.036*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-125 kg80/KGM80 oa22a/oa22d2a 2-or and 2-nand into 2-nand with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 oa22a oa22d2a oa22 oa22d2 abcdabcd 0.6 0.5 0.9 0.9 1.1 1.1 0.9 0.8 3.0 4.0 KGM80 oa22a oa22d2a oa22 oa22d2 abcdabcd 1.0 1.0 1.0 1.0 2.0 1.9 1.0 1.0 3.0 4.0 c d y a b truth table abcdy 00xx1 xx111 1x0x0 1xx00 x10x0 x1x00
kg80/KGM80 3-126 sec asic oa22a/oa22d2a 2-or and 2-nand into 2-nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 oa22a kg80 oa22d2a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.33 0.19 + 0.068*sl 0.19 + 0.070*sl 0.18 + 0.071*sl t phl 0.16 0.08 + 0.043*sl 0.10 + 0.034*sl 0.10 + 0.034*sl t r 0.57 0.27 + 0.152*sl 0.25 + 0.159*sl 0.23 + 0.163*sl t f 0.31 0.19 + 0.058*sl 0.18 + 0.062*sl 0.16 + 0.065*sl b to y t plh 0.33 0.19 + 0.069*sl 0.19 + 0.070*sl 0.18 + 0.071*sl t phl 0.18 0.10 + 0.040*sl 0.12 + 0.034*sl 0.12 + 0.034*sl t r 0.58 0.27 + 0.153*sl 0.25 + 0.159*sl 0.23 + 0.162*sl t f 0.35 0.23 + 0.059*sl 0.23 + 0.061*sl 0.20 + 0.065*sl c to y t plh 0.33 0.25 + 0.042*sl 0.25 + 0.042*sl 0.25 + 0.042*sl t phl 0.35 0.28 + 0.036*sl 0.28 + 0.035*sl 0.28 + 0.034*sl t r 0.40 0.22 + 0.087*sl 0.22 + 0.089*sl 0.21 + 0.090*sl t f 0.28 0.15 + 0.066*sl 0.14 + 0.068*sl 0.14 + 0.069*sl d to y t plh 0.32 0.24 + 0.042*sl 0.24 + 0.042*sl 0.24 + 0.042*sl t phl 0.38 0.31 + 0.036*sl 0.31 + 0.034*sl 0.31 + 0.034*sl t r 0.40 0.23 + 0.086*sl 0.22 + 0.089*sl 0.21 + 0.090*sl t f 0.28 0.15 + 0.065*sl 0.15 + 0.067*sl 0.14 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.24 0.17 + 0.036*sl 0.17 + 0.034*sl 0.17 + 0.035*sl t phl 0.11 0.05 + 0.027*sl 0.07 + 0.021*sl 0.10 + 0.016*sl t r 0.38 0.23 + 0.073*sl 0.22 + 0.077*sl 0.20 + 0.080*sl t f 0.23 0.16 + 0.034*sl 0.17 + 0.029*sl 0.16 + 0.031*sl b to y t plh 0.25 0.17 + 0.037*sl 0.18 + 0.035*sl 0.18 + 0.035*sl t phl 0.13 0.09 + 0.024*sl 0.10 + 0.019*sl 0.11 + 0.017*sl t r 0.38 0.24 + 0.071*sl 0.22 + 0.078*sl 0.21 + 0.080*sl t f 0.28 0.22 + 0.030*sl 0.23 + 0.029*sl 0.22 + 0.030*sl c to y t plh 0.33 0.28 + 0.021*sl 0.28 + 0.021*sl 0.28 + 0.021*sl t phl 0.34 0.30 + 0.019*sl 0.31 + 0.018*sl 0.31 + 0.017*sl t r 0.29 0.22 + 0.036*sl 0.20 + 0.043*sl 0.19 + 0.044*sl t f 0.21 0.15 + 0.031*sl 0.15 + 0.033*sl 0.14 + 0.033*sl d to y t plh 0.31 0.27 + 0.021*sl 0.27 + 0.021*sl 0.27 + 0.021*sl t phl 0.37 0.33 + 0.020*sl 0.34 + 0.018*sl 0.34 + 0.017*sl t r 0.29 0.20 + 0.043*sl 0.20 + 0.043*sl 0.19 + 0.044*sl t f 0.22 0.16 + 0.032*sl 0.16 + 0.032*sl 0.15 + 0.033*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-127 kg80/KGM80 oa22a/oa22d2a 2-or and 2-nand into 2-nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 oa22a KGM80 oa22d2a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.44 0.25 + 0.093*sl 0.25 + 0.094*sl 0.25 + 0.094*sl t phl 0.20 0.11 + 0.045*sl 0.14 + 0.037*sl 0.14 + 0.037*sl t r 0.79 0.39 + 0.201*sl 0.37 + 0.206*sl 0.35 + 0.208*sl t f 0.34 0.21 + 0.066*sl 0.20 + 0.070*sl 0.16 + 0.073*sl b to y t plh 0.46 0.27 + 0.094*sl 0.27 + 0.094*sl 0.27 + 0.094*sl t phl 0.23 0.15 + 0.043*sl 0.16 + 0.037*sl 0.17 + 0.037*sl t r 0.79 0.39 + 0.202*sl 0.38 + 0.206*sl 0.35 + 0.208*sl t f 0.39 0.26 + 0.066*sl 0.24 + 0.070*sl 0.21 + 0.073*sl c to y t plh 0.45 0.35 + 0.051*sl 0.35 + 0.050*sl 0.36 + 0.050*sl t phl 0.45 0.37 + 0.040*sl 0.37 + 0.038*sl 0.38 + 0.037*sl t r 0.52 0.31 + 0.106*sl 0.30 + 0.108*sl 0.29 + 0.109*sl t f 0.34 0.19 + 0.072*sl 0.19 + 0.074*sl 0.18 + 0.075*sl d to y t plh 0.45 0.35 + 0.051*sl 0.35 + 0.050*sl 0.36 + 0.050*sl t phl 0.49 0.41 + 0.040*sl 0.42 + 0.038*sl 0.42 + 0.037*sl t r 0.52 0.31 + 0.106*sl 0.30 + 0.108*sl 0.29 + 0.109*sl t f 0.34 0.20 + 0.071*sl 0.19 + 0.073*sl 0.18 + 0.074*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.31 0.21 + 0.048*sl 0.21 + 0.047*sl 0.21 + 0.047*sl t phl 0.14 0.08 + 0.026*sl 0.10 + 0.021*sl 0.12 + 0.018*sl t r 0.51 0.32 + 0.099*sl 0.31 + 0.102*sl 0.29 + 0.103*sl t f 0.24 0.17 + 0.038*sl 0.18 + 0.034*sl 0.16 + 0.035*sl b to y t plh 0.35 0.25 + 0.049*sl 0.25 + 0.047*sl 0.25 + 0.047*sl t phl 0.17 0.12 + 0.025*sl 0.14 + 0.020*sl 0.15 + 0.019*sl t r 0.52 0.32 + 0.099*sl 0.31 + 0.101*sl 0.29 + 0.103*sl t f 0.31 0.24 + 0.033*sl 0.24 + 0.034*sl 0.22 + 0.035*sl c to y t plh 0.44 0.39 + 0.026*sl 0.39 + 0.025*sl 0.40 + 0.025*sl t phl 0.45 0.41 + 0.022*sl 0.41 + 0.020*sl 0.42 + 0.019*sl t r 0.38 0.27 + 0.051*sl 0.27 + 0.053*sl 0.26 + 0.054*sl t f 0.26 0.20 + 0.034*sl 0.19 + 0.036*sl 0.18 + 0.037*sl d to y t plh 0.44 0.39 + 0.026*sl 0.39 + 0.025*sl 0.39 + 0.025*sl t phl 0.49 0.45 + 0.023*sl 0.46 + 0.020*sl 0.47 + 0.019*sl t r 0.37 0.27 + 0.052*sl 0.27 + 0.053*sl 0.26 + 0.054*sl t f 0.27 0.20 + 0.034*sl 0.20 + 0.036*sl 0.19 + 0.036*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-128 sec asic oa2222/oa2222d2 four 2-ors into 4-nand with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 oa2222 oa2222d2 oa2222 oa2222 d2 abcdefghabcdefgh 0.5 0.6 0.8 0.8 0.6 0.6 0.8 0.8 0.5 0.6 0.8 0.8 0.6 0.6 0.8 0.8 6.0 6.0 KGM80 oa2222 oa2222d2 oa2222 oa2222 d2 abcdefghabcdefgh 1.0 1.0 1.0 1.0 0.7 0.7 0.9 0.9 1.0 1.0 1.0 1.0 0.7 0.7 0.9 0.9 6.0 6.0 e f y c d g h a b truth table abcdefghy 00xxxxxx1 xx00xxxx1 xxxx00xx1 xxxxxx001 other states 0
sec asic 3-129 kg80/KGM80 oa2222/oa2222d2 four 2-ors into 4-nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 oa2222 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.49 0.41 + 0.042*sl 0.41 + 0.041*sl 0.40 + 0.042*sl t phl 0.42 0.36 + 0.033*sl 0.37 + 0.027*sl 0.39 + 0.024*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.089*sl 0.08 + 0.091*sl t f 0.18 0.10 + 0.043*sl 0.10 + 0.041*sl 0.10 + 0.041*sl b to y t plh 0.49 0.40 + 0.041*sl 0.40 + 0.041*sl 0.40 + 0.042*sl t phl 0.45 0.39 + 0.033*sl 0.40 + 0.026*sl 0.42 + 0.024*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.08 + 0.091*sl t f 0.18 0.10 + 0.043*sl 0.11 + 0.040*sl 0.10 + 0.041*sl c to y t plh 0.56 0.48 + 0.042*sl 0.48 + 0.041*sl 0.47 + 0.042*sl t phl 0.43 0.37 + 0.033*sl 0.38 + 0.026*sl 0.40 + 0.024*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.18 0.10 + 0.042*sl 0.10 + 0.041*sl 0.10 + 0.041*sl d to y t plh 0.56 0.47 + 0.042*sl 0.47 + 0.041*sl 0.47 + 0.042*sl t phl 0.41 0.34 + 0.033*sl 0.35 + 0.026*sl 0.37 + 0.024*sl t r 0.27 0.09 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.18 0.10 + 0.042*sl 0.10 + 0.041*sl 0.10 + 0.041*sl e to y t plh 0.51 0.42 + 0.041*sl 0.42 + 0.041*sl 0.42 + 0.042*sl t phl 0.43 0.37 + 0.033*sl 0.38 + 0.026*sl 0.40 + 0.024*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.041*sl 0.10 + 0.041*sl f to y t plh 0.51 0.42 + 0.041*sl 0.42 + 0.041*sl 0.42 + 0.042*sl t phl 0.46 0.40 + 0.033*sl 0.41 + 0.027*sl 0.43 + 0.024*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.18 0.10 + 0.043*sl 0.11 + 0.040*sl 0.10 + 0.041*sl g to y t plh 0.58 0.50 + 0.041*sl 0.50 + 0.041*sl 0.49 + 0.042*sl t phl 0.44 0.38 + 0.032*sl 0.39 + 0.026*sl 0.41 + 0.024*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.19 0.10 + 0.044*sl 0.11 + 0.040*sl 0.10 + 0.041*sl h to y t plh 0.58 0.50 + 0.041*sl 0.50 + 0.041*sl 0.49 + 0.042*sl t phl 0.42 0.35 + 0.033*sl 0.37 + 0.027*sl 0.39 + 0.024*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.041*sl 0.10 + 0.041*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-130 sec asic oa2222/oa2222d2 four 2-ors into 4-nand with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 oa2222d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.48 0.43 + 0.023*sl 0.44 + 0.020*sl 0.44 + 0.021*sl t phl 0.44 0.40 + 0.022*sl 0.41 + 0.017*sl 0.43 + 0.014*sl t r 0.17 0.09 + 0.038*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.17 0.12 + 0.024*sl 0.13 + 0.021*sl 0.13 + 0.020*sl b to y t plh 0.48 0.43 + 0.022*sl 0.44 + 0.021*sl 0.44 + 0.021*sl t phl 0.47 0.42 + 0.022*sl 0.44 + 0.017*sl 0.46 + 0.014*sl t r 0.16 0.09 + 0.037*sl 0.07 + 0.043*sl 0.07 + 0.044*sl t f 0.17 0.12 + 0.024*sl 0.13 + 0.021*sl 0.13 + 0.020*sl c to y t plh 0.55 0.50 + 0.022*sl 0.51 + 0.021*sl 0.51 + 0.021*sl t phl 0.45 0.41 + 0.022*sl 0.42 + 0.017*sl 0.44 + 0.014*sl t r 0.17 0.09 + 0.038*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.16 0.12 + 0.023*sl 0.12 + 0.021*sl 0.13 + 0.020*sl d to y t plh 0.55 0.50 + 0.023*sl 0.51 + 0.020*sl 0.51 + 0.021*sl t phl 0.42 0.38 + 0.022*sl 0.39 + 0.017*sl 0.41 + 0.014*sl t r 0.17 0.09 + 0.038*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.16 0.12 + 0.023*sl 0.12 + 0.021*sl 0.13 + 0.020*sl e to y t plh 0.49 0.45 + 0.022*sl 0.45 + 0.021*sl 0.45 + 0.020*sl t phl 0.45 0.41 + 0.023*sl 0.42 + 0.017*sl 0.44 + 0.014*sl t r 0.17 0.09 + 0.040*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.17 0.12 + 0.024*sl 0.13 + 0.020*sl 0.13 + 0.020*sl f to y t plh 0.49 0.45 + 0.022*sl 0.45 + 0.021*sl 0.45 + 0.021*sl t phl 0.48 0.43 + 0.023*sl 0.45 + 0.017*sl 0.47 + 0.014*sl t r 0.17 0.09 + 0.041*sl 0.08 + 0.042*sl 0.07 + 0.044*sl t f 0.17 0.12 + 0.024*sl 0.13 + 0.020*sl 0.13 + 0.020*sl g to y t plh 0.57 0.52 + 0.022*sl 0.53 + 0.021*sl 0.53 + 0.020*sl t phl 0.46 0.42 + 0.022*sl 0.43 + 0.017*sl 0.45 + 0.014*sl t r 0.17 0.09 + 0.038*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.16 0.12 + 0.024*sl 0.13 + 0.021*sl 0.13 + 0.020*sl h to y t plh 0.57 0.52 + 0.023*sl 0.53 + 0.020*sl 0.53 + 0.020*sl t phl 0.44 0.39 + 0.022*sl 0.41 + 0.017*sl 0.42 + 0.014*sl t r 0.17 0.09 + 0.038*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.17 0.12 + 0.024*sl 0.13 + 0.020*sl 0.13 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-131 kg80/KGM80 oa2222/oa2222d2 four 2-ors into 4-nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 oa2222 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.67 0.57 + 0.050*sl 0.57 + 0.050*sl 0.58 + 0.050*sl t phl 0.59 0.52 + 0.037*sl 0.54 + 0.028*sl 0.58 + 0.024*sl t r 0.34 0.14 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.23 0.13 + 0.047*sl 0.15 + 0.042*sl 0.15 + 0.042*sl b to y t plh 0.70 0.60 + 0.050*sl 0.60 + 0.050*sl 0.60 + 0.050*sl t phl 0.63 0.55 + 0.037*sl 0.58 + 0.028*sl 0.62 + 0.024*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.22 0.13 + 0.046*sl 0.14 + 0.042*sl 0.15 + 0.042*sl c to y t plh 0.84 0.74 + 0.050*sl 0.74 + 0.050*sl 0.74 + 0.050*sl t phl 0.62 0.54 + 0.037*sl 0.57 + 0.028*sl 0.61 + 0.024*sl t r 0.34 0.14 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.23 0.13 + 0.047*sl 0.15 + 0.042*sl 0.15 + 0.042*sl d to y t plh 0.81 0.71 + 0.050*sl 0.71 + 0.050*sl 0.71 + 0.050*sl t phl 0.58 0.51 + 0.037*sl 0.54 + 0.028*sl 0.58 + 0.024*sl t r 0.34 0.14 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.22 0.13 + 0.047*sl 0.14 + 0.042*sl 0.15 + 0.042*sl e to y t plh 0.70 0.60 + 0.050*sl 0.60 + 0.050*sl 0.60 + 0.050*sl t phl 0.63 0.55 + 0.037*sl 0.58 + 0.028*sl 0.62 + 0.024*sl t r 0.35 0.14 + 0.103*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.23 0.13 + 0.047*sl 0.14 + 0.042*sl 0.15 + 0.042*sl f to y t plh 0.72 0.62 + 0.051*sl 0.62 + 0.050*sl 0.62 + 0.050*sl t phl 0.66 0.58 + 0.037*sl 0.61 + 0.028*sl 0.65 + 0.024*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.23 0.13 + 0.047*sl 0.15 + 0.042*sl 0.15 + 0.042*sl g to y t plh 0.86 0.76 + 0.050*sl 0.76 + 0.050*sl 0.76 + 0.050*sl t phl 0.65 0.58 + 0.037*sl 0.61 + 0.028*sl 0.65 + 0.024*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.23 0.13 + 0.047*sl 0.15 + 0.042*sl 0.14 + 0.042*sl h to y t plh 0.83 0.73 + 0.050*sl 0.74 + 0.050*sl 0.74 + 0.050*sl t phl 0.62 0.55 + 0.037*sl 0.57 + 0.028*sl 0.61 + 0.024*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.23 0.13 + 0.046*sl 0.14 + 0.042*sl 0.15 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-132 sec asic oa2222/oa2222d2 four 2-ors into 4-nand with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 oa2222d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.66 0.61 + 0.027*sl 0.61 + 0.025*sl 0.61 + 0.025*sl t phl 0.63 0.58 + 0.026*sl 0.60 + 0.019*sl 0.64 + 0.015*sl t r 0.21 0.11 + 0.050*sl 0.11 + 0.053*sl 0.09 + 0.054*sl t f 0.21 0.15 + 0.027*sl 0.17 + 0.023*sl 0.18 + 0.021*sl b to y t plh 0.69 0.63 + 0.027*sl 0.64 + 0.025*sl 0.64 + 0.025*sl t phl 0.67 0.62 + 0.027*sl 0.64 + 0.019*sl 0.68 + 0.015*sl t r 0.21 0.11 + 0.050*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.21 0.15 + 0.027*sl 0.16 + 0.023*sl 0.18 + 0.021*sl c to y t plh 0.82 0.77 + 0.028*sl 0.78 + 0.025*sl 0.78 + 0.025*sl t phl 0.66 0.61 + 0.026*sl 0.63 + 0.019*sl 0.67 + 0.015*sl t r 0.21 0.11 + 0.050*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.21 0.15 + 0.028*sl 0.17 + 0.022*sl 0.18 + 0.021*sl d to y t plh 0.80 0.74 + 0.028*sl 0.75 + 0.025*sl 0.75 + 0.025*sl t phl 0.63 0.57 + 0.027*sl 0.59 + 0.019*sl 0.64 + 0.015*sl t r 0.21 0.11 + 0.051*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.21 0.15 + 0.028*sl 0.16 + 0.022*sl 0.18 + 0.021*sl e to y t plh 0.68 0.63 + 0.027*sl 0.63 + 0.025*sl 0.64 + 0.025*sl t phl 0.67 0.61 + 0.027*sl 0.64 + 0.019*sl 0.68 + 0.015*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.21 0.15 + 0.027*sl 0.16 + 0.023*sl 0.19 + 0.021*sl f to y t plh 0.71 0.65 + 0.028*sl 0.66 + 0.025*sl 0.66 + 0.025*sl t phl 0.70 0.65 + 0.027*sl 0.67 + 0.019*sl 0.71 + 0.015*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.21 0.15 + 0.028*sl 0.17 + 0.023*sl 0.18 + 0.021*sl g to y t plh 0.84 0.79 + 0.028*sl 0.80 + 0.025*sl 0.80 + 0.025*sl t phl 0.70 0.64 + 0.026*sl 0.66 + 0.019*sl 0.71 + 0.015*sl t r 0.22 0.11 + 0.050*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.21 0.15 + 0.028*sl 0.16 + 0.023*sl 0.19 + 0.021*sl h to y t plh 0.82 0.76 + 0.028*sl 0.77 + 0.025*sl 0.77 + 0.025*sl t phl 0.66 0.61 + 0.026*sl 0.63 + 0.019*sl 0.68 + 0.015*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.21 0.15 + 0.027*sl 0.16 + 0.023*sl 0.19 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-133 kg80/KGM80 dl(1/2/3/4/5/10)d2/dl(1/2/3/4/5/10)d4 (1/2/3/4/5/10)ns delay cell with 2x/4x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 dl1d2 kg80 dl1d4 input load (sl) kg80 dl1d2 dl1d4 dl2d2 dl2d4 dl3d2 dl3d4 dl4d2 dl4d4 dl5d2 dl5d4 dl10d2 dl10d4 aaaaaaaaaaaa 0.8 0.8 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 KGM80 dl1d2 dl1d4 dl2d2 dl2d4 dl3d2 dl3d4 dl4d2 dl4d4 dl5d2 dl5d4 dl10d2 dl10d4 aaaaaaaaaaaa 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 gate count kgd80/KGM80 dl1d2 dl1d4 dl2d2 dl2d4 dl3d2 dl3d4 dl4d2 dl4d4 dl5d2 dl5d4 dl10d2 dl10d4 7.0 7.0 11.0 12.0 15.0 16.0 20.0 20.0 24.0 24.0 43.0 44.0 ay path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.76 0.72 + 0.020*sl 0.73 + 0.016*sl 0.74 + 0.015*sl t phl 0.80 0.74 + 0.026*sl 0.75 + 0.024*sl 0.76 + 0.023*sl t r 0.19 0.14 + 0.025*sl 0.14 + 0.026*sl 0.13 + 0.027*sl t f 0.18 0.11 + 0.038*sl 0.10 + 0.041*sl 0.10 + 0.041*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.81 0.78 + 0.016*sl 0.78 + 0.012*sl 0.79 + 0.011*sl t phl 0.79 0.76 + 0.016*sl 0.77 + 0.014*sl 0.78 + 0.012*sl t r 0.19 0.15 + 0.020*sl 0.15 + 0.019*sl 0.14 + 0.020*sl t f 0.16 0.12 + 0.019*sl 0.12 + 0.019*sl 0.12 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = truth table ay 00 11
kg80/KGM80 3-134 sec asic dl(1/2/3/4/5/10)d2/dl(1/2/3/4/5/10)d4 (1/2/3/4/5/10)ns delay cell with 2x/4x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 dl2d2 kg80 dl2d4 kg80 dl3d2 kg80 dl3d4 kg80 dl4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 1.44 1.40 + 0.021*sl 1.41 + 0.016*sl 1.42 + 0.014*sl t phl 1.52 1.46 + 0.026*sl 1.47 + 0.024*sl 1.47 + 0.023*sl t r 0.20 0.16 + 0.024*sl 0.16 + 0.025*sl 0.14 + 0.027*sl t f 0.19 0.11 + 0.039*sl 0.11 + 0.040*sl 0.09 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 1.50 1.47 + 0.016*sl 1.47 + 0.012*sl 1.48 + 0.011*sl t phl 1.52 1.48 + 0.016*sl 1.49 + 0.014*sl 1.50 + 0.012*sl t r 0.20 0.17 + 0.017*sl 0.17 + 0.018*sl 0.16 + 0.020*sl t f 0.17 0.13 + 0.019*sl 0.13 + 0.019*sl 0.13 + 0.019*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 2.63 2.59 + 0.019*sl 2.60 + 0.015*sl 2.61 + 0.014*sl t phl 2.59 2.53 + 0.026*sl 2.54 + 0.024*sl 2.55 + 0.023*sl t r 0.17 0.13 + 0.023*sl 0.12 + 0.026*sl 0.10 + 0.028*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.040*sl 0.09 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 2.68 2.65 + 0.013*sl 2.66 + 0.010*sl 2.67 + 0.009*sl t phl 2.62 2.59 + 0.016*sl 2.59 + 0.014*sl 2.60 + 0.012*sl t r 0.17 0.14 + 0.013*sl 0.14 + 0.015*sl 0.13 + 0.016*sl t f 0.17 0.13 + 0.019*sl 0.13 + 0.019*sl 0.13 + 0.019*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 3.14 3.09 + 0.025*sl 3.11 + 0.018*sl 3.13 + 0.015*sl t phl 3.28 3.22 + 0.030*sl 3.23 + 0.026*sl 3.24 + 0.024*sl t r 0.27 0.22 + 0.023*sl 0.22 + 0.024*sl 0.20 + 0.027*sl t f 0.25 0.17 + 0.040*sl 0.17 + 0.039*sl 0.17 + 0.040*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-135 kg80/KGM80 dl(1/2/3/4/5/10)d2/dl(1/2/3/4/5/10)d4 (1/2/3/4/5/10)ns delay cell with 2x/4x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 dl4d4 kg80 dl5d2 kg80 dl5d4 kg80 dl10d2 kg80 dl10d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 3.23 3.20 + 0.019*sl 3.21 + 0.015*sl 3.22 + 0.012*sl t phl 3.29 3.25 + 0.020*sl 3.26 + 0.016*sl 3.28 + 0.014*sl t r 0.27 0.23 + 0.016*sl 0.23 + 0.018*sl 0.22 + 0.020*sl t f 0.24 0.19 + 0.023*sl 0.20 + 0.019*sl 0.20 + 0.019*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 3.90 3.86 + 0.021*sl 3.87 + 0.017*sl 3.89 + 0.015*sl t phl 3.88 3.82 + 0.030*sl 3.83 + 0.026*sl 3.85 + 0.024*sl t r 0.21 0.16 + 0.024*sl 0.16 + 0.026*sl 0.15 + 0.027*sl t f 0.24 0.16 + 0.038*sl 0.16 + 0.040*sl 0.15 + 0.040*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 3.97 3.94 + 0.018*sl 3.95 + 0.013*sl 3.96 + 0.011*sl t phl 3.89 3.85 + 0.020*sl 3.86 + 0.016*sl 3.88 + 0.014*sl t r 0.21 0.17 + 0.018*sl 0.17 + 0.019*sl 0.17 + 0.020*sl t f 0.23 0.18 + 0.023*sl 0.19 + 0.019*sl 0.19 + 0.020*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 7.50 7.45 + 0.024*sl 7.47 + 0.017*sl 7.49 + 0.015*sl t phl 7.60 7.55 + 0.027*sl 7.56 + 0.024*sl 7.56 + 0.023*sl t r 0.24 0.20 + 0.023*sl 0.19 + 0.024*sl 0.17 + 0.027*sl t f 0.20 0.13 + 0.037*sl 0.13 + 0.039*sl 0.11 + 0.041*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 7.57 7.54 + 0.017*sl 7.55 + 0.013*sl 7.56 + 0.011*sl t phl 7.61 7.57 + 0.017*sl 7.58 + 0.014*sl 7.59 + 0.012*sl t r 0.24 0.21 + 0.016*sl 0.20 + 0.018*sl 0.19 + 0.019*sl t f 0.19 0.15 + 0.020*sl 0.15 + 0.018*sl 0.15 + 0.019*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-136 sec asic dl(1/2/3/4/5/10)d2/dl(1/2/3/4/5/10)d4 (1/2/3/4/5/10)ns delay cell with 2x/4x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 dl1d2 KGM80 dl1d4 KGM80 dl2d2 KGM80 dl2d4 KGM80 dl3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 1.18 1.13 + 0.024*sl 1.14 + 0.019*sl 1.16 + 0.017*sl t phl 1.09 1.03 + 0.030*sl 1.04 + 0.025*sl 1.06 + 0.023*sl t r 0.24 0.18 + 0.033*sl 0.18 + 0.032*sl 0.16 + 0.034*sl t f 0.22 0.14 + 0.043*sl 0.14 + 0.041*sl 0.13 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 1.25 1.21 + 0.019*sl 1.22 + 0.015*sl 1.24 + 0.013*sl t phl 1.10 1.06 + 0.019*sl 1.07 + 0.015*sl 1.09 + 0.013*sl t r 0.23 0.18 + 0.026*sl 0.18 + 0.025*sl 0.18 + 0.025*sl t f 0.19 0.15 + 0.022*sl 0.15 + 0.021*sl 0.15 + 0.020*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 2.25 2.20 + 0.026*sl 2.22 + 0.019*sl 2.24 + 0.017*sl t phl 2.26 2.20 + 0.031*sl 2.21 + 0.025*sl 2.23 + 0.023*sl t r 0.27 0.21 + 0.030*sl 0.21 + 0.031*sl 0.18 + 0.034*sl t f 0.23 0.14 + 0.043*sl 0.15 + 0.041*sl 0.13 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 2.33 2.29 + 0.019*sl 2.31 + 0.015*sl 2.33 + 0.013*sl t phl 2.27 2.23 + 0.019*sl 2.24 + 0.015*sl 2.27 + 0.013*sl t r 0.27 0.22 + 0.023*sl 0.22 + 0.023*sl 0.21 + 0.025*sl t f 0.21 0.16 + 0.022*sl 0.17 + 0.020*sl 0.17 + 0.020*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 4.15 4.10 + 0.023*sl 4.11 + 0.018*sl 4.13 + 0.017*sl t phl 4.02 3.96 + 0.030*sl 3.97 + 0.025*sl 3.99 + 0.023*sl t r 0.22 0.17 + 0.030*sl 0.16 + 0.032*sl 0.13 + 0.034*sl t f 0.22 0.13 + 0.042*sl 0.13 + 0.041*sl 0.12 + 0.043*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-137 kg80/KGM80 dl(1/2/3/4/5/10)d2/dl(1/2/3/4/5/10)d4 (1/2/3/4/5/10)ns delay cell with 2x/4x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 dl3d4 KGM80 dl4d2 KGM80 dl4d4 KGM80 dl5d2 KGM80 dl5d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 4.22 4.18 + 0.016*sl 4.20 + 0.012*sl 4.22 + 0.010*sl t phl 4.07 4.03 + 0.018*sl 4.04 + 0.015*sl 4.07 + 0.013*sl t r 0.22 0.18 + 0.019*sl 0.18 + 0.018*sl 0.17 + 0.020*sl t f 0.20 0.16 + 0.022*sl 0.16 + 0.021*sl 0.17 + 0.020*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 5.02 4.96 + 0.031*sl 4.98 + 0.022*sl 5.02 + 0.018*sl t phl 5.10 5.03 + 0.035*sl 5.04 + 0.028*sl 5.09 + 0.025*sl t r 0.35 0.28 + 0.032*sl 0.28 + 0.031*sl 0.27 + 0.033*sl t f 0.30 0.21 + 0.045*sl 0.23 + 0.041*sl 0.23 + 0.041*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 5.16 5.11 + 0.025*sl 5.13 + 0.018*sl 5.16 + 0.015*sl t phl 5.14 5.09 + 0.024*sl 5.11 + 0.018*sl 5.14 + 0.015*sl t r 0.34 0.30 + 0.023*sl 0.29 + 0.024*sl 0.29 + 0.024*sl t f 0.29 0.24 + 0.025*sl 0.25 + 0.022*sl 0.27 + 0.020*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 6.23 6.18 + 0.027*sl 6.19 + 0.020*sl 6.23 + 0.017*sl t phl 6.06 5.99 + 0.035*sl 6.01 + 0.028*sl 6.05 + 0.025*sl t r 0.28 0.22 + 0.032*sl 0.22 + 0.032*sl 0.20 + 0.033*sl t f 0.29 0.20 + 0.045*sl 0.21 + 0.042*sl 0.21 + 0.041*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 6.33 6.29 + 0.021*sl 6.30 + 0.016*sl 6.33 + 0.014*sl t phl 6.10 6.05 + 0.024*sl 6.06 + 0.018*sl 6.10 + 0.015*sl t r 0.27 0.22 + 0.024*sl 0.22 + 0.024*sl 0.22 + 0.024*sl t f 0.27 0.22 + 0.025*sl 0.23 + 0.022*sl 0.25 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-138 sec asic dl(1/2/3/4/5/10)d2/dl(1/2/3/4/5/10)d4 (1/2/3/4/5/10)ns delay cell with 2x/4x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 dl10d2 KGM80 dl10d4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 12.10 12.04 + 0.030*sl 12.07 + 0.021*sl 12.10 + 0.017*sl t phl 12.04 11.98 + 0.032*sl 12.00 + 0.025*sl 12.02 + 0.023*sl t r 0.32 0.26 + 0.033*sl 0.26 + 0.031*sl 0.24 + 0.033*sl t f 0.24 0.16 + 0.043*sl 0.16 + 0.040*sl 0.15 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 12.21 12.16 + 0.022*sl 12.18 + 0.016*sl 12.21 + 0.014*sl t phl 12.06 12.02 + 0.019*sl 12.03 + 0.016*sl 12.06 + 0.013*sl t r 0.32 0.27 + 0.024*sl 0.28 + 0.023*sl 0.27 + 0.024*sl t f 0.22 0.18 + 0.022*sl 0.18 + 0.020*sl 0.19 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-139 kg80/KGM80 iv/ivd2/ivd3/ivd4/ivd6/ivd8 inverter with 1x/2x/3x/4x/6x/8x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 iv kg80 ivd2 kg80 ivd3 input load (sl) gate count kg80 iv ivd2 ivd3 ivd4 ivd6 ivd8 iv ivd2 ivd3 ivd4 ivd6 ivd8 aaaaaa 1.0 1.7 2.5 3.4 5.1 6.9 1.0 1.0 2.0 2.0 3.0 4.0 KGM80 iv ivd2 ivd3 ivd4 ivd6 ivd8 iv ivd2 ivd3 ivd4 ivd6 ivd8 aaaaaa 1.0 2.0 2.9 4.0 6.0 8.0 1.0 1.0 2.0 2.0 3.0 4.0 a y path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.24 0.16 + 0.042*sl 0.17 + 0.040*sl 0.16 + 0.041*sl t phl 0.13 0.06 + 0.034*sl 0.08 + 0.025*sl 0.09 + 0.023*sl t r 0.36 0.20 + 0.079*sl 0.18 + 0.085*sl 0.16 + 0.089*sl t f 0.24 0.16 + 0.039*sl 0.17 + 0.036*sl 0.15 + 0.038*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.16 0.11 + 0.027*sl 0.12 + 0.021*sl 0.13 + 0.020*sl t phl 0.06 0.01 + 0.025*sl 0.02 + 0.017*sl 0.05 + 0.013*sl t r 0.21 0.13 + 0.040*sl 0.13 + 0.040*sl 0.11 + 0.042*sl t f 0.17 0.12 + 0.025*sl 0.14 + 0.018*sl 0.14 + 0.018*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.15 0.11 + 0.019*sl 0.12 + 0.015*sl 0.14 + 0.013*sl t phl 0.04 0.01 + 0.017*sl 0.02 + 0.013*sl 0.04 + 0.010*sl t r 0.19 0.14 + 0.028*sl 0.14 + 0.026*sl 0.13 + 0.027*sl t f 0.16 0.12 + 0.018*sl 0.14 + 0.013*sl 0.14 + 0.013*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = truth table ay 01 10
kg80/KGM80 3-140 sec asic iv/ivd2/ivd3/ivd4/ivd6/ivd8 inverter with 1x/2x/3x/4x/6x/8x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ivd4 kg80 ivd6 kg80 ivd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.14 0.11 + 0.015*sl 0.11 + 0.012*sl 0.13 + 0.010*sl t phl 0.03 0.00 + 0.015*sl 0.01 + 0.011*sl 0.03 + 0.009*sl t r 0.17 0.13 + 0.021*sl 0.13 + 0.020*sl 0.14 + 0.019*sl t f 0.15 0.12 + 0.014*sl 0.13 + 0.011*sl 0.14 + 0.009*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.13 0.11 + 0.011*sl 0.11 + 0.009*sl 0.12 + 0.008*sl t phl 0.02 0.00 + 0.011*sl 0.01 + 0.008*sl 0.02 + 0.007*sl t r 0.16 0.13 + 0.014*sl 0.13 + 0.013*sl 0.14 + 0.013*sl t f 0.14 0.12 + 0.008*sl 0.12 + 0.008*sl 0.14 + 0.006*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.12 0.10 + 0.008*sl 0.11 + 0.007*sl 0.12 + 0.006*sl t phl 0.02 -0.00 + 0.009*sl 0.00 + 0.007*sl 0.01 + 0.005*sl t r 0.15 0.13 + 0.011*sl 0.13 + 0.010*sl 0.13 + 0.010*sl t f 0.13 0.12 + 0.007*sl 0.12 + 0.007*sl 0.13 + 0.005*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-141 kg80/KGM80 iv/ivd2/ivd3/ivd4/ivd6/ivd8 inverter with 1x/2x/3x/4x/6x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 iv KGM80 ivd2 KGM80 ivd3 KGM80 ivd4 KGM80 ivd6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.30 0.20 + 0.051*sl 0.20 + 0.049*sl 0.20 + 0.049*sl t phl 0.15 0.09 + 0.033*sl 0.11 + 0.025*sl 0.13 + 0.023*sl t r 0.46 0.25 + 0.102*sl 0.24 + 0.106*sl 0.21 + 0.108*sl t f 0.25 0.17 + 0.040*sl 0.17 + 0.039*sl 0.14 + 0.042*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.18 0.12 + 0.032*sl 0.14 + 0.025*sl 0.14 + 0.025*sl t phl 0.07 0.02 + 0.023*sl 0.04 + 0.016*sl 0.08 + 0.012*sl t r 0.24 0.14 + 0.052*sl 0.14 + 0.050*sl 0.12 + 0.053*sl t f 0.16 0.11 + 0.023*sl 0.12 + 0.020*sl 0.13 + 0.019*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.17 0.12 + 0.022*sl 0.14 + 0.018*sl 0.15 + 0.016*sl t phl 0.06 0.03 + 0.016*sl 0.04 + 0.012*sl 0.07 + 0.009*sl t r 0.22 0.15 + 0.036*sl 0.16 + 0.033*sl 0.14 + 0.035*sl t f 0.15 0.12 + 0.016*sl 0.12 + 0.014*sl 0.14 + 0.013*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.15 0.12 + 0.017*sl 0.12 + 0.014*sl 0.15 + 0.012*sl t phl 0.05 0.02 + 0.014*sl 0.03 + 0.010*sl 0.06 + 0.008*sl t r 0.19 0.14 + 0.027*sl 0.14 + 0.025*sl 0.14 + 0.026*sl t f 0.14 0.11 + 0.013*sl 0.12 + 0.011*sl 0.13 + 0.010*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.14 0.11 + 0.012*sl 0.12 + 0.010*sl 0.14 + 0.009*sl t phl 0.04 0.02 + 0.009*sl 0.03 + 0.007*sl 0.04 + 0.006*sl t r 0.17 0.13 + 0.020*sl 0.14 + 0.017*sl 0.14 + 0.017*sl t f 0.13 0.11 + 0.009*sl 0.11 + 0.008*sl 0.12 + 0.007*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-142 sec asic iv/ivd2/ivd3/ivd4/ivd6/ivd8 inverter with 1x/2x/3x/4x/6x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ivd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.13 0.11 + 0.010*sl 0.12 + 0.008*sl 0.13 + 0.007*sl t phl 0.03 0.02 + 0.008*sl 0.02 + 0.006*sl 0.04 + 0.005*sl t r 0.16 0.13 + 0.015*sl 0.14 + 0.013*sl 0.15 + 0.012*sl t f 0.12 0.11 + 0.007*sl 0.11 + 0.006*sl 0.12 + 0.006*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-143 kg80/KGM80 iva/ivd2a/ivd3a/ivd4a inverter with (2x/4x/6x/8x) p-transistor, (1x/2x/3x/4x) n-transistor logic symbol cell data input load (sl) gate count kg80 iva ivd2a ivd3a ivd4a iva ivd2a ivd3a ivd4a aaaa 1.3 3.3 4.9 6.7 1.0 2.0 3.0 4.0 KGM80 iva ivd2a ivd3a ivd4a iva ivd2a ivd3a ivd4a aaaa 1.6 3.8 5.8 7.8 1.0 2.0 3.0 4.0 a y truth table ay 01 10
kg80/KGM80 3-144 sec asic iva/ivd2a/ivd3a/ivd4a inverter with (2x/4x/6x/8x) p-transistor, (1x/2x/3x/4x) n-transistor switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 iva kg80 ivd2a kg80 ivd3a kg80 ivd4a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.13 0.07 + 0.032*sl 0.09 + 0.023*sl 0.11 + 0.020*sl t phl 0.12 0.06 + 0.034*sl 0.08 + 0.025*sl 0.09 + 0.023*sl t r 0.23 0.15 + 0.039*sl 0.15 + 0.038*sl 0.13 + 0.041*sl t f 0.21 0.13 + 0.037*sl 0.14 + 0.037*sl 0.12 + 0.039*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.10 0.07 + 0.019*sl 0.08 + 0.014*sl 0.10 + 0.011*sl t phl 0.09 0.05 + 0.019*sl 0.06 + 0.015*sl 0.08 + 0.012*sl t r 0.19 0.15 + 0.021*sl 0.15 + 0.019*sl 0.15 + 0.019*sl t f 0.17 0.13 + 0.020*sl 0.14 + 0.018*sl 0.13 + 0.019*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.09 0.07 + 0.013*sl 0.08 + 0.010*sl 0.09 + 0.008*sl t phl 0.08 0.06 + 0.013*sl 0.06 + 0.011*sl 0.08 + 0.009*sl t r 0.18 0.15 + 0.013*sl 0.15 + 0.013*sl 0.16 + 0.012*sl t f 0.16 0.13 + 0.015*sl 0.14 + 0.013*sl 0.15 + 0.011*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.08 0.06 + 0.011*sl 0.07 + 0.009*sl 0.08 + 0.007*sl t phl 0.07 0.05 + 0.011*sl 0.06 + 0.009*sl 0.07 + 0.008*sl t r 0.17 0.15 + 0.011*sl 0.15 + 0.010*sl 0.16 + 0.009*sl t f 0.15 0.13 + 0.012*sl 0.13 + 0.010*sl 0.14 + 0.009*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-145 kg80/KGM80 iva/ivd2a/ivd3a/ivd4a inverter with (2x/4x/6x/8x) p-transistor, (1x/2x/3x/4x) n-transistor switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 iva KGM80 ivd2a KGM80 ivd3a KGM80 ivd4a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.16 0.09 + 0.035*sl 0.11 + 0.026*sl 0.13 + 0.025*sl t phl 0.14 0.07 + 0.034*sl 0.09 + 0.025*sl 0.12 + 0.023*sl t r 0.25 0.15 + 0.049*sl 0.15 + 0.050*sl 0.12 + 0.052*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.039*sl 0.10 + 0.042*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.12 0.08 + 0.020*sl 0.10 + 0.015*sl 0.13 + 0.012*sl t phl 0.10 0.06 + 0.019*sl 0.08 + 0.015*sl 0.11 + 0.012*sl t r 0.20 0.15 + 0.026*sl 0.15 + 0.024*sl 0.14 + 0.025*sl t f 0.16 0.12 + 0.024*sl 0.13 + 0.020*sl 0.13 + 0.020*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.12 0.09 + 0.013*sl 0.10 + 0.011*sl 0.12 + 0.009*sl t phl 0.10 0.07 + 0.013*sl 0.08 + 0.011*sl 0.10 + 0.009*sl t r 0.19 0.16 + 0.017*sl 0.16 + 0.016*sl 0.16 + 0.016*sl t f 0.15 0.12 + 0.017*sl 0.13 + 0.014*sl 0.14 + 0.013*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.10 0.08 + 0.011*sl 0.09 + 0.009*sl 0.10 + 0.007*sl t phl 0.08 0.06 + 0.011*sl 0.07 + 0.009*sl 0.08 + 0.007*sl t r 0.17 0.15 + 0.012*sl 0.15 + 0.013*sl 0.15 + 0.012*sl t f 0.14 0.11 + 0.013*sl 0.12 + 0.011*sl 0.13 + 0.010*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-146 sec asic ivcd(11/13)/ivcd(22/26)/ivcd44 1x iv into (1x/3x) iv/2x iv into (2x/6x) iv/4x iv into 4x iv logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ivcd11 kg80 ivcd13 input load (sl) gate count kg80 ivcd11 ivcd13 ivcd22 ivcd26 ivcd44 ivcd11 ivcd13 ivcd22 ivcd26 ivcd44 aaaaa 0.9 0.8 1.7 1.7 3.4 2.0 2.0 2.0 4.0 4.0 KGM80 ivcd11 ivcd13 ivcd22 ivcd26 ivcd44 ivcd11 ivcd13 ivcd22 ivcd26 ivcd44 aaaaa 1.0 1.0 2.1 2.0 4.0 2.0 2.0 2.0 4.0 4.0 a y yn path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.28 0.20 + 0.039*sl 0.20 + 0.040*sl 0.19 + 0.041*sl t phl 0.15 0.09 + 0.031*sl 0.10 + 0.024*sl 0.12 + 0.022*sl t r 0.44 0.28 + 0.082*sl 0.27 + 0.086*sl 0.25 + 0.089*sl t f 0.27 0.20 + 0.035*sl 0.20 + 0.036*sl 0.17 + 0.040*sl y to yn t plh 0.24 0.16 + 0.041*sl 0.16 + 0.040*sl 0.16 + 0.041*sl t phl 0.13 0.06 + 0.034*sl 0.08 + 0.025*sl 0.10 + 0.023*sl t r 0.36 0.20 + 0.080*sl 0.19 + 0.085*sl 0.16 + 0.089*sl t f 0.24 0.16 + 0.039*sl 0.17 + 0.036*sl 0.15 + 0.038*sl *g 1 sl 2 *g 2 2 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.32 0.25 + 0.038*sl 0.24 + 0.040*sl 0.24 + 0.041*sl t phl 0.17 0.12 + 0.028*sl 0.13 + 0.024*sl 0.14 + 0.022*sl t r 0.54 0.37 + 0.084*sl 0.37 + 0.087*sl 0.35 + 0.089*sl t f 0.33 0.26 + 0.034*sl 0.26 + 0.034*sl 0.22 + 0.040*sl y to yn t plh 0.15 0.11 + 0.019*sl 0.12 + 0.015*sl 0.14 + 0.013*sl t phl 0.04 0.01 + 0.017*sl 0.02 + 0.013*sl 0.04 + 0.010*sl t r 0.19 0.14 + 0.028*sl 0.14 + 0.026*sl 0.13 + 0.027*sl t f 0.16 0.13 + 0.017*sl 0.13 + 0.013*sl 0.14 + 0.013*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = truth table ayyn 101 010
sec asic 3-147 kg80/KGM80 ivcd(11/13)/ivcd(22/26)/ivcd44 1x iv into (1x/3x) iv/2x iv into (2x/6x) iv/4x iv into 4x iv switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ivcd22 kg80 ivcd26 kg80 ivcd44 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.20 0.16 + 0.022*sl 0.16 + 0.020*sl 0.16 + 0.020*sl t phl 0.09 0.05 + 0.019*sl 0.06 + 0.016*sl 0.08 + 0.013*sl t r 0.29 0.21 + 0.040*sl 0.21 + 0.041*sl 0.20 + 0.042*sl t f 0.21 0.17 + 0.018*sl 0.17 + 0.017*sl 0.17 + 0.018*sl y to yn t plh 0.16 0.11 + 0.027*sl 0.12 + 0.021*sl 0.13 + 0.020*sl t phl 0.06 0.01 + 0.025*sl 0.02 + 0.017*sl 0.05 + 0.013*sl t r 0.21 0.13 + 0.040*sl 0.13 + 0.040*sl 0.11 + 0.042*sl t f 0.17 0.12 + 0.024*sl 0.14 + 0.019*sl 0.15 + 0.017*sl *g 1 sl 2 *g 2 2 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.28 0.24 + 0.018*sl 0.24 + 0.019*sl 0.23 + 0.020*sl t phl 0.14 0.11 + 0.015*sl 0.11 + 0.014*sl 0.12 + 0.012*sl t r 0.43 0.35 + 0.041*sl 0.35 + 0.043*sl 0.34 + 0.043*sl t f 0.29 0.26 + 0.015*sl 0.26 + 0.015*sl 0.24 + 0.018*sl y to yn t plh 0.13 0.11 + 0.011*sl 0.11 + 0.009*sl 0.12 + 0.008*sl t phl 0.02 0.00 + 0.011*sl 0.01 + 0.008*sl 0.02 + 0.007*sl t r 0.16 0.13 + 0.014*sl 0.13 + 0.013*sl 0.14 + 0.013*sl t f 0.14 0.12 + 0.008*sl 0.12 + 0.008*sl 0.14 + 0.006*sl *g 1 sl 2 *g 2 2 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.18 0.16 + 0.011*sl 0.16 + 0.011*sl 0.17 + 0.010*sl t phl 0.07 0.05 + 0.011*sl 0.05 + 0.009*sl 0.06 + 0.008*sl t r 0.26 0.21 + 0.024*sl 0.22 + 0.018*sl 0.21 + 0.021*sl t f 0.19 0.17 + 0.009*sl 0.17 + 0.009*sl 0.16 + 0.010*sl y to yn t plh 0.14 0.11 + 0.015*sl 0.11 + 0.012*sl 0.13 + 0.010*sl t phl 0.03 0.00 + 0.014*sl 0.01 + 0.011*sl 0.03 + 0.009*sl t r 0.17 0.13 + 0.021*sl 0.13 + 0.020*sl 0.14 + 0.019*sl t f 0.15 0.12 + 0.015*sl 0.13 + 0.010*sl 0.14 + 0.009*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-148 sec asic ivcd(11/13)/ivcd(22/26)/ivcd44 1x iv into (1x/3x) iv/2x iv into (2x/6x) iv/4x iv into 4x iv switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ivcd11 KGM80 ivcd13 KGM80 ivcd22 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.35 0.25 + 0.049*sl 0.25 + 0.049*sl 0.24 + 0.050*sl t phl 0.18 0.12 + 0.030*sl 0.14 + 0.024*sl 0.15 + 0.023*sl t r 0.58 0.38 + 0.103*sl 0.37 + 0.106*sl 0.34 + 0.108*sl t f 0.28 0.21 + 0.038*sl 0.20 + 0.040*sl 0.18 + 0.042*sl y to yn t plh 0.30 0.20 + 0.051*sl 0.20 + 0.049*sl 0.20 + 0.050*sl t phl 0.15 0.09 + 0.033*sl 0.11 + 0.025*sl 0.13 + 0.023*sl t r 0.46 0.26 + 0.101*sl 0.24 + 0.106*sl 0.22 + 0.108*sl t f 0.25 0.17 + 0.040*sl 0.17 + 0.039*sl 0.14 + 0.042*sl *g 1 sl 3 *g 2 3 sl 11 *g 3 11 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.41 0.31 + 0.048*sl 0.31 + 0.049*sl 0.30 + 0.049*sl t phl 0.20 0.15 + 0.028*sl 0.16 + 0.024*sl 0.17 + 0.023*sl t r 0.70 0.49 + 0.105*sl 0.49 + 0.107*sl 0.47 + 0.109*sl t f 0.34 0.27 + 0.033*sl 0.26 + 0.039*sl 0.23 + 0.042*sl y to yn t plh 0.17 0.12 + 0.022*sl 0.14 + 0.018*sl 0.15 + 0.016*sl t phl 0.06 0.03 + 0.016*sl 0.04 + 0.012*sl 0.07 + 0.009*sl t r 0.22 0.15 + 0.036*sl 0.16 + 0.033*sl 0.14 + 0.035*sl t f 0.15 0.12 + 0.016*sl 0.12 + 0.014*sl 0.14 + 0.013*sl *g 1 sl 3 *g 2 3 sl 11 *g 3 11 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.24 0.18 + 0.027*sl 0.19 + 0.025*sl 0.19 + 0.025*sl t phl 0.11 0.07 + 0.020*sl 0.08 + 0.015*sl 0.11 + 0.012*sl t r 0.36 0.26 + 0.048*sl 0.26 + 0.051*sl 0.24 + 0.053*sl t f 0.20 0.16 + 0.022*sl 0.17 + 0.019*sl 0.16 + 0.020*sl y to yn t plh 0.18 0.12 + 0.032*sl 0.14 + 0.025*sl 0.14 + 0.025*sl t phl 0.07 0.03 + 0.023*sl 0.04 + 0.016*sl 0.09 + 0.012*sl t r 0.24 0.14 + 0.052*sl 0.14 + 0.050*sl 0.12 + 0.053*sl t f 0.16 0.11 + 0.023*sl 0.12 + 0.020*sl 0.13 + 0.019*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-149 kg80/KGM80 ivcd(11/13)/ivcd(22/26)/ivcd44 1x iv into (1x/3x) iv/2x iv into (2x/6x) iv/4x iv into 4x iv switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ivcd26 KGM80 ivcd44 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.34 0.30 + 0.023*sl 0.29 + 0.024*sl 0.29 + 0.025*sl t phl 0.17 0.13 + 0.016*sl 0.14 + 0.013*sl 0.16 + 0.012*sl t r 0.56 0.46 + 0.051*sl 0.46 + 0.053*sl 0.45 + 0.054*sl t f 0.30 0.27 + 0.014*sl 0.26 + 0.018*sl 0.24 + 0.020*sl y to yn t plh 0.14 0.11 + 0.013*sl 0.12 + 0.010*sl 0.14 + 0.009*sl t phl 0.04 0.02 + 0.009*sl 0.03 + 0.007*sl 0.04 + 0.006*sl t r 0.17 0.14 + 0.019*sl 0.14 + 0.017*sl 0.14 + 0.017*sl t f 0.13 0.11 + 0.009*sl 0.11 + 0.008*sl 0.13 + 0.007*sl *g 1 sl 3 *g 2 3 sl 11 *g 3 11 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.21 0.18 + 0.015*sl 0.19 + 0.013*sl 0.19 + 0.012*sl t phl 0.09 0.07 + 0.010*sl 0.07 + 0.008*sl 0.09 + 0.007*sl t r 0.31 0.26 + 0.026*sl 0.26 + 0.025*sl 0.25 + 0.026*sl t f 0.18 0.16 + 0.009*sl 0.16 + 0.010*sl 0.17 + 0.009*sl y to yn t plh 0.15 0.11 + 0.018*sl 0.12 + 0.014*sl 0.15 + 0.012*sl t phl 0.05 0.02 + 0.014*sl 0.03 + 0.010*sl 0.06 + 0.008*sl t r 0.19 0.14 + 0.028*sl 0.15 + 0.025*sl 0.14 + 0.026*sl t f 0.14 0.11 + 0.013*sl 0.11 + 0.011*sl 0.13 + 0.009*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-150 sec asic ivt/ivtd2/ivtd4/ivtd8 inverting tri-state buffer with enable high, 1x/2x/4x/8x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ivt input load (sl) output load (sl) gate count kg80 ivt ivtd2 ivtd4 ivtd8 ivt ivtd2 ivtd4 ivtd8 ivt ivtd2 ivtd4 ivtd8 aeaeaeae y y y y 0.9 1.5 0.8 2.4 0.8 2.1 0.8 2.1 0.8 1.2 6.1 11.6 4.0 5.0 8.0 14.0 KGM80 ivt ivtd2 ivtd4 ivtd8 ivt ivtd2 ivtd4 ivtd8 ivt ivtd2 ivtd4 ivtd8 aeaeaeae y y y y 1.0 1.8 1.0 2.7 0.9 2.5 0.9 4.1 1.1 1.6 7.7 14.5 4.0 5.0 8.0 14.0 a y e path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.38 0.34 + 0.024*sl 0.34 + 0.021*sl 0.34 + 0.021*sl t phl 0.34 0.27 + 0.036*sl 0.27 + 0.035*sl 0.28 + 0.034*sl t r 0.21 0.13 + 0.040*sl 0.12 + 0.043*sl 0.11 + 0.044*sl t f 0.23 0.10 + 0.065*sl 0.10 + 0.068*sl 0.09 + 0.068*sl e to y t plh 0.22 0.17 + 0.024*sl 0.18 + 0.022*sl 0.19 + 0.021*sl t phl 0.14 0.04 + 0.051*sl 0.07 + 0.037*sl 0.09 + 0.035*sl t r 0.22 0.14 + 0.039*sl 0.13 + 0.041*sl 0.12 + 0.044*sl t f 0.28 0.15 + 0.066*sl 0.16 + 0.062*sl 0.13 + 0.066*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.37 0.37 + 0.000*sl 0.37 + 0.000*sl 0.37 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = truth table aey x 0 hi-z 011 110
sec asic 3-151 kg80/KGM80 ivt/ivtd2/ivtd4/ivtd8 inverting tri-state buffer with enable high, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ivtd2 kg80 ivtd4 kg80 ivtd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.43 0.40 + 0.014*sl 0.40 + 0.012*sl 0.41 + 0.011*sl t phl 0.37 0.33 + 0.021*sl 0.34 + 0.018*sl 0.34 + 0.017*sl t r 0.19 0.15 + 0.018*sl 0.15 + 0.020*sl 0.14 + 0.021*sl t f 0.19 0.13 + 0.029*sl 0.13 + 0.030*sl 0.11 + 0.033*sl e to y t plh 0.27 0.24 + 0.014*sl 0.24 + 0.013*sl 0.25 + 0.011*sl t phl 0.07 -0.00 + 0.034*sl 0.02 + 0.024*sl 0.06 + 0.018*sl t r 0.20 0.16 + 0.022*sl 0.17 + 0.018*sl 0.16 + 0.020*sl t f 0.20 0.13 + 0.039*sl 0.14 + 0.031*sl 0.15 + 0.031*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.53 0.53 + 0.000*sl 0.53 + 0.000*sl 0.53 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.44 0.43 + 0.009*sl 0.43 + 0.008*sl 0.44 + 0.007*sl t phl 0.44 0.42 + 0.011*sl 0.42 + 0.010*sl 0.43 + 0.009*sl t r 0.19 0.17 + 0.011*sl 0.17 + 0.009*sl 0.17 + 0.010*sl t f 0.23 0.20 + 0.013*sl 0.20 + 0.014*sl 0.19 + 0.016*sl e to y t plh 0.31 0.29 + 0.007*sl 0.29 + 0.008*sl 0.30 + 0.007*sl t phl 0.05 0.02 + 0.015*sl 0.02 + 0.012*sl 0.04 + 0.011*sl t r 0.20 0.18 + 0.010*sl 0.18 + 0.009*sl 0.18 + 0.009*sl t f 0.21 0.19 + 0.013*sl 0.18 + 0.014*sl 0.18 + 0.015*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.59 0.59 + 0.000*sl 0.59 + 0.000*sl 0.59 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.59 0.58 + 0.006*sl 0.58 + 0.005*sl 0.58 + 0.005*sl t phl 0.65 0.63 + 0.008*sl 0.64 + 0.006*sl 0.64 + 0.006*sl t r 0.28 0.27 + 0.004*sl 0.27 + 0.004*sl 0.27 + 0.005*sl t f 0.34 0.33 + 0.006*sl 0.33 + 0.006*sl 0.33 + 0.006*sl e to y t plh 0.45 0.44 + 0.006*sl 0.44 + 0.005*sl 0.45 + 0.005*sl t phl 0.02 0.01 + 0.008*sl 0.01 + 0.007*sl 0.02 + 0.006*sl t r 0.28 0.27 + 0.004*sl 0.27 + 0.005*sl 0.28 + 0.004*sl t f 0.19 0.17 + 0.007*sl 0.17 + 0.007*sl 0.17 + 0.008*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.90 0.90 + 0.000*sl 0.90 + 0.000*sl 0.90 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-152 sec asic ivt/ivtd2/ivtd4/ivtd8 inverting tri-state buffer with enable high, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ivt KGM80 ivtd2 KGM80 ivtd4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.51 0.45 + 0.028*sl 0.46 + 0.026*sl 0.46 + 0.025*sl t phl 0.47 0.39 + 0.041*sl 0.40 + 0.038*sl 0.40 + 0.037*sl t r 0.27 0.17 + 0.050*sl 0.16 + 0.053*sl 0.15 + 0.054*sl t f 0.28 0.14 + 0.071*sl 0.13 + 0.073*sl 0.12 + 0.074*sl e to y t plh 0.31 0.26 + 0.029*sl 0.26 + 0.026*sl 0.27 + 0.025*sl t phl 0.19 0.09 + 0.049*sl 0.12 + 0.038*sl 0.13 + 0.037*sl t r 0.27 0.18 + 0.048*sl 0.17 + 0.052*sl 0.15 + 0.054*sl t f 0.32 0.18 + 0.070*sl 0.17 + 0.070*sl 0.14 + 0.073*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.48 0.48 + 0.000*sl 0.48 + 0.000*sl 0.48 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.56 0.53 + 0.018*sl 0.54 + 0.015*sl 0.55 + 0.013*sl t phl 0.52 0.47 + 0.024*sl 0.48 + 0.021*sl 0.50 + 0.019*sl t r 0.23 0.19 + 0.025*sl 0.18 + 0.025*sl 0.18 + 0.026*sl t f 0.22 0.16 + 0.034*sl 0.15 + 0.035*sl 0.14 + 0.036*sl e to y t plh 0.38 0.34 + 0.018*sl 0.35 + 0.015*sl 0.37 + 0.013*sl t phl 0.11 0.05 + 0.031*sl 0.07 + 0.022*sl 0.11 + 0.019*sl t r 0.24 0.19 + 0.024*sl 0.19 + 0.025*sl 0.18 + 0.026*sl t f 0.22 0.14 + 0.041*sl 0.16 + 0.034*sl 0.15 + 0.035*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.70 0.70 + 0.000*sl 0.70 + 0.000*sl 0.70 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.59 0.57 + 0.011*sl 0.57 + 0.009*sl 0.58 + 0.008*sl t phl 0.62 0.60 + 0.013*sl 0.60 + 0.012*sl 0.62 + 0.011*sl t r 0.23 0.20 + 0.013*sl 0.21 + 0.013*sl 0.20 + 0.013*sl t f 0.28 0.24 + 0.019*sl 0.24 + 0.018*sl 0.25 + 0.017*sl e to y t plh 0.43 0.41 + 0.011*sl 0.41 + 0.009*sl 0.43 + 0.008*sl t phl 0.10 0.07 + 0.015*sl 0.07 + 0.012*sl 0.09 + 0.011*sl t r 0.23 0.21 + 0.012*sl 0.21 + 0.013*sl 0.21 + 0.013*sl t f 0.26 0.25 + 0.006*sl 0.23 + 0.015*sl 0.21 + 0.017*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.80 0.80 + -0.001*sl 0.80 + 0.000*sl 0.79 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-153 kg80/KGM80 ivt/ivtd2/ivtd4/ivtd8 inverting tri-state buffer with enable high, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ivtd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.77 0.76 + 0.007*sl 0.76 + 0.006*sl 0.77 + 0.005*sl t phl 0.90 0.89 + 0.008*sl 0.89 + 0.007*sl 0.90 + 0.006*sl t r 0.31 0.30 + 0.006*sl 0.30 + 0.006*sl 0.30 + 0.006*sl t f 0.39 0.38 + 0.008*sl 0.37 + 0.009*sl 0.38 + 0.008*sl e to y t plh 0.62 0.61 + 0.006*sl 0.61 + 0.006*sl 0.62 + 0.005*sl t phl 0.07 0.06 + 0.008*sl 0.06 + 0.007*sl 0.07 + 0.006*sl t r 0.31 0.30 + 0.006*sl 0.30 + 0.006*sl 0.30 + 0.006*sl t f 0.23 0.22 + 0.005*sl 0.21 + 0.008*sl 0.20 + 0.009*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 1.22 1.22 + 0.000*sl 1.22 + 0.000*sl 1.22 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-154 sec asic ivtn/ivtnd2/ivtnd4/ivtnd8 inverting tri-state buffer with enable low, 1x/2x/4x/8x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ivtn input load (sl) output load (sl) kg80 ivtn ivtnd2 ivtnd4 ivtnd8 ivtn ivtnd2 ivtnd4 ivtnd8 aenaenaenaenyyyy 0.9 0.9 0.9 0.9 0.8 0.8 0.8 0.8 1.3 1.1 6.1 11.6 KGM80 ivtn ivtnd2 ivtnd4 ivtnd8 ivtn ivtnd2 ivtnd4 ivtnd8 aenaenaenaenyyyy 1.0 1.0 1.0 1.0 0.9 0.9 0.9 0.9 1.7 1.5 7.7 14.5 kg80/KGM80 gate count ivtn ivtnd2 ivtnd4 ivtnd8 4.0 5.0 8.0 14.0 ay en path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.40 0.35 + 0.023*sl 0.36 + 0.021*sl 0.36 + 0.021*sl t phl 0.35 0.28 + 0.036*sl 0.29 + 0.035*sl 0.29 + 0.034*sl t r 0.22 0.14 + 0.041*sl 0.13 + 0.043*sl 0.13 + 0.044*sl t f 0.27 0.14 + 0.065*sl 0.13 + 0.068*sl 0.13 + 0.069*sl en to y t plh 0.42 0.38 + 0.023*sl 0.38 + 0.021*sl 0.38 + 0.021*sl t phl 0.35 0.27 + 0.040*sl 0.28 + 0.036*sl 0.28 + 0.035*sl t r 0.22 0.14 + 0.041*sl 0.14 + 0.043*sl 0.13 + 0.044*sl t f 0.28 0.15 + 0.065*sl 0.15 + 0.067*sl 0.14 + 0.068*sl t plz 0.16 0.16 + 0.000*sl 0.16 + 0.000*sl 0.16 + 0.000*sl t phz 0.37 0.37 + 0.000*sl 0.37 + 0.000*sl 0.37 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = truth table aeny x 1 hi-z 001 100
sec asic 3-155 kg80/KGM80 ivtn/ivtnd2/ivtnd4/ivtnd8 inverting tri-state buffer with enable low, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ivtnd2 kg80 ivtnd4 kg80 ivtnd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.44 0.41 + 0.015*sl 0.41 + 0.013*sl 0.42 + 0.011*sl t phl 0.39 0.35 + 0.021*sl 0.35 + 0.018*sl 0.36 + 0.018*sl t r 0.19 0.15 + 0.019*sl 0.15 + 0.020*sl 0.15 + 0.020*sl t f 0.20 0.14 + 0.028*sl 0.13 + 0.031*sl 0.12 + 0.032*sl en to y t plh 0.50 0.47 + 0.015*sl 0.48 + 0.013*sl 0.49 + 0.011*sl t phl 0.30 0.25 + 0.027*sl 0.26 + 0.021*sl 0.28 + 0.018*sl t r 0.20 0.16 + 0.019*sl 0.16 + 0.020*sl 0.16 + 0.020*sl t f 0.17 0.10 + 0.036*sl 0.11 + 0.032*sl 0.10 + 0.033*sl t plz 0.21 0.20 + 0.001*sl 0.21 + 0.000*sl 0.20 + 0.000*sl t phz 0.59 0.58 + 0.001*sl 0.59 + 0.000*sl 0.59 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.44 0.43 + 0.009*sl 0.43 + 0.008*sl 0.44 + 0.007*sl t phl 0.44 0.42 + 0.011*sl 0.42 + 0.010*sl 0.43 + 0.009*sl t r 0.19 0.17 + 0.011*sl 0.17 + 0.009*sl 0.17 + 0.010*sl t f 0.23 0.20 + 0.014*sl 0.20 + 0.015*sl 0.19 + 0.016*sl en to y t plh 0.52 0.51 + 0.009*sl 0.51 + 0.008*sl 0.52 + 0.007*sl t phl 0.29 0.26 + 0.013*sl 0.26 + 0.011*sl 0.27 + 0.010*sl t r 0.19 0.17 + 0.012*sl 0.18 + 0.009*sl 0.17 + 0.010*sl t f 0.18 0.16 + 0.011*sl 0.15 + 0.015*sl 0.14 + 0.016*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.64 0.64 + 0.000*sl 0.64 + 0.000*sl 0.64 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.59 0.58 + 0.006*sl 0.58 + 0.005*sl 0.58 + 0.005*sl t phl 0.65 0.63 + 0.008*sl 0.64 + 0.006*sl 0.64 + 0.006*sl t r 0.28 0.27 + 0.004*sl 0.27 + 0.004*sl 0.27 + 0.005*sl t f 0.34 0.33 + 0.007*sl 0.33 + 0.006*sl 0.33 + 0.006*sl en to y t plh 0.73 0.72 + 0.006*sl 0.72 + 0.005*sl 0.73 + 0.005*sl t phl 0.31 0.29 + 0.008*sl 0.29 + 0.007*sl 0.30 + 0.006*sl t r 0.29 0.28 + 0.005*sl 0.28 + 0.004*sl 0.28 + 0.004*sl t f 0.18 0.16 + 0.007*sl 0.16 + 0.008*sl 0.16 + 0.008*sl t plz 0.27 0.27 + 0.000*sl 0.28 + -0.001*sl 0.27 + 0.001*sl t phz 1.01 1.01 + 0.000*sl 1.01 + 0.000*sl 1.01 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-156 sec asic ivtn/ivtnd2/ivtnd4/ivtnd8 inverting tri-state buffer with enable low, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ivtn KGM80 ivtnd2 KGM80 ivtnd4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.53 0.47 + 0.027*sl 0.48 + 0.025*sl 0.48 + 0.025*sl t phl 0.48 0.40 + 0.041*sl 0.41 + 0.038*sl 0.42 + 0.037*sl t r 0.29 0.19 + 0.051*sl 0.18 + 0.053*sl 0.17 + 0.054*sl t f 0.33 0.19 + 0.071*sl 0.18 + 0.073*sl 0.17 + 0.074*sl en to y t plh 0.57 0.51 + 0.028*sl 0.52 + 0.026*sl 0.53 + 0.025*sl t phl 0.44 0.36 + 0.043*sl 0.37 + 0.038*sl 0.38 + 0.037*sl t r 0.29 0.19 + 0.051*sl 0.18 + 0.053*sl 0.17 + 0.054*sl t f 0.34 0.20 + 0.070*sl 0.20 + 0.072*sl 0.18 + 0.074*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.52 0.52 + 0.000*sl 0.52 + 0.000*sl 0.51 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.58 0.55 + 0.018*sl 0.55 + 0.015*sl 0.57 + 0.013*sl t phl 0.54 0.49 + 0.025*sl 0.50 + 0.021*sl 0.52 + 0.019*sl t r 0.24 0.19 + 0.024*sl 0.19 + 0.025*sl 0.18 + 0.026*sl t f 0.23 0.16 + 0.035*sl 0.16 + 0.035*sl 0.15 + 0.036*sl en to y t plh 0.68 0.64 + 0.018*sl 0.65 + 0.015*sl 0.67 + 0.013*sl t phl 0.40 0.35 + 0.029*sl 0.37 + 0.022*sl 0.40 + 0.019*sl t r 0.24 0.19 + 0.026*sl 0.20 + 0.025*sl 0.19 + 0.025*sl t f 0.21 0.14 + 0.039*sl 0.15 + 0.036*sl 0.14 + 0.036*sl t plz 0.25 0.25 + 0.000*sl 0.25 + 0.000*sl 0.25 + 0.000*sl t phz 0.81 0.81 + 0.001*sl 0.81 + 0.000*sl 0.81 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.59 0.57 + 0.011*sl 0.57 + 0.009*sl 0.58 + 0.008*sl t phl 0.62 0.60 + 0.013*sl 0.60 + 0.012*sl 0.62 + 0.011*sl t r 0.23 0.20 + 0.013*sl 0.21 + 0.013*sl 0.20 + 0.013*sl t f 0.28 0.24 + 0.019*sl 0.24 + 0.018*sl 0.24 + 0.018*sl en to y t plh 0.70 0.68 + 0.011*sl 0.69 + 0.009*sl 0.70 + 0.008*sl t phl 0.37 0.35 + 0.014*sl 0.35 + 0.012*sl 0.37 + 0.011*sl t r 0.24 0.21 + 0.013*sl 0.21 + 0.013*sl 0.21 + 0.013*sl t f 0.26 0.25 + 0.004*sl 0.22 + 0.016*sl 0.20 + 0.018*sl t plz 0.24 0.24 + 0.000*sl 0.24 + 0.000*sl 0.25 + 0.000*sl t phz 0.89 0.89 + -0.001*sl 0.89 + 0.000*sl 0.89 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-157 kg80/KGM80 ivtn/ivtnd2/ivtnd4/ivtnd8 inverting tri-state buffer with enable low, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ivtnd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.77 0.76 + 0.007*sl 0.76 + 0.006*sl 0.77 + 0.005*sl t phl 0.90 0.89 + 0.008*sl 0.89 + 0.007*sl 0.90 + 0.007*sl t r 0.31 0.30 + 0.006*sl 0.30 + 0.006*sl 0.30 + 0.006*sl t f 0.39 0.38 + 0.008*sl 0.37 + 0.009*sl 0.38 + 0.008*sl en to y t plh 0.99 0.97 + 0.007*sl 0.98 + 0.006*sl 0.99 + 0.005*sl t phl 0.42 0.40 + 0.008*sl 0.40 + 0.007*sl 0.41 + 0.006*sl t r 0.32 0.31 + 0.006*sl 0.31 + 0.006*sl 0.31 + 0.006*sl t f 0.25 0.24 + 0.005*sl 0.23 + 0.009*sl 0.22 + 0.009*sl t plz 0.33 0.33 + -0.001*sl 0.33 + 0.000*sl 0.33 + 0.000*sl t phz 1.39 1.39 + -0.001*sl 1.39 + 0.000*sl 1.39 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-158 sec asic nid/nid2/nid3/nid4/nid6/nid8 non-inverting buffer with 1x/2x/3x/4x/6x/8x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nid kg80 nid2 kg80 nid3 input load (sl) gate count kg80 nid nid2 nid3 nid4 nid6 nid8 nid nid2 nid3 nid4 nid6 nid8 aaaaaa 0.9 0.9 0.8 1.7 1.7 1.7 1.0 2.0 2.0 3.0 4.0 5.0 KGM80 nid nid2 nid3 nid4 nid6 nid8 nid nid2 nid3 nid4 nid6 nid8 aaaaaa 1.0 1.0 1.0 1.9 1.9 2.0 1.0 2.0 2.0 3.0 4.0 5.0 ay path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.21 0.13 + 0.041*sl 0.12 + 0.041*sl 0.12 + 0.042*sl t phl 0.26 0.21 + 0.028*sl 0.22 + 0.024*sl 0.22 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.08 + 0.091*sl t f 0.16 0.09 + 0.035*sl 0.07 + 0.041*sl 0.06 + 0.042*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.20 0.16 + 0.021*sl 0.16 + 0.020*sl 0.16 + 0.021*sl t phl 0.27 0.24 + 0.016*sl 0.25 + 0.014*sl 0.26 + 0.012*sl t r 0.18 0.10 + 0.043*sl 0.10 + 0.043*sl 0.08 + 0.045*sl t f 0.13 0.09 + 0.019*sl 0.09 + 0.019*sl 0.09 + 0.020*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.22 0.19 + 0.015*sl 0.19 + 0.014*sl 0.20 + 0.014*sl t phl 0.29 0.27 + 0.013*sl 0.27 + 0.011*sl 0.28 + 0.009*sl t r 0.16 0.11 + 0.023*sl 0.10 + 0.029*sl 0.10 + 0.029*sl t f 0.14 0.11 + 0.013*sl 0.11 + 0.013*sl 0.11 + 0.013*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = truth table ay 00 11
sec asic 3-159 kg80/KGM80 nid/nid2/nid3/nid4/nid6/nid8 non-inverting buffer with 1x/2x/3x/4x/6x/8x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nid4 kg80 nid6 kg80 nid8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.18 0.16 + 0.011*sl 0.16 + 0.010*sl 0.16 + 0.010*sl t phl 0.25 0.24 + 0.009*sl 0.24 + 0.008*sl 0.25 + 0.007*sl t r 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.09 + 0.022*sl t f 0.11 0.09 + 0.010*sl 0.09 + 0.010*sl 0.09 + 0.010*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.20 0.19 + 0.008*sl 0.19 + 0.007*sl 0.19 + 0.007*sl t phl 0.28 0.27 + 0.007*sl 0.27 + 0.006*sl 0.28 + 0.005*sl t r 0.14 0.10 + 0.016*sl 0.11 + 0.012*sl 0.10 + 0.015*sl t f 0.12 0.11 + 0.008*sl 0.11 + 0.006*sl 0.11 + 0.007*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.23 0.22 + 0.006*sl 0.22 + 0.006*sl 0.23 + 0.005*sl t phl 0.31 0.30 + 0.006*sl 0.30 + 0.005*sl 0.31 + 0.004*sl t r 0.14 0.11 + 0.011*sl 0.11 + 0.013*sl 0.15 + 0.007*sl t f 0.14 0.12 + 0.006*sl 0.13 + 0.005*sl 0.13 + 0.005*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-160 sec asic nid/nid2/nid3/nid4/nid6/nid8 non-inverting buffer with 1x/2x/3x/4x/6x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nid KGM80 nid2 KGM80 nid3 KGM80 nid4 KGM80 nid6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.28 0.18 + 0.051*sl 0.18 + 0.050*sl 0.18 + 0.050*sl t phl 0.32 0.26 + 0.030*sl 0.27 + 0.024*sl 0.29 + 0.023*sl t r 0.34 0.13 + 0.106*sl 0.12 + 0.109*sl 0.11 + 0.109*sl t f 0.18 0.11 + 0.036*sl 0.10 + 0.041*sl 0.08 + 0.043*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.27 0.21 + 0.026*sl 0.22 + 0.025*sl 0.22 + 0.025*sl t phl 0.35 0.31 + 0.019*sl 0.32 + 0.014*sl 0.34 + 0.012*sl t r 0.24 0.13 + 0.051*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.16 0.11 + 0.022*sl 0.12 + 0.020*sl 0.12 + 0.021*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.29 0.25 + 0.018*sl 0.25 + 0.017*sl 0.26 + 0.017*sl t phl 0.38 0.35 + 0.015*sl 0.36 + 0.011*sl 0.38 + 0.009*sl t r 0.21 0.14 + 0.033*sl 0.14 + 0.035*sl 0.13 + 0.036*sl t f 0.16 0.13 + 0.016*sl 0.14 + 0.014*sl 0.14 + 0.014*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.24 0.21 + 0.014*sl 0.21 + 0.013*sl 0.22 + 0.012*sl t phl 0.32 0.30 + 0.011*sl 0.31 + 0.008*sl 0.33 + 0.007*sl t r 0.18 0.13 + 0.026*sl 0.13 + 0.026*sl 0.13 + 0.027*sl t f 0.13 0.11 + 0.012*sl 0.11 + 0.011*sl 0.12 + 0.010*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.27 0.25 + 0.010*sl 0.25 + 0.009*sl 0.25 + 0.008*sl t phl 0.37 0.35 + 0.008*sl 0.35 + 0.007*sl 0.37 + 0.005*sl t r 0.18 0.14 + 0.017*sl 0.14 + 0.017*sl 0.14 + 0.017*sl t f 0.15 0.13 + 0.008*sl 0.13 + 0.008*sl 0.14 + 0.007*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-161 kg80/KGM80 nid/nid2/nid3/nid4/nid6/nid8 non-inverting buffer with 1x/2x/3x/4x/6x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nid8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.30 0.28 + 0.008*sl 0.28 + 0.007*sl 0.29 + 0.006*sl t phl 0.41 0.40 + 0.007*sl 0.40 + 0.006*sl 0.41 + 0.005*sl t r 0.18 0.15 + 0.013*sl 0.15 + 0.012*sl 0.15 + 0.013*sl t f 0.17 0.15 + 0.007*sl 0.15 + 0.006*sl 0.16 + 0.006*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-162 sec asic nit/nitd2/nitd4/nitd8 non-inverting tri-state buffer with enable high, 1x/2x/4x/8x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nit input load (sl) output load (sl) gate count kg80 nit nitd2 nitd4 nitd8 nit nitd2 nitd4 nitd 8 nit nitd2 nitd4 nitd8 aeaeaeae yyyy 0.9 1.6 0.9 2.4 0.9 2.2 0.9 3.6 0.8 1.3 5.8 11.6 3.0 4.0 7.0 13.0 KGM80 nit nitd2 nitd4 nitd8 nit nitd2 nitd4 nitd 8 nit nitd2 nitd4 nitd8 aeaeaeae yyyy 1.0 1.9 1.1 2.8 0.9 2.5 0.9 4.1 1.1 1.8 7.2 14.3 3.0 4.0 7.0 13.0 ay e path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.24 0.19 + 0.024*sl 0.19 + 0.022*sl 0.20 + 0.021*sl t phl 0.34 0.27 + 0.036*sl 0.28 + 0.034*sl 0.28 + 0.034*sl t r 0.22 0.14 + 0.038*sl 0.13 + 0.042*sl 0.12 + 0.044*sl t f 0.23 0.11 + 0.063*sl 0.10 + 0.067*sl 0.09 + 0.068*sl e to y t plh 0.22 0.17 + 0.023*sl 0.18 + 0.022*sl 0.18 + 0.021*sl t phl 0.14 0.04 + 0.051*sl 0.07 + 0.037*sl 0.09 + 0.035*sl t r 0.21 0.14 + 0.037*sl 0.13 + 0.042*sl 0.12 + 0.043*sl t f 0.28 0.15 + 0.066*sl 0.16 + 0.062*sl 0.13 + 0.066*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.36 0.36 + 0.000*sl 0.36 + 0.000*sl 0.36 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = truth table aey x 0 hi-z 010 111
sec asic 3-163 kg80/KGM80 nit/nitd2/nitd4/nitd8 non-inverting tri-state buffer with enable high, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nitd2 kg80 nitd4 kg80 nitd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.30 0.27 + 0.015*sl 0.28 + 0.013*sl 0.29 + 0.011*sl t phl 0.39 0.35 + 0.020*sl 0.36 + 0.018*sl 0.36 + 0.017*sl t r 0.21 0.17 + 0.015*sl 0.17 + 0.018*sl 0.15 + 0.020*sl t f 0.20 0.15 + 0.027*sl 0.14 + 0.030*sl 0.13 + 0.032*sl e to y t plh 0.28 0.25 + 0.015*sl 0.25 + 0.013*sl 0.27 + 0.011*sl t phl 0.07 0.01 + 0.033*sl 0.03 + 0.024*sl 0.07 + 0.018*sl t r 0.21 0.18 + 0.018*sl 0.18 + 0.018*sl 0.16 + 0.020*sl t f 0.21 0.13 + 0.038*sl 0.15 + 0.031*sl 0.15 + 0.031*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.55 0.55 + 0.000*sl 0.55 + 0.000*sl 0.55 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.32 0.29 + 0.011*sl 0.30 + 0.008*sl 0.31 + 0.007*sl t phl 0.45 0.42 + 0.012*sl 0.43 + 0.010*sl 0.44 + 0.009*sl t r 0.19 0.18 + 0.005*sl 0.17 + 0.009*sl 0.17 + 0.010*sl t f 0.22 0.19 + 0.014*sl 0.19 + 0.015*sl 0.19 + 0.015*sl e to y t plh 0.31 0.28 + 0.011*sl 0.29 + 0.008*sl 0.30 + 0.007*sl t phl 0.04 0.01 + 0.015*sl 0.02 + 0.013*sl 0.03 + 0.011*sl t r 0.19 0.18 + 0.008*sl 0.17 + 0.009*sl 0.17 + 0.010*sl t f 0.20 0.18 + 0.013*sl 0.17 + 0.014*sl 0.17 + 0.015*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.58 0.58 + 0.000*sl 0.58 + 0.000*sl 0.58 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.46 0.45 + 0.006*sl 0.45 + 0.005*sl 0.45 + 0.005*sl t phl 0.66 0.64 + 0.007*sl 0.64 + 0.006*sl 0.65 + 0.006*sl t r 0.28 0.27 + 0.004*sl 0.27 + 0.005*sl 0.27 + 0.005*sl t f 0.34 0.33 + 0.006*sl 0.33 + 0.006*sl 0.33 + 0.007*sl e to y t plh 0.45 0.44 + 0.006*sl 0.44 + 0.005*sl 0.44 + 0.005*sl t phl 0.02 0.01 + 0.008*sl 0.01 + 0.007*sl 0.02 + 0.006*sl t r 0.28 0.27 + 0.004*sl 0.27 + 0.004*sl 0.27 + 0.005*sl t f 0.19 0.17 + 0.007*sl 0.17 + 0.007*sl 0.17 + 0.008*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.90 0.90 + 0.000*sl 0.90 + 0.000*sl 0.90 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-164 sec asic nit/nitd2/nitd4/nitd8 non-inverting tri-state buffer with enable high, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nit KGM80 nitd2 KGM80 nitd4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.32 0.26 + 0.029*sl 0.27 + 0.026*sl 0.28 + 0.025*sl t phl 0.44 0.36 + 0.041*sl 0.37 + 0.038*sl 0.38 + 0.037*sl t r 0.27 0.17 + 0.049*sl 0.16 + 0.052*sl 0.15 + 0.054*sl t f 0.28 0.14 + 0.070*sl 0.13 + 0.073*sl 0.12 + 0.074*sl e to y t plh 0.31 0.25 + 0.028*sl 0.26 + 0.026*sl 0.27 + 0.025*sl t phl 0.19 0.09 + 0.050*sl 0.12 + 0.038*sl 0.13 + 0.037*sl t r 0.27 0.17 + 0.049*sl 0.16 + 0.052*sl 0.14 + 0.054*sl t f 0.31 0.17 + 0.070*sl 0.17 + 0.070*sl 0.14 + 0.073*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.47 0.47 + 0.000*sl 0.47 + 0.000*sl 0.47 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.40 0.37 + 0.018*sl 0.38 + 0.015*sl 0.39 + 0.013*sl t phl 0.52 0.47 + 0.024*sl 0.48 + 0.021*sl 0.49 + 0.019*sl t r 0.24 0.19 + 0.025*sl 0.19 + 0.025*sl 0.18 + 0.025*sl t f 0.24 0.17 + 0.034*sl 0.17 + 0.034*sl 0.16 + 0.036*sl e to y t plh 0.39 0.35 + 0.018*sl 0.36 + 0.015*sl 0.38 + 0.013*sl t phl 0.12 0.06 + 0.031*sl 0.08 + 0.022*sl 0.12 + 0.019*sl t r 0.24 0.19 + 0.026*sl 0.19 + 0.025*sl 0.18 + 0.026*sl t f 0.23 0.15 + 0.039*sl 0.17 + 0.034*sl 0.15 + 0.035*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.74 0.74 + 0.000*sl 0.74 + 0.000*sl 0.74 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.42 0.40 + 0.011*sl 0.41 + 0.009*sl 0.42 + 0.008*sl t phl 0.60 0.57 + 0.014*sl 0.58 + 0.012*sl 0.59 + 0.010*sl t r 0.22 0.20 + 0.013*sl 0.20 + 0.013*sl 0.20 + 0.013*sl t f 0.27 0.23 + 0.017*sl 0.23 + 0.018*sl 0.24 + 0.017*sl e to y t plh 0.42 0.40 + 0.010*sl 0.41 + 0.009*sl 0.42 + 0.008*sl t phl 0.09 0.06 + 0.015*sl 0.06 + 0.012*sl 0.08 + 0.010*sl t r 0.22 0.20 + 0.012*sl 0.20 + 0.013*sl 0.20 + 0.013*sl t f 0.25 0.23 + 0.008*sl 0.21 + 0.016*sl 0.20 + 0.017*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.79 0.79 + -0.001*sl 0.79 + 0.000*sl 0.79 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-165 kg80/KGM80 nit/nitd2/nitd4/nitd8 non-inverting tri-state buffer with enable high, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nitd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.61 0.60 + 0.007*sl 0.60 + 0.006*sl 0.61 + 0.005*sl t phl 0.89 0.87 + 0.008*sl 0.88 + 0.007*sl 0.89 + 0.006*sl t r 0.31 0.30 + 0.007*sl 0.30 + 0.006*sl 0.30 + 0.006*sl t f 0.39 0.38 + 0.008*sl 0.37 + 0.009*sl 0.38 + 0.008*sl e to y t plh 0.61 0.60 + 0.006*sl 0.60 + 0.006*sl 0.61 + 0.005*sl t phl 0.07 0.06 + 0.008*sl 0.06 + 0.007*sl 0.07 + 0.006*sl t r 0.31 0.30 + 0.006*sl 0.30 + 0.006*sl 0.30 + 0.006*sl t f 0.23 0.22 + 0.004*sl 0.21 + 0.008*sl 0.20 + 0.009*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 1.22 1.23 + -0.001*sl 1.22 + 0.000*sl 1.22 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-166 sec asic nitn/nitnd2/nitnd4/nitnd8 non-inverting tri-state buffer with enable low, 1x/2x/4x/8x drive logic symbol cell data switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nitn input load (sl) output load (sl) kg80 nitn nitnd2 nitnd4 nitnd8 nitn nitnd2 nitnd4 nitnd 8 aenaenaenaenyyyy 0.9 0.9 0.9 0.9 0.8 0.8 0.9 0.8 0.9 1.1 5.8 11.6 KGM80 nitn nitnd2 nitnd4 nitnd8 nitn nitnd2 nitnd4 nitnd 8 aenaenaenaenyyyy 0.7 1.0 0.7 1.0 0.6 0.9 0.6 0.9 1.2 1.5 7.2 14.3 kg80/KGM80 gate count nitn nitnd2 nitnd4 nitnd8 3.0 5.0 8.0 14.0 ay en path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.24 0.19 + 0.023*sl 0.19 + 0.022*sl 0.20 + 0.021*sl t phl 0.35 0.27 + 0.036*sl 0.28 + 0.035*sl 0.28 + 0.034*sl t r 0.22 0.14 + 0.037*sl 0.13 + 0.042*sl 0.12 + 0.044*sl t f 0.24 0.11 + 0.064*sl 0.10 + 0.067*sl 0.09 + 0.069*sl en to y t plh 0.41 0.36 + 0.024*sl 0.36 + 0.021*sl 0.37 + 0.021*sl t phl 0.33 0.25 + 0.041*sl 0.26 + 0.036*sl 0.27 + 0.034*sl t r 0.21 0.13 + 0.041*sl 0.12 + 0.042*sl 0.11 + 0.044*sl t f 0.25 0.11 + 0.065*sl 0.11 + 0.067*sl 0.10 + 0.068*sl t plz 0.16 0.16 + 0.000*sl 0.16 + 0.000*sl 0.16 + 0.000*sl t phz 0.36 0.36 + 0.001*sl 0.36 + 0.000*sl 0.37 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = truth table aeny x 1 hi-z 000 101
sec asic 3-167 kg80/KGM80 nitn/nitnd2/nitnd4/nitnd8 non-inverting tri-state buffer with enable low, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 nitnd2 kg80 nitnd4 kg80 nitnd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.30 0.27 + 0.015*sl 0.27 + 0.013*sl 0.29 + 0.011*sl t phl 0.39 0.35 + 0.021*sl 0.36 + 0.018*sl 0.36 + 0.017*sl t r 0.20 0.17 + 0.016*sl 0.16 + 0.019*sl 0.15 + 0.020*sl t f 0.20 0.14 + 0.028*sl 0.14 + 0.030*sl 0.12 + 0.032*sl en to y t plh 0.50 0.47 + 0.016*sl 0.48 + 0.013*sl 0.48 + 0.011*sl t phl 0.30 0.24 + 0.027*sl 0.26 + 0.021*sl 0.28 + 0.018*sl t r 0.20 0.17 + 0.017*sl 0.16 + 0.020*sl 0.16 + 0.020*sl t f 0.17 0.10 + 0.036*sl 0.11 + 0.033*sl 0.10 + 0.033*sl t plz 0.20 0.20 + 0.001*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.59 0.59 + 0.001*sl 0.59 + 0.000*sl 0.59 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.32 0.29 + 0.011*sl 0.30 + 0.008*sl 0.31 + 0.007*sl t phl 0.45 0.42 + 0.012*sl 0.43 + 0.010*sl 0.44 + 0.009*sl t r 0.19 0.18 + 0.005*sl 0.17 + 0.009*sl 0.17 + 0.010*sl t f 0.22 0.19 + 0.014*sl 0.19 + 0.014*sl 0.19 + 0.015*sl en to y t plh 0.52 0.50 + 0.009*sl 0.50 + 0.008*sl 0.51 + 0.007*sl t phl 0.28 0.25 + 0.012*sl 0.26 + 0.011*sl 0.26 + 0.010*sl t r 0.19 0.17 + 0.010*sl 0.17 + 0.009*sl 0.16 + 0.010*sl t f 0.17 0.16 + 0.005*sl 0.14 + 0.015*sl 0.14 + 0.016*sl t plz 0.20 0.20 + -0.001*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.64 0.64 + -0.001*sl 0.64 + 0.000*sl 0.64 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.46 0.45 + 0.006*sl 0.45 + 0.005*sl 0.45 + 0.005*sl t phl 0.66 0.64 + 0.007*sl 0.64 + 0.006*sl 0.65 + 0.006*sl t r 0.28 0.27 + 0.004*sl 0.27 + 0.004*sl 0.27 + 0.005*sl t f 0.34 0.33 + 0.006*sl 0.33 + 0.006*sl 0.33 + 0.007*sl en to y t plh 0.73 0.72 + 0.006*sl 0.72 + 0.005*sl 0.72 + 0.005*sl t phl 0.31 0.29 + 0.008*sl 0.29 + 0.007*sl 0.30 + 0.006*sl t r 0.28 0.28 + 0.004*sl 0.28 + 0.004*sl 0.27 + 0.005*sl t f 0.18 0.16 + 0.007*sl 0.16 + 0.007*sl 0.16 + 0.008*sl t plz 0.28 0.27 + 0.001*sl 0.28 + 0.000*sl 0.28 + -0.001*sl t phz 1.01 1.01 + 0.000*sl 1.01 + 0.000*sl 1.01 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-168 sec asic nitn/nitnd2/nitnd4/nitnd8 non-inverting tri-state buffer with enable low, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nitn KGM80 nitnd2 KGM80 nitnd4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.32 0.26 + 0.028*sl 0.27 + 0.026*sl 0.28 + 0.025*sl t phl 0.45 0.36 + 0.041*sl 0.37 + 0.038*sl 0.38 + 0.037*sl t r 0.27 0.17 + 0.049*sl 0.16 + 0.052*sl 0.15 + 0.054*sl t f 0.29 0.15 + 0.072*sl 0.14 + 0.073*sl 0.13 + 0.074*sl en to y t plh 0.54 0.48 + 0.029*sl 0.49 + 0.026*sl 0.50 + 0.025*sl t phl 0.42 0.34 + 0.044*sl 0.35 + 0.038*sl 0.36 + 0.037*sl t r 0.27 0.17 + 0.050*sl 0.16 + 0.052*sl 0.15 + 0.054*sl t f 0.30 0.16 + 0.072*sl 0.15 + 0.073*sl 0.14 + 0.074*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.51 0.51 + 0.000*sl 0.51 + 0.000*sl 0.51 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.40 0.37 + 0.018*sl 0.38 + 0.015*sl 0.40 + 0.013*sl t phl 0.52 0.47 + 0.025*sl 0.48 + 0.021*sl 0.50 + 0.019*sl t r 0.24 0.19 + 0.025*sl 0.19 + 0.025*sl 0.18 + 0.025*sl t f 0.23 0.16 + 0.034*sl 0.16 + 0.035*sl 0.15 + 0.036*sl en to y t plh 0.67 0.64 + 0.018*sl 0.65 + 0.015*sl 0.66 + 0.013*sl t phl 0.40 0.34 + 0.029*sl 0.36 + 0.022*sl 0.39 + 0.019*sl t r 0.24 0.19 + 0.025*sl 0.19 + 0.025*sl 0.18 + 0.025*sl t f 0.21 0.14 + 0.038*sl 0.14 + 0.036*sl 0.14 + 0.036*sl t plz 0.25 0.25 + 0.000*sl 0.25 + 0.000*sl 0.25 + 0.000*sl t phz 0.82 0.82 + -0.001*sl 0.82 + 0.000*sl 0.81 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.42 0.40 + 0.011*sl 0.41 + 0.009*sl 0.42 + 0.008*sl t phl 0.60 0.57 + 0.014*sl 0.58 + 0.012*sl 0.59 + 0.010*sl t r 0.22 0.20 + 0.013*sl 0.20 + 0.013*sl 0.20 + 0.013*sl t f 0.27 0.23 + 0.017*sl 0.23 + 0.018*sl 0.24 + 0.017*sl en to y t plh 0.70 0.68 + 0.010*sl 0.68 + 0.009*sl 0.70 + 0.008*sl t phl 0.37 0.34 + 0.014*sl 0.34 + 0.012*sl 0.36 + 0.010*sl t r 0.23 0.20 + 0.013*sl 0.20 + 0.013*sl 0.20 + 0.013*sl t f 0.24 0.22 + 0.010*sl 0.20 + 0.016*sl 0.19 + 0.017*sl t plz 0.24 0.25 + -0.001*sl 0.24 + 0.000*sl 0.25 + 0.000*sl t phz 0.88 0.89 + -0.001*sl 0.88 + 0.000*sl 0.88 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-169 kg80/KGM80 nitn/nitnd2/nitnd4/nitnd8 non-inverting tri-state buffer with enable low, 1x/2x/4x/8x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 nitnd8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to y t plh 0.61 0.60 + 0.007*sl 0.60 + 0.006*sl 0.61 + 0.005*sl t phl 0.89 0.87 + 0.008*sl 0.88 + 0.007*sl 0.88 + 0.006*sl t r 0.31 0.30 + 0.006*sl 0.30 + 0.006*sl 0.30 + 0.006*sl t f 0.39 0.37 + 0.009*sl 0.38 + 0.008*sl 0.38 + 0.008*sl en to y t plh 0.98 0.97 + 0.007*sl 0.97 + 0.006*sl 0.98 + 0.005*sl t phl 0.41 0.40 + 0.009*sl 0.40 + 0.007*sl 0.41 + 0.006*sl t r 0.32 0.31 + 0.006*sl 0.31 + 0.006*sl 0.30 + 0.006*sl t f 0.25 0.24 + 0.005*sl 0.23 + 0.008*sl 0.22 + 0.009*sl t plz 0.33 0.33 + 0.000*sl 0.33 + 0.000*sl 0.33 + 0.000*sl t phz 1.39 1.39 + -0.001*sl 1.39 + 0.000*sl 1.39 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-170 sec asic flip-flops cell list cell name function description fd1 d flip-flop fd1d2 d flip-flop with 2x drive fd1cs d flip-flop with scan clock fd1csd2 d flip-flop with scan clock, 2x drive fd1s d flip-flop with scan fd1sd2 d flip-flop with scan, 2x drive fd1q d flip-flop with q output only fd1qd2 d flip-flop with q output only, 2x drive fd1x2 2-bit d flip-flop fd1x4 4-bit d flip-flop yfd1 fast d flip-flop yfd1d2 fast d flip-flop with 2x drive fd2 d flip-flop with reset fd2d2 d flip-flop with reset, 2x drive fd2cs d flip-flop with reset, scan clock fd2csd2 d flip-flop with reset, scan clock, 2x drive fd2s d flip-flop with reset, scan fd2sd2 d flip-flop with reset, scan, 2x drive fd2q d flip-flop with reset, q output only fd2qd2 d flip-flop with reset, q output only, 2x drive fd2x2 2-bit d flip-flop with reset fd2x4 4-bit d flip-flop with reset yfd2 fast d flip-flop with reset yfd2d2 fast d flip-flop with reset, 2x drive fd2t d flip-flop with reset, tri-state output fd2td2 d flip-flop with reset, tri-state output, 2x drive fd2tcs d flip-flop with reset, scan clock, tri-state output fd2tcsd2 d flip-flop with reset, scan clock, tri-state output, 2x drive fd2ts d flip-flop with reset, scan, tri-state output fd2tsd2 d flip-flop with reset, scan, tri-state output, 2x drive fd3 d flip-flop with set fd3d2 d flip-flop with set, 2x drive fd3cs d flip-flop with set, scan clock fd3csd2 d flip-flop with set, scan clock, 2x drive
sec asic 3-171 kg80/KGM80 fd3s d flip-flop with set, scan fd3sd2 d flip-flop with set, scan, 2x drive fd3q d flip-flop with set, q output only fd3qd2 d flip-flop with set, q output only, 2x drive fd3x2 2-bit d flip-flop with set fd3x4 4-bit d flip-flop with set yfd3 fast d flip-flop with set yfd3d2 fast d flip-flop with set, 2x drive fd4 d flip-flop with reset, set fd4d2 d flip-flop with reset, set, 2x drive fd4cs d flip-flop with reset, set, scan clock fd4csd2 d flip-flop with reset, set, scan clock, 2x drive fd4s d flip-flop with reset, set, scan fd4sd2 d flip-flop with reset, set, scan, 2x drive fd4q d flip-flop with reset, set, q output only fd4qd2 d flip-flop with reset, set, q output only, 2x drive fd4x2 2-bit d flip-flop with reset, set fd4x4 4-bit d flip-flop with reset, set yfd4 fast d flip-flop with reset, set yfd4d2 fast d flip-flop with reset, set, 2x drive fd5 d flip-flop with negative edge trigger fd5d2 d flip-flop with negative edge trigger, 2x drive fd5s d flip-flop with negative edge trigger, scan fd5sd2 d flip-flop with negative edge trigger, scan, 2x drive fd5x4 4-bit flip-flop with negative edge trigger fd6 d flip-flop with negative edge trigger, reset fd6d2 d flip-flop with negative edge trigger, reset, 2x drive fd6s d flip-flop with negative edge trigger, reset, scan fd6sd2 d flip-flop with negative edge trigger, reset, scan, 2x drive fd7 d flip-flop with negative edge trigger, set fd7d2 d flip-flop with negative edge trigger, set, 2x drive fd7s d flip-flop with negative edge trigger, set, scan fd7sd2 d flip-flop with negative edge trigger, set, scan, 2x drive fd8 d flip-flop with negative edge trigger, reset, set cell name function description flip-flops cell list (continued)
kg80/KGM80 3-172 sec asic fd8d2 d flip-flop with negative edge trigger, reset, set, 2x drive fd8s d flip-flop with negative edge trigger, reset, set, scan fd8sd2 d flip-flop with negative edge trigger, reset, set, scan, 2x drive fds2 d flip-flop with synchronous clear fds2d2 d flip-flop with synchronous clear, 2x drive fds2cs d flip-flop with synchronous clear, scan clock fds2csd2 d flip-flop with synchronous clear, scan clock, 2x drive fds2s d flip-flop with synchronous clear, scan fds2sd2 d flip-flop with synchronous clear, scan, 2x drive fds3 d flip-flop with synchronous set fds3d2 d flip-flop with synchronous set, 2x drive fg1 d flip-flop with ck enable fg1x4 4-bit d flip-flop with ck enable fg2 d flip-flop with ck enable, reset fg2x4 4-bit d flip-flop with ck enable, reset fj1 jk flip-flop fj1d2 jk flip-flop with 2x drive fj1s jk flip-flop with scan fj1sd2 jk flip-flop with scan, 2x drive fj2 jk flip-flop with reset fj2d2 jk flip-flop with reset, 2x drive fj2s jk flip-flop with reset, scan fj2sd2 jk flip-flop with reset, scan, 2x drive fj4 jk flip-flop with reset, set fj4d2 jk flip-flop with reset, set, 2x drive fj4s jk flip-flop with reset, set, scan fj4sd2 jk flip-flop with reset, set, scan, 2x drive ft2 toggle flip-flop with reset ft2d2 toggle flip-flop with reset, 2x drive ft3 toggle flip-flop with set ft3d2 toggle flip-flop with set, 2x drive cell name function description flip-flops cell list (continued)
sec asic 3-173 kg80/KGM80 fd1/fd1d2 d flip-flop with 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 fd1 fd1d2 fd1 fd1d2 dckdck 0.9 0.9 0.9 0.9 7.0 8.0 KGM80 fd1 fd1d2 fd1 fd1d2 dckdck 1.0 1.0 1.0 1.0 7.0 8.0 parameter symbol kg80 KGM80 fd1 fd1d2 fd1 fd1d2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 input setup time (d to ck) t su 0.37 0.37 0.64 0.64 input hold time (d to ck) t hd 0.15 0.15 0.33 0.33 d ck q qn d ck cl clb q cl clb clb cl clb cl cl clb qn truth table d ck q (n+1) qn (n+1) 001 110 x q (n) qn (n)
kg80/KGM80 3-174 sec asic fd1/fd1d2 d flip-flop with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40, sl: standard load) kg80 fd1 kg80 fd1d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.51 0.43 + 0.042*sl 0.43 + 0.042*sl 0.43 + 0.042*sl t phl 0.53 0.47 + 0.030*sl 0.49 + 0.026*sl 0.50 + 0.023*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.08 + 0.041*sl ck to qn t plh 0.67 0.59 + 0.040*sl 0.59 + 0.041*sl 0.58 + 0.042*sl t phl 0.59 0.53 + 0.030*sl 0.54 + 0.025*sl 0.55 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.041*sl 0.07 + 0.042*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.49 0.44 + 0.023*sl 0.45 + 0.021*sl 0.45 + 0.021*sl t phl 0.53 0.49 + 0.021*sl 0.50 + 0.015*sl 0.52 + 0.013*sl t r 0.17 0.09 + 0.039*sl 0.08 + 0.044*sl 0.07 + 0.044*sl t f 0.14 0.09 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.020*sl ck to qn t plh 0.70 0.66 + 0.019*sl 0.66 + 0.019*sl 0.65 + 0.020*sl t phl 0.62 0.58 + 0.019*sl 0.59 + 0.015*sl 0.61 + 0.013*sl t r 0.16 0.08 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.021*sl 0.09 + 0.020*sl 0.10 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-175 kg80/KGM80 fd1/fd1d2 d flip-flop with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40, sl: standard load) KGM80 fd1 KGM80 fd1d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.71 0.60 + 0.051*sl 0.61 + 0.050*sl 0.61 + 0.050*sl t phl 0.75 0.68 + 0.034*sl 0.70 + 0.026*sl 0.73 + 0.024*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.045*sl 0.12 + 0.041*sl 0.11 + 0.042*sl ck to qn t plh 0.94 0.85 + 0.049*sl 0.84 + 0.050*sl 0.84 + 0.050*sl t phl 0.83 0.76 + 0.033*sl 0.78 + 0.026*sl 0.81 + 0.023*sl t r 0.34 0.13 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.68 0.62 + 0.028*sl 0.63 + 0.025*sl 0.63 + 0.025*sl t phl 0.75 0.70 + 0.023*sl 0.72 + 0.017*sl 0.76 + 0.013*sl t r 0.22 0.12 + 0.051*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.022*sl 0.13 + 0.021*sl ck to qn t plh 0.99 0.94 + 0.025*sl 0.94 + 0.024*sl 0.93 + 0.025*sl t phl 0.88 0.84 + 0.022*sl 0.85 + 0.016*sl 0.88 + 0.013*sl t r 0.21 0.11 + 0.051*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-176 sec asic fd1cs/fd1csd2 d flip-flop with scan clock, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 fd1cs fd1csd2 fd1cs fd1csd2 si sck d ck si sck d ck 0.9 2.1 0.9 0.9 0.9 2.1 0.9 0.9 11.0 12.0 KGM80 fd1cs fd1csd2 fd1cs fd1csd2 si sck d ck si sck d ck 1.0 2.1 1.0 1.0 1.0 2.1 1.0 1.0 11.0 12.0 q qn si sck d ck cl clb q cl clb clb cl clb cl cl clb qn sck sckb sck sckb sckb sck sckb sck sck sck sckb d si ck truth table si sck d ck q (n+1) qn (n+1) x00 01 x01 10 0 x001 1 x010
sec asic 3-177 kg80/KGM80 fd1cs/fd1csd2 d flip-flop with scan clock, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 fd1cs fd1csd2 fd1cs fd1csd2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (sck) t pwl 0.61 0.61 0.99 0.99 pulse width high (sck) t pwh 0.61 0.61 0.99 0.99 input setup time (d to ck) t su 0.15 0.15 0.64 0.64 input hold time (d to ck) t hd 0.37 0.37 0.33 0.33 input setup time (si to sck) t su 0.15 0.15 0.96 0.96 input hold time (si to sck) t hd 0.56 0.56 0.33 0.33
kg80/KGM80 3-178 sec asic fd1cs/fd1csd2 d flip-flop with scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd1cs kg80 fd1csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.52 0.43 + 0.042*sl 0.43 + 0.042*sl 0.43 + 0.042*sl t phl 0.54 0.48 + 0.030*sl 0.49 + 0.025*sl 0.50 + 0.024*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl sck to q t plh 0.55 0.46 + 0.042*sl 0.47 + 0.041*sl 0.47 + 0.042*sl t phl 0.47 0.41 + 0.031*sl 0.42 + 0.026*sl 0.44 + 0.023*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.089*sl 0.09 + 0.090*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.040*sl 0.09 + 0.041*sl ck to qn t plh 0.74 0.65 + 0.042*sl 0.66 + 0.041*sl 0.65 + 0.041*sl t phl 0.67 0.60 + 0.035*sl 0.62 + 0.028*sl 0.64 + 0.025*sl t r 0.29 0.12 + 0.085*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.21 0.12 + 0.042*sl 0.13 + 0.040*sl 0.12 + 0.041*sl sck to qn t plh 0.61 0.53 + 0.040*sl 0.53 + 0.041*sl 0.52 + 0.042*sl t phl 0.62 0.56 + 0.029*sl 0.57 + 0.025*sl 0.58 + 0.023*sl t r 0.27 0.09 + 0.086*sl 0.09 + 0.090*sl 0.08 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.51 0.46 + 0.022*sl 0.47 + 0.021*sl 0.47 + 0.021*sl t phl 0.54 0.51 + 0.019*sl 0.51 + 0.015*sl 0.53 + 0.013*sl t r 0.19 0.10 + 0.042*sl 0.10 + 0.043*sl 0.09 + 0.045*sl t f 0.15 0.11 + 0.021*sl 0.11 + 0.020*sl 0.11 + 0.020*sl sck to q t plh 0.55 0.51 + 0.023*sl 0.51 + 0.021*sl 0.51 + 0.020*sl t phl 0.48 0.45 + 0.019*sl 0.46 + 0.015*sl 0.47 + 0.013*sl t r 0.20 0.12 + 0.040*sl 0.11 + 0.043*sl 0.11 + 0.044*sl t f 0.16 0.11 + 0.021*sl 0.12 + 0.020*sl 0.12 + 0.020*sl ck to qn t plh 0.78 0.73 + 0.021*sl 0.74 + 0.020*sl 0.74 + 0.020*sl t phl 0.71 0.67 + 0.021*sl 0.68 + 0.017*sl 0.70 + 0.014*sl t r 0.21 0.12 + 0.042*sl 0.12 + 0.042*sl 0.11 + 0.043*sl t f 0.18 0.14 + 0.024*sl 0.14 + 0.020*sl 0.15 + 0.020*sl sck to qn t plh 0.65 0.61 + 0.019*sl 0.61 + 0.019*sl 0.60 + 0.020*sl t phl 0.68 0.64 + 0.017*sl 0.65 + 0.014*sl 0.66 + 0.013*sl t r 0.19 0.10 + 0.042*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.11 + 0.020*sl 0.11 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-179 kg80/KGM80 fd1cs/fd1csd2 d flip-flop with scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd1cs KGM80 fd1csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.72 0.61 + 0.051*sl 0.62 + 0.050*sl 0.62 + 0.050*sl t phl 0.75 0.68 + 0.034*sl 0.70 + 0.026*sl 0.73 + 0.024*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.043*sl 0.12 + 0.042*sl 0.11 + 0.042*sl sck to q t plh 0.81 0.70 + 0.052*sl 0.71 + 0.050*sl 0.71 + 0.050*sl t phl 0.66 0.59 + 0.035*sl 0.61 + 0.026*sl 0.65 + 0.023*sl t r 0.37 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.12 + 0.042*sl ck to qn t plh 1.03 0.92 + 0.053*sl 0.93 + 0.050*sl 0.93 + 0.050*sl t phl 0.95 0.88 + 0.040*sl 0.90 + 0.029*sl 0.95 + 0.025*sl t r 0.38 0.17 + 0.102*sl 0.16 + 0.106*sl 0.14 + 0.108*sl t f 0.25 0.15 + 0.047*sl 0.16 + 0.043*sl 0.17 + 0.042*sl sck to qn t plh 0.85 0.76 + 0.049*sl 0.75 + 0.050*sl 0.75 + 0.050*sl t phl 0.92 0.86 + 0.032*sl 0.88 + 0.025*sl 0.90 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.11 + 0.041*sl 0.10 + 0.043*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.71 0.65 + 0.027*sl 0.66 + 0.025*sl 0.66 + 0.025*sl t phl 0.77 0.73 + 0.021*sl 0.74 + 0.016*sl 0.77 + 0.013*sl t r 0.25 0.15 + 0.051*sl 0.14 + 0.053*sl 0.13 + 0.054*sl t f 0.18 0.13 + 0.024*sl 0.14 + 0.021*sl 0.15 + 0.021*sl sck to q t plh 0.82 0.76 + 0.028*sl 0.77 + 0.025*sl 0.77 + 0.025*sl t phl 0.69 0.64 + 0.022*sl 0.66 + 0.016*sl 0.69 + 0.013*sl t r 0.27 0.17 + 0.050*sl 0.17 + 0.052*sl 0.15 + 0.053*sl t f 0.19 0.14 + 0.023*sl 0.15 + 0.021*sl 0.16 + 0.020*sl ck to qn t plh 1.09 1.03 + 0.028*sl 1.04 + 0.025*sl 1.04 + 0.025*sl t phl 1.02 0.97 + 0.025*sl 0.99 + 0.018*sl 1.02 + 0.015*sl t r 0.28 0.17 + 0.052*sl 0.18 + 0.052*sl 0.16 + 0.053*sl t f 0.22 0.17 + 0.027*sl 0.18 + 0.022*sl 0.20 + 0.021*sl sck to qn t plh 0.92 0.87 + 0.023*sl 0.87 + 0.024*sl 0.86 + 0.025*sl t phl 1.01 0.97 + 0.019*sl 0.98 + 0.015*sl 1.01 + 0.013*sl t r 0.25 0.15 + 0.051*sl 0.14 + 0.053*sl 0.13 + 0.054*sl t f 0.18 0.13 + 0.023*sl 0.14 + 0.021*sl 0.14 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-180 sec asic fd1s/fd1sd2 d flip-flop with scan, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 fd1s fd1sd2 fd1s fd1sd2 d ti te ck d ti te ck 0.6 0.8 1.6 0.9 0.6 0.8 1.6 0.9 9.0 10.0 KGM80 fd1s fd1sd2 fd1s fd1sd2 d ti te ck d ti te ck 1.0 1.0 2.0 1.1 1.0 1.0 2.0 1.1 9.0 10.0 parameter symbol kg80 KGM80 fd1s fd1sd2 fd1s fd1sd2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 input setup time (d to ck) t su 0.47 0.47 0.86 0.86 input hold time (d to ck) t hd 0.15 0.15 0.33 0.33 input setup time (ti to ck) t su 0.50 0.53 0.96 0.96 input hold time (ti to ck) t hd 0.15 0.15 0.33 0.33 input setup time (te to ck) t su 0.56 0.56 0.96 0.99 input hold time (te to ck) t hd 0.15 0.15 0.33 0.33 q qn d ti te ck d te ti cl clb q clb cl clb cl cl clb qn cl clb ck truth table dtiteck q (n+1) qn (n+1) 0x0 01 1x0 10 x01 01 x11 10
sec asic 3-181 kg80/KGM80 fd1s/fd1sd2 d flip-flop with scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd1s kg80 fd1sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.51 0.43 + 0.042*sl 0.43 + 0.042*sl 0.43 + 0.042*sl t phl 0.53 0.47 + 0.030*sl 0.48 + 0.026*sl 0.50 + 0.023*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.041*sl ck to qn t plh 0.67 0.59 + 0.040*sl 0.58 + 0.041*sl 0.58 + 0.042*sl t phl 0.59 0.53 + 0.030*sl 0.54 + 0.025*sl 0.55 + 0.023*sl t r 0.26 0.09 + 0.085*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl *g 1 sl 2 *g 2 2 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.49 0.44 + 0.022*sl 0.45 + 0.021*sl 0.45 + 0.021*sl t phl 0.53 0.49 + 0.021*sl 0.50 + 0.015*sl 0.51 + 0.013*sl t r 0.17 0.09 + 0.040*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl ck to qn t plh 0.69 0.66 + 0.019*sl 0.66 + 0.019*sl 0.65 + 0.020*sl t phl 0.62 0.58 + 0.018*sl 0.59 + 0.015*sl 0.61 + 0.013*sl t r 0.17 0.08 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.021*sl 0.09 + 0.020*sl 0.10 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-182 sec asic fd1s/fd1sd2 d flip-flop with scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd1s KGM80 fd1sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.70 0.60 + 0.051*sl 0.60 + 0.050*sl 0.61 + 0.050*sl t phl 0.74 0.67 + 0.034*sl 0.70 + 0.026*sl 0.73 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl ck to qn t plh 0.94 0.84 + 0.049*sl 0.84 + 0.050*sl 0.84 + 0.050*sl t phl 0.82 0.76 + 0.033*sl 0.78 + 0.026*sl 0.80 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.044*sl 0.11 + 0.041*sl 0.10 + 0.042*sl *g 1 sl 3 *g 2 3 sl 11 *g 3 11 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.67 0.62 + 0.028*sl 0.62 + 0.025*sl 0.63 + 0.025*sl t phl 0.75 0.70 + 0.023*sl 0.72 + 0.016*sl 0.75 + 0.013*sl t r 0.22 0.12 + 0.051*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.022*sl 0.13 + 0.021*sl ck to qn t plh 0.98 0.93 + 0.024*sl 0.93 + 0.024*sl 0.93 + 0.025*sl t phl 0.88 0.83 + 0.022*sl 0.85 + 0.016*sl 0.88 + 0.013*sl t r 0.21 0.11 + 0.051*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-183 kg80/KGM80 fd1q/fd1qd2 d flip-flop with q output only, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 fd1q fd1qd2 fd1q fd1qd2 dckdck 0.8 0.8 0.8 0.8 8.0 9.0 KGM80 fd1q fd1qd2 fd1q fd1qd2 dckdck 0.9 0.9 0.9 0.9 8.0 9.0 parameter symbol kg80 KGM80 fd1q fd1qd2 fd1q fd1qd2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 input setup time (d to ck) t su 0.39 0.39 0.71 0.71 input hold time (d to ck) t hd 0.15 0.15 0.33 0.33 d ck q d ck cl clb q cl clb clb cl clb cl cl clb truth table d ck q (n+1) 00 11 x q (n)
kg80/KGM80 3-184 sec asic fd1q/fd1qd2 d flip-flop with q output only, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd1q kg80 fd1qd2 switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd1q KGM80 fd1qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.49 0.41 + 0.043*sl 0.41 + 0.042*sl 0.41 + 0.042*sl t phl 0.50 0.44 + 0.031*sl 0.45 + 0.025*sl 0.46 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.041*sl 0.08 + 0.040*sl 0.07 + 0.041*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.48 0.44 + 0.022*sl 0.44 + 0.021*sl 0.44 + 0.021*sl t phl 0.50 0.46 + 0.019*sl 0.47 + 0.015*sl 0.49 + 0.013*sl t r 0.19 0.10 + 0.041*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.70 0.60 + 0.052*sl 0.60 + 0.050*sl 0.61 + 0.050*sl t phl 0.70 0.63 + 0.034*sl 0.65 + 0.026*sl 0.68 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.044*sl 0.11 + 0.041*sl 0.10 + 0.042*sl gs g s g s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.69 0.63 + 0.027*sl 0.64 + 0.025*sl 0.64 + 0.025*sl t phl 0.71 0.67 + 0.021*sl 0.69 + 0.016*sl 0.72 + 0.013*sl t r 0.24 0.14 + 0.051*sl 0.14 + 0.053*sl 0.12 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.021*sl 0.14 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-185 kg80/KGM80 fd1x2 2-bit d flip-flop logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd1x2 parameter symbol kg80 KGM80 pulse width low (ck) t pwl 0.61 1.02 pulse width high (ck) t pwh 0.61 0.99 input setup time (d0 to ck) t su 0.15 0.58 input hold time (d0 to ck) t hd 0.28 0.33 input setup time (d1 to ck) t su 0.31 0.58 input hold time (d1 to ck) t hd 0.15 0.33 q0 qn1 d0 d1 ck q1 qn0 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.57 0.48 + 0.042*sl 0.48 + 0.042*sl 0.48 + 0.042*sl t phl 0.64 0.57 + 0.031*sl 0.59 + 0.026*sl 0.60 + 0.024*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.08 + 0.042*sl ck to q1 t plh 0.57 0.48 + 0.042*sl 0.48 + 0.042*sl 0.48 + 0.042*sl t phl 0.64 0.57 + 0.031*sl 0.59 + 0.026*sl 0.60 + 0.024*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.08 + 0.042*sl ck to qn0 t plh 0.77 0.69 + 0.040*sl 0.69 + 0.041*sl 0.68 + 0.042*sl t phl 0.64 0.58 + 0.030*sl 0.59 + 0.025*sl 0.61 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl ck to qn1 t plh 0.77 0.69 + 0.040*sl 0.69 + 0.041*sl 0.68 + 0.042*sl t phl 0.64 0.58 + 0.030*sl 0.59 + 0.025*sl 0.61 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = truth table cell data dn ck qn (n+1) qnn (n+1) 001 110 x qn (n) qnn (n) input load (sl) gate count kg80 dn ck 12.0 1.0 0.9 KGM80 dn ck 12.0 1.0 1.1
kg80/KGM80 3-186 sec asic fd1x2 2-bit d flip-flop switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd1x2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.77 0.67 + 0.051*sl 0.67 + 0.050*sl 0.68 + 0.050*sl t phl 0.89 0.82 + 0.034*sl 0.84 + 0.026*sl 0.87 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.044*sl 0.12 + 0.042*sl 0.11 + 0.042*sl ck to q1 t plh 0.77 0.67 + 0.051*sl 0.67 + 0.050*sl 0.68 + 0.050*sl t phl 0.89 0.82 + 0.034*sl 0.84 + 0.026*sl 0.87 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.044*sl 0.12 + 0.042*sl 0.11 + 0.042*sl ck to qn0 t plh 1.08 0.98 + 0.049*sl 0.98 + 0.050*sl 0.98 + 0.050*sl t phl 0.89 0.83 + 0.033*sl 0.85 + 0.026*sl 0.87 + 0.023*sl t r 0.34 0.13 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.041*sl 0.10 + 0.042*sl ck to qn1 t plh 1.08 0.98 + 0.049*sl 0.98 + 0.050*sl 0.98 + 0.050*sl t phl 0.89 0.82 + 0.033*sl 0.84 + 0.026*sl 0.87 + 0.023*sl t r 0.34 0.13 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-187 kg80/KGM80 fd1x4 4-bit d flip-flop logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 pulse width low (ck) t pwl 0.80 1.27 pulse width high (ck) t pwh 0.61 0.99 input setup time (d0 to ck) t su 0.17 0.46 input hold time (d0 to ck) t hd 0.26 0.43 input setup time (d1 to ck) t su 0.17 0.46 input hold time (d1 to ck) t hd 0.26 0.43 input setup time (d2 to ck) t su 0.17 0.46 input hold time (d2 to ck) t hd 0.26 0.43 input setup time (d3 to ck) t su 0.17 0.46 input hold time (d3 to ck) t hd 0.26 0.43 d0 d1 d2 d3 ck q0 q1 q2 q3 qn0 qn1 qn2 qn3 truth table cell data dn ck qn (n+1) qnn (n+1) 001 110 x qn (n) qnn (n) input load (sl) gate count kg80 dn ck 24.0 1.0 0.9 KGM80 dn ck 24.0 1.0 1.1
kg80/KGM80 3-188 sec asic fd1x4 4-bit d flip-flop switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd1x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.67 0.59 + 0.042*sl 0.59 + 0.042*sl 0.59 + 0.042*sl t phl 0.83 0.77 + 0.031*sl 0.78 + 0.026*sl 0.80 + 0.023*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.041*sl 0.10 + 0.040*sl 0.08 + 0.041*sl ck to q1 t plh 0.68 0.59 + 0.042*sl 0.59 + 0.042*sl 0.59 + 0.042*sl t phl 0.84 0.77 + 0.031*sl 0.79 + 0.026*sl 0.80 + 0.024*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.09 + 0.041*sl ck to q2 t plh 0.68 0.59 + 0.042*sl 0.59 + 0.042*sl 0.59 + 0.042*sl t phl 0.84 0.77 + 0.031*sl 0.79 + 0.026*sl 0.80 + 0.024*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.09 + 0.041*sl ck to q3 t plh 0.67 0.59 + 0.042*sl 0.59 + 0.042*sl 0.59 + 0.042*sl t phl 0.83 0.77 + 0.031*sl 0.78 + 0.026*sl 0.80 + 0.023*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.041*sl 0.10 + 0.040*sl 0.08 + 0.041*sl ck to qn0 t plh 0.96 0.88 + 0.040*sl 0.88 + 0.041*sl 0.88 + 0.042*sl t phl 0.74 0.68 + 0.030*sl 0.69 + 0.025*sl 0.71 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl ck to qn1 t plh 0.97 0.89 + 0.040*sl 0.89 + 0.041*sl 0.88 + 0.042*sl t phl 0.75 0.69 + 0.029*sl 0.70 + 0.025*sl 0.71 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl ck to qn2 t plh 0.97 0.89 + 0.040*sl 0.89 + 0.041*sl 0.88 + 0.042*sl t phl 0.75 0.69 + 0.030*sl 0.70 + 0.025*sl 0.71 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.041*sl 0.07 + 0.042*sl ck to qn3 t plh 0.96 0.88 + 0.040*sl 0.88 + 0.041*sl 0.88 + 0.042*sl t phl 0.74 0.68 + 0.030*sl 0.69 + 0.025*sl 0.71 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-189 kg80/KGM80 fd1x4 4-bit d flip-flop switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd1x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.89 0.79 + 0.051*sl 0.79 + 0.050*sl 0.80 + 0.050*sl t phl 1.16 1.09 + 0.034*sl 1.11 + 0.026*sl 1.14 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl ck to q1 t plh 0.90 0.80 + 0.050*sl 0.80 + 0.050*sl 0.81 + 0.050*sl t phl 1.17 1.10 + 0.034*sl 1.12 + 0.026*sl 1.15 + 0.023*sl t r 0.35 0.15 + 0.104*sl 0.14 + 0.108*sl 0.13 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.12 + 0.042*sl ck to q2 t plh 0.90 0.80 + 0.051*sl 0.80 + 0.050*sl 0.81 + 0.050*sl t phl 1.17 1.10 + 0.034*sl 1.12 + 0.026*sl 1.15 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.12 + 0.042*sl ck to q3 t plh 0.89 0.79 + 0.051*sl 0.79 + 0.050*sl 0.80 + 0.050*sl t phl 1.16 1.09 + 0.034*sl 1.11 + 0.026*sl 1.14 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl ck to qn0 t plh 1.35 1.25 + 0.049*sl 1.25 + 0.050*sl 1.25 + 0.050*sl t phl 1.01 0.95 + 0.033*sl 0.97 + 0.026*sl 0.99 + 0.023*sl t r 0.34 0.13 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl ck to qn1 t plh 1.36 1.26 + 0.050*sl 1.26 + 0.050*sl 1.26 + 0.050*sl t phl 1.02 0.96 + 0.032*sl 0.98 + 0.026*sl 1.00 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.041*sl 0.10 + 0.042*sl ck to qn2 t plh 1.36 1.26 + 0.049*sl 1.26 + 0.050*sl 1.26 + 0.050*sl t phl 1.02 0.96 + 0.032*sl 0.98 + 0.026*sl 1.00 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl ck to qn3 t plh 1.35 1.25 + 0.049*sl 1.25 + 0.050*sl 1.25 + 0.050*sl t phl 1.01 0.95 + 0.033*sl 0.97 + 0.026*sl 0.99 + 0.023*sl t r 0.34 0.13 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-190 sec asic yfd1/yfd1d2 fast d flip-flop with 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 yfd1 yfd1d2 yfd1 yfd1d2 dckdck 2.9 0.8 2.9 0.8 5.0 6.0 KGM80 yfd1 yfd1d2 yfd1 yfd1d2 dckdck 3.7 0.9 3.7 0.9 5.0 6.0 parameter symbol kg80 KGM80 yfd1 yfd1d2 yfd1 yfd1d2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 input setup time (d to ck) t su 0.26 0.26 0.52 0.49 input hold time (d to ck) t hd 0.26 0.26 0.46 0.46 d ck q qn d ck cl clb q cl clb clb cl clb cl cl clb qn truth table d ck q (n+1) qn (n+1) 001 110 x q (n) qn (n)
sec asic 3-191 kg80/KGM80 yfd1/yfd1d2 fast d flip-flop with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40, sl: standard load) kg80 yfd1 kg80 yfd1d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.45 0.37 + 0.043*sl 0.37 + 0.042*sl 0.37 + 0.042*sl t phl 0.38 0.32 + 0.033*sl 0.33 + 0.028*sl 0.35 + 0.025*sl t r 0.35 0.18 + 0.086*sl 0.18 + 0.088*sl 0.16 + 0.090*sl t f 0.22 0.13 + 0.043*sl 0.13 + 0.042*sl 0.14 + 0.042*sl ck to qn t plh 0.57 0.40 + 0.086*sl 0.42 + 0.080*sl 0.44 + 0.077*sl t phl 0.58 0.42 + 0.078*sl 0.42 + 0.077*sl 0.42 + 0.077*sl t r 0.32 0.13 + 0.094*sl 0.13 + 0.094*sl 0.13 + 0.094*sl t f 0.21 0.09 + 0.061*sl 0.08 + 0.063*sl 0.08 + 0.063*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.44 0.40 + 0.023*sl 0.40 + 0.021*sl 0.40 + 0.021*sl t phl 0.38 0.34 + 0.019*sl 0.35 + 0.016*sl 0.37 + 0.014*sl t r 0.28 0.19 + 0.042*sl 0.19 + 0.044*sl 0.18 + 0.045*sl t f 0.20 0.15 + 0.023*sl 0.15 + 0.022*sl 0.16 + 0.021*sl ck to qn t plh 0.51 0.42 + 0.047*sl 0.43 + 0.043*sl 0.44 + 0.041*sl t phl 0.52 0.44 + 0.040*sl 0.44 + 0.039*sl 0.45 + 0.038*sl t r 0.21 0.11 + 0.048*sl 0.11 + 0.047*sl 0.11 + 0.048*sl t f 0.14 0.08 + 0.031*sl 0.08 + 0.031*sl 0.07 + 0.031*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-192 sec asic yfd1/yfd1d2 fast d flip-flop with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40, sl: standard load) KGM80 yfd1 KGM80 yfd1d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.63 0.53 + 0.052*sl 0.53 + 0.050*sl 0.54 + 0.050*sl t phl 0.55 0.47 + 0.037*sl 0.49 + 0.029*sl 0.54 + 0.025*sl t r 0.47 0.26 + 0.103*sl 0.25 + 0.107*sl 0.23 + 0.109*sl t f 0.27 0.18 + 0.048*sl 0.19 + 0.044*sl 0.21 + 0.042*sl ck to qn t plh 0.80 0.60 + 0.101*sl 0.63 + 0.091*sl 0.67 + 0.087*sl t phl 0.80 0.61 + 0.094*sl 0.62 + 0.092*sl 0.62 + 0.092*sl t r 0.43 0.20 + 0.112*sl 0.20 + 0.112*sl 0.20 + 0.112*sl t f 0.25 0.11 + 0.067*sl 0.11 + 0.068*sl 0.11 + 0.068*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.62 0.56 + 0.028*sl 0.57 + 0.026*sl 0.58 + 0.025*sl t phl 0.56 0.52 + 0.023*sl 0.53 + 0.018*sl 0.57 + 0.015*sl t r 0.37 0.27 + 0.052*sl 0.27 + 0.052*sl 0.25 + 0.053*sl t f 0.26 0.21 + 0.025*sl 0.22 + 0.023*sl 0.24 + 0.021*sl ck to qn t plh 0.74 0.63 + 0.055*sl 0.64 + 0.050*sl 0.69 + 0.046*sl t phl 0.73 0.63 + 0.048*sl 0.64 + 0.046*sl 0.64 + 0.046*sl t r 0.27 0.16 + 0.055*sl 0.16 + 0.056*sl 0.16 + 0.056*sl t f 0.16 0.10 + 0.032*sl 0.10 + 0.033*sl 0.09 + 0.033*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-193 kg80/KGM80 fd2/fd2d2 d flip-flop with reset, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 fd2 fd2d2 fd2 fd2d2 d ck rn d ck rn 0.9 0.9 1.7 0.9 0.9 1.6 8.0 9.0 KGM80 fd2 fd2d2 fd2 fd2d2 d ck rn d ck rn 1.1 1.0 2.0 1.1 1.0 2.0 8.0 9.0 parameter symbol kg80 KGM80 fd2 fd2d2 fd2 fd2d2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 0.99 input setup time (d to ck) t su 0.37 0.37 0.68 0.68 input hold time (d to ck) t hd 0.15 0.15 0.33 0.33 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ck) t hd 0.37 0.37 0.63 0.63 d ck q qn rn d ck cl clb q cl clb cl clb cl cl clb qn clb rn rn rn rn truth table d ck rn q (n+1) qn (n+1) 0 101 1 110 xx001 x 1 q (n) qn (n)
kg80/KGM80 3-194 sec asic fd2/fd2d2 d flip-flop with reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd2 kg80 fd2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.58 0.49 + 0.045*sl 0.50 + 0.042*sl 0.50 + 0.042*sl t phl 0.55 0.48 + 0.032*sl 0.50 + 0.026*sl 0.52 + 0.024*sl t r 0.29 0.12 + 0.086*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.09 + 0.043*sl 0.10 + 0.040*sl 0.09 + 0.041*sl rn to q t phl 0.35 0.28 + 0.033*sl 0.29 + 0.027*sl 0.31 + 0.024*sl t f 0.20 0.11 + 0.041*sl 0.12 + 0.039*sl 0.11 + 0.040*sl ck to qn t plh 0.69 0.61 + 0.040*sl 0.61 + 0.041*sl 0.60 + 0.042*sl t phl 0.66 0.60 + 0.030*sl 0.61 + 0.025*sl 0.62 + 0.023*sl t r 0.26 0.09 + 0.085*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl rn to qn t plh 0.49 0.41 + 0.040*sl 0.41 + 0.041*sl 0.40 + 0.042*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.08 + 0.091*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.56 0.51 + 0.025*sl 0.52 + 0.022*sl 0.53 + 0.021*sl t phl 0.54 0.50 + 0.021*sl 0.51 + 0.016*sl 0.53 + 0.014*sl t r 0.19 0.11 + 0.043*sl 0.11 + 0.043*sl 0.10 + 0.044*sl t f 0.15 0.10 + 0.023*sl 0.11 + 0.020*sl 0.11 + 0.020*sl rn to q t phl 0.33 0.29 + 0.022*sl 0.30 + 0.017*sl 0.33 + 0.014*sl t f 0.16 0.12 + 0.023*sl 0.12 + 0.020*sl 0.13 + 0.019*sl ck to qn t plh 0.72 0.68 + 0.020*sl 0.68 + 0.019*sl 0.67 + 0.020*sl t phl 0.71 0.67 + 0.018*sl 0.68 + 0.015*sl 0.69 + 0.013*sl t r 0.17 0.09 + 0.040*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.019*sl 0.10 + 0.020*sl rn to qn t plh 0.51 0.48 + 0.020*sl 0.48 + 0.019*sl 0.47 + 0.020*sl t r 0.17 0.09 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-195 kg80/KGM80 fd2/fd2d2 d flip-flop with reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd2 KGM80 fd2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.80 0.70 + 0.054*sl 0.71 + 0.051*sl 0.72 + 0.050*sl t phl 0.77 0.70 + 0.036*sl 0.73 + 0.027*sl 0.76 + 0.024*sl t r 0.38 0.17 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.108*sl t f 0.22 0.13 + 0.045*sl 0.14 + 0.041*sl 0.13 + 0.042*sl rn to q t phl 0.45 0.38 + 0.037*sl 0.40 + 0.028*sl 0.44 + 0.024*sl t f 0.23 0.14 + 0.044*sl 0.15 + 0.041*sl 0.14 + 0.041*sl ck to qn t plh 0.98 0.88 + 0.049*sl 0.88 + 0.050*sl 0.87 + 0.050*sl t phl 0.93 0.87 + 0.033*sl 0.89 + 0.026*sl 0.92 + 0.023*sl t r 0.34 0.14 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.12 + 0.043*sl 0.12 + 0.041*sl 0.11 + 0.042*sl rn to qn t plh 0.66 0.56 + 0.049*sl 0.56 + 0.050*sl 0.55 + 0.050*sl t r 0.34 0.14 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.78 0.72 + 0.031*sl 0.73 + 0.027*sl 0.75 + 0.025*sl t phl 0.77 0.72 + 0.024*sl 0.74 + 0.017*sl 0.78 + 0.014*sl t r 0.25 0.14 + 0.053*sl 0.14 + 0.052*sl 0.14 + 0.053*sl t f 0.17 0.12 + 0.026*sl 0.13 + 0.022*sl 0.15 + 0.021*sl rn to q t phl 0.45 0.39 + 0.026*sl 0.42 + 0.018*sl 0.46 + 0.014*sl t f 0.19 0.13 + 0.027*sl 0.15 + 0.022*sl 0.17 + 0.020*sl ck to qn t plh 1.02 0.97 + 0.025*sl 0.97 + 0.024*sl 0.96 + 0.025*sl t phl 1.01 0.96 + 0.021*sl 0.98 + 0.016*sl 1.01 + 0.013*sl t r 0.22 0.11 + 0.051*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.021*sl 0.14 + 0.020*sl rn to qn t plh 0.70 0.65 + 0.025*sl 0.65 + 0.024*sl 0.64 + 0.025*sl t r 0.22 0.12 + 0.051*sl 0.11 + 0.052*sl 0.10 + 0.054*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-196 sec asic fd2cs/fd2csd2 d flip-flop with reset, scan clock, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 fd2cs fd2csd2 fd2cs fd2csd2 si sck d ck rn si sck d ck rn 0.9 2.1 0.9 0.9 2.7 0.9 2.1 0.9 0.9 2.7 12.0 13.0 KGM80 fd2cs fd2csd2 fd2cs fd2csd2 si sck d ck rn si sck d ck rn 1.0 2.9 1.1 1.0 3.2 1.0 2.9 1.1 1.0 3.2 12.0 13.0 q qn si sck d ck rn d cl clb q cl clb cl cl clb qn clb sck sckb sck sckb sckb sck sckb sck si rn rn rn cl clb sck sck sckb ck rn rn truth table si sck d ck rn q (n+1) qn (n+1) x00 101 x01 110 0 x0101 1 x0110 xxxx001
sec asic 3-197 kg80/KGM80 fd2cs/fd2csd2 d flip-flop with reset, scan clock, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 fd2cs fd2csd2 fd2cs fd2csd2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (sck) t pwl 0.61 0.61 0.99 0.99 pulse width high (sck) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 0.99 input setup time (d to ck) t su 0.37 0.37 0.68 0.68 input hold time (d to ck) t hd 0.15 0.15 0.33 0.33 input setup time (si to sck) t su 0.56 0.56 0.96 0.96 input hold time (si to sck) t hd 0.15 0.15 0.33 0.33 recovery time (rn to ck) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ck) t hd 0.37 0.37 0.63 0.63 recovery time (rn to sck) t rc 0.15 0.15 0.33 0.33 input hold time (rn to sck) t hd 0.26 0.26 0.63 0.63
kg80/KGM80 3-198 sec asic fd2cs/fd2csd2 d flip-flop with reset, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd2cs kg80 fd2csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.56 0.47 + 0.044*sl 0.48 + 0.042*sl 0.48 + 0.042*sl t phl 0.53 0.47 + 0.031*sl 0.49 + 0.026*sl 0.50 + 0.024*sl t r 0.29 0.12 + 0.085*sl 0.11 + 0.089*sl 0.10 + 0.090*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.08 + 0.042*sl sck to q t plh 0.62 0.53 + 0.044*sl 0.54 + 0.042*sl 0.54 + 0.042*sl t phl 0.47 0.41 + 0.031*sl 0.43 + 0.026*sl 0.44 + 0.024*sl t r 0.30 0.13 + 0.085*sl 0.12 + 0.088*sl 0.11 + 0.089*sl t f 0.18 0.10 + 0.042*sl 0.10 + 0.039*sl 0.09 + 0.041*sl rn to q t phl 0.33 0.27 + 0.032*sl 0.29 + 0.026*sl 0.30 + 0.024*sl t f 0.19 0.11 + 0.039*sl 0.11 + 0.039*sl 0.10 + 0.041*sl ck to qn t plh 0.74 0.66 + 0.042*sl 0.66 + 0.041*sl 0.66 + 0.041*sl t phl 0.73 0.66 + 0.036*sl 0.68 + 0.028*sl 0.70 + 0.025*sl t r 0.29 0.12 + 0.083*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.21 0.13 + 0.043*sl 0.14 + 0.040*sl 0.13 + 0.041*sl sck to qn t plh 0.62 0.54 + 0.040*sl 0.53 + 0.041*sl 0.53 + 0.042*sl t phl 0.70 0.64 + 0.030*sl 0.65 + 0.025*sl 0.67 + 0.023*sl t r 0.27 0.09 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.039*sl 0.09 + 0.040*sl 0.08 + 0.041*sl rn to qn t plh 0.55 0.47 + 0.042*sl 0.47 + 0.041*sl 0.47 + 0.041*sl t r 0.29 0.12 + 0.084*sl 0.11 + 0.088*sl 0.10 + 0.090*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.56 0.52 + 0.024*sl 0.52 + 0.022*sl 0.53 + 0.021*sl t phl 0.54 0.50 + 0.019*sl 0.51 + 0.015*sl 0.53 + 0.013*sl t r 0.21 0.13 + 0.042*sl 0.12 + 0.043*sl 0.12 + 0.044*sl t f 0.15 0.11 + 0.023*sl 0.11 + 0.020*sl 0.11 + 0.020*sl sck to q t plh 0.63 0.58 + 0.024*sl 0.59 + 0.022*sl 0.60 + 0.021*sl t phl 0.48 0.45 + 0.019*sl 0.46 + 0.015*sl 0.47 + 0.013*sl t r 0.22 0.14 + 0.042*sl 0.14 + 0.042*sl 0.13 + 0.044*sl t f 0.16 0.12 + 0.021*sl 0.12 + 0.020*sl 0.12 + 0.020*sl rn to q t phl 0.34 0.30 + 0.020*sl 0.31 + 0.016*sl 0.33 + 0.013*sl t f 0.17 0.12 + 0.022*sl 0.13 + 0.019*sl 0.13 + 0.019*sl ck to qn t plh 0.79 0.74 + 0.022*sl 0.75 + 0.020*sl 0.75 + 0.020*sl t phl 0.78 0.74 + 0.021*sl 0.75 + 0.017*sl 0.77 + 0.014*sl t r 0.21 0.13 + 0.042*sl 0.13 + 0.042*sl 0.12 + 0.043*sl t f 0.20 0.15 + 0.025*sl 0.16 + 0.020*sl 0.16 + 0.020*sl sck to qn t plh 0.66 0.62 + 0.019*sl 0.62 + 0.019*sl 0.61 + 0.020*sl t phl 0.77 0.74 + 0.017*sl 0.74 + 0.014*sl 0.75 + 0.013*sl t r 0.19 0.10 + 0.043*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.15 0.11 + 0.020*sl 0.11 + 0.019*sl 0.11 + 0.020*sl rn to qn t plh 0.59 0.55 + 0.021*sl 0.55 + 0.020*sl 0.55 + 0.020*sl t r 0.21 0.13 + 0.041*sl 0.13 + 0.042*sl 0.12 + 0.043*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-199 kg80/KGM80 fd2cs/fd2csd2 d flip-flop with reset, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd2cs KGM80 fd2csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.78 0.67 + 0.054*sl 0.68 + 0.051*sl 0.69 + 0.050*sl t phl 0.75 0.68 + 0.034*sl 0.71 + 0.026*sl 0.74 + 0.024*sl t r 0.37 0.16 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.109*sl t f 0.20 0.12 + 0.043*sl 0.12 + 0.042*sl 0.12 + 0.042*sl sck to q t plh 0.90 0.79 + 0.055*sl 0.81 + 0.051*sl 0.82 + 0.050*sl t phl 0.67 0.59 + 0.035*sl 0.62 + 0.027*sl 0.65 + 0.023*sl t r 0.39 0.18 + 0.105*sl 0.18 + 0.106*sl 0.15 + 0.108*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.041*sl 0.12 + 0.042*sl rn to q t phl 0.43 0.36 + 0.036*sl 0.39 + 0.027*sl 0.41 + 0.024*sl t f 0.22 0.13 + 0.043*sl 0.14 + 0.041*sl 0.13 + 0.042*sl ck to qn t plh 1.04 0.93 + 0.053*sl 0.94 + 0.050*sl 0.94 + 0.050*sl t phl 1.04 0.96 + 0.040*sl 0.99 + 0.030*sl 1.03 + 0.025*sl t r 0.38 0.17 + 0.103*sl 0.16 + 0.106*sl 0.14 + 0.108*sl t f 0.25 0.16 + 0.047*sl 0.17 + 0.043*sl 0.18 + 0.042*sl sck to qn t plh 0.87 0.77 + 0.049*sl 0.77 + 0.050*sl 0.77 + 0.050*sl t phl 1.03 0.97 + 0.033*sl 0.99 + 0.026*sl 1.02 + 0.023*sl t r 0.35 0.14 + 0.103*sl 0.13 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.12 + 0.043*sl 0.12 + 0.041*sl 0.11 + 0.042*sl rn to qn t plh 0.73 0.62 + 0.053*sl 0.63 + 0.050*sl 0.63 + 0.050*sl t r 0.38 0.17 + 0.102*sl 0.16 + 0.106*sl 0.14 + 0.108*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.79 0.73 + 0.030*sl 0.74 + 0.026*sl 0.75 + 0.025*sl t phl 0.77 0.73 + 0.022*sl 0.75 + 0.016*sl 0.78 + 0.013*sl t r 0.28 0.18 + 0.052*sl 0.18 + 0.052*sl 0.16 + 0.054*sl t f 0.18 0.13 + 0.024*sl 0.14 + 0.021*sl 0.15 + 0.021*sl sck to q t plh 0.93 0.87 + 0.031*sl 0.88 + 0.026*sl 0.89 + 0.025*sl t phl 0.69 0.65 + 0.022*sl 0.66 + 0.016*sl 0.69 + 0.013*sl t r 0.30 0.19 + 0.052*sl 0.19 + 0.052*sl 0.18 + 0.053*sl t f 0.19 0.14 + 0.025*sl 0.15 + 0.021*sl 0.16 + 0.020*sl rn to q t phl 0.45 0.40 + 0.023*sl 0.42 + 0.016*sl 0.45 + 0.013*sl t f 0.20 0.15 + 0.025*sl 0.16 + 0.021*sl 0.17 + 0.020*sl ck to qn t plh 1.10 1.05 + 0.028*sl 1.06 + 0.025*sl 1.06 + 0.025*sl t phl 1.13 1.08 + 0.024*sl 1.09 + 0.018*sl 1.13 + 0.015*sl t r 0.28 0.18 + 0.052*sl 0.18 + 0.052*sl 0.17 + 0.053*sl t f 0.23 0.18 + 0.027*sl 0.19 + 0.022*sl 0.21 + 0.021*sl sck to qn t plh 0.94 0.89 + 0.024*sl 0.89 + 0.024*sl 0.88 + 0.025*sl t phl 1.14 1.11 + 0.019*sl 1.12 + 0.015*sl 1.14 + 0.013*sl t r 0.25 0.15 + 0.051*sl 0.15 + 0.053*sl 0.13 + 0.054*sl t f 0.19 0.14 + 0.023*sl 0.15 + 0.021*sl 0.15 + 0.020*sl rn to qn t plh 0.79 0.73 + 0.028*sl 0.74 + 0.025*sl 0.74 + 0.024*sl t r 0.28 0.18 + 0.052*sl 0.18 + 0.052*sl 0.17 + 0.053*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-200 sec asic fd2s/fd2sd2 d flip-flop with reset, scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 fd2s fd2sd2 fd2s fd2sd2 d ti te ck rn d ti te ck rn 0.5 0.9 1.7 0.9 1.7 0.5 0.9 1.7 0.9 1.7 10.0 11.0 KGM80 fd2s fd2sd2 fd2s fd2sd2 d ti te ck rn d ti te ck rn 1.0 1.0 2.1 1.0 2.0 1.0 1.0 2.1 1.0 2.0 10.0 11.0 q qn d ti te ck rn ck cl clb q cl clb cl clb cl cl clb qn clb rn rn rn rn d te ti truth table dtiteckrn q (n+1) qn (n+1) 0x0 101 1x0 110 x01 101 x11 110 xxxx001
sec asic 3-201 kg80/KGM80 fd2s/fd2sd2 d flip-flop with reset, scan, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd2s kg80 fd2sd2 parameter symbol kg80 KGM80 fd2s fd2sd2 fd2s fd2sd2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 0.99 input setup time (d to ck) t su 0.47 0.47 0.86 0.86 input hold time (d to ck) t hd 0.15 0.15 0.33 0.33 input setup time (ti to ck) t su 0.53 0.53 0.96 0.96 input hold time (ti to ck) t hd 0.15 0.15 0.33 0.33 input setup time (te to ck) t su 0.58 0.58 0.96 1.02 input hold time (te to ck) t hd 0.15 0.15 0.33 0.33 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ck) t hd 0.42 0.42 0.63 0.63 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.58 0.49 + 0.044*sl 0.50 + 0.042*sl 0.50 + 0.042*sl t phl 0.55 0.49 + 0.032*sl 0.50 + 0.026*sl 0.52 + 0.024*sl t r 0.29 0.12 + 0.087*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.10 + 0.042*sl 0.10 + 0.040*sl 0.09 + 0.041*sl rn to q t phl 0.35 0.28 + 0.033*sl 0.30 + 0.026*sl 0.31 + 0.024*sl t f 0.19 0.11 + 0.040*sl 0.12 + 0.039*sl 0.11 + 0.040*sl ck to qn t plh 0.69 0.61 + 0.041*sl 0.61 + 0.041*sl 0.61 + 0.042*sl t phl 0.66 0.60 + 0.030*sl 0.61 + 0.025*sl 0.63 + 0.023*sl t r 0.26 0.09 + 0.085*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl rn to qn t plh 0.49 0.41 + 0.040*sl 0.41 + 0.041*sl 0.40 + 0.042*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.08 + 0.091*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.57 0.52 + 0.025*sl 0.52 + 0.022*sl 0.53 + 0.021*sl t phl 0.55 0.50 + 0.021*sl 0.52 + 0.016*sl 0.53 + 0.014*sl t r 0.19 0.11 + 0.042*sl 0.11 + 0.043*sl 0.10 + 0.044*sl t f 0.15 0.10 + 0.023*sl 0.11 + 0.020*sl 0.11 + 0.020*sl rn to q t phl 0.33 0.29 + 0.022*sl 0.30 + 0.017*sl 0.32 + 0.014*sl t f 0.16 0.12 + 0.023*sl 0.12 + 0.020*sl 0.13 + 0.019*sl ck to qn t plh 0.72 0.68 + 0.019*sl 0.68 + 0.019*sl 0.68 + 0.020*sl t phl 0.71 0.67 + 0.018*sl 0.68 + 0.015*sl 0.69 + 0.013*sl t r 0.17 0.09 + 0.040*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.11 + 0.019*sl rn to qn t plh 0.51 0.47 + 0.019*sl 0.48 + 0.019*sl 0.47 + 0.020*sl t r 0.17 0.08 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-202 sec asic fd2s/fd2sd2 d flip-flop with reset, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd2s KGM80 fd2sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.81 0.70 + 0.054*sl 0.71 + 0.051*sl 0.72 + 0.050*sl t phl 0.78 0.71 + 0.036*sl 0.73 + 0.027*sl 0.77 + 0.024*sl t r 0.38 0.17 + 0.104*sl 0.16 + 0.107*sl 0.14 + 0.108*sl t f 0.21 0.12 + 0.045*sl 0.13 + 0.041*sl 0.13 + 0.042*sl rn to q t phl 0.45 0.38 + 0.037*sl 0.40 + 0.028*sl 0.44 + 0.024*sl t f 0.23 0.14 + 0.045*sl 0.15 + 0.041*sl 0.14 + 0.041*sl ck to qn t plh 0.98 0.89 + 0.049*sl 0.88 + 0.050*sl 0.88 + 0.050*sl t phl 0.94 0.87 + 0.034*sl 0.89 + 0.026*sl 0.92 + 0.023*sl t r 0.34 0.14 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.041*sl 0.11 + 0.042*sl rn to qn t plh 0.66 0.56 + 0.049*sl 0.56 + 0.050*sl 0.56 + 0.050*sl t r 0.34 0.14 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.79 0.72 + 0.032*sl 0.74 + 0.027*sl 0.75 + 0.025*sl t phl 0.78 0.73 + 0.024*sl 0.75 + 0.017*sl 0.79 + 0.014*sl t r 0.25 0.14 + 0.054*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.17 0.12 + 0.026*sl 0.13 + 0.022*sl 0.15 + 0.021*sl rn to q t phl 0.45 0.39 + 0.026*sl 0.42 + 0.018*sl 0.46 + 0.014*sl t f 0.19 0.13 + 0.027*sl 0.15 + 0.022*sl 0.17 + 0.020*sl ck to qn t plh 1.03 0.98 + 0.025*sl 0.98 + 0.024*sl 0.97 + 0.025*sl t phl 1.01 0.96 + 0.021*sl 0.98 + 0.016*sl 1.01 + 0.013*sl t r 0.22 0.11 + 0.051*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.021*sl 0.14 + 0.020*sl rn to qn t plh 0.70 0.65 + 0.025*sl 0.65 + 0.024*sl 0.64 + 0.025*sl t r 0.22 0.12 + 0.051*sl 0.11 + 0.052*sl 0.09 + 0.054*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-203 kg80/KGM80 fd2q/fd2qd2 d flip-flop with reset, q output only, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 fd2q fd2qd2 fd2q fd2qd2 d ck rn d ck rn 0.8 0.8 1.4 0.8 0.8 1.4 7.0 8.0 KGM80 fd2q fd2qd2 fd2q fd2qd2 d ck rn d ck rn 0.9 0.9 1.6 0.9 0.9 1.6 7.0 8.0 parameter symbol kg80 KGM80 fd2q fd2qd2 fd2q fd2qd2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 0.99 input setup time (d to ck) t su 0.39 0.39 0.71 0.71 input hold time (d to ck) t hd 0.15 0.15 0.33 0.33 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ck) t hd 0.37 0.37 0.63 0.63 d ck q rn d ck cl clb q cl clb cl clb cl cl clb clb rn rn rn rn truth table d ck rn q (n+1) 010 111 xx00 x x q (n)
kg80/KGM80 3-204 sec asic fd2q/fd2qd2 d flip-flop with reset, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd2q kg80 fd2qd2 switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd2q KGM80 fd2qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.56 0.47 + 0.045*sl 0.48 + 0.042*sl 0.48 + 0.042*sl t phl 0.51 0.45 + 0.031*sl 0.46 + 0.026*sl 0.48 + 0.023*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.043*sl 0.09 + 0.040*sl 0.08 + 0.041*sl rn to q t phl 0.34 0.27 + 0.034*sl 0.29 + 0.026*sl 0.31 + 0.024*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.039*sl 0.10 + 0.040*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.55 0.51 + 0.023*sl 0.51 + 0.022*sl 0.52 + 0.021*sl t phl 0.51 0.47 + 0.019*sl 0.48 + 0.015*sl 0.50 + 0.013*sl t r 0.21 0.12 + 0.044*sl 0.12 + 0.042*sl 0.11 + 0.044*sl t f 0.15 0.10 + 0.024*sl 0.11 + 0.020*sl 0.11 + 0.020*sl rn to q t phl 0.34 0.29 + 0.021*sl 0.31 + 0.016*sl 0.33 + 0.013*sl t f 0.17 0.12 + 0.023*sl 0.13 + 0.019*sl 0.13 + 0.019*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.80 0.69 + 0.056*sl 0.70 + 0.050*sl 0.71 + 0.050*sl t phl 0.73 0.65 + 0.036*sl 0.68 + 0.027*sl 0.71 + 0.023*sl t r 0.37 0.16 + 0.105*sl 0.15 + 0.106*sl 0.13 + 0.108*sl t f 0.21 0.12 + 0.045*sl 0.13 + 0.041*sl 0.12 + 0.042*sl rn to q t phl 0.44 0.37 + 0.038*sl 0.40 + 0.027*sl 0.43 + 0.024*sl t f 0.22 0.13 + 0.045*sl 0.14 + 0.041*sl 0.13 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.80 0.74 + 0.030*sl 0.75 + 0.027*sl 0.76 + 0.025*sl t phl 0.74 0.69 + 0.022*sl 0.71 + 0.016*sl 0.74 + 0.013*sl t r 0.28 0.17 + 0.054*sl 0.17 + 0.052*sl 0.16 + 0.053*sl t f 0.18 0.13 + 0.026*sl 0.14 + 0.021*sl 0.15 + 0.020*sl rn to q t phl 0.45 0.40 + 0.023*sl 0.42 + 0.017*sl 0.46 + 0.013*sl t f 0.20 0.15 + 0.027*sl 0.16 + 0.021*sl 0.17 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-205 kg80/KGM80 fd2x2 2-bit d flip-flop with reset logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 pulse width low (ck) t pwl 0.61 1.02 pulse width high (ck) t pwh 0.61 0.99 pulse width low (rn) t pwl 0.61 0.99 input setup time (d0 to ck) t su 0.31 0.58 input hold time (d0 to ck) t hd 0.15 0.33 input setup time (d1 to ck) t su 0.31 0.58 input hold time (d1 to ck) t hd 0.15 0.33 recovery time (rn) t rc 0.15 0.33 q0 qn1 d0 d1 ck q1 qn0 rn truth table cell data dn ck rn qn (n+1) qnn (n+1) 0101 1110 xx0 0 1 x 1 qn (n) qnn (n) input load (sl) gate count kg80 dn ck rn 14.0 1.0 0.9 3.6 KGM80 dn ck rn 14.0 1.0 1.0 4.4
kg80/KGM80 3-206 sec asic fd2x2 2-bit d flip-flop with reset switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd2x2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.62 0.53 + 0.044*sl 0.54 + 0.042*sl 0.54 + 0.042*sl t phl 0.64 0.58 + 0.031*sl 0.59 + 0.026*sl 0.61 + 0.023*sl t r 0.29 0.12 + 0.085*sl 0.11 + 0.089*sl 0.10 + 0.090*sl t f 0.17 0.10 + 0.040*sl 0.09 + 0.040*sl 0.09 + 0.041*sl rn to q0 t phl 0.33 0.27 + 0.032*sl 0.28 + 0.026*sl 0.30 + 0.024*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.039*sl 0.10 + 0.041*sl ck to q1 t plh 0.62 0.53 + 0.044*sl 0.54 + 0.042*sl 0.54 + 0.042*sl t phl 0.64 0.58 + 0.031*sl 0.59 + 0.026*sl 0.61 + 0.023*sl t r 0.29 0.12 + 0.085*sl 0.11 + 0.089*sl 0.10 + 0.090*sl t f 0.17 0.10 + 0.040*sl 0.09 + 0.040*sl 0.09 + 0.041*sl rn to q1 t phl 0.33 0.27 + 0.032*sl 0.28 + 0.026*sl 0.30 + 0.024*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.039*sl 0.10 + 0.041*sl ck to qn0 t plh 0.78 0.70 + 0.040*sl 0.70 + 0.041*sl 0.69 + 0.042*sl t phl 0.70 0.64 + 0.030*sl 0.66 + 0.025*sl 0.67 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.041*sl rn to qn0 t plh 0.48 0.40 + 0.040*sl 0.40 + 0.041*sl 0.39 + 0.042*sl t r 0.26 0.09 + 0.086*sl 0.09 + 0.089*sl 0.07 + 0.091*sl ck to qn1 t plh 0.78 0.70 + 0.040*sl 0.70 + 0.041*sl 0.69 + 0.042*sl t phl 0.70 0.64 + 0.030*sl 0.66 + 0.025*sl 0.67 + 0.024*sl t r 0.26 0.09 + 0.085*sl 0.08 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.041*sl rn to qn1 t plh 0.48 0.40 + 0.040*sl 0.40 + 0.041*sl 0.39 + 0.042*sl t r 0.26 0.09 + 0.086*sl 0.09 + 0.089*sl 0.07 + 0.091*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-207 kg80/KGM80 fd2x2 2-bit d flip-flop with reset switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd2x2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.85 0.75 + 0.054*sl 0.75 + 0.051*sl 0.76 + 0.050*sl t phl 0.90 0.83 + 0.034*sl 0.85 + 0.026*sl 0.88 + 0.023*sl t r 0.38 0.17 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.12 + 0.042*sl rn to q0 t phl 0.43 0.36 + 0.036*sl 0.39 + 0.027*sl 0.42 + 0.024*sl t f 0.22 0.14 + 0.042*sl 0.14 + 0.041*sl 0.13 + 0.042*sl ck to q1 t plh 0.85 0.74 + 0.054*sl 0.75 + 0.051*sl 0.76 + 0.050*sl t phl 0.90 0.83 + 0.034*sl 0.85 + 0.026*sl 0.88 + 0.023*sl t r 0.38 0.17 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.12 + 0.042*sl rn to q1 t phl 0.43 0.36 + 0.036*sl 0.39 + 0.027*sl 0.42 + 0.024*sl t f 0.22 0.14 + 0.042*sl 0.14 + 0.041*sl 0.13 + 0.042*sl ck to qn0 t plh 1.10 1.00 + 0.049*sl 1.00 + 0.049*sl 1.00 + 0.050*sl t phl 0.98 0.92 + 0.034*sl 0.94 + 0.026*sl 0.97 + 0.023*sl t r 0.34 0.14 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.041*sl 0.11 + 0.042*sl rn to qn0 t plh 0.64 0.54 + 0.049*sl 0.54 + 0.050*sl 0.54 + 0.050*sl t r 0.34 0.14 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl ck to qn1 t plh 1.10 1.00 + 0.049*sl 1.00 + 0.050*sl 1.00 + 0.050*sl t phl 0.98 0.92 + 0.033*sl 0.94 + 0.026*sl 0.96 + 0.023*sl t r 0.34 0.14 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl rn to qn1 t plh 0.64 0.54 + 0.049*sl 0.54 + 0.050*sl 0.54 + 0.050*sl t r 0.34 0.14 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-208 sec asic fd2x4 4-bit d flip-flop with reset logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 pulse width low (ck) t pwl 0.80 1.27 pulse width high (ck) t pwh 0.61 0.99 pulse width low (rn) t pwl 0.61 0.99 input setup time (d0 to ck) t su 0.20 0.46 input hold time (d0 to ck) t hd 0.26 0.43 input setup time (d1 to ck) t su 0.20 0.46 input hold time (d1 to ck) t hd 0.26 0.43 input setup time (d2 to ck) t su 0.20 0.46 input hold time (d2 to ck) t hd 0.26 0.43 input setup time (d3 to ck) t su 0.20 0.46 input hold time (d3 to ck) t hd 0.26 0.43 recovery time (rn) t rc 0.15 0.33 d0 d1 d2 d3 ck q0 q1 q2 q3 qn0 qn1 qn2 qn3 rn truth table cell data dn ck rn qn (n+1) qnn (n+1) 0101 1110 xx0 0 1 x 1 qn (n) qnn (n) input load (sl) gate count kg80 dn ck rn 28.0 1.0 0.9 7.5 KGM80 dn ck rn 28.0 1.0 1.1 8.9
sec asic 3-209 kg80/KGM80 fd2x4 4-bit d flip-flop with reset switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load kg80 fd2x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.73 0.64 + 0.043*sl 0.64 + 0.042*sl 0.65 + 0.042*sl t phl 0.84 0.77 + 0.031*sl 0.79 + 0.026*sl 0.80 + 0.024*sl t r 0.29 0.12 + 0.087*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.09 + 0.042*sl 0.10 + 0.040*sl 0.09 + 0.041*sl rn to q0 t phl 0.33 0.27 + 0.032*sl 0.28 + 0.026*sl 0.30 + 0.024*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.039*sl 0.10 + 0.041*sl ck to q1 t plh 0.74 0.65 + 0.044*sl 0.65 + 0.042*sl 0.66 + 0.042*sl t phl 0.84 0.78 + 0.031*sl 0.79 + 0.026*sl 0.81 + 0.023*sl t r 0.29 0.12 + 0.087*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.10 + 0.042*sl 0.10 + 0.039*sl 0.09 + 0.041*sl rn to q1 t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.31 + 0.024*sl t f 0.19 0.11 + 0.039*sl 0.11 + 0.039*sl 0.10 + 0.041*sl ck to q2 t plh 0.74 0.65 + 0.045*sl 0.65 + 0.042*sl 0.66 + 0.042*sl t phl 0.84 0.78 + 0.031*sl 0.79 + 0.026*sl 0.81 + 0.023*sl t r 0.29 0.12 + 0.087*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.10 + 0.042*sl 0.10 + 0.039*sl 0.09 + 0.041*sl rn to q2 t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.30 + 0.024*sl t f 0.19 0.11 + 0.039*sl 0.11 + 0.039*sl 0.10 + 0.040*sl ck to q3 t plh 0.73 0.64 + 0.043*sl 0.64 + 0.042*sl 0.65 + 0.042*sl t phl 0.84 0.77 + 0.031*sl 0.79 + 0.026*sl 0.80 + 0.024*sl t r 0.29 0.12 + 0.087*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.09 + 0.042*sl 0.10 + 0.040*sl 0.09 + 0.041*sl rn to q3 t phl 0.33 0.27 + 0.032*sl 0.28 + 0.026*sl 0.30 + 0.024*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.039*sl 0.10 + 0.041*sl ck to qn0 t plh 0.97 0.89 + 0.040*sl 0.89 + 0.041*sl 0.89 + 0.042*sl t phl 0.81 0.75 + 0.030*sl 0.76 + 0.025*sl 0.77 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.09 + 0.089*sl 0.07 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.041*sl rn to qn0 t plh 0.48 0.40 + 0.040*sl 0.40 + 0.041*sl 0.39 + 0.042*sl t r 0.27 0.09 + 0.086*sl 0.09 + 0.089*sl 0.07 + 0.091*sl ck to qn1 t plh 0.98 0.90 + 0.040*sl 0.90 + 0.041*sl 0.89 + 0.042*sl t phl 0.82 0.76 + 0.030*sl 0.77 + 0.025*sl 0.78 + 0.023*sl t r 0.27 0.10 + 0.085*sl 0.08 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl rn to qn1 t plh 0.48 0.40 + 0.040*sl 0.40 + 0.041*sl 0.39 + 0.042*sl t r 0.27 0.09 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl ck to qn2 t plh 0.98 0.90 + 0.040*sl 0.90 + 0.041*sl 0.90 + 0.041*sl t phl 0.82 0.76 + 0.030*sl 0.77 + 0.025*sl 0.78 + 0.023*sl t r 0.27 0.09 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.041*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-210 sec asic fd2x4 4-bit d flip-flop with reset switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd2x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.97 0.87 + 0.054*sl 0.88 + 0.051*sl 0.88 + 0.050*sl t phl 1.18 1.11 + 0.034*sl 1.13 + 0.027*sl 1.16 + 0.023*sl t r 0.38 0.17 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.108*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.12 + 0.042*sl rn to q0 t phl 0.43 0.36 + 0.035*sl 0.39 + 0.027*sl 0.42 + 0.024*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.041*sl 0.13 + 0.042*sl ck to q1 t plh 0.99 0.88 + 0.054*sl 0.89 + 0.051*sl 0.90 + 0.050*sl t phl 1.19 1.12 + 0.035*sl 1.14 + 0.027*sl 1.17 + 0.023*sl t r 0.38 0.17 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.12 + 0.042*sl rn to q1 t phl 0.44 0.37 + 0.036*sl 0.39 + 0.027*sl 0.42 + 0.024*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.041*sl 0.13 + 0.042*sl ck to q2 t plh 0.99 0.88 + 0.054*sl 0.89 + 0.051*sl 0.90 + 0.050*sl t phl 1.18 1.11 + 0.035*sl 1.14 + 0.027*sl 1.17 + 0.023*sl t r 0.38 0.17 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.12 + 0.042*sl rn to q2 t phl 0.44 0.36 + 0.036*sl 0.39 + 0.027*sl 0.42 + 0.024*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.041*sl 0.13 + 0.042*sl ck to q3 t plh 0.97 0.87 + 0.054*sl 0.88 + 0.051*sl 0.88 + 0.050*sl t phl 1.18 1.11 + 0.034*sl 1.13 + 0.027*sl 1.16 + 0.023*sl t r 0.38 0.17 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.108*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.12 + 0.042*sl rn to q3 t phl 0.43 0.36 + 0.035*sl 0.39 + 0.027*sl 0.42 + 0.024*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.041*sl 0.13 + 0.042*sl ck to qn0 t plh 1.38 1.28 + 0.049*sl 1.28 + 0.050*sl 1.28 + 0.050*sl t phl 1.10 1.04 + 0.033*sl 1.06 + 0.026*sl 1.08 + 0.023*sl t r 0.34 0.14 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.041*sl 0.11 + 0.042*sl rn to qn0 t plh 0.64 0.54 + 0.049*sl 0.54 + 0.050*sl 0.54 + 0.050*sl t r 0.34 0.14 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl ck to qn1 t plh 1.39 1.29 + 0.049*sl 1.29 + 0.050*sl 1.28 + 0.050*sl t phl 1.12 1.05 + 0.033*sl 1.07 + 0.026*sl 1.10 + 0.023*sl t r 0.34 0.14 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.041*sl 0.11 + 0.042*sl rn to qn1 t plh 0.64 0.54 + 0.049*sl 0.54 + 0.050*sl 0.54 + 0.050*sl t r 0.34 0.14 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl ck to qn2 t plh 1.39 1.29 + 0.050*sl 1.29 + 0.050*sl 1.29 + 0.050*sl t phl 1.12 1.05 + 0.033*sl 1.07 + 0.026*sl 1.10 + 0.023*sl t r 0.34 0.14 + 0.104*sl 0.13 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.041*sl 0.11 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-211 kg80/KGM80 yfd2/yfd2d2 fast d flip-flop with reset, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 yfd2 yfd2d2 yfd2 yfd2d2 d ck rn d ck rn 2.9 0.8 1.4 2.9 0.8 2.1 6.0 8.0 KGM80 yfd2 yfd2d2 yfd2 yfd2d2 d ck rn d ck rn 3.7 0.9 1.7 3.7 0.9 2.4 6.0 8.0 parameter symbol kg80 KGM80 yfd2 yfd2d2 yfd2 yfd2d2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 1.02 1.02 input setup time (d to ck) t su 0.26 0.26 0.55 0.52 input hold time (d to ck) t hd 0.26 0.26 0.46 0.46 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ck) t hd 0.15 0.15 0.41 0.41 d ck q qn rn d ck cl clb q cl clb cl clb cl cl clb qn clb rn rn rn rn truth table d ck rn q (n+1) qn (n+1) 0 101 1 110 xx001 x 1 q (n) qn (n)
kg80/KGM80 3-212 sec asic yfd2/yfd2d2 fast d flip-flop with reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 yfd2 kg80 yfd2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.48 0.39 + 0.046*sl 0.40 + 0.043*sl 0.41 + 0.042*sl t phl 0.38 0.32 + 0.033*sl 0.33 + 0.028*sl 0.35 + 0.025*sl t r 0.36 0.19 + 0.086*sl 0.19 + 0.088*sl 0.17 + 0.089*sl t f 0.22 0.13 + 0.044*sl 0.13 + 0.043*sl 0.14 + 0.042*sl rn to q t phl 0.48 0.41 + 0.040*sl 0.43 + 0.029*sl 0.46 + 0.025*sl t f 0.26 0.17 + 0.042*sl 0.18 + 0.040*sl 0.18 + 0.039*sl ck to qn t plh 0.58 0.41 + 0.085*sl 0.43 + 0.080*sl 0.45 + 0.077*sl t phl 0.67 0.48 + 0.092*sl 0.49 + 0.090*sl 0.49 + 0.089*sl t r 0.35 0.16 + 0.094*sl 0.16 + 0.094*sl 0.16 + 0.095*sl t f 0.31 0.14 + 0.086*sl 0.14 + 0.086*sl 0.14 + 0.086*sl rn to qn t plh 0.28 0.20 + 0.041*sl 0.20 + 0.041*sl 0.22 + 0.039*sl t r 0.42 0.29 + 0.064*sl 0.31 + 0.056*sl 0.31 + 0.055*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.48 0.43 + 0.025*sl 0.44 + 0.023*sl 0.44 + 0.022*sl t phl 0.38 0.34 + 0.019*sl 0.35 + 0.016*sl 0.36 + 0.015*sl t r 0.30 0.22 + 0.040*sl 0.22 + 0.042*sl 0.20 + 0.044*sl t f 0.20 0.15 + 0.023*sl 0.15 + 0.022*sl 0.16 + 0.021*sl rn to q t phl 0.48 0.43 + 0.024*sl 0.44 + 0.019*sl 0.47 + 0.015*sl t f 0.23 0.19 + 0.023*sl 0.19 + 0.020*sl 0.19 + 0.021*sl ck to qn t plh 0.52 0.43 + 0.047*sl 0.44 + 0.043*sl 0.46 + 0.041*sl t phl 0.60 0.51 + 0.048*sl 0.51 + 0.046*sl 0.52 + 0.045*sl t r 0.23 0.14 + 0.047*sl 0.14 + 0.047*sl 0.13 + 0.048*sl t f 0.21 0.12 + 0.042*sl 0.12 + 0.043*sl 0.12 + 0.043*sl rn to qn t plh 0.23 0.19 + 0.022*sl 0.19 + 0.020*sl 0.19 + 0.021*sl t r 0.33 0.26 + 0.036*sl 0.27 + 0.034*sl 0.30 + 0.029*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-213 kg80/KGM80 yfd2/yfd2d2 fast d flip-flop with reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 yfd2 KGM80 yfd2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.68 0.56 + 0.057*sl 0.58 + 0.051*sl 0.59 + 0.050*sl t phl 0.54 0.47 + 0.038*sl 0.49 + 0.029*sl 0.53 + 0.025*sl t r 0.47 0.27 + 0.105*sl 0.26 + 0.106*sl 0.24 + 0.108*sl t f 0.27 0.18 + 0.049*sl 0.19 + 0.044*sl 0.21 + 0.042*sl rn to q t phl 0.68 0.58 + 0.048*sl 0.63 + 0.031*sl 0.70 + 0.025*sl t f 0.33 0.23 + 0.047*sl 0.25 + 0.041*sl 0.26 + 0.040*sl ck to qn t plh 0.82 0.62 + 0.100*sl 0.64 + 0.091*sl 0.69 + 0.087*sl t phl 0.93 0.70 + 0.113*sl 0.71 + 0.108*sl 0.72 + 0.107*sl t r 0.47 0.25 + 0.112*sl 0.25 + 0.112*sl 0.25 + 0.112*sl t f 0.39 0.20 + 0.093*sl 0.20 + 0.094*sl 0.19 + 0.095*sl rn to qn t plh 0.36 0.26 + 0.050*sl 0.26 + 0.050*sl 0.31 + 0.046*sl t r 0.55 0.37 + 0.092*sl 0.43 + 0.070*sl 0.46 + 0.067*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.67 0.61 + 0.031*sl 0.62 + 0.027*sl 0.64 + 0.026*sl t phl 0.56 0.51 + 0.023*sl 0.52 + 0.018*sl 0.56 + 0.015*sl t r 0.40 0.30 + 0.050*sl 0.29 + 0.051*sl 0.28 + 0.052*sl t f 0.26 0.21 + 0.026*sl 0.21 + 0.024*sl 0.24 + 0.021*sl rn to q t phl 0.68 0.62 + 0.030*sl 0.64 + 0.021*sl 0.71 + 0.015*sl t f 0.31 0.26 + 0.024*sl 0.27 + 0.021*sl 0.29 + 0.020*sl ck to qn t plh 0.76 0.65 + 0.055*sl 0.66 + 0.050*sl 0.70 + 0.046*sl t phl 0.84 0.73 + 0.058*sl 0.73 + 0.055*sl 0.75 + 0.054*sl t r 0.32 0.21 + 0.056*sl 0.21 + 0.056*sl 0.21 + 0.056*sl t f 0.26 0.17 + 0.045*sl 0.17 + 0.046*sl 0.16 + 0.047*sl rn to qn t plh 0.29 0.24 + 0.026*sl 0.24 + 0.025*sl 0.24 + 0.025*sl t r 0.42 0.32 + 0.050*sl 0.33 + 0.044*sl 0.44 + 0.035*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-214 sec asic fd2t/fd2td2 d flip-flop with reset, tri-state output, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) output load (sl) gate count kg80 fd2t fd2td2 fd2t fd2td2 fd2t fd2td2 d rd ck rn d rd ck rn z z 0.9 1.4 0.9 1.7 0.9 2.0 0.9 1.7 0.7 1.4 10.0 13.0 KGM80 fd2t fd2td2 fd2t fd2td2 fd2t fd2td2 d rd ck rn d rd ck rn z z 1.1 1.7 1.0 2.0 1.1 2.6 1.0 2.0 0.9 1.8 10.0 13.0 parameter symbol kg80 KGM80 fd2t fd2td2 fd2t fd2td2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.64 1.02 1.05 input setup time (d to ck) t su 0.37 0.37 0.64 0.64 input hold time (d to ck) t hd 0.15 0.15 0.33 0.33 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ck) t hd 0.37 0.37 0.63 0.63 d ck rd q z rn q z d ck cl clb cl clb cl clb cl cl clb clb rn rn rn rn rd truth table * rd is a tri-state enable pin. d rd* ck rn q (n+1) z (n+1) 01 100 11 111 x1x000 x 0 x 1 x hi-z x 1 1 q (n) z (n)
sec asic 3-215 kg80/KGM80 fd2t/fd2td2 d flip-flop with reset, tri-state output, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd2t kg80 fd2td2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.68 0.58 + 0.053*sl 0.58 + 0.052*sl 0.60 + 0.049*sl t phl 0.63 0.56 + 0.038*sl 0.57 + 0.032*sl 0.60 + 0.028*sl t r 0.41 0.20 + 0.103*sl 0.18 + 0.110*sl 0.21 + 0.105*sl t f 0.25 0.15 + 0.048*sl 0.15 + 0.049*sl 0.16 + 0.048*sl rn to q t phl 0.45 0.37 + 0.038*sl 0.39 + 0.032*sl 0.42 + 0.027*sl t f 0.27 0.18 + 0.045*sl 0.17 + 0.047*sl 0.17 + 0.047*sl ck to z t plh 0.93 0.75 + 0.088*sl 0.77 + 0.081*sl 0.83 + 0.072*sl t phl 0.87 0.72 + 0.074*sl 0.74 + 0.066*sl 0.78 + 0.059*sl t r 0.22 0.11 + 0.053*sl 0.10 + 0.057*sl 0.12 + 0.054*sl t f 0.48 0.28 + 0.099*sl 0.27 + 0.103*sl 0.31 + 0.097*sl rn to z t phl 0.69 0.54 + 0.074*sl 0.56 + 0.065*sl 0.60 + 0.059*sl t f 0.48 0.28 + 0.098*sl 0.27 + 0.102*sl 0.31 + 0.097*sl rd to z t plh 0.24 0.17 + 0.035*sl 0.19 + 0.028*sl 0.21 + 0.025*sl t phl 0.13 -0.01 + 0.069*sl 0.04 + 0.048*sl 0.10 + 0.040*sl t r 0.24 0.16 + 0.042*sl 0.14 + 0.050*sl 0.14 + 0.051*sl t f 0.34 0.18 + 0.081*sl 0.20 + 0.076*sl 0.20 + 0.075*sl t plz 0.25 0.25 + 0.000*sl 0.25 + 0.000*sl 0.25 + 0.000*sl t phz 0.38 0.38 + 0.000*sl 0.38 + 0.000*sl 0.38 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.69 0.63 + 0.030*sl 0.63 + 0.028*sl 0.66 + 0.025*sl t phl 0.64 0.59 + 0.026*sl 0.60 + 0.021*sl 0.63 + 0.016*sl t r 0.27 0.17 + 0.052*sl 0.17 + 0.052*sl 0.18 + 0.051*sl t f 0.21 0.16 + 0.026*sl 0.16 + 0.025*sl 0.18 + 0.023*sl rn to q t phl 0.46 0.40 + 0.026*sl 0.42 + 0.020*sl 0.45 + 0.015*sl t f 0.23 0.18 + 0.025*sl 0.18 + 0.023*sl 0.20 + 0.021*sl ck to z t plh 0.95 0.84 + 0.053*sl 0.86 + 0.047*sl 0.91 + 0.040*sl t phl 0.90 0.81 + 0.046*sl 0.82 + 0.040*sl 0.87 + 0.033*sl t r 0.19 0.13 + 0.030*sl 0.14 + 0.028*sl 0.15 + 0.026*sl t f 0.44 0.34 + 0.052*sl 0.34 + 0.052*sl 0.36 + 0.049*sl rn to z t phl 0.71 0.62 + 0.045*sl 0.64 + 0.039*sl 0.68 + 0.032*sl t f 0.44 0.33 + 0.052*sl 0.34 + 0.051*sl 0.36 + 0.048*sl rd to z t plh 0.27 0.22 + 0.025*sl 0.24 + 0.019*sl 0.27 + 0.014*sl t phl 0.06 -0.02 + 0.042*sl 0.01 + 0.031*sl 0.07 + 0.022*sl t r 0.25 0.22 + 0.014*sl 0.20 + 0.022*sl 0.19 + 0.023*sl t f 0.27 0.17 + 0.047*sl 0.19 + 0.039*sl 0.21 + 0.036*sl t plz 0.25 0.25 + 0.000*sl 0.25 + 0.000*sl 0.25 + 0.000*sl t phz 0.54 0.54 + 0.001*sl 0.54 + 0.000*sl 0.54 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-216 sec asic fd2t/fd2td2 d flip-flop with reset, tri-state output, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd2t KGM80 fd2td2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.91 0.81 + 0.054*sl 0.82 + 0.050*sl 0.82 + 0.050*sl t phl 0.86 0.79 + 0.036*sl 0.81 + 0.027*sl 0.85 + 0.024*sl t r 0.49 0.28 + 0.103*sl 0.27 + 0.106*sl 0.25 + 0.108*sl t f 0.28 0.19 + 0.043*sl 0.20 + 0.041*sl 0.20 + 0.041*sl rn to q t phl 0.54 0.47 + 0.037*sl 0.49 + 0.028*sl 0.54 + 0.024*sl t f 0.30 0.21 + 0.044*sl 0.22 + 0.040*sl 0.21 + 0.041*sl ck to z t plh 1.25 1.07 + 0.091*sl 1.10 + 0.080*sl 1.16 + 0.075*sl t phl 1.13 1.00 + 0.068*sl 1.03 + 0.055*sl 1.07 + 0.051*sl t r 0.25 0.15 + 0.054*sl 0.15 + 0.053*sl 0.13 + 0.055*sl t f 0.53 0.35 + 0.088*sl 0.36 + 0.086*sl 0.36 + 0.086*sl rn to z t phl 0.81 0.68 + 0.068*sl 0.71 + 0.055*sl 0.75 + 0.051*sl t f 0.53 0.36 + 0.087*sl 0.36 + 0.086*sl 0.36 + 0.086*sl rd to z t plh 0.31 0.25 + 0.033*sl 0.26 + 0.026*sl 0.28 + 0.025*sl t phl 0.16 0.05 + 0.052*sl 0.09 + 0.038*sl 0.11 + 0.037*sl t r 0.29 0.23 + 0.029*sl 0.17 + 0.050*sl 0.14 + 0.053*sl t f 0.32 0.18 + 0.070*sl 0.18 + 0.069*sl 0.14 + 0.073*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.47 0.47 + 0.000*sl 0.47 + 0.000*sl 0.47 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.92 0.86 + 0.032*sl 0.87 + 0.028*sl 0.90 + 0.025*sl t phl 0.90 0.84 + 0.026*sl 0.86 + 0.019*sl 0.91 + 0.015*sl t r 0.33 0.22 + 0.054*sl 0.22 + 0.052*sl 0.22 + 0.052*sl t f 0.24 0.19 + 0.027*sl 0.20 + 0.022*sl 0.22 + 0.020*sl rn to q t phl 0.57 0.51 + 0.027*sl 0.53 + 0.019*sl 0.59 + 0.014*sl t f 0.26 0.21 + 0.025*sl 0.22 + 0.021*sl 0.24 + 0.019*sl ck to z t plh 1.31 1.19 + 0.057*sl 1.22 + 0.047*sl 1.28 + 0.042*sl t phl 1.20 1.12 + 0.043*sl 1.14 + 0.034*sl 1.20 + 0.029*sl t r 0.23 0.18 + 0.027*sl 0.18 + 0.026*sl 0.18 + 0.027*sl t f 0.51 0.41 + 0.048*sl 0.42 + 0.045*sl 0.43 + 0.044*sl rn to z t phl 0.88 0.79 + 0.042*sl 0.81 + 0.034*sl 0.88 + 0.028*sl t f 0.50 0.40 + 0.049*sl 0.42 + 0.044*sl 0.43 + 0.043*sl rd to z t plh 0.37 0.32 + 0.023*sl 0.34 + 0.016*sl 0.37 + 0.013*sl t phl 0.11 0.05 + 0.030*sl 0.07 + 0.022*sl 0.11 + 0.018*sl t r 0.33 0.30 + 0.016*sl 0.29 + 0.018*sl 0.22 + 0.025*sl t f 0.25 0.17 + 0.039*sl 0.19 + 0.033*sl 0.17 + 0.035*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.69 0.69 + 0.000*sl 0.69 + 0.000*sl 0.69 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-217 kg80/KGM80 fd2tcs/fd2tcsd2 d flip-flop with reset, scan clock, tri-state output, 1x/2x drive logic symbol cell data schematic diagram input load (sl) output load (sl) gate count kg80 fd2tcs fd2tcsd2 fd2tcs fd2tcs d2 fd2tcs fd2tcs d2 si sck d rd ck rn si sck d rd ck rn z z 0.8 2.1 0.9 1.6 0.9 2.9 0.8 2.5 0.9 2.4 0.9 3.0 0.9 1.5 15.0 17.0 KGM80 fd2tcs fd2tcsd2 fd2tcs fd2tcs d2 fd2tcs fd2tcs d2 si sck d rd ck rn si sck d rd ck rn z z 1.0 2.9 1.0 1.9 1.0 3.4 1.0 2.9 1.0 2.8 1.0 3.6 1.3 2.0 15.0 17.0 q z si rd ck sck d rn d cl clb cl clb cl cl clb clb sck sckb sck sckb sckb sck sckb sck si rn rn rn cl clb sck sck sckb ck rn rn q z rd truth table * rd is a tri-state enable pin. si sck d rd ck rn q (n+1) z (n+1) x001 100 x011 111 0 x10100 1 x10111 xxx1x000 x x x 0 x 1 x hi-z
kg80/KGM80 3-218 sec asic fd2tcs/fd2tcsd2 d flip-flop with reset, scan clock, tri-state output, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd2tcs parameter symbol kg80 KGM80 fd2tcs fd2tcsd2 fd2tcs fd2tcsd2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (sck) t pwl 0.61 0.61 0.99 0.99 pulse width high (sck) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 1.02 input setup time (d to ck) t su 0.37 0.37 0.64 0.64 input hold time (d to ck) t hd 0.15 0.15 0.33 0.33 input setup time (si to sck) t su 0.56 0.56 0.96 0.96 input hold time (si to sck) t hd 0.15 0.15 0.33 0.33 recovery time (rn to ck) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ck) t hd 0.42 0.42 0.63 0.63 recovery time (rn to sck) t rc 0.15 0.15 0.33 0.33 input hold time (rn to sck) t hd 0.26 0.26 0.63 0.63 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.65 0.56 + 0.044*sl 0.56 + 0.042*sl 0.57 + 0.042*sl t phl 0.60 0.53 + 0.031*sl 0.55 + 0.026*sl 0.56 + 0.024*sl t r 0.38 0.19 + 0.094*sl 0.21 + 0.087*sl 0.20 + 0.089*sl t f 0.22 0.14 + 0.040*sl 0.14 + 0.040*sl 0.14 + 0.040*sl sck to q t plh 0.72 0.63 + 0.045*sl 0.63 + 0.042*sl 0.64 + 0.041*sl t phl 0.54 0.48 + 0.033*sl 0.49 + 0.026*sl 0.51 + 0.024*sl t r 0.39 0.21 + 0.091*sl 0.22 + 0.086*sl 0.21 + 0.089*sl t f 0.23 0.15 + 0.039*sl 0.15 + 0.039*sl 0.14 + 0.040*sl rn to q t phl 0.39 0.33 + 0.032*sl 0.34 + 0.026*sl 0.36 + 0.024*sl t f 0.24 0.16 + 0.040*sl 0.16 + 0.039*sl 0.15 + 0.041*sl ck to z t plh 0.90 0.74 + 0.077*sl 0.76 + 0.069*sl 0.79 + 0.065*sl t phl 0.82 0.70 + 0.060*sl 0.71 + 0.052*sl 0.73 + 0.050*sl t r 0.21 0.12 + 0.045*sl 0.13 + 0.044*sl 0.12 + 0.046*sl t f 0.43 0.26 + 0.083*sl 0.26 + 0.082*sl 0.26 + 0.082*sl sck to z t plh 0.96 0.81 + 0.077*sl 0.83 + 0.069*sl 0.86 + 0.065*sl t phl 0.76 0.64 + 0.060*sl 0.66 + 0.052*sl 0.68 + 0.050*sl t r 0.21 0.13 + 0.043*sl 0.12 + 0.045*sl 0.12 + 0.046*sl t f 0.43 0.26 + 0.083*sl 0.27 + 0.082*sl 0.27 + 0.082*sl rn to z t phl 0.61 0.49 + 0.060*sl 0.51 + 0.052*sl 0.53 + 0.050*sl t f 0.43 0.26 + 0.084*sl 0.27 + 0.082*sl 0.27 + 0.082*sl rd to z t plh 0.22 0.16 + 0.029*sl 0.18 + 0.023*sl 0.19 + 0.021*sl t phl 0.13 0.03 + 0.050*sl 0.06 + 0.037*sl 0.08 + 0.034*sl t r 0.23 0.17 + 0.035*sl 0.15 + 0.040*sl 0.13 + 0.043*sl t f 0.31 0.18 + 0.063*sl 0.18 + 0.061*sl 0.16 + 0.065*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.40 0.40 + -0.001*sl 0.40 + 0.000*sl 0.40 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-219 kg80/KGM80 fd2tcs/fd2tcsd2 d flip-flop with reset, scan clock, tri-state output, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd2tcsd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.67 0.62 + 0.026*sl 0.63 + 0.022*sl 0.64 + 0.021*sl t phl 0.63 0.58 + 0.023*sl 0.60 + 0.017*sl 0.62 + 0.015*sl t r 0.25 0.17 + 0.042*sl 0.16 + 0.044*sl 0.17 + 0.044*sl t f 0.20 0.16 + 0.023*sl 0.16 + 0.020*sl 0.17 + 0.020*sl sck to q t plh 0.76 0.71 + 0.026*sl 0.71 + 0.023*sl 0.73 + 0.021*sl t phl 0.58 0.53 + 0.023*sl 0.54 + 0.018*sl 0.57 + 0.015*sl t r 0.27 0.18 + 0.043*sl 0.18 + 0.043*sl 0.18 + 0.043*sl t f 0.21 0.16 + 0.023*sl 0.17 + 0.020*sl 0.18 + 0.019*sl rn to q t phl 0.42 0.37 + 0.023*sl 0.38 + 0.018*sl 0.41 + 0.014*sl t f 0.21 0.17 + 0.022*sl 0.18 + 0.019*sl 0.18 + 0.018*sl ck to z t plh 0.93 0.84 + 0.047*sl 0.85 + 0.041*sl 0.88 + 0.037*sl t phl 0.87 0.79 + 0.037*sl 0.80 + 0.032*sl 0.83 + 0.028*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.022*sl 0.15 + 0.022*sl t f 0.39 0.30 + 0.044*sl 0.30 + 0.042*sl 0.30 + 0.042*sl sck to z t plh 1.02 0.92 + 0.048*sl 0.94 + 0.041*sl 0.97 + 0.036*sl t phl 0.82 0.74 + 0.038*sl 0.75 + 0.032*sl 0.78 + 0.028*sl t r 0.19 0.14 + 0.023*sl 0.14 + 0.022*sl 0.15 + 0.022*sl t f 0.39 0.30 + 0.045*sl 0.30 + 0.042*sl 0.31 + 0.042*sl rn to z t phl 0.65 0.58 + 0.037*sl 0.59 + 0.031*sl 0.62 + 0.027*sl t f 0.38 0.29 + 0.043*sl 0.30 + 0.041*sl 0.30 + 0.041*sl rd to z t plh 0.24 0.20 + 0.018*sl 0.21 + 0.015*sl 0.23 + 0.012*sl t phl 0.07 0.01 + 0.031*sl 0.03 + 0.023*sl 0.06 + 0.018*sl t r 0.23 0.20 + 0.014*sl 0.19 + 0.018*sl 0.18 + 0.020*sl t f 0.23 0.15 + 0.038*sl 0.17 + 0.031*sl 0.17 + 0.031*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.53 0.53 + -0.001*sl 0.53 + 0.000*sl 0.53 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-220 sec asic fd2tcs/fd2tcsd2 d flip-flop with reset, scan clock, tri-state output, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd2tcs path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.90 0.79 + 0.054*sl 0.80 + 0.051*sl 0.81 + 0.050*sl t phl 0.84 0.77 + 0.035*sl 0.79 + 0.027*sl 0.83 + 0.024*sl t r 0.50 0.27 + 0.114*sl 0.29 + 0.106*sl 0.27 + 0.108*sl t f 0.26 0.18 + 0.043*sl 0.18 + 0.041*sl 0.18 + 0.042*sl sck to q t plh 1.04 0.93 + 0.055*sl 0.94 + 0.051*sl 0.95 + 0.050*sl t phl 0.76 0.69 + 0.036*sl 0.71 + 0.027*sl 0.75 + 0.024*sl t r 0.52 0.29 + 0.111*sl 0.31 + 0.105*sl 0.28 + 0.108*sl t f 0.27 0.19 + 0.043*sl 0.20 + 0.040*sl 0.19 + 0.041*sl rn to q t phl 0.52 0.45 + 0.036*sl 0.47 + 0.028*sl 0.51 + 0.024*sl t f 0.28 0.20 + 0.043*sl 0.20 + 0.041*sl 0.20 + 0.042*sl ck to z t plh 1.26 1.07 + 0.095*sl 1.10 + 0.083*sl 1.16 + 0.078*sl t phl 1.11 0.98 + 0.064*sl 1.01 + 0.054*sl 1.04 + 0.051*sl t r 0.28 0.17 + 0.053*sl 0.17 + 0.053*sl 0.16 + 0.054*sl t f 0.51 0.33 + 0.090*sl 0.34 + 0.087*sl 0.35 + 0.086*sl sck to z t plh 1.40 1.21 + 0.095*sl 1.25 + 0.083*sl 1.30 + 0.078*sl t phl 1.03 0.90 + 0.064*sl 0.93 + 0.054*sl 0.96 + 0.051*sl t r 0.28 0.17 + 0.053*sl 0.17 + 0.053*sl 0.16 + 0.054*sl t f 0.51 0.33 + 0.091*sl 0.34 + 0.086*sl 0.35 + 0.085*sl rn to z t phl 0.78 0.65 + 0.064*sl 0.68 + 0.054*sl 0.72 + 0.051*sl t f 0.51 0.33 + 0.089*sl 0.34 + 0.087*sl 0.35 + 0.085*sl rd to z t plh 0.32 0.26 + 0.031*sl 0.27 + 0.026*sl 0.28 + 0.025*sl t phl 0.18 0.09 + 0.048*sl 0.11 + 0.038*sl 0.12 + 0.037*sl t r 0.31 0.26 + 0.027*sl 0.19 + 0.050*sl 0.16 + 0.053*sl t f 0.34 0.21 + 0.068*sl 0.20 + 0.069*sl 0.17 + 0.073*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.53 0.53 + 0.000*sl 0.53 + 0.000*sl 0.53 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-221 kg80/KGM80 fd2tcs/fd2tcsd2 d flip-flop with reset, scan clock, tri-state output, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd2tcsd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.93 0.86 + 0.032*sl 0.88 + 0.028*sl 0.90 + 0.025*sl t phl 0.90 0.84 + 0.026*sl 0.86 + 0.019*sl 0.91 + 0.015*sl t r 0.32 0.22 + 0.055*sl 0.22 + 0.054*sl 0.23 + 0.053*sl t f 0.24 0.19 + 0.026*sl 0.20 + 0.022*sl 0.22 + 0.020*sl sck to q t plh 1.10 1.03 + 0.032*sl 1.05 + 0.028*sl 1.07 + 0.025*sl t phl 0.82 0.77 + 0.027*sl 0.79 + 0.020*sl 0.84 + 0.015*sl t r 0.34 0.23 + 0.055*sl 0.24 + 0.053*sl 0.25 + 0.052*sl t f 0.25 0.20 + 0.025*sl 0.21 + 0.022*sl 0.23 + 0.020*sl rn to q t phl 0.56 0.51 + 0.027*sl 0.53 + 0.019*sl 0.58 + 0.014*sl t f 0.26 0.20 + 0.026*sl 0.22 + 0.021*sl 0.24 + 0.019*sl ck to z t plh 1.31 1.19 + 0.060*sl 1.22 + 0.049*sl 1.29 + 0.043*sl t phl 1.19 1.11 + 0.042*sl 1.13 + 0.033*sl 1.19 + 0.028*sl t r 0.24 0.19 + 0.027*sl 0.19 + 0.027*sl 0.19 + 0.027*sl t f 0.46 0.36 + 0.049*sl 0.37 + 0.046*sl 0.39 + 0.044*sl sck to z t plh 1.48 1.36 + 0.061*sl 1.39 + 0.049*sl 1.46 + 0.043*sl t phl 1.12 1.04 + 0.042*sl 1.06 + 0.033*sl 1.12 + 0.028*sl t r 0.25 0.19 + 0.026*sl 0.19 + 0.027*sl 0.19 + 0.027*sl t f 0.46 0.36 + 0.050*sl 0.37 + 0.046*sl 0.39 + 0.044*sl rn to z t phl 0.86 0.78 + 0.041*sl 0.80 + 0.033*sl 0.86 + 0.028*sl t f 0.45 0.35 + 0.050*sl 0.37 + 0.045*sl 0.38 + 0.043*sl rd to z t plh 0.35 0.31 + 0.021*sl 0.33 + 0.016*sl 0.35 + 0.013*sl t phl 0.11 0.06 + 0.029*sl 0.08 + 0.022*sl 0.11 + 0.019*sl t r 0.30 0.30 + 0.000*sl 0.24 + 0.023*sl 0.22 + 0.025*sl t f 0.25 0.18 + 0.039*sl 0.19 + 0.034*sl 0.18 + 0.035*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.70 0.70 + 0.000*sl 0.70 + 0.000*sl 0.70 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-222 sec asic fd2ts/fd2tsd2 d flip-flop with reset, scan, tri-state output, 1x/2x drive logic symbol cell data schematic diagram input load (sl) output load (sl) gate count kg80 fd2ts fd2tsd2 fd2ts fd2tsd2 fd2ts fd2tsd2 drdti teckrn d rd ti teckrn z z 0.9 1.3 0.8 1.7 0.9 1.7 0.9 2.2 0.8 1.7 0.9 1.7 0.7 1.2 12.0 15.0 KGM80 fd2ts fd2tsd2 fd2ts fd2tsd2 fd2ts fd2tsd2 drdti teckrn d rd ti teckrn z z 1.0 1.7 0.9 2.0 1.0 2.0 1.0 2.6 0.9 2.0 1.0 2.0 0.9 1.6 12.0 15.0 q z d te ck rd ti rn ck cl clb cl clb cl clb cl cl clb clb rn rn rn rn d te ti q z rd truth table * rd is a tri-state enable pin. drdtiteckrn q (n+1) z (n+1) 01x0 100 11x0 111 x101 100 x111 111 x1xxx000 x 0 x x x 1 x hi-z x 1 x x 1 q (n) z (n)
sec asic 3-223 kg80/KGM80 fd2ts/fd2tsd2 d flip-flop with reset, scan, tri-state output, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 fd2ts fd2tsd2 fd2ts fd2tsd2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.64 0.99 1.05 input setup time (d to ck) t su 0.47 0.47 0.86 0.86 input hold time (d to ck) t hd 0.15 0.15 0.33 0.33 input setup time (ti to ck) t su 0.50 0.50 0.93 0.93 input hold time (ti to ck) t hd 0.15 0.15 0.33 0.33 input setup time (te to ck) t su 0.15 0.15 0.33 0.33 input hold time (te to ck) t hd 0.15 0.15 0.33 0.33 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ck) t hd 0.42 0.42 0.63 0.63
kg80/KGM80 3-224 sec asic fd2ts/fd2tsd2 d flip-flop with reset, scan, tri-state output, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd2ts kg80 fd2tsd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.66 0.57 + 0.045*sl 0.58 + 0.042*sl 0.58 + 0.041*sl t phl 0.62 0.55 + 0.032*sl 0.57 + 0.026*sl 0.58 + 0.024*sl t r 0.37 0.20 + 0.084*sl 0.19 + 0.087*sl 0.18 + 0.089*sl t f 0.23 0.15 + 0.041*sl 0.16 + 0.039*sl 0.15 + 0.041*sl rn to q t phl 0.41 0.34 + 0.033*sl 0.36 + 0.027*sl 0.38 + 0.023*sl t f 0.25 0.17 + 0.040*sl 0.17 + 0.038*sl 0.16 + 0.039*sl ck to z t plh 0.89 0.74 + 0.075*sl 0.77 + 0.066*sl 0.79 + 0.063*sl t phl 0.84 0.72 + 0.062*sl 0.74 + 0.054*sl 0.76 + 0.051*sl t r 0.20 0.11 + 0.044*sl 0.11 + 0.045*sl 0.10 + 0.046*sl t f 0.44 0.28 + 0.082*sl 0.28 + 0.083*sl 0.28 + 0.083*sl rn to z t phl 0.63 0.51 + 0.063*sl 0.53 + 0.053*sl 0.55 + 0.051*sl t f 0.44 0.28 + 0.082*sl 0.28 + 0.082*sl 0.28 + 0.082*sl rd to z t plh 0.22 0.16 + 0.030*sl 0.18 + 0.023*sl 0.20 + 0.021*sl t phl 0.12 0.01 + 0.054*sl 0.05 + 0.036*sl 0.05 + 0.036*sl t r 0.22 0.16 + 0.031*sl 0.14 + 0.040*sl 0.12 + 0.043*sl t f 0.29 0.16 + 0.066*sl 0.17 + 0.062*sl 0.16 + 0.064*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.36 0.36 + 0.001*sl 0.36 + 0.000*sl 0.36 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.67 0.62 + 0.025*sl 0.63 + 0.023*sl 0.64 + 0.021*sl t phl 0.63 0.59 + 0.022*sl 0.60 + 0.018*sl 0.62 + 0.015*sl t r 0.26 0.17 + 0.043*sl 0.17 + 0.042*sl 0.17 + 0.043*sl t f 0.20 0.16 + 0.023*sl 0.16 + 0.021*sl 0.17 + 0.020*sl rn to q t phl 0.42 0.37 + 0.023*sl 0.38 + 0.018*sl 0.41 + 0.014*sl t f 0.22 0.17 + 0.022*sl 0.18 + 0.018*sl 0.18 + 0.018*sl ck to z t plh 0.93 0.84 + 0.045*sl 0.85 + 0.039*sl 0.88 + 0.035*sl t phl 0.88 0.80 + 0.039*sl 0.82 + 0.033*sl 0.85 + 0.029*sl t r 0.18 0.13 + 0.024*sl 0.14 + 0.023*sl 0.14 + 0.022*sl t f 0.42 0.33 + 0.043*sl 0.34 + 0.041*sl 0.34 + 0.041*sl rn to z t phl 0.66 0.59 + 0.038*sl 0.60 + 0.032*sl 0.63 + 0.028*sl t f 0.41 0.33 + 0.043*sl 0.33 + 0.040*sl 0.33 + 0.041*sl rd to z t plh 0.25 0.21 + 0.021*sl 0.22 + 0.016*sl 0.25 + 0.013*sl t phl 0.06 -0.01 + 0.033*sl 0.01 + 0.024*sl 0.05 + 0.018*sl t r 0.23 0.21 + 0.012*sl 0.20 + 0.017*sl 0.18 + 0.019*sl t f 0.22 0.14 + 0.039*sl 0.16 + 0.031*sl 0.16 + 0.031*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.51 0.51 + 0.000*sl 0.51 + 0.000*sl 0.51 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-225 kg80/KGM80 fd2ts/fd2tsd2 d flip-flop with reset, scan, tri-state output, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd2ts KGM80 fd2tsd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.92 0.81 + 0.054*sl 0.82 + 0.050*sl 0.83 + 0.050*sl t phl 0.87 0.80 + 0.036*sl 0.82 + 0.027*sl 0.86 + 0.024*sl t r 0.49 0.28 + 0.103*sl 0.27 + 0.106*sl 0.25 + 0.108*sl t f 0.28 0.19 + 0.044*sl 0.20 + 0.041*sl 0.20 + 0.041*sl rn to q t phl 0.54 0.47 + 0.037*sl 0.49 + 0.028*sl 0.54 + 0.024*sl t f 0.30 0.21 + 0.044*sl 0.22 + 0.040*sl 0.21 + 0.041*sl ck to z t plh 1.26 1.08 + 0.092*sl 1.11 + 0.080*sl 1.16 + 0.075*sl t phl 1.14 1.00 + 0.068*sl 1.04 + 0.055*sl 1.08 + 0.051*sl t r 0.25 0.15 + 0.053*sl 0.15 + 0.053*sl 0.13 + 0.055*sl t f 0.53 0.35 + 0.088*sl 0.36 + 0.086*sl 0.36 + 0.086*sl rn to z t phl 0.81 0.67 + 0.068*sl 0.71 + 0.055*sl 0.75 + 0.051*sl t f 0.53 0.36 + 0.087*sl 0.36 + 0.086*sl 0.37 + 0.086*sl rd to z t plh 0.31 0.25 + 0.033*sl 0.26 + 0.026*sl 0.28 + 0.025*sl t phl 0.16 0.05 + 0.052*sl 0.09 + 0.038*sl 0.11 + 0.037*sl t r 0.29 0.23 + 0.029*sl 0.17 + 0.050*sl 0.14 + 0.053*sl t f 0.32 0.18 + 0.069*sl 0.18 + 0.069*sl 0.14 + 0.073*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.47 0.47 + 0.000*sl 0.47 + 0.000*sl 0.47 + 0.000*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.93 0.86 + 0.032*sl 0.87 + 0.028*sl 0.90 + 0.025*sl t phl 0.90 0.85 + 0.025*sl 0.87 + 0.019*sl 0.91 + 0.015*sl t r 0.33 0.22 + 0.053*sl 0.23 + 0.052*sl 0.22 + 0.052*sl t f 0.24 0.19 + 0.026*sl 0.20 + 0.022*sl 0.22 + 0.020*sl rn to q t phl 0.57 0.51 + 0.027*sl 0.53 + 0.019*sl 0.59 + 0.014*sl t f 0.26 0.20 + 0.027*sl 0.22 + 0.020*sl 0.24 + 0.019*sl ck to z t plh 1.31 1.19 + 0.057*sl 1.22 + 0.047*sl 1.28 + 0.042*sl t phl 1.21 1.12 + 0.044*sl 1.14 + 0.035*sl 1.21 + 0.029*sl t r 0.23 0.18 + 0.027*sl 0.18 + 0.027*sl 0.18 + 0.026*sl t f 0.50 0.40 + 0.048*sl 0.41 + 0.045*sl 0.42 + 0.044*sl rn to z t phl 0.87 0.79 + 0.043*sl 0.81 + 0.034*sl 0.87 + 0.028*sl t f 0.49 0.40 + 0.048*sl 0.41 + 0.044*sl 0.42 + 0.043*sl rd to z t plh 0.36 0.32 + 0.023*sl 0.34 + 0.016*sl 0.37 + 0.013*sl t phl 0.10 0.04 + 0.031*sl 0.06 + 0.022*sl 0.10 + 0.018*sl t r 0.31 0.30 + 0.002*sl 0.25 + 0.021*sl 0.21 + 0.025*sl t f 0.24 0.16 + 0.041*sl 0.18 + 0.034*sl 0.16 + 0.035*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.69 0.69 + 0.000*sl 0.69 + 0.000*sl 0.69 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-226 sec asic fd3/fd3d2 d flip-flop with set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 fd3 fd3d2 fd3 fd3d2 d ck sn d ck sn 0.9 0.9 1.6 0.9 0.9 1.6 8.0 9.0 KGM80 fd3 fd3d2 fd3 fd3d2 d ck sn d ck sn 1.0 1.0 1.9 1.0 1.0 1.9 8.0 9.0 parameter symbol kg80 KGM80 fd3 fd3d2 fd3 fd3d2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (sn) t pwl 0.61 0.61 0.99 0.99 input setup time (d to ck) t su 0.42 0.42 0.74 0.74 input hold time (d to ck) t hd 0.15 0.15 0.33 0.33 recovery time (sn) t rc 0.15 0.15 0.33 0.33 input hold time (sn to ck) t hd 0.15 0.15 0.41 0.41 d ck q qn sn d ck cl clb q cl clb cl clb cl cl clb qn clb sn sn sn sn truth table d ck sn q (n+1) qn (n+1) 0 101 1 110 xx010 x 1 q (n) qn (n)
sec asic 3-227 kg80/KGM80 fd3/fd3d2 d flip-flop with set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd3 kg80 fd3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.51 0.43 + 0.042*sl 0.43 + 0.042*sl 0.43 + 0.042*sl t phl 0.56 0.50 + 0.031*sl 0.51 + 0.026*sl 0.52 + 0.024*sl t r 0.27 0.09 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.041*sl sn to q t plh 0.59 0.50 + 0.041*sl 0.50 + 0.041*sl 0.50 + 0.042*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.090*sl ck to qn t plh 0.76 0.68 + 0.042*sl 0.68 + 0.041*sl 0.68 + 0.042*sl t phl 0.60 0.54 + 0.030*sl 0.55 + 0.026*sl 0.57 + 0.023*sl t r 0.28 0.11 + 0.086*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.08 + 0.041*sl sn to qn t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.30 + 0.024*sl t f 0.18 0.11 + 0.039*sl 0.11 + 0.039*sl 0.09 + 0.040*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.49 0.45 + 0.023*sl 0.45 + 0.021*sl 0.45 + 0.021*sl t phl 0.56 0.52 + 0.020*sl 0.53 + 0.015*sl 0.54 + 0.013*sl t r 0.17 0.09 + 0.037*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl sn to q t plh 0.57 0.53 + 0.023*sl 0.53 + 0.021*sl 0.53 + 0.021*sl t r 0.17 0.09 + 0.040*sl 0.09 + 0.042*sl 0.07 + 0.044*sl ck to qn t plh 0.81 0.76 + 0.022*sl 0.77 + 0.020*sl 0.77 + 0.020*sl t phl 0.64 0.60 + 0.019*sl 0.61 + 0.015*sl 0.62 + 0.013*sl t r 0.19 0.10 + 0.042*sl 0.10 + 0.043*sl 0.10 + 0.044*sl t f 0.14 0.10 + 0.022*sl 0.10 + 0.020*sl 0.11 + 0.019*sl sn to qn t phl 0.33 0.29 + 0.022*sl 0.30 + 0.016*sl 0.32 + 0.013*sl t f 0.16 0.11 + 0.021*sl 0.12 + 0.019*sl 0.12 + 0.019*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-228 sec asic fd3/fd3d2 d flip-flop with set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd3 KGM80 fd3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.71 0.60 + 0.051*sl 0.61 + 0.050*sl 0.61 + 0.050*sl t phl 0.78 0.71 + 0.034*sl 0.74 + 0.026*sl 0.76 + 0.024*sl t r 0.34 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.044*sl 0.12 + 0.042*sl 0.11 + 0.042*sl sn to q t plh 0.82 0.72 + 0.051*sl 0.72 + 0.050*sl 0.72 + 0.050*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.11 + 0.109*sl ck to qn t plh 1.08 0.97 + 0.052*sl 0.98 + 0.050*sl 0.98 + 0.050*sl t phl 0.85 0.78 + 0.034*sl 0.81 + 0.026*sl 0.84 + 0.024*sl t r 0.36 0.16 + 0.104*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.20 0.11 + 0.044*sl 0.12 + 0.042*sl 0.12 + 0.042*sl sn to qn t phl 0.44 0.37 + 0.037*sl 0.39 + 0.027*sl 0.43 + 0.024*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.041*sl 0.13 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.68 0.62 + 0.028*sl 0.63 + 0.025*sl 0.63 + 0.025*sl t phl 0.79 0.74 + 0.024*sl 0.76 + 0.016*sl 0.80 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.021*sl 0.13 + 0.021*sl sn to q t plh 0.80 0.75 + 0.028*sl 0.75 + 0.025*sl 0.76 + 0.025*sl t r 0.22 0.12 + 0.050*sl 0.12 + 0.052*sl 0.10 + 0.054*sl ck to qn t plh 1.14 1.08 + 0.029*sl 1.09 + 0.025*sl 1.10 + 0.025*sl t phl 0.90 0.86 + 0.022*sl 0.88 + 0.016*sl 0.91 + 0.013*sl t r 0.24 0.14 + 0.053*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.17 0.12 + 0.026*sl 0.13 + 0.022*sl 0.14 + 0.021*sl sn to qn t phl 0.44 0.39 + 0.025*sl 0.41 + 0.017*sl 0.45 + 0.014*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.021*sl 0.16 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-229 kg80/KGM80 fd3cs/fd3csd2 d flip-flop with set, scan clock, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 fd3cs fd3csd2 fd3cs fd3cs d2 si sck d ck sn si sck d ck sn 0.8 2.1 0.9 0.9 2.7 0.8 2.1 0.9 0.9 2.7 12.0 13.0 KGM80 fd3cs fd3csd2 fd3cs fd3cs d2 si sck d ck sn si sck d ck sn 1.0 2.8 1.0 1.0 3.1 1.0 2.8 1.0 1.0 3.1 12.0 13.0 q qn si sck d ck sn d cl clb q cl clb cl cl clb qn clb sn sn sck sckb sck sckb sck sckb sn sckb sck si cl clb sck sck sckb ck sn sn truth table si sck d ck sn q (n+1) qn (n+1) x00 101 x01 110 0 x0101 1 x0110 xxxx010
kg80/KGM80 3-230 sec asic fd3cs/fd3csd2 d flip-flop with set, scan clock, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 fd3cs fd3csd2 fd3cs fd3csd2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (sck) t pwl 0.61 0.61 0.99 0.99 pulse width high (sck) t pwh 0.61 0.61 0.99 0.99 pulse width low (sn) t pwl 0.67 0.69 1.11 1.14 input setup time (d to ck) t su 0.42 0.42 0.74 0.74 input hold time (d to ck) t hd 0.15 0.15 0.33 0.33 input setup time (si to sck) t su 0.61 0.61 1.02 1.02 input hold time (si to sck) t hd 0.15 0.15 0.33 0.33 recovery time (sn to ck) t rc 0.15 0.15 0.33 0.33 input hold time (sn to ck) t hd 0.15 0.15 0.41 0.41 recovery time (sn to sck) t rc 0.31 0.31 0.55 0.55 input hold time (sn to sck) t hd 0.15 0.15 0.41 0.41
sec asic 3-231 kg80/KGM80 fd3cs/fd3csd2 d flip-flop with set, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd3cs kg80 fd3csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.51 0.43 + 0.041*sl 0.43 + 0.042*sl 0.43 + 0.042*sl t phl 0.56 0.50 + 0.030*sl 0.51 + 0.025*sl 0.52 + 0.024*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl sck to q t plh 0.54 0.46 + 0.043*sl 0.46 + 0.041*sl 0.46 + 0.041*sl t phl 0.53 0.46 + 0.031*sl 0.48 + 0.026*sl 0.49 + 0.024*sl t r 0.28 0.11 + 0.083*sl 0.10 + 0.089*sl 0.09 + 0.090*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.040*sl 0.09 + 0.041*sl sn to q t plh 0.59 0.51 + 0.041*sl 0.51 + 0.041*sl 0.51 + 0.042*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.08 + 0.090*sl ck to qn t plh 0.85 0.76 + 0.045*sl 0.77 + 0.042*sl 0.77 + 0.041*sl t phl 0.68 0.61 + 0.036*sl 0.63 + 0.028*sl 0.65 + 0.025*sl t r 0.32 0.15 + 0.085*sl 0.14 + 0.086*sl 0.12 + 0.089*sl t f 0.21 0.13 + 0.042*sl 0.13 + 0.040*sl 0.13 + 0.041*sl sck to qn t plh 0.72 0.64 + 0.042*sl 0.64 + 0.041*sl 0.64 + 0.041*sl t phl 0.63 0.57 + 0.030*sl 0.58 + 0.025*sl 0.59 + 0.023*sl t r 0.28 0.11 + 0.086*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl sn to qn t phl 0.41 0.34 + 0.037*sl 0.36 + 0.027*sl 0.38 + 0.024*sl t f 0.22 0.14 + 0.039*sl 0.15 + 0.037*sl 0.13 + 0.039*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.50 0.45 + 0.023*sl 0.46 + 0.021*sl 0.46 + 0.021*sl t phl 0.56 0.52 + 0.021*sl 0.53 + 0.015*sl 0.55 + 0.013*sl t r 0.17 0.09 + 0.038*sl 0.08 + 0.043*sl 0.07 + 0.045*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl sck to q t plh 0.54 0.49 + 0.023*sl 0.50 + 0.021*sl 0.50 + 0.021*sl t phl 0.53 0.49 + 0.021*sl 0.50 + 0.016*sl 0.52 + 0.013*sl t r 0.18 0.11 + 0.038*sl 0.10 + 0.042*sl 0.09 + 0.044*sl t f 0.15 0.11 + 0.021*sl 0.12 + 0.020*sl 0.12 + 0.020*sl sn to q t plh 0.58 0.53 + 0.023*sl 0.54 + 0.021*sl 0.54 + 0.020*sl t r 0.17 0.09 + 0.042*sl 0.09 + 0.042*sl 0.08 + 0.044*sl ck to qn t plh 0.91 0.86 + 0.024*sl 0.86 + 0.021*sl 0.87 + 0.021*sl t phl 0.72 0.68 + 0.021*sl 0.69 + 0.017*sl 0.71 + 0.014*sl t r 0.24 0.16 + 0.041*sl 0.16 + 0.042*sl 0.15 + 0.043*sl t f 0.19 0.14 + 0.025*sl 0.15 + 0.020*sl 0.15 + 0.020*sl sck to qn t plh 0.78 0.74 + 0.021*sl 0.74 + 0.020*sl 0.74 + 0.020*sl t phl 0.68 0.65 + 0.017*sl 0.65 + 0.014*sl 0.66 + 0.013*sl t r 0.21 0.12 + 0.043*sl 0.12 + 0.043*sl 0.12 + 0.044*sl t f 0.15 0.11 + 0.020*sl 0.11 + 0.020*sl 0.11 + 0.020*sl sn to qn t phl 0.41 0.36 + 0.023*sl 0.38 + 0.017*sl 0.40 + 0.014*sl t f 0.20 0.16 + 0.021*sl 0.16 + 0.019*sl 0.17 + 0.018*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 7, *grou p 3 : 7 < sl < < = =
kg80/KGM80 3-232 sec asic fd3cs/fd3csd2 d flip-flop with set, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd3cs KGM80 fd3csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.71 0.61 + 0.051*sl 0.61 + 0.050*sl 0.61 + 0.050*sl t phl 0.78 0.71 + 0.034*sl 0.74 + 0.026*sl 0.76 + 0.024*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.042*sl 0.12 + 0.042*sl 0.11 + 0.043*sl sck to q t plh 0.80 0.69 + 0.052*sl 0.70 + 0.050*sl 0.70 + 0.050*sl t phl 0.73 0.66 + 0.036*sl 0.69 + 0.027*sl 0.72 + 0.024*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.22 0.13 + 0.043*sl 0.13 + 0.041*sl 0.13 + 0.042*sl sn to q t plh 0.82 0.72 + 0.051*sl 0.72 + 0.050*sl 0.73 + 0.050*sl t r 0.35 0.15 + 0.103*sl 0.13 + 0.108*sl 0.12 + 0.109*sl ck to qn t plh 1.19 1.08 + 0.059*sl 1.10 + 0.051*sl 1.11 + 0.050*sl t phl 0.97 0.89 + 0.040*sl 0.92 + 0.030*sl 0.96 + 0.025*sl t r 0.42 0.21 + 0.104*sl 0.21 + 0.104*sl 0.18 + 0.107*sl t f 0.25 0.16 + 0.048*sl 0.17 + 0.043*sl 0.18 + 0.042*sl sck to qn t plh 1.01 0.91 + 0.051*sl 0.92 + 0.050*sl 0.92 + 0.050*sl t phl 0.93 0.86 + 0.033*sl 0.88 + 0.026*sl 0.91 + 0.023*sl t r 0.37 0.16 + 0.104*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.041*sl 0.11 + 0.042*sl sn to qn t phl 0.55 0.47 + 0.042*sl 0.50 + 0.029*sl 0.56 + 0.024*sl t f 0.26 0.17 + 0.044*sl 0.19 + 0.039*sl 0.17 + 0.041*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.69 0.63 + 0.028*sl 0.64 + 0.025*sl 0.64 + 0.025*sl t phl 0.80 0.75 + 0.023*sl 0.77 + 0.016*sl 0.80 + 0.013*sl t r 0.22 0.12 + 0.051*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.021*sl 0.14 + 0.021*sl sck to q t plh 0.80 0.74 + 0.029*sl 0.75 + 0.025*sl 0.75 + 0.025*sl t phl 0.75 0.71 + 0.024*sl 0.73 + 0.017*sl 0.76 + 0.014*sl t r 0.24 0.14 + 0.050*sl 0.13 + 0.052*sl 0.12 + 0.053*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.021*sl 0.15 + 0.020*sl sn to q t plh 0.81 0.75 + 0.028*sl 0.76 + 0.025*sl 0.77 + 0.025*sl t r 0.23 0.13 + 0.050*sl 0.12 + 0.052*sl 0.10 + 0.054*sl ck to qn t plh 1.27 1.21 + 0.031*sl 1.22 + 0.027*sl 1.24 + 0.025*sl t phl 1.03 0.98 + 0.025*sl 1.00 + 0.018*sl 1.04 + 0.015*sl t r 0.32 0.21 + 0.054*sl 0.22 + 0.052*sl 0.22 + 0.052*sl t f 0.23 0.18 + 0.026*sl 0.19 + 0.023*sl 0.20 + 0.021*sl sck to qn t plh 1.11 1.06 + 0.027*sl 1.06 + 0.024*sl 1.06 + 0.025*sl t phl 1.02 0.98 + 0.019*sl 1.00 + 0.015*sl 1.02 + 0.013*sl t r 0.28 0.17 + 0.053*sl 0.17 + 0.052*sl 0.16 + 0.053*sl t f 0.18 0.13 + 0.024*sl 0.14 + 0.021*sl 0.15 + 0.020*sl sn to qn t phl 0.56 0.51 + 0.027*sl 0.53 + 0.018*sl 0.58 + 0.014*sl t f 0.24 0.19 + 0.025*sl 0.20 + 0.020*sl 0.22 + 0.019*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 11, *grou p 3 : 11 < sl < < = =
sec asic 3-233 kg80/KGM80 fd3s/fd3sd2 d flip-flop with set, scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 fd3s fd3sd2 fd3s fd3s d2 d ti te ck sn d ti te ck sn 0.5 0.8 1.7 0.9 1.7 0.5 0.8 1.7 0.9 1.7 10.0 11.0 KGM80 fd3s fd3sd2 fd3s fd3s d2 d ti te ck sn d ti te ck sn 1.0 1.0 2.1 1.0 1.9 1.0 1.0 2.1 1.0 1.9 10.0 11.0 q qn d ti te ck sn cl clb q cl clb cl cl clb qn clb sn sn ck cl clb sn sn d te ti truth table dtitecksn q (n+1) qn (n+1) 0x0 101 1x0 110 x01 101 x11 110 xxxx010 x x x 1 q (n) qn (n)
kg80/KGM80 3-234 sec asic fd3s/fd3sd2 d flip-flop with set, scan, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd3s kg80 fd3sd2 parameter symbol kg80 KGM80 fd3s fd3sd2 fd3s fd3sd2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (sn) t pwl 0.61 0.61 0.99 0.99 input setup time (d to ck) t su 0.53 0.53 0.93 0.93 input hold time (d to ck) t hd 0.15 0.15 0.33 0.33 input setup time (ti to ck) t su 0.58 0.58 1.02 1.02 input hold time (ti to ck) t hd 0.15 0.15 0.33 0.33 input setup time (te to ck) t su 0.53 0.53 0.96 0.96 input hold time (te to ck) t hd 0.15 0.15 0.33 0.33 recovery time (sn) t rc 0.15 0.15 0.33 0.33 input hold time (sn to ck) t hd 0.15 0.15 0.41 0.41 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.51 0.43 + 0.042*sl 0.43 + 0.042*sl 0.43 + 0.042*sl t phl 0.56 0.50 + 0.031*sl 0.51 + 0.026*sl 0.52 + 0.024*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.090*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.041*sl sn to q t plh 0.59 0.51 + 0.041*sl 0.51 + 0.041*sl 0.50 + 0.042*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.08 + 0.090*sl ck to qn t plh 0.76 0.68 + 0.042*sl 0.68 + 0.041*sl 0.68 + 0.041*sl t phl 0.60 0.54 + 0.031*sl 0.55 + 0.026*sl 0.57 + 0.023*sl t r 0.28 0.11 + 0.086*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.08 + 0.041*sl 0.08 + 0.041*sl sn to qn t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.30 + 0.024*sl t f 0.18 0.11 + 0.039*sl 0.11 + 0.039*sl 0.09 + 0.041*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.49 0.45 + 0.023*sl 0.45 + 0.021*sl 0.45 + 0.021*sl t phl 0.56 0.52 + 0.021*sl 0.53 + 0.015*sl 0.55 + 0.013*sl t r 0.17 0.08 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.022*sl 0.11 + 0.019*sl 0.10 + 0.020*sl sn to q t plh 0.58 0.53 + 0.023*sl 0.53 + 0.021*sl 0.54 + 0.020*sl t r 0.17 0.09 + 0.043*sl 0.09 + 0.042*sl 0.07 + 0.044*sl ck to qn t plh 0.81 0.76 + 0.022*sl 0.77 + 0.020*sl 0.76 + 0.020*sl t phl 0.64 0.60 + 0.019*sl 0.61 + 0.015*sl 0.62 + 0.013*sl t r 0.19 0.10 + 0.042*sl 0.10 + 0.043*sl 0.10 + 0.044*sl t f 0.14 0.10 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.020*sl sn to qn t phl 0.33 0.29 + 0.021*sl 0.30 + 0.016*sl 0.32 + 0.013*sl t f 0.16 0.11 + 0.022*sl 0.12 + 0.019*sl 0.12 + 0.019*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-235 kg80/KGM80 fd3s/fd3sd2 d flip-flop with set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd3s KGM80 fd3sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.71 0.60 + 0.051*sl 0.61 + 0.050*sl 0.61 + 0.050*sl t phl 0.78 0.71 + 0.034*sl 0.73 + 0.026*sl 0.77 + 0.024*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.043*sl 0.12 + 0.042*sl 0.12 + 0.042*sl sn to q t plh 0.82 0.72 + 0.051*sl 0.72 + 0.050*sl 0.72 + 0.050*sl t r 0.35 0.14 + 0.103*sl 0.13 + 0.108*sl 0.11 + 0.109*sl ck to qn t plh 1.08 0.97 + 0.052*sl 0.98 + 0.050*sl 0.98 + 0.050*sl t phl 0.85 0.79 + 0.034*sl 0.81 + 0.026*sl 0.84 + 0.024*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.20 0.11 + 0.045*sl 0.12 + 0.042*sl 0.12 + 0.042*sl sn to qn t phl 0.44 0.37 + 0.037*sl 0.39 + 0.027*sl 0.43 + 0.024*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.041*sl 0.13 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.68 0.62 + 0.028*sl 0.63 + 0.025*sl 0.63 + 0.025*sl t phl 0.79 0.74 + 0.024*sl 0.76 + 0.017*sl 0.80 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.09 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.021*sl 0.13 + 0.021*sl sn to q t plh 0.81 0.75 + 0.028*sl 0.76 + 0.025*sl 0.76 + 0.025*sl t r 0.22 0.12 + 0.051*sl 0.12 + 0.052*sl 0.10 + 0.054*sl ck to qn t plh 1.14 1.08 + 0.029*sl 1.09 + 0.025*sl 1.10 + 0.025*sl t phl 0.91 0.86 + 0.023*sl 0.88 + 0.016*sl 0.91 + 0.013*sl t r 0.24 0.14 + 0.053*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.021*sl 0.14 + 0.021*sl sn to qn t phl 0.44 0.39 + 0.025*sl 0.41 + 0.017*sl 0.45 + 0.014*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.021*sl 0.16 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-236 sec asic fd3q/fd3qd2 d flip-flop with set, q output only, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 fd3q fd3qd2 fd3q fd3qd2 d ck sn d ck sn 0.8 0.8 1.4 0.8 0.8 1.4 7.0 8.0 KGM80 fd3q fd3qd2 fd3q fd3qd2 d ck sn d ck sn 0.9 0.9 1.7 0.9 0.9 1.7 7.0 8.0 parameter symbol kg80 KGM80 fd3q fd3qd2 fd3q fd3qd2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (sn) t pwl 0.61 0.61 1.02 1.02 input setup time (d to ck) t su 0.15 0.15 0.80 0.80 input hold time (d to ck) t hd 0.45 0.45 0.33 0.33 recovery time (sn) t rc 0.15 0.15 0.33 0.33 input hold time (sn to ck) t hd 0.15 0.15 0.41 0.41 d ck q sn d ck cl clb q cl clb cl clb cl cl clb clb sn sn sn sn truth table d ck sn q (n+1) 010 111 xx01 x x q (n)
sec asic 3-237 kg80/KGM80 fd3q/fd3qd2 d flip-flop with set, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd3q kg80 fd3qd2 switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd3q KGM80 fd3qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.49 0.40 + 0.043*sl 0.41 + 0.042*sl 0.41 + 0.042*sl t phl 0.52 0.46 + 0.030*sl 0.47 + 0.026*sl 0.49 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.17 0.08 + 0.041*sl 0.09 + 0.040*sl 0.08 + 0.042*sl sn to q t plh 0.59 0.50 + 0.042*sl 0.50 + 0.041*sl 0.50 + 0.042*sl t r 0.27 0.10 + 0.083*sl 0.08 + 0.089*sl 0.07 + 0.091*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.48 0.43 + 0.022*sl 0.44 + 0.021*sl 0.44 + 0.021*sl t phl 0.53 0.49 + 0.018*sl 0.50 + 0.015*sl 0.51 + 0.013*sl t r 0.18 0.10 + 0.042*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl sn to q t plh 0.58 0.54 + 0.022*sl 0.54 + 0.020*sl 0.54 + 0.021*sl t r 0.18 0.10 + 0.040*sl 0.10 + 0.043*sl 0.09 + 0.044*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.70 0.59 + 0.051*sl 0.60 + 0.050*sl 0.60 + 0.050*sl t phl 0.74 0.67 + 0.034*sl 0.69 + 0.026*sl 0.72 + 0.023*sl t r 0.34 0.13 + 0.105*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.044*sl 0.12 + 0.042*sl 0.11 + 0.042*sl sn to q t plh 0.83 0.73 + 0.051*sl 0.73 + 0.050*sl 0.73 + 0.050*sl t r 0.34 0.14 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.69 0.63 + 0.027*sl 0.64 + 0.025*sl 0.64 + 0.025*sl t phl 0.76 0.71 + 0.021*sl 0.73 + 0.016*sl 0.76 + 0.013*sl t r 0.24 0.14 + 0.052*sl 0.14 + 0.053*sl 0.12 + 0.054*sl t f 0.18 0.13 + 0.023*sl 0.13 + 0.021*sl 0.14 + 0.021*sl sn to q t plh 0.83 0.77 + 0.026*sl 0.78 + 0.025*sl 0.78 + 0.025*sl t r 0.25 0.15 + 0.050*sl 0.14 + 0.052*sl 0.13 + 0.054*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-238 sec asic fd3x2 2-bit d flip-flop with set logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 pulse width low (ck) t pwl 0.67 1.05 pulse width high (ck) t pwh 0.61 0.99 pulse width low (sn) t pwl 0.61 0.99 input setup time (d0 to ck) t su 0.37 0.64 input hold time (d0 to ck) t hd 0.15 0.33 input setup time (d1 to ck) t su 0.37 0.64 input hold time (d1 to ck) t hd 0.15 0.33 recovery time (sn) t rc 0.15 0.33 input hold time (sn to ck) t hd 0.20 0.41 q0 qn1 d0 d1 ck q1 qn0 sn truth table cell data dn ck sn qn (n+1) qnn (n+1) 0101 1110 xx0 1 0 x 1 qn (n) qnn (n) input load (sl) gate count kg80 dn ck sn 15.0 1.0 0.9 3.4 KGM80 dn ck sn 15.0 1.0 1.0 4.2
sec asic 3-239 kg80/KGM80 fd3x2 2-bit d flip-flop with set switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd3x2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.57 0.48 + 0.042*sl 0.48 + 0.042*sl 0.48 + 0.042*sl t phl 0.67 0.60 + 0.031*sl 0.62 + 0.026*sl 0.63 + 0.024*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.041*sl sn to q0 t plh 0.59 0.50 + 0.042*sl 0.50 + 0.041*sl 0.50 + 0.042*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.090*sl ck to q1 t plh 0.57 0.48 + 0.042*sl 0.48 + 0.042*sl 0.48 + 0.042*sl t phl 0.67 0.60 + 0.031*sl 0.62 + 0.026*sl 0.63 + 0.024*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.090*sl 0.08 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.041*sl sn to q1 t plh 0.59 0.50 + 0.042*sl 0.50 + 0.041*sl 0.50 + 0.042*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.090*sl ck to qn0 t plh 0.87 0.79 + 0.042*sl 0.79 + 0.041*sl 0.79 + 0.041*sl t phl 0.66 0.60 + 0.031*sl 0.61 + 0.025*sl 0.62 + 0.024*sl t r 0.28 0.11 + 0.086*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl sn to qn0 t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.30 + 0.024*sl t f 0.18 0.11 + 0.039*sl 0.11 + 0.039*sl 0.10 + 0.040*sl ck to qn1 t plh 0.87 0.79 + 0.042*sl 0.79 + 0.041*sl 0.79 + 0.041*sl t phl 0.66 0.60 + 0.031*sl 0.61 + 0.025*sl 0.62 + 0.024*sl t r 0.28 0.11 + 0.086*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.041*sl sn to qn1 t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.30 + 0.024*sl t f 0.18 0.11 + 0.039*sl 0.11 + 0.039*sl 0.10 + 0.040*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-240 sec asic fd3x2 2-bit d flip-flop with set switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd3x2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.77 0.67 + 0.051*sl 0.67 + 0.050*sl 0.68 + 0.050*sl t phl 0.93 0.86 + 0.034*sl 0.88 + 0.026*sl 0.91 + 0.024*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.043*sl 0.12 + 0.042*sl 0.11 + 0.042*sl sn to q0 t plh 0.81 0.71 + 0.051*sl 0.71 + 0.050*sl 0.72 + 0.050*sl t r 0.35 0.14 + 0.103*sl 0.13 + 0.108*sl 0.11 + 0.109*sl ck to q1 t plh 0.78 0.67 + 0.051*sl 0.68 + 0.050*sl 0.68 + 0.050*sl t phl 0.93 0.86 + 0.034*sl 0.88 + 0.026*sl 0.91 + 0.024*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.043*sl 0.12 + 0.042*sl 0.11 + 0.042*sl sn to q1 t plh 0.81 0.71 + 0.051*sl 0.71 + 0.050*sl 0.72 + 0.050*sl t r 0.35 0.14 + 0.103*sl 0.13 + 0.108*sl 0.11 + 0.109*sl ck to qn0 t plh 1.23 1.12 + 0.052*sl 1.13 + 0.050*sl 1.13 + 0.050*sl t phl 0.92 0.85 + 0.034*sl 0.88 + 0.026*sl 0.91 + 0.024*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.045*sl 0.12 + 0.042*sl 0.12 + 0.042*sl sn to qn0 t phl 0.44 0.37 + 0.037*sl 0.40 + 0.027*sl 0.43 + 0.024*sl t f 0.22 0.13 + 0.046*sl 0.14 + 0.041*sl 0.13 + 0.042*sl ck to qn1 t plh 1.23 1.12 + 0.052*sl 1.13 + 0.050*sl 1.13 + 0.050*sl t phl 0.92 0.86 + 0.034*sl 0.88 + 0.026*sl 0.91 + 0.024*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.20 0.11 + 0.045*sl 0.12 + 0.042*sl 0.12 + 0.042*sl sn to qn1 t phl 0.44 0.37 + 0.037*sl 0.40 + 0.027*sl 0.43 + 0.024*sl t f 0.22 0.13 + 0.046*sl 0.14 + 0.041*sl 0.13 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-241 kg80/KGM80 fd3x4 4-bit d flip-flop with set logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 pulse width low (ck) t pwl 0.83 1.33 pulse width high (ck) t pwh 0.61 0.99 pulse width low (sn) t pwl 0.61 0.99 input setup time (d0 to ck) t su 0.23 0.49 input hold time (d0 to ck) t hd 0.23 0.39 input setup time (d1 to ck) t su 0.23 0.49 input hold time (d1 to ck) t hd 0.23 0.39 input setup time (d2 to ck) t su 0.23 0.49 input hold time (d2 to ck) t hd 0.23 0.39 input setup time (d3 to ck) t su 0.23 0.49 input hold time (d3 to ck) t hd 0.23 0.39 recovery time (sn) t rc 0.15 0.33 input hold time (sn to ck) t hd 0.37 0.63 d0 d1 d2 d3 ck q0 q1 q2 q3 qn0 qn1 qn2 qn3 sn truth table cell data dn ck sn qn (n+1) qnn (n+1) 0101 1110 xx0 1 0 x 1 qn (n) qnn (n) input load (sl) gate count kg80 dn ck sn 30.0 1.0 0.9 7.2 KGM80 dn ck sn 30.0 1.0 1.0 8.6
kg80/KGM80 3-242 sec asic fd3x4 4-bit d flip-flop with set switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd3x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.67 0.59 + 0.042*sl 0.59 + 0.042*sl 0.59 + 0.042*sl t phl 0.87 0.81 + 0.030*sl 0.82 + 0.026*sl 0.84 + 0.024*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.041*sl sn to q0 t plh 0.58 0.50 + 0.041*sl 0.50 + 0.041*sl 0.50 + 0.042*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.090*sl ck to q1 t plh 0.68 0.60 + 0.042*sl 0.60 + 0.042*sl 0.60 + 0.042*sl t phl 0.88 0.82 + 0.031*sl 0.83 + 0.026*sl 0.85 + 0.024*sl t r 0.27 0.11 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.040*sl 0.09 + 0.041*sl sn to q1 t plh 0.59 0.51 + 0.041*sl 0.51 + 0.041*sl 0.51 + 0.041*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.08 + 0.090*sl ck to q2 t plh 0.68 0.60 + 0.042*sl 0.60 + 0.042*sl 0.60 + 0.042*sl t phl 0.88 0.82 + 0.031*sl 0.83 + 0.026*sl 0.85 + 0.024*sl t r 0.27 0.11 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.040*sl 0.09 + 0.041*sl sn to q2 t plh 0.59 0.51 + 0.041*sl 0.51 + 0.041*sl 0.51 + 0.041*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.08 + 0.090*sl ck to q3 t plh 0.67 0.59 + 0.042*sl 0.59 + 0.042*sl 0.59 + 0.042*sl t phl 0.87 0.81 + 0.030*sl 0.82 + 0.026*sl 0.84 + 0.024*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.041*sl sn to q3 t plh 0.58 0.50 + 0.041*sl 0.50 + 0.041*sl 0.50 + 0.042*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.090*sl ck to qn0 t plh 1.08 0.99 + 0.042*sl 0.99 + 0.041*sl 0.99 + 0.041*sl t phl 0.76 0.70 + 0.030*sl 0.71 + 0.026*sl 0.73 + 0.023*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.08 + 0.041*sl sn to qn0 t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.30 + 0.023*sl t f 0.18 0.11 + 0.039*sl 0.11 + 0.039*sl 0.09 + 0.040*sl ck to qn1 t plh 1.08 0.99 + 0.042*sl 0.99 + 0.041*sl 0.99 + 0.041*sl t phl 0.77 0.71 + 0.030*sl 0.72 + 0.025*sl 0.73 + 0.023*sl t r 0.28 0.11 + 0.086*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.08 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl sn to qn1 t phl 0.33 0.27 + 0.032*sl 0.28 + 0.026*sl 0.30 + 0.023*sl t f 0.18 0.10 + 0.039*sl 0.10 + 0.039*sl 0.09 + 0.040*sl ck to qn2 t plh 1.08 0.99 + 0.042*sl 0.99 + 0.041*sl 0.99 + 0.041*sl t phl 0.77 0.71 + 0.030*sl 0.72 + 0.025*sl 0.73 + 0.023*sl t r 0.28 0.11 + 0.086*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.08 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-243 kg80/KGM80 fd3x4 4-bit d flip-flop with set switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd3x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.90 0.80 + 0.051*sl 0.80 + 0.050*sl 0.81 + 0.050*sl t phl 1.22 1.15 + 0.035*sl 1.17 + 0.026*sl 1.20 + 0.024*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.043*sl 0.12 + 0.042*sl 0.12 + 0.042*sl sn to q0 t plh 0.81 0.71 + 0.050*sl 0.71 + 0.050*sl 0.71 + 0.050*sl t r 0.35 0.14 + 0.103*sl 0.13 + 0.108*sl 0.11 + 0.109*sl ck to q1 t plh 0.92 0.82 + 0.051*sl 0.82 + 0.050*sl 0.82 + 0.050*sl t phl 1.23 1.16 + 0.035*sl 1.18 + 0.027*sl 1.21 + 0.024*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.042*sl 0.12 + 0.042*sl sn to q1 t plh 0.82 0.72 + 0.051*sl 0.72 + 0.050*sl 0.72 + 0.050*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.108*sl 0.12 + 0.109*sl ck to q2 t plh 0.92 0.82 + 0.051*sl 0.82 + 0.050*sl 0.82 + 0.050*sl t phl 1.23 1.16 + 0.035*sl 1.18 + 0.027*sl 1.21 + 0.024*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.042*sl 0.12 + 0.042*sl sn to q2 t plh 0.82 0.72 + 0.051*sl 0.72 + 0.050*sl 0.72 + 0.050*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.108*sl 0.12 + 0.109*sl ck to q3 t plh 0.90 0.80 + 0.051*sl 0.80 + 0.050*sl 0.81 + 0.050*sl t phl 1.22 1.15 + 0.035*sl 1.17 + 0.026*sl 1.20 + 0.024*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.043*sl 0.12 + 0.042*sl 0.12 + 0.042*sl sn to q3 t plh 0.81 0.71 + 0.050*sl 0.71 + 0.050*sl 0.71 + 0.050*sl t r 0.35 0.14 + 0.103*sl 0.13 + 0.108*sl 0.11 + 0.109*sl ck to qn0 t plh 1.51 1.41 + 0.052*sl 1.41 + 0.050*sl 1.41 + 0.050*sl t phl 1.05 0.98 + 0.034*sl 1.00 + 0.026*sl 1.03 + 0.024*sl t r 0.36 0.16 + 0.104*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.20 0.11 + 0.044*sl 0.12 + 0.042*sl 0.11 + 0.042*sl sn to qn0 t phl 0.44 0.37 + 0.037*sl 0.40 + 0.027*sl 0.43 + 0.024*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.041*sl 0.13 + 0.042*sl ck to qn1 t plh 1.51 1.41 + 0.052*sl 1.41 + 0.050*sl 1.41 + 0.050*sl t phl 1.05 0.99 + 0.034*sl 1.01 + 0.026*sl 1.03 + 0.023*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.042*sl 0.11 + 0.042*sl sn to qn1 t phl 0.43 0.36 + 0.036*sl 0.39 + 0.027*sl 0.42 + 0.024*sl t f 0.21 0.13 + 0.044*sl 0.14 + 0.041*sl 0.12 + 0.042*sl ck to qn2 t plh 1.51 1.41 + 0.052*sl 1.41 + 0.050*sl 1.41 + 0.050*sl t phl 1.05 0.99 + 0.033*sl 1.01 + 0.026*sl 1.03 + 0.023*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.20 0.11 + 0.044*sl 0.12 + 0.042*sl 0.11 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-244 sec asic yfd3/yfd3d2 fast d flip-flop with set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 yfd3 yfd3d2 yfd3 yfd3d2 dcksndcksn 2.9 0.8 1.4 2.9 0.8 2.1 6.0 8.0 KGM80 yfd3 yfd3d2 yfd3 yfd3d2 dcksndcksn 3.7 0.9 1.6 3.7 0.9 2.4 6.0 8.0 parameter symbol kg80 KGM80 yfd3 yfd3d2 yfd3 yfd3d2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (sn) t pwl 0.61 0.61 0.99 0.99 input setup time (d to ck) t su 0.26 0.26 0.46 0.46 input hold time (d to ck) t hd 0.26 0.26 0.52 0.52 recovery time (sn) t rc 0.15 0.15 0.33 0.33 input hold time (sn to ck) t hd 0.42 0.42 0.85 0.63 d ck q qn sn d ck cl clb q cl clb cl clb cl cl clb qn clb sn sn sn sn truth table d ck sn q (n+1) qn (n+1) 0 101 1 110 xx010 x 1 q (n) qn (n)
sec asic 3-245 kg80/KGM80 yfd3/yfd3d2 fast d flip-flop with set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 yfd3 kg80 yfd3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.47 0.38 + 0.043*sl 0.38 + 0.042*sl 0.39 + 0.042*sl t phl 0.44 0.36 + 0.041*sl 0.37 + 0.037*sl 0.38 + 0.035*sl t r 0.38 0.21 + 0.085*sl 0.21 + 0.088*sl 0.19 + 0.090*sl t f 0.32 0.19 + 0.068*sl 0.19 + 0.067*sl 0.19 + 0.067*sl sn to q t plh 0.29 0.21 + 0.040*sl 0.21 + 0.040*sl 0.30 + 0.027*sl t r 0.44 0.32 + 0.061*sl 0.38 + 0.038*sl 0.37 + 0.039*sl ck to qn t plh 0.66 0.46 + 0.102*sl 0.47 + 0.098*sl 0.48 + 0.095*sl t phl 0.59 0.44 + 0.078*sl 0.44 + 0.077*sl 0.44 + 0.077*sl t r 0.34 0.15 + 0.099*sl 0.14 + 0.100*sl 0.14 + 0.100*sl t f 0.22 0.10 + 0.061*sl 0.09 + 0.063*sl 0.09 + 0.063*sl sn to qn t phl 0.41 0.26 + 0.076*sl 0.28 + 0.068*sl 0.36 + 0.056*sl t f 0.23 0.11 + 0.060*sl 0.14 + 0.048*sl 0.16 + 0.045*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.45 0.41 + 0.023*sl 0.41 + 0.022*sl 0.41 + 0.021*sl t phl 0.44 0.39 + 0.023*sl 0.40 + 0.021*sl 0.41 + 0.019*sl t r 0.31 0.22 + 0.043*sl 0.22 + 0.044*sl 0.21 + 0.045*sl t f 0.28 0.21 + 0.032*sl 0.21 + 0.033*sl 0.21 + 0.033*sl sn to q t plh 0.25 0.21 + 0.020*sl 0.21 + 0.020*sl 0.20 + 0.021*sl t r 0.39 0.31 + 0.040*sl 0.34 + 0.027*sl 0.40 + 0.019*sl ck to qn t plh 0.58 0.48 + 0.055*sl 0.48 + 0.051*sl 0.50 + 0.049*sl t phl 0.53 0.45 + 0.040*sl 0.45 + 0.039*sl 0.46 + 0.039*sl t r 0.22 0.13 + 0.048*sl 0.12 + 0.050*sl 0.12 + 0.051*sl t f 0.14 0.08 + 0.031*sl 0.08 + 0.031*sl 0.08 + 0.032*sl sn to qn t phl 0.32 0.25 + 0.040*sl 0.25 + 0.038*sl 0.27 + 0.035*sl t f 0.16 0.10 + 0.030*sl 0.10 + 0.030*sl 0.13 + 0.025*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-246 sec asic yfd3/yfd3d2 fast d flip-flop with set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 yfd3 KGM80 yfd3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.65 0.55 + 0.052*sl 0.55 + 0.050*sl 0.56 + 0.050*sl t phl 0.63 0.53 + 0.049*sl 0.55 + 0.041*sl 0.59 + 0.038*sl t r 0.51 0.30 + 0.105*sl 0.30 + 0.107*sl 0.28 + 0.109*sl t f 0.41 0.26 + 0.076*sl 0.27 + 0.073*sl 0.27 + 0.073*sl sn to q t plh 0.36 0.26 + 0.049*sl 0.27 + 0.048*sl 0.48 + 0.028*sl t r 0.59 0.40 + 0.095*sl 0.52 + 0.049*sl 0.52 + 0.049*sl ck to qn t plh 0.92 0.68 + 0.121*sl 0.70 + 0.113*sl 0.74 + 0.110*sl t phl 0.82 0.64 + 0.094*sl 0.64 + 0.092*sl 0.65 + 0.092*sl t r 0.46 0.22 + 0.118*sl 0.22 + 0.119*sl 0.22 + 0.119*sl t f 0.26 0.12 + 0.067*sl 0.12 + 0.068*sl 0.12 + 0.068*sl sn to qn t phl 0.54 0.35 + 0.092*sl 0.39 + 0.079*sl 0.56 + 0.063*sl t f 0.27 0.14 + 0.065*sl 0.19 + 0.049*sl 0.18 + 0.050*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.64 0.59 + 0.028*sl 0.59 + 0.026*sl 0.60 + 0.025*sl t phl 0.64 0.58 + 0.028*sl 0.60 + 0.023*sl 0.63 + 0.020*sl t r 0.41 0.31 + 0.053*sl 0.31 + 0.052*sl 0.30 + 0.053*sl t f 0.37 0.29 + 0.038*sl 0.29 + 0.037*sl 0.31 + 0.036*sl sn to q t plh 0.31 0.26 + 0.025*sl 0.26 + 0.025*sl 0.26 + 0.025*sl t r 0.48 0.38 + 0.051*sl 0.42 + 0.036*sl 0.56 + 0.023*sl ck to qn t plh 0.84 0.71 + 0.065*sl 0.73 + 0.059*sl 0.76 + 0.056*sl t phl 0.75 0.66 + 0.048*sl 0.66 + 0.046*sl 0.67 + 0.046*sl t r 0.30 0.18 + 0.059*sl 0.18 + 0.059*sl 0.18 + 0.059*sl t f 0.17 0.11 + 0.032*sl 0.10 + 0.033*sl 0.10 + 0.033*sl sn to qn t phl 0.42 0.33 + 0.047*sl 0.33 + 0.046*sl 0.40 + 0.039*sl t f 0.19 0.12 + 0.034*sl 0.13 + 0.031*sl 0.22 + 0.023*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-247 kg80/KGM80 fd4/fd4d2 d flip-flop with reset, set, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 fd4 fd4d2 fd4 fd4d2 d ck rn sn d ck rn sn 0.9 0.9 1.7 1.6 0.9 0.9 1.7 1.6 9.0 10.0 KGM80 fd4 fd4d2 fd4 fd4d2 d ck rn sn d ck rn sn 1.0 1.0 2.2 2.1 1.0 1.0 2.2 2.1 9.0 10.0 d ck q qn rn sn d ck cl clb q cl clb cl clb cl cl clb qn clb sn sn rn rn rn rn sn sn truth table dckrnsn q (n+1) qn (n+1) 01101 11110 xx1010 xx0101 xx0000 x 1 1 q (n) qn (n)
kg80/KGM80 3-248 sec asic fd4/fd4d2 d flip-flop with reset, set, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 fd4 fd4d2 fd4 fd4d2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 0.99 pulse width low (sn) t pwl 0.61 0.64 1.02 1.02 input setup time (d to ck) t su 0.42 0.42 0.74 0.74 input hold time (d to ck) t hd 0.15 0.15 0.33 0.33 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ck) t hd 0.42 0.42 0.63 0.63 recovery time (sn) t rc 0.15 0.15 0.33 0.33 input hold time (sn to ck) t hd 0.15 0.15 0.41 0.41
sec asic 3-249 kg80/KGM80 fd4/fd4d2 d flip-flop with reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd4 kg80 fd4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.57 0.48 + 0.044*sl 0.48 + 0.042*sl 0.49 + 0.042*sl t phl 0.57 0.51 + 0.031*sl 0.52 + 0.026*sl 0.53 + 0.024*sl t r 0.29 0.11 + 0.087*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.10 + 0.041*sl 0.10 + 0.040*sl 0.09 + 0.041*sl rn to q t plh 0.29 0.20 + 0.043*sl 0.21 + 0.041*sl 0.21 + 0.042*sl t phl 0.33 0.27 + 0.032*sl 0.28 + 0.026*sl 0.30 + 0.024*sl t r 0.28 0.12 + 0.084*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.040*sl 0.10 + 0.041*sl sn to q t plh 0.65 0.56 + 0.043*sl 0.57 + 0.041*sl 0.57 + 0.041*sl t r 0.29 0.12 + 0.085*sl 0.11 + 0.088*sl 0.10 + 0.090*sl ck to qn t plh 0.76 0.67 + 0.042*sl 0.67 + 0.041*sl 0.67 + 0.042*sl t phl 0.65 0.58 + 0.030*sl 0.60 + 0.025*sl 0.61 + 0.023*sl t r 0.28 0.10 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.08 + 0.041*sl 0.09 + 0.040*sl 0.07 + 0.042*sl rn to qn t plh 0.52 0.44 + 0.042*sl 0.44 + 0.041*sl 0.44 + 0.041*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl sn to qn t plh 0.29 0.20 + 0.044*sl 0.21 + 0.041*sl 0.21 + 0.041*sl t phl 0.32 0.26 + 0.032*sl 0.28 + 0.025*sl 0.29 + 0.024*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.039*sl 0.09 + 0.041*sl [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.57 0.52 + 0.024*sl 0.52 + 0.022*sl 0.53 + 0.021*sl t phl 0.58 0.54 + 0.019*sl 0.55 + 0.015*sl 0.56 + 0.013*sl t r 0.21 0.13 + 0.042*sl 0.12 + 0.043*sl 0.12 + 0.044*sl t f 0.16 0.11 + 0.022*sl 0.12 + 0.019*sl 0.11 + 0.020*sl rn to q t plh 0.29 0.24 + 0.023*sl 0.24 + 0.022*sl 0.25 + 0.021*sl t phl 0.33 0.29 + 0.020*sl 0.30 + 0.016*sl 0.32 + 0.013*sl t r 0.21 0.12 + 0.043*sl 0.13 + 0.042*sl 0.12 + 0.044*sl t f 0.16 0.12 + 0.021*sl 0.13 + 0.019*sl 0.12 + 0.020*sl sn to q t plh 0.65 0.61 + 0.023*sl 0.61 + 0.022*sl 0.62 + 0.021*sl t r 0.21 0.13 + 0.042*sl 0.13 + 0.043*sl 0.12 + 0.044*sl ck to qn t plh 0.80 0.76 + 0.021*sl 0.76 + 0.020*sl 0.76 + 0.020*sl t phl 0.69 0.65 + 0.019*sl 0.66 + 0.015*sl 0.68 + 0.013*sl t r 0.19 0.10 + 0.042*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.019*sl 0.10 + 0.020*sl rn to qn t plh 0.56 0.52 + 0.022*sl 0.52 + 0.020*sl 0.52 + 0.020*sl t r 0.19 0.10 + 0.042*sl 0.10 + 0.043*sl 0.09 + 0.044*sl sn to qn t plh 0.28 0.23 + 0.025*sl 0.24 + 0.022*sl 0.24 + 0.021*sl t phl 0.32 0.28 + 0.021*sl 0.29 + 0.016*sl 0.31 + 0.013*sl t r 0.19 0.10 + 0.041*sl 0.10 + 0.042*sl 0.09 + 0.044*sl t f 0.15 0.11 + 0.021*sl 0.11 + 0.019*sl 0.11 + 0.019*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-250 sec asic fd4/fd4d2 d flip-flop with reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd4 KGM80 fd4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.79 0.68 + 0.054*sl 0.69 + 0.051*sl 0.70 + 0.050*sl t phl 0.80 0.73 + 0.034*sl 0.75 + 0.027*sl 0.79 + 0.024*sl t r 0.37 0.16 + 0.106*sl 0.16 + 0.107*sl 0.14 + 0.108*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.042*sl 0.12 + 0.042*sl rn to q t plh 0.39 0.28 + 0.054*sl 0.29 + 0.050*sl 0.30 + 0.050*sl t phl 0.43 0.36 + 0.035*sl 0.38 + 0.027*sl 0.41 + 0.024*sl t r 0.37 0.16 + 0.104*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.22 0.13 + 0.042*sl 0.13 + 0.042*sl 0.13 + 0.042*sl sn to q t plh 0.90 0.80 + 0.054*sl 0.81 + 0.050*sl 0.81 + 0.050*sl t r 0.37 0.17 + 0.103*sl 0.16 + 0.106*sl 0.14 + 0.109*sl ck to qn t plh 1.07 0.97 + 0.052*sl 0.98 + 0.050*sl 0.98 + 0.050*sl t phl 0.91 0.85 + 0.034*sl 0.87 + 0.026*sl 0.89 + 0.023*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.041*sl 0.11 + 0.042*sl rn to qn t plh 0.70 0.60 + 0.051*sl 0.60 + 0.050*sl 0.60 + 0.050*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.107*sl 0.12 + 0.109*sl sn to qn t plh 0.40 0.29 + 0.054*sl 0.30 + 0.050*sl 0.30 + 0.050*sl t phl 0.42 0.35 + 0.035*sl 0.38 + 0.026*sl 0.41 + 0.024*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.041*sl 0.12 + 0.042*sl [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.79 0.73 + 0.030*sl 0.74 + 0.026*sl 0.75 + 0.025*sl t phl 0.82 0.78 + 0.022*sl 0.80 + 0.016*sl 0.83 + 0.013*sl t r 0.28 0.18 + 0.053*sl 0.18 + 0.052*sl 0.17 + 0.053*sl t f 0.19 0.14 + 0.025*sl 0.15 + 0.021*sl 0.15 + 0.021*sl rn to q t plh 0.39 0.33 + 0.030*sl 0.34 + 0.026*sl 0.35 + 0.025*sl t phl 0.44 0.40 + 0.023*sl 0.42 + 0.016*sl 0.45 + 0.013*sl t r 0.28 0.18 + 0.049*sl 0.17 + 0.052*sl 0.16 + 0.053*sl t f 0.20 0.15 + 0.025*sl 0.16 + 0.021*sl 0.16 + 0.020*sl sn to q t plh 0.92 0.86 + 0.030*sl 0.87 + 0.026*sl 0.88 + 0.025*sl t r 0.28 0.18 + 0.053*sl 0.18 + 0.052*sl 0.16 + 0.053*sl ck to qn t plh 1.13 1.08 + 0.029*sl 1.09 + 0.025*sl 1.09 + 0.025*sl t phl 0.99 0.94 + 0.022*sl 0.96 + 0.016*sl 0.99 + 0.013*sl t r 0.24 0.13 + 0.054*sl 0.14 + 0.052*sl 0.12 + 0.053*sl t f 0.17 0.12 + 0.024*sl 0.13 + 0.021*sl 0.14 + 0.020*sl rn to qn t plh 0.76 0.70 + 0.029*sl 0.71 + 0.025*sl 0.71 + 0.025*sl t r 0.24 0.13 + 0.055*sl 0.14 + 0.052*sl 0.13 + 0.053*sl sn to qn t plh 0.38 0.32 + 0.031*sl 0.33 + 0.026*sl 0.35 + 0.025*sl t phl 0.43 0.38 + 0.025*sl 0.40 + 0.017*sl 0.44 + 0.013*sl t r 0.24 0.13 + 0.055*sl 0.14 + 0.052*sl 0.12 + 0.053*sl t f 0.18 0.13 + 0.026*sl 0.14 + 0.021*sl 0.15 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-251 kg80/KGM80 fd4cs/fd4csd2 d flip-flop with reset, set, scan clock, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 fd4cs fd4csd2 fd4cs fd4csd2 si sck d ck rn sn si sck d ck rn sn 0.8 2.1 0.9 0.9 3.0 2.6 0.8 2.1 0.9 0.9 3.0 2.7 14.0 15.0 KGM80 fd4cs fd4csd2 fd4cs fd4csd2 si sck d ck rn sn si sck d ck rn sn 1.0 2.6 1.0 1.0 3.5 3.1 1.0 2.5 1.0 1.0 3.6 3.1 14.0 15.0 q qn si sck d ck rn sn d cl clb q cl clb cl cl clb qn clb sn sn rn rn sck sckb si sck sckb sck sckb sn rn sckb sck cl clb sck sck sckb ck rn rn sn sn truth table si sck d ck rn sn q (n+1) qn (n+1) x00 11 0 1 x01 11 1 0 0x01101 1x01110 xxxx10 1 0 xxxx01 0 1 xxxx00 0 0
kg80/KGM80 3-252 sec asic fd4cs/fd4csd2 d flip-flop with reset, set, scan clock, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 fd4cs fd4csd2 fd4cs fd4csd2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (sck) t pwl 0.61 0.61 0.99 0.99 pulse width high (sck) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 0.99 pulse width low (sn) t pwl 0.72 0.75 1.18 1.24 input setup time (d to ck) t su 0.42 0.42 0.74 0.74 input hold time (d to ck) t hd 0.15 0.15 0.33 0.33 input setup time (si to sck) t su 0.61 0.61 1.02 1.05 input hold time (si to sck) t hd 0.15 0.15 0.33 0.33 recovery time (rn to ck) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ck) t hd 0.42 0.42 0.85 0.85 recovery time (rn to sck) t rc 0.15 0.15 0.55 0.58 input hold time (rn to sck) t hd 0.31 0.31 0.63 0.63 recovery time (sn to ck) t rc 0.15 0.15 0.33 0.33 input hold time (sn to ck) t hd 0.15 0.15 0.41 0.41 recovery time (sn to sck) t rc 0.31 0.31 0.33 0.52 input hold time (sn to sck) t hd 0.15 0.15 0.41 0.41
sec asic 3-253 kg80/KGM80 fd4cs/fd4csd2 d flip-flop with reset, set, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd4cs path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.59 0.50 + 0.044*sl 0.51 + 0.042*sl 0.51 + 0.042*sl t phl 0.58 0.52 + 0.032*sl 0.53 + 0.026*sl 0.55 + 0.024*sl t r 0.29 0.12 + 0.085*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.10 + 0.041*sl 0.10 + 0.040*sl 0.10 + 0.041*sl sck to q t plh 0.65 0.56 + 0.045*sl 0.57 + 0.042*sl 0.57 + 0.041*sl t phl 0.55 0.49 + 0.033*sl 0.50 + 0.027*sl 0.52 + 0.024*sl t r 0.30 0.13 + 0.085*sl 0.13 + 0.087*sl 0.11 + 0.089*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.040*sl 0.11 + 0.040*sl sn to q t plh 0.69 0.60 + 0.044*sl 0.60 + 0.041*sl 0.61 + 0.041*sl t r 0.29 0.12 + 0.086*sl 0.12 + 0.088*sl 0.10 + 0.090*sl rn to q t plh 0.31 0.22 + 0.044*sl 0.23 + 0.041*sl 0.23 + 0.042*sl t phl 0.34 0.28 + 0.033*sl 0.29 + 0.026*sl 0.31 + 0.024*sl t r 0.29 0.12 + 0.084*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.040*sl 0.10 + 0.041*sl ck to qn t plh 0.89 0.79 + 0.045*sl 0.80 + 0.042*sl 0.81 + 0.041*sl t phl 0.76 0.69 + 0.036*sl 0.71 + 0.028*sl 0.73 + 0.025*sl t r 0.32 0.15 + 0.084*sl 0.15 + 0.086*sl 0.13 + 0.089*sl t f 0.22 0.13 + 0.043*sl 0.14 + 0.040*sl 0.13 + 0.041*sl sck to qn t plh 0.75 0.66 + 0.042*sl 0.66 + 0.041*sl 0.66 + 0.041*sl t phl 0.73 0.67 + 0.030*sl 0.68 + 0.025*sl 0.69 + 0.023*sl t r 0.28 0.11 + 0.086*sl 0.11 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.041*sl sn to qn t plh 0.40 0.31 + 0.047*sl 0.32 + 0.043*sl 0.33 + 0.041*sl t phl 0.41 0.34 + 0.038*sl 0.36 + 0.028*sl 0.39 + 0.024*sl t r 0.32 0.15 + 0.085*sl 0.15 + 0.086*sl 0.13 + 0.088*sl t f 0.23 0.14 + 0.041*sl 0.15 + 0.038*sl 0.14 + 0.039*sl rn to qn t plh 0.65 0.56 + 0.045*sl 0.57 + 0.042*sl 0.57 + 0.041*sl t r 0.32 0.15 + 0.084*sl 0.15 + 0.086*sl 0.13 + 0.088*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-254 sec asic fd4cs/fd4csd2 d flip-flop with reset, set, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd4csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.58 0.53 + 0.025*sl 0.54 + 0.022*sl 0.55 + 0.021*sl t phl 0.58 0.54 + 0.021*sl 0.55 + 0.016*sl 0.57 + 0.014*sl t r 0.20 0.11 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.044*sl t f 0.15 0.11 + 0.022*sl 0.11 + 0.020*sl 0.11 + 0.020*sl sck to q t plh 0.65 0.60 + 0.025*sl 0.61 + 0.022*sl 0.62 + 0.021*sl t phl 0.56 0.51 + 0.021*sl 0.53 + 0.016*sl 0.54 + 0.014*sl t r 0.21 0.13 + 0.042*sl 0.13 + 0.042*sl 0.12 + 0.043*sl t f 0.17 0.12 + 0.021*sl 0.13 + 0.020*sl 0.13 + 0.019*sl sn to q t plh 0.68 0.63 + 0.025*sl 0.64 + 0.022*sl 0.65 + 0.021*sl t r 0.20 0.11 + 0.042*sl 0.11 + 0.042*sl 0.11 + 0.043*sl rn to q t plh 0.30 0.25 + 0.025*sl 0.25 + 0.022*sl 0.26 + 0.021*sl t phl 0.34 0.29 + 0.023*sl 0.31 + 0.017*sl 0.33 + 0.014*sl t r 0.20 0.12 + 0.042*sl 0.12 + 0.041*sl 0.10 + 0.044*sl t f 0.16 0.12 + 0.023*sl 0.12 + 0.020*sl 0.13 + 0.019*sl ck to qn t plh 0.94 0.89 + 0.026*sl 0.90 + 0.022*sl 0.91 + 0.021*sl t phl 0.82 0.77 + 0.023*sl 0.78 + 0.017*sl 0.80 + 0.015*sl t r 0.23 0.15 + 0.042*sl 0.15 + 0.042*sl 0.14 + 0.043*sl t f 0.19 0.14 + 0.026*sl 0.16 + 0.020*sl 0.16 + 0.020*sl sck to qn t plh 0.81 0.77 + 0.022*sl 0.78 + 0.020*sl 0.77 + 0.020*sl t phl 0.80 0.76 + 0.018*sl 0.77 + 0.015*sl 0.78 + 0.013*sl t r 0.19 0.11 + 0.042*sl 0.11 + 0.043*sl 0.10 + 0.043*sl t f 0.15 0.11 + 0.021*sl 0.11 + 0.019*sl 0.11 + 0.020*sl sn to qn t plh 0.40 0.34 + 0.028*sl 0.36 + 0.023*sl 0.37 + 0.021*sl t phl 0.41 0.36 + 0.026*sl 0.38 + 0.018*sl 0.40 + 0.015*sl t r 0.23 0.15 + 0.043*sl 0.15 + 0.042*sl 0.15 + 0.042*sl t f 0.20 0.15 + 0.026*sl 0.16 + 0.019*sl 0.17 + 0.018*sl rn to qn t plh 0.71 0.65 + 0.026*sl 0.67 + 0.022*sl 0.67 + 0.021*sl t r 0.23 0.15 + 0.041*sl 0.15 + 0.043*sl 0.15 + 0.042*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-255 kg80/KGM80 fd4cs/fd4csd2 d flip-flop with reset, set, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd4cs path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.82 0.71 + 0.054*sl 0.72 + 0.051*sl 0.73 + 0.050*sl t phl 0.83 0.76 + 0.036*sl 0.78 + 0.027*sl 0.81 + 0.024*sl t r 0.38 0.17 + 0.104*sl 0.16 + 0.107*sl 0.14 + 0.108*sl t f 0.22 0.13 + 0.043*sl 0.14 + 0.042*sl 0.13 + 0.042*sl sck to q t plh 0.96 0.84 + 0.056*sl 0.86 + 0.051*sl 0.87 + 0.050*sl t phl 0.78 0.71 + 0.037*sl 0.73 + 0.028*sl 0.77 + 0.024*sl t r 0.39 0.18 + 0.104*sl 0.18 + 0.106*sl 0.16 + 0.108*sl t f 0.23 0.14 + 0.044*sl 0.15 + 0.041*sl 0.15 + 0.042*sl sn to q t plh 0.97 0.86 + 0.054*sl 0.87 + 0.050*sl 0.88 + 0.050*sl t r 0.38 0.17 + 0.104*sl 0.17 + 0.106*sl 0.14 + 0.108*sl rn to q t plh 0.42 0.31 + 0.054*sl 0.32 + 0.050*sl 0.33 + 0.050*sl t phl 0.45 0.38 + 0.036*sl 0.40 + 0.027*sl 0.43 + 0.024*sl t r 0.37 0.17 + 0.104*sl 0.16 + 0.107*sl 0.14 + 0.109*sl t f 0.22 0.14 + 0.043*sl 0.14 + 0.042*sl 0.14 + 0.042*sl ck to qn t plh 1.25 1.13 + 0.059*sl 1.16 + 0.051*sl 1.17 + 0.050*sl t phl 1.09 1.01 + 0.040*sl 1.04 + 0.030*sl 1.08 + 0.026*sl t r 0.42 0.22 + 0.105*sl 0.22 + 0.104*sl 0.18 + 0.107*sl t f 0.26 0.17 + 0.045*sl 0.17 + 0.043*sl 0.18 + 0.042*sl sck to qn t plh 1.06 0.96 + 0.051*sl 0.97 + 0.050*sl 0.96 + 0.050*sl t phl 1.08 1.02 + 0.033*sl 1.04 + 0.026*sl 1.06 + 0.023*sl t r 0.37 0.16 + 0.104*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.20 0.12 + 0.042*sl 0.12 + 0.041*sl 0.11 + 0.042*sl sn to qn t plh 0.54 0.42 + 0.061*sl 0.44 + 0.052*sl 0.46 + 0.050*sl t phl 0.55 0.47 + 0.042*sl 0.50 + 0.030*sl 0.56 + 0.025*sl t r 0.42 0.22 + 0.104*sl 0.21 + 0.104*sl 0.18 + 0.107*sl t f 0.27 0.17 + 0.047*sl 0.19 + 0.041*sl 0.19 + 0.041*sl rn to qn t plh 0.88 0.76 + 0.059*sl 0.78 + 0.051*sl 0.80 + 0.050*sl t r 0.42 0.21 + 0.105*sl 0.22 + 0.104*sl 0.18 + 0.107*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-256 sec asic fd4cs/fd4csd2 d flip-flop with reset, set, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd4csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.81 0.75 + 0.032*sl 0.76 + 0.027*sl 0.78 + 0.025*sl t phl 0.84 0.79 + 0.025*sl 0.81 + 0.017*sl 0.85 + 0.014*sl t r 0.26 0.15 + 0.053*sl 0.15 + 0.052*sl 0.14 + 0.053*sl t f 0.18 0.13 + 0.026*sl 0.15 + 0.021*sl 0.15 + 0.021*sl sck to q t plh 0.96 0.90 + 0.032*sl 0.91 + 0.027*sl 0.93 + 0.025*sl t phl 0.80 0.75 + 0.025*sl 0.77 + 0.018*sl 0.81 + 0.014*sl t r 0.27 0.17 + 0.053*sl 0.17 + 0.052*sl 0.16 + 0.053*sl t f 0.20 0.15 + 0.026*sl 0.16 + 0.021*sl 0.17 + 0.021*sl sn to q t plh 0.96 0.90 + 0.031*sl 0.91 + 0.027*sl 0.93 + 0.025*sl t r 0.26 0.15 + 0.054*sl 0.16 + 0.052*sl 0.14 + 0.053*sl rn to q t plh 0.40 0.34 + 0.032*sl 0.35 + 0.027*sl 0.37 + 0.025*sl t phl 0.45 0.40 + 0.026*sl 0.42 + 0.018*sl 0.47 + 0.014*sl t r 0.25 0.14 + 0.054*sl 0.15 + 0.052*sl 0.14 + 0.053*sl t f 0.19 0.14 + 0.025*sl 0.15 + 0.022*sl 0.17 + 0.020*sl ck to qn t plh 1.34 1.27 + 0.033*sl 1.28 + 0.028*sl 1.31 + 0.025*sl t phl 1.17 1.12 + 0.027*sl 1.14 + 0.019*sl 1.18 + 0.015*sl t r 0.30 0.19 + 0.056*sl 0.20 + 0.052*sl 0.20 + 0.052*sl t f 0.23 0.17 + 0.029*sl 0.19 + 0.023*sl 0.21 + 0.021*sl sck to qn t plh 1.17 1.11 + 0.028*sl 1.12 + 0.025*sl 1.12 + 0.025*sl t phl 1.20 1.16 + 0.021*sl 1.17 + 0.016*sl 1.20 + 0.013*sl t r 0.25 0.14 + 0.054*sl 0.15 + 0.052*sl 0.14 + 0.053*sl t f 0.18 0.13 + 0.026*sl 0.14 + 0.021*sl 0.15 + 0.020*sl sn to qn t plh 0.53 0.46 + 0.035*sl 0.48 + 0.029*sl 0.52 + 0.026*sl t phl 0.56 0.50 + 0.030*sl 0.53 + 0.020*sl 0.59 + 0.015*sl t r 0.30 0.19 + 0.056*sl 0.20 + 0.052*sl 0.20 + 0.052*sl t f 0.24 0.18 + 0.028*sl 0.20 + 0.022*sl 0.22 + 0.020*sl rn to qn t plh 0.96 0.89 + 0.034*sl 0.91 + 0.028*sl 0.94 + 0.025*sl t r 0.30 0.19 + 0.057*sl 0.20 + 0.052*sl 0.20 + 0.052*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-257 kg80/KGM80 fd4s/fd4sd2 d flip-flop with reset, set, scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 fd4s fd4sd2 fd4s fd4sd2 d ti te ck rn sn d ti te ck rn sn 0.9 0.7 1.6 0.9 1.9 1.7 0.9 0.7 1.6 0.9 1.9 1.7 11.0 12.0 KGM80 fd4s fd4sd2 fd4s fd4sd2 d ti te ck rn sn d ti te ck rn sn 1.0 0.9 1.9 1.1 2.3 2.1 1.0 0.9 1.9 1.1 2.3 2.1 11.0 12.0 q qn d ti te ck rn sn cl clb q cl clb cl cl clb qn clb sn sn rn rn d ti ck cl clb rn rn sn sn te truth table dtiteckrnsn q (n+1) qn (n+1) 0x0 11 0 1 1x0 11 1 0 x01 11 0 1 x11 11 1 0 xxxx10 1 0 xxxx01 0 1 xxxx00 0 0 x x x 1 1 q (n) qn (n)
kg80/KGM80 3-258 sec asic fd4s/fd4sd2 d flip-flop with reset, set, scan, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 fd4s fd4sd2 fd4s fd4sd2 pulse width low (ck) t pwl 0.61 0.61 1.02 1.02 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 0.99 pulse width low (sn) t pwl 0.64 0.64 1.05 1.05 input setup time (d to ck) t su 0.53 0.53 0.93 0.93 input hold time (d to ck) t hd 0.15 0.15 0.33 0.33 input setup time (ti to ck) t su 0.58 0.58 1.05 1.05 input hold time (ti to ck) t hd 0.15 0.15 0.33 0.33 input setup time (te to ck) t su 0.56 0.56 0.99 0.99 input hold time (te to ck) t hd 0.15 0.15 0.33 0.33 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ck) t hd 0.42 0.42 0.85 0.85 recovery time (sn) t rc 0.15 0.15 0.33 0.33 input hold time (sn to ck) t hd 0.15 0.15 0.41 0.41
sec asic 3-259 kg80/KGM80 fd4s/fd4sd2 d flip-flop with reset, set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd4s kg80 fd4sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.57 0.48 + 0.044*sl 0.49 + 0.042*sl 0.49 + 0.042*sl t phl 0.57 0.51 + 0.031*sl 0.52 + 0.026*sl 0.54 + 0.024*sl t r 0.29 0.11 + 0.086*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.09 + 0.041*sl 0.09 + 0.041*sl 0.09 + 0.041*sl rn to q t plh 0.29 0.20 + 0.043*sl 0.21 + 0.041*sl 0.21 + 0.042*sl t phl 0.33 0.27 + 0.032*sl 0.28 + 0.026*sl 0.30 + 0.024*sl t r 0.28 0.11 + 0.085*sl 0.11 + 0.088*sl 0.09 + 0.090*sl t f 0.19 0.11 + 0.039*sl 0.11 + 0.040*sl 0.10 + 0.041*sl sn to q t plh 0.66 0.58 + 0.043*sl 0.58 + 0.041*sl 0.58 + 0.041*sl t r 0.29 0.12 + 0.085*sl 0.11 + 0.088*sl 0.10 + 0.090*sl ck to qn t plh 0.78 0.69 + 0.042*sl 0.69 + 0.041*sl 0.69 + 0.042*sl t phl 0.66 0.60 + 0.030*sl 0.61 + 0.025*sl 0.62 + 0.024*sl t r 0.28 0.11 + 0.086*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl rn to qn t plh 0.54 0.45 + 0.042*sl 0.45 + 0.041*sl 0.45 + 0.041*sl t r 0.28 0.11 + 0.086*sl 0.10 + 0.088*sl 0.09 + 0.090*sl sn to qn t plh 0.31 0.22 + 0.044*sl 0.22 + 0.041*sl 0.22 + 0.042*sl t phl 0.33 0.27 + 0.032*sl 0.28 + 0.026*sl 0.30 + 0.024*sl t r 0.29 0.11 + 0.088*sl 0.12 + 0.086*sl 0.09 + 0.090*sl t f 0.18 0.11 + 0.040*sl 0.11 + 0.039*sl 0.10 + 0.041*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.56 0.51 + 0.025*sl 0.52 + 0.022*sl 0.52 + 0.021*sl t phl 0.57 0.53 + 0.021*sl 0.54 + 0.016*sl 0.56 + 0.013*sl t r 0.19 0.11 + 0.042*sl 0.10 + 0.043*sl 0.10 + 0.044*sl t f 0.15 0.10 + 0.021*sl 0.11 + 0.020*sl 0.11 + 0.020*sl rn to q t plh 0.28 0.23 + 0.024*sl 0.23 + 0.022*sl 0.24 + 0.021*sl t phl 0.32 0.28 + 0.021*sl 0.29 + 0.016*sl 0.31 + 0.013*sl t r 0.19 0.10 + 0.041*sl 0.10 + 0.043*sl 0.10 + 0.043*sl t f 0.15 0.11 + 0.023*sl 0.12 + 0.020*sl 0.11 + 0.020*sl sn to q t plh 0.66 0.61 + 0.024*sl 0.61 + 0.022*sl 0.62 + 0.021*sl t r 0.19 0.11 + 0.042*sl 0.11 + 0.043*sl 0.10 + 0.043*sl ck to qn t plh 0.82 0.77 + 0.023*sl 0.78 + 0.020*sl 0.78 + 0.020*sl t phl 0.71 0.67 + 0.019*sl 0.68 + 0.015*sl 0.69 + 0.013*sl t r 0.19 0.11 + 0.041*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.15 0.10 + 0.022*sl 0.11 + 0.019*sl 0.11 + 0.020*sl rn to qn t plh 0.58 0.53 + 0.023*sl 0.54 + 0.020*sl 0.53 + 0.020*sl t r 0.19 0.10 + 0.042*sl 0.10 + 0.043*sl 0.10 + 0.043*sl sn to qn t plh 0.29 0.24 + 0.024*sl 0.25 + 0.022*sl 0.26 + 0.021*sl t phl 0.33 0.28 + 0.022*sl 0.30 + 0.016*sl 0.32 + 0.014*sl t r 0.19 0.11 + 0.040*sl 0.11 + 0.041*sl 0.09 + 0.044*sl t f 0.15 0.11 + 0.022*sl 0.12 + 0.020*sl 0.12 + 0.019*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 7, *grou p 3 : 7 < sl < < = =
kg80/KGM80 3-260 sec asic fd4s/fd4sd2 d flip-flop with reset, set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd4s KGM80 fd4sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.79 0.68 + 0.055*sl 0.70 + 0.051*sl 0.70 + 0.050*sl t phl 0.80 0.73 + 0.035*sl 0.76 + 0.027*sl 0.79 + 0.024*sl t r 0.37 0.16 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.042*sl 0.12 + 0.042*sl rn to q t plh 0.39 0.28 + 0.054*sl 0.30 + 0.050*sl 0.30 + 0.050*sl t phl 0.43 0.36 + 0.035*sl 0.38 + 0.027*sl 0.41 + 0.024*sl t r 0.37 0.16 + 0.104*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.22 0.13 + 0.043*sl 0.13 + 0.042*sl 0.13 + 0.042*sl sn to q t plh 0.93 0.82 + 0.054*sl 0.83 + 0.050*sl 0.84 + 0.050*sl t r 0.37 0.17 + 0.103*sl 0.16 + 0.106*sl 0.13 + 0.109*sl ck to qn t plh 1.10 1.00 + 0.052*sl 1.00 + 0.050*sl 1.00 + 0.050*sl t phl 0.94 0.87 + 0.034*sl 0.89 + 0.026*sl 0.92 + 0.024*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.046*sl 0.13 + 0.041*sl 0.12 + 0.042*sl rn to qn t plh 0.73 0.62 + 0.052*sl 0.63 + 0.050*sl 0.63 + 0.050*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.12 + 0.109*sl sn to qn t plh 0.42 0.31 + 0.055*sl 0.32 + 0.050*sl 0.33 + 0.050*sl t phl 0.44 0.37 + 0.037*sl 0.39 + 0.027*sl 0.43 + 0.024*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.22 0.13 + 0.045*sl 0.14 + 0.041*sl 0.13 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.78 0.71 + 0.031*sl 0.73 + 0.027*sl 0.74 + 0.025*sl t phl 0.81 0.76 + 0.024*sl 0.78 + 0.017*sl 0.82 + 0.013*sl t r 0.24 0.14 + 0.053*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.17 0.12 + 0.024*sl 0.13 + 0.021*sl 0.14 + 0.021*sl rn to q t plh 0.37 0.31 + 0.031*sl 0.32 + 0.026*sl 0.34 + 0.025*sl t phl 0.43 0.38 + 0.025*sl 0.40 + 0.017*sl 0.44 + 0.013*sl t r 0.24 0.14 + 0.053*sl 0.14 + 0.052*sl 0.12 + 0.053*sl t f 0.18 0.13 + 0.026*sl 0.14 + 0.021*sl 0.15 + 0.021*sl sn to q t plh 0.92 0.86 + 0.031*sl 0.87 + 0.026*sl 0.89 + 0.025*sl t r 0.25 0.14 + 0.053*sl 0.15 + 0.052*sl 0.13 + 0.053*sl ck to qn t plh 1.16 1.10 + 0.029*sl 1.11 + 0.025*sl 1.12 + 0.025*sl t phl 1.01 0.97 + 0.022*sl 0.98 + 0.016*sl 1.01 + 0.013*sl t r 0.24 0.14 + 0.054*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.18 0.13 + 0.024*sl 0.13 + 0.021*sl 0.15 + 0.020*sl rn to qn t plh 0.78 0.72 + 0.029*sl 0.74 + 0.025*sl 0.74 + 0.025*sl t r 0.24 0.14 + 0.054*sl 0.14 + 0.052*sl 0.13 + 0.053*sl sn to qn t plh 0.40 0.34 + 0.031*sl 0.35 + 0.027*sl 0.37 + 0.025*sl t phl 0.44 0.39 + 0.026*sl 0.41 + 0.017*sl 0.45 + 0.014*sl t r 0.24 0.13 + 0.053*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.18 0.13 + 0.026*sl 0.14 + 0.021*sl 0.15 + 0.020*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 11, *grou p 3 : 11 < sl < < = =
sec asic 3-261 kg80/KGM80 fd4q/fd4qd2 d flip-flop with reset, set, q output only, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 fd4q fd4qd2 fd4q fd4qd2 d ck rn sn d ck rn sn 0.8 0.8 1.5 1.5 0.8 0.8 1.5 1.5 8.0 9.0 KGM80 fd4q fd4qd2 fd4q fd4qd2 d ck rn sn d ck rn sn 0.9 0.9 1.7 1.7 0.9 0.9 1.7 1.7 8.0 9.0 d ck q sn rn d ck cl clb q cl clb cl clb cl cl clb clb sn sn rn rn rn rn sn sn truth table d ck rn sn q (n+1) 0110 1111 xx101 xx010 xx000 x 1 1 q (n)
kg80/KGM80 3-262 sec asic fd4q/fd4qd2 d flip-flop with reset, set, q output only, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd4q kg80 fd4qd2 parameter symbol kg80 KGM80 fd4q fd4qd2 fd4q fd4qd2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 0.99 pulse width low (sn) t pwl 0.64 0.64 1.05 1.05 input setup time (d to ck) t su 0.45 0.45. 0.80 0.80 input hold time (d to ck) t hd 0.15 0.15 0.33 0.33 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ck) t hd 0.42 0.42 0.63 0.63 recovery time (sn) t rc 0.15 0.15 0.33 0.33 input hold time (sn to ck) t hd 0.15 0.15 0.41 0.41 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.56 0.47 + 0.045*sl 0.48 + 0.042*sl 0.48 + 0.042*sl t phl 0.54 0.47 + 0.031*sl 0.49 + 0.026*sl 0.50 + 0.024*sl t r 0.28 0.11 + 0.087*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.09 + 0.041*sl rn to q t plh 0.29 0.20 + 0.044*sl 0.21 + 0.041*sl 0.21 + 0.041*sl t phl 0.33 0.27 + 0.033*sl 0.28 + 0.026*sl 0.30 + 0.024*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.040*sl 0.10 + 0.040*sl sn to q t plh 0.66 0.57 + 0.043*sl 0.58 + 0.041*sl 0.58 + 0.042*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.55 0.51 + 0.024*sl 0.51 + 0.022*sl 0.52 + 0.021*sl t phl 0.54 0.50 + 0.019*sl 0.51 + 0.015*sl 0.52 + 0.013*sl t r 0.21 0.12 + 0.044*sl 0.12 + 0.043*sl 0.11 + 0.044*sl t f 0.15 0.11 + 0.022*sl 0.11 + 0.020*sl 0.12 + 0.019*sl rn to q t plh 0.28 0.24 + 0.023*sl 0.24 + 0.022*sl 0.25 + 0.021*sl t phl 0.33 0.29 + 0.020*sl 0.30 + 0.016*sl 0.32 + 0.013*sl t r 0.20 0.11 + 0.043*sl 0.11 + 0.043*sl 0.11 + 0.045*sl t f 0.16 0.12 + 0.021*sl 0.12 + 0.020*sl 0.13 + 0.019*sl sn to q t plh 0.66 0.61 + 0.024*sl 0.62 + 0.021*sl 0.62 + 0.021*sl t r 0.20 0.12 + 0.042*sl 0.12 + 0.044*sl 0.11 + 0.044*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-263 kg80/KGM80 fd4q/fd4qd2 d flip-flop with reset, set, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd4q KGM80 fd4qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.80 0.69 + 0.055*sl 0.70 + 0.051*sl 0.71 + 0.050*sl t phl 0.77 0.69 + 0.035*sl 0.72 + 0.027*sl 0.75 + 0.024*sl t r 0.37 0.16 + 0.105*sl 0.15 + 0.107*sl 0.13 + 0.108*sl t f 0.21 0.12 + 0.045*sl 0.13 + 0.042*sl 0.12 + 0.042*sl rn to q t plh 0.40 0.29 + 0.054*sl 0.30 + 0.050*sl 0.30 + 0.050*sl t phl 0.44 0.36 + 0.037*sl 0.39 + 0.027*sl 0.43 + 0.024*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.22 0.13 + 0.045*sl 0.14 + 0.041*sl 0.13 + 0.042*sl sn to q t plh 0.94 0.83 + 0.054*sl 0.84 + 0.050*sl 0.84 + 0.050*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.108*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.79 0.73 + 0.030*sl 0.74 + 0.027*sl 0.76 + 0.025*sl t phl 0.78 0.73 + 0.022*sl 0.75 + 0.016*sl 0.78 + 0.013*sl t r 0.27 0.16 + 0.053*sl 0.16 + 0.052*sl 0.16 + 0.053*sl t f 0.18 0.13 + 0.024*sl 0.14 + 0.021*sl 0.15 + 0.020*sl rn to q t plh 0.39 0.33 + 0.030*sl 0.34 + 0.026*sl 0.35 + 0.025*sl t phl 0.44 0.39 + 0.023*sl 0.41 + 0.017*sl 0.45 + 0.013*sl t r 0.26 0.16 + 0.053*sl 0.16 + 0.052*sl 0.15 + 0.053*sl t f 0.19 0.14 + 0.025*sl 0.15 + 0.021*sl 0.16 + 0.020*sl sn to q t plh 0.94 0.88 + 0.030*sl 0.89 + 0.026*sl 0.90 + 0.025*sl t r 0.27 0.16 + 0.052*sl 0.17 + 0.052*sl 0.15 + 0.053*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-264 sec asic fd4x2 2-bit d flip-flop with reset, set logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 pulse width low (ck) t pwl 0.64 1.05 pulse width high (ck) t pwh 0.61 0.99 pulse width low (rn) t pwl 0.61 0.99 pulse width low (sn) t pwl 0.61 1.02 input setup time (d0 to ck) t su 0.34 0.64 input hold time (d0 to ck) t hd 0.15 0.33 input setup time (d1 to ck) t su 0.34 0.64 input hold time (d1 to ck) t hd 0.15 0.33 recovery time (rn) t rc 0.15 0.33 input hold time (rn to ck) t hd 0.48 0.85 recovery time (sn) t rc 0.15 0.33 input hold time (sn to ck) t hd 0.26 0.41 q0 qn1 d0 d1 ck rn sn q1 qn0 truth table cell data dn ck rn sn qn (n+1) qnn (n+1) 01101 11110 xx10 1 0 xx01 0 1 xx00 0 0 x 1 1 qn (n) qnn (n) input load (sl) gate count kg80 dn ck rn sn 16.0 0.9 0.9 3.9 3.8 KGM80 dn ck rn sn 16.0 1.0 1.0 4.9 4.7
sec asic 3-265 kg80/KGM80 fd4x2 2-bit d flip-flop with reset, set switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd4x2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.63 0.54 + 0.043*sl 0.54 + 0.042*sl 0.55 + 0.042*sl t phl 0.68 0.62 + 0.031*sl 0.63 + 0.026*sl 0.65 + 0.024*sl t r 0.28 0.11 + 0.086*sl 0.11 + 0.089*sl 0.10 + 0.090*sl t f 0.18 0.09 + 0.041*sl 0.10 + 0.040*sl 0.09 + 0.041*sl rn to q0 t plh 0.29 0.20 + 0.044*sl 0.21 + 0.041*sl 0.21 + 0.042*sl t phl 0.33 0.27 + 0.032*sl 0.28 + 0.026*sl 0.30 + 0.024*sl t r 0.28 0.11 + 0.084*sl 0.11 + 0.088*sl 0.09 + 0.090*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.039*sl 0.10 + 0.041*sl sn to q0 t plh 0.65 0.57 + 0.043*sl 0.57 + 0.041*sl 0.57 + 0.041*sl t r 0.29 0.11 + 0.085*sl 0.11 + 0.088*sl 0.10 + 0.090*sl ck to q1 t plh 0.63 0.54 + 0.044*sl 0.55 + 0.042*sl 0.55 + 0.042*sl t phl 0.68 0.62 + 0.031*sl 0.63 + 0.026*sl 0.65 + 0.024*sl t r 0.28 0.11 + 0.086*sl 0.11 + 0.089*sl 0.10 + 0.090*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.040*sl 0.09 + 0.041*sl rn to q1 t plh 0.29 0.20 + 0.044*sl 0.21 + 0.041*sl 0.21 + 0.042*sl t phl 0.33 0.27 + 0.032*sl 0.28 + 0.026*sl 0.30 + 0.024*sl t r 0.28 0.11 + 0.084*sl 0.11 + 0.088*sl 0.09 + 0.090*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.039*sl 0.10 + 0.041*sl sn to q1 t plh 0.65 0.56 + 0.043*sl 0.57 + 0.041*sl 0.57 + 0.042*sl t r 0.29 0.11 + 0.085*sl 0.11 + 0.088*sl 0.10 + 0.090*sl ck to qn0 t plh 0.89 0.80 + 0.042*sl 0.81 + 0.041*sl 0.80 + 0.041*sl t phl 0.72 0.66 + 0.030*sl 0.67 + 0.026*sl 0.68 + 0.024*sl t r 0.28 0.11 + 0.086*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.09 + 0.041*sl rn to qn0 t plh 0.54 0.45 + 0.042*sl 0.46 + 0.041*sl 0.45 + 0.041*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl sn to qn0 t plh 0.31 0.22 + 0.043*sl 0.22 + 0.042*sl 0.23 + 0.041*sl t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.30 + 0.024*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.18 0.11 + 0.039*sl 0.11 + 0.039*sl 0.10 + 0.041*sl ck to qn1 t plh 0.89 0.80 + 0.043*sl 0.81 + 0.041*sl 0.80 + 0.041*sl t phl 0.72 0.66 + 0.030*sl 0.67 + 0.026*sl 0.68 + 0.024*sl t r 0.28 0.11 + 0.086*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.09 + 0.041*sl rn to qn1 t plh 0.54 0.45 + 0.042*sl 0.46 + 0.041*sl 0.45 + 0.041*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl sn to qn1 t plh 0.31 0.22 + 0.043*sl 0.22 + 0.042*sl 0.23 + 0.041*sl t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.30 + 0.024*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.18 0.11 + 0.039*sl 0.11 + 0.039*sl 0.10 + 0.041*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-266 sec asic fd4x2 2-bit d flip-flop with reset, set switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd4x2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.87 0.76 + 0.054*sl 0.77 + 0.051*sl 0.78 + 0.050*sl t phl 0.96 0.89 + 0.035*sl 0.91 + 0.027*sl 0.94 + 0.024*sl t r 0.37 0.16 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.042*sl 0.12 + 0.042*sl rn to q0 t plh 0.39 0.28 + 0.054*sl 0.30 + 0.050*sl 0.30 + 0.050*sl t phl 0.43 0.36 + 0.035*sl 0.38 + 0.027*sl 0.41 + 0.024*sl t r 0.37 0.16 + 0.104*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.22 0.13 + 0.043*sl 0.13 + 0.042*sl 0.13 + 0.042*sl sn to q0 t plh 0.91 0.80 + 0.053*sl 0.81 + 0.050*sl 0.82 + 0.050*sl t r 0.37 0.17 + 0.103*sl 0.16 + 0.106*sl 0.13 + 0.109*sl ck to q1 t plh 0.87 0.76 + 0.054*sl 0.77 + 0.051*sl 0.78 + 0.050*sl t phl 0.96 0.89 + 0.035*sl 0.91 + 0.027*sl 0.94 + 0.024*sl t r 0.37 0.16 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.042*sl 0.12 + 0.042*sl rn to q1 t plh 0.39 0.28 + 0.054*sl 0.30 + 0.050*sl 0.30 + 0.050*sl t phl 0.43 0.36 + 0.035*sl 0.38 + 0.027*sl 0.41 + 0.024*sl t r 0.37 0.16 + 0.104*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.22 0.13 + 0.043*sl 0.13 + 0.042*sl 0.13 + 0.042*sl sn to q1 t plh 0.91 0.80 + 0.054*sl 0.81 + 0.050*sl 0.82 + 0.050*sl t r 0.37 0.17 + 0.103*sl 0.16 + 0.106*sl 0.13 + 0.109*sl ck to qn0 t plh 1.26 1.15 + 0.053*sl 1.16 + 0.050*sl 1.16 + 0.050*sl t phl 1.01 0.94 + 0.034*sl 0.96 + 0.026*sl 1.00 + 0.024*sl t r 0.36 0.16 + 0.104*sl 0.15 + 0.106*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.042*sl 0.12 + 0.042*sl 0.12 + 0.042*sl rn to qn0 t plh 0.73 0.62 + 0.052*sl 0.63 + 0.050*sl 0.63 + 0.050*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl sn to qn0 t plh 0.42 0.31 + 0.054*sl 0.32 + 0.050*sl 0.33 + 0.050*sl t phl 0.44 0.37 + 0.036*sl 0.40 + 0.027*sl 0.43 + 0.024*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.22 0.13 + 0.043*sl 0.14 + 0.041*sl 0.13 + 0.042*sl ck to qn1 t plh 1.26 1.15 + 0.052*sl 1.16 + 0.050*sl 1.16 + 0.050*sl t phl 1.01 0.94 + 0.034*sl 0.96 + 0.026*sl 1.00 + 0.024*sl t r 0.36 0.16 + 0.104*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.12 + 0.042*sl 0.12 + 0.042*sl rn to qn1 t plh 0.73 0.62 + 0.052*sl 0.63 + 0.050*sl 0.63 + 0.050*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl sn to qn1 t plh 0.42 0.31 + 0.054*sl 0.32 + 0.050*sl 0.33 + 0.050*sl t phl 0.44 0.37 + 0.036*sl 0.40 + 0.027*sl 0.43 + 0.024*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.22 0.13 + 0.043*sl 0.14 + 0.041*sl 0.13 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-267 kg80/KGM80 fd4x4 4-bit d flip-flop with reset, set logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 pulse width low (ck) t pwl 0.83 1.30 pulse width high (ck) t pwh 0.61 0.99 pulse width low (rn) t pwl 0.61 0.99 pulse width low (sn) t pwl 0.61 1.02 input setup time (d0 to ck) t su 0.23 0.46 input hold time (d0 to ck) t hd 0.26 0.43 input setup time (d1 to ck) t su 0.23 0.46 input hold time (d1 to ck) t hd 0.26 0.43 input setup time (d2 to ck) t su 0.23 0.46 input hold time (d2 to ck) t hd 0.26 0.43 input setup time (d3 to ck) t su 0.23 0.46 input hold time (d3 to ck) t hd 0.26 0.43 recovery time (rn) t rc 0.15 0.33 input hold time (rn to ck) t hd 0.59 1.07 recovery time (sn) t rc 0.15 0.33 input hold time (rn to ck) t hd 0.37 0.63 q0 q1 q2 q3 d0 d1 d2 d3 ck rn qn0 qn1 qn2 qn3 sn truth table cell data dn ck rn sn qn (n+1) qnn (n+1) 01101 11110 xx10 1 0 xx01 0 1 xx00 0 0 x 1 1 qn (n) qnn (n) input load (sl) gate count kg80 dn ck rn sn 32.0 1.0 1.1 8.3 8.0 KGM80 dn ck rn sn 32.0 1.0 1.0 9.7 9.6
kg80/KGM80 3-268 sec asic fd4x4 4-bit d flip-flop with reset, set switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd4x4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.74 0.65 + 0.045*sl 0.65 + 0.042*sl 0.66 + 0.042*sl t phl 0.89 0.83 + 0.031*sl 0.84 + 0.026*sl 0.85 + 0.024*sl t r 0.29 0.11 + 0.087*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.10 + 0.039*sl 0.10 + 0.040*sl 0.09 + 0.041*sl rn to q0 t plh 0.29 0.20 + 0.044*sl 0.21 + 0.041*sl 0.21 + 0.041*sl t phl 0.33 0.27 + 0.032*sl 0.28 + 0.026*sl 0.30 + 0.024*sl t r 0.28 0.12 + 0.084*sl 0.11 + 0.088*sl 0.09 + 0.090*sl t f 0.18 0.11 + 0.039*sl 0.11 + 0.040*sl 0.10 + 0.041*sl sn to q0 t plh 0.65 0.56 + 0.044*sl 0.57 + 0.041*sl 0.56 + 0.042*sl t r 0.28 0.11 + 0.085*sl 0.11 + 0.088*sl 0.09 + 0.090*sl ck to q1 t plh 0.73 0.64 + 0.044*sl 0.65 + 0.042*sl 0.65 + 0.042*sl t phl 0.88 0.82 + 0.031*sl 0.83 + 0.026*sl 0.85 + 0.024*sl t r 0.29 0.12 + 0.085*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.040*sl 0.09 + 0.041*sl rn to q1 t plh 0.29 0.20 + 0.044*sl 0.21 + 0.041*sl 0.21 + 0.042*sl t phl 0.33 0.27 + 0.032*sl 0.28 + 0.026*sl 0.29 + 0.024*sl t r 0.29 0.12 + 0.084*sl 0.11 + 0.088*sl 0.09 + 0.090*sl t f 0.18 0.11 + 0.039*sl 0.11 + 0.040*sl 0.10 + 0.041*sl sn to q1 t plh 0.65 0.56 + 0.043*sl 0.56 + 0.041*sl 0.56 + 0.041*sl t r 0.29 0.12 + 0.085*sl 0.11 + 0.088*sl 0.10 + 0.090*sl ck to q2 t plh 0.73 0.64 + 0.044*sl 0.65 + 0.042*sl 0.65 + 0.042*sl t phl 0.88 0.82 + 0.031*sl 0.83 + 0.026*sl 0.85 + 0.024*sl t r 0.29 0.12 + 0.085*sl 0.11 + 0.089*sl 0.10 + 0.090*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.040*sl 0.09 + 0.041*sl rn to q2 t plh 0.29 0.20 + 0.044*sl 0.21 + 0.041*sl 0.21 + 0.041*sl t phl 0.33 0.27 + 0.032*sl 0.28 + 0.026*sl 0.29 + 0.024*sl t r 0.29 0.12 + 0.084*sl 0.11 + 0.088*sl 0.09 + 0.090*sl t f 0.19 0.11 + 0.039*sl 0.11 + 0.040*sl 0.10 + 0.041*sl sn to q2 t plh 0.64 0.56 + 0.043*sl 0.56 + 0.041*sl 0.56 + 0.042*sl t r 0.29 0.12 + 0.085*sl 0.11 + 0.088*sl 0.10 + 0.090*sl ck to q3 t plh 0.74 0.65 + 0.045*sl 0.65 + 0.042*sl 0.66 + 0.042*sl t phl 0.89 0.83 + 0.031*sl 0.84 + 0.026*sl 0.85 + 0.024*sl t r 0.29 0.11 + 0.087*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.10 + 0.039*sl 0.10 + 0.040*sl 0.09 + 0.041*sl rn to q3 t plh 0.29 0.20 + 0.044*sl 0.21 + 0.041*sl 0.21 + 0.041*sl t phl 0.33 0.27 + 0.032*sl 0.28 + 0.026*sl 0.30 + 0.024*sl t r 0.28 0.12 + 0.084*sl 0.11 + 0.088*sl 0.09 + 0.090*sl t f 0.19 0.11 + 0.039*sl 0.11 + 0.040*sl 0.10 + 0.041*sl sn to q3 t plh 0.65 0.56 + 0.044*sl 0.57 + 0.041*sl 0.56 + 0.042*sl t r 0.28 0.11 + 0.085*sl 0.11 + 0.088*sl 0.09 + 0.090*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-269 kg80/KGM80 fd4x4 4-bit d flip-flop with reset, set switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd4x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to qn0 t plh 1.09 1.01 + 0.042*sl 1.01 + 0.041*sl 1.01 + 0.041*sl t phl 0.82 0.76 + 0.031*sl 0.77 + 0.025*sl 0.79 + 0.023*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl rn to qn0 t plh 0.54 0.45 + 0.042*sl 0.46 + 0.041*sl 0.45 + 0.042*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl sn to qn0 t plh 0.31 0.22 + 0.044*sl 0.22 + 0.041*sl 0.22 + 0.042*sl t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.30 + 0.024*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.18 0.11 + 0.039*sl 0.11 + 0.039*sl 0.10 + 0.040*sl ck to qn1 t plh 1.09 1.00 + 0.042*sl 1.01 + 0.041*sl 1.01 + 0.041*sl t phl 0.82 0.76 + 0.031*sl 0.77 + 0.025*sl 0.78 + 0.024*sl t r 0.28 0.11 + 0.086*sl 0.11 + 0.088*sl 0.09 + 0.090*sl t f 0.18 0.09 + 0.041*sl 0.10 + 0.040*sl 0.08 + 0.041*sl rn to qn1 t plh 0.54 0.46 + 0.042*sl 0.46 + 0.041*sl 0.46 + 0.042*sl t r 0.28 0.11 + 0.086*sl 0.11 + 0.088*sl 0.09 + 0.090*sl sn to qn1 t plh 0.31 0.22 + 0.043*sl 0.23 + 0.042*sl 0.23 + 0.041*sl t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.31 + 0.024*sl t r 0.28 0.12 + 0.085*sl 0.11 + 0.088*sl 0.09 + 0.090*sl t f 0.19 0.11 + 0.039*sl 0.11 + 0.039*sl 0.10 + 0.041*sl ck to qn2 t plh 1.09 1.01 + 0.042*sl 1.01 + 0.041*sl 1.01 + 0.041*sl t phl 0.82 0.76 + 0.030*sl 0.77 + 0.025*sl 0.78 + 0.024*sl t r 0.29 0.12 + 0.086*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.040*sl 0.09 + 0.041*sl rn to qn2 t plh 0.54 0.46 + 0.042*sl 0.46 + 0.041*sl 0.46 + 0.041*sl t r 0.29 0.12 + 0.086*sl 0.11 + 0.088*sl 0.10 + 0.090*sl sn to qn2 t plh 0.31 0.23 + 0.044*sl 0.23 + 0.041*sl 0.23 + 0.041*sl t phl 0.34 0.28 + 0.033*sl 0.29 + 0.026*sl 0.31 + 0.024*sl t r 0.29 0.12 + 0.085*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.19 0.11 + 0.039*sl 0.11 + 0.039*sl 0.10 + 0.041*sl ck to qn3 t plh 1.09 1.01 + 0.042*sl 1.01 + 0.041*sl 1.01 + 0.041*sl t phl 0.82 0.76 + 0.031*sl 0.77 + 0.025*sl 0.79 + 0.023*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl rn to qn3 t plh 0.54 0.45 + 0.042*sl 0.46 + 0.041*sl 0.45 + 0.042*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl sn to qn3 t plh 0.31 0.22 + 0.044*sl 0.22 + 0.041*sl 0.22 + 0.042*sl t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.30 + 0.024*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.18 0.11 + 0.039*sl 0.11 + 0.039*sl 0.10 + 0.040*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-270 sec asic fd4x4 4-bit d flip-flop with reset, set switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd4x4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.99 0.88 + 0.054*sl 0.89 + 0.051*sl 0.90 + 0.050*sl t phl 1.24 1.17 + 0.035*sl 1.20 + 0.027*sl 1.23 + 0.024*sl t r 0.37 0.16 + 0.106*sl 0.16 + 0.107*sl 0.14 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.042*sl 0.12 + 0.042*sl rn to q0 t plh 0.39 0.28 + 0.054*sl 0.29 + 0.050*sl 0.30 + 0.050*sl t phl 0.43 0.36 + 0.036*sl 0.38 + 0.027*sl 0.41 + 0.024*sl t r 0.37 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.21 0.13 + 0.042*sl 0.13 + 0.042*sl 0.13 + 0.042*sl sn to q0 t plh 0.90 0.79 + 0.054*sl 0.80 + 0.050*sl 0.81 + 0.050*sl t r 0.37 0.16 + 0.103*sl 0.16 + 0.106*sl 0.13 + 0.109*sl ck to q1 t plh 0.98 0.87 + 0.054*sl 0.88 + 0.051*sl 0.89 + 0.050*sl t phl 1.24 1.17 + 0.034*sl 1.19 + 0.027*sl 1.22 + 0.024*sl t r 0.37 0.16 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.109*sl t f 0.21 0.13 + 0.042*sl 0.13 + 0.042*sl 0.12 + 0.042*sl rn to q1 t plh 0.39 0.28 + 0.054*sl 0.29 + 0.050*sl 0.30 + 0.050*sl t phl 0.43 0.36 + 0.036*sl 0.38 + 0.027*sl 0.41 + 0.024*sl t r 0.37 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.22 0.13 + 0.043*sl 0.13 + 0.042*sl 0.13 + 0.042*sl sn to q1 t plh 0.90 0.79 + 0.054*sl 0.80 + 0.050*sl 0.80 + 0.050*sl t r 0.37 0.17 + 0.103*sl 0.16 + 0.107*sl 0.14 + 0.109*sl ck to q2 t plh 0.98 0.87 + 0.054*sl 0.88 + 0.051*sl 0.89 + 0.050*sl t phl 1.24 1.17 + 0.034*sl 1.19 + 0.027*sl 1.22 + 0.024*sl t r 0.37 0.16 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.042*sl 0.12 + 0.042*sl rn to q2 t plh 0.39 0.28 + 0.054*sl 0.29 + 0.050*sl 0.30 + 0.050*sl t phl 0.43 0.36 + 0.035*sl 0.38 + 0.027*sl 0.41 + 0.024*sl t r 0.37 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.22 0.13 + 0.042*sl 0.13 + 0.042*sl 0.13 + 0.042*sl sn to q2 t plh 0.90 0.79 + 0.054*sl 0.80 + 0.050*sl 0.80 + 0.050*sl t r 0.37 0.17 + 0.104*sl 0.16 + 0.106*sl 0.14 + 0.109*sl ck to q3 t plh 0.99 0.88 + 0.054*sl 0.89 + 0.051*sl 0.90 + 0.050*sl t phl 1.24 1.17 + 0.035*sl 1.20 + 0.027*sl 1.23 + 0.024*sl t r 0.37 0.16 + 0.106*sl 0.16 + 0.107*sl 0.14 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.042*sl 0.12 + 0.042*sl rn to q3 t plh 0.39 0.28 + 0.054*sl 0.29 + 0.050*sl 0.30 + 0.050*sl t phl 0.43 0.36 + 0.036*sl 0.38 + 0.027*sl 0.41 + 0.024*sl t r 0.37 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.21 0.13 + 0.043*sl 0.13 + 0.042*sl 0.13 + 0.042*sl sn to q3 t plh 0.90 0.79 + 0.054*sl 0.80 + 0.050*sl 0.81 + 0.050*sl t r 0.37 0.16 + 0.103*sl 0.16 + 0.106*sl 0.13 + 0.109*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-271 kg80/KGM80 fd4x4 4-bit d flip-flop with reset, set switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd4x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to qn0 t plh 1.54 1.43 + 0.052*sl 1.44 + 0.050*sl 1.44 + 0.050*sl t phl 1.14 1.07 + 0.034*sl 1.09 + 0.026*sl 1.12 + 0.024*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.12 + 0.042*sl 0.12 + 0.042*sl rn to qn0 t plh 0.73 0.62 + 0.052*sl 0.63 + 0.050*sl 0.63 + 0.050*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl sn to qn0 t plh 0.42 0.31 + 0.055*sl 0.32 + 0.050*sl 0.33 + 0.050*sl t phl 0.44 0.37 + 0.037*sl 0.39 + 0.027*sl 0.43 + 0.024*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.041*sl 0.13 + 0.042*sl ck to qn1 t plh 1.54 1.44 + 0.052*sl 1.44 + 0.050*sl 1.44 + 0.050*sl t phl 1.13 1.06 + 0.034*sl 1.09 + 0.026*sl 1.12 + 0.024*sl t r 0.37 0.16 + 0.103*sl 0.15 + 0.106*sl 0.13 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.12 + 0.042*sl rn to qn1 t plh 0.73 0.63 + 0.053*sl 0.64 + 0.050*sl 0.64 + 0.050*sl t r 0.37 0.16 + 0.104*sl 0.15 + 0.106*sl 0.13 + 0.109*sl sn to qn1 t plh 0.43 0.32 + 0.054*sl 0.33 + 0.050*sl 0.34 + 0.050*sl t phl 0.45 0.37 + 0.037*sl 0.40 + 0.027*sl 0.44 + 0.024*sl t r 0.37 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.041*sl 0.13 + 0.042*sl ck to qn2 t plh 1.54 1.44 + 0.052*sl 1.44 + 0.050*sl 1.44 + 0.050*sl t phl 1.13 1.07 + 0.034*sl 1.09 + 0.026*sl 1.12 + 0.024*sl t r 0.38 0.17 + 0.104*sl 0.16 + 0.106*sl 0.14 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.042*sl 0.13 + 0.042*sl rn to qn2 t plh 0.74 0.63 + 0.052*sl 0.64 + 0.050*sl 0.64 + 0.050*sl t r 0.38 0.17 + 0.104*sl 0.16 + 0.107*sl 0.14 + 0.109*sl sn to qn2 t plh 0.43 0.32 + 0.054*sl 0.33 + 0.050*sl 0.34 + 0.050*sl t phl 0.45 0.38 + 0.037*sl 0.40 + 0.027*sl 0.44 + 0.024*sl t r 0.38 0.17 + 0.103*sl 0.16 + 0.107*sl 0.14 + 0.109*sl t f 0.22 0.14 + 0.044*sl 0.14 + 0.041*sl 0.14 + 0.042*sl ck to qn3 t plh 1.54 1.43 + 0.052*sl 1.44 + 0.050*sl 1.44 + 0.050*sl t phl 1.14 1.07 + 0.034*sl 1.09 + 0.026*sl 1.12 + 0.024*sl t r 0.36 0.16 + 0.104*sl 0.15 + 0.106*sl 0.13 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.12 + 0.042*sl 0.12 + 0.042*sl rn to qn3 t plh 0.73 0.62 + 0.052*sl 0.63 + 0.050*sl 0.63 + 0.050*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl sn to qn3 t plh 0.42 0.31 + 0.055*sl 0.32 + 0.050*sl 0.33 + 0.050*sl t phl 0.44 0.37 + 0.037*sl 0.39 + 0.027*sl 0.43 + 0.024*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.22 0.13 + 0.043*sl 0.14 + 0.041*sl 0.13 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-272 sec asic yfd4/yfd4d2 fast d flip-flop with reset, set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 yfd4 yfd4d2 yfd4 yfd4d2 d ck rn sn d ck rn sn 2.8 0.8 1.2 1.5 2.8 0.8 1.9 2.3 7.0 9.0 KGM80 yfd4 yfd4d2 yfd4 yfd4d2 d ck rn sn d ck rn sn 3.5 0.9 1.4 1.8 3.6 0.9 2.3 2.6 7.0 9.0 parameter symbol kg80 KGM80 yfd4 yfd4d2 yfd4 yfd4d2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 1.02 pulse width low (sn) t pwl 0.61 0.61 0.99 0.99 input setup time (d to ck) t su 0.28 0.31 0.61 0.58 input hold time (d to ck) t hd 0.26 0.26 0.46 0.46 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ck) t hd 0.20 0.20 0.41 0.41 recovery time (sn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ck) t hd 0.42 0.42 0.85 0.85 d ck q qn rn sn d ck cl clb q cl clb cl clb cl cl clb qn clb sn sn rn rn rn rn sn sn truth table dckrnsn q (n+1) qn (n+1) 01101 11110 xx1010 xx0101 xx0011 x 1 1 q (n) qn (n)
sec asic 3-273 kg80/KGM80 yfd4/yfd4d2 fast d flip-flop with reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 yfd4 kg80 yfd4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.53 0.44 + 0.045*sl 0.45 + 0.043*sl 0.45 + 0.042*sl t phl 0.44 0.36 + 0.038*sl 0.37 + 0.036*sl 0.38 + 0.035*sl t r 0.45 0.29 + 0.081*sl 0.28 + 0.087*sl 0.26 + 0.089*sl t f 0.31 0.18 + 0.065*sl 0.17 + 0.067*sl 0.16 + 0.068*sl rn to q t phl 0.50 0.42 + 0.042*sl 0.43 + 0.036*sl 0.44 + 0.035*sl t f 0.32 0.19 + 0.062*sl 0.18 + 0.067*sl 0.18 + 0.067*sl sn to q t plh 0.25 0.17 + 0.042*sl 0.17 + 0.041*sl 0.22 + 0.034*sl t phl 0.18 0.10 + 0.041*sl 0.11 + 0.034*sl 0.12 + 0.034*sl t r 0.40 0.25 + 0.076*sl 0.31 + 0.049*sl 0.37 + 0.041*sl t f 0.33 0.22 + 0.056*sl 0.20 + 0.062*sl 0.18 + 0.065*sl ck to qn t plh 0.67 0.48 + 0.097*sl 0.48 + 0.095*sl 0.49 + 0.094*sl t phl 0.72 0.54 + 0.092*sl 0.54 + 0.090*sl 0.55 + 0.089*sl t r 0.37 0.18 + 0.099*sl 0.17 + 0.100*sl 0.17 + 0.100*sl t f 0.33 0.16 + 0.086*sl 0.16 + 0.086*sl 0.16 + 0.086*sl rn to qn t plh 0.28 0.20 + 0.041*sl 0.20 + 0.041*sl 0.21 + 0.040*sl t phl 0.18 0.10 + 0.038*sl 0.11 + 0.034*sl 0.11 + 0.034*sl t r 0.42 0.29 + 0.064*sl 0.30 + 0.061*sl 0.29 + 0.062*sl t f 0.31 0.20 + 0.060*sl 0.18 + 0.064*sl 0.16 + 0.067*sl sn to qn t phl 0.44 0.26 + 0.089*sl 0.27 + 0.083*sl 0.36 + 0.071*sl t f 0.32 0.15 + 0.084*sl 0.17 + 0.076*sl 0.21 + 0.070*sl [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.49 0.44 + 0.024*sl 0.45 + 0.023*sl 0.46 + 0.022*sl t phl 0.43 0.39 + 0.023*sl 0.39 + 0.021*sl 0.41 + 0.019*sl t r 0.34 0.26 + 0.040*sl 0.25 + 0.042*sl 0.24 + 0.044*sl t f 0.28 0.21 + 0.033*sl 0.21 + 0.033*sl 0.21 + 0.033*sl rn to q t phl 0.50 0.45 + 0.027*sl 0.46 + 0.022*sl 0.48 + 0.019*sl t f 0.29 0.22 + 0.032*sl 0.22 + 0.032*sl 0.22 + 0.033*sl sn to q t plh 0.24 0.20 + 0.020*sl 0.20 + 0.020*sl 0.20 + 0.021*sl t phl 0.13 0.09 + 0.021*sl 0.09 + 0.019*sl 0.10 + 0.018*sl t r 0.39 0.32 + 0.036*sl 0.33 + 0.031*sl 0.39 + 0.022*sl t f 0.26 0.20 + 0.030*sl 0.19 + 0.031*sl 0.18 + 0.032*sl ck to qn t plh 0.59 0.49 + 0.054*sl 0.49 + 0.051*sl 0.50 + 0.049*sl t phl 0.62 0.52 + 0.048*sl 0.52 + 0.047*sl 0.53 + 0.045*sl t r 0.25 0.16 + 0.048*sl 0.15 + 0.050*sl 0.15 + 0.051*sl t f 0.21 0.13 + 0.041*sl 0.13 + 0.043*sl 0.13 + 0.042*sl rn to qn t plh 0.23 0.19 + 0.022*sl 0.19 + 0.020*sl 0.19 + 0.021*sl t phl 0.12 0.08 + 0.022*sl 0.09 + 0.018*sl 0.10 + 0.017*sl t r 0.33 0.26 + 0.038*sl 0.27 + 0.035*sl 0.29 + 0.032*sl t f 0.24 0.18 + 0.027*sl 0.18 + 0.030*sl 0.16 + 0.032*sl sn to qn t phl 0.37 0.28 + 0.045*sl 0.28 + 0.044*sl 0.30 + 0.041*sl t f 0.22 0.14 + 0.042*sl 0.14 + 0.042*sl 0.17 + 0.038*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-274 sec asic yfd4/yfd4d2 fast d flip-flop with reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 yfd4 KGM80 yfd4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.75 0.64 + 0.054*sl 0.65 + 0.051*sl 0.67 + 0.050*sl t phl 0.62 0.53 + 0.044*sl 0.55 + 0.039*sl 0.56 + 0.038*sl t r 0.60 0.40 + 0.101*sl 0.38 + 0.106*sl 0.36 + 0.108*sl t f 0.38 0.24 + 0.073*sl 0.24 + 0.073*sl 0.23 + 0.073*sl rn to q t phl 0.71 0.61 + 0.049*sl 0.63 + 0.041*sl 0.67 + 0.037*sl t f 0.40 0.26 + 0.070*sl 0.26 + 0.072*sl 0.24 + 0.073*sl sn to q t plh 0.31 0.21 + 0.051*sl 0.21 + 0.050*sl 0.37 + 0.036*sl t phl 0.22 0.13 + 0.044*sl 0.15 + 0.038*sl 0.15 + 0.037*sl t r 0.51 0.31 + 0.102*sl 0.41 + 0.062*sl 0.55 + 0.050*sl t f 0.37 0.24 + 0.067*sl 0.23 + 0.071*sl 0.20 + 0.073*sl ck to qn t plh 0.94 0.71 + 0.115*sl 0.72 + 0.111*sl 0.73 + 0.109*sl t phl 1.01 0.79 + 0.112*sl 0.80 + 0.108*sl 0.81 + 0.107*sl t r 0.51 0.27 + 0.118*sl 0.27 + 0.119*sl 0.26 + 0.119*sl t f 0.41 0.22 + 0.094*sl 0.22 + 0.094*sl 0.21 + 0.095*sl rn to qn t plh 0.36 0.26 + 0.050*sl 0.26 + 0.050*sl 0.28 + 0.048*sl t phl 0.23 0.15 + 0.041*sl 0.16 + 0.038*sl 0.17 + 0.037*sl t r 0.56 0.37 + 0.094*sl 0.42 + 0.077*sl 0.42 + 0.077*sl t f 0.36 0.23 + 0.068*sl 0.22 + 0.072*sl 0.20 + 0.074*sl sn to qn t phl 0.57 0.35 + 0.108*sl 0.38 + 0.098*sl 0.57 + 0.081*sl t f 0.39 0.20 + 0.093*sl 0.23 + 0.082*sl 0.28 + 0.078*sl [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.69 0.63 + 0.030*sl 0.64 + 0.027*sl 0.66 + 0.026*sl t phl 0.63 0.58 + 0.028*sl 0.59 + 0.023*sl 0.62 + 0.021*sl t r 0.45 0.35 + 0.049*sl 0.35 + 0.051*sl 0.33 + 0.053*sl t f 0.37 0.29 + 0.039*sl 0.29 + 0.037*sl 0.31 + 0.036*sl rn to q t phl 0.71 0.65 + 0.033*sl 0.67 + 0.025*sl 0.72 + 0.020*sl t f 0.39 0.31 + 0.037*sl 0.32 + 0.035*sl 0.32 + 0.035*sl sn to q t plh 0.31 0.26 + 0.025*sl 0.26 + 0.025*sl 0.25 + 0.026*sl t phl 0.18 0.13 + 0.023*sl 0.14 + 0.021*sl 0.15 + 0.019*sl t r 0.49 0.39 + 0.047*sl 0.41 + 0.041*sl 0.57 + 0.026*sl t f 0.29 0.22 + 0.034*sl 0.22 + 0.036*sl 0.21 + 0.036*sl ck to qn t plh 0.86 0.73 + 0.064*sl 0.74 + 0.059*sl 0.78 + 0.056*sl t phl 0.87 0.75 + 0.058*sl 0.76 + 0.055*sl 0.78 + 0.054*sl t r 0.34 0.22 + 0.059*sl 0.22 + 0.059*sl 0.22 + 0.059*sl t f 0.27 0.18 + 0.046*sl 0.18 + 0.046*sl 0.17 + 0.047*sl rn to qn t plh 0.29 0.24 + 0.026*sl 0.24 + 0.025*sl 0.24 + 0.025*sl t phl 0.17 0.12 + 0.022*sl 0.13 + 0.020*sl 0.14 + 0.018*sl t r 0.41 0.32 + 0.049*sl 0.32 + 0.047*sl 0.40 + 0.039*sl t f 0.26 0.20 + 0.033*sl 0.19 + 0.034*sl 0.18 + 0.036*sl sn to qn t phl 0.48 0.38 + 0.054*sl 0.38 + 0.053*sl 0.44 + 0.048*sl t f 0.28 0.18 + 0.047*sl 0.19 + 0.045*sl 0.26 + 0.039*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-275 kg80/KGM80 fd5/fd5d2 d flip-flop with negative edge trigger, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 fd5 fd5d2 fd5 fd5d2 d ckn d ckn 0.9 0.9 0.9 0.9 7.0 8.0 KGM80 fd5 fd5d2 fd5 fd5d2 d ckn d ckn 1.0 1.0 1.0 1.0 7.0 8.0 parameter symbol kg80 KGM80 fd5 fd5d2 fd5 fd5d2 pulse width low (ckn) t pwl 0.61 0.61 0.99 0.99 pulse width high (ckn) t pwh 0.61 0.61 0.99 0.99 input setup time (d to ckn) t su 0.31 0.31 0.58 0.58 input hold time (d to ckn) t hd 0.26 0.26 0.49 0.49 d ckn q qn d ckn clbn cln q cln clbn cln clbn cln clbn clbn cln qn truth table d ckn q (n+1) qn (n+1) 001 110 x q (n) qn (n)
kg80/KGM80 3-276 sec asic fd5/fd5d2 d flip-flop with negative edge trigger, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd5 kg80 fd5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.64 0.56 + 0.042*sl 0.55 + 0.042*sl 0.55 + 0.042*sl t phl 0.56 0.50 + 0.031*sl 0.51 + 0.026*sl 0.53 + 0.023*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.08 + 0.041*sl ckn to qn t plh 0.70 0.62 + 0.040*sl 0.61 + 0.041*sl 0.61 + 0.042*sl t phl 0.71 0.66 + 0.029*sl 0.67 + 0.025*sl 0.68 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl *g 1 sl 2 *g 2 2 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.62 0.58 + 0.023*sl 0.58 + 0.021*sl 0.58 + 0.021*sl t phl 0.56 0.52 + 0.021*sl 0.53 + 0.015*sl 0.54 + 0.013*sl t r 0.17 0.09 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.045*sl t f 0.14 0.09 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl ckn to qn t plh 0.73 0.69 + 0.019*sl 0.69 + 0.019*sl 0.68 + 0.020*sl t phl 0.75 0.72 + 0.018*sl 0.73 + 0.015*sl 0.74 + 0.013*sl t r 0.17 0.08 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-277 kg80/KGM80 fd5/fd5d2 d flip-flop with negative edge trigger, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd5 KGM80 fd5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.88 0.78 + 0.051*sl 0.78 + 0.050*sl 0.79 + 0.050*sl t phl 0.76 0.69 + 0.034*sl 0.71 + 0.026*sl 0.74 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.045*sl 0.12 + 0.041*sl 0.11 + 0.042*sl ckn to qn t plh 0.95 0.86 + 0.049*sl 0.85 + 0.050*sl 0.85 + 0.050*sl t phl 1.00 0.94 + 0.033*sl 0.96 + 0.026*sl 0.98 + 0.023*sl t r 0.34 0.13 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl *g 1 sl 3 *g 2 3 sl 11 *g 3 11 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.86 0.80 + 0.028*sl 0.81 + 0.025*sl 0.81 + 0.025*sl t phl 0.77 0.72 + 0.023*sl 0.74 + 0.016*sl 0.77 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.022*sl 0.14 + 0.020*sl ckn to qn t plh 1.00 0.95 + 0.024*sl 0.95 + 0.024*sl 0.95 + 0.025*sl t phl 1.06 1.02 + 0.021*sl 1.03 + 0.016*sl 1.06 + 0.013*sl t r 0.22 0.11 + 0.050*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-278 sec asic fd5s/fd5sd2 d flip-flop with negative edge trigger, scan, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 fd5s fd5sd2 fd5s fd5sd2 d ti te ckn d ti te ckn 0.6 0.8 1.7 0.9 0.6 0.8 1.7 0.9 9.0 10.0 KGM80 fd5s fd5sd2 fd5s fd5sd2 d ti te ckn d ti te ckn 1.0 1.0 2.1 1.0 1.0 1.0 2.1 1.0 9.0 10.0 parameter symbol kg80 KGM80 fd5s fd5sd2 fd5s fd5sd2 pulse width low (ckn) t pwl 0.61 0.61 0.99 0.99 pulse width high (ckn) t pwh 0.61 0.61 0.99 0.99 input setup time (d to ckn) t su 0.39 0.39 0.74 0.74 input hold time (d to ckn) t hd 0.17 0.17 0.36 0.36 input setup time (ti to ckn) t su 0.45 0.45 0.83 0.83 input hold time (ti to ckn) t hd 0.15 0.15 0.33 0.33 input setup time (te to ckn) t su 0.45 0.45 0.77 0.77 input hold time (te to ckn) t hd 0.15 0.15 0.33 0.33 q qn d ti te ckn d te ti clbn cln q cln clbn cln clbn clbn cln qn cln clbn ckn truth table d ti te ckn q (n+1) qn (n+1) 0x0 01 1x0 10 x01 01 x11 10 x x x q (n) qn (n)
sec asic 3-279 kg80/KGM80 fd5s/fd5sd2 d flip-flop with negative edge trigger, scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd5s kg80 fd5sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.63 0.55 + 0.042*sl 0.55 + 0.042*sl 0.55 + 0.042*sl t phl 0.56 0.50 + 0.031*sl 0.51 + 0.026*sl 0.53 + 0.023*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.08 + 0.041*sl ckn to qn t plh 0.69 0.61 + 0.040*sl 0.61 + 0.041*sl 0.61 + 0.042*sl t phl 0.71 0.65 + 0.030*sl 0.66 + 0.025*sl 0.68 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.041*sl 0.08 + 0.040*sl 0.07 + 0.042*sl *g 1 sl 2 *g 2 2 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.62 0.57 + 0.023*sl 0.58 + 0.021*sl 0.58 + 0.021*sl t phl 0.56 0.52 + 0.020*sl 0.53 + 0.015*sl 0.54 + 0.013*sl t r 0.17 0.09 + 0.040*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl ckn to qn t plh 0.73 0.69 + 0.019*sl 0.69 + 0.019*sl 0.68 + 0.020*sl t phl 0.75 0.71 + 0.019*sl 0.72 + 0.015*sl 0.73 + 0.013*sl t r 0.17 0.08 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-280 sec asic fd5s/fd5sd2 d flip-flop with negative edge trigger, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd5s KGM80 fd5sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.88 0.77 + 0.051*sl 0.78 + 0.050*sl 0.78 + 0.050*sl t phl 0.76 0.69 + 0.034*sl 0.71 + 0.026*sl 0.74 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl ckn to qn t plh 0.95 0.85 + 0.049*sl 0.85 + 0.050*sl 0.85 + 0.050*sl t phl 1.00 0.93 + 0.033*sl 0.95 + 0.026*sl 0.98 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl *g 1 sl 3 *g 2 3 sl 11 *g 3 11 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.85 0.79 + 0.028*sl 0.80 + 0.025*sl 0.80 + 0.025*sl t phl 0.76 0.72 + 0.023*sl 0.74 + 0.016*sl 0.77 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.022*sl 0.14 + 0.021*sl ckn to qn t plh 1.00 0.95 + 0.024*sl 0.95 + 0.024*sl 0.94 + 0.025*sl t phl 1.05 1.01 + 0.021*sl 1.03 + 0.016*sl 1.06 + 0.013*sl t r 0.22 0.11 + 0.050*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-281 kg80/KGM80 fd5x4 4-bit d flip-flop with negative edge trigger logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 pulse width low (ckn) t pwl 0.80 1.27 pulse width high (ckn) t pwh 0.61 0.99 input setup time (d0 to ckn) t su 0.17 0.39 input hold time (d0 to ckn) t hd 0.47 0.83 input setup time (d1 to ckn) t su 0.17 0.39 input hold time (d1 to ckn) t hd 0.47 0.83 input setup time (d2 to ckn) t su 0.17 0.39 input hold time (d2 to ckn) t hd 0.47 0.83 input setup time (d3 to ckn) t su 0.17 0.39 input hold time (d3 to ckn) t hd 0.47 0.83 d0 d1 d2 d3 ckn q0 q1 q2 q3 qn0 qn1 qn2 qn3 truth table cell data dn ckn qn (n+1) qnn (n+1) 001 110 x qn (n) qnn (n) input load (sl) gate count kg80 dn ckn 24.0 0.9 0.9 KGM80 dn ckn 24.0 1.0 1.1
kg80/KGM80 3-282 sec asic fd5x4 4-bit d flip-flop with negative edge trigger switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd5x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q0 t plh 0.98 0.89 + 0.042*sl 0.89 + 0.041*sl 0.89 + 0.042*sl t phl 0.76 0.69 + 0.031*sl 0.71 + 0.026*sl 0.72 + 0.023*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.041*sl ckn to q1 t plh 0.98 0.90 + 0.042*sl 0.90 + 0.041*sl 0.90 + 0.042*sl t phl 0.76 0.70 + 0.031*sl 0.71 + 0.026*sl 0.73 + 0.023*sl t r 0.28 0.10 + 0.085*sl 0.10 + 0.089*sl 0.09 + 0.091*sl t f 0.18 0.09 + 0.041*sl 0.10 + 0.040*sl 0.09 + 0.041*sl ckn to q2 t plh 0.98 0.90 + 0.042*sl 0.90 + 0.041*sl 0.90 + 0.042*sl t phl 0.76 0.70 + 0.031*sl 0.71 + 0.026*sl 0.73 + 0.023*sl t r 0.28 0.10 + 0.086*sl 0.10 + 0.089*sl 0.09 + 0.091*sl t f 0.18 0.09 + 0.041*sl 0.10 + 0.040*sl 0.09 + 0.041*sl ckn to q3 t plh 0.98 0.89 + 0.042*sl 0.89 + 0.041*sl 0.89 + 0.042*sl t phl 0.76 0.69 + 0.031*sl 0.71 + 0.026*sl 0.72 + 0.023*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.041*sl ckn to qn0 t plh 0.87 0.79 + 0.040*sl 0.79 + 0.041*sl 0.79 + 0.041*sl t phl 1.05 1.00 + 0.029*sl 1.01 + 0.025*sl 1.02 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl ckn to qn1 t plh 0.88 0.80 + 0.040*sl 0.80 + 0.041*sl 0.79 + 0.042*sl t phl 1.06 1.00 + 0.030*sl 1.01 + 0.025*sl 1.02 + 0.023*sl t r 0.27 0.09 + 0.087*sl 0.09 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl ckn to qn2 t plh 0.88 0.80 + 0.040*sl 0.80 + 0.041*sl 0.79 + 0.042*sl t phl 1.06 1.00 + 0.030*sl 1.01 + 0.025*sl 1.02 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.089*sl 0.08 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl ckn to qn3 t plh 0.87 0.79 + 0.040*sl 0.79 + 0.041*sl 0.79 + 0.041*sl t phl 1.05 1.00 + 0.029*sl 1.01 + 0.025*sl 1.02 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-283 kg80/KGM80 fd5x4 4-bit d flip-flop with negative edge trigger switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd5x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q0 t plh 1.37 1.27 + 0.051*sl 1.27 + 0.050*sl 1.28 + 0.050*sl t phl 1.04 0.97 + 0.034*sl 0.99 + 0.026*sl 1.02 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl ckn to q1 t plh 1.38 1.28 + 0.051*sl 1.28 + 0.050*sl 1.28 + 0.050*sl t phl 1.05 0.98 + 0.034*sl 1.00 + 0.026*sl 1.03 + 0.023*sl t r 0.36 0.15 + 0.105*sl 0.14 + 0.108*sl 0.13 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.12 + 0.042*sl ckn to q2 t plh 1.38 1.28 + 0.051*sl 1.28 + 0.050*sl 1.28 + 0.050*sl t phl 1.05 0.98 + 0.034*sl 1.00 + 0.026*sl 1.03 + 0.023*sl t r 0.36 0.15 + 0.105*sl 0.14 + 0.108*sl 0.13 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.12 + 0.042*sl ckn to q3 t plh 1.37 1.27 + 0.051*sl 1.27 + 0.050*sl 1.28 + 0.050*sl t phl 1.04 0.97 + 0.034*sl 0.99 + 0.026*sl 1.03 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl ckn to qn0 t plh 1.22 1.12 + 0.049*sl 1.12 + 0.050*sl 1.12 + 0.050*sl t phl 1.49 1.43 + 0.033*sl 1.45 + 0.026*sl 1.47 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl ckn to qn1 t plh 1.23 1.13 + 0.049*sl 1.13 + 0.050*sl 1.13 + 0.050*sl t phl 1.50 1.44 + 0.033*sl 1.46 + 0.026*sl 1.48 + 0.023*sl t r 0.34 0.14 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.044*sl 0.11 + 0.042*sl 0.11 + 0.042*sl ckn to qn2 t plh 1.23 1.13 + 0.049*sl 1.13 + 0.050*sl 1.13 + 0.050*sl t phl 1.50 1.44 + 0.033*sl 1.46 + 0.026*sl 1.48 + 0.023*sl t r 0.34 0.14 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.044*sl 0.11 + 0.041*sl 0.10 + 0.042*sl ckn to qn3 t plh 1.22 1.12 + 0.049*sl 1.12 + 0.050*sl 1.12 + 0.050*sl t phl 1.49 1.43 + 0.033*sl 1.45 + 0.026*sl 1.47 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-284 sec asic fd6/fd6d2 d flip-flop with negative edge trigger, reset, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 fd6 fd6d2 fd6 fd6d2 d ckn rn d ckn rn 0.9 0.9 1.6 0.9 0.9 1.6 8.0 9.0 KGM80 fd6 fd6d2 fd6 fd6d2 d ckn rn d ckn rn 1.0 1.0 1.9 1.0 1.0 1.9 8.0 9.0 parameter symbol kg80 KGM80 fd6 fd6d2 fd6 fd6d2 pulse width low (ckn) t pwl 0.61 0.61 0.99 0.99 pulse width high (ckn) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 0.99 input setup time (d to ckn) t su 0.31 0.31 0.58 0.58 input hold time (d to ckn) t hd 0.26 0.26 0.49 0.49 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ckn) t hd 0.53 0.53 0.85 0.85 d ckn q qn rn d ckn clbn cln q cln clbn clbn cln clbn clbn cln qn cln rn rn rn rn truth table d ckn rn q (n+1) qn (n+1) 0 101 1 110 xx001 x 1 q (n) qn (n)
sec asic 3-285 kg80/KGM80 fd6/fd6d2 d flip-flop with negative edge trigger, reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd6 kg80 fd6d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.70 0.61 + 0.044*sl 0.61 + 0.042*sl 0.62 + 0.042*sl t phl 0.57 0.51 + 0.031*sl 0.52 + 0.026*sl 0.54 + 0.023*sl t r 0.28 0.11 + 0.087*sl 0.11 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.041*sl rn to q t phl 0.33 0.27 + 0.033*sl 0.28 + 0.026*sl 0.30 + 0.024*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.039*sl 0.10 + 0.040*sl ckn to qn t plh 0.70 0.62 + 0.040*sl 0.62 + 0.041*sl 0.62 + 0.042*sl t phl 0.77 0.71 + 0.029*sl 0.72 + 0.025*sl 0.73 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl rn to qn t plh 0.47 0.38 + 0.040*sl 0.38 + 0.041*sl 0.38 + 0.042*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.089*sl 0.07 + 0.091*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.70 0.65 + 0.023*sl 0.66 + 0.022*sl 0.66 + 0.021*sl t phl 0.58 0.54 + 0.019*sl 0.55 + 0.015*sl 0.56 + 0.013*sl t r 0.21 0.13 + 0.043*sl 0.12 + 0.043*sl 0.12 + 0.044*sl t f 0.15 0.11 + 0.021*sl 0.11 + 0.020*sl 0.11 + 0.020*sl rn to q t phl 0.34 0.29 + 0.020*sl 0.31 + 0.016*sl 0.32 + 0.013*sl t f 0.17 0.12 + 0.021*sl 0.13 + 0.020*sl 0.13 + 0.019*sl ckn to qn t plh 0.73 0.69 + 0.020*sl 0.69 + 0.019*sl 0.69 + 0.020*sl t phl 0.82 0.78 + 0.018*sl 0.79 + 0.015*sl 0.81 + 0.013*sl t r 0.16 0.08 + 0.042*sl 0.08 + 0.043*sl 0.06 + 0.045*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.019*sl 0.10 + 0.020*sl rn to qn t plh 0.49 0.45 + 0.019*sl 0.45 + 0.019*sl 0.45 + 0.020*sl t r 0.17 0.09 + 0.038*sl 0.08 + 0.043*sl 0.07 + 0.044*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-286 sec asic fd6/fd6d2 d flip-flop with negative edge trigger, reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd6 KGM80 fd6d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.97 0.86 + 0.054*sl 0.87 + 0.051*sl 0.88 + 0.050*sl t phl 0.78 0.71 + 0.035*sl 0.73 + 0.027*sl 0.76 + 0.023*sl t r 0.37 0.16 + 0.105*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.20 0.12 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl rn to q t phl 0.43 0.36 + 0.036*sl 0.38 + 0.027*sl 0.42 + 0.024*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.041*sl 0.13 + 0.042*sl ckn to qn t plh 0.97 0.87 + 0.049*sl 0.87 + 0.050*sl 0.87 + 0.050*sl t phl 1.08 1.02 + 0.032*sl 1.04 + 0.025*sl 1.06 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.041*sl 0.10 + 0.042*sl rn to qn t plh 0.62 0.52 + 0.049*sl 0.52 + 0.050*sl 0.52 + 0.050*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.97 0.91 + 0.030*sl 0.92 + 0.026*sl 0.93 + 0.025*sl t phl 0.80 0.75 + 0.022*sl 0.77 + 0.016*sl 0.80 + 0.013*sl t r 0.28 0.17 + 0.053*sl 0.18 + 0.052*sl 0.17 + 0.053*sl t f 0.18 0.14 + 0.023*sl 0.14 + 0.021*sl 0.15 + 0.021*sl rn to q t phl 0.44 0.40 + 0.023*sl 0.42 + 0.017*sl 0.45 + 0.013*sl t f 0.20 0.15 + 0.024*sl 0.16 + 0.021*sl 0.17 + 0.020*sl ckn to qn t plh 1.01 0.96 + 0.025*sl 0.96 + 0.024*sl 0.96 + 0.025*sl t phl 1.16 1.12 + 0.021*sl 1.13 + 0.016*sl 1.16 + 0.013*sl t r 0.21 0.11 + 0.050*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.17 0.12 + 0.024*sl 0.13 + 0.021*sl 0.13 + 0.020*sl rn to qn t plh 0.66 0.61 + 0.025*sl 0.61 + 0.024*sl 0.61 + 0.025*sl t r 0.21 0.11 + 0.051*sl 0.11 + 0.052*sl 0.09 + 0.054*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-287 kg80/KGM80 fd6s/fd6sd2 d flip-flop with negative edge trigger, reset, scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 fd6s fd6sd2 fd6s fd6sd2 d ti te ckn rn d ti te ckn rn 0.6 0.9 1.7 0.9 1.5 0.6 0.9 1.7 0.9 1.5 10.0 11.0 KGM80 fd6s fd6sd2 fd6s fd6sd2 d ti te ckn rn d ti te ckn rn 1.1 1.0 2.1 1.0 1.9 1.1 1.0 2.1 1.0 1.9 10.0 11.0 q qn d ti te ckn rn ckn clbn cln q cln clbn clbn cln clbn clbn cln qn cln rn rn rn rn d te ti truth table d ti te ckn rn q (n+1) qn (n+1) 0x0 101 1x0 110 x01 101 x11 110 xxxx001 x x x 1 q (n) qn (n)
kg80/KGM80 3-288 sec asic fd6s/fd6sd2 d flip-flop with negative edge trigger, reset, scan, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd6s kg80 fd6sd2 parameter symbol kg80 KGM80 fd6s fd6sd2 fd6s fd6sd2 pulse width low (ckn) t pwl 0.61 0.61 0.99 0.99 pulse width high (ckn) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 0.99 input setup time (d to ckn) t su 0.39 0.37 0.74 0.74 input hold time (d to ckn) t hd 0.17 0.17 0.36 0.36 input setup time (ti to ckn) t su 0.45 0.45 0.86 0.86 input hold time (ti to ckn) t hd 0.15 0.15 0.33 0.33 input setup time (te to ckn) t su 0.45 0.45 0.77 0.80 input hold time (te to ckn) t hd 0.15 0.15 0.33 0.33 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ckn) t hd 0.0.53 0.53 0.85 0.85 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.72 0.63 + 0.044*sl 0.64 + 0.042*sl 0.64 + 0.042*sl t phl 0.59 0.52 + 0.031*sl 0.54 + 0.026*sl 0.55 + 0.024*sl t r 0.28 0.11 + 0.085*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.17 0.09 + 0.042*sl 0.10 + 0.040*sl 0.08 + 0.041*sl rn to q t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.31 + 0.024*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.039*sl 0.10 + 0.040*sl ckn to qn t plh 0.72 0.64 + 0.040*sl 0.64 + 0.041*sl 0.64 + 0.042*sl t phl 0.79 0.74 + 0.029*sl 0.75 + 0.025*sl 0.76 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl rn to qn t plh 0.47 0.40 + 0.040*sl 0.39 + 0.041*sl 0.39 + 0.042*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.089*sl 0.07 + 0.091*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.71 0.66 + 0.025*sl 0.67 + 0.022*sl 0.67 + 0.021*sl t phl 0.58 0.54 + 0.021*sl 0.55 + 0.016*sl 0.57 + 0.014*sl t r 0.19 0.11 + 0.043*sl 0.11 + 0.043*sl 0.10 + 0.044*sl t f 0.14 0.10 + 0.023*sl 0.10 + 0.020*sl 0.11 + 0.020*sl rn to q t phl 0.33 0.29 + 0.022*sl 0.30 + 0.016*sl 0.32 + 0.014*sl t f 0.16 0.11 + 0.023*sl 0.12 + 0.020*sl 0.13 + 0.019*sl ckn to qn t plh 0.76 0.72 + 0.018*sl 0.72 + 0.019*sl 0.71 + 0.020*sl t phl 0.85 0.82 + 0.016*sl 0.83 + 0.014*sl 0.84 + 0.013*sl t r 0.19 0.11 + 0.039*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.15 0.11 + 0.019*sl 0.11 + 0.019*sl 0.11 + 0.020*sl rn to qn t plh 0.51 0.47 + 0.019*sl 0.47 + 0.019*sl 0.47 + 0.020*sl t r 0.19 0.10 + 0.044*sl 0.10 + 0.043*sl 0.09 + 0.044*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-289 kg80/KGM80 fd6s/fd6sd2 d flip-flop with negative edge trigger, reset, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd6s KGM80 fd6sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 1.00 0.89 + 0.055*sl 0.90 + 0.051*sl 0.91 + 0.050*sl t phl 0.80 0.73 + 0.036*sl 0.75 + 0.027*sl 0.79 + 0.024*sl t r 0.37 0.16 + 0.105*sl 0.15 + 0.107*sl 0.13 + 0.108*sl t f 0.21 0.12 + 0.045*sl 0.13 + 0.041*sl 0.12 + 0.042*sl rn to q t phl 0.44 0.37 + 0.037*sl 0.39 + 0.027*sl 0.43 + 0.024*sl t f 0.22 0.13 + 0.045*sl 0.14 + 0.041*sl 0.13 + 0.042*sl ckn to qn t plh 0.99 0.90 + 0.049*sl 0.89 + 0.050*sl 0.89 + 0.050*sl t phl 1.12 1.05 + 0.032*sl 1.07 + 0.025*sl 1.09 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.042*sl 0.11 + 0.041*sl 0.10 + 0.042*sl rn to qn t plh 0.64 0.54 + 0.048*sl 0.53 + 0.050*sl 0.53 + 0.050*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.98 0.92 + 0.031*sl 0.93 + 0.027*sl 0.95 + 0.025*sl t phl 0.80 0.75 + 0.024*sl 0.77 + 0.017*sl 0.81 + 0.014*sl t r 0.25 0.14 + 0.054*sl 0.14 + 0.052*sl 0.14 + 0.053*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.022*sl 0.14 + 0.021*sl rn to q t phl 0.44 0.39 + 0.025*sl 0.41 + 0.017*sl 0.45 + 0.014*sl t f 0.18 0.13 + 0.026*sl 0.14 + 0.022*sl 0.16 + 0.020*sl ckn to qn t plh 1.05 1.01 + 0.023*sl 1.01 + 0.024*sl 1.00 + 0.025*sl t phl 1.21 1.17 + 0.019*sl 1.18 + 0.015*sl 1.21 + 0.013*sl t r 0.25 0.14 + 0.051*sl 0.14 + 0.053*sl 0.12 + 0.054*sl t f 0.18 0.13 + 0.024*sl 0.14 + 0.021*sl 0.15 + 0.020*sl rn to qn t plh 0.69 0.65 + 0.023*sl 0.65 + 0.024*sl 0.64 + 0.025*sl t r 0.25 0.15 + 0.051*sl 0.14 + 0.053*sl 0.12 + 0.054*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-290 sec asic fd7/fd7d2 d flip-flop with negative edge trigger, set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 fd7 fd7d2 fd7 fd7d2 d ckn sn d ckn sn 0.9 0.9 1.6 0.9 0.9 1.6 8.0 9.0 KGM80 fd7 fd7d2 fd7 fd7d2 d ckn sn d ckn sn 1.0 1.0 2.0 1.0 1.0 2.0 8.0 9.0 parameter symbol kg80 KGM80 fd7 fd7d2 fd7 fd7d2 pulse width low (ckn) t pwl 0.61 0.61 0.99 0.99 pulse width high (ckn) t pwh 0.61 0.61 0.99 0.99 pulse width low (sn) t pwl 0.61 0.61 0.99 1.02 input setup time (d to ckn) t su 0.37 0.37 0.68 0.68 input hold time (d to ckn) t hd 0.26 0.26 0.46 0.46 recovery time (sn) t rc 0.15 0.15 0.33 0.33 input hold time (sn to ckn) t hd 0.26 0.26 0.41 0.41 d ckn q qn sn d ckn clbn cln q cln clbn clbn cln clbn clbn cln qn cln sn sn sn sn truth table d ckn sn q (n+1) qn (n+1) 0 101 1 110 xx010 x 1 q (n) qn (n)
sec asic 3-291 kg80/KGM80 fd7/fd7d2 d flip-flop with negative edge trigger, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd7 kg80 fd7d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.63 0.55 + 0.042*sl 0.55 + 0.042*sl 0.55 + 0.042*sl t phl 0.59 0.53 + 0.031*sl 0.54 + 0.026*sl 0.55 + 0.024*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.041*sl sn to q t plh 0.59 0.50 + 0.041*sl 0.50 + 0.041*sl 0.50 + 0.042*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.091*sl ckn to qn t plh 0.79 0.71 + 0.042*sl 0.71 + 0.041*sl 0.71 + 0.042*sl t phl 0.73 0.67 + 0.030*sl 0.68 + 0.026*sl 0.69 + 0.023*sl t r 0.28 0.11 + 0.086*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.08 + 0.042*sl sn to qn t phl 0.34 0.27 + 0.032*sl 0.29 + 0.026*sl 0.30 + 0.023*sl t f 0.18 0.11 + 0.038*sl 0.11 + 0.039*sl 0.09 + 0.041*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.62 0.57 + 0.022*sl 0.58 + 0.021*sl 0.58 + 0.021*sl t phl 0.59 0.55 + 0.021*sl 0.56 + 0.015*sl 0.58 + 0.013*sl t r 0.17 0.09 + 0.042*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl sn to q t plh 0.57 0.53 + 0.023*sl 0.53 + 0.021*sl 0.53 + 0.020*sl t r 0.17 0.09 + 0.041*sl 0.09 + 0.043*sl 0.07 + 0.044*sl ckn to qn t plh 0.84 0.79 + 0.022*sl 0.80 + 0.020*sl 0.80 + 0.020*sl t phl 0.76 0.72 + 0.019*sl 0.73 + 0.015*sl 0.75 + 0.013*sl t r 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.044*sl t f 0.14 0.09 + 0.023*sl 0.10 + 0.020*sl 0.10 + 0.020*sl sn to qn t phl 0.33 0.29 + 0.022*sl 0.30 + 0.016*sl 0.32 + 0.013*sl t f 0.16 0.11 + 0.023*sl 0.12 + 0.019*sl 0.12 + 0.019*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-292 sec asic fd7/fd7d2 d flip-flop with negative edge trigger, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd7 fdm80 fd7d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.88 0.78 + 0.051*sl 0.78 + 0.050*sl 0.78 + 0.050*sl t phl 0.80 0.73 + 0.034*sl 0.75 + 0.026*sl 0.78 + 0.024*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.044*sl 0.12 + 0.042*sl 0.11 + 0.042*sl sn to q t plh 0.82 0.71 + 0.051*sl 0.72 + 0.050*sl 0.72 + 0.050*sl t r 0.35 0.14 + 0.103*sl 0.13 + 0.108*sl 0.12 + 0.109*sl ckn to qn t plh 1.10 0.99 + 0.052*sl 1.00 + 0.050*sl 1.00 + 0.050*sl t phl 1.03 0.96 + 0.034*sl 0.98 + 0.026*sl 1.01 + 0.024*sl t r 0.36 0.16 + 0.104*sl 0.15 + 0.106*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.044*sl 0.12 + 0.042*sl 0.12 + 0.042*sl sn to qn t phl 0.44 0.37 + 0.037*sl 0.40 + 0.027*sl 0.43 + 0.024*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.041*sl 0.13 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.86 0.80 + 0.028*sl 0.81 + 0.025*sl 0.81 + 0.025*sl t phl 0.81 0.76 + 0.024*sl 0.78 + 0.016*sl 0.82 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.021*sl 0.13 + 0.021*sl sn to q t plh 0.80 0.74 + 0.029*sl 0.75 + 0.025*sl 0.75 + 0.025*sl t r 0.22 0.12 + 0.051*sl 0.12 + 0.052*sl 0.10 + 0.054*sl ckn to qn t plh 1.16 1.11 + 0.029*sl 1.12 + 0.025*sl 1.12 + 0.025*sl t phl 1.08 1.04 + 0.023*sl 1.05 + 0.016*sl 1.09 + 0.013*sl t r 0.25 0.14 + 0.053*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.17 0.12 + 0.024*sl 0.13 + 0.022*sl 0.14 + 0.021*sl sn to qn t phl 0.44 0.39 + 0.025*sl 0.42 + 0.017*sl 0.46 + 0.014*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.021*sl 0.16 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-293 kg80/KGM80 fd7s/fd7sd2 d flip-flop with negative edge trigger, set, scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 fd7s fd7sd2 fd7s fd7sd2 d ti te ckn sn d ti te ckn sn 0.5 0.8 1.7 0.9 1./6 0.5 0.8 1.7 0.9 1.6 10.0 11.0 KGM80 fd7s fd7sd2 fd7s fd7sd2 d ti te ckn sn d ti te ckn sn 1.0 1.0 2.1 1.0 1.9 1.0 1.0 2.1 1.0 1.9 10.0 11.0 q qn d ti te ckn sn clbn cln q clbn cln clbn clbn cln qn cln sn sn ckn cln clbn sn sn d te ti truth table d ti te ckn sn q (n+1) qn (n+1) 0x0 101 1x0 110 x01 101 x11 110 xxxx010 x x x 1 q (n) qn (n)
kg80/KGM80 3-294 sec asic fd7s/fd7sd2 d flip-flop with negative edge trigger, set, scan, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd7s kg80 fd7sd2 parameter symbol kg80 KGM80 fd7s fd7sd2 fd7s fd7sd2 pulse width low (ckn) t pwl 0.61 0.61 0.99 0.99 pulse width high (ckn) t pwh 0.61 0.61 0.99 0.99 pulse width low (sn) t pwl 0.61 0.61 0.99 1.02 input setup time (d to ckn) t su 0.45 0.45 0.83 0.83 input hold time (d to ckn) t hd 0.17 0.17 0.33 0.33 input setup time (ti to ckn) t su 0.50 0.50 0.93 0.93 input hold time (ti to ckn) t hd 0.15 0.15 0.33 0.33 input setup time (te to ckn) t su 0.45 0.45 0.83 0.83 input hold time (te to ckn) t hd 0.15 0.15 0.33 0.33 recovery time (sn) t rc 0.15 0.15 0.33 0.33 input hold time (sn to ckn) t hd 0.26 0.26 0.41 0.41 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.64 0.55 + 0.042*sl 0.55 + 0.042*sl 0.55 + 0.042*sl t phl 0.59 0.53 + 0.030*sl 0.54 + 0.026*sl 0.55 + 0.024*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.041*sl 0.08 + 0.041*sl sn to q t plh 0.59 0.51 + 0.041*sl 0.51 + 0.041*sl 0.50 + 0.042*sl t r 0.27 0.10 + 0.083*sl 0.09 + 0.089*sl 0.08 + 0.091*sl ckn to qn t plh 0.79 0.71 + 0.042*sl 0.71 + 0.041*sl 0.71 + 0.042*sl t phl 0.73 0.67 + 0.030*sl 0.68 + 0.026*sl 0.69 + 0.023*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.08 + 0.042*sl sn to qn t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.30 + 0.024*sl t f 0.18 0.11 + 0.040*sl 0.11 + 0.039*sl 0.10 + 0.040*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.62 0.57 + 0.023*sl 0.58 + 0.021*sl 0.58 + 0.021*sl t phl 0.59 0.55 + 0.021*sl 0.56 + 0.015*sl 0.58 + 0.013*sl t r 0.17 0.09 + 0.038*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl sn to q t plh 0.58 0.53 + 0.023*sl 0.54 + 0.021*sl 0.54 + 0.020*sl t r 0.17 0.09 + 0.042*sl 0.09 + 0.042*sl 0.07 + 0.044*sl ckn to qn t plh 0.84 0.79 + 0.023*sl 0.80 + 0.020*sl 0.80 + 0.020*sl t phl 0.76 0.73 + 0.019*sl 0.73 + 0.015*sl 0.75 + 0.013*sl t r 0.19 0.10 + 0.042*sl 0.10 + 0.043*sl 0.10 + 0.044*sl t f 0.14 0.10 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.020*sl sn to qn t phl 0.33 0.29 + 0.022*sl 0.30 + 0.016*sl 0.32 + 0.013*sl t f 0.16 0.11 + 0.023*sl 0.12 + 0.019*sl 0.12 + 0.019*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-295 kg80/KGM80 fd7s/fd7sd2 d flip-flop with negative edge trigger, set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd7s KGM80 fd7sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.88 0.78 + 0.051*sl 0.78 + 0.050*sl 0.78 + 0.050*sl t phl 0.80 0.73 + 0.035*sl 0.76 + 0.026*sl 0.78 + 0.024*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.044*sl 0.12 + 0.042*sl 0.11 + 0.042*sl sn to q t plh 0.82 0.72 + 0.051*sl 0.72 + 0.050*sl 0.72 + 0.050*sl t r 0.35 0.14 + 0.103*sl 0.13 + 0.108*sl 0.12 + 0.109*sl ckn to qn t plh 1.10 0.99 + 0.053*sl 1.00 + 0.050*sl 1.00 + 0.050*sl t phl 1.03 0.96 + 0.034*sl 0.98 + 0.026*sl 1.01 + 0.024*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.042*sl 0.12 + 0.042*sl 0.12 + 0.042*sl sn to qn t phl 0.44 0.37 + 0.037*sl 0.40 + 0.027*sl 0.43 + 0.024*sl t f 0.22 0.13 + 0.043*sl 0.14 + 0.041*sl 0.13 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.86 0.80 + 0.028*sl 0.81 + 0.025*sl 0.81 + 0.025*sl t phl 0.81 0.76 + 0.024*sl 0.78 + 0.016*sl 0.82 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.021*sl 0.13 + 0.021*sl sn to q t plh 0.80 0.75 + 0.028*sl 0.76 + 0.025*sl 0.76 + 0.025*sl t r 0.22 0.12 + 0.050*sl 0.12 + 0.052*sl 0.10 + 0.054*sl ckn to qn t plh 1.16 1.11 + 0.029*sl 1.12 + 0.025*sl 1.12 + 0.025*sl t phl 1.08 1.04 + 0.023*sl 1.05 + 0.016*sl 1.09 + 0.013*sl t r 0.25 0.14 + 0.054*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.17 0.12 + 0.026*sl 0.13 + 0.021*sl 0.14 + 0.021*sl sn to qn t phl 0.44 0.39 + 0.025*sl 0.41 + 0.017*sl 0.46 + 0.014*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.021*sl 0.16 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-296 sec asic fd8/fd8d2 d flip-flop with negative edge trigger, reset, set, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 fd8 fd8d2 fd8 fd8d2 d ckn rn sn d ckn rn sn 0.9 0.9 1.8 1.6 0.9 0.9 1.8 1.6 9.0 10.0 KGM80 fd8 fd8d2 fd8 fd8d2 d ckn rn sn d ckn rn sn 1.0 1.0 2.2 2.1 1.0 1.0 2.2 2.1 9.0 10.0 d ckn q qn rn sn d ckn clbn cln q cln clbn clbn cln clbn clbn cln qn cln sn sn rn rn rn rn sn sn truth table d ckn rn sn q (n+1) qn (n+1) 01101 11110 xx1010 xx0101 xx0000 x 1 1 q (n) qn (n)
sec asic 3-297 kg80/KGM80 fd8/fd8d2 d flip-flop with negative edge trigger, reset, set, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 fd8 fd8d2 fd8 fd8d2 pulse width low (ckn) t pwl 0.61 0.61 0.99 0.99 pulse width high (ckn) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 0.99 pulse width low (sn) t pwl 0.64 0.64 1.05 1.08 input setup time (d to ckn) t su 0.37 0.37 0.68 0.68 input hold time (d to ckn) t hd 0.26 0.26 0.49 0.49 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ckn) t hd 0.53 0.53 0.85 0.85 recovery time (sn) t rc 0.15 0.15 0.33 0.33 input hold time (sn to ckn) t hd 0.26 0.26 0.49 0.49
kg80/KGM80 3-298 sec asic fd8/fd8d2 d flip-flop with negative edge trigger, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd8 kg80 fd8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.71 0.62 + 0.045*sl 0.62 + 0.042*sl 0.63 + 0.042*sl t phl 0.61 0.54 + 0.031*sl 0.56 + 0.026*sl 0.57 + 0.024*sl t r 0.29 0.11 + 0.086*sl 0.11 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.09 + 0.041*sl rn to q t plh 0.29 0.20 + 0.044*sl 0.21 + 0.041*sl 0.21 + 0.041*sl t phl 0.33 0.27 + 0.032*sl 0.28 + 0.026*sl 0.30 + 0.024*sl t r 0.28 0.11 + 0.085*sl 0.11 + 0.088*sl 0.09 + 0.090*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.040*sl 0.10 + 0.041*sl sn to q t plh 0.66 0.57 + 0.043*sl 0.58 + 0.041*sl 0.58 + 0.041*sl t r 0.28 0.11 + 0.084*sl 0.11 + 0.088*sl 0.09 + 0.090*sl ckn to qn t plh 0.80 0.71 + 0.042*sl 0.71 + 0.041*sl 0.71 + 0.041*sl t phl 0.79 0.73 + 0.030*sl 0.74 + 0.025*sl 0.75 + 0.023*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.041*sl rn to qn t plh 0.52 0.44 + 0.042*sl 0.44 + 0.041*sl 0.44 + 0.041*sl t r 0.28 0.11 + 0.086*sl 0.10 + 0.088*sl 0.09 + 0.090*sl sn to qn t plh 0.29 0.20 + 0.044*sl 0.21 + 0.041*sl 0.21 + 0.041*sl t phl 0.33 0.26 + 0.032*sl 0.28 + 0.025*sl 0.29 + 0.024*sl t r 0.28 0.11 + 0.086*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.039*sl 0.09 + 0.041*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.70 0.65 + 0.025*sl 0.66 + 0.022*sl 0.66 + 0.021*sl t phl 0.61 0.56 + 0.021*sl 0.58 + 0.016*sl 0.59 + 0.013*sl t r 0.19 0.11 + 0.042*sl 0.10 + 0.043*sl 0.10 + 0.044*sl t f 0.14 0.10 + 0.023*sl 0.11 + 0.020*sl 0.11 + 0.020*sl rn to q t plh 0.27 0.23 + 0.023*sl 0.23 + 0.022*sl 0.24 + 0.021*sl t phl 0.32 0.28 + 0.021*sl 0.29 + 0.016*sl 0.31 + 0.013*sl t r 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.043*sl t f 0.15 0.11 + 0.022*sl 0.12 + 0.020*sl 0.12 + 0.020*sl sn to q t plh 0.66 0.61 + 0.025*sl 0.61 + 0.022*sl 0.62 + 0.021*sl t r 0.19 0.11 + 0.042*sl 0.10 + 0.043*sl 0.10 + 0.043*sl ckn to qn t plh 0.84 0.80 + 0.021*sl 0.80 + 0.020*sl 0.80 + 0.020*sl t phl 0.84 0.80 + 0.018*sl 0.81 + 0.015*sl 0.82 + 0.013*sl t r 0.19 0.10 + 0.043*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.019*sl 0.10 + 0.020*sl rn to qn t plh 0.56 0.52 + 0.022*sl 0.52 + 0.020*sl 0.52 + 0.020*sl t r 0.19 0.10 + 0.041*sl 0.10 + 0.043*sl 0.09 + 0.044*sl sn to qn t plh 0.28 0.23 + 0.025*sl 0.24 + 0.022*sl 0.25 + 0.021*sl t phl 0.32 0.28 + 0.021*sl 0.29 + 0.016*sl 0.31 + 0.013*sl t r 0.19 0.10 + 0.041*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.15 0.11 + 0.021*sl 0.11 + 0.019*sl 0.11 + 0.019*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 7, *grou p 3 : 7 < sl < < = =
sec asic 3-299 kg80/KGM80 fd8/fd8d2 d flip-flop with negative edge trigger, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd8 KGM80 fd8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.98 0.87 + 0.054*sl 0.88 + 0.051*sl 0.89 + 0.050*sl t phl 0.83 0.76 + 0.035*sl 0.78 + 0.027*sl 0.81 + 0.024*sl t r 0.37 0.16 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.108*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.042*sl 0.12 + 0.042*sl rn to q t plh 0.39 0.28 + 0.054*sl 0.29 + 0.050*sl 0.30 + 0.050*sl t phl 0.43 0.36 + 0.036*sl 0.38 + 0.027*sl 0.41 + 0.024*sl t r 0.36 0.16 + 0.104*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.21 0.13 + 0.043*sl 0.13 + 0.042*sl 0.13 + 0.042*sl sn to q t plh 0.93 0.82 + 0.054*sl 0.83 + 0.050*sl 0.83 + 0.050*sl t r 0.37 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.108*sl ckn to qn t plh 1.11 1.00 + 0.052*sl 1.01 + 0.050*sl 1.01 + 0.050*sl t phl 1.11 1.05 + 0.033*sl 1.07 + 0.026*sl 1.09 + 0.023*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.041*sl 0.11 + 0.042*sl rn to qn t plh 0.70 0.60 + 0.052*sl 0.61 + 0.050*sl 0.61 + 0.050*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.107*sl 0.12 + 0.109*sl sn to qn t plh 0.40 0.29 + 0.054*sl 0.30 + 0.050*sl 0.31 + 0.050*sl t phl 0.43 0.35 + 0.036*sl 0.38 + 0.026*sl 0.41 + 0.024*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.041*sl 0.12 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.97 0.90 + 0.031*sl 0.92 + 0.027*sl 0.93 + 0.025*sl t phl 0.84 0.79 + 0.024*sl 0.81 + 0.017*sl 0.84 + 0.013*sl t r 0.25 0.14 + 0.053*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.17 0.12 + 0.024*sl 0.13 + 0.022*sl 0.14 + 0.021*sl rn to q t plh 0.37 0.31 + 0.032*sl 0.32 + 0.026*sl 0.34 + 0.025*sl t phl 0.43 0.38 + 0.025*sl 0.40 + 0.017*sl 0.44 + 0.014*sl t r 0.24 0.14 + 0.052*sl 0.14 + 0.052*sl 0.12 + 0.053*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.021*sl 0.15 + 0.021*sl sn to q t plh 0.92 0.86 + 0.031*sl 0.87 + 0.026*sl 0.89 + 0.025*sl t r 0.25 0.14 + 0.053*sl 0.14 + 0.052*sl 0.13 + 0.053*sl ckn to qn t plh 1.17 1.11 + 0.028*sl 1.12 + 0.025*sl 1.12 + 0.025*sl t phl 1.19 1.15 + 0.021*sl 1.16 + 0.016*sl 1.19 + 0.013*sl t r 0.24 0.13 + 0.053*sl 0.14 + 0.052*sl 0.12 + 0.053*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.021*sl 0.14 + 0.020*sl rn to qn t plh 0.76 0.70 + 0.029*sl 0.71 + 0.025*sl 0.72 + 0.025*sl t r 0.24 0.13 + 0.055*sl 0.14 + 0.052*sl 0.13 + 0.053*sl sn to qn t plh 0.38 0.32 + 0.032*sl 0.33 + 0.026*sl 0.34 + 0.025*sl t phl 0.43 0.38 + 0.025*sl 0.40 + 0.017*sl 0.44 + 0.013*sl t r 0.24 0.13 + 0.053*sl 0.13 + 0.052*sl 0.12 + 0.053*sl t f 0.18 0.13 + 0.026*sl 0.14 + 0.021*sl 0.15 + 0.020*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 11, *grou p 3 : 11 < sl < < = =
kg80/KGM80 3-300 sec asic fd8s/fd8sd2 d flip-flop with negative edge trigger, reset, set, scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 fd8s fd8sd2 fd8s fd8sd2 d ti te ckn rn sn d ti te ckn rn sn 0.9 0.8 1.6 0.9 1.9 1.8 0.9 0.8 1.6 0.9 1.9 1.8 11.0 12.0 KGM80 fd8s fd8sd2 fd8s fd8sd2 d ti te ckn rn sn d ti te ckn rn sn 1.1 0.9 2.0 1.0 2.2 2.1 1.1 0.9 2.0 1.0 2.2 2.1 11.0 12.0 q qn d ti te ckn rn sn clbn cln q clbn cln clbn clbn cln qn cln sn sn rn rn d ti ckn cln clbn rn rn sn sn te truth table d ti te ckn rn sn q (n+1) qn (n+1) 0x0 11 0 1 1x0 11 1 0 x01 11 0 1 x11 11 1 0 xxxx10 1 0 xxxx01 0 1 xxxx00 0 0 x x x 1 1 q (n) qn (n)
sec asic 3-301 kg80/KGM80 fd8s/fd8sd2 d flip-flop with negative edge trigger, reset, set, scan, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 fd8s fd8sd2 fd8s fd8sd2 pulse width low (ckn) t pwl 0.61 0.61 0.99 0.99 pulse width high (ckn) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 0.99 pulse width low (sn) t pwl 0.61 0.64 1.02 1.05 input setup time (d to ckn) t su 0.42 0.42 0.80 0.80 input hold time (d to ckn) t hd 0.20 0.20 0.39 0.39 input setup time (ti to ckn) t su 0.47 0.47 0.93 0.93 input hold time (ti to ckn) t hd 0.15 0.15 0.33 0.33 input setup time (te to ckn) t su 0.42 0.45 0.77 0.77 input hold time (te to ckn) t hd 0.15 0.15 0.33 0.33 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ckn) t hd 0.53 0.53 0.85 0.85 recovery time (sn) t rc 0.15 0.15 0.33 0.33 input hold time (sn to ckn) t hd 0.26 0.26 0.63 0.63
kg80/KGM80 3-302 sec asic fd8s/fd8sd2 d flip-flop with negative edge trigger, reset, set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fd8s kg80 fd8sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.71 0.63 + 0.044*sl 0.63 + 0.042*sl 0.63 + 0.042*sl t phl 0.61 0.55 + 0.031*sl 0.56 + 0.026*sl 0.57 + 0.024*sl t r 0.29 0.11 + 0.086*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.09 + 0.042*sl 0.09 + 0.040*sl 0.09 + 0.041*sl rn to q t plh 0.29 0.20 + 0.044*sl 0.21 + 0.041*sl 0.21 + 0.041*sl t phl 0.33 0.27 + 0.032*sl 0.28 + 0.026*sl 0.30 + 0.024*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.18 0.11 + 0.040*sl 0.11 + 0.040*sl 0.10 + 0.041*sl sn to q t plh 0.65 0.56 + 0.043*sl 0.57 + 0.041*sl 0.57 + 0.041*sl t r 0.28 0.11 + 0.084*sl 0.11 + 0.088*sl 0.09 + 0.090*sl ckn to qn t plh 0.80 0.72 + 0.042*sl 0.72 + 0.041*sl 0.71 + 0.042*sl t phl 0.79 0.73 + 0.030*sl 0.75 + 0.025*sl 0.76 + 0.023*sl t r 0.28 0.10 + 0.086*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.08 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl rn to qn t plh 0.52 0.44 + 0.042*sl 0.44 + 0.041*sl 0.44 + 0.041*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl sn to qn t plh 0.29 0.20 + 0.043*sl 0.21 + 0.041*sl 0.21 + 0.042*sl t phl 0.33 0.26 + 0.032*sl 0.28 + 0.025*sl 0.29 + 0.024*sl t r 0.28 0.10 + 0.087*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.18 0.10 + 0.039*sl 0.10 + 0.039*sl 0.09 + 0.041*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.70 0.65 + 0.025*sl 0.66 + 0.022*sl 0.67 + 0.021*sl t phl 0.61 0.57 + 0.021*sl 0.58 + 0.016*sl 0.60 + 0.013*sl t r 0.19 0.11 + 0.042*sl 0.10 + 0.043*sl 0.10 + 0.044*sl t f 0.15 0.10 + 0.023*sl 0.11 + 0.020*sl 0.11 + 0.020*sl rn to q t plh 0.27 0.23 + 0.023*sl 0.23 + 0.022*sl 0.24 + 0.021*sl t phl 0.32 0.28 + 0.021*sl 0.29 + 0.016*sl 0.31 + 0.013*sl t r 0.19 0.10 + 0.041*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.15 0.11 + 0.022*sl 0.12 + 0.020*sl 0.12 + 0.020*sl sn to q t plh 0.64 0.59 + 0.025*sl 0.60 + 0.022*sl 0.61 + 0.021*sl t r 0.19 0.11 + 0.042*sl 0.10 + 0.043*sl 0.10 + 0.043*sl ckn to qn t plh 0.84 0.80 + 0.021*sl 0.80 + 0.020*sl 0.80 + 0.020*sl t phl 0.84 0.81 + 0.018*sl 0.81 + 0.015*sl 0.83 + 0.013*sl t r 0.18 0.10 + 0.042*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.019*sl 0.10 + 0.020*sl rn to qn t plh 0.56 0.52 + 0.022*sl 0.52 + 0.020*sl 0.52 + 0.020*sl t r 0.19 0.10 + 0.043*sl 0.10 + 0.043*sl 0.09 + 0.044*sl sn to qn t plh 0.28 0.23 + 0.024*sl 0.24 + 0.022*sl 0.24 + 0.021*sl t phl 0.32 0.28 + 0.021*sl 0.29 + 0.016*sl 0.31 + 0.013*sl t r 0.19 0.11 + 0.036*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.15 0.11 + 0.021*sl 0.11 + 0.019*sl 0.11 + 0.019*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 7, *grou p 3 : 7 < sl < < = =
sec asic 3-303 kg80/KGM80 fd8s/fd8sd2 d flip-flop with negative edge trigger, reset, set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fd8s KGM80 fd8sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.99 0.88 + 0.054*sl 0.89 + 0.051*sl 0.90 + 0.050*sl t phl 0.84 0.76 + 0.035*sl 0.79 + 0.027*sl 0.82 + 0.024*sl t r 0.37 0.16 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.108*sl t f 0.21 0.12 + 0.043*sl 0.12 + 0.042*sl 0.12 + 0.042*sl rn to q t plh 0.39 0.28 + 0.054*sl 0.29 + 0.050*sl 0.30 + 0.050*sl t phl 0.43 0.36 + 0.036*sl 0.38 + 0.027*sl 0.41 + 0.024*sl t r 0.37 0.16 + 0.104*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.21 0.13 + 0.042*sl 0.13 + 0.042*sl 0.13 + 0.042*sl sn to q t plh 0.91 0.80 + 0.054*sl 0.81 + 0.050*sl 0.81 + 0.050*sl t r 0.37 0.16 + 0.103*sl 0.15 + 0.106*sl 0.13 + 0.108*sl ckn to qn t plh 1.11 1.01 + 0.052*sl 1.01 + 0.050*sl 1.01 + 0.050*sl t phl 1.12 1.05 + 0.034*sl 1.08 + 0.026*sl 1.10 + 0.023*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.041*sl 0.11 + 0.042*sl rn to qn t plh 0.70 0.60 + 0.052*sl 0.60 + 0.050*sl 0.61 + 0.050*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.107*sl 0.12 + 0.109*sl sn to qn t plh 0.40 0.29 + 0.054*sl 0.30 + 0.050*sl 0.30 + 0.050*sl t phl 0.42 0.35 + 0.035*sl 0.38 + 0.026*sl 0.41 + 0.024*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.12 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ckn to q t plh 0.98 0.92 + 0.031*sl 0.93 + 0.027*sl 0.94 + 0.025*sl t phl 0.84 0.79 + 0.024*sl 0.81 + 0.017*sl 0.85 + 0.013*sl t r 0.25 0.14 + 0.053*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.17 0.12 + 0.024*sl 0.13 + 0.021*sl 0.14 + 0.021*sl rn to q t plh 0.37 0.31 + 0.031*sl 0.32 + 0.026*sl 0.34 + 0.025*sl t phl 0.43 0.38 + 0.025*sl 0.40 + 0.017*sl 0.44 + 0.013*sl t r 0.24 0.14 + 0.052*sl 0.14 + 0.052*sl 0.12 + 0.053*sl t f 0.18 0.13 + 0.026*sl 0.14 + 0.021*sl 0.15 + 0.020*sl sn to q t plh 0.90 0.84 + 0.031*sl 0.85 + 0.026*sl 0.87 + 0.025*sl t r 0.25 0.14 + 0.054*sl 0.15 + 0.052*sl 0.13 + 0.053*sl ckn to qn t plh 1.17 1.12 + 0.028*sl 1.12 + 0.025*sl 1.13 + 0.025*sl t phl 1.20 1.15 + 0.021*sl 1.17 + 0.016*sl 1.20 + 0.013*sl t r 0.24 0.13 + 0.054*sl 0.14 + 0.052*sl 0.12 + 0.053*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.021*sl 0.13 + 0.021*sl rn to qn t plh 0.76 0.70 + 0.029*sl 0.71 + 0.025*sl 0.72 + 0.025*sl t r 0.24 0.13 + 0.054*sl 0.14 + 0.052*sl 0.13 + 0.053*sl sn to qn t plh 0.38 0.32 + 0.031*sl 0.33 + 0.026*sl 0.35 + 0.025*sl t phl 0.43 0.38 + 0.025*sl 0.40 + 0.017*sl 0.44 + 0.013*sl t r 0.24 0.13 + 0.055*sl 0.14 + 0.052*sl 0.12 + 0.053*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.021*sl 0.15 + 0.020*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 11, *grou p 3 : 11 < sl < < = =
kg80/KGM80 3-304 sec asic fds2/fds2d2 d flip-flop with synchronous clear, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 fds2 fds2d2 fds2 fds2d2 d crn ck d crn ck 0.9 0.8 0.9 0.9 0.8 0.9 7.0 8.0 KGM80 fds2 fds2d2 fds2 fds2d2 d crn ck d crn ck 1.0 1.0 1.0 1.0 1.0 1.0 7.0 8.0 parameter symbol kg80 KGM80 fds2 fds2d2 fds2 fds2d2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 input setup time (d to ck) t su 0.42 0.42 0.77 0.80 input hold time (d to ck) t hd 0.15 0.15 0.33 0.33 input setup time (crn to ck) t su 0.42 0.42 0.77 0.80 input hold time (crn to ck) t hd 0.15 0.15 0.33 0.33 d crn ck q qn d ck cl clb q cl clb clb cl clb cl cl clb qn crn truth table d crn ck q (n+1) qn (n+1) 01 01 11 10 x0 01 x x q (n) qn (n)
sec asic 3-305 kg80/KGM80 fds2/fds2d2 d flip-flop with synchronous clear, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fds2 kg80 fds2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.50 0.42 + 0.042*sl 0.42 + 0.042*sl 0.42 + 0.042*sl t phl 0.52 0.46 + 0.030*sl 0.48 + 0.026*sl 0.49 + 0.023*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.08 + 0.041*sl ck to qn t plh 0.66 0.58 + 0.040*sl 0.58 + 0.041*sl 0.57 + 0.042*sl t phl 0.58 0.52 + 0.030*sl 0.53 + 0.025*sl 0.54 + 0.023*sl t r 0.26 0.09 + 0.085*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl *g 1 sl 2 *g 2 2 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.48 0.44 + 0.022*sl 0.44 + 0.021*sl 0.44 + 0.021*sl t phl 0.52 0.48 + 0.021*sl 0.49 + 0.015*sl 0.51 + 0.013*sl t r 0.17 0.08 + 0.042*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.09 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.020*sl ck to qn t plh 0.69 0.65 + 0.019*sl 0.65 + 0.019*sl 0.65 + 0.020*sl t phl 0.61 0.58 + 0.018*sl 0.59 + 0.015*sl 0.60 + 0.013*sl t r 0.17 0.08 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.022*sl 0.09 + 0.020*sl 0.10 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-306 sec asic fds2/fds2d2 d flip-flop with synchronous clear, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fds2 KGM80 fds2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.69 0.59 + 0.051*sl 0.59 + 0.050*sl 0.60 + 0.050*sl t phl 0.74 0.67 + 0.034*sl 0.69 + 0.026*sl 0.72 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl ck to qn t plh 0.93 0.83 + 0.049*sl 0.83 + 0.050*sl 0.83 + 0.050*sl t phl 0.81 0.75 + 0.033*sl 0.77 + 0.026*sl 0.79 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl *g 1 sl 3 *g 2 3 sl 11 *g 3 11 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.67 0.61 + 0.028*sl 0.62 + 0.025*sl 0.62 + 0.025*sl t phl 0.74 0.69 + 0.023*sl 0.71 + 0.016*sl 0.75 + 0.013*sl t r 0.22 0.11 + 0.051*sl 0.11 + 0.053*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.022*sl 0.13 + 0.021*sl ck to qn t plh 0.98 0.93 + 0.024*sl 0.93 + 0.024*sl 0.92 + 0.025*sl t phl 0.87 0.83 + 0.021*sl 0.84 + 0.016*sl 0.87 + 0.013*sl t r 0.22 0.11 + 0.051*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-307 kg80/KGM80 fds2cs/fds2csd2 d flip-flop with synchronous clear, scan clock, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 fds2cs fds2csd2 fds2cs fds2csd2 si sck d crn ck si sck d crn ck 0.9 2.1 0.9 0.8 0.9 0.9 2.1 0.9 0.8 0.9 11.0 12.0 KGM80 fds2cs fds2csd2 fds2cs fds2csd2 si sck d crn ck si sck d crn ck 1.0 2.4 1.0 1.0 1.0 1.0 2.5 1.0 1.0 1.0 11.0 12.0 q qn si crn ck sck d d cl clb q clb cl clb cl cl clb qn crn sck sckb sck sckb sckb sck sckb sck si cl clb sck sck sckb ck truth table si sck d crn ck q (n+1) qn (n+1) x001 01 x011 10 0 x1001 1 x1010 xxx0 01
kg80/KGM80 3-308 sec asic fds2cs/fds2csd2 d flip-flop with synchronous clear, scan clock, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 fds2cs fds2csd2 fds2cs fds2csd2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (sck) t pwl 0.61 0.61 0.99 0.99 pulse width high (sck) t pwh 0.61 0.61 0.99 0.99 input setup time (d to ck) t su 0.42 0.42 0.77 0.77 input hold time (d to ck) t hd 0.15 0.15 0.33 0.33 input setup time (si to sck) t su 0.56 0.56 0.96 0.96 input hold time (si to sck) t hd 0.15 0.15 0.33 0.33 input setup time (crn to ck) t su 0.42 0.42 0.33 0.33 input hold time (crn to ck) t hd 0.15 0.15 0.33 0.33
sec asic 3-309 kg80/KGM80 fds2cs/fds2csd2 d flip-flop with synchronous clear, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fds2cs kg80 fds2csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.51 0.42 + 0.041*sl 0.42 + 0.042*sl 0.42 + 0.042*sl t phl 0.52 0.46 + 0.030*sl 0.48 + 0.025*sl 0.49 + 0.024*sl t r 0.27 0.09 + 0.087*sl 0.09 + 0.090*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl sck to q t plh 0.54 0.46 + 0.042*sl 0.46 + 0.042*sl 0.46 + 0.041*sl t phl 0.47 0.41 + 0.031*sl 0.42 + 0.026*sl 0.44 + 0.023*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.089*sl 0.09 + 0.090*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.040*sl 0.09 + 0.041*sl ck to qn t plh 0.73 0.64 + 0.042*sl 0.65 + 0.041*sl 0.64 + 0.041*sl t phl 0.67 0.60 + 0.035*sl 0.61 + 0.028*sl 0.64 + 0.025*sl t r 0.29 0.12 + 0.084*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.040*sl 0.13 + 0.041*sl sck to qn t plh 0.61 0.53 + 0.040*sl 0.52 + 0.041*sl 0.52 + 0.042*sl t phl 0.62 0.56 + 0.029*sl 0.57 + 0.025*sl 0.58 + 0.023*sl t r 0.27 0.09 + 0.086*sl 0.09 + 0.090*sl 0.08 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.49 0.44 + 0.022*sl 0.45 + 0.021*sl 0.44 + 0.021*sl t phl 0.52 0.48 + 0.020*sl 0.49 + 0.015*sl 0.51 + 0.013*sl t r 0.17 0.08 + 0.042*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.09 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.020*sl sck to q t plh 0.53 0.49 + 0.023*sl 0.49 + 0.021*sl 0.50 + 0.020*sl t phl 0.47 0.43 + 0.020*sl 0.44 + 0.016*sl 0.46 + 0.013*sl t r 0.18 0.10 + 0.039*sl 0.10 + 0.042*sl 0.08 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.11 + 0.020*sl 0.11 + 0.020*sl ck to qn t plh 0.76 0.71 + 0.022*sl 0.72 + 0.020*sl 0.72 + 0.020*sl t phl 0.69 0.65 + 0.023*sl 0.66 + 0.017*sl 0.68 + 0.014*sl t r 0.19 0.10 + 0.042*sl 0.10 + 0.042*sl 0.10 + 0.043*sl t f 0.18 0.12 + 0.026*sl 0.14 + 0.021*sl 0.14 + 0.020*sl sck to qn t plh 0.64 0.60 + 0.019*sl 0.60 + 0.019*sl 0.59 + 0.020*sl t phl 0.67 0.63 + 0.018*sl 0.64 + 0.014*sl 0.65 + 0.013*sl t r 0.17 0.08 + 0.042*sl 0.08 + 0.043*sl 0.07 + 0.045*sl t f 0.14 0.09 + 0.022*sl 0.10 + 0.019*sl 0.10 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-310 sec asic fds2cs/fds2csd2 d flip-flop with synchronous clear, scan clock, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fds2cs KGM80 fds2csd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.70 0.60 + 0.051*sl 0.60 + 0.050*sl 0.61 + 0.050*sl t phl 0.74 0.67 + 0.034*sl 0.69 + 0.026*sl 0.72 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.042*sl 0.11 + 0.042*sl sck to q t plh 0.80 0.69 + 0.052*sl 0.70 + 0.050*sl 0.70 + 0.050*sl t phl 0.65 0.58 + 0.035*sl 0.61 + 0.026*sl 0.64 + 0.023*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.041*sl 0.12 + 0.042*sl ck to qn t plh 1.02 0.91 + 0.053*sl 0.92 + 0.050*sl 0.92 + 0.050*sl t phl 0.95 0.87 + 0.040*sl 0.89 + 0.030*sl 0.94 + 0.025*sl t r 0.38 0.17 + 0.102*sl 0.16 + 0.106*sl 0.13 + 0.108*sl t f 0.25 0.15 + 0.048*sl 0.17 + 0.043*sl 0.18 + 0.042*sl sck to qn t plh 0.85 0.75 + 0.049*sl 0.75 + 0.050*sl 0.75 + 0.050*sl t phl 0.92 0.85 + 0.032*sl 0.87 + 0.026*sl 0.89 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.11 + 0.042*sl 0.11 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.67 0.62 + 0.028*sl 0.63 + 0.025*sl 0.63 + 0.025*sl t phl 0.74 0.69 + 0.023*sl 0.71 + 0.016*sl 0.75 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.021*sl sck to q t plh 0.79 0.73 + 0.029*sl 0.74 + 0.025*sl 0.74 + 0.025*sl t phl 0.66 0.62 + 0.024*sl 0.63 + 0.017*sl 0.67 + 0.013*sl t r 0.24 0.14 + 0.050*sl 0.13 + 0.052*sl 0.11 + 0.053*sl t f 0.17 0.12 + 0.026*sl 0.13 + 0.021*sl 0.14 + 0.020*sl ck to qn t plh 1.06 1.00 + 0.030*sl 1.01 + 0.025*sl 1.02 + 0.024*sl t phl 0.99 0.94 + 0.027*sl 0.96 + 0.019*sl 1.00 + 0.015*sl t r 0.25 0.14 + 0.053*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.21 0.16 + 0.028*sl 0.17 + 0.023*sl 0.19 + 0.021*sl sck to qn t plh 0.90 0.85 + 0.024*sl 0.85 + 0.024*sl 0.84 + 0.025*sl t phl 0.99 0.95 + 0.020*sl 0.97 + 0.016*sl 1.00 + 0.013*sl t r 0.22 0.11 + 0.052*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-311 kg80/KGM80 fds2s/fds2sd2 d flip-flop with synchronous clear, scan, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 fds2s fds2sd2 fds2s fds2sd2 d crn ti te ck d crn ti te ck 0.9 0.8 0.9 1.7 0.9 0.9 0.8 0.9 1.7 0.9 10.0 11.0 KGM80 fds2s fds2sd2 fds2s fds2sd2 d crn ti te ck d crn ti te ck 1.0 1.0 1.0 2.0 1.0 1.0 1.0 1.0 2.0 1.0 10.0 11.0 parameter symbol kg80 KGM80 fds2s fds2sd2 fds2s fds2sd2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 input setup time (d to ck) t su 0.58 0.58 0.99 0.99 input hold time (d to ck) t hd 0.15 0.15 0.33 0.33 input setup time (crn to ck) t su 0.58 0.58 0.99 0.99 input hold time (crn to ck) t hd 0.15 0.15 0.33 0.33 input setup time (ti to ck) t su 0.56 0.56 1.02 0.99 input hold time (ti to ck) t hd 0.15 0.15 0.33 0.33 input setup time (te to ck) t su 0.47 0.47 0.83 0.83 input hold time (te to ck) t hd 0.15 0.15 0.33 0.33 q qn d te ck crn ti qn q clb cl cl clb cl clb clb cl d crn te ti cl ck clb truth table d crn ti te ck q (n+1) qn (n+1) 01x0 01 11x0 10 x0x0 01 xx01 01 xx11 10 x x x x q (n) qn (n)
kg80/KGM80 3-312 sec asic fds2s/fds2sd2 d flip-flop with synchronous clear, scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fds2s kg80 fds2sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.66 0.58 + 0.040*sl 0.58 + 0.041*sl 0.57 + 0.042*sl t phl 0.58 0.52 + 0.030*sl 0.53 + 0.025*sl 0.54 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.041*sl 0.08 + 0.040*sl 0.07 + 0.042*sl ck to qn t plh 0.50 0.42 + 0.042*sl 0.42 + 0.042*sl 0.42 + 0.042*sl t phl 0.53 0.46 + 0.031*sl 0.48 + 0.026*sl 0.49 + 0.023*sl t r 0.27 0.09 + 0.087*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.08 + 0.041*sl *g 1 sl 2 *g 2 2 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.69 0.65 + 0.019*sl 0.65 + 0.019*sl 0.64 + 0.020*sl t phl 0.62 0.58 + 0.018*sl 0.59 + 0.015*sl 0.60 + 0.013*sl t r 0.17 0.09 + 0.038*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.021*sl 0.09 + 0.020*sl 0.10 + 0.020*sl ck to qn t plh 0.48 0.44 + 0.022*sl 0.44 + 0.021*sl 0.44 + 0.021*sl t phl 0.52 0.48 + 0.020*sl 0.49 + 0.015*sl 0.51 + 0.013*sl t r 0.17 0.08 + 0.042*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.09 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-313 kg80/KGM80 fds2s/fds2sd2 d flip-flop with synchronous clear, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fds2s KGM80 fds2sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.93 0.83 + 0.049*sl 0.83 + 0.050*sl 0.83 + 0.050*sl t phl 0.81 0.75 + 0.033*sl 0.77 + 0.026*sl 0.79 + 0.023*sl t r 0.34 0.13 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl ck to qn t plh 0.69 0.59 + 0.051*sl 0.60 + 0.050*sl 0.60 + 0.050*sl t phl 0.74 0.67 + 0.034*sl 0.69 + 0.026*sl 0.72 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl *g 1 sl 3 *g 2 3 sl 11 *g 3 11 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.98 0.93 + 0.025*sl 0.93 + 0.024*sl 0.92 + 0.025*sl t phl 0.87 0.83 + 0.021*sl 0.84 + 0.016*sl 0.87 + 0.013*sl t r 0.21 0.11 + 0.051*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.026*sl 0.12 + 0.021*sl 0.13 + 0.021*sl ck to qn t plh 0.67 0.61 + 0.028*sl 0.62 + 0.025*sl 0.62 + 0.025*sl t phl 0.74 0.69 + 0.023*sl 0.71 + 0.016*sl 0.75 + 0.013*sl t r 0.22 0.11 + 0.051*sl 0.11 + 0.053*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.022*sl 0.13 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-314 sec asic fds3/fds3d2 d flip-flop with synchronous set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 fds3 fds3d2 fds3 fds3d2 d csn ck d csn ck 0.8 0.8 0.8 0.8 0.8 0.8 8.0 9.0 KGM80 fds3 fds3d2 fds3 fds3d2 d csn ck d csn ck 0.9 0.9 0.9 0.9 0.9 0.9 8.0 9.0 parameter symbol kg80 KGM80 fds2 fds2d2 fds2 fds2d2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 input setup time (d to ck) t su 0.15 0.15 0.33 0.33 input hold time (d to ck) t hd 0.15 0.15 0.33 0.33 input setup time (csn to ck) t su 0.45 0.45 0.77 0.77 input hold time (csn to ck) t hd 0.15 0.15 0.33 0.33 d csn ck q qn qn q clb cl cl clb cl clb clb cl cl ck clb d csn truth table d csn ck q (n+1) qn (n+1) 01 01 11 10 x0 10 x x q (n) qn (n)
sec asic 3-315 kg80/KGM80 fds3/fds3d2 d flip-flop with synchronous set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fds3 kg80 fds3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.62 0.54 + 0.040*sl 0.54 + 0.041*sl 0.54 + 0.042*sl t phl 0.56 0.50 + 0.028*sl 0.51 + 0.025*sl 0.52 + 0.023*sl t r 0.26 0.08 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.15 0.07 + 0.040*sl 0.07 + 0.041*sl 0.06 + 0.042*sl ck to qn t plh 0.49 0.41 + 0.042*sl 0.41 + 0.042*sl 0.41 + 0.042*sl t phl 0.50 0.44 + 0.030*sl 0.45 + 0.025*sl 0.46 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.041*sl 0.08 + 0.040*sl 0.07 + 0.042*sl *g 1 sl 2 *g 2 2 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.65 0.61 + 0.019*sl 0.61 + 0.020*sl 0.60 + 0.021*sl t phl 0.59 0.55 + 0.017*sl 0.56 + 0.014*sl 0.57 + 0.012*sl t r 0.18 0.09 + 0.043*sl 0.09 + 0.044*sl 0.08 + 0.045*sl t f 0.13 0.09 + 0.021*sl 0.09 + 0.019*sl 0.09 + 0.020*sl ck to qn t plh 0.48 0.44 + 0.021*sl 0.44 + 0.021*sl 0.44 + 0.021*sl t phl 0.50 0.46 + 0.018*sl 0.47 + 0.015*sl 0.48 + 0.013*sl t r 0.18 0.10 + 0.044*sl 0.10 + 0.044*sl 0.08 + 0.045*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-316 sec asic fds3/fds3d2 d flip-flop with synchronous clear, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fds3 KGM80 fds3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.88 0.78 + 0.049*sl 0.78 + 0.050*sl 0.78 + 0.050*sl t phl 0.80 0.74 + 0.031*sl 0.76 + 0.025*sl 0.78 + 0.023*sl t r 0.33 0.12 + 0.105*sl 0.11 + 0.109*sl 0.11 + 0.109*sl t f 0.18 0.10 + 0.043*sl 0.10 + 0.042*sl 0.09 + 0.043*sl ck to qn t plh 0.70 0.60 + 0.051*sl 0.60 + 0.050*sl 0.60 + 0.050*sl t phl 0.70 0.63 + 0.034*sl 0.65 + 0.026*sl 0.68 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.044*sl 0.11 + 0.041*sl 0.10 + 0.042*sl *g 1 sl 3 *g 2 3 sl 11 *g 3 11 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.92 0.87 + 0.023*sl 0.87 + 0.024*sl 0.86 + 0.025*sl t phl 0.86 0.82 + 0.019*sl 0.83 + 0.015*sl 0.85 + 0.012*sl t r 0.23 0.13 + 0.051*sl 0.13 + 0.053*sl 0.11 + 0.054*sl t f 0.16 0.11 + 0.023*sl 0.12 + 0.021*sl 0.12 + 0.020*sl ck to qn t plh 0.69 0.63 + 0.027*sl 0.64 + 0.025*sl 0.64 + 0.025*sl t phl 0.71 0.67 + 0.021*sl 0.68 + 0.015*sl 0.71 + 0.013*sl t r 0.24 0.14 + 0.051*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.17 0.12 + 0.023*sl 0.13 + 0.021*sl 0.13 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-317 kg80/KGM80 fg1 d flip-flop with ck enable logic symbol schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 pulse width low (ck) t pwl 0.61 0.99 pulse width high (ck) t pwh 0.61 0.99 pulse width low (e) t pwl 0.61 0.99 pulse width high (e) t pwh 0.61 0.99 input setup time (d to ck) t su 0.31 0.58 input hold time (d to ck) t hd 0.15 0.33 input setup time (d to e) t su 0.31 0.58 input hold time (d to e) t hd 0.15 0.33 dq qn e ck d cke ckeb ckeb cke ckeb cke q cke ckeb qn cke ck ckeb e truth table cell data d e ck q (n+1) qn (n+1) 01 01 11 10 x 0 x q (n) qn (n) x x q (n) qn (n) input load (sl) gate count kg80 deck 7.0 1.0 0.9 0.9 KGM80 deck 7.0 1.0 1.0 1.0
kg80/KGM80 3-318 sec asic fg1 d flip-flop with ck enable switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fg1 switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fg1 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.58 0.49 + 0.042*sl 0.49 + 0.042*sl 0.50 + 0.042*sl t phl 0.60 0.54 + 0.030*sl 0.55 + 0.026*sl 0.56 + 0.023*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.08 + 0.041*sl e to q t plh 0.56 0.48 + 0.042*sl 0.48 + 0.042*sl 0.48 + 0.042*sl t phl 0.58 0.52 + 0.031*sl 0.53 + 0.026*sl 0.55 + 0.023*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.08 + 0.041*sl ck to qn t plh 0.73 0.65 + 0.040*sl 0.65 + 0.041*sl 0.65 + 0.042*sl t phl 0.65 0.60 + 0.029*sl 0.61 + 0.025*sl 0.62 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.041*sl 0.08 + 0.040*sl 0.07 + 0.042*sl e to qn t plh 0.72 0.64 + 0.040*sl 0.63 + 0.041*sl 0.63 + 0.042*sl t phl 0.64 0.58 + 0.030*sl 0.59 + 0.025*sl 0.60 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.80 0.70 + 0.051*sl 0.70 + 0.050*sl 0.70 + 0.050*sl t phl 0.83 0.77 + 0.033*sl 0.79 + 0.026*sl 0.82 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl e to q t plh 0.79 0.69 + 0.051*sl 0.69 + 0.050*sl 0.69 + 0.050*sl t phl 0.82 0.76 + 0.034*sl 0.78 + 0.026*sl 0.81 + 0.024*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl ck to qn t plh 1.03 0.93 + 0.048*sl 0.93 + 0.050*sl 0.93 + 0.050*sl t phl 0.92 0.85 + 0.033*sl 0.87 + 0.026*sl 0.90 + 0.023*sl t r 0.34 0.13 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl e to qn t plh 1.02 0.92 + 0.049*sl 0.92 + 0.050*sl 0.92 + 0.050*sl t phl 0.91 0.84 + 0.033*sl 0.86 + 0.026*sl 0.89 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-319 kg80/KGM80 fg1x4 4-bit d flip-flop with ck enable logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 pulse width low (ck) t pwl 0.78 1.24 pulse width high (ck) t pwh 0.69 1.11 pulse width low (e) t pwl 0.80 1.30 pulse width high (e) t pwh 0.67 1.08 input setup time (d0 to ck) t su 0.15 0.33 input hold time (d0 to ck) t hd 0.37 0.58 input setup time (d0 to e) t su 0.15 0.33 input hold time (d0 to e) t hd 0.34 0.58 input setup time (d1 to ck) t su 0.15 0.33 input hold time (d1 to ck) t hd 0.37 0.58 input setup time (d1 to e) t su 0.15 0.33 input hold time (d1 to e) t hd 0.34 0.55 input setup time (d2 to ck) t su 0.15 0.33 input hold time (d2 to ck) t hd 0.37 0.58 input setup time (d2 to e) t su 0.15 0.33 input hold time (d2 to e) t hd 0.34 0.55 input setup time (d3 to ck) t su 0.15 0.33 input hold time (d3 to ck) t hd 0.37 0.58 input setup time (d3 to e) t su 0.15 0.33 input hold time (d3 to e) t hd 0.34 0.55 d0 d1 d2 d3 q0 q1 q2 q3 qn0 qn1 qn2 qn3 e ck truth table cell data dn e ck qn (n+1) qnn (n+1) 01 0 1 11 1 0 x 0 x qn (n) qnn (n) x x qn (n) qnn (n) input load (sl) gate count kg80 dn e ck 25.0 0.9 0.8 0.6 KGM80 dn e ck 25.0 1.0 0.9 0.7
kg80/KGM80 3-320 sec asic fg1x4 4-bit d flip-flop with ck enable switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fg1x4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.80 0.71 + 0.042*sl 0.71 + 0.042*sl 0.71 + 0.042*sl t phl 0.97 0.90 + 0.030*sl 0.92 + 0.026*sl 0.93 + 0.023*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.09 + 0.041*sl e to q0 t plh 0.78 0.70 + 0.042*sl 0.70 + 0.042*sl 0.70 + 0.042*sl t phl 0.95 0.89 + 0.031*sl 0.90 + 0.026*sl 0.91 + 0.023*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.08 + 0.041*sl ck to q1 t plh 0.80 0.72 + 0.042*sl 0.72 + 0.041*sl 0.72 + 0.042*sl t phl 0.97 0.91 + 0.030*sl 0.92 + 0.026*sl 0.94 + 0.023*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.089*sl 0.09 + 0.091*sl t f 0.18 0.09 + 0.040*sl 0.10 + 0.040*sl 0.09 + 0.041*sl e to q1 t plh 0.79 0.70 + 0.042*sl 0.70 + 0.042*sl 0.70 + 0.042*sl t phl 0.95 0.89 + 0.031*sl 0.90 + 0.026*sl 0.92 + 0.024*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.089*sl 0.09 + 0.091*sl t f 0.18 0.09 + 0.041*sl 0.10 + 0.040*sl 0.09 + 0.041*sl ck to q2 t plh 0.80 0.72 + 0.042*sl 0.72 + 0.041*sl 0.72 + 0.042*sl t phl 0.97 0.91 + 0.030*sl 0.92 + 0.026*sl 0.94 + 0.023*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.089*sl 0.09 + 0.091*sl t f 0.18 0.09 + 0.040*sl 0.10 + 0.040*sl 0.09 + 0.041*sl e to q2 t plh 0.79 0.70 + 0.042*sl 0.70 + 0.042*sl 0.70 + 0.042*sl t phl 0.95 0.89 + 0.031*sl 0.90 + 0.026*sl 0.92 + 0.024*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.089*sl 0.09 + 0.091*sl t f 0.18 0.09 + 0.041*sl 0.10 + 0.040*sl 0.09 + 0.041*sl ck to q3 t plh 0.80 0.71 + 0.042*sl 0.71 + 0.042*sl 0.71 + 0.042*sl t phl 0.97 0.90 + 0.030*sl 0.92 + 0.026*sl 0.93 + 0.023*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.09 + 0.041*sl e to q3 t plh 0.78 0.70 + 0.042*sl 0.70 + 0.042*sl 0.70 + 0.042*sl t phl 0.95 0.89 + 0.031*sl 0.90 + 0.026*sl 0.91 + 0.023*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.08 + 0.041*sl ck to qn0 t plh 1.10 1.02 + 0.040*sl 1.01 + 0.041*sl 1.01 + 0.042*sl t phl 0.87 0.81 + 0.030*sl 0.82 + 0.025*sl 0.83 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.041*sl 0.08 + 0.040*sl 0.07 + 0.042*sl e to qn0 t plh 1.08 1.00 + 0.041*sl 1.00 + 0.041*sl 1.00 + 0.041*sl t phl 0.85 0.79 + 0.030*sl 0.80 + 0.025*sl 0.82 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.041*sl 0.08 + 0.040*sl 0.07 + 0.042*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-321 kg80/KGM80 fg1x4 4-bit d flip-flop with ck enable switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fg1x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to qn1 t plh 1.10 1.02 + 0.040*sl 1.02 + 0.041*sl 1.02 + 0.042*sl t phl 0.88 0.82 + 0.029*sl 0.83 + 0.025*sl 0.84 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.08 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl e to qn1 t plh 1.09 1.01 + 0.040*sl 1.00 + 0.041*sl 1.00 + 0.042*sl t phl 0.86 0.80 + 0.030*sl 0.81 + 0.025*sl 0.82 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl ck to qn2 t plh 1.10 1.02 + 0.040*sl 1.02 + 0.041*sl 1.02 + 0.042*sl t phl 0.88 0.82 + 0.029*sl 0.83 + 0.025*sl 0.84 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl e to qn2 t plh 1.09 1.01 + 0.040*sl 1.00 + 0.041*sl 1.00 + 0.042*sl t phl 0.86 0.80 + 0.030*sl 0.81 + 0.025*sl 0.82 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl ck to qn3 t plh 1.10 1.02 + 0.040*sl 1.01 + 0.041*sl 1.01 + 0.042*sl t phl 0.87 0.81 + 0.030*sl 0.82 + 0.025*sl 0.83 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.041*sl 0.08 + 0.040*sl 0.07 + 0.042*sl e to qn3 t plh 1.08 1.00 + 0.041*sl 1.00 + 0.041*sl 1.00 + 0.041*sl t phl 0.85 0.79 + 0.030*sl 0.80 + 0.025*sl 0.82 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.041*sl 0.08 + 0.040*sl 0.07 + 0.042*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-322 sec asic fg1x4 4-bit d flip-flop with ck enable switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fg1x4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 1.08 0.97 + 0.051*sl 0.98 + 0.050*sl 0.98 + 0.050*sl t phl 1.36 1.29 + 0.034*sl 1.31 + 0.026*sl 1.34 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl e to q0 t plh 1.07 0.96 + 0.051*sl 0.97 + 0.050*sl 0.97 + 0.050*sl t phl 1.35 1.28 + 0.034*sl 1.30 + 0.026*sl 1.33 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.11 + 0.042*sl ck to q1 t plh 1.09 0.98 + 0.051*sl 0.99 + 0.050*sl 0.99 + 0.050*sl t phl 1.36 1.30 + 0.034*sl 1.32 + 0.026*sl 1.35 + 0.023*sl t r 0.36 0.15 + 0.105*sl 0.14 + 0.108*sl 0.13 + 0.109*sl t f 0.21 0.12 + 0.045*sl 0.13 + 0.041*sl 0.12 + 0.042*sl e to q1 t plh 1.08 0.97 + 0.051*sl 0.98 + 0.050*sl 0.98 + 0.050*sl t phl 1.36 1.29 + 0.034*sl 1.31 + 0.026*sl 1.34 + 0.023*sl t r 0.36 0.15 + 0.105*sl 0.14 + 0.108*sl 0.13 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.12 + 0.042*sl ck to q2 t plh 1.09 0.98 + 0.051*sl 0.99 + 0.050*sl 0.99 + 0.050*sl t phl 1.36 1.30 + 0.034*sl 1.32 + 0.026*sl 1.35 + 0.023*sl t r 0.36 0.15 + 0.105*sl 0.14 + 0.108*sl 0.13 + 0.109*sl t f 0.21 0.12 + 0.045*sl 0.13 + 0.041*sl 0.12 + 0.042*sl e to q2 t plh 1.08 0.97 + 0.051*sl 0.98 + 0.050*sl 0.98 + 0.050*sl t phl 1.36 1.29 + 0.034*sl 1.31 + 0.026*sl 1.34 + 0.023*sl t r 0.36 0.15 + 0.105*sl 0.14 + 0.108*sl 0.13 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.12 + 0.042*sl ck to q3 t plh 1.08 0.97 + 0.051*sl 0.98 + 0.050*sl 0.98 + 0.050*sl t phl 1.36 1.29 + 0.034*sl 1.31 + 0.026*sl 1.34 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl e to q3 t plh 1.07 0.96 + 0.051*sl 0.97 + 0.050*sl 0.97 + 0.050*sl t phl 1.35 1.28 + 0.034*sl 1.30 + 0.026*sl 1.33 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.11 + 0.042*sl ck to qn0 t plh 1.55 1.45 + 0.049*sl 1.45 + 0.050*sl 1.45 + 0.050*sl t phl 1.20 1.13 + 0.033*sl 1.15 + 0.026*sl 1.17 + 0.023*sl t r 0.34 0.13 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl e to qn0 t plh 1.54 1.44 + 0.049*sl 1.44 + 0.050*sl 1.44 + 0.050*sl t phl 1.19 1.12 + 0.033*sl 1.14 + 0.026*sl 1.16 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-323 kg80/KGM80 fg1x4 4-bit d flip-flop with ck enable switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 kg1x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to qn1 t plh 1.56 1.46 + 0.049*sl 1.46 + 0.050*sl 1.46 + 0.050*sl t phl 1.21 1.14 + 0.033*sl 1.16 + 0.026*sl 1.19 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.041*sl 0.10 + 0.042*sl e to qn1 t plh 1.55 1.45 + 0.049*sl 1.45 + 0.050*sl 1.45 + 0.050*sl t phl 1.20 1.13 + 0.032*sl 1.15 + 0.026*sl 1.18 + 0.023*sl t r 0.34 0.14 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.041*sl 0.10 + 0.042*sl ck to qn2 t plh 1.56 1.46 + 0.049*sl 1.46 + 0.050*sl 1.46 + 0.050*sl t phl 1.21 1.14 + 0.033*sl 1.16 + 0.026*sl 1.19 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.041*sl 0.10 + 0.042*sl e to qn2 t plh 1.55 1.45 + 0.049*sl 1.45 + 0.050*sl 1.45 + 0.050*sl t phl 1.20 1.13 + 0.033*sl 1.15 + 0.026*sl 1.18 + 0.023*sl t r 0.34 0.14 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.041*sl 0.10 + 0.042*sl ck to qn3 t plh 1.55 1.45 + 0.049*sl 1.45 + 0.050*sl 1.45 + 0.050*sl t phl 1.20 1.13 + 0.033*sl 1.15 + 0.026*sl 1.17 + 0.023*sl t r 0.34 0.13 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl e to qn3 t plh 1.54 1.44 + 0.049*sl 1.44 + 0.050*sl 1.44 + 0.050*sl t phl 1.19 1.12 + 0.033*sl 1.14 + 0.026*sl 1.16 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-324 sec asic fg2 d flip-flop with ck enable, reset logic symbol schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 pulse width low (ck) t pwl 0.61 0.99 pulse width high (ck) t pwh 0.61 0.99 pulse width low (e) t pwl 0.61 0.99 pulse width high (e) t pwh 0.61 0.99 pulse width low (rn) t pwl 0.61 0.99 input setup time (d to ck) t su 0.31 0.58 input hold time (d to ck) t hd 0.15 0.33 input setup time (d to e) t su 0.31 0.58 input hold time (d to e) t hd 0.15 0.33 recovery time (rn to ck) t rc 0.15 0.33 input hold time (rn to ck) t hd 0.48 0.85 recovery time (rn to e) t rc 0.15 0.33 input hold time (rn to e) t hd 0.48 0.85 dq qn rn e ck cke ck ckeb e d ckeb cke cke ckeb ckeb cke q cke ckeb qn rn rn rn rn truth table cell data d e ck rn q (n+1) qn (n+1) 01 101 11 110 x 0 x 1 q (n) qn (n) xxx001 x x 1 q (n) qn (n) input load (sl) gate count kg80 d e ck rn 8.0 1.0 0.9 0.9 1.5 KGM80 d e ck rn 8.0 1.0 1.0 1.1 1.9
sec asic 3-325 kg80/KGM80 fg2 d flip-flop with ck enable, reset switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fg2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.64 0.55 + 0.044*sl 0.56 + 0.042*sl 0.57 + 0.041*sl t phl 0.62 0.55 + 0.031*sl 0.57 + 0.026*sl 0.58 + 0.024*sl t r 0.28 0.11 + 0.086*sl 0.11 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.042*sl 0.10 + 0.040*sl 0.09 + 0.041*sl e to q t plh 0.63 0.54 + 0.045*sl 0.55 + 0.042*sl 0.55 + 0.042*sl t phl 0.60 0.54 + 0.031*sl 0.55 + 0.026*sl 0.57 + 0.024*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.09 + 0.041*sl rn to q t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.31 + 0.024*sl t f 0.19 0.11 + 0.041*sl 0.11 + 0.039*sl 0.10 + 0.040*sl ck to qn t plh 0.75 0.67 + 0.040*sl 0.67 + 0.041*sl 0.67 + 0.042*sl t phl 0.72 0.66 + 0.030*sl 0.67 + 0.025*sl 0.68 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.08 + 0.091*sl t f 0.16 0.09 + 0.039*sl 0.08 + 0.040*sl 0.07 + 0.042*sl e to qn t plh 0.74 0.66 + 0.040*sl 0.65 + 0.041*sl 0.65 + 0.042*sl t phl 0.71 0.65 + 0.030*sl 0.66 + 0.025*sl 0.67 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.08 + 0.091*sl t f 0.16 0.09 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl rn to qn t plh 0.48 0.40 + 0.040*sl 0.39 + 0.041*sl 0.39 + 0.042*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.08 + 0.091*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 7, *grou p 3 : 7 < sl < < = =
kg80/KGM80 3-326 sec asic fg2 d flip-flop with ck enable, reset switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fg2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.89 0.78 + 0.055*sl 0.80 + 0.051*sl 0.81 + 0.050*sl t phl 0.86 0.79 + 0.036*sl 0.82 + 0.027*sl 0.85 + 0.023*sl t r 0.37 0.16 + 0.104*sl 0.15 + 0.107*sl 0.13 + 0.108*sl t f 0.21 0.12 + 0.045*sl 0.13 + 0.041*sl 0.12 + 0.042*sl e to q t plh 0.88 0.77 + 0.055*sl 0.79 + 0.051*sl 0.80 + 0.050*sl t phl 0.86 0.78 + 0.036*sl 0.81 + 0.027*sl 0.84 + 0.024*sl t r 0.37 0.16 + 0.105*sl 0.15 + 0.107*sl 0.13 + 0.108*sl t f 0.21 0.12 + 0.045*sl 0.13 + 0.041*sl 0.12 + 0.042*sl rn to q t phl 0.44 0.37 + 0.037*sl 0.39 + 0.027*sl 0.43 + 0.024*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.041*sl 0.13 + 0.042*sl ck to qn t plh 1.06 0.96 + 0.049*sl 0.96 + 0.050*sl 0.96 + 0.050*sl t phl 1.02 0.95 + 0.033*sl 0.97 + 0.026*sl 0.99 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.11 + 0.041*sl 0.10 + 0.042*sl e to qn t plh 1.05 0.95 + 0.049*sl 0.95 + 0.050*sl 0.95 + 0.050*sl t phl 1.01 0.94 + 0.033*sl 0.96 + 0.025*sl 0.98 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.042*sl 0.11 + 0.041*sl 0.10 + 0.042*sl rn to qn t plh 0.64 0.54 + 0.049*sl 0.54 + 0.050*sl 0.54 + 0.050*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 11, *grou p 3 : 11 < sl < < = =
sec asic 3-327 kg80/KGM80 fg2x4 4-bit d flip-flop with ck enable, reset logic symbol timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 pulse width low (ck) t pwl 0.78 1.27 pulse width high (ck) t pwh 0.72 1.14 pulse width low (e) t pwl 0.83 1.30 pulse width high (e) t pwh 0.69 1.11 pulse width low (rn) t pwl 0.61 0.99 input setup time (d0 to ck) t su 0.15 0.33 input hold time (d0 to ck) t hd 0.37 0.58 input setup time (d0 to e) t su 0.15 0.36 input hold time (d0 to e) t hd 0.37 0.58 input setup time (d1 to ck) t su 0.15 0.33 input hold time (d1 to ck) t hd 0.39 0.61 input setup time (d1 to e) t su 0.15 0.36 input hold time (d1 to e) t hd 0.37 0.58 input setup time (d2 to ck) t su 0.15 0.33 input hold time (d2 to ck) t hd 0.39 0.61 input setup time (d2 to e) t su 0.15 0.36 input hold time (d2 to e) t hd 0.37 0.58 input setup time (d3 to ck) t su 0.15 0.33 input hold time (d3 to ck) t hd 0.37 0.58 input setup time (d3 to e) t su 0.15 0.36 input hold time (d3 to e) t hd 0.37 0.58 recovery time (rn to ck) t rc 0.15 0.33 input hold time (rn to ck) t hd 0.75 1.07 recovery time (rn to e) t rc 0.15 0.33 input hold time (rn to e) t hd 0.69 1.07 d0 d1 d2 d3 q0 q1 q2 q3 qn0 qn1 qn2 qn3 rn e ck truth table cell data dn e ck rn qn (n+1) qnn (n+1) 01 1 0 1 11 1 1 0 x0x1qn (n) qnn (n) xxx0 0 1 x x 1 qn (n) qnn (n) input load (sl) gate count kg80 dn e ck rn 29.0 0.9 0.8 0.6 7.0 KGM80 dn e ck rn 29.0 1.0 0.9 0.7 8.3
kg80/KGM80 3-328 sec asic fg2x4 4-bit d flip-flop with ck enable, reset switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fg2x4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 0.87 0.78 + 0.045*sl 0.79 + 0.042*sl 0.80 + 0.041*sl t phl 0.99 0.93 + 0.031*sl 0.94 + 0.026*sl 0.96 + 0.023*sl t r 0.28 0.11 + 0.086*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.09 + 0.042*sl 0.10 + 0.040*sl 0.09 + 0.041*sl e to q0 t plh 0.86 0.77 + 0.045*sl 0.77 + 0.042*sl 0.78 + 0.042*sl t phl 0.98 0.91 + 0.032*sl 0.93 + 0.026*sl 0.94 + 0.024*sl t r 0.28 0.11 + 0.087*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.09 + 0.042*sl 0.10 + 0.039*sl 0.09 + 0.041*sl rn to q0 t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.31 + 0.024*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.039*sl 0.10 + 0.040*sl ck to q1 t plh 0.88 0.79 + 0.044*sl 0.79 + 0.042*sl 0.80 + 0.042*sl t phl 1.00 0.93 + 0.031*sl 0.95 + 0.026*sl 0.96 + 0.024*sl t r 0.29 0.12 + 0.086*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.09 + 0.042*sl 0.10 + 0.040*sl 0.09 + 0.041*sl e to q1 t plh 0.86 0.77 + 0.044*sl 0.78 + 0.042*sl 0.78 + 0.042*sl t phl 0.98 0.92 + 0.031*sl 0.93 + 0.026*sl 0.95 + 0.024*sl t r 0.29 0.12 + 0.086*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.10 + 0.041*sl 0.10 + 0.040*sl 0.09 + 0.041*sl rn to q1 t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.31 + 0.024*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.039*sl 0.10 + 0.040*sl ck to q2 t plh 0.88 0.79 + 0.044*sl 0.79 + 0.042*sl 0.80 + 0.042*sl t phl 1.00 0.93 + 0.031*sl 0.95 + 0.026*sl 0.96 + 0.024*sl t r 0.29 0.11 + 0.087*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.09 + 0.042*sl 0.10 + 0.039*sl 0.09 + 0.041*sl e to q2 t plh 0.86 0.77 + 0.044*sl 0.78 + 0.042*sl 0.78 + 0.042*sl t phl 0.98 0.92 + 0.031*sl 0.93 + 0.026*sl 0.95 + 0.024*sl t r 0.29 0.12 + 0.086*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.10 + 0.041*sl 0.10 + 0.039*sl 0.09 + 0.041*sl rn to q2 t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.31 + 0.024*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.039*sl 0.10 + 0.040*sl ck to q3 t plh 0.87 0.78 + 0.045*sl 0.79 + 0.042*sl 0.80 + 0.041*sl t phl 0.99 0.93 + 0.031*sl 0.94 + 0.026*sl 0.96 + 0.023*sl t r 0.28 0.11 + 0.086*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.09 + 0.042*sl 0.10 + 0.040*sl 0.09 + 0.041*sl e to q3 t plh 0.86 0.77 + 0.045*sl 0.77 + 0.042*sl 0.78 + 0.042*sl t phl 0.98 0.91 + 0.032*sl 0.93 + 0.026*sl 0.94 + 0.024*sl t r 0.28 0.11 + 0.087*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.09 + 0.042*sl 0.10 + 0.039*sl 0.09 + 0.041*sl rn to q3 t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.31 + 0.024*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.039*sl 0.10 + 0.040*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-329 kg80/KGM80 fg2x4 4-bit d flip-flop with ck enable, reset switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fg2x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to qn0 t plh 1.13 1.05 + 0.040*sl 1.05 + 0.041*sl 1.04 + 0.042*sl t phl 0.95 0.89 + 0.030*sl 0.90 + 0.025*sl 0.91 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.09 + 0.039*sl 0.08 + 0.040*sl 0.07 + 0.042*sl e to qn0 t plh 1.11 1.03 + 0.040*sl 1.03 + 0.041*sl 1.02 + 0.042*sl t phl 0.93 0.87 + 0.029*sl 0.88 + 0.025*sl 0.89 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.08 + 0.091*sl t f 0.16 0.09 + 0.039*sl 0.08 + 0.040*sl 0.07 + 0.042*sl rn to qn0 t plh 0.47 0.40 + 0.040*sl 0.39 + 0.041*sl 0.39 + 0.042*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.08 + 0.091*sl ck to qn1 t plh 1.13 1.05 + 0.040*sl 1.05 + 0.041*sl 1.05 + 0.042*sl t phl 0.95 0.90 + 0.029*sl 0.91 + 0.025*sl 0.92 + 0.023*sl t r 0.27 0.09 + 0.087*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl e to qn1 t plh 1.12 1.04 + 0.040*sl 1.03 + 0.041*sl 1.03 + 0.041*sl t phl 0.94 0.88 + 0.029*sl 0.89 + 0.025*sl 0.90 + 0.023*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl rn to qn1 t plh 0.48 0.40 + 0.040*sl 0.40 + 0.041*sl 0.39 + 0.042*sl t r 0.27 0.09 + 0.087*sl 0.09 + 0.089*sl 0.08 + 0.091*sl ck to qn2 t plh 1.13 1.05 + 0.040*sl 1.05 + 0.041*sl 1.05 + 0.042*sl t phl 0.95 0.89 + 0.030*sl 0.91 + 0.025*sl 0.92 + 0.023*sl t r 0.27 0.09 + 0.087*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl e to qn2 t plh 1.12 1.04 + 0.040*sl 1.03 + 0.041*sl 1.03 + 0.041*sl t phl 0.94 0.88 + 0.030*sl 0.89 + 0.025*sl 0.90 + 0.023*sl t r 0.27 0.09 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl rn to qn2 t plh 0.48 0.40 + 0.040*sl 0.40 + 0.041*sl 0.39 + 0.042*sl t r 0.27 0.09 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl ck to qn3 t plh 1.13 1.05 + 0.040*sl 1.05 + 0.041*sl 1.04 + 0.042*sl t phl 0.95 0.89 + 0.030*sl 0.90 + 0.025*sl 0.91 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.09 + 0.039*sl 0.08 + 0.040*sl 0.07 + 0.042*sl e to qn3 t plh 1.11 1.03 + 0.040*sl 1.03 + 0.041*sl 1.02 + 0.042*sl t phl 0.93 0.87 + 0.029*sl 0.88 + 0.025*sl 0.89 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.08 + 0.091*sl t f 0.16 0.09 + 0.039*sl 0.08 + 0.040*sl 0.07 + 0.042*sl rn to qn3 t plh 0.47 0.40 + 0.040*sl 0.39 + 0.041*sl 0.39 + 0.042*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.08 + 0.091*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-330 sec asic fg2x4 4-bit d flip-flop with ck enable, reset switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fg2x4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q0 t plh 1.18 1.07 + 0.055*sl 1.08 + 0.051*sl 1.09 + 0.050*sl t phl 1.41 1.33 + 0.036*sl 1.36 + 0.027*sl 1.39 + 0.024*sl t r 0.37 0.16 + 0.105*sl 0.15 + 0.107*sl 0.13 + 0.108*sl t f 0.21 0.12 + 0.046*sl 0.13 + 0.041*sl 0.12 + 0.042*sl e to q0 t plh 1.17 1.06 + 0.055*sl 1.07 + 0.051*sl 1.08 + 0.050*sl t phl 1.40 1.32 + 0.036*sl 1.35 + 0.027*sl 1.39 + 0.024*sl t r 0.37 0.16 + 0.104*sl 0.15 + 0.107*sl 0.13 + 0.108*sl t f 0.21 0.12 + 0.046*sl 0.13 + 0.041*sl 0.12 + 0.042*sl rn to q0 t phl 0.44 0.36 + 0.037*sl 0.39 + 0.027*sl 0.43 + 0.024*sl t f 0.22 0.13 + 0.045*sl 0.14 + 0.041*sl 0.13 + 0.042*sl ck to q1 t plh 1.19 1.08 + 0.054*sl 1.09 + 0.051*sl 1.10 + 0.050*sl t phl 1.41 1.34 + 0.035*sl 1.36 + 0.027*sl 1.40 + 0.023*sl t r 0.37 0.17 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.108*sl t f 0.21 0.12 + 0.045*sl 0.13 + 0.041*sl 0.12 + 0.042*sl e to q1 t plh 1.18 1.07 + 0.055*sl 1.08 + 0.051*sl 1.09 + 0.050*sl t phl 1.40 1.33 + 0.035*sl 1.35 + 0.027*sl 1.39 + 0.024*sl t r 0.38 0.17 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.108*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.041*sl 0.12 + 0.042*sl rn to q1 t phl 0.44 0.37 + 0.037*sl 0.39 + 0.027*sl 0.43 + 0.024*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.041*sl 0.13 + 0.042*sl ck to q2 t plh 1.19 1.08 + 0.054*sl 1.09 + 0.051*sl 1.10 + 0.050*sl t phl 1.41 1.34 + 0.035*sl 1.36 + 0.027*sl 1.40 + 0.024*sl t r 0.37 0.16 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.108*sl t f 0.21 0.12 + 0.046*sl 0.13 + 0.041*sl 0.12 + 0.042*sl e to q2 t plh 1.18 1.07 + 0.054*sl 1.08 + 0.051*sl 1.09 + 0.050*sl t phl 1.40 1.33 + 0.035*sl 1.35 + 0.027*sl 1.39 + 0.024*sl t r 0.37 0.16 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.108*sl t f 0.21 0.12 + 0.045*sl 0.13 + 0.041*sl 0.12 + 0.042*sl rn to q2 t phl 0.44 0.37 + 0.036*sl 0.39 + 0.027*sl 0.43 + 0.024*sl t f 0.22 0.13 + 0.045*sl 0.14 + 0.041*sl 0.13 + 0.042*sl ck to q3 t plh 1.18 1.07 + 0.055*sl 1.08 + 0.051*sl 1.09 + 0.050*sl t phl 1.41 1.33 + 0.036*sl 1.36 + 0.027*sl 1.39 + 0.024*sl t r 0.37 0.16 + 0.105*sl 0.15 + 0.107*sl 0.13 + 0.108*sl t f 0.21 0.12 + 0.046*sl 0.13 + 0.041*sl 0.12 + 0.042*sl e to q3 t plh 1.17 1.06 + 0.055*sl 1.07 + 0.051*sl 1.08 + 0.050*sl t phl 1.40 1.32 + 0.036*sl 1.35 + 0.027*sl 1.39 + 0.024*sl t r 0.37 0.16 + 0.104*sl 0.15 + 0.107*sl 0.13 + 0.108*sl t f 0.21 0.12 + 0.046*sl 0.13 + 0.041*sl 0.12 + 0.042*sl rn to q3 t phl 0.44 0.36 + 0.037*sl 0.39 + 0.027*sl 0.43 + 0.024*sl t f 0.22 0.13 + 0.045*sl 0.14 + 0.041*sl 0.13 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-331 kg80/KGM80 fg2x4 4-bit d flip-flop with ck enable, reset switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fg2x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to qn0 t plh 1.60 1.50 + 0.049*sl 1.50 + 0.050*sl 1.50 + 0.050*sl t phl 1.30 1.24 + 0.032*sl 1.26 + 0.026*sl 1.28 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.042*sl 0.11 + 0.041*sl 0.10 + 0.042*sl e to qn0 t plh 1.59 1.49 + 0.049*sl 1.49 + 0.050*sl 1.49 + 0.050*sl t phl 1.29 1.23 + 0.032*sl 1.25 + 0.026*sl 1.27 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.042*sl 0.11 + 0.041*sl 0.10 + 0.043*sl rn to qn0 t plh 0.64 0.54 + 0.048*sl 0.54 + 0.050*sl 0.54 + 0.050*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl ck to qn1 t plh 1.61 1.51 + 0.049*sl 1.51 + 0.050*sl 1.51 + 0.050*sl t phl 1.32 1.25 + 0.033*sl 1.27 + 0.026*sl 1.29 + 0.023*sl t r 0.35 0.14 + 0.103*sl 0.13 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.041*sl 0.11 + 0.042*sl e to qn1 t plh 1.60 1.50 + 0.049*sl 1.50 + 0.050*sl 1.50 + 0.050*sl t phl 1.31 1.24 + 0.033*sl 1.26 + 0.026*sl 1.29 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.041*sl 0.11 + 0.042*sl rn to qn1 t plh 0.64 0.54 + 0.049*sl 0.54 + 0.050*sl 0.54 + 0.050*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.11 + 0.109*sl ck to qn2 t plh 1.61 1.51 + 0.049*sl 1.51 + 0.050*sl 1.51 + 0.050*sl t phl 1.31 1.25 + 0.033*sl 1.27 + 0.026*sl 1.29 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.041*sl 0.11 + 0.042*sl e to qn2 t plh 1.60 1.50 + 0.049*sl 1.50 + 0.050*sl 1.50 + 0.050*sl t phl 1.30 1.24 + 0.033*sl 1.26 + 0.026*sl 1.28 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.041*sl 0.11 + 0.042*sl rn to qn2 t plh 0.64 0.54 + 0.049*sl 0.54 + 0.050*sl 0.54 + 0.050*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl ck to qn3 t plh 1.60 1.50 + 0.049*sl 1.50 + 0.050*sl 1.50 + 0.050*sl t phl 1.30 1.24 + 0.032*sl 1.26 + 0.026*sl 1.28 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.042*sl 0.11 + 0.041*sl 0.10 + 0.042*sl e to qn3 t plh 1.59 1.49 + 0.049*sl 1.49 + 0.050*sl 1.49 + 0.050*sl t phl 1.29 1.23 + 0.032*sl 1.25 + 0.026*sl 1.27 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.042*sl 0.11 + 0.041*sl 0.10 + 0.043*sl rn to qn3 t plh 0.64 0.54 + 0.048*sl 0.54 + 0.050*sl 0.54 + 0.050*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-332 sec asic fj1/fj1d2 jk flip-flop with 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 fj1 fj1d2 fj1 fj1d2 jckk jckk 0.5 0.9 0.9 0.5 0.9 0.9 9.0 12.0 KGM80 fj1 fj1d2 fj1 fj1d2 jckk jckk 1.0 1.0 1.0 1.0 1.0 1.0 9.0 12.0 parameter symbol kg80 KGM80 fj1 fj1d2 fj1 fj1d2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 input setup time (j to ck) t su 0.42 0.42 0.77 0.77 input hold time (j to ck) t hd 0.15 0.15 0.33 0.33 input setup time (k to ck) t su 0.42 0.42 0.77 0.77 input hold time (k to ck) t hd 0.15 0.15 0.33 0.33 j ck k q qn j cl clb cl clb clb cl qn clb cl q k cl ck clb truth table j ck k q (n+1) qn (n+1) 0 101 1 010 0 0 q (n) qn (n) 1 1 qn (n) q (n) x x q (n) qn (n)
sec asic 3-333 kg80/KGM80 fj1/fj1d2 jk flip-flop with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fj1 kg80 fj1d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.73 0.65 + 0.041*sl 0.65 + 0.041*sl 0.64 + 0.041*sl t phl 0.66 0.59 + 0.035*sl 0.61 + 0.028*sl 0.63 + 0.024*sl t r 0.27 0.10 + 0.086*sl 0.10 + 0.088*sl 0.08 + 0.090*sl t f 0.20 0.12 + 0.043*sl 0.12 + 0.039*sl 0.12 + 0.040*sl ck to qn t plh 0.50 0.42 + 0.042*sl 0.42 + 0.042*sl 0.42 + 0.042*sl t phl 0.53 0.47 + 0.030*sl 0.48 + 0.025*sl 0.49 + 0.024*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.090*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.041*sl 0.08 + 0.042*sl *g 1 sl 2 *g 2 2 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.76 0.71 + 0.022*sl 0.72 + 0.020*sl 0.72 + 0.020*sl t phl 0.69 0.64 + 0.023*sl 0.66 + 0.017*sl 0.68 + 0.014*sl t r 0.18 0.10 + 0.041*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.17 0.12 + 0.024*sl 0.13 + 0.020*sl 0.14 + 0.020*sl ck to qn t plh 0.48 0.44 + 0.023*sl 0.44 + 0.021*sl 0.44 + 0.021*sl t phl 0.53 0.48 + 0.021*sl 0.50 + 0.015*sl 0.51 + 0.013*sl t r 0.17 0.09 + 0.039*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.09 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-334 sec asic fj1/fj1d2 jk flip-flop with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fj1 KGM80 fj1d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.02 0.92 + 0.050*sl 0.92 + 0.050*sl 0.92 + 0.050*sl t phl 0.93 0.85 + 0.040*sl 0.88 + 0.029*sl 0.93 + 0.024*sl t r 0.35 0.15 + 0.104*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.24 0.15 + 0.047*sl 0.17 + 0.041*sl 0.16 + 0.041*sl ck to qn t plh 0.70 0.59 + 0.051*sl 0.60 + 0.050*sl 0.60 + 0.050*sl t phl 0.74 0.67 + 0.034*sl 0.69 + 0.026*sl 0.72 + 0.024*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.042*sl 0.11 + 0.042*sl *g 1 sl 3 *g 2 3 sl 11 *g 3 11 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.06 1.01 + 0.027*sl 1.01 + 0.024*sl 1.01 + 0.025*sl t phl 0.98 0.92 + 0.027*sl 0.94 + 0.019*sl 0.99 + 0.014*sl t r 0.23 0.13 + 0.052*sl 0.13 + 0.052*sl 0.11 + 0.053*sl t f 0.21 0.15 + 0.029*sl 0.17 + 0.022*sl 0.19 + 0.020*sl ck to qn t plh 0.67 0.61 + 0.028*sl 0.62 + 0.025*sl 0.62 + 0.025*sl t phl 0.74 0.70 + 0.023*sl 0.72 + 0.016*sl 0.75 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-335 kg80/KGM80 fj1s/fj1sd2 jk flip-flop with scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 fj1s fj1sd2 fj1s fj1sd 2 j ck k ti te j ck k ti te 0.9 0.9 0.8 0.9 1.6 0.9 0.9 0.8 0.9 1.6 11.0 12.0 KGM80 fj1s fj1sd2 fj1s fj1sd 2 j ck k ti te j ck k ti te 1.0 1.0 1.0 1.0 2.0 1.0 1.0 1.0 1.0 2.0 11.0 12.0 q qn j ti te ck k j clb cl clb cl clb cl q clb qn k ti te cl cl ck clb truth table j ck k ti te q (n+1) qn (n+1) 01x001 10x010 0 0 x 0 q (n) qn (n) 1 1 x 0 qn (n) q (n) x x x x q (n) qn (n) x x0101 x x1110
kg80/KGM80 3-336 sec asic fj1s/fj1sd2 jk flip-flop with scan, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fj1s kg80 fj1sd2 parameter symbol kg80 KGM80 fj1s fj1sd2 fj1s fj1sd2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 input setup time (j to ck) t su 0.64 0.64 1.14 1.14 input hold time (j to ck) t hd 0.15 0.15 0.33 0.33 input setup time (k to ck) t su 0.64 0.64 1.14 1.14 input hold time (k to ck) t hd 0.15 0.15 0.33 0.33 input setup time (ti to ck) t su 0.50 0.50 0.93 0.93 input hold time (ti to ck) t hd 0.15 0.15 0.33 0.33 input setup time (te to ck) t su 0.47 0.50 0.86 0.86 input hold time (te to ck) t hd 0.15 0.15 0.33 0.33 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.58 0.50 + 0.043*sl 0.50 + 0.042*sl 0.50 + 0.042*sl t phl 0.62 0.55 + 0.036*sl 0.57 + 0.028*sl 0.59 + 0.025*sl t r 0.29 0.12 + 0.085*sl 0.11 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.13 + 0.043*sl 0.13 + 0.040*sl 0.13 + 0.040*sl ck to qn t plh 0.76 0.68 + 0.040*sl 0.67 + 0.041*sl 0.67 + 0.042*sl t phl 0.66 0.60 + 0.030*sl 0.61 + 0.025*sl 0.62 + 0.023*sl t r 0.26 0.09 + 0.085*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl *g 1 sl 2 *g 2 2 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.56 0.51 + 0.025*sl 0.51 + 0.021*sl 0.52 + 0.021*sl t phl 0.61 0.56 + 0.025*sl 0.57 + 0.018*sl 0.59 + 0.015*sl t r 0.19 0.10 + 0.041*sl 0.10 + 0.042*sl 0.09 + 0.044*sl t f 0.18 0.13 + 0.024*sl 0.14 + 0.021*sl 0.14 + 0.020*sl ck to qn t plh 0.79 0.75 + 0.020*sl 0.75 + 0.019*sl 0.74 + 0.020*sl t phl 0.69 0.65 + 0.019*sl 0.66 + 0.015*sl 0.68 + 0.013*sl t r 0.17 0.09 + 0.040*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.020*sl 0.10 + 0.019*sl 0.10 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-337 kg80/KGM80 fj1s/fj1sd2 jk flip-flop with scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fj1s KGM80 fj1sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.80 0.69 + 0.053*sl 0.70 + 0.050*sl 0.71 + 0.050*sl t phl 0.87 0.79 + 0.042*sl 0.82 + 0.030*sl 0.88 + 0.024*sl t r 0.37 0.16 + 0.104*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.25 0.16 + 0.048*sl 0.18 + 0.041*sl 0.18 + 0.041*sl ck to qn t plh 1.07 0.97 + 0.050*sl 0.97 + 0.050*sl 0.97 + 0.050*sl t phl 0.92 0.85 + 0.033*sl 0.87 + 0.026*sl 0.90 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.041*sl 0.10 + 0.042*sl *g 1 sl 3 *g 2 3 sl 11 *g 3 11 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.76 0.70 + 0.030*sl 0.71 + 0.026*sl 0.72 + 0.025*sl t phl 0.86 0.80 + 0.029*sl 0.83 + 0.019*sl 0.88 + 0.015*sl t r 0.24 0.13 + 0.051*sl 0.13 + 0.052*sl 0.12 + 0.053*sl t f 0.21 0.16 + 0.027*sl 0.17 + 0.023*sl 0.19 + 0.020*sl ck to qn t plh 1.12 1.07 + 0.025*sl 1.07 + 0.024*sl 1.06 + 0.025*sl t phl 0.97 0.93 + 0.021*sl 0.94 + 0.016*sl 0.97 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.12 + 0.052*sl 0.10 + 0.054*sl t f 0.17 0.11 + 0.025*sl 0.13 + 0.021*sl 0.13 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-338 sec asic fj2/fj2d2 jk flip-flop with reset, 1x/2x drive logic symbol cell datacell data schematic diagram input load (sl) gate count kg80 fj2 fj2d2 fj2 fj2d2 jckkrnjckkrn 0.5 0.9 0.9 1.6 0.5 0.9 0.9 1.6 10.0 11.0 KGM80 fj2 fj2d2 fj2 fj2d2 jckkrnjckkrn 1.0 1.0 1.0 1.9 1.0 1.0 1.0 1.9 10.0 11.0 j ck k q qn rn j k cl ck clb q clb cl cl clb cl clb clb cl rn qn truth table jckkrn q (n+1) qn (n+1) 01101 10110 0 0 1 q (n) qn (n) 1 1 1 qn (n) q (n) x x 1 q (n) qn (n) xxx001
sec asic 3-339 kg80/KGM80 fj2/fj2d2 jk flip-flop with reset, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fj2 kg80 fj2d2 parameter symbol kg80 KGM80 fj2 fj2d2 fj2 fj2d2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 0.99 input setup time (j to ck) t su 0.50 0.50 0.83 0.83 input hold time (j to ck) t hd 0.15 0.15 0.33 0.33 input setup time (k to ck) t su 0.50 0.50 0.83 0.83 input hold time (k to ck) t hd 0.15 0.15 0.33 0.33 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ck) t hd 0.15 0.15 0.41 0.41 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.86 0.77 + 0.045*sl 0.78 + 0.042*sl 0.78 + 0.041*sl t phl 0.69 0.62 + 0.035*sl 0.64 + 0.028*sl 0.66 + 0.025*sl t r 0.31 0.14 + 0.086*sl 0.14 + 0.087*sl 0.12 + 0.089*sl t f 0.21 0.12 + 0.042*sl 0.13 + 0.040*sl 0.13 + 0.040*sl rn to q t phl 0.42 0.34 + 0.038*sl 0.37 + 0.027*sl 0.39 + 0.023*sl t f 0.22 0.15 + 0.039*sl 0.15 + 0.036*sl 0.14 + 0.038*sl ck to qn t plh 0.51 0.43 + 0.042*sl 0.43 + 0.042*sl 0.43 + 0.042*sl t phl 0.57 0.51 + 0.031*sl 0.52 + 0.025*sl 0.53 + 0.024*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl rn to qn t plh 0.60 0.52 + 0.042*sl 0.52 + 0.041*sl 0.52 + 0.042*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.08 + 0.090*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.90 0.85 + 0.026*sl 0.86 + 0.022*sl 0.86 + 0.021*sl t phl 0.71 0.66 + 0.023*sl 0.68 + 0.017*sl 0.70 + 0.014*sl t r 0.22 0.13 + 0.042*sl 0.13 + 0.043*sl 0.13 + 0.043*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.020*sl 0.14 + 0.020*sl rn to q t phl 0.40 0.35 + 0.026*sl 0.37 + 0.018*sl 0.40 + 0.014*sl t f 0.19 0.15 + 0.023*sl 0.16 + 0.019*sl 0.17 + 0.018*sl ck to qn t plh 0.49 0.45 + 0.023*sl 0.45 + 0.021*sl 0.45 + 0.021*sl t phl 0.57 0.53 + 0.021*sl 0.54 + 0.016*sl 0.56 + 0.013*sl t r 0.17 0.09 + 0.040*sl 0.08 + 0.043*sl 0.07 + 0.045*sl t f 0.14 0.10 + 0.021*sl 0.11 + 0.020*sl 0.10 + 0.020*sl rn to qn t plh 0.58 0.54 + 0.023*sl 0.54 + 0.021*sl 0.55 + 0.020*sl t r 0.17 0.10 + 0.039*sl 0.09 + 0.043*sl 0.08 + 0.044*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-340 sec asic fj2/fj2d2 jk flip-flop with reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fj2 KGM80 fj2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.21 1.09 + 0.057*sl 1.11 + 0.051*sl 1.12 + 0.050*sl t phl 0.97 0.89 + 0.041*sl 0.92 + 0.029*sl 0.98 + 0.024*sl t r 0.40 0.19 + 0.105*sl 0.19 + 0.105*sl 0.17 + 0.107*sl t f 0.25 0.16 + 0.047*sl 0.17 + 0.041*sl 0.18 + 0.041*sl rn to q t phl 0.56 0.47 + 0.044*sl 0.51 + 0.029*sl 0.57 + 0.024*sl t f 0.27 0.18 + 0.045*sl 0.20 + 0.038*sl 0.18 + 0.040*sl ck to qn t plh 0.71 0.61 + 0.051*sl 0.61 + 0.050*sl 0.62 + 0.050*sl t phl 0.80 0.73 + 0.035*sl 0.75 + 0.026*sl 0.77 + 0.024*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.12 + 0.042*sl 0.12 + 0.042*sl rn to qn t plh 0.84 0.74 + 0.050*sl 0.74 + 0.050*sl 0.74 + 0.050*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.108*sl 0.12 + 0.109*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.26 1.19 + 0.032*sl 1.21 + 0.027*sl 1.23 + 0.025*sl t phl 1.01 0.95 + 0.028*sl 0.98 + 0.019*sl 1.02 + 0.015*sl t r 0.27 0.16 + 0.056*sl 0.17 + 0.052*sl 0.17 + 0.052*sl t f 0.21 0.15 + 0.028*sl 0.17 + 0.022*sl 0.19 + 0.020*sl rn to q t phl 0.54 0.48 + 0.030*sl 0.51 + 0.020*sl 0.57 + 0.014*sl t f 0.23 0.17 + 0.029*sl 0.20 + 0.021*sl 0.22 + 0.019*sl ck to qn t plh 0.68 0.62 + 0.029*sl 0.63 + 0.025*sl 0.64 + 0.025*sl t phl 0.80 0.76 + 0.023*sl 0.77 + 0.017*sl 0.81 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.024*sl 0.13 + 0.021*sl 0.14 + 0.021*sl rn to qn t plh 0.82 0.76 + 0.028*sl 0.77 + 0.025*sl 0.77 + 0.025*sl t r 0.22 0.13 + 0.049*sl 0.12 + 0.052*sl 0.10 + 0.054*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-341 kg80/KGM80 fj2s/fj2sd2 jk flip-flop with reset, scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 fj2s fj2sd2 fj2s fj2s d2 j ck k ti te rn j ck k ti te rn 0.9 0.9 0.8 0.8 1.6 1.9 0.9 0.9 0.8 0.8 1.6 1.8 12.0 13.0 KGM80 fj2s fj2sd2 fj2s fj2s d2 j ck k ti te rn j ck k ti te rn 1.0 1.0 1.0 0.9 2.0 2.2 1.0 1.0 1.0 0.9 2.0 2.1 12.0 13.0 q qn j ti te ck k rn j clb cl clb cl clb cl q clb qn k ti te cl cl ck clb rn rn rn rn truth table j ck k ti te rn q (n+1) qn (n+1) 01x0101 10x0110 0 0 x 0 1 q (n) qn (n) 1 1 x 0 1 qn (n) q (n) x x x 0 1 q (n) qn (n) xxxxx0 0 1 xx01101 xx11110
kg80/KGM80 3-342 sec asic fj2s/fj2sd2 jk flip-flop with reset, scan, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 fj2s fj2sd2 fj2s fj2sd2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width high (rn) t pwh 0.61 0.61 0.99 1.02 input setup time (j to ck) t su 0.64 0.64 1.14 1.14 input hold time (j to ck) t hd 0.15 0.15 0.33 0.33 input setup time (k to ck) t su 0.64 0.64 1.14 1.14 input hold time (k to ck) t hd 0.15 0.15 0.33 0.33 input setup time (ti to ck) t su 0.50 0.50 0.93 0.93 input hold time (ti to ck) t hd 0.15 0.15 0.33 0.33 input setup time (te to ck) t su 0.50 0.50 0.86 0.86 input hold time (te to ck) t hd 0.15 0.15 0.33 0.33 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ck) t hd 0.42 0.42 0.63 0.63
sec asic 3-343 kg80/KGM80 fj2s/fj2sd2 jk flip-flop with reset, scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fj2s kg80 fj2sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.68 0.58 + 0.047*sl 0.59 + 0.043*sl 0.60 + 0.041*sl t phl 0.63 0.56 + 0.038*sl 0.58 + 0.029*sl 0.61 + 0.025*sl t r 0.31 0.14 + 0.086*sl 0.14 + 0.087*sl 0.13 + 0.089*sl t f 0.22 0.13 + 0.043*sl 0.14 + 0.040*sl 0.14 + 0.040*sl rn to q t phl 0.43 0.34 + 0.041*sl 0.37 + 0.029*sl 0.41 + 0.024*sl t f 0.24 0.15 + 0.042*sl 0.17 + 0.037*sl 0.15 + 0.038*sl ck to qn t plh 0.77 0.69 + 0.040*sl 0.69 + 0.041*sl 0.69 + 0.042*sl t phl 0.75 0.69 + 0.030*sl 0.70 + 0.025*sl 0.72 + 0.023*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.039*sl 0.08 + 0.042*sl rn to qn t plh 0.57 0.49 + 0.040*sl 0.48 + 0.041*sl 0.48 + 0.042*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.08 + 0.091*sl *g 1 sl 2 *g 2 2 sl 7 *g 3 7 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.66 0.60 + 0.028*sl 0.61 + 0.023*sl 0.62 + 0.022*sl t phl 0.62 0.57 + 0.025*sl 0.58 + 0.018*sl 0.61 + 0.015*sl t r 0.22 0.14 + 0.042*sl 0.14 + 0.043*sl 0.13 + 0.043*sl t f 0.18 0.13 + 0.024*sl 0.14 + 0.021*sl 0.15 + 0.020*sl rn to q t phl 0.41 0.35 + 0.027*sl 0.37 + 0.019*sl 0.40 + 0.014*sl t f 0.20 0.15 + 0.025*sl 0.16 + 0.019*sl 0.18 + 0.018*sl ck to qn t plh 0.80 0.76 + 0.020*sl 0.76 + 0.019*sl 0.76 + 0.020*sl t phl 0.80 0.76 + 0.018*sl 0.77 + 0.015*sl 0.78 + 0.013*sl t r 0.17 0.09 + 0.040*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.15 0.11 + 0.021*sl 0.11 + 0.019*sl 0.11 + 0.020*sl rn to qn t plh 0.59 0.55 + 0.019*sl 0.55 + 0.019*sl 0.55 + 0.020*sl t r 0.17 0.09 + 0.040*sl 0.09 + 0.042*sl 0.07 + 0.044*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-344 sec asic fj2s/fj2sd2 jk flip-flop with reset, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fj2s KGM80 fj2sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.93 0.81 + 0.059*sl 0.83 + 0.052*sl 0.85 + 0.050*sl t phl 0.90 0.81 + 0.043*sl 0.84 + 0.030*sl 0.91 + 0.025*sl t r 0.41 0.19 + 0.106*sl 0.20 + 0.105*sl 0.17 + 0.107*sl t f 0.26 0.16 + 0.049*sl 0.18 + 0.041*sl 0.19 + 0.041*sl rn to q t phl 0.57 0.47 + 0.046*sl 0.52 + 0.031*sl 0.59 + 0.024*sl t f 0.28 0.18 + 0.050*sl 0.21 + 0.039*sl 0.20 + 0.040*sl ck to qn t plh 1.10 1.00 + 0.049*sl 1.00 + 0.050*sl 1.00 + 0.050*sl t phl 1.05 0.99 + 0.033*sl 1.01 + 0.026*sl 1.03 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.041*sl 0.12 + 0.041*sl 0.11 + 0.042*sl rn to qn t plh 0.77 0.67 + 0.049*sl 0.67 + 0.049*sl 0.67 + 0.050*sl t r 0.35 0.14 + 0.103*sl 0.13 + 0.108*sl 0.12 + 0.109*sl *g 1 sl 3 *g 2 3 sl 11 *g 3 11 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.90 0.83 + 0.034*sl 0.85 + 0.029*sl 0.87 + 0.026*sl t phl 0.88 0.82 + 0.030*sl 0.85 + 0.020*sl 0.90 + 0.015*sl t r 0.28 0.16 + 0.056*sl 0.17 + 0.053*sl 0.17 + 0.053*sl t f 0.22 0.16 + 0.029*sl 0.18 + 0.023*sl 0.20 + 0.021*sl rn to q t phl 0.55 0.48 + 0.031*sl 0.51 + 0.021*sl 0.58 + 0.015*sl t f 0.24 0.18 + 0.030*sl 0.20 + 0.022*sl 0.23 + 0.019*sl ck to qn t plh 1.14 1.09 + 0.025*sl 1.09 + 0.024*sl 1.08 + 0.025*sl t phl 1.12 1.08 + 0.021*sl 1.09 + 0.016*sl 1.12 + 0.013*sl t r 0.22 0.12 + 0.051*sl 0.12 + 0.052*sl 0.10 + 0.054*sl t f 0.18 0.12 + 0.025*sl 0.14 + 0.021*sl 0.14 + 0.020*sl rn to qn t plh 0.81 0.77 + 0.024*sl 0.77 + 0.024*sl 0.76 + 0.025*sl t r 0.22 0.12 + 0.051*sl 0.12 + 0.052*sl 0.10 + 0.054*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-345 kg80/KGM80 fj4/fj4d2 jk flip-flop with reset, set, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 fj4 fj4d2 fj4 fj4d2 j ck k rn sn j ck k rn sn 0.9 0.9 0.8 1.8 1.7 0.9 0.9 0.7 1.7 1.7 11.0 12.0 KGM80 fj4 fj4d2 fj4 fj4d2 j ck k rn sn j ck k rn sn 1.0 1.0 1.0 2.2 2.2 1.0 1.0 1.0 2.2 2.2 11.0 12.0 j ck k q qn rn sn j cl clb k q qn cl clb clb cl clb cl rn sn cl ck clb truth table j ck k rn sn q (n+1) qn (n+1) 0 11101 1 01110 0 0 1 1 q (n) qn (n) 1 1 1 1 qn (n) q (n) x x 1 1 q (n) qn (n) xxx0101 xxx1010 xxx0000
kg80/KGM80 3-346 sec asic fj4/fj4d2 jk flip-flop with reset, set, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 fj4 fj4d2 fj4 fj4d2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 0.99 pulse width low (sn) t pwl 0.61 0;64 1.05 0.79 input setup time (j to ck) t su 0.47 0.47 0.83 0.83 input hold time (j to ck) t hd 0.15 0.15 0.33 0.33 input setup time (k to ck) t su 0.47 0.47 0.83 0.83 input hold time (k to ck) t hd 0.15 0.15 0.33 0.33 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ck) t hd 0.15 0.15 0.41 0.41 recovery time (sn) t rc 0.15 0.15 0.33 0.33 input hold time (sn to ck) t hd 0.42 0.42 0.85 0.85
sec asic 3-347 kg80/KGM80 fj4/fj4d2 jk flip-flop with reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fj4 kg80 fj4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.87 0.78 + 0.045*sl 0.79 + 0.042*sl 0.79 + 0.041*sl t phl 0.76 0.68 + 0.035*sl 0.70 + 0.028*sl 0.73 + 0.025*sl t r 0.31 0.14 + 0.086*sl 0.13 + 0.087*sl 0.12 + 0.089*sl t f 0.21 0.13 + 0.041*sl 0.13 + 0.039*sl 0.13 + 0.040*sl rn to q t plh 0.39 0.29 + 0.048*sl 0.31 + 0.042*sl 0.31 + 0.041*sl t phl 0.41 0.34 + 0.038*sl 0.36 + 0.028*sl 0.39 + 0.024*sl t r 0.31 0.14 + 0.084*sl 0.13 + 0.086*sl 0.12 + 0.089*sl t f 0.23 0.14 + 0.043*sl 0.16 + 0.037*sl 0.14 + 0.039*sl sn to q t plh 0.64 0.55 + 0.045*sl 0.55 + 0.041*sl 0.56 + 0.041*sl t r 0.31 0.14 + 0.085*sl 0.13 + 0.086*sl 0.11 + 0.089*sl ck to qn t plh 0.58 0.49 + 0.044*sl 0.50 + 0.042*sl 0.50 + 0.042*sl t phl 0.58 0.52 + 0.031*sl 0.53 + 0.026*sl 0.54 + 0.024*sl t r 0.29 0.12 + 0.084*sl 0.11 + 0.089*sl 0.10 + 0.090*sl t f 0.18 0.10 + 0.041*sl 0.10 + 0.040*sl 0.09 + 0.041*sl rn to qn t plh 0.67 0.58 + 0.044*sl 0.59 + 0.041*sl 0.59 + 0.041*sl t r 0.29 0.12 + 0.085*sl 0.11 + 0.088*sl 0.10 + 0.090*sl sn to qn t plh 0.30 0.22 + 0.044*sl 0.22 + 0.041*sl 0.22 + 0.041*sl t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.30 + 0.024*sl t r 0.28 0.11 + 0.085*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.19 0.11 + 0.039*sl 0.11 + 0.040*sl 0.10 + 0.040*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.91 0.85 + 0.026*sl 0.86 + 0.022*sl 0.87 + 0.021*sl t phl 0.79 0.75 + 0.023*sl 0.76 + 0.017*sl 0.78 + 0.014*sl t r 0.21 0.13 + 0.042*sl 0.13 + 0.043*sl 0.13 + 0.043*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.020*sl 0.15 + 0.020*sl rn to q t plh 0.37 0.32 + 0.027*sl 0.33 + 0.023*sl 0.34 + 0.021*sl t phl 0.40 0.35 + 0.026*sl 0.36 + 0.019*sl 0.39 + 0.014*sl t r 0.21 0.13 + 0.043*sl 0.13 + 0.042*sl 0.12 + 0.043*sl t f 0.19 0.14 + 0.026*sl 0.16 + 0.019*sl 0.17 + 0.018*sl sn to q t plh 0.67 0.62 + 0.025*sl 0.63 + 0.022*sl 0.63 + 0.020*sl t r 0.21 0.13 + 0.043*sl 0.13 + 0.042*sl 0.13 + 0.043*sl ck to qn t plh 0.58 0.53 + 0.024*sl 0.54 + 0.022*sl 0.54 + 0.021*sl t phl 0.59 0.55 + 0.020*sl 0.56 + 0.015*sl 0.57 + 0.013*sl t r 0.21 0.13 + 0.042*sl 0.13 + 0.043*sl 0.12 + 0.044*sl t f 0.16 0.12 + 0.022*sl 0.12 + 0.020*sl 0.12 + 0.020*sl rn to qn t plh 0.67 0.63 + 0.024*sl 0.63 + 0.022*sl 0.64 + 0.021*sl t r 0.22 0.13 + 0.042*sl 0.13 + 0.042*sl 0.12 + 0.044*sl sn to qn t plh 0.30 0.25 + 0.023*sl 0.26 + 0.022*sl 0.26 + 0.021*sl t phl 0.34 0.30 + 0.020*sl 0.31 + 0.016*sl 0.33 + 0.013*sl t r 0.22 0.15 + 0.032*sl 0.13 + 0.042*sl 0.12 + 0.044*sl t f 0.17 0.13 + 0.021*sl 0.13 + 0.020*sl 0.13 + 0.020*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 7, *grou p 3 : 7 < sl < < = =
kg80/KGM80 3-348 sec asic fj4/fj4d2 jk flip-flop with reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fj4 KGM80 fj4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.23 1.11 + 0.057*sl 1.13 + 0.051*sl 1.14 + 0.050*sl t phl 1.08 0.99 + 0.041*sl 1.03 + 0.029*sl 1.07 + 0.025*sl t r 0.40 0.19 + 0.105*sl 0.19 + 0.105*sl 0.16 + 0.108*sl t f 0.25 0.16 + 0.046*sl 0.18 + 0.041*sl 0.17 + 0.041*sl rn to q t plh 0.53 0.41 + 0.058*sl 0.43 + 0.051*sl 0.44 + 0.050*sl t phl 0.55 0.46 + 0.044*sl 0.50 + 0.030*sl 0.57 + 0.024*sl t r 0.40 0.19 + 0.103*sl 0.18 + 0.105*sl 0.15 + 0.108*sl t f 0.27 0.17 + 0.048*sl 0.20 + 0.040*sl 0.19 + 0.040*sl sn to q t plh 0.86 0.74 + 0.056*sl 0.76 + 0.050*sl 0.77 + 0.050*sl t r 0.39 0.19 + 0.104*sl 0.18 + 0.105*sl 0.15 + 0.108*sl ck to qn t plh 0.81 0.70 + 0.054*sl 0.71 + 0.051*sl 0.72 + 0.050*sl t phl 0.82 0.75 + 0.036*sl 0.77 + 0.027*sl 0.80 + 0.024*sl t r 0.37 0.17 + 0.104*sl 0.16 + 0.107*sl 0.14 + 0.108*sl t f 0.21 0.13 + 0.043*sl 0.13 + 0.042*sl 0.13 + 0.042*sl rn to qn t plh 0.94 0.83 + 0.054*sl 0.84 + 0.050*sl 0.85 + 0.050*sl t r 0.38 0.17 + 0.103*sl 0.16 + 0.106*sl 0.14 + 0.108*sl sn to qn t plh 0.41 0.30 + 0.054*sl 0.32 + 0.050*sl 0.32 + 0.050*sl t phl 0.44 0.37 + 0.037*sl 0.40 + 0.027*sl 0.43 + 0.024*sl t r 0.37 0.16 + 0.104*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.22 0.14 + 0.043*sl 0.14 + 0.042*sl 0.14 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.28 1.21 + 0.032*sl 1.23 + 0.027*sl 1.25 + 0.025*sl t phl 1.13 1.08 + 0.027*sl 1.10 + 0.019*sl 1.14 + 0.015*sl t r 0.27 0.16 + 0.057*sl 0.17 + 0.052*sl 0.17 + 0.052*sl t f 0.22 0.16 + 0.028*sl 0.18 + 0.022*sl 0.20 + 0.020*sl rn to q t plh 0.49 0.43 + 0.034*sl 0.44 + 0.028*sl 0.47 + 0.025*sl t phl 0.54 0.48 + 0.031*sl 0.50 + 0.020*sl 0.57 + 0.015*sl t r 0.27 0.16 + 0.056*sl 0.17 + 0.052*sl 0.16 + 0.052*sl t f 0.23 0.17 + 0.030*sl 0.19 + 0.022*sl 0.22 + 0.019*sl sn to q t plh 0.90 0.84 + 0.032*sl 0.85 + 0.027*sl 0.87 + 0.025*sl t r 0.27 0.16 + 0.056*sl 0.17 + 0.052*sl 0.16 + 0.052*sl ck to qn t plh 0.81 0.75 + 0.030*sl 0.76 + 0.026*sl 0.78 + 0.025*sl t phl 0.84 0.79 + 0.023*sl 0.81 + 0.016*sl 0.84 + 0.013*sl t r 0.28 0.18 + 0.052*sl 0.18 + 0.052*sl 0.17 + 0.053*sl t f 0.19 0.15 + 0.024*sl 0.15 + 0.021*sl 0.16 + 0.021*sl rn to qn t plh 0.95 0.89 + 0.031*sl 0.90 + 0.026*sl 0.91 + 0.025*sl t r 0.29 0.18 + 0.052*sl 0.19 + 0.052*sl 0.17 + 0.053*sl sn to qn t plh 0.41 0.35 + 0.030*sl 0.36 + 0.026*sl 0.37 + 0.025*sl t phl 0.46 0.41 + 0.023*sl 0.43 + 0.017*sl 0.46 + 0.013*sl t r 0.28 0.18 + 0.051*sl 0.18 + 0.052*sl 0.16 + 0.053*sl t f 0.20 0.15 + 0.024*sl 0.16 + 0.021*sl 0.17 + 0.020*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 11, *grou p 3 : 11 < sl < < = =
sec asic 3-349 kg80/KGM80 fj4s/fj4sd2 jk flip-flop with reset, set, scan, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 fj4s fj4sd2 fj4s fj4s d2 j ck k ti te rn sn j ck k ti te rn sn 0.9 0.9 0.7 0.7 1.6 1.7 1.7 0.9 0.9 0.7 0.7 1.6 1.7 1.7 13.0 14.0 KGM80 fj4s fj4sd2 fj4s fj4s d2 j ck k ti te rn sn j ck k ti te rn sn 1.0 1.0 1.0 0.9 1.9 2.2 2.2 1.0 1.0 1.0 0.9 1.9 2.2 2.2 13.0 14.0 q qn j ti te ck k rn sn j cl clb k qn q cl clb clb cl clb cl cl ck clb te ti sn rn rn sn sn sn rn rn truth table j ck k ti te rn sn q (n+1) qn (n+1) 01x01101 10x01110 0 0 x 0 1 1 q (n) qn (n) 1 1 x 0 1 1 qn (n) q (n) x x x 0 1 1 q (n) qn (n) xxxxx01 0 1 xxxxx10 1 0 xxxxx00 0 0 x x0111 0 1 x x1111 1 0
kg80/KGM80 3-350 sec asic fj4s/fj4sd2 jk flip-flop with reset, set, scan, 1x/2x drive timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 fj4s fj4sd2 fj4s fj4sd2 pulse width low (ck) t pwl 0.61 0.61 1.02 1.02 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width high (rn) t pwh 0.61 0.61 1.02 1.02 pulse width high (sn) t pwh 0.64 0.64 1.05 1.05 input setup time (j to ck) t su 0.69 0.69 1.21 1.21 input hold time (j to ck) t hd 0.15 0.15 0.33 0.33 input setup time (k to ck) t su 0.69 0.69 1.21 1.21 input hold time (k to ck) t hd 0.15 0.15 0.33 0.33 input setup time (ti to ck) t su 0.58 0.58 1.05 1.05 input hold time (ti to ck) t hd 0.15 0.15 0.33 0.33 input setup time (te to ck) t su 0.50 0.50 0.93 1.05 input hold time (te to ck) t hd 0.15 0.15 0.33 0.33 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ck) t hd 0.42 0.42 0.85 0.85 recovery time (sn) t rc 0.15 0.15 0.33 0.33 input hold time (sn to ck) t hd 0.15 0.15 0.41 0.41
sec asic 3-351 kg80/KGM80 fj4s/fj4sd2 jk flip-flop with reset, set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fj4s kg80 fj4sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.69 0.59 + 0.048*sl 0.60 + 0.043*sl 0.62 + 0.042*sl t phl 0.67 0.59 + 0.038*sl 0.61 + 0.029*sl 0.64 + 0.025*sl t r 0.32 0.15 + 0.086*sl 0.15 + 0.087*sl 0.13 + 0.088*sl t f 0.22 0.14 + 0.043*sl 0.15 + 0.040*sl 0.15 + 0.040*sl rn to q t plh 0.41 0.31 + 0.047*sl 0.32 + 0.042*sl 0.33 + 0.041*sl t phl 0.43 0.35 + 0.040*sl 0.37 + 0.030*sl 0.41 + 0.025*sl t r 0.31 0.14 + 0.085*sl 0.14 + 0.086*sl 0.12 + 0.089*sl t f 0.24 0.15 + 0.044*sl 0.17 + 0.038*sl 0.16 + 0.038*sl sn to q t plh 0.78 0.69 + 0.046*sl 0.70 + 0.042*sl 0.70 + 0.041*sl t r 0.32 0.15 + 0.085*sl 0.14 + 0.086*sl 0.12 + 0.089*sl ck to qn t plh 0.87 0.79 + 0.042*sl 0.79 + 0.041*sl 0.79 + 0.041*sl t phl 0.77 0.71 + 0.030*sl 0.72 + 0.025*sl 0.73 + 0.023*sl t r 0.28 0.11 + 0.086*sl 0.11 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.10 + 0.038*sl 0.09 + 0.040*sl 0.08 + 0.041*sl rn to qn t plh 0.63 0.55 + 0.042*sl 0.55 + 0.041*sl 0.55 + 0.041*sl t r 0.28 0.11 + 0.084*sl 0.11 + 0.088*sl 0.09 + 0.090*sl sn to qn t plh 0.29 0.21 + 0.043*sl 0.21 + 0.041*sl 0.21 + 0.042*sl t phl 0.33 0.26 + 0.032*sl 0.28 + 0.026*sl 0.29 + 0.023*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.18 0.10 + 0.039*sl 0.10 + 0.040*sl 0.09 + 0.041*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.68 0.63 + 0.026*sl 0.64 + 0.023*sl 0.65 + 0.022*sl t phl 0.67 0.62 + 0.023*sl 0.63 + 0.018*sl 0.65 + 0.015*sl t r 0.25 0.16 + 0.043*sl 0.16 + 0.043*sl 0.16 + 0.043*sl t f 0.20 0.15 + 0.023*sl 0.16 + 0.021*sl 0.16 + 0.020*sl rn to q t plh 0.40 0.35 + 0.026*sl 0.35 + 0.023*sl 0.36 + 0.021*sl t phl 0.42 0.37 + 0.025*sl 0.39 + 0.018*sl 0.41 + 0.015*sl t r 0.24 0.16 + 0.042*sl 0.16 + 0.042*sl 0.15 + 0.043*sl t f 0.21 0.17 + 0.024*sl 0.18 + 0.020*sl 0.18 + 0.019*sl sn to q t plh 0.78 0.72 + 0.026*sl 0.73 + 0.023*sl 0.74 + 0.021*sl t r 0.24 0.16 + 0.043*sl 0.16 + 0.042*sl 0.16 + 0.043*sl ck to qn t plh 0.91 0.87 + 0.022*sl 0.87 + 0.020*sl 0.87 + 0.020*sl t phl 0.81 0.77 + 0.019*sl 0.78 + 0.015*sl 0.79 + 0.013*sl t r 0.19 0.11 + 0.042*sl 0.11 + 0.042*sl 0.10 + 0.043*sl t f 0.15 0.11 + 0.021*sl 0.11 + 0.019*sl 0.11 + 0.019*sl rn to qn t plh 0.67 0.63 + 0.023*sl 0.63 + 0.020*sl 0.63 + 0.020*sl t r 0.19 0.11 + 0.042*sl 0.11 + 0.042*sl 0.09 + 0.044*sl sn to qn t plh 0.28 0.23 + 0.024*sl 0.24 + 0.022*sl 0.24 + 0.021*sl t phl 0.32 0.28 + 0.021*sl 0.29 + 0.016*sl 0.31 + 0.013*sl t r 0.18 0.10 + 0.041*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.15 0.11 + 0.021*sl 0.11 + 0.020*sl 0.11 + 0.019*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 7, *grou p 3 : 7 < sl < < = =
kg80/KGM80 3-352 sec asic fj4s/fj4sd2 jk flip-flop with reset, set, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fj4s KGM80 fj4sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.95 0.83 + 0.059*sl 0.85 + 0.052*sl 0.88 + 0.050*sl t phl 0.95 0.86 + 0.043*sl 0.90 + 0.031*sl 0.96 + 0.025*sl t r 0.41 0.20 + 0.107*sl 0.20 + 0.105*sl 0.18 + 0.107*sl t f 0.27 0.17 + 0.047*sl 0.19 + 0.042*sl 0.20 + 0.041*sl rn to q t plh 0.54 0.43 + 0.058*sl 0.45 + 0.051*sl 0.46 + 0.050*sl t phl 0.57 0.48 + 0.046*sl 0.52 + 0.031*sl 0.59 + 0.025*sl t r 0.40 0.20 + 0.103*sl 0.19 + 0.105*sl 0.16 + 0.107*sl t f 0.28 0.19 + 0.049*sl 0.21 + 0.040*sl 0.22 + 0.040*sl sn to q t plh 1.09 0.97 + 0.059*sl 0.99 + 0.051*sl 1.01 + 0.050*sl t r 0.41 0.20 + 0.104*sl 0.20 + 0.105*sl 0.17 + 0.107*sl ck to qn t plh 1.24 1.14 + 0.052*sl 1.14 + 0.050*sl 1.14 + 0.050*sl t phl 1.08 1.01 + 0.034*sl 1.04 + 0.026*sl 1.06 + 0.023*sl t r 0.37 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.041*sl 0.12 + 0.042*sl rn to qn t plh 0.87 0.77 + 0.052*sl 0.77 + 0.050*sl 0.77 + 0.050*sl t r 0.37 0.16 + 0.103*sl 0.15 + 0.106*sl 0.13 + 0.109*sl sn to qn t plh 0.40 0.29 + 0.054*sl 0.30 + 0.050*sl 0.31 + 0.050*sl t phl 0.43 0.36 + 0.035*sl 0.38 + 0.026*sl 0.41 + 0.024*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.041*sl 0.12 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.94 0.88 + 0.033*sl 0.89 + 0.028*sl 0.91 + 0.026*sl t phl 0.95 0.90 + 0.027*sl 0.92 + 0.019*sl 0.97 + 0.015*sl t r 0.32 0.21 + 0.055*sl 0.21 + 0.053*sl 0.22 + 0.052*sl t f 0.24 0.19 + 0.027*sl 0.20 + 0.022*sl 0.22 + 0.021*sl rn to q t plh 0.53 0.47 + 0.032*sl 0.48 + 0.028*sl 0.51 + 0.025*sl t phl 0.57 0.52 + 0.028*sl 0.54 + 0.020*sl 0.60 + 0.015*sl t r 0.31 0.20 + 0.054*sl 0.21 + 0.052*sl 0.20 + 0.052*sl t f 0.26 0.20 + 0.029*sl 0.22 + 0.022*sl 0.25 + 0.019*sl sn to q t plh 1.08 1.02 + 0.032*sl 1.03 + 0.027*sl 1.06 + 0.025*sl t r 0.32 0.21 + 0.055*sl 0.22 + 0.051*sl 0.21 + 0.052*sl ck to qn t plh 1.30 1.24 + 0.029*sl 1.25 + 0.025*sl 1.26 + 0.025*sl t phl 1.15 1.10 + 0.023*sl 1.12 + 0.016*sl 1.15 + 0.013*sl t r 0.25 0.14 + 0.053*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.18 0.13 + 0.024*sl 0.14 + 0.021*sl 0.15 + 0.020*sl rn to qn t plh 0.93 0.87 + 0.028*sl 0.88 + 0.025*sl 0.88 + 0.025*sl t r 0.25 0.14 + 0.053*sl 0.14 + 0.052*sl 0.13 + 0.053*sl sn to qn t plh 0.38 0.32 + 0.032*sl 0.33 + 0.026*sl 0.34 + 0.025*sl t phl 0.43 0.38 + 0.025*sl 0.40 + 0.017*sl 0.44 + 0.013*sl t r 0.24 0.13 + 0.053*sl 0.13 + 0.052*sl 0.12 + 0.053*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.021*sl 0.15 + 0.020*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 11, *grou p 3 : 11 < sl < < = =
sec asic 3-353 kg80/KGM80 ft2/ft2d2 toggle flip-flop with reset, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 ft2 ft2d2 ft2 ft2d2 ck rn ck rn 0.9 1.7 0.9 1.7 7.0 8.0 KGM80 ft2 ft2d2 ft2 ft2d2 ck rn ck rn 1.0 2.2 1.0 2.1 7.0 8.0 parameter symbol kg80 KGM80 ft2 ft2d2 ft2 ft2d2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width high (rn) t pwh 0.61 0.61 0.99 0.99 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to ck) t hd 0.15 0.15 0.41 0.41 ck q qn rn ck cl clb qn cl clb cl clb cl cl clb q clb rn rn rn rn truth table ck rn q (n+1) qn (n+1) 1 qn (n) q (n) x001
kg80/KGM80 3-354 sec asic ft2/ft2d2 toggle flip-flop with reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ft2 kg80 ft2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.81 0.73 + 0.043*sl 0.73 + 0.041*sl 0.73 + 0.041*sl t phl 0.64 0.58 + 0.033*sl 0.59 + 0.026*sl 0.61 + 0.024*sl t r 0.29 0.12 + 0.085*sl 0.11 + 0.088*sl 0.10 + 0.089*sl t f 0.18 0.10 + 0.042*sl 0.10 + 0.040*sl 0.10 + 0.041*sl rn to q t phl 0.37 0.30 + 0.035*sl 0.32 + 0.027*sl 0.34 + 0.024*sl t f 0.20 0.12 + 0.040*sl 0.12 + 0.038*sl 0.11 + 0.040*sl ck to qn t plh 0.52 0.43 + 0.042*sl 0.43 + 0.042*sl 0.43 + 0.042*sl t phl 0.56 0.50 + 0.031*sl 0.52 + 0.026*sl 0.53 + 0.024*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.09 + 0.041*sl rn to qn t plh 0.59 0.51 + 0.042*sl 0.51 + 0.041*sl 0.51 + 0.042*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.85 0.80 + 0.024*sl 0.81 + 0.021*sl 0.82 + 0.020*sl t phl 0.67 0.63 + 0.021*sl 0.64 + 0.016*sl 0.66 + 0.014*sl t r 0.20 0.11 + 0.042*sl 0.11 + 0.042*sl 0.11 + 0.043*sl t f 0.15 0.11 + 0.024*sl 0.12 + 0.020*sl 0.12 + 0.020*sl rn to q t phl 0.36 0.31 + 0.023*sl 0.33 + 0.017*sl 0.35 + 0.014*sl t f 0.17 0.12 + 0.024*sl 0.13 + 0.019*sl 0.14 + 0.018*sl ck to qn t plh 0.49 0.45 + 0.023*sl 0.45 + 0.021*sl 0.45 + 0.021*sl t phl 0.56 0.52 + 0.021*sl 0.53 + 0.015*sl 0.55 + 0.013*sl t r 0.17 0.09 + 0.040*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.022*sl 0.11 + 0.020*sl 0.10 + 0.020*sl rn to qn t plh 0.58 0.53 + 0.023*sl 0.54 + 0.021*sl 0.54 + 0.021*sl t r 0.17 0.09 + 0.041*sl 0.08 + 0.043*sl 0.08 + 0.044*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-355 kg80/KGM80 ft2/ft2d2 toggle flip-flop with reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ft2 KGM80 ft2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.15 1.04 + 0.054*sl 1.05 + 0.050*sl 1.05 + 0.050*sl t phl 0.91 0.83 + 0.038*sl 0.86 + 0.028*sl 0.90 + 0.024*sl t r 0.38 0.17 + 0.104*sl 0.16 + 0.106*sl 0.14 + 0.108*sl t f 0.22 0.13 + 0.046*sl 0.14 + 0.042*sl 0.14 + 0.042*sl rn to q t phl 0.49 0.42 + 0.040*sl 0.45 + 0.028*sl 0.50 + 0.024*sl t f 0.24 0.14 + 0.046*sl 0.16 + 0.040*sl 0.15 + 0.041*sl ck to qn t plh 0.71 0.61 + 0.051*sl 0.61 + 0.050*sl 0.62 + 0.050*sl t phl 0.79 0.72 + 0.035*sl 0.74 + 0.026*sl 0.77 + 0.024*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.042*sl 0.12 + 0.042*sl 0.12 + 0.042*sl rn to qn t plh 0.83 0.72 + 0.050*sl 0.73 + 0.050*sl 0.73 + 0.050*sl t r 0.35 0.15 + 0.103*sl 0.14 + 0.108*sl 0.12 + 0.109*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.20 1.14 + 0.031*sl 1.16 + 0.026*sl 1.17 + 0.025*sl t phl 0.95 0.90 + 0.025*sl 0.92 + 0.017*sl 0.96 + 0.014*sl t r 0.25 0.15 + 0.054*sl 0.15 + 0.052*sl 0.15 + 0.053*sl t f 0.19 0.13 + 0.028*sl 0.15 + 0.022*sl 0.16 + 0.021*sl rn to q t phl 0.49 0.43 + 0.028*sl 0.46 + 0.018*sl 0.51 + 0.014*sl t f 0.20 0.15 + 0.027*sl 0.16 + 0.021*sl 0.18 + 0.019*sl ck to qn t plh 0.68 0.62 + 0.028*sl 0.63 + 0.025*sl 0.64 + 0.025*sl t phl 0.80 0.75 + 0.024*sl 0.77 + 0.017*sl 0.80 + 0.013*sl t r 0.22 0.12 + 0.051*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.021*sl 0.13 + 0.021*sl rn to qn t plh 0.81 0.75 + 0.029*sl 0.76 + 0.025*sl 0.76 + 0.025*sl t r 0.22 0.12 + 0.050*sl 0.12 + 0.052*sl 0.10 + 0.054*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-356 sec asic ft3/ft3d2 toggle flip-flop with set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 ft3 ft3d2 ft3 ft3d2 ck sn ck sn 0.9 1.3 0.9 1.3 7.0 8.0 KGM80 ft3 ft3d2 ft3 ft3d2 ck sn ck sn 1.0 1.9 1.0 1.9 7.0 8.0 parameter symbol kg80 KGM80 ft3 ft3d2 ft3 ft3d2 pulse width low (ck) t pwl 0.61 0.61 0.99 0.99 pulse width high (ck) t pwh 0.61 0.61 0.99 0.99 pulse width high (sn) t pwh 0.61 0.61 0.99 0.99 recovery time (sn) t rc 0.15 0.15 0.33 0.33 input hold time (sn to ck) t hd 0.41 0.41 0.85 0.85 ck q qn sn ck cl clb cl clb qn cl clb cl cl clb q clb sn sn sn sn truth table ck sn q (n+1) qn (n+1) 1 qn (n) q (n) x010
sec asic 3-357 kg80/KGM80 ft3/ft3d2 toggle flip-flop with set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ft3 kg80 ft3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.74 0.66 + 0.040*sl 0.66 + 0.041*sl 0.66 + 0.042*sl t phl 0.68 0.62 + 0.031*sl 0.63 + 0.026*sl 0.65 + 0.024*sl t r 0.27 0.10 + 0.086*sl 0.10 + 0.089*sl 0.08 + 0.090*sl t f 0.19 0.10 + 0.041*sl 0.11 + 0.040*sl 0.10 + 0.041*sl sn to q t plh 0.48 0.40 + 0.040*sl 0.40 + 0.041*sl 0.39 + 0.042*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl ck to qn t plh 0.56 0.47 + 0.044*sl 0.48 + 0.042*sl 0.48 + 0.042*sl t phl 0.57 0.50 + 0.033*sl 0.52 + 0.026*sl 0.53 + 0.024*sl t r 0.28 0.11 + 0.086*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.18 0.10 + 0.041*sl 0.11 + 0.039*sl 0.09 + 0.041*sl sn to qn t phl 0.31 0.24 + 0.032*sl 0.26 + 0.026*sl 0.27 + 0.024*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.040*sl 0.09 + 0.041*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 0.77 0.73 + 0.020*sl 0.73 + 0.019*sl 0.73 + 0.020*sl t phl 0.72 0.69 + 0.019*sl 0.69 + 0.015*sl 0.71 + 0.013*sl t r 0.18 0.09 + 0.041*sl 0.09 + 0.042*sl 0.08 + 0.044*sl t f 0.16 0.11 + 0.023*sl 0.12 + 0.019*sl 0.12 + 0.020*sl sn to q t plh 0.51 0.47 + 0.020*sl 0.47 + 0.019*sl 0.46 + 0.020*sl t r 0.18 0.09 + 0.043*sl 0.09 + 0.042*sl 0.08 + 0.044*sl ck to qn t plh 0.55 0.50 + 0.025*sl 0.51 + 0.022*sl 0.51 + 0.021*sl t phl 0.56 0.52 + 0.022*sl 0.53 + 0.016*sl 0.55 + 0.014*sl t r 0.19 0.10 + 0.042*sl 0.10 + 0.043*sl 0.10 + 0.044*sl t f 0.15 0.11 + 0.022*sl 0.11 + 0.020*sl 0.12 + 0.020*sl sn to qn t phl 0.30 0.26 + 0.021*sl 0.27 + 0.016*sl 0.29 + 0.013*sl t f 0.15 0.10 + 0.022*sl 0.11 + 0.020*sl 0.11 + 0.019*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-358 sec asic ft3/ft3d2 toggle flip-flop with set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ft3 KGM80 ft3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.05 0.95 + 0.049*sl 0.95 + 0.049*sl 0.95 + 0.050*sl t phl 0.97 0.89 + 0.036*sl 0.92 + 0.027*sl 0.95 + 0.024*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.22 0.14 + 0.044*sl 0.14 + 0.041*sl 0.14 + 0.042*sl sn to q t plh 0.64 0.55 + 0.049*sl 0.54 + 0.050*sl 0.54 + 0.050*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.108*sl 0.12 + 0.109*sl ck to qn t plh 0.77 0.67 + 0.054*sl 0.68 + 0.051*sl 0.69 + 0.050*sl t phl 0.80 0.72 + 0.036*sl 0.75 + 0.027*sl 0.79 + 0.024*sl t r 0.36 0.16 + 0.104*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.21 0.13 + 0.043*sl 0.13 + 0.041*sl 0.12 + 0.042*sl sn to qn t phl 0.39 0.32 + 0.035*sl 0.35 + 0.027*sl 0.37 + 0.024*sl t f 0.20 0.12 + 0.043*sl 0.12 + 0.042*sl 0.12 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* ck to q t plh 1.09 1.04 + 0.026*sl 1.04 + 0.024*sl 1.04 + 0.025*sl t phl 1.03 0.98 + 0.023*sl 1.00 + 0.017*sl 1.03 + 0.014*sl t r 0.23 0.12 + 0.051*sl 0.12 + 0.052*sl 0.11 + 0.054*sl t f 0.19 0.13 + 0.027*sl 0.15 + 0.022*sl 0.16 + 0.021*sl sn to q t plh 0.68 0.63 + 0.025*sl 0.64 + 0.024*sl 0.63 + 0.025*sl t r 0.23 0.12 + 0.052*sl 0.12 + 0.052*sl 0.10 + 0.054*sl ck to qn t plh 0.76 0.69 + 0.032*sl 0.71 + 0.027*sl 0.72 + 0.025*sl t phl 0.80 0.75 + 0.025*sl 0.77 + 0.017*sl 0.81 + 0.014*sl t r 0.24 0.14 + 0.054*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.18 0.13 + 0.026*sl 0.14 + 0.021*sl 0.15 + 0.020*sl sn to qn t phl 0.40 0.35 + 0.023*sl 0.37 + 0.017*sl 0.40 + 0.013*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.022*sl 0.14 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-359 kg80/KGM80 latches cell list cell name function description ld1 d latch with active high ld1d2 d latch with active high, 2x drive ld1s d latch with active high, scan ld1sd2 d latch with active high, scan, 2x drive ld1q d latch with active high, q output only ld1qd2 d latch with active high, q output only, 2x drive ld1x4 4-bit d latch with active high ld1x4d2 4-bit d latch with active high, 2x drive yld1 fast d latch with active high yld1d2 fast d latch with active high, 2x drive ld1a d latch with active high, tri-state output ld1b d latch with active high, tri-state output, separate wr, wrn ld2 d latch with active high, reset ld2d2 d latch with active high, reset, 2x drive ld2q d latch with active high, reset, q output only ld2qd2 d latch with active high, reset, q output only, 2x drive yld2 fast d latch with active high, reset yld2d2 fast d latch with active high, reset, 2x drive ld3 d latch with active high, set ld3d2 d latch with active high, set, 2x drive ld4 d latch with active high, reset, set ld4d2 d latch with active high, reset, set, 2x drive ld5 d latch with active low ld5d2 d latch with active low, 2x drive ld5s d latch with active low, scan ld5sd2 d latch with active low, scan, 2x drive ld5x4 4-bit d latch with active low ld5x4d2 4-bit d latch with active low, 2x drive ld6 d latch with active low, reset ld6d2 d latch with active low, reset, 2x drive ld7 d latch with active low, set ld7d2 d latch with active low, set, 2x drive ld8 d latch with active low, reset, set ld8d2 d latch with active low, reset, set, 2x drive
kg80/KGM80 3-360 sec asic lds2 d latch with active high, synchronous clear lds6 d latch with active low, synchronous clear ls0 sr latch ls0d2 sr latch with 2x drive ls1 sr latch with separate inputs ls2 sr latch with common inputs cell name function description latches cell list (continued)
sec asic 3-361 kg80/KGM80 ld1/ld1d2 d latch with active high, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 ld1 ld1d2 ld1 ld1d2 dgdg 0.9 0.9 0.9 0.9 4.0 5.0 KGM80 ld1 ld1d2 ld1 ld1d2 dgdg 1.0 1.0 1.0 1.0 4.0 5.0 parameter symbol kg80 KGM80 ld1 ld1d2 ld1 ld1d2 pulse width high (g) t pwh 0.61 0.61 0.99 0.99 input setup time (d to g) t su 0.34 0.37 0.61 0.64 input hold time (d to g) t hd 0.15 0.15 0.33 0.33 d g q qn g g gb d gb g g gb qn q truth table d g q (n+1) qn (n+1) 0101 1110 x 0 q (n) qn (n)
kg80/KGM80 3-362 sec asic ld1/ld1d2 d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld1 kg80 ld1d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.53 0.45 + 0.040*sl 0.45 + 0.041*sl 0.45 + 0.042*sl t phl 0.59 0.53 + 0.030*sl 0.54 + 0.025*sl 0.55 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.041*sl 0.07 + 0.042*sl g to q t plh 0.61 0.53 + 0.040*sl 0.52 + 0.041*sl 0.52 + 0.042*sl t phl 0.55 0.49 + 0.029*sl 0.50 + 0.025*sl 0.51 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.041*sl 0.08 + 0.041*sl 0.07 + 0.042*sl d to qn t plh 0.51 0.43 + 0.042*sl 0.43 + 0.042*sl 0.43 + 0.042*sl t phl 0.40 0.33 + 0.031*sl 0.35 + 0.025*sl 0.36 + 0.023*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.18 0.09 + 0.042*sl 0.10 + 0.040*sl 0.09 + 0.041*sl g to qn t plh 0.47 0.39 + 0.042*sl 0.39 + 0.042*sl 0.39 + 0.042*sl t phl 0.47 0.41 + 0.030*sl 0.42 + 0.026*sl 0.44 + 0.023*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.090*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.08 + 0.042*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.56 0.52 + 0.019*sl 0.52 + 0.019*sl 0.51 + 0.021*sl t phl 0.63 0.59 + 0.018*sl 0.60 + 0.015*sl 0.61 + 0.013*sl t r 0.17 0.09 + 0.040*sl 0.08 + 0.043*sl 0.07 + 0.045*sl t f 0.13 0.09 + 0.021*sl 0.10 + 0.020*sl 0.09 + 0.020*sl g to q t plh 0.64 0.60 + 0.019*sl 0.60 + 0.019*sl 0.59 + 0.020*sl t phl 0.59 0.55 + 0.018*sl 0.56 + 0.015*sl 0.57 + 0.013*sl t r 0.17 0.08 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.022*sl 0.09 + 0.020*sl 0.10 + 0.020*sl d to qn t plh 0.49 0.45 + 0.023*sl 0.45 + 0.021*sl 0.45 + 0.021*sl t phl 0.39 0.35 + 0.021*sl 0.36 + 0.015*sl 0.38 + 0.014*sl t r 0.17 0.08 + 0.043*sl 0.09 + 0.042*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.023*sl 0.10 + 0.021*sl 0.11 + 0.019*sl g to qn t plh 0.45 0.41 + 0.023*sl 0.41 + 0.021*sl 0.41 + 0.021*sl t phl 0.47 0.43 + 0.021*sl 0.44 + 0.015*sl 0.46 + 0.013*sl t r 0.17 0.08 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.09 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-363 kg80/KGM80 ld1/ld1d2 d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld1 KGM80 ld1d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.73 0.64 + 0.049*sl 0.63 + 0.050*sl 0.63 + 0.050*sl t phl 0.82 0.76 + 0.032*sl 0.78 + 0.026*sl 0.80 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.044*sl 0.11 + 0.042*sl 0.10 + 0.042*sl g to q t plh 0.86 0.76 + 0.049*sl 0.76 + 0.050*sl 0.76 + 0.050*sl t phl 0.79 0.72 + 0.033*sl 0.74 + 0.025*sl 0.76 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.044*sl 0.11 + 0.041*sl 0.10 + 0.043*sl d to qn t plh 0.70 0.60 + 0.051*sl 0.60 + 0.050*sl 0.61 + 0.050*sl t phl 0.54 0.47 + 0.034*sl 0.50 + 0.026*sl 0.53 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.045*sl 0.12 + 0.041*sl 0.11 + 0.042*sl g to qn t plh 0.67 0.56 + 0.051*sl 0.57 + 0.050*sl 0.57 + 0.050*sl t phl 0.66 0.59 + 0.034*sl 0.62 + 0.026*sl 0.65 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.044*sl 0.12 + 0.042*sl 0.11 + 0.042*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.78 0.73 + 0.025*sl 0.73 + 0.024*sl 0.73 + 0.025*sl t phl 0.88 0.84 + 0.021*sl 0.85 + 0.016*sl 0.88 + 0.013*sl t r 0.21 0.11 + 0.050*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.020*sl g to q t plh 0.90 0.85 + 0.024*sl 0.86 + 0.024*sl 0.85 + 0.025*sl t phl 0.84 0.80 + 0.021*sl 0.82 + 0.016*sl 0.85 + 0.013*sl t r 0.21 0.11 + 0.051*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.021*sl d to qn t plh 0.68 0.62 + 0.028*sl 0.63 + 0.025*sl 0.63 + 0.025*sl t phl 0.55 0.50 + 0.023*sl 0.52 + 0.016*sl 0.55 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.16 0.12 + 0.024*sl 0.12 + 0.022*sl 0.13 + 0.021*sl g to qn t plh 0.64 0.58 + 0.028*sl 0.59 + 0.025*sl 0.59 + 0.025*sl t phl 0.67 0.62 + 0.023*sl 0.64 + 0.016*sl 0.67 + 0.013*sl t r 0.22 0.11 + 0.051*sl 0.11 + 0.053*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.022*sl 0.13 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-364 sec asic ld1s/ld1sd2 d latch with active high, scan, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 ld1s ld1sd2 ld1s ld1sd2 d g si sg d g si sg 0.9 1.7 0.9 1.8 0.9 1.7 0.9 1.8 7.0 8.0 KGM80 ld1s ld1sd2 ld1s ld1sd2 d g si sg d g si sg 1.0 1.0 2.0 2.1 1.0 1.0 2.0 2.1 7.0 8.0 parameter symbol kg80 KGM80 ld1s ld1sd2 ld1s ld1sd2 pulse width high (g) t pwh 0.61 0.61 0.99 0.99 pulse width high (sg) t pwh 0.61 0.61 0.99 0.99 input setup time (d to g) t su 0.37 0.42 0.74 0.80 input hold time (d to g) t hd 0.15 0.15 0.33 0.33 input setup time (si to sg) t su 0.37 0.39 0.68 0.74 input hold time (si to sg) t hd 0.15 0.15 0.33 0.33 q qn d g si sg g qn sg d si q truth table d g si sg q (n+1) qn (n+1) x0x0q (n)qn (n) xx1110 x00101 11xx10 01x001 010101
sec asic 3-365 kg80/KGM80 ld1s/ld1sd2 d latch with active high, scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld1s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.63 0.55 + 0.040*sl 0.54 + 0.041*sl 0.54 + 0.042*sl t phl 0.67 0.61 + 0.029*sl 0.62 + 0.025*sl 0.63 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl si to q t plh 0.70 0.62 + 0.040*sl 0.62 + 0.041*sl 0.61 + 0.042*sl t phl 0.71 0.65 + 0.030*sl 0.66 + 0.025*sl 0.68 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.039*sl 0.08 + 0.040*sl 0.07 + 0.042*sl g to q t plh 0.66 0.58 + 0.040*sl 0.57 + 0.041*sl 0.57 + 0.042*sl t phl 0.55 0.49 + 0.029*sl 0.50 + 0.025*sl 0.52 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl sg to q t plh 0.71 0.63 + 0.040*sl 0.63 + 0.041*sl 0.63 + 0.042*sl t phl 0.57 0.51 + 0.030*sl 0.52 + 0.025*sl 0.53 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.041*sl 0.08 + 0.040*sl 0.07 + 0.042*sl d to qn t plh 0.59 0.50 + 0.042*sl 0.51 + 0.041*sl 0.50 + 0.042*sl t phl 0.49 0.43 + 0.031*sl 0.44 + 0.026*sl 0.46 + 0.023*sl t r 0.27 0.10 + 0.086*sl 0.10 + 0.089*sl 0.08 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.10 + 0.040*sl 0.09 + 0.041*sl si to qn t plh 0.64 0.55 + 0.042*sl 0.55 + 0.041*sl 0.55 + 0.042*sl t phl 0.57 0.50 + 0.031*sl 0.52 + 0.026*sl 0.53 + 0.023*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.089*sl 0.08 + 0.090*sl t f 0.18 0.10 + 0.041*sl 0.10 + 0.039*sl 0.09 + 0.041*sl g to qn t plh 0.48 0.39 + 0.042*sl 0.39 + 0.042*sl 0.39 + 0.042*sl t phl 0.52 0.46 + 0.031*sl 0.47 + 0.026*sl 0.49 + 0.023*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.041*sl sg to qn t plh 0.49 0.41 + 0.042*sl 0.41 + 0.042*sl 0.41 + 0.042*sl t phl 0.58 0.52 + 0.031*sl 0.53 + 0.026*sl 0.55 + 0.023*sl t r 0.27 0.10 + 0.087*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.10 + 0.040*sl 0.10 + 0.040*sl 0.08 + 0.041*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-366 sec asic ld1s/ld1sd2 d latch with active high, scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld1sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.66 0.62 + 0.019*sl 0.62 + 0.019*sl 0.61 + 0.020*sl t phl 0.71 0.67 + 0.018*sl 0.68 + 0.015*sl 0.69 + 0.013*sl t r 0.17 0.09 + 0.037*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.020*sl si to q t plh 0.73 0.69 + 0.019*sl 0.69 + 0.019*sl 0.69 + 0.020*sl t phl 0.76 0.72 + 0.018*sl 0.73 + 0.014*sl 0.74 + 0.013*sl t r 0.17 0.08 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.09 + 0.022*sl 0.10 + 0.019*sl 0.10 + 0.020*sl g to q t plh 0.69 0.65 + 0.019*sl 0.65 + 0.019*sl 0.64 + 0.020*sl t phl 0.59 0.55 + 0.018*sl 0.56 + 0.015*sl 0.58 + 0.013*sl t r 0.16 0.08 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.022*sl 0.10 + 0.020*sl 0.09 + 0.020*sl sg to q t plh 0.75 0.71 + 0.019*sl 0.71 + 0.019*sl 0.70 + 0.020*sl t phl 0.61 0.57 + 0.019*sl 0.58 + 0.015*sl 0.59 + 0.013*sl t r 0.17 0.09 + 0.038*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.022*sl 0.10 + 0.019*sl 0.09 + 0.020*sl d to qn t plh 0.58 0.53 + 0.023*sl 0.54 + 0.021*sl 0.53 + 0.021*sl t phl 0.49 0.45 + 0.020*sl 0.46 + 0.016*sl 0.48 + 0.013*sl t r 0.17 0.10 + 0.038*sl 0.09 + 0.043*sl 0.08 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.11 + 0.020*sl si to qn t plh 0.62 0.58 + 0.023*sl 0.58 + 0.021*sl 0.58 + 0.021*sl t phl 0.56 0.52 + 0.021*sl 0.53 + 0.015*sl 0.55 + 0.014*sl t r 0.18 0.10 + 0.038*sl 0.09 + 0.043*sl 0.08 + 0.044*sl t f 0.15 0.10 + 0.021*sl 0.11 + 0.020*sl 0.11 + 0.020*sl g to qn t plh 0.46 0.41 + 0.023*sl 0.42 + 0.021*sl 0.42 + 0.021*sl t phl 0.52 0.48 + 0.021*sl 0.49 + 0.015*sl 0.51 + 0.013*sl t r 0.17 0.09 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl sg to qn t plh 0.48 0.43 + 0.023*sl 0.44 + 0.021*sl 0.44 + 0.021*sl t phl 0.58 0.54 + 0.020*sl 0.55 + 0.015*sl 0.57 + 0.013*sl t r 0.17 0.09 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.11 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-367 kg80/KGM80 ld1s/ld1sd2 d latch with active high, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld1s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.87 0.77 + 0.049*sl 0.77 + 0.050*sl 0.77 + 0.050*sl t phl 0.96 0.90 + 0.033*sl 0.92 + 0.026*sl 0.94 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl si to q t plh 0.96 0.87 + 0.049*sl 0.86 + 0.050*sl 0.86 + 0.050*sl t phl 1.06 1.00 + 0.032*sl 1.02 + 0.026*sl 1.04 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.041*sl 0.10 + 0.042*sl g to q t plh 0.93 0.83 + 0.049*sl 0.83 + 0.050*sl 0.83 + 0.050*sl t phl 0.80 0.73 + 0.033*sl 0.75 + 0.026*sl 0.77 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl sg to q t plh 0.99 0.90 + 0.049*sl 0.89 + 0.050*sl 0.89 + 0.050*sl t phl 0.81 0.74 + 0.032*sl 0.76 + 0.026*sl 0.79 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl d to qn t plh 0.84 0.74 + 0.051*sl 0.75 + 0.050*sl 0.75 + 0.050*sl t phl 0.68 0.61 + 0.034*sl 0.63 + 0.026*sl 0.66 + 0.023*sl t r 0.35 0.15 + 0.104*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.041*sl 0.12 + 0.042*sl si to qn t plh 0.94 0.84 + 0.051*sl 0.84 + 0.050*sl 0.85 + 0.050*sl t phl 0.77 0.70 + 0.035*sl 0.72 + 0.026*sl 0.76 + 0.023*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.041*sl 0.12 + 0.042*sl g to qn t plh 0.68 0.57 + 0.051*sl 0.58 + 0.050*sl 0.58 + 0.050*sl t phl 0.73 0.66 + 0.035*sl 0.69 + 0.026*sl 0.72 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.12 + 0.041*sl 0.12 + 0.042*sl sg to qn t plh 0.69 0.59 + 0.051*sl 0.59 + 0.050*sl 0.60 + 0.050*sl t phl 0.80 0.73 + 0.035*sl 0.75 + 0.026*sl 0.79 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.12 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-368 sec asic ld1s/ld1sd2 d latch with active high, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld1sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.92 0.87 + 0.025*sl 0.87 + 0.024*sl 0.86 + 0.025*sl t phl 1.03 0.99 + 0.021*sl 1.00 + 0.016*sl 1.03 + 0.013*sl t r 0.21 0.11 + 0.051*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.020*sl si to q t plh 1.01 0.97 + 0.024*sl 0.97 + 0.024*sl 0.96 + 0.025*sl t phl 1.13 1.09 + 0.021*sl 1.11 + 0.016*sl 1.14 + 0.013*sl t r 0.21 0.11 + 0.051*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.021*sl g to q t plh 0.98 0.93 + 0.024*sl 0.93 + 0.024*sl 0.92 + 0.025*sl t phl 0.86 0.81 + 0.021*sl 0.83 + 0.016*sl 0.86 + 0.013*sl t r 0.21 0.11 + 0.050*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.021*sl sg to q t plh 1.05 1.00 + 0.024*sl 1.00 + 0.024*sl 0.99 + 0.025*sl t phl 0.87 0.83 + 0.021*sl 0.84 + 0.016*sl 0.87 + 0.013*sl t r 0.21 0.11 + 0.050*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.021*sl d to qn t plh 0.83 0.77 + 0.029*sl 0.78 + 0.025*sl 0.78 + 0.025*sl t phl 0.68 0.64 + 0.024*sl 0.65 + 0.017*sl 0.69 + 0.013*sl t r 0.23 0.13 + 0.050*sl 0.12 + 0.052*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.024*sl 0.13 + 0.021*sl 0.14 + 0.020*sl si to qn t plh 0.93 0.87 + 0.029*sl 0.88 + 0.025*sl 0.89 + 0.025*sl t phl 0.78 0.73 + 0.024*sl 0.75 + 0.017*sl 0.78 + 0.013*sl t r 0.23 0.13 + 0.049*sl 0.12 + 0.052*sl 0.11 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.021*sl 0.14 + 0.020*sl g to qn t plh 0.65 0.60 + 0.028*sl 0.60 + 0.025*sl 0.61 + 0.025*sl t phl 0.74 0.69 + 0.024*sl 0.71 + 0.017*sl 0.75 + 0.013*sl t r 0.22 0.12 + 0.051*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.021*sl 0.14 + 0.020*sl sg to qn t plh 0.67 0.61 + 0.028*sl 0.62 + 0.025*sl 0.62 + 0.025*sl t phl 0.81 0.76 + 0.024*sl 0.78 + 0.017*sl 0.82 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.13 + 0.023*sl 0.13 + 0.021*sl 0.14 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-369 kg80/KGM80 ld1q/ld1qd2 d latch with active high, q output only, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 ld1q ld1qd2 ld1q ld1qd2 dgdg 0.8 0.8 0.8 0.8 4.0 5.0 KGM80 ld1q ld1qd2 ld1q ld1qd2 dgdg 0.9 0.9 0.9 0.9 4.0 5.0 parameter symbol kg80 KGM80 ld1q ld1qd2 ld1q ld1qd2 pulse width high (g) t pwh 0.61 0.61 0.99 0.99 input setup time (d to g) t su 0.31 0.31 0.61 0.61 input hold time (d to g) t hd 0.15 0.15 0.33 0.33 d g q g g gb d gb g g gb q truth table d g q (n+1) 010 111 x 0 q (n)
kg80/KGM80 3-370 sec asic ld1q/ld1qd2 d latch with active high, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld1q kg80 ld1qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.49 0.40 + 0.042*sl 0.40 + 0.042*sl 0.40 + 0.042*sl t phl 0.54 0.48 + 0.029*sl 0.50 + 0.025*sl 0.50 + 0.023*sl t r 0.26 0.08 + 0.087*sl 0.07 + 0.090*sl 0.07 + 0.091*sl t f 0.15 0.07 + 0.041*sl 0.07 + 0.041*sl 0.06 + 0.042*sl g to q t plh 0.54 0.45 + 0.042*sl 0.45 + 0.042*sl 0.45 + 0.042*sl t phl 0.49 0.43 + 0.029*sl 0.44 + 0.025*sl 0.45 + 0.023*sl t r 0.26 0.08 + 0.087*sl 0.07 + 0.090*sl 0.07 + 0.091*sl t f 0.15 0.07 + 0.040*sl 0.07 + 0.041*sl 0.06 + 0.042*sl *g 1 sl 2 *g 2 2 sl *g 3 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.47 0.42 + 0.023*sl 0.43 + 0.021*sl 0.43 + 0.021*sl t phl 0.54 0.51 + 0.018*sl 0.52 + 0.014*sl 0.53 + 0.012*sl t r 0.18 0.09 + 0.043*sl 0.09 + 0.044*sl 0.08 + 0.046*sl t f 0.13 0.09 + 0.020*sl 0.09 + 0.020*sl 0.09 + 0.020*sl g to q t plh 0.52 0.48 + 0.021*sl 0.48 + 0.021*sl 0.48 + 0.021*sl t phl 0.49 0.46 + 0.018*sl 0.46 + 0.014*sl 0.48 + 0.012*sl t r 0.17 0.09 + 0.041*sl 0.08 + 0.045*sl 0.08 + 0.046*sl t f 0.13 0.09 + 0.021*sl 0.09 + 0.020*sl 0.09 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-371 kg80/KGM80 ld1q/ld1qd2 d latch with active high, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld1q KGM80 ld1qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.67 0.57 + 0.051*sl 0.57 + 0.050*sl 0.57 + 0.050*sl t phl 0.76 0.70 + 0.032*sl 0.72 + 0.025*sl 0.74 + 0.023*sl t r 0.33 0.12 + 0.106*sl 0.11 + 0.109*sl 0.11 + 0.109*sl t f 0.18 0.09 + 0.044*sl 0.10 + 0.042*sl 0.09 + 0.043*sl g to q t plh 0.76 0.66 + 0.051*sl 0.66 + 0.050*sl 0.66 + 0.050*sl t phl 0.72 0.65 + 0.032*sl 0.67 + 0.025*sl 0.69 + 0.023*sl t r 0.33 0.12 + 0.106*sl 0.11 + 0.109*sl 0.11 + 0.109*sl t f 0.18 0.10 + 0.043*sl 0.10 + 0.042*sl 0.09 + 0.043*sl *g 1 sl 3 *g 2 3 sl 11 *g 3 11 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.65 0.59 + 0.027*sl 0.60 + 0.025*sl 0.60 + 0.025*sl t phl 0.77 0.73 + 0.020*sl 0.75 + 0.015*sl 0.77 + 0.013*sl t r 0.23 0.13 + 0.051*sl 0.12 + 0.053*sl 0.11 + 0.054*sl t f 0.16 0.11 + 0.023*sl 0.12 + 0.021*sl 0.12 + 0.020*sl g to q t plh 0.74 0.68 + 0.027*sl 0.69 + 0.025*sl 0.69 + 0.025*sl t phl 0.73 0.69 + 0.020*sl 0.70 + 0.015*sl 0.73 + 0.012*sl t r 0.23 0.13 + 0.051*sl 0.12 + 0.053*sl 0.11 + 0.054*sl t f 0.16 0.11 + 0.023*sl 0.12 + 0.021*sl 0.12 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-372 sec asic ld1x4/ld1x4d2 4-bit d latch with active high, 1x/2x drive logic symbol cell data timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 ld1x4 ld1x4d2 ld1x4 ld1x4d2 dngdng 0.9 0.9 0.9 0.9 15.0 19.0 KGM80 ld1x4 ld1x4d2 ld1x4 ld1x4d2 dngdng 1.0 1.1 1.0 1.1 15.0 19.0 parameter symbol kg80 KGM80 ld1x4 ld1x4d2 ld1x4 ld1x4d2 pulse width high (g) t pwh 0.61 0.61 0.99 0.99 input setup time (d0 to g) t su 0.26 0.28 0.52 0.55 input hold time (d0 to g) t hd 0.26 0.20 0.46 0.46 input setup time (d1 to g) t su 0.26 0.28 0.52 0.55 input hold time (d1 to g) t hd 0.26 0.20 0.46 0.46 input setup time (d2 to g) t su 0.26 0.28 0.52 0.55 input hold time (d2 to g) t hd 0.26 0.20 0.46 0.46 input setup time (d3 to g) t su 0.26 0.28 0.52 0.55 input hold time (d3 to g) t hd 0.26 0.20 0.46 0.46 d0 d1 d2 d3 g q0 q1 q2 q3 qn0 qn1 qn2 qn3 truth table dn g qn (n+1) qnn (n+1) 0101 1110 x 0 qn (n) qnn (n)
sec asic 3-373 kg80/KGM80 ld1x4/ld1x4d2 4-bit d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld1x4 (continued) [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to q0 t plh 0.54 0.46 + 0.040*sl 0.46 + 0.041*sl 0.45 + 0.042*sl t phl 0.60 0.54 + 0.030*sl 0.55 + 0.025*sl 0.56 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl g to q0 t plh 0.78 0.70 + 0.041*sl 0.70 + 0.041*sl 0.69 + 0.042*sl t phl 0.65 0.59 + 0.029*sl 0.60 + 0.025*sl 0.61 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.041*sl 0.08 + 0.040*sl 0.07 + 0.042*sl d1 to q1 t plh 0.55 0.46 + 0.041*sl 0.46 + 0.041*sl 0.46 + 0.042*sl t phl 0.60 0.54 + 0.030*sl 0.55 + 0.025*sl 0.57 + 0.023*sl t r 0.27 0.10 + 0.087*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl g to q1 t plh 0.79 0.71 + 0.040*sl 0.70 + 0.041*sl 0.70 + 0.042*sl t phl 0.66 0.60 + 0.030*sl 0.61 + 0.025*sl 0.62 + 0.023*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.08 + 0.040*sl 0.08 + 0.042*sl d2 to q2 t plh 0.54 0.46 + 0.040*sl 0.46 + 0.041*sl 0.46 + 0.042*sl t phl 0.60 0.54 + 0.030*sl 0.55 + 0.025*sl 0.56 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.08 + 0.091*sl t f 0.16 0.08 + 0.041*sl 0.08 + 0.040*sl 0.07 + 0.042*sl g to q2 t plh 0.78 0.70 + 0.040*sl 0.70 + 0.041*sl 0.70 + 0.042*sl t phl 0.65 0.60 + 0.030*sl 0.61 + 0.025*sl 0.62 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.041*sl 0.08 + 0.040*sl 0.07 + 0.042*sl d3 to q3 t plh 0.54 0.46 + 0.040*sl 0.46 + 0.041*sl 0.45 + 0.042*sl t phl 0.60 0.54 + 0.030*sl 0.55 + 0.025*sl 0.56 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl g to q3 t plh 0.78 0.70 + 0.041*sl 0.70 + 0.041*sl 0.69 + 0.042*sl t phl 0.65 0.59 + 0.029*sl 0.60 + 0.025*sl 0.61 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.041*sl 0.08 + 0.040*sl 0.07 + 0.042*sl d0 to qn0 t plh 0.52 0.44 + 0.042*sl 0.44 + 0.041*sl 0.44 + 0.042*sl t phl 0.41 0.34 + 0.031*sl 0.36 + 0.026*sl 0.37 + 0.023*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.039*sl 0.09 + 0.040*sl 0.08 + 0.042*sl g to qn0 t plh 0.57 0.49 + 0.041*sl 0.49 + 0.042*sl 0.49 + 0.042*sl t phl 0.65 0.59 + 0.030*sl 0.60 + 0.026*sl 0.61 + 0.023*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.090*sl 0.08 + 0.090*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.09 + 0.041*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-374 sec asic ld1x4/ld1x4d2 4-bit d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld1x4 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d1 to qn1 t plh 0.52 0.44 + 0.042*sl 0.44 + 0.042*sl 0.44 + 0.042*sl t phl 0.41 0.34 + 0.031*sl 0.36 + 0.026*sl 0.37 + 0.023*sl t r 0.27 0.11 + 0.084*sl 0.09 + 0.089*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl g to qn1 t plh 0.57 0.49 + 0.042*sl 0.49 + 0.042*sl 0.49 + 0.042*sl t phl 0.65 0.59 + 0.030*sl 0.60 + 0.026*sl 0.61 + 0.023*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.090*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.08 + 0.041*sl d2 to qn2 t plh 0.52 0.44 + 0.042*sl 0.44 + 0.041*sl 0.44 + 0.042*sl t phl 0.41 0.34 + 0.031*sl 0.36 + 0.026*sl 0.37 + 0.023*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.089*sl 0.09 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl g to qn2 t plh 0.58 0.49 + 0.042*sl 0.49 + 0.042*sl 0.49 + 0.042*sl t phl 0.65 0.59 + 0.030*sl 0.60 + 0.026*sl 0.61 + 0.023*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.09 + 0.041*sl d3 to qn3 t plh 0.52 0.44 + 0.042*sl 0.44 + 0.041*sl 0.44 + 0.042*sl t phl 0.41 0.34 + 0.031*sl 0.36 + 0.026*sl 0.37 + 0.023*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.039*sl 0.09 + 0.040*sl 0.08 + 0.042*sl g to qn3 t plh 0.57 0.49 + 0.041*sl 0.49 + 0.042*sl 0.49 + 0.042*sl t phl 0.65 0.59 + 0.030*sl 0.60 + 0.026*sl 0.61 + 0.023*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.090*sl 0.08 + 0.090*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.09 + 0.041*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-375 kg80/KGM80 ld1x4/ld1x4d2 4-bit d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld1x4d2 (continued) [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to q0 t plh 0.56 0.53 + 0.019*sl 0.53 + 0.019*sl 0.52 + 0.020*sl t phl 0.63 0.59 + 0.018*sl 0.60 + 0.015*sl 0.61 + 0.013*sl t r 0.16 0.09 + 0.039*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.022*sl 0.10 + 0.020*sl 0.09 + 0.020*sl g to q0 t plh 0.81 0.77 + 0.019*sl 0.77 + 0.019*sl 0.76 + 0.020*sl t phl 0.68 0.65 + 0.018*sl 0.65 + 0.015*sl 0.67 + 0.013*sl t r 0.16 0.08 + 0.042*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.022*sl 0.09 + 0.020*sl 0.09 + 0.020*sl d1 to q1 t plh 0.57 0.53 + 0.020*sl 0.53 + 0.019*sl 0.53 + 0.020*sl t phl 0.64 0.60 + 0.019*sl 0.61 + 0.015*sl 0.62 + 0.013*sl t r 0.17 0.09 + 0.039*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.09 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.020*sl g to q1 t plh 0.82 0.78 + 0.019*sl 0.78 + 0.019*sl 0.77 + 0.020*sl t phl 0.69 0.65 + 0.019*sl 0.66 + 0.015*sl 0.67 + 0.013*sl t r 0.17 0.09 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.09 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl d2 to q2 t plh 0.58 0.54 + 0.019*sl 0.54 + 0.019*sl 0.54 + 0.020*sl t phl 0.65 0.61 + 0.017*sl 0.62 + 0.014*sl 0.63 + 0.013*sl t r 0.19 0.11 + 0.040*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.15 0.10 + 0.021*sl 0.11 + 0.020*sl 0.11 + 0.020*sl g to q2 t plh 0.83 0.79 + 0.018*sl 0.79 + 0.019*sl 0.78 + 0.020*sl t phl 0.70 0.66 + 0.018*sl 0.67 + 0.014*sl 0.68 + 0.013*sl t r 0.19 0.11 + 0.041*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.15 0.10 + 0.022*sl 0.11 + 0.020*sl 0.11 + 0.020*sl d3 to q3 t plh 0.56 0.53 + 0.020*sl 0.53 + 0.019*sl 0.52 + 0.020*sl t phl 0.63 0.59 + 0.018*sl 0.60 + 0.015*sl 0.62 + 0.013*sl t r 0.16 0.08 + 0.040*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.022*sl 0.10 + 0.019*sl 0.09 + 0.020*sl g to q3 t plh 0.81 0.77 + 0.019*sl 0.77 + 0.019*sl 0.77 + 0.020*sl t phl 0.68 0.65 + 0.018*sl 0.65 + 0.015*sl 0.67 + 0.013*sl t r 0.16 0.08 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.022*sl 0.09 + 0.020*sl 0.09 + 0.020*sl d0 to qn0 t plh 0.50 0.45 + 0.023*sl 0.46 + 0.021*sl 0.46 + 0.021*sl t phl 0.40 0.36 + 0.021*sl 0.37 + 0.015*sl 0.39 + 0.013*sl t r 0.17 0.09 + 0.037*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.020*sl g to qn0 t plh 0.55 0.51 + 0.023*sl 0.51 + 0.021*sl 0.51 + 0.021*sl t phl 0.65 0.61 + 0.020*sl 0.62 + 0.015*sl 0.63 + 0.013*sl t r 0.17 0.09 + 0.038*sl 0.08 + 0.043*sl 0.07 + 0.045*sl t f 0.14 0.10 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-376 sec asic ld1x4/ld1x4d2 4-bit d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld1x4d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d1 to qn1 t plh 0.50 0.46 + 0.023*sl 0.46 + 0.021*sl 0.46 + 0.021*sl t phl 0.40 0.36 + 0.020*sl 0.37 + 0.015*sl 0.39 + 0.013*sl t r 0.17 0.09 + 0.038*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl g to qn1 t plh 0.55 0.51 + 0.023*sl 0.51 + 0.021*sl 0.51 + 0.021*sl t phl 0.65 0.61 + 0.020*sl 0.62 + 0.015*sl 0.63 + 0.013*sl t r 0.17 0.09 + 0.038*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl d2 to qn2 t plh 0.50 0.46 + 0.022*sl 0.46 + 0.021*sl 0.46 + 0.021*sl t phl 0.40 0.36 + 0.021*sl 0.37 + 0.015*sl 0.39 + 0.013*sl t r 0.17 0.09 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl g to qn2 t plh 0.55 0.51 + 0.023*sl 0.51 + 0.021*sl 0.51 + 0.021*sl t phl 0.65 0.61 + 0.021*sl 0.62 + 0.015*sl 0.63 + 0.013*sl t r 0.17 0.09 + 0.038*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl d3 to qn3 t plh 0.50 0.45 + 0.023*sl 0.46 + 0.021*sl 0.46 + 0.021*sl t phl 0.40 0.36 + 0.020*sl 0.37 + 0.015*sl 0.38 + 0.013*sl t r 0.17 0.09 + 0.038*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.020*sl g to qn3 t plh 0.55 0.51 + 0.023*sl 0.51 + 0.021*sl 0.51 + 0.021*sl t phl 0.64 0.60 + 0.020*sl 0.62 + 0.015*sl 0.63 + 0.013*sl t r 0.17 0.09 + 0.038*sl 0.08 + 0.043*sl 0.07 + 0.045*sl t f 0.14 0.09 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-377 kg80/KGM80 ld1x4/ld1x4d2 4-bit d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld1x4 (continued) [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to q0 t plh 0.74 0.64 + 0.049*sl 0.64 + 0.050*sl 0.64 + 0.050*sl t phl 0.83 0.77 + 0.033*sl 0.79 + 0.026*sl 0.81 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl g to q0 t plh 1.09 1.00 + 0.049*sl 0.99 + 0.050*sl 1.00 + 0.050*sl t phl 0.90 0.84 + 0.032*sl 0.85 + 0.026*sl 0.88 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl d1 to q1 t plh 0.75 0.66 + 0.049*sl 0.65 + 0.050*sl 0.65 + 0.050*sl t phl 0.84 0.78 + 0.032*sl 0.79 + 0.026*sl 0.82 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.042*sl 0.11 + 0.042*sl g to q1 t plh 1.11 1.01 + 0.049*sl 1.00 + 0.050*sl 1.01 + 0.050*sl t phl 0.91 0.85 + 0.032*sl 0.87 + 0.026*sl 0.89 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.041*sl 0.11 + 0.042*sl d2 to q2 t plh 0.75 0.65 + 0.049*sl 0.65 + 0.050*sl 0.65 + 0.050*sl t phl 0.84 0.77 + 0.033*sl 0.79 + 0.026*sl 0.82 + 0.023*sl t r 0.34 0.14 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl g to q2 t plh 1.10 1.00 + 0.049*sl 1.00 + 0.050*sl 1.00 + 0.050*sl t phl 0.91 0.84 + 0.033*sl 0.86 + 0.026*sl 0.89 + 0.023*sl t r 0.34 0.14 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.11 + 0.042*sl 0.11 + 0.042*sl d3 to q3 t plh 0.74 0.64 + 0.049*sl 0.64 + 0.050*sl 0.64 + 0.050*sl t phl 0.83 0.76 + 0.033*sl 0.79 + 0.026*sl 0.81 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl g to q3 t plh 1.09 1.00 + 0.049*sl 0.99 + 0.050*sl 1.00 + 0.050*sl t phl 0.90 0.84 + 0.033*sl 0.86 + 0.026*sl 0.88 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl d0 to qn0 t plh 0.71 0.61 + 0.051*sl 0.61 + 0.050*sl 0.62 + 0.050*sl t phl 0.55 0.48 + 0.034*sl 0.50 + 0.026*sl 0.53 + 0.023*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.043*sl 0.12 + 0.041*sl 0.11 + 0.042*sl g to qn0 t plh 0.79 0.68 + 0.051*sl 0.69 + 0.050*sl 0.69 + 0.050*sl t phl 0.90 0.84 + 0.034*sl 0.86 + 0.026*sl 0.89 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-378 sec asic ld1x4/ld1x4d2 4-bit d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld1x4 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d1 to qn1 t plh 0.71 0.61 + 0.051*sl 0.61 + 0.050*sl 0.62 + 0.050*sl t phl 0.55 0.48 + 0.034*sl 0.50 + 0.026*sl 0.54 + 0.023*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.042*sl 0.12 + 0.041*sl 0.11 + 0.042*sl g to qn1 t plh 0.79 0.68 + 0.051*sl 0.69 + 0.050*sl 0.69 + 0.050*sl t phl 0.90 0.84 + 0.034*sl 0.86 + 0.026*sl 0.89 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl d2 to qn2 t plh 0.71 0.61 + 0.051*sl 0.61 + 0.050*sl 0.62 + 0.050*sl t phl 0.55 0.48 + 0.034*sl 0.51 + 0.026*sl 0.54 + 0.023*sl t r 0.36 0.15 + 0.105*sl 0.14 + 0.108*sl 0.13 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.12 + 0.041*sl 0.12 + 0.042*sl g to qn2 t plh 0.79 0.69 + 0.051*sl 0.69 + 0.050*sl 0.69 + 0.050*sl t phl 0.91 0.84 + 0.034*sl 0.86 + 0.026*sl 0.89 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.14 + 0.108*sl 0.13 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.12 + 0.041*sl 0.12 + 0.042*sl d3 to qn3 t plh 0.71 0.61 + 0.051*sl 0.61 + 0.050*sl 0.62 + 0.050*sl t phl 0.55 0.48 + 0.034*sl 0.50 + 0.026*sl 0.53 + 0.023*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.042*sl 0.12 + 0.041*sl 0.11 + 0.042*sl g to qn3 t plh 0.79 0.68 + 0.051*sl 0.69 + 0.050*sl 0.69 + 0.050*sl t phl 0.90 0.84 + 0.034*sl 0.86 + 0.026*sl 0.89 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-379 kg80/KGM80 ld1x4/ld1x4d2 4-bit d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld1x4d2 (continued) [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to q0 t plh 0.78 0.74 + 0.025*sl 0.74 + 0.024*sl 0.73 + 0.025*sl t phl 0.89 0.84 + 0.021*sl 0.86 + 0.016*sl 0.89 + 0.013*sl t r 0.21 0.11 + 0.051*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.021*sl g to q0 t plh 1.14 1.09 + 0.025*sl 1.10 + 0.024*sl 1.09 + 0.025*sl t phl 0.96 0.91 + 0.021*sl 0.93 + 0.016*sl 0.96 + 0.013*sl t r 0.21 0.11 + 0.051*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.026*sl 0.12 + 0.021*sl 0.13 + 0.021*sl d1 to q1 t plh 0.80 0.75 + 0.025*sl 0.75 + 0.024*sl 0.74 + 0.025*sl t phl 0.90 0.85 + 0.021*sl 0.87 + 0.016*sl 0.90 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.052*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.021*sl 0.13 + 0.021*sl g to q1 t plh 1.15 1.10 + 0.025*sl 1.11 + 0.024*sl 1.10 + 0.025*sl t phl 0.97 0.92 + 0.021*sl 0.94 + 0.016*sl 0.97 + 0.013*sl t r 0.22 0.12 + 0.051*sl 0.11 + 0.052*sl 0.10 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.13 + 0.021*sl 0.13 + 0.020*sl d2 to q2 t plh 0.81 0.76 + 0.023*sl 0.76 + 0.024*sl 0.75 + 0.025*sl t phl 0.91 0.87 + 0.019*sl 0.88 + 0.015*sl 0.91 + 0.013*sl t r 0.25 0.15 + 0.051*sl 0.14 + 0.053*sl 0.13 + 0.054*sl t f 0.18 0.13 + 0.024*sl 0.14 + 0.021*sl 0.14 + 0.021*sl g to q2 t plh 1.17 1.12 + 0.024*sl 1.12 + 0.024*sl 1.11 + 0.025*sl t phl 0.98 0.94 + 0.020*sl 0.95 + 0.015*sl 0.98 + 0.013*sl t r 0.25 0.15 + 0.052*sl 0.15 + 0.052*sl 0.13 + 0.054*sl t f 0.18 0.13 + 0.024*sl 0.14 + 0.021*sl 0.15 + 0.020*sl d3 to q3 t plh 0.78 0.73 + 0.025*sl 0.74 + 0.024*sl 0.73 + 0.025*sl t phl 0.89 0.84 + 0.021*sl 0.86 + 0.016*sl 0.89 + 0.013*sl t r 0.21 0.11 + 0.051*sl 0.11 + 0.053*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.021*sl g to q3 t plh 1.14 1.09 + 0.024*sl 1.10 + 0.024*sl 1.09 + 0.025*sl t phl 0.96 0.91 + 0.021*sl 0.93 + 0.016*sl 0.96 + 0.013*sl t r 0.21 0.11 + 0.050*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.026*sl 0.12 + 0.021*sl 0.13 + 0.021*sl d0 to qn0 t plh 0.69 0.63 + 0.028*sl 0.64 + 0.025*sl 0.64 + 0.025*sl t phl 0.55 0.50 + 0.023*sl 0.52 + 0.017*sl 0.56 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.12 + 0.022*sl 0.14 + 0.020*sl g to qn0 t plh 0.76 0.70 + 0.028*sl 0.71 + 0.025*sl 0.71 + 0.025*sl t phl 0.91 0.86 + 0.023*sl 0.88 + 0.016*sl 0.92 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.022*sl 0.14 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-380 sec asic ld1x4/ld1x4d2 4-bit d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld1x4d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d1 to qn1 t plh 0.69 0.63 + 0.028*sl 0.64 + 0.025*sl 0.64 + 0.025*sl t phl 0.55 0.51 + 0.023*sl 0.53 + 0.016*sl 0.56 + 0.013*sl t r 0.22 0.12 + 0.049*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.022*sl 0.14 + 0.021*sl g to qn1 t plh 0.76 0.70 + 0.028*sl 0.71 + 0.025*sl 0.71 + 0.025*sl t phl 0.91 0.87 + 0.023*sl 0.89 + 0.016*sl 0.92 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.022*sl 0.14 + 0.021*sl d2 to qn2 t plh 0.69 0.63 + 0.028*sl 0.64 + 0.025*sl 0.64 + 0.025*sl t phl 0.55 0.51 + 0.023*sl 0.53 + 0.017*sl 0.56 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.022*sl 0.14 + 0.021*sl g to qn2 t plh 0.76 0.70 + 0.028*sl 0.71 + 0.025*sl 0.71 + 0.025*sl t phl 0.91 0.87 + 0.023*sl 0.89 + 0.016*sl 0.92 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.022*sl 0.14 + 0.021*sl d3 to qn3 t plh 0.69 0.63 + 0.028*sl 0.64 + 0.025*sl 0.64 + 0.025*sl t phl 0.55 0.50 + 0.023*sl 0.52 + 0.016*sl 0.56 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.021*sl g to qn3 t plh 0.76 0.70 + 0.027*sl 0.71 + 0.025*sl 0.71 + 0.025*sl t phl 0.91 0.86 + 0.023*sl 0.88 + 0.017*sl 0.92 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.022*sl 0.14 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-381 kg80/KGM80 yld1/yld1d2 fast d latch with active high, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 yld1 yld1d2 yld1 yld1d2 dgdg 2.9 0.8 3.7 0.8 4.0 5.0 KGM80 yld1 yld1d2 yld1 yld1d2 dgdg 3.7 0.9 4.6 0.9 4.0 5.0 parameter symbol kg80 KGM80 yld1 yld1d2 yld1 yld1d2 pulse width high (g) t pwh 0.61 0.61 0.99 0.99 input setup time (d to g) t su 0.17 0.15 0.39 0.39 input hold time (d to g) t hd 0.15 0.15 0.33 0.33 d g q qn g g gb d gb g g gb qn q truth table d g q (n+1) qn (n+1) 0101 1110 x 0 q (n) qn (n)
kg80/KGM80 3-382 sec asic yld1/yld1d2 fast d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 yld1 kg80 yld1d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.36 0.18 + 0.086*sl 0.20 + 0.078*sl 0.22 + 0.076*sl t phl 0.40 0.25 + 0.076*sl 0.25 + 0.076*sl 0.25 + 0.076*sl t r 0.32 0.14 + 0.090*sl 0.13 + 0.094*sl 0.13 + 0.094*sl t f 0.21 0.09 + 0.061*sl 0.09 + 0.062*sl 0.08 + 0.063*sl g to q t plh 0.49 0.33 + 0.080*sl 0.34 + 0.077*sl 0.34 + 0.076*sl t phl 0.50 0.34 + 0.077*sl 0.34 + 0.077*sl 0.34 + 0.077*sl t r 0.32 0.13 + 0.094*sl 0.13 + 0.094*sl 0.13 + 0.095*sl t f 0.21 0.08 + 0.064*sl 0.08 + 0.063*sl 0.08 + 0.063*sl d to qn t plh 0.28 0.20 + 0.041*sl 0.20 + 0.040*sl 0.19 + 0.041*sl t phl 0.16 0.09 + 0.036*sl 0.11 + 0.027*sl 0.14 + 0.023*sl t r 0.37 0.21 + 0.080*sl 0.20 + 0.085*sl 0.18 + 0.089*sl t f 0.26 0.19 + 0.037*sl 0.19 + 0.036*sl 0.17 + 0.038*sl g to qn t plh 0.37 0.29 + 0.042*sl 0.29 + 0.042*sl 0.29 + 0.042*sl t phl 0.31 0.25 + 0.028*sl 0.26 + 0.024*sl 0.27 + 0.023*sl t r 0.34 0.16 + 0.087*sl 0.16 + 0.090*sl 0.15 + 0.091*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.041*sl 0.09 + 0.042*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.27 0.18 + 0.047*sl 0.19 + 0.042*sl 0.20 + 0.039*sl t phl 0.33 0.25 + 0.040*sl 0.26 + 0.038*sl 0.25 + 0.038*sl t r 0.21 0.12 + 0.044*sl 0.11 + 0.046*sl 0.11 + 0.048*sl t f 0.14 0.08 + 0.030*sl 0.08 + 0.031*sl 0.07 + 0.031*sl g to q t plh 0.42 0.34 + 0.042*sl 0.34 + 0.040*sl 0.35 + 0.039*sl t phl 0.43 0.35 + 0.039*sl 0.35 + 0.038*sl 0.35 + 0.038*sl t r 0.20 0.10 + 0.047*sl 0.10 + 0.048*sl 0.10 + 0.048*sl t f 0.13 0.07 + 0.031*sl 0.07 + 0.031*sl 0.06 + 0.032*sl d to qn t plh 0.25 0.21 + 0.022*sl 0.22 + 0.020*sl 0.21 + 0.020*sl t phl 0.14 0.10 + 0.020*sl 0.11 + 0.016*sl 0.13 + 0.013*sl t r 0.29 0.21 + 0.040*sl 0.21 + 0.042*sl 0.20 + 0.044*sl t f 0.23 0.19 + 0.018*sl 0.19 + 0.018*sl 0.19 + 0.019*sl g to qn t plh 0.35 0.31 + 0.021*sl 0.31 + 0.021*sl 0.31 + 0.021*sl t phl 0.30 0.27 + 0.016*sl 0.28 + 0.014*sl 0.28 + 0.012*sl t r 0.26 0.17 + 0.043*sl 0.17 + 0.045*sl 0.16 + 0.046*sl t f 0.15 0.11 + 0.020*sl 0.11 + 0.020*sl 0.11 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-383 kg80/KGM80 yld1/yld1d2 fast d latch with active high, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 yld1 KGM80 yld1d2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.49 0.29 + 0.098*sl 0.32 + 0.088*sl 0.34 + 0.086*sl t phl 0.52 0.34 + 0.092*sl 0.34 + 0.092*sl 0.34 + 0.092*sl t r 0.43 0.21 + 0.110*sl 0.20 + 0.112*sl 0.20 + 0.113*sl t f 0.25 0.12 + 0.065*sl 0.11 + 0.067*sl 0.11 + 0.067*sl g to q t plh 0.67 0.48 + 0.092*sl 0.50 + 0.087*sl 0.51 + 0.086*sl t phl 0.69 0.50 + 0.092*sl 0.50 + 0.092*sl 0.50 + 0.092*sl t r 0.42 0.20 + 0.112*sl 0.20 + 0.112*sl 0.19 + 0.113*sl t f 0.25 0.11 + 0.068*sl 0.11 + 0.067*sl 0.11 + 0.068*sl d to qn t plh 0.36 0.26 + 0.050*sl 0.26 + 0.049*sl 0.26 + 0.050*sl t phl 0.23 0.16 + 0.038*sl 0.19 + 0.027*sl 0.22 + 0.023*sl t r 0.47 0.27 + 0.101*sl 0.25 + 0.106*sl 0.22 + 0.109*sl t f 0.29 0.20 + 0.042*sl 0.21 + 0.038*sl 0.19 + 0.040*sl g to qn t plh 0.52 0.42 + 0.051*sl 0.42 + 0.050*sl 0.42 + 0.050*sl t phl 0.42 0.36 + 0.030*sl 0.38 + 0.025*sl 0.39 + 0.023*sl t r 0.44 0.23 + 0.105*sl 0.23 + 0.108*sl 0.21 + 0.109*sl t f 0.21 0.13 + 0.042*sl 0.13 + 0.042*sl 0.12 + 0.043*sl yy path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.39 0.28 + 0.053*sl 0.30 + 0.047*sl 0.33 + 0.044*sl t phl 0.44 0.34 + 0.047*sl 0.35 + 0.045*sl 0.35 + 0.045*sl t r 0.27 0.16 + 0.055*sl 0.16 + 0.055*sl 0.15 + 0.056*sl t f 0.16 0.10 + 0.032*sl 0.09 + 0.033*sl 0.09 + 0.033*sl g to q t plh 0.59 0.50 + 0.049*sl 0.51 + 0.045*sl 0.53 + 0.043*sl t phl 0.60 0.51 + 0.046*sl 0.51 + 0.046*sl 0.51 + 0.046*sl t r 0.27 0.16 + 0.056*sl 0.15 + 0.056*sl 0.15 + 0.056*sl t f 0.16 0.09 + 0.032*sl 0.09 + 0.033*sl 0.09 + 0.034*sl d to qn t plh 0.33 0.28 + 0.026*sl 0.28 + 0.025*sl 0.28 + 0.025*sl t phl 0.21 0.17 + 0.022*sl 0.18 + 0.016*sl 0.23 + 0.013*sl t r 0.36 0.26 + 0.050*sl 0.26 + 0.052*sl 0.24 + 0.053*sl t f 0.26 0.21 + 0.023*sl 0.22 + 0.019*sl 0.23 + 0.019*sl g to qn t plh 0.50 0.44 + 0.025*sl 0.45 + 0.025*sl 0.45 + 0.025*sl t phl 0.43 0.39 + 0.018*sl 0.40 + 0.014*sl 0.42 + 0.012*sl t r 0.34 0.24 + 0.051*sl 0.23 + 0.053*sl 0.22 + 0.054*sl t f 0.19 0.15 + 0.022*sl 0.15 + 0.021*sl 0.15 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-384 sec asic ld1a d latch with active high, tri-state output logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) output load (sl) gate count kg80 dgeq 6.0 0.9 0.9 1.7 0.9 KGM80 dgeq 6.0 1.0 1.0 1.9 1.4 parameter symbol kg80 KGM80 pulse width high (g) t pwh 0.61 0.99 input setup time (d to g) t su 0.34 0.64 input hold time (d to g) t hd 0.15 0.33 d g q e d gb g e q g gb g g gb truth table d g e q (n+1) x x 0 hi-z 0110 1111 x 0 1 q (n)
sec asic 3-385 kg80/KGM80 ld1a d latch with active high, tri-state output switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld1a switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld1a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.56 0.47 + 0.043*sl 0.48 + 0.042*sl 0.48 + 0.042*sl t phl 0.64 0.56 + 0.040*sl 0.57 + 0.035*sl 0.58 + 0.034*sl t r 0.27 0.10 + 0.087*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.23 0.10 + 0.065*sl 0.10 + 0.066*sl 0.09 + 0.068*sl g to q t plh 0.63 0.54 + 0.044*sl 0.55 + 0.042*sl 0.55 + 0.042*sl t phl 0.60 0.52 + 0.040*sl 0.53 + 0.035*sl 0.54 + 0.034*sl t r 0.27 0.10 + 0.087*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.23 0.10 + 0.065*sl 0.10 + 0.066*sl 0.09 + 0.068*sl e to q t plh 0.26 0.16 + 0.051*sl 0.18 + 0.042*sl 0.19 + 0.042*sl t phl 0.10 0.00 + 0.049*sl 0.03 + 0.037*sl 0.05 + 0.035*sl t r 0.27 0.11 + 0.083*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.28 0.17 + 0.056*sl 0.16 + 0.062*sl 0.13 + 0.065*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.28 0.28 + 0.000*sl 0.28 + 0.000*sl 0.28 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.77 0.67 + 0.053*sl 0.68 + 0.050*sl 0.68 + 0.050*sl t phl 0.90 0.80 + 0.046*sl 0.82 + 0.039*sl 0.84 + 0.037*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.28 0.14 + 0.073*sl 0.14 + 0.072*sl 0.12 + 0.074*sl g to q t plh 0.89 0.78 + 0.053*sl 0.79 + 0.050*sl 0.79 + 0.050*sl t phl 0.86 0.77 + 0.046*sl 0.79 + 0.039*sl 0.80 + 0.037*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.28 0.14 + 0.073*sl 0.14 + 0.072*sl 0.12 + 0.074*sl e to q t plh 0.36 0.25 + 0.056*sl 0.26 + 0.050*sl 0.26 + 0.050*sl t phl 0.15 0.05 + 0.048*sl 0.08 + 0.039*sl 0.09 + 0.037*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.31 0.18 + 0.064*sl 0.16 + 0.070*sl 0.13 + 0.073*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.37 0.37 + -0.001*sl 0.36 + 0.000*sl 0.37 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-386 sec asic ld1b d latch with active high, tri-state output, separate wr, wrn logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) output load (sl) gate count kg80 d wr wrn rd zn 5.0 0.9 0.7 0.6 1.5 0.6 KGM80 d wr wrn rd zn 5.0 1.0 1.1 0.7 1.8 0.8 parameter symbol kg80 KGM80 pulse width high (wr) t pwh 0.61 0.99 pulse width low (wrn) t pwl 0.61 0.99 input setup time (d to wr) t su 0.67 1.11 input hold time (d to wr) t hd 0.15 0.33 input setup time (d to wrn) t su 0.67 1.11 input hold time (d to wrn) t hd 0.15 0.33 skew time (wr to wrn) t sk 0.81 1.22 skew time (wrn to wr) t sk 0.81 1.22 d wr wrn zn rd qn d wrn wr rd qn wrn wr wr wr wrn wrn zn truth table d wr wrn rd qn (n+1) zn (n+1) 01001 hi-z 11000 hi-z 010111 110100 x 0 1 0 qn (n) hi-z x 0 1 1 qn (n) qn (n)
sec asic 3-387 kg80/KGM80 ld1b d latch with active high, tri-state output, separate wr, wrn switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld1b path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to qn t plh 0.53 0.44 + 0.043*sl 0.45 + 0.042*sl 0.45 + 0.042*sl t phl 0.41 0.35 + 0.031*sl 0.36 + 0.027*sl 0.38 + 0.024*sl t r 0.44 0.27 + 0.084*sl 0.26 + 0.088*sl 0.25 + 0.090*sl t f 0.28 0.19 + 0.043*sl 0.19 + 0.042*sl 0.20 + 0.041*sl wr to qn t plh 0.31 0.23 + 0.042*sl 0.23 + 0.042*sl 0.23 + 0.042*sl t phl 0.32 0.26 + 0.030*sl 0.27 + 0.026*sl 0.28 + 0.024*sl t r 0.44 0.27 + 0.085*sl 0.27 + 0.088*sl 0.25 + 0.090*sl t f 0.27 0.18 + 0.043*sl 0.19 + 0.042*sl 0.19 + 0.042*sl wrn to qn t plh 0.31 0.23 + 0.042*sl 0.23 + 0.042*sl 0.23 + 0.042*sl t phl 0.32 0.26 + 0.030*sl 0.27 + 0.026*sl 0.28 + 0.024*sl t r 0.44 0.27 + 0.085*sl 0.27 + 0.088*sl 0.25 + 0.090*sl t f 0.27 0.18 + 0.043*sl 0.19 + 0.042*sl 0.19 + 0.042*sl d to zn t plh 0.82 0.64 + 0.090*sl 0.64 + 0.087*sl 0.66 + 0.085*sl t phl 0.67 0.52 + 0.075*sl 0.54 + 0.069*sl 0.56 + 0.065*sl t r 0.31 0.14 + 0.087*sl 0.13 + 0.090*sl 0.12 + 0.091*sl t f 0.21 0.08 + 0.065*sl 0.08 + 0.068*sl 0.07 + 0.069*sl wr to zn t plh 0.60 0.42 + 0.090*sl 0.43 + 0.086*sl 0.44 + 0.085*sl t phl 0.58 0.43 + 0.074*sl 0.45 + 0.068*sl 0.47 + 0.065*sl t r 0.31 0.14 + 0.088*sl 0.13 + 0.090*sl 0.12 + 0.091*sl t f 0.21 0.08 + 0.065*sl 0.08 + 0.068*sl 0.07 + 0.069*sl wrn to zn t plh 0.60 0.42 + 0.090*sl 0.43 + 0.086*sl 0.44 + 0.085*sl t phl 0.58 0.43 + 0.074*sl 0.45 + 0.068*sl 0.47 + 0.065*sl t r 0.31 0.14 + 0.088*sl 0.13 + 0.090*sl 0.12 + 0.091*sl t f 0.21 0.08 + 0.065*sl 0.08 + 0.068*sl 0.07 + 0.069*sl rd to zn t plh 0.26 0.18 + 0.041*sl 0.18 + 0.041*sl 0.18 + 0.041*sl t phl 0.11 0.00 + 0.055*sl 0.04 + 0.038*sl 0.07 + 0.034*sl t r 0.31 0.14 + 0.084*sl 0.13 + 0.088*sl 0.12 + 0.091*sl t f 0.29 0.15 + 0.067*sl 0.17 + 0.061*sl 0.14 + 0.065*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.33 0.32 + 0.002*sl 0.33 + 0.000*sl 0.33 + 0.000*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-388 sec asic ld1b d latch with active high, tri-state output, separate wr, wrn switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld1b path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to qn t plh 0.70 0.60 + 0.052*sl 0.60 + 0.051*sl 0.60 + 0.050*sl t phl 0.59 0.52 + 0.035*sl 0.54 + 0.028*sl 0.58 + 0.024*sl t r 0.59 0.38 + 0.102*sl 0.37 + 0.107*sl 0.35 + 0.109*sl t f 0.35 0.26 + 0.044*sl 0.26 + 0.042*sl 0.27 + 0.042*sl wr to qn t plh 0.42 0.32 + 0.052*sl 0.32 + 0.051*sl 0.33 + 0.050*sl t phl 0.42 0.35 + 0.034*sl 0.37 + 0.027*sl 0.40 + 0.024*sl t r 0.59 0.39 + 0.102*sl 0.37 + 0.107*sl 0.35 + 0.109*sl t f 0.33 0.23 + 0.045*sl 0.24 + 0.043*sl 0.25 + 0.042*sl wrn to qn t plh 0.42 0.32 + 0.052*sl 0.32 + 0.051*sl 0.33 + 0.050*sl t phl 0.42 0.35 + 0.034*sl 0.37 + 0.027*sl 0.40 + 0.024*sl t r 0.59 0.39 + 0.102*sl 0.37 + 0.107*sl 0.35 + 0.109*sl t f 0.33 0.23 + 0.045*sl 0.24 + 0.043*sl 0.25 + 0.042*sl d to zn t plh 1.10 0.88 + 0.110*sl 0.90 + 0.104*sl 0.93 + 0.101*sl t phl 0.94 0.78 + 0.085*sl 0.81 + 0.073*sl 0.86 + 0.069*sl t r 0.40 0.19 + 0.106*sl 0.18 + 0.108*sl 0.17 + 0.109*sl t f 0.25 0.11 + 0.071*sl 0.10 + 0.074*sl 0.09 + 0.075*sl wr to zn t plh 0.82 0.60 + 0.111*sl 0.62 + 0.104*sl 0.66 + 0.101*sl t phl 0.77 0.60 + 0.084*sl 0.63 + 0.073*sl 0.68 + 0.069*sl t r 0.40 0.19 + 0.106*sl 0.18 + 0.108*sl 0.17 + 0.109*sl t f 0.25 0.11 + 0.072*sl 0.10 + 0.074*sl 0.09 + 0.074*sl wrn to zn t plh 0.82 0.60 + 0.111*sl 0.62 + 0.104*sl 0.66 + 0.101*sl t phl 0.77 0.60 + 0.084*sl 0.63 + 0.073*sl 0.68 + 0.069*sl t r 0.40 0.19 + 0.106*sl 0.18 + 0.108*sl 0.17 + 0.109*sl t f 0.25 0.11 + 0.072*sl 0.10 + 0.074*sl 0.09 + 0.074*sl rd to zn t plh 0.36 0.26 + 0.050*sl 0.27 + 0.049*sl 0.26 + 0.049*sl t phl 0.15 0.05 + 0.053*sl 0.09 + 0.039*sl 0.10 + 0.037*sl t r 0.40 0.19 + 0.104*sl 0.18 + 0.108*sl 0.16 + 0.109*sl t f 0.31 0.17 + 0.070*sl 0.17 + 0.069*sl 0.13 + 0.072*sl t plz 0.20 0.20 + 0.000*sl 0.20 + 0.000*sl 0.20 + 0.000*sl t phz 0.42 0.42 + 0.000*sl 0.42 + 0.000*sl 0.42 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-389 kg80/KGM80 ld2/ld2d2 d latch with active high, reset, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 ld2 ld2d2 ld2 ld2d2 d g rn d g rn 0.9 0.9 0.9 0.9 0.9 0.9 6.0 7.0 KGM80 ld2 ld2d2 ld2 ld2d2 d g rn d g rn 1.0 1.0 1.0 1.0 1.0 1.0 6.0 7.0 parameter symbol kg80 KGM80 ld2 ld2d2 ld2 ld2d2 pulse width high (g) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 0.99 input setup time (d to g) t su 0.37 0.39 0.64 0.68 input hold time (d to g) t hd 0.15 0.15 0.33 0.33 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to g) t hd 0.26 0.20 0.41 0.41 d g q qn rn g g gb d gb g gb q qn rn g truth table d g rn q (n+1) qn (n+1) 01101 11110 x 0 1 q (n) qn (n) xx001
kg80/KGM80 3-390 sec asic ld2/ld2d2 d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.56 0.47 + 0.044*sl 0.47 + 0.042*sl 0.48 + 0.042*sl t phl 0.58 0.52 + 0.031*sl 0.53 + 0.026*sl 0.55 + 0.024*sl t r 0.29 0.12 + 0.087*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.10 + 0.041*sl 0.11 + 0.039*sl 0.09 + 0.041*sl g to q t plh 0.52 0.44 + 0.044*sl 0.44 + 0.042*sl 0.44 + 0.042*sl t phl 0.50 0.44 + 0.032*sl 0.45 + 0.026*sl 0.47 + 0.023*sl t r 0.29 0.11 + 0.087*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.040*sl 0.09 + 0.041*sl rn to q t plh 0.31 0.22 + 0.044*sl 0.23 + 0.042*sl 0.23 + 0.042*sl t phl 0.30 0.24 + 0.030*sl 0.25 + 0.025*sl 0.27 + 0.023*sl t r 0.29 0.12 + 0.085*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.10 + 0.039*sl 0.10 + 0.039*sl 0.09 + 0.041*sl d to qn t plh 0.72 0.64 + 0.040*sl 0.64 + 0.041*sl 0.64 + 0.042*sl t phl 0.64 0.58 + 0.030*sl 0.59 + 0.025*sl 0.60 + 0.023*sl t r 0.27 0.09 + 0.087*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.08 + 0.042*sl g to qn t plh 0.64 0.56 + 0.040*sl 0.56 + 0.041*sl 0.56 + 0.042*sl t phl 0.60 0.55 + 0.029*sl 0.55 + 0.025*sl 0.57 + 0.023*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.08 + 0.042*sl rn to qn t plh 0.51 0.43 + 0.042*sl 0.43 + 0.041*sl 0.44 + 0.040*sl t phl 0.39 0.33 + 0.030*sl 0.34 + 0.025*sl 0.35 + 0.023*sl t r 0.29 0.12 + 0.084*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.17 0.09 + 0.038*sl 0.09 + 0.040*sl 0.08 + 0.041*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-391 kg80/KGM80 ld2/ld2d2 d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.54 0.49 + 0.025*sl 0.50 + 0.022*sl 0.51 + 0.021*sl t phl 0.57 0.53 + 0.021*sl 0.54 + 0.016*sl 0.56 + 0.014*sl t r 0.19 0.11 + 0.041*sl 0.10 + 0.043*sl 0.10 + 0.044*sl t f 0.15 0.11 + 0.023*sl 0.11 + 0.020*sl 0.12 + 0.019*sl g to q t plh 0.51 0.46 + 0.025*sl 0.47 + 0.022*sl 0.47 + 0.021*sl t phl 0.49 0.45 + 0.022*sl 0.46 + 0.016*sl 0.48 + 0.014*sl t r 0.19 0.10 + 0.042*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.15 0.11 + 0.023*sl 0.11 + 0.020*sl 0.11 + 0.020*sl rn to q t plh 0.29 0.25 + 0.023*sl 0.25 + 0.022*sl 0.26 + 0.021*sl t phl 0.30 0.26 + 0.020*sl 0.27 + 0.015*sl 0.29 + 0.013*sl t r 0.19 0.10 + 0.042*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.14 0.10 + 0.022*sl 0.11 + 0.019*sl 0.10 + 0.019*sl d to qn t plh 0.75 0.71 + 0.019*sl 0.71 + 0.019*sl 0.70 + 0.020*sl t phl 0.68 0.64 + 0.018*sl 0.65 + 0.015*sl 0.66 + 0.013*sl t r 0.17 0.09 + 0.038*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.019*sl 0.10 + 0.019*sl 0.10 + 0.020*sl g to qn t plh 0.66 0.62 + 0.019*sl 0.62 + 0.019*sl 0.62 + 0.020*sl t phl 0.64 0.61 + 0.018*sl 0.62 + 0.014*sl 0.63 + 0.013*sl t r 0.17 0.08 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.019*sl 0.10 + 0.020*sl rn to qn t plh 0.53 0.49 + 0.023*sl 0.50 + 0.020*sl 0.49 + 0.020*sl t phl 0.43 0.39 + 0.018*sl 0.40 + 0.015*sl 0.42 + 0.013*sl t r 0.19 0.10 + 0.042*sl 0.10 + 0.042*sl 0.09 + 0.043*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.019*sl 0.10 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-392 sec asic ld2/ld2d2 d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.80 0.69 + 0.054*sl 0.70 + 0.051*sl 0.71 + 0.050*sl t phl 0.79 0.72 + 0.035*sl 0.74 + 0.027*sl 0.77 + 0.023*sl t r 0.38 0.17 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.108*sl t f 0.22 0.13 + 0.043*sl 0.14 + 0.041*sl 0.12 + 0.042*sl g to q t plh 0.74 0.63 + 0.054*sl 0.64 + 0.051*sl 0.65 + 0.050*sl t phl 0.71 0.64 + 0.036*sl 0.66 + 0.027*sl 0.70 + 0.023*sl t r 0.37 0.16 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.109*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.041*sl 0.12 + 0.042*sl rn to q t plh 0.40 0.30 + 0.053*sl 0.30 + 0.051*sl 0.31 + 0.050*sl t phl 0.39 0.32 + 0.034*sl 0.34 + 0.026*sl 0.37 + 0.023*sl t r 0.37 0.16 + 0.105*sl 0.16 + 0.107*sl 0.14 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.041*sl 0.11 + 0.042*sl d to qn t plh 0.99 0.89 + 0.049*sl 0.89 + 0.050*sl 0.89 + 0.050*sl t phl 0.93 0.86 + 0.032*sl 0.88 + 0.026*sl 0.90 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl g to qn t plh 0.91 0.81 + 0.049*sl 0.81 + 0.050*sl 0.81 + 0.050*sl t phl 0.86 0.80 + 0.032*sl 0.82 + 0.026*sl 0.84 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.041*sl 0.11 + 0.042*sl rn to qn t plh 0.67 0.57 + 0.053*sl 0.58 + 0.050*sl 0.58 + 0.050*sl t phl 0.53 0.46 + 0.032*sl 0.48 + 0.026*sl 0.51 + 0.023*sl t r 0.38 0.17 + 0.103*sl 0.17 + 0.106*sl 0.14 + 0.108*sl t f 0.20 0.11 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-393 kg80/KGM80 ld2/ld2d2 d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.78 0.71 + 0.032*sl 0.73 + 0.027*sl 0.74 + 0.025*sl t phl 0.78 0.73 + 0.025*sl 0.76 + 0.017*sl 0.79 + 0.014*sl t r 0.24 0.14 + 0.053*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.021*sl 0.15 + 0.020*sl g to q t plh 0.71 0.65 + 0.031*sl 0.66 + 0.027*sl 0.68 + 0.025*sl t phl 0.71 0.66 + 0.025*sl 0.68 + 0.017*sl 0.72 + 0.014*sl t r 0.24 0.13 + 0.053*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.18 0.13 + 0.026*sl 0.14 + 0.021*sl 0.15 + 0.020*sl rn to q t plh 0.38 0.32 + 0.031*sl 0.33 + 0.026*sl 0.34 + 0.025*sl t phl 0.39 0.34 + 0.024*sl 0.36 + 0.016*sl 0.40 + 0.013*sl t r 0.24 0.13 + 0.052*sl 0.13 + 0.052*sl 0.12 + 0.053*sl t f 0.17 0.12 + 0.024*sl 0.13 + 0.021*sl 0.14 + 0.020*sl d to qn t plh 1.02 0.98 + 0.024*sl 0.98 + 0.024*sl 0.97 + 0.025*sl t phl 0.99 0.95 + 0.021*sl 0.96 + 0.016*sl 0.99 + 0.013*sl t r 0.21 0.11 + 0.051*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.021*sl 0.13 + 0.020*sl g to qn t plh 0.95 0.90 + 0.024*sl 0.90 + 0.024*sl 0.89 + 0.025*sl t phl 0.93 0.88 + 0.020*sl 0.90 + 0.016*sl 0.93 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.021*sl 0.13 + 0.020*sl rn to qn t plh 0.71 0.65 + 0.029*sl 0.66 + 0.025*sl 0.66 + 0.025*sl t phl 0.59 0.55 + 0.020*sl 0.56 + 0.016*sl 0.59 + 0.013*sl t r 0.24 0.14 + 0.053*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.17 0.12 + 0.023*sl 0.13 + 0.021*sl 0.14 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-394 sec asic ld2q/ld2qd2 d latch with active high, reset, q output only, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 ld2q ld2qd2 ld2q ld2qd2 d g rn d g rn 0.8 0.8 0.7 0.8 0.8 0.7 6.0 7.0 KGM80 ld2q ld2qd2 ld2q ld2qd2 d g rn d g rn 0.9 0.9 0.9 0.9 0.9 0.9 6.0 7.0 parameter symbol kg80 KGM80 ld2q ld2qd2 ld2q ld2qd2 pulse width high (g) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 0.99 input setup time (d to g) t su 0.37 0.39 0.68 0.71 input hold time (d to g) t hd 0.15 0.15 0.33 0.33 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to g) t hd 0.26 0.20 0.41 0.41 d g q rn g g gb d gb g gb q rn g truth table d g rn q (n+1) 0110 1111 x 0 1 q (n) xx00
sec asic 3-395 kg80/KGM80 ld2q/ld2qd2 d latch with active high, reset, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld2q kg80 ld2qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.56 0.47 + 0.045*sl 0.48 + 0.042*sl 0.48 + 0.042*sl t phl 0.55 0.49 + 0.031*sl 0.50 + 0.026*sl 0.52 + 0.023*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.041*sl g to q t plh 0.53 0.44 + 0.045*sl 0.45 + 0.042*sl 0.45 + 0.042*sl t phl 0.47 0.40 + 0.031*sl 0.42 + 0.026*sl 0.43 + 0.023*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.08 + 0.041*sl rn to q t plh 0.30 0.21 + 0.045*sl 0.22 + 0.042*sl 0.22 + 0.041*sl t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.30 + 0.023*sl t r 0.28 0.11 + 0.085*sl 0.11 + 0.088*sl 0.09 + 0.090*sl t f 0.19 0.11 + 0.039*sl 0.11 + 0.038*sl 0.09 + 0.040*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.56 0.51 + 0.024*sl 0.52 + 0.022*sl 0.52 + 0.021*sl t phl 0.55 0.51 + 0.019*sl 0.52 + 0.015*sl 0.54 + 0.013*sl t r 0.21 0.12 + 0.042*sl 0.12 + 0.044*sl 0.11 + 0.044*sl t f 0.15 0.10 + 0.023*sl 0.11 + 0.020*sl 0.11 + 0.020*sl g to q t plh 0.52 0.48 + 0.024*sl 0.48 + 0.022*sl 0.49 + 0.021*sl t phl 0.47 0.43 + 0.019*sl 0.44 + 0.015*sl 0.45 + 0.013*sl t r 0.21 0.12 + 0.044*sl 0.12 + 0.043*sl 0.11 + 0.044*sl t f 0.15 0.10 + 0.024*sl 0.11 + 0.019*sl 0.11 + 0.020*sl rn to q t plh 0.29 0.25 + 0.024*sl 0.25 + 0.022*sl 0.26 + 0.021*sl t phl 0.33 0.29 + 0.021*sl 0.30 + 0.015*sl 0.32 + 0.013*sl t r 0.21 0.12 + 0.045*sl 0.12 + 0.043*sl 0.11 + 0.045*sl t f 0.16 0.12 + 0.021*sl 0.13 + 0.019*sl 0.13 + 0.019*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-396 sec asic ld2q/ld2qd2 d latch with active high, reset, q output only, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld2q KGM80 ld2qd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.82 0.71 + 0.055*sl 0.72 + 0.051*sl 0.73 + 0.050*sl t phl 0.75 0.67 + 0.036*sl 0.70 + 0.026*sl 0.73 + 0.023*sl t r 0.37 0.16 + 0.105*sl 0.15 + 0.107*sl 0.13 + 0.108*sl t f 0.20 0.11 + 0.045*sl 0.13 + 0.041*sl 0.12 + 0.042*sl g to q t plh 0.76 0.65 + 0.055*sl 0.67 + 0.051*sl 0.67 + 0.050*sl t phl 0.66 0.59 + 0.036*sl 0.62 + 0.026*sl 0.65 + 0.023*sl t r 0.37 0.16 + 0.105*sl 0.15 + 0.107*sl 0.13 + 0.108*sl t f 0.20 0.12 + 0.045*sl 0.13 + 0.041*sl 0.12 + 0.042*sl rn to q t plh 0.41 0.30 + 0.055*sl 0.31 + 0.050*sl 0.32 + 0.050*sl t phl 0.44 0.37 + 0.036*sl 0.39 + 0.027*sl 0.43 + 0.023*sl t r 0.36 0.15 + 0.104*sl 0.15 + 0.107*sl 0.13 + 0.108*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.040*sl 0.12 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.82 0.76 + 0.031*sl 0.77 + 0.027*sl 0.79 + 0.025*sl t phl 0.75 0.71 + 0.021*sl 0.72 + 0.016*sl 0.76 + 0.013*sl t r 0.27 0.17 + 0.053*sl 0.17 + 0.052*sl 0.16 + 0.053*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.021*sl 0.15 + 0.020*sl g to q t plh 0.76 0.70 + 0.031*sl 0.71 + 0.027*sl 0.73 + 0.025*sl t phl 0.67 0.63 + 0.022*sl 0.64 + 0.016*sl 0.68 + 0.013*sl t r 0.27 0.16 + 0.054*sl 0.17 + 0.052*sl 0.16 + 0.053*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.021*sl 0.15 + 0.020*sl rn to q t plh 0.40 0.34 + 0.030*sl 0.35 + 0.027*sl 0.36 + 0.025*sl t phl 0.44 0.40 + 0.023*sl 0.42 + 0.016*sl 0.45 + 0.013*sl t r 0.27 0.16 + 0.053*sl 0.16 + 0.052*sl 0.15 + 0.053*sl t f 0.19 0.14 + 0.025*sl 0.16 + 0.020*sl 0.17 + 0.019*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-397 kg80/KGM80 yld2/yld2d2 fast d latch with active high, reset, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 yld2 yld2d2 yld2 yld2d2 dgrndgrn 2.9 0.8 0.7 3.7 0.8 1.5 6.0 7.0 KGM80 yld2 yld2d2 yld2 yld2d2 dgrndgrn 3.7 0.9 0.9 4.6 0.9 1.7 6.0 7.0 parameter symbol kg80 KGM80 yld2 yld2d2 yld2 yld2d2 pulse width high (g) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 0.99 input setup time (d to g) t su 0.23 0.20 0.46 0.43 input hold time (d to g) t hd 0.15 0.15 0.33 0.33 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to g) t hd 0.15 0.20 0.41 0.41 d g q qn rn g g gb d gb g gb qn q rn g truth table d g rn q (n+1) qn (n+1) 01101 11110 x 0 1 q (n) qn (n) xx001
kg80/KGM80 3-398 sec asic yld2/yld2d2 fast d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 yld2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.45 0.25 + 0.100*sl 0.26 + 0.095*sl 0.26 + 0.095*sl t phl 0.41 0.26 + 0.078*sl 0.26 + 0.076*sl 0.26 + 0.076*sl t r 0.35 0.15 + 0.099*sl 0.15 + 0.100*sl 0.14 + 0.100*sl t f 0.22 0.10 + 0.060*sl 0.09 + 0.062*sl 0.09 + 0.063*sl g to q t plh 0.58 0.38 + 0.097*sl 0.39 + 0.095*sl 0.39 + 0.095*sl t phl 0.51 0.36 + 0.077*sl 0.36 + 0.077*sl 0.36 + 0.077*sl t r 0.34 0.14 + 0.099*sl 0.14 + 0.100*sl 0.14 + 0.100*sl t f 0.21 0.09 + 0.062*sl 0.09 + 0.064*sl 0.09 + 0.063*sl rn to q t plh 0.40 0.20 + 0.095*sl 0.21 + 0.095*sl 0.21 + 0.095*sl t phl 0.47 0.32 + 0.079*sl 0.32 + 0.077*sl 0.32 + 0.077*sl t r 0.34 0.15 + 0.097*sl 0.14 + 0.100*sl 0.14 + 0.100*sl t f 0.32 0.21 + 0.057*sl 0.20 + 0.060*sl 0.20 + 0.061*sl d to qn t plh 0.29 0.21 + 0.041*sl 0.21 + 0.041*sl 0.20 + 0.041*sl t phl 0.23 0.15 + 0.041*sl 0.16 + 0.035*sl 0.17 + 0.034*sl t r 0.41 0.25 + 0.079*sl 0.23 + 0.085*sl 0.21 + 0.089*sl t f 0.36 0.25 + 0.054*sl 0.23 + 0.062*sl 0.21 + 0.065*sl g to qn t plh 0.39 0.30 + 0.042*sl 0.30 + 0.042*sl 0.30 + 0.042*sl t phl 0.36 0.29 + 0.036*sl 0.29 + 0.035*sl 0.30 + 0.034*sl t r 0.37 0.19 + 0.087*sl 0.19 + 0.090*sl 0.18 + 0.091*sl t f 0.29 0.15 + 0.066*sl 0.15 + 0.068*sl 0.14 + 0.068*sl rn to qn t plh 0.29 0.21 + 0.040*sl 0.21 + 0.040*sl 0.20 + 0.041*sl t phl 0.18 0.10 + 0.038*sl 0.11 + 0.035*sl 0.12 + 0.034*sl t r 0.44 0.30 + 0.071*sl 0.29 + 0.075*sl 0.27 + 0.079*sl t f 0.32 0.21 + 0.056*sl 0.19 + 0.064*sl 0.17 + 0.067*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-399 kg80/KGM80 yld2/yld2d2 fast d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 yld2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.34 0.24 + 0.053*sl 0.25 + 0.049*sl 0.26 + 0.048*sl t phl 0.34 0.26 + 0.039*sl 0.26 + 0.038*sl 0.26 + 0.038*sl t r 0.22 0.13 + 0.049*sl 0.12 + 0.050*sl 0.12 + 0.050*sl t f 0.14 0.08 + 0.030*sl 0.08 + 0.030*sl 0.08 + 0.032*sl g to q t plh 0.49 0.39 + 0.050*sl 0.39 + 0.048*sl 0.39 + 0.048*sl t phl 0.44 0.37 + 0.039*sl 0.37 + 0.039*sl 0.37 + 0.039*sl t r 0.22 0.12 + 0.050*sl 0.12 + 0.051*sl 0.11 + 0.051*sl t f 0.14 0.08 + 0.030*sl 0.08 + 0.031*sl 0.07 + 0.032*sl rn to q t plh 0.28 0.18 + 0.050*sl 0.19 + 0.048*sl 0.19 + 0.048*sl t phl 0.36 0.28 + 0.041*sl 0.28 + 0.039*sl 0.29 + 0.039*sl t r 0.22 0.13 + 0.047*sl 0.12 + 0.050*sl 0.12 + 0.051*sl t f 0.22 0.16 + 0.028*sl 0.16 + 0.029*sl 0.16 + 0.030*sl d to qn t plh 0.26 0.22 + 0.021*sl 0.22 + 0.020*sl 0.22 + 0.021*sl t phl 0.20 0.15 + 0.023*sl 0.16 + 0.019*sl 0.17 + 0.017*sl t r 0.32 0.24 + 0.040*sl 0.24 + 0.042*sl 0.23 + 0.044*sl t f 0.30 0.25 + 0.028*sl 0.24 + 0.029*sl 0.23 + 0.031*sl g to qn t plh 0.37 0.32 + 0.021*sl 0.32 + 0.021*sl 0.32 + 0.021*sl t phl 0.35 0.31 + 0.019*sl 0.31 + 0.018*sl 0.32 + 0.017*sl t r 0.28 0.19 + 0.045*sl 0.19 + 0.045*sl 0.19 + 0.046*sl t f 0.23 0.17 + 0.031*sl 0.16 + 0.033*sl 0.16 + 0.033*sl rn to qn t plh 0.25 0.21 + 0.020*sl 0.21 + 0.020*sl 0.20 + 0.021*sl t phl 0.14 0.10 + 0.020*sl 0.10 + 0.018*sl 0.11 + 0.017*sl t r 0.37 0.30 + 0.035*sl 0.30 + 0.036*sl 0.29 + 0.037*sl t f 0.26 0.21 + 0.026*sl 0.20 + 0.030*sl 0.19 + 0.031*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-400 sec asic yld2/yld2d2 fast d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 yld2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.61 0.38 + 0.115*sl 0.39 + 0.110*sl 0.40 + 0.109*sl t phl 0.55 0.36 + 0.092*sl 0.36 + 0.092*sl 0.37 + 0.092*sl t r 0.46 0.22 + 0.117*sl 0.22 + 0.119*sl 0.22 + 0.119*sl t f 0.26 0.12 + 0.066*sl 0.12 + 0.067*sl 0.12 + 0.067*sl g to q t plh 0.78 0.56 + 0.113*sl 0.56 + 0.110*sl 0.57 + 0.109*sl t phl 0.71 0.53 + 0.093*sl 0.53 + 0.092*sl 0.53 + 0.092*sl t r 0.45 0.22 + 0.118*sl 0.22 + 0.119*sl 0.21 + 0.119*sl t f 0.25 0.12 + 0.068*sl 0.12 + 0.068*sl 0.12 + 0.068*sl rn to q t plh 0.52 0.30 + 0.112*sl 0.30 + 0.110*sl 0.31 + 0.109*sl t phl 0.60 0.41 + 0.097*sl 0.42 + 0.094*sl 0.44 + 0.092*sl t r 0.46 0.22 + 0.117*sl 0.22 + 0.119*sl 0.22 + 0.119*sl t f 0.40 0.28 + 0.061*sl 0.27 + 0.064*sl 0.26 + 0.066*sl d to qn t plh 0.38 0.28 + 0.050*sl 0.28 + 0.050*sl 0.28 + 0.050*sl t phl 0.32 0.23 + 0.045*sl 0.25 + 0.038*sl 0.26 + 0.037*sl t r 0.52 0.31 + 0.103*sl 0.30 + 0.106*sl 0.27 + 0.109*sl t f 0.42 0.28 + 0.066*sl 0.28 + 0.069*sl 0.24 + 0.072*sl g to qn t plh 0.54 0.44 + 0.051*sl 0.44 + 0.050*sl 0.45 + 0.050*sl t phl 0.50 0.41 + 0.041*sl 0.42 + 0.038*sl 0.43 + 0.037*sl t r 0.49 0.28 + 0.106*sl 0.27 + 0.109*sl 0.26 + 0.109*sl t f 0.35 0.21 + 0.072*sl 0.21 + 0.073*sl 0.19 + 0.074*sl rn to qn t plh 0.36 0.26 + 0.049*sl 0.26 + 0.050*sl 0.26 + 0.050*sl t phl 0.23 0.15 + 0.041*sl 0.16 + 0.038*sl 0.17 + 0.037*sl t r 0.57 0.38 + 0.096*sl 0.38 + 0.097*sl 0.37 + 0.098*sl t f 0.36 0.23 + 0.067*sl 0.22 + 0.072*sl 0.20 + 0.074*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-401 kg80/KGM80 yld2/yld2d2 fast d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 yld2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.49 0.36 + 0.061*sl 0.38 + 0.056*sl 0.39 + 0.055*sl t phl 0.46 0.36 + 0.047*sl 0.37 + 0.046*sl 0.37 + 0.046*sl t r 0.29 0.18 + 0.058*sl 0.18 + 0.059*sl 0.17 + 0.059*sl t f 0.17 0.11 + 0.032*sl 0.10 + 0.033*sl 0.10 + 0.033*sl g to q t plh 0.68 0.57 + 0.059*sl 0.57 + 0.056*sl 0.59 + 0.055*sl t phl 0.63 0.53 + 0.047*sl 0.53 + 0.046*sl 0.54 + 0.046*sl t r 0.29 0.17 + 0.059*sl 0.17 + 0.059*sl 0.17 + 0.059*sl t f 0.17 0.10 + 0.034*sl 0.10 + 0.033*sl 0.10 + 0.033*sl rn to q t plh 0.38 0.27 + 0.058*sl 0.27 + 0.055*sl 0.28 + 0.055*sl t phl 0.46 0.36 + 0.049*sl 0.37 + 0.047*sl 0.38 + 0.046*sl t r 0.29 0.17 + 0.059*sl 0.18 + 0.059*sl 0.17 + 0.059*sl t f 0.27 0.21 + 0.032*sl 0.21 + 0.032*sl 0.20 + 0.032*sl d to qn t plh 0.35 0.30 + 0.026*sl 0.30 + 0.025*sl 0.30 + 0.025*sl t phl 0.29 0.24 + 0.026*sl 0.25 + 0.021*sl 0.27 + 0.019*sl t r 0.41 0.30 + 0.052*sl 0.30 + 0.052*sl 0.28 + 0.053*sl t f 0.36 0.29 + 0.033*sl 0.29 + 0.033*sl 0.28 + 0.034*sl g to qn t plh 0.52 0.46 + 0.026*sl 0.47 + 0.025*sl 0.47 + 0.025*sl t phl 0.49 0.45 + 0.022*sl 0.45 + 0.020*sl 0.47 + 0.018*sl t r 0.38 0.28 + 0.053*sl 0.28 + 0.054*sl 0.27 + 0.054*sl t f 0.29 0.22 + 0.036*sl 0.22 + 0.035*sl 0.22 + 0.036*sl rn to qn t plh 0.31 0.26 + 0.025*sl 0.26 + 0.025*sl 0.26 + 0.025*sl t phl 0.19 0.14 + 0.022*sl 0.15 + 0.020*sl 0.16 + 0.018*sl t r 0.48 0.38 + 0.047*sl 0.38 + 0.047*sl 0.37 + 0.048*sl t f 0.30 0.23 + 0.033*sl 0.22 + 0.035*sl 0.21 + 0.036*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-402 sec asic ld3/ld3d2 d latch with active high, set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 ld3 ld3d2 ld3 ld3d2 d g sn d g sn 0.8 0.8 0.7 0.8 0.8 0.7 8.0 9.0 KGM80 ld3 ld3d2 ld3 ld3d2 d g sn d g sn 0.9 0.9 0.9 0.9 0.9 0.9 8.0 9.0 parameter symbol kg80 KGM80 ld3 ld3d2 ld3 ld3d2 pulse width high (g) t pwh 0.61 0.61 0.99 0.99 pulse width low (sn) t pwl 0.61 0.61 0.99 0.99 input setup time (d to g) t su 0.39 0.42 0.71 0.74 input hold time (d to g) t hd 0.15 0.15 0.33 0.33 recovery time (sn) t rc 0.15 0.15 0.33 0.33 input hold time (sn to g) t hd 0.20 0.15 0.41 0.41 d g q qn sn g g gb d gb g gb qn q sn g truth table d g sn q (n+1) qn (n+1) 01101 11110 x 0 1 q (n) qn (n) xx010
sec asic 3-403 kg80/KGM80 ld3/ld3d2 d latch with active high, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.54 0.46 + 0.040*sl 0.45 + 0.041*sl 0.45 + 0.042*sl t phl 0.65 0.59 + 0.028*sl 0.60 + 0.025*sl 0.61 + 0.023*sl t r 0.26 0.08 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl g to q t plh 0.59 0.51 + 0.040*sl 0.51 + 0.041*sl 0.51 + 0.042*sl t phl 0.59 0.53 + 0.028*sl 0.54 + 0.025*sl 0.55 + 0.023*sl t r 0.26 0.08 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl sn to q t plh 0.55 0.47 + 0.042*sl 0.47 + 0.041*sl 0.47 + 0.041*sl t phl 0.37 0.31 + 0.028*sl 0.32 + 0.025*sl 0.33 + 0.023*sl t r 0.28 0.11 + 0.085*sl 0.11 + 0.087*sl 0.09 + 0.090*sl t f 0.16 0.08 + 0.041*sl 0.08 + 0.040*sl 0.07 + 0.042*sl d to qn t plh 0.58 0.49 + 0.044*sl 0.50 + 0.042*sl 0.50 + 0.041*sl t phl 0.41 0.35 + 0.031*sl 0.36 + 0.026*sl 0.38 + 0.024*sl t r 0.28 0.11 + 0.087*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.08 + 0.041*sl g to qn t plh 0.53 0.44 + 0.045*sl 0.44 + 0.042*sl 0.45 + 0.042*sl t phl 0.47 0.40 + 0.031*sl 0.42 + 0.026*sl 0.43 + 0.024*sl t r 0.28 0.10 + 0.087*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.08 + 0.041*sl sn to qn t plh 0.30 0.21 + 0.045*sl 0.22 + 0.042*sl 0.22 + 0.042*sl t phl 0.34 0.27 + 0.032*sl 0.29 + 0.026*sl 0.30 + 0.023*sl t r 0.28 0.11 + 0.086*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.19 0.11 + 0.039*sl 0.11 + 0.039*sl 0.10 + 0.040*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-404 sec asic ld3/ld3d2 d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.56 0.53 + 0.018*sl 0.52 + 0.020*sl 0.52 + 0.021*sl t phl 0.69 0.66 + 0.016*sl 0.66 + 0.014*sl 0.67 + 0.012*sl t r 0.18 0.09 + 0.042*sl 0.09 + 0.044*sl 0.08 + 0.046*sl t f 0.14 0.10 + 0.020*sl 0.10 + 0.019*sl 0.09 + 0.020*sl g to q t plh 0.62 0.58 + 0.019*sl 0.58 + 0.020*sl 0.57 + 0.021*sl t phl 0.64 0.60 + 0.016*sl 0.61 + 0.014*sl 0.62 + 0.012*sl t r 0.18 0.09 + 0.042*sl 0.09 + 0.044*sl 0.08 + 0.046*sl t f 0.14 0.10 + 0.019*sl 0.10 + 0.019*sl 0.10 + 0.020*sl sn to q t plh 0.58 0.53 + 0.021*sl 0.54 + 0.020*sl 0.53 + 0.020*sl t phl 0.40 0.37 + 0.016*sl 0.38 + 0.014*sl 0.39 + 0.012*sl t r 0.20 0.12 + 0.043*sl 0.12 + 0.043*sl 0.11 + 0.044*sl t f 0.14 0.10 + 0.019*sl 0.10 + 0.019*sl 0.10 + 0.020*sl d to qn t plh 0.58 0.53 + 0.024*sl 0.53 + 0.022*sl 0.54 + 0.021*sl t phl 0.41 0.37 + 0.019*sl 0.38 + 0.015*sl 0.40 + 0.013*sl t r 0.20 0.12 + 0.043*sl 0.12 + 0.044*sl 0.11 + 0.045*sl t f 0.15 0.10 + 0.021*sl 0.11 + 0.020*sl 0.11 + 0.020*sl g to qn t plh 0.52 0.47 + 0.025*sl 0.48 + 0.022*sl 0.48 + 0.021*sl t phl 0.46 0.43 + 0.019*sl 0.44 + 0.015*sl 0.45 + 0.013*sl t r 0.20 0.12 + 0.044*sl 0.12 + 0.044*sl 0.11 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.021*sl 0.11 + 0.020*sl sn to qn t plh 0.29 0.24 + 0.024*sl 0.25 + 0.022*sl 0.25 + 0.021*sl t phl 0.33 0.29 + 0.020*sl 0.30 + 0.015*sl 0.32 + 0.013*sl t r 0.20 0.12 + 0.041*sl 0.12 + 0.043*sl 0.11 + 0.045*sl t f 0.16 0.12 + 0.020*sl 0.12 + 0.019*sl 0.12 + 0.019*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-405 kg80/KGM80 ld3/ld3d2 d latch with active high, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.75 0.65 + 0.049*sl 0.65 + 0.050*sl 0.65 + 0.050*sl t phl 0.92 0.85 + 0.032*sl 0.87 + 0.025*sl 0.89 + 0.023*sl t r 0.33 0.12 + 0.105*sl 0.11 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.041*sl 0.09 + 0.043*sl g to q t plh 0.84 0.75 + 0.049*sl 0.74 + 0.050*sl 0.75 + 0.050*sl t phl 0.87 0.80 + 0.031*sl 0.82 + 0.025*sl 0.84 + 0.023*sl t r 0.33 0.12 + 0.105*sl 0.11 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.042*sl 0.10 + 0.041*sl 0.09 + 0.043*sl sn to q t plh 0.73 0.62 + 0.054*sl 0.63 + 0.050*sl 0.63 + 0.050*sl t phl 0.51 0.45 + 0.032*sl 0.47 + 0.025*sl 0.49 + 0.023*sl t r 0.37 0.16 + 0.103*sl 0.16 + 0.106*sl 0.13 + 0.108*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.041*sl 0.09 + 0.043*sl d to qn t plh 0.81 0.70 + 0.055*sl 0.71 + 0.051*sl 0.72 + 0.050*sl t phl 0.57 0.50 + 0.035*sl 0.52 + 0.027*sl 0.56 + 0.024*sl t r 0.37 0.16 + 0.105*sl 0.15 + 0.107*sl 0.13 + 0.108*sl t f 0.20 0.11 + 0.045*sl 0.12 + 0.041*sl 0.12 + 0.042*sl g to qn t plh 0.76 0.65 + 0.054*sl 0.66 + 0.051*sl 0.67 + 0.050*sl t phl 0.66 0.59 + 0.035*sl 0.62 + 0.027*sl 0.65 + 0.024*sl t r 0.36 0.15 + 0.105*sl 0.15 + 0.107*sl 0.13 + 0.108*sl t f 0.20 0.11 + 0.046*sl 0.12 + 0.041*sl 0.12 + 0.042*sl sn to qn t plh 0.41 0.30 + 0.055*sl 0.31 + 0.051*sl 0.32 + 0.050*sl t phl 0.44 0.37 + 0.037*sl 0.39 + 0.027*sl 0.43 + 0.023*sl t r 0.36 0.15 + 0.105*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.22 0.13 + 0.043*sl 0.14 + 0.040*sl 0.13 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-406 sec asic ld3/ld3d2 d latch with active high, reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld3d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.79 0.75 + 0.023*sl 0.75 + 0.024*sl 0.74 + 0.025*sl t phl 0.99 0.95 + 0.018*sl 0.96 + 0.015*sl 0.98 + 0.012*sl t r 0.24 0.13 + 0.051*sl 0.13 + 0.053*sl 0.11 + 0.054*sl t f 0.17 0.12 + 0.023*sl 0.13 + 0.020*sl 0.13 + 0.020*sl g to q t plh 0.89 0.84 + 0.023*sl 0.84 + 0.024*sl 0.83 + 0.025*sl t phl 0.93 0.90 + 0.018*sl 0.91 + 0.015*sl 0.93 + 0.012*sl t r 0.23 0.13 + 0.050*sl 0.13 + 0.053*sl 0.11 + 0.054*sl t f 0.17 0.12 + 0.023*sl 0.13 + 0.020*sl 0.13 + 0.020*sl sn to q t plh 0.77 0.71 + 0.028*sl 0.72 + 0.025*sl 0.73 + 0.024*sl t phl 0.57 0.54 + 0.019*sl 0.55 + 0.015*sl 0.57 + 0.012*sl t r 0.27 0.16 + 0.053*sl 0.17 + 0.051*sl 0.15 + 0.053*sl t f 0.17 0.13 + 0.022*sl 0.13 + 0.020*sl 0.13 + 0.020*sl d to qn t plh 0.81 0.75 + 0.030*sl 0.76 + 0.026*sl 0.77 + 0.025*sl t phl 0.58 0.53 + 0.022*sl 0.55 + 0.016*sl 0.58 + 0.013*sl t r 0.27 0.16 + 0.053*sl 0.17 + 0.052*sl 0.15 + 0.053*sl t f 0.17 0.13 + 0.024*sl 0.13 + 0.021*sl 0.15 + 0.020*sl g to qn t plh 0.76 0.70 + 0.030*sl 0.71 + 0.026*sl 0.72 + 0.025*sl t phl 0.67 0.63 + 0.022*sl 0.64 + 0.016*sl 0.67 + 0.013*sl t r 0.27 0.16 + 0.054*sl 0.17 + 0.052*sl 0.15 + 0.053*sl t f 0.17 0.13 + 0.024*sl 0.13 + 0.021*sl 0.15 + 0.020*sl sn to qn t plh 0.40 0.34 + 0.030*sl 0.35 + 0.026*sl 0.36 + 0.025*sl t phl 0.44 0.40 + 0.023*sl 0.42 + 0.016*sl 0.45 + 0.013*sl t r 0.26 0.16 + 0.052*sl 0.16 + 0.052*sl 0.15 + 0.053*sl t f 0.19 0.14 + 0.024*sl 0.15 + 0.020*sl 0.16 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-407 kg80/KGM80 ld4/ld4d2 d latch with active high, reset, set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 ld4 ld4d2 ld4 ld4d2 d g sn rn d g sn rn 0.8 0.8 0.7 0.8 0.8 0.8 0.7 0.8 7.0 8.0 KGM80 ld4 ld4d2 ld4 ld4d2 d g sn rn d g sn rn 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 7.0 8.0 parameter symbol kg80 KGM80 ld4 ld4d2 ld4 ld4d2 pulse width high (g) t pwh 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 0.99 pulse width low (sn) t pwl 0.61 0.61 0.99 0.99 input setup time (d to g) t su 0.42 0.45 0.77 0.80 input hold time (d to g) t hd 0.15 0.15 0.33 0.33 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to g) t hd 0.15 0.15 0.41 0.41 recovery time (sn) t rc 0.15 0.15 0.33 0.33 input hold time (sn to g) t hd 0.31 0.26 0.63 0.63 d g q qn sn rn g g gb d gb g gb qn q g sn rn rn rn sn sn truth table d g rn sn q (n+1) qn (n+1) 011101 111110 x 0 1 1 q (n) qn (n) xx1010 xx0101 xx0010
kg80/KGM80 3-408 sec asic ld4/ld4d2 d latch with active high, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.73 0.65 + 0.040*sl 0.65 + 0.041*sl 0.65 + 0.042*sl t phl 0.77 0.71 + 0.030*sl 0.73 + 0.025*sl 0.74 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.041*sl 0.08 + 0.040*sl 0.07 + 0.041*sl g to q t plh 0.70 0.62 + 0.041*sl 0.62 + 0.041*sl 0.62 + 0.042*sl t phl 0.69 0.63 + 0.031*sl 0.64 + 0.025*sl 0.65 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.042*sl 0.09 + 0.040*sl 0.07 + 0.041*sl sn to q t plh 0.47 0.38 + 0.040*sl 0.38 + 0.041*sl 0.38 + 0.042*sl t phl 0.37 0.31 + 0.030*sl 0.33 + 0.025*sl 0.34 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.07 + 0.041*sl rn to q t plh 0.48 0.40 + 0.041*sl 0.39 + 0.041*sl 0.39 + 0.042*sl t phl 0.56 0.51 + 0.027*sl 0.51 + 0.025*sl 0.52 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl d to qn t plh 0.70 0.61 + 0.044*sl 0.62 + 0.042*sl 0.62 + 0.042*sl t phl 0.61 0.54 + 0.031*sl 0.56 + 0.026*sl 0.57 + 0.024*sl t r 0.28 0.10 + 0.086*sl 0.10 + 0.089*sl 0.09 + 0.090*sl t f 0.17 0.08 + 0.044*sl 0.09 + 0.039*sl 0.08 + 0.041*sl g to qn t plh 0.62 0.53 + 0.045*sl 0.53 + 0.042*sl 0.54 + 0.042*sl t phl 0.57 0.51 + 0.031*sl 0.52 + 0.026*sl 0.54 + 0.023*sl t r 0.28 0.10 + 0.086*sl 0.10 + 0.089*sl 0.09 + 0.090*sl t f 0.17 0.08 + 0.043*sl 0.09 + 0.040*sl 0.08 + 0.042*sl sn to qn t plh 0.30 0.21 + 0.044*sl 0.22 + 0.042*sl 0.22 + 0.042*sl t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.31 + 0.024*sl t r 0.28 0.11 + 0.086*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.039*sl 0.10 + 0.041*sl rn to qn t plh 0.49 0.41 + 0.042*sl 0.40 + 0.042*sl 0.41 + 0.042*sl t phl 0.35 0.29 + 0.031*sl 0.30 + 0.026*sl 0.32 + 0.024*sl t r 0.28 0.10 + 0.088*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.08 + 0.043*sl 0.09 + 0.040*sl 0.08 + 0.041*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-409 kg80/KGM80 ld4/ld4d2 d latch with active high, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.76 0.72 + 0.019*sl 0.72 + 0.020*sl 0.71 + 0.021*sl t phl 0.81 0.78 + 0.017*sl 0.79 + 0.014*sl 0.80 + 0.012*sl t r 0.18 0.09 + 0.043*sl 0.09 + 0.044*sl 0.08 + 0.045*sl t f 0.14 0.10 + 0.021*sl 0.11 + 0.019*sl 0.11 + 0.019*sl g to q t plh 0.73 0.69 + 0.020*sl 0.69 + 0.020*sl 0.68 + 0.021*sl t phl 0.73 0.69 + 0.018*sl 0.70 + 0.014*sl 0.72 + 0.012*sl t r 0.18 0.10 + 0.041*sl 0.09 + 0.044*sl 0.08 + 0.045*sl t f 0.14 0.10 + 0.021*sl 0.11 + 0.019*sl 0.11 + 0.019*sl sn to q t plh 0.49 0.45 + 0.019*sl 0.45 + 0.020*sl 0.44 + 0.021*sl t phl 0.41 0.38 + 0.018*sl 0.39 + 0.014*sl 0.39 + 0.013*sl t r 0.18 0.10 + 0.043*sl 0.09 + 0.044*sl 0.08 + 0.045*sl t f 0.15 0.11 + 0.018*sl 0.11 + 0.020*sl 0.11 + 0.019*sl rn to q t plh 0.50 0.46 + 0.019*sl 0.46 + 0.020*sl 0.46 + 0.021*sl t phl 0.60 0.57 + 0.016*sl 0.57 + 0.014*sl 0.59 + 0.012*sl t r 0.18 0.10 + 0.043*sl 0.09 + 0.044*sl 0.08 + 0.045*sl t f 0.14 0.10 + 0.020*sl 0.10 + 0.019*sl 0.10 + 0.020*sl d to qn t plh 0.69 0.65 + 0.024*sl 0.65 + 0.022*sl 0.65 + 0.021*sl t phl 0.61 0.57 + 0.019*sl 0.58 + 0.015*sl 0.59 + 0.013*sl t r 0.20 0.12 + 0.042*sl 0.11 + 0.044*sl 0.11 + 0.045*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.021*sl 0.11 + 0.019*sl g to qn t plh 0.61 0.56 + 0.024*sl 0.56 + 0.022*sl 0.57 + 0.021*sl t phl 0.57 0.53 + 0.019*sl 0.54 + 0.015*sl 0.56 + 0.013*sl t r 0.20 0.11 + 0.043*sl 0.11 + 0.044*sl 0.10 + 0.045*sl t f 0.14 0.10 + 0.022*sl 0.10 + 0.020*sl 0.11 + 0.020*sl sn to qn t plh 0.29 0.24 + 0.025*sl 0.25 + 0.021*sl 0.25 + 0.021*sl t phl 0.33 0.29 + 0.021*sl 0.30 + 0.016*sl 0.32 + 0.014*sl t r 0.20 0.12 + 0.040*sl 0.11 + 0.044*sl 0.11 + 0.045*sl t f 0.16 0.12 + 0.022*sl 0.12 + 0.020*sl 0.13 + 0.019*sl rn to qn t plh 0.48 0.43 + 0.024*sl 0.44 + 0.022*sl 0.45 + 0.021*sl t phl 0.35 0.31 + 0.019*sl 0.32 + 0.015*sl 0.33 + 0.013*sl t r 0.20 0.12 + 0.043*sl 0.11 + 0.044*sl 0.11 + 0.045*sl t f 0.15 0.10 + 0.023*sl 0.11 + 0.020*sl 0.11 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-410 sec asic ld4/ld4d2 d latch with active high, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 1.08 0.98 + 0.050*sl 0.98 + 0.050*sl 0.98 + 0.050*sl t phl 1.07 1.00 + 0.033*sl 1.02 + 0.026*sl 1.05 + 0.023*sl t r 0.34 0.13 + 0.105*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.041*sl 0.10 + 0.042*sl g to q t plh 1.02 0.92 + 0.050*sl 0.92 + 0.050*sl 0.92 + 0.050*sl t phl 0.99 0.92 + 0.033*sl 0.94 + 0.026*sl 0.97 + 0.023*sl t r 0.34 0.13 + 0.105*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.042*sl 0.11 + 0.041*sl 0.10 + 0.042*sl sn to q t plh 0.62 0.52 + 0.049*sl 0.52 + 0.050*sl 0.52 + 0.050*sl t phl 0.52 0.45 + 0.033*sl 0.47 + 0.026*sl 0.50 + 0.023*sl t r 0.34 0.13 + 0.105*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.11 + 0.041*sl 0.10 + 0.042*sl rn to q t plh 0.67 0.57 + 0.050*sl 0.57 + 0.050*sl 0.58 + 0.050*sl t phl 0.77 0.70 + 0.032*sl 0.72 + 0.026*sl 0.74 + 0.023*sl t r 0.34 0.13 + 0.105*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl d to qn t plh 0.96 0.85 + 0.054*sl 0.86 + 0.051*sl 0.87 + 0.050*sl t phl 0.90 0.83 + 0.035*sl 0.85 + 0.027*sl 0.88 + 0.023*sl t r 0.36 0.15 + 0.105*sl 0.14 + 0.107*sl 0.13 + 0.109*sl t f 0.20 0.11 + 0.045*sl 0.12 + 0.041*sl 0.12 + 0.042*sl g to qn t plh 0.88 0.77 + 0.054*sl 0.78 + 0.051*sl 0.79 + 0.050*sl t phl 0.84 0.77 + 0.035*sl 0.79 + 0.027*sl 0.83 + 0.023*sl t r 0.36 0.15 + 0.105*sl 0.14 + 0.107*sl 0.13 + 0.109*sl t f 0.20 0.11 + 0.045*sl 0.12 + 0.041*sl 0.12 + 0.042*sl sn to qn t plh 0.41 0.30 + 0.054*sl 0.31 + 0.051*sl 0.32 + 0.050*sl t phl 0.44 0.37 + 0.037*sl 0.39 + 0.027*sl 0.43 + 0.024*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.107*sl 0.13 + 0.109*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.041*sl 0.13 + 0.042*sl rn to qn t plh 0.66 0.55 + 0.054*sl 0.56 + 0.051*sl 0.57 + 0.050*sl t phl 0.49 0.43 + 0.035*sl 0.45 + 0.027*sl 0.48 + 0.023*sl t r 0.36 0.15 + 0.105*sl 0.14 + 0.107*sl 0.13 + 0.109*sl t f 0.20 0.12 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-411 kg80/KGM80 ld4/ld4d2 d latch with active high, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 1.12 1.07 + 0.023*sl 1.07 + 0.024*sl 1.06 + 0.025*sl t phl 1.13 1.09 + 0.019*sl 1.10 + 0.015*sl 1.13 + 0.013*sl t r 0.24 0.14 + 0.051*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.17 0.13 + 0.024*sl 0.14 + 0.020*sl 0.14 + 0.020*sl g to q t plh 1.06 1.01 + 0.024*sl 1.01 + 0.024*sl 1.01 + 0.025*sl t phl 1.05 1.01 + 0.019*sl 1.02 + 0.015*sl 1.05 + 0.013*sl t r 0.24 0.13 + 0.052*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.17 0.13 + 0.024*sl 0.14 + 0.020*sl 0.14 + 0.020*sl sn to q t plh 0.66 0.62 + 0.023*sl 0.62 + 0.024*sl 0.61 + 0.025*sl t phl 0.58 0.54 + 0.019*sl 0.55 + 0.015*sl 0.58 + 0.012*sl t r 0.24 0.14 + 0.051*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.020*sl 0.14 + 0.020*sl rn to q t plh 0.72 0.67 + 0.023*sl 0.67 + 0.024*sl 0.66 + 0.025*sl t phl 0.83 0.79 + 0.019*sl 0.80 + 0.015*sl 0.83 + 0.013*sl t r 0.24 0.14 + 0.051*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.17 0.13 + 0.023*sl 0.13 + 0.020*sl 0.13 + 0.020*sl d to qn t plh 0.95 0.89 + 0.030*sl 0.90 + 0.026*sl 0.91 + 0.025*sl t phl 0.90 0.86 + 0.022*sl 0.88 + 0.016*sl 0.91 + 0.013*sl t r 0.26 0.16 + 0.052*sl 0.16 + 0.053*sl 0.15 + 0.053*sl t f 0.17 0.13 + 0.025*sl 0.13 + 0.021*sl 0.15 + 0.020*sl g to qn t plh 0.86 0.80 + 0.030*sl 0.81 + 0.026*sl 0.83 + 0.025*sl t phl 0.85 0.80 + 0.021*sl 0.82 + 0.016*sl 0.85 + 0.013*sl t r 0.26 0.16 + 0.053*sl 0.16 + 0.052*sl 0.15 + 0.053*sl t f 0.17 0.13 + 0.023*sl 0.13 + 0.021*sl 0.14 + 0.020*sl sn to qn t plh 0.39 0.33 + 0.030*sl 0.34 + 0.026*sl 0.36 + 0.025*sl t phl 0.44 0.40 + 0.023*sl 0.42 + 0.017*sl 0.45 + 0.013*sl t r 0.26 0.16 + 0.053*sl 0.16 + 0.052*sl 0.15 + 0.053*sl t f 0.19 0.15 + 0.024*sl 0.15 + 0.021*sl 0.17 + 0.020*sl rn to qn t plh 0.65 0.59 + 0.030*sl 0.60 + 0.026*sl 0.61 + 0.025*sl t phl 0.50 0.46 + 0.022*sl 0.47 + 0.016*sl 0.51 + 0.013*sl t r 0.26 0.16 + 0.052*sl 0.16 + 0.053*sl 0.15 + 0.053*sl t f 0.18 0.13 + 0.024*sl 0.14 + 0.021*sl 0.15 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-412 sec asic ld5/ld5d2 d latch with active low, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 ld5 ld5d2 ld5 ld5d2 dgndgn 0.9 0.9 0.9 0.9 5.0 6.0 KGM80 ld5 ld5d2 ld5 ld5d2 dgndgn 1.0 1.0 1.0 1.0 5.0 6.0 parameter symbol kg80 KGM80 ld5 ld5d2 ld5 ld5d2 pulse width low (gn) t pwl 0.61 0.61 0.99 0.99 input setup time (d to gn) t su 0.37 0.39 0.68 0.71 input hold time (d to gn) t hd 0.15 0.15 0.33 0.33 d gn q qn qn q d gnb gn gn gnb gn gn gnb truth table d gn q (n+1) qn (n+1) 0001 1010 x 1 q (n) qn (n)
sec asic 3-413 kg80/KGM80 ld5/ld5d2 d latch with active low, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld5 kg80 ld5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.54 0.46 + 0.040*sl 0.45 + 0.041*sl 0.45 + 0.042*sl t phl 0.60 0.54 + 0.030*sl 0.55 + 0.025*sl 0.56 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.041*sl 0.07 + 0.042*sl gn to q t plh 0.66 0.58 + 0.040*sl 0.58 + 0.041*sl 0.58 + 0.042*sl t phl 0.66 0.60 + 0.029*sl 0.61 + 0.024*sl 0.62 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl d to qn t plh 0.52 0.44 + 0.042*sl 0.44 + 0.042*sl 0.44 + 0.042*sl t phl 0.40 0.34 + 0.030*sl 0.35 + 0.026*sl 0.37 + 0.023*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.17 0.09 + 0.039*sl 0.09 + 0.040*sl 0.08 + 0.041*sl gn to qn t plh 0.58 0.50 + 0.042*sl 0.50 + 0.041*sl 0.49 + 0.042*sl t phl 0.53 0.46 + 0.031*sl 0.48 + 0.026*sl 0.49 + 0.023*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.08 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.57 0.53 + 0.019*sl 0.53 + 0.019*sl 0.52 + 0.020*sl t phl 0.63 0.60 + 0.018*sl 0.60 + 0.015*sl 0.62 + 0.013*sl t r 0.16 0.08 + 0.042*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.022*sl 0.10 + 0.020*sl 0.09 + 0.020*sl gn to q t plh 0.69 0.65 + 0.019*sl 0.65 + 0.019*sl 0.64 + 0.020*sl t phl 0.69 0.66 + 0.018*sl 0.67 + 0.015*sl 0.68 + 0.013*sl t r 0.16 0.09 + 0.040*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.022*sl 0.10 + 0.020*sl 0.09 + 0.020*sl d to qn t plh 0.50 0.46 + 0.023*sl 0.46 + 0.021*sl 0.46 + 0.021*sl t phl 0.40 0.36 + 0.020*sl 0.37 + 0.015*sl 0.39 + 0.013*sl t r 0.17 0.09 + 0.039*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.020*sl gn to qn t plh 0.56 0.52 + 0.023*sl 0.52 + 0.021*sl 0.52 + 0.021*sl t phl 0.52 0.48 + 0.021*sl 0.50 + 0.015*sl 0.51 + 0.013*sl t r 0.17 0.09 + 0.038*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.09 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-414 sec asic ld5/ld5d2 d latch with active low, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld5 KGM80 ld5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.74 0.64 + 0.049*sl 0.64 + 0.050*sl 0.64 + 0.050*sl t phl 0.83 0.77 + 0.033*sl 0.79 + 0.026*sl 0.81 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl gn to q t plh 0.90 0.80 + 0.049*sl 0.80 + 0.050*sl 0.80 + 0.050*sl t phl 0.92 0.85 + 0.033*sl 0.87 + 0.026*sl 0.90 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl d to qn t plh 0.71 0.61 + 0.051*sl 0.61 + 0.050*sl 0.62 + 0.050*sl t phl 0.55 0.48 + 0.034*sl 0.50 + 0.026*sl 0.53 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.045*sl 0.12 + 0.041*sl 0.11 + 0.042*sl gn to qn t plh 0.80 0.70 + 0.051*sl 0.70 + 0.050*sl 0.70 + 0.050*sl t phl 0.71 0.64 + 0.034*sl 0.66 + 0.026*sl 0.69 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.79 0.74 + 0.025*sl 0.74 + 0.024*sl 0.73 + 0.025*sl t phl 0.89 0.85 + 0.021*sl 0.86 + 0.016*sl 0.89 + 0.013*sl t r 0.21 0.11 + 0.051*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.021*sl gn to q t plh 0.95 0.90 + 0.025*sl 0.90 + 0.024*sl 0.89 + 0.025*sl t phl 0.97 0.93 + 0.021*sl 0.95 + 0.016*sl 0.98 + 0.013*sl t r 0.21 0.11 + 0.051*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.026*sl 0.12 + 0.021*sl 0.13 + 0.021*sl d to qn t plh 0.69 0.63 + 0.028*sl 0.64 + 0.025*sl 0.64 + 0.025*sl t phl 0.55 0.51 + 0.023*sl 0.53 + 0.016*sl 0.56 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.021*sl gn to qn t plh 0.77 0.72 + 0.028*sl 0.72 + 0.025*sl 0.73 + 0.025*sl t phl 0.71 0.67 + 0.023*sl 0.68 + 0.016*sl 0.72 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.022*sl 0.13 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-415 kg80/KGM80 ld5s/ld5sd2 d latch with active low, scan, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 ld5s ld5sd2 ld5s ld5sd2 d gn si sg d gn si sg 0.6 0.9 0.8 1.8 0.6 0.9 0.8 1.8 7.0 8.0 KGM80 ld5s ld5sd2 ld5s ld5sd2 d gn si sg d gn si sg 1.0 1.1 1.0 2.1 1.0 1.1 1.0 2.1 7.0 8.0 parameter symbol kg80 KGM80 ld5s ld5sd2 ld5s ld5sd2 pulse width low (gn) t pwl 0.61 0.61 0.99 0.99 pulse width high (sg) t pwh 0.61 0.61 0.99 0.99 input setup time (d to gn) t su 0.37 0.39 0.68 0.74 input hold time (d to gn) t hd 0.15 0.15 0.33 0.33 input setup time (si to sg) t su 0.37 0.39 0.68 0.74 input hold time (si to sg) t hd 0.15 0.15 0.33 0.33 q qn d gn si sg sg gn si d qn q truth table dgnsisg q (n+1) qn (n+1) x 1 x 0 q (n) qn (n) xx1110 x10101 10xx10 00x001 000101
kg80/KGM80 3-416 sec asic ld5s/ld5sd2 d latch with active low, scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld5s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.63 0.55 + 0.040*sl 0.54 + 0.041*sl 0.54 + 0.042*sl t phl 0.67 0.61 + 0.029*sl 0.62 + 0.025*sl 0.63 + 0.023*sl t r 0.26 0.09 + 0.085*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl si to q t plh 0.70 0.62 + 0.040*sl 0.62 + 0.041*sl 0.62 + 0.042*sl t phl 0.71 0.66 + 0.030*sl 0.67 + 0.025*sl 0.68 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl gn to q t plh 0.86 0.78 + 0.040*sl 0.77 + 0.041*sl 0.77 + 0.042*sl t phl 0.76 0.70 + 0.030*sl 0.71 + 0.025*sl 0.72 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.041*sl 0.08 + 0.040*sl 0.07 + 0.042*sl sg to q t plh 0.72 0.64 + 0.040*sl 0.63 + 0.041*sl 0.63 + 0.042*sl t phl 0.57 0.51 + 0.029*sl 0.52 + 0.025*sl 0.53 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.041*sl 0.07 + 0.042*sl d to qn t plh 0.59 0.51 + 0.042*sl 0.51 + 0.041*sl 0.51 + 0.042*sl t phl 0.49 0.43 + 0.031*sl 0.44 + 0.026*sl 0.46 + 0.023*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.089*sl 0.09 + 0.090*sl t f 0.18 0.09 + 0.041*sl 0.10 + 0.040*sl 0.09 + 0.041*sl si to qn t plh 0.64 0.55 + 0.042*sl 0.56 + 0.041*sl 0.56 + 0.041*sl t phl 0.57 0.50 + 0.031*sl 0.52 + 0.026*sl 0.53 + 0.023*sl t r 0.28 0.11 + 0.086*sl 0.10 + 0.089*sl 0.09 + 0.090*sl t f 0.18 0.10 + 0.041*sl 0.10 + 0.039*sl 0.09 + 0.041*sl gn to qn t plh 0.68 0.60 + 0.042*sl 0.60 + 0.042*sl 0.60 + 0.042*sl t phl 0.72 0.66 + 0.030*sl 0.67 + 0.026*sl 0.69 + 0.023*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.18 0.09 + 0.041*sl 0.10 + 0.039*sl 0.08 + 0.041*sl sg to qn t plh 0.50 0.41 + 0.042*sl 0.41 + 0.042*sl 0.41 + 0.042*sl t phl 0.58 0.52 + 0.031*sl 0.53 + 0.026*sl 0.55 + 0.023*sl t r 0.27 0.10 + 0.087*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.18 0.09 + 0.041*sl 0.10 + 0.040*sl 0.08 + 0.041*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-417 kg80/KGM80 ld5s/ld5sd2 d latch with active low, scan, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld5sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.66 0.62 + 0.020*sl 0.62 + 0.019*sl 0.61 + 0.020*sl t phl 0.71 0.67 + 0.018*sl 0.68 + 0.015*sl 0.69 + 0.013*sl t r 0.16 0.09 + 0.038*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.023*sl 0.10 + 0.019*sl 0.09 + 0.020*sl si to q t plh 0.73 0.69 + 0.019*sl 0.69 + 0.019*sl 0.69 + 0.020*sl t phl 0.76 0.72 + 0.018*sl 0.73 + 0.015*sl 0.74 + 0.013*sl t r 0.16 0.08 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.021*sl 0.10 + 0.020*sl 0.09 + 0.020*sl gn to q t plh 0.89 0.85 + 0.019*sl 0.85 + 0.019*sl 0.84 + 0.020*sl t phl 0.79 0.76 + 0.018*sl 0.76 + 0.015*sl 0.78 + 0.013*sl t r 0.16 0.08 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.023*sl 0.10 + 0.019*sl 0.09 + 0.020*sl sg to q t plh 0.75 0.71 + 0.019*sl 0.71 + 0.019*sl 0.70 + 0.020*sl t phl 0.61 0.57 + 0.018*sl 0.58 + 0.015*sl 0.59 + 0.013*sl t r 0.17 0.09 + 0.039*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.021*sl 0.09 + 0.020*sl 0.09 + 0.020*sl d to qn t plh 0.58 0.53 + 0.023*sl 0.54 + 0.021*sl 0.54 + 0.021*sl t phl 0.49 0.45 + 0.020*sl 0.46 + 0.015*sl 0.47 + 0.014*sl t r 0.17 0.10 + 0.037*sl 0.09 + 0.043*sl 0.08 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.11 + 0.020*sl si to qn t plh 0.62 0.58 + 0.023*sl 0.58 + 0.021*sl 0.58 + 0.021*sl t phl 0.56 0.52 + 0.021*sl 0.54 + 0.015*sl 0.55 + 0.013*sl t r 0.18 0.10 + 0.039*sl 0.09 + 0.043*sl 0.08 + 0.044*sl t f 0.15 0.10 + 0.021*sl 0.11 + 0.020*sl 0.11 + 0.020*sl gn to qn t plh 0.66 0.62 + 0.023*sl 0.62 + 0.021*sl 0.62 + 0.021*sl t phl 0.72 0.68 + 0.021*sl 0.69 + 0.015*sl 0.71 + 0.013*sl t r 0.17 0.09 + 0.042*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.11 + 0.020*sl sg to qn t plh 0.48 0.43 + 0.023*sl 0.44 + 0.021*sl 0.44 + 0.021*sl t phl 0.58 0.54 + 0.020*sl 0.55 + 0.016*sl 0.57 + 0.013*sl t r 0.17 0.08 + 0.043*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.11 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-418 sec asic ld5s/ld5sd2 d latch with active low, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld5s path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.87 0.77 + 0.049*sl 0.77 + 0.050*sl 0.77 + 0.050*sl t phl 0.97 0.90 + 0.033*sl 0.92 + 0.026*sl 0.95 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.044*sl 0.11 + 0.041*sl 0.10 + 0.042*sl si to q t plh 0.97 0.87 + 0.049*sl 0.87 + 0.050*sl 0.87 + 0.050*sl t phl 1.07 1.00 + 0.033*sl 1.02 + 0.026*sl 1.05 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl gn to q t plh 1.19 1.09 + 0.049*sl 1.08 + 0.050*sl 1.08 + 0.050*sl t phl 1.06 0.99 + 0.032*sl 1.01 + 0.026*sl 1.04 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl sg to q t plh 1.00 0.90 + 0.049*sl 0.90 + 0.050*sl 0.90 + 0.050*sl t phl 0.81 0.75 + 0.033*sl 0.77 + 0.026*sl 0.79 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl d to qn t plh 0.85 0.75 + 0.051*sl 0.75 + 0.050*sl 0.75 + 0.050*sl t phl 0.68 0.61 + 0.034*sl 0.63 + 0.026*sl 0.66 + 0.023*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.108*sl 0.13 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.12 + 0.042*sl si to qn t plh 0.95 0.85 + 0.051*sl 0.85 + 0.050*sl 0.85 + 0.050*sl t phl 0.77 0.70 + 0.035*sl 0.73 + 0.026*sl 0.76 + 0.023*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.107*sl 0.13 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.041*sl 0.12 + 0.042*sl gn to qn t plh 0.94 0.84 + 0.051*sl 0.84 + 0.050*sl 0.84 + 0.050*sl t phl 0.99 0.92 + 0.034*sl 0.94 + 0.026*sl 0.98 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.12 + 0.042*sl sg to qn t plh 0.69 0.59 + 0.051*sl 0.59 + 0.050*sl 0.60 + 0.050*sl t phl 0.80 0.73 + 0.035*sl 0.76 + 0.026*sl 0.79 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.041*sl 0.12 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-419 kg80/KGM80 ld5s/ld5sd2 d latch with active low, scan, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld5sd2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.92 0.87 + 0.024*sl 0.87 + 0.024*sl 0.86 + 0.025*sl t phl 1.03 0.99 + 0.021*sl 1.01 + 0.016*sl 1.03 + 0.013*sl t r 0.21 0.11 + 0.050*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.021*sl si to q t plh 1.01 0.97 + 0.024*sl 0.97 + 0.024*sl 0.96 + 0.025*sl t phl 1.13 1.09 + 0.021*sl 1.11 + 0.016*sl 1.14 + 0.013*sl t r 0.21 0.11 + 0.051*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.021*sl gn to q t plh 1.23 1.18 + 0.024*sl 1.19 + 0.024*sl 1.18 + 0.025*sl t phl 1.11 1.07 + 0.021*sl 1.09 + 0.016*sl 1.12 + 0.013*sl t r 0.21 0.11 + 0.051*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.020*sl sg to q t plh 1.04 1.00 + 0.024*sl 1.00 + 0.024*sl 0.99 + 0.025*sl t phl 0.87 0.83 + 0.021*sl 0.84 + 0.016*sl 0.87 + 0.013*sl t r 0.21 0.11 + 0.050*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.021*sl d to qn t plh 0.83 0.77 + 0.029*sl 0.78 + 0.025*sl 0.79 + 0.025*sl t phl 0.68 0.64 + 0.023*sl 0.66 + 0.017*sl 0.69 + 0.013*sl t r 0.23 0.13 + 0.050*sl 0.12 + 0.052*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.021*sl 0.14 + 0.020*sl si to qn t plh 0.93 0.88 + 0.029*sl 0.88 + 0.025*sl 0.89 + 0.025*sl t phl 0.78 0.73 + 0.024*sl 0.75 + 0.017*sl 0.79 + 0.013*sl t r 0.23 0.13 + 0.050*sl 0.12 + 0.052*sl 0.11 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.021*sl 0.14 + 0.020*sl gn to qn t plh 0.91 0.86 + 0.028*sl 0.87 + 0.025*sl 0.87 + 0.025*sl t phl 1.00 0.95 + 0.024*sl 0.97 + 0.017*sl 1.00 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.021*sl 0.14 + 0.020*sl sg to qn t plh 0.67 0.61 + 0.028*sl 0.62 + 0.025*sl 0.62 + 0.025*sl t phl 0.81 0.76 + 0.024*sl 0.78 + 0.017*sl 0.82 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.021*sl 0.14 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-420 sec asic ld5x4/ld5xd2 4-bit d latch with active low, 1x/2x drive logic symbol cell data timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 ld5x4 ld5x4d2 ld5x4 ld5x4d2 dn gn dn gn 1.0 0.9 1.0 0.9 15.0 19.0 KGM80 ld5x4 ld5x4d2 ld5x4 ld5x4d2 dn gn dn gn 1.0 1.1 1.0 1.1 15.0 19.0 parameter symbol kg80 KGM80 ld5x4 ld5x4d2 ld5x4 ld5x4d2 pulse width low (gn) t pwl 0.61 0.64 1.02 1.05 input setup time (d0 to gn) t su 0.26 0.28 0.52 0.55 input hold time (d0 to gn) t hd 0.15 0.15 0.33 0.33 input setup time (d1 to gn) t su 0.26 0.28 0.52 0.55 input hold time (d1 to gn) t hd 0.15 0.15 0.33 0.33 input setup time (d2 to gn) t su 0.26 0.28 0.52 0.55 input hold time (d2 to gn) t hd 0.15 0.15 0.33 0.33 input setup time (d3 to gn) t su 0.26 0.28 0.52 0.55 input hold time (d3 to gn) t hd 0.15 0.15 0.33 0.33 d0 d1 d2 d3 gn q0 q1 q2 q3 qn0 qn1 qn2 qn3 truth table dn gn qn (n+1) qnn (n+1) 0001 1010 x 1 qn (n) qnn (n)
sec asic 3-421 kg80/KGM80 ld5x4/ld5xd2 4-bit d latch with active low, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld5x4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to q0 t plh 0.54 0.46 + 0.040*sl 0.46 + 0.041*sl 0.45 + 0.042*sl t phl 0.60 0.54 + 0.030*sl 0.55 + 0.025*sl 0.56 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl gn to q0 t plh 0.77 0.69 + 0.040*sl 0.69 + 0.041*sl 0.68 + 0.042*sl t phl 0.85 0.79 + 0.030*sl 0.80 + 0.025*sl 0.81 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl d1 to q1 t plh 0.55 0.46 + 0.040*sl 0.46 + 0.041*sl 0.46 + 0.042*sl t phl 0.60 0.54 + 0.030*sl 0.55 + 0.025*sl 0.56 + 0.023*sl t r 0.27 0.10 + 0.087*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl gn to q1 t plh 0.78 0.70 + 0.040*sl 0.69 + 0.041*sl 0.69 + 0.042*sl t phl 0.85 0.79 + 0.029*sl 0.80 + 0.025*sl 0.81 + 0.023*sl t r 0.27 0.09 + 0.087*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.08 + 0.040*sl 0.08 + 0.040*sl 0.08 + 0.042*sl d2 to q2 t plh 0.54 0.46 + 0.040*sl 0.46 + 0.041*sl 0.46 + 0.042*sl t phl 0.60 0.54 + 0.030*sl 0.55 + 0.025*sl 0.56 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.08 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl gn to q2 t plh 0.77 0.69 + 0.041*sl 0.69 + 0.041*sl 0.69 + 0.042*sl t phl 0.85 0.79 + 0.029*sl 0.80 + 0.025*sl 0.81 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl d3 to q3 t plh 0.54 0.46 + 0.040*sl 0.45 + 0.041*sl 0.45 + 0.042*sl t phl 0.60 0.54 + 0.030*sl 0.55 + 0.025*sl 0.56 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl gn to q3 t plh 0.77 0.69 + 0.040*sl 0.69 + 0.041*sl 0.68 + 0.042*sl t phl 0.84 0.79 + 0.029*sl 0.80 + 0.025*sl 0.81 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.041*sl 0.07 + 0.042*sl d0 to qn0 t plh 0.52 0.44 + 0.042*sl 0.44 + 0.041*sl 0.44 + 0.042*sl t phl 0.41 0.34 + 0.031*sl 0.36 + 0.026*sl 0.37 + 0.023*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.039*sl 0.09 + 0.040*sl 0.08 + 0.041*sl gn to qn0 t plh 0.77 0.69 + 0.042*sl 0.69 + 0.041*sl 0.69 + 0.042*sl t phl 0.64 0.58 + 0.031*sl 0.59 + 0.026*sl 0.60 + 0.023*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.08 + 0.041*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-422 sec asic ld5x4/ld5xd2 4-bit d latch with active low, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld5x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d1 to qn1 t plh 0.52 0.44 + 0.042*sl 0.44 + 0.042*sl 0.44 + 0.042*sl t phl 0.41 0.34 + 0.031*sl 0.36 + 0.026*sl 0.37 + 0.023*sl t r 0.27 0.11 + 0.084*sl 0.09 + 0.089*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl gn to qn1 t plh 0.77 0.69 + 0.041*sl 0.69 + 0.042*sl 0.69 + 0.042*sl t phl 0.64 0.58 + 0.031*sl 0.59 + 0.026*sl 0.60 + 0.023*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.08 + 0.042*sl d2 to qn2 t plh 0.52 0.44 + 0.042*sl 0.44 + 0.041*sl 0.44 + 0.042*sl t phl 0.41 0.34 + 0.031*sl 0.36 + 0.026*sl 0.37 + 0.023*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.089*sl 0.09 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl gn to qn2 t plh 0.77 0.69 + 0.042*sl 0.69 + 0.042*sl 0.69 + 0.042*sl t phl 0.64 0.58 + 0.030*sl 0.59 + 0.026*sl 0.60 + 0.023*sl t r 0.27 0.11 + 0.084*sl 0.09 + 0.089*sl 0.09 + 0.091*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.08 + 0.041*sl d3 to qn3 t plh 0.52 0.44 + 0.042*sl 0.44 + 0.041*sl 0.44 + 0.042*sl t phl 0.41 0.34 + 0.031*sl 0.36 + 0.026*sl 0.37 + 0.023*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.039*sl 0.09 + 0.040*sl 0.08 + 0.041*sl gn to qn3 t plh 0.77 0.69 + 0.042*sl 0.69 + 0.041*sl 0.69 + 0.042*sl t phl 0.64 0.58 + 0.031*sl 0.59 + 0.026*sl 0.60 + 0.023*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.08 + 0.041*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-423 kg80/KGM80 ld5x4/ld5xd2 4-bit d latch with active low, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld5x4d2 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to q0 t plh 0.57 0.52 + 0.020*sl 0.53 + 0.019*sl 0.52 + 0.020*sl t phl 0.63 0.59 + 0.018*sl 0.60 + 0.015*sl 0.61 + 0.013*sl t r 0.16 0.09 + 0.039*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.022*sl 0.10 + 0.019*sl 0.09 + 0.020*sl gn to q0 t plh 0.80 0.76 + 0.019*sl 0.76 + 0.019*sl 0.75 + 0.020*sl t phl 0.88 0.85 + 0.018*sl 0.86 + 0.015*sl 0.87 + 0.013*sl t r 0.16 0.08 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.021*sl 0.09 + 0.020*sl 0.09 + 0.020*sl d1 to q1 t plh 0.57 0.52 + 0.025*sl 0.53 + 0.019*sl 0.53 + 0.020*sl t phl 0.64 0.60 + 0.018*sl 0.61 + 0.015*sl 0.62 + 0.013*sl t r 0.17 0.10 + 0.036*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.09 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl gn to q1 t plh 0.81 0.77 + 0.019*sl 0.77 + 0.019*sl 0.76 + 0.020*sl t phl 0.89 0.85 + 0.018*sl 0.86 + 0.015*sl 0.88 + 0.013*sl t r 0.17 0.09 + 0.040*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.09 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl d2 to q2 t plh 0.58 0.54 + 0.019*sl 0.54 + 0.019*sl 0.54 + 0.020*sl t phl 0.65 0.61 + 0.017*sl 0.62 + 0.014*sl 0.63 + 0.013*sl t r 0.19 0.11 + 0.040*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.15 0.10 + 0.021*sl 0.11 + 0.020*sl 0.11 + 0.020*sl gn to q2 t plh 0.82 0.78 + 0.018*sl 0.78 + 0.019*sl 0.77 + 0.020*sl t phl 0.90 0.87 + 0.018*sl 0.87 + 0.014*sl 0.89 + 0.013*sl t r 0.19 0.11 + 0.041*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.15 0.10 + 0.021*sl 0.11 + 0.019*sl 0.11 + 0.020*sl d3 to q3 t plh 0.56 0.53 + 0.020*sl 0.53 + 0.019*sl 0.52 + 0.020*sl t phl 0.63 0.59 + 0.018*sl 0.60 + 0.015*sl 0.62 + 0.013*sl t r 0.16 0.08 + 0.040*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.022*sl 0.10 + 0.019*sl 0.09 + 0.020*sl gn to q3 t plh 0.80 0.76 + 0.019*sl 0.76 + 0.019*sl 0.75 + 0.020*sl t phl 0.88 0.85 + 0.018*sl 0.86 + 0.015*sl 0.87 + 0.013*sl t r 0.16 0.08 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.021*sl 0.09 + 0.020*sl 0.09 + 0.020*sl d0 to qn0 t plh 0.50 0.45 + 0.023*sl 0.46 + 0.021*sl 0.46 + 0.021*sl t phl 0.40 0.36 + 0.020*sl 0.37 + 0.015*sl 0.38 + 0.014*sl t r 0.17 0.09 + 0.039*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.020*sl 0.10 + 0.020*sl gn to qn0 t plh 0.75 0.71 + 0.023*sl 0.71 + 0.021*sl 0.71 + 0.021*sl t phl 0.64 0.59 + 0.021*sl 0.61 + 0.015*sl 0.62 + 0.013*sl t r 0.17 0.08 + 0.042*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.09 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-424 sec asic ld5x4/ld5xd2 4-bit d latch with active low, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld5x4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d1 to qn1 t plh 0.50 0.46 + 0.022*sl 0.46 + 0.021*sl 0.46 + 0.021*sl t phl 0.40 0.35 + 0.023*sl 0.37 + 0.015*sl 0.39 + 0.013*sl t r 0.17 0.09 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.11 + 0.017*sl 0.10 + 0.020*sl 0.11 + 0.020*sl gn to qn1 t plh 0.76 0.71 + 0.023*sl 0.71 + 0.021*sl 0.71 + 0.021*sl t phl 0.64 0.60 + 0.020*sl 0.61 + 0.015*sl 0.62 + 0.013*sl t r 0.17 0.09 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.09 + 0.023*sl 0.10 + 0.020*sl 0.10 + 0.020*sl d2 to qn2 t plh 0.50 0.46 + 0.022*sl 0.46 + 0.021*sl 0.46 + 0.021*sl t phl 0.40 0.36 + 0.020*sl 0.37 + 0.015*sl 0.39 + 0.013*sl t r 0.17 0.09 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.020*sl 0.10 + 0.020*sl 0.10 + 0.020*sl gn to qn2 t plh 0.76 0.71 + 0.023*sl 0.71 + 0.021*sl 0.71 + 0.021*sl t phl 0.64 0.60 + 0.020*sl 0.61 + 0.015*sl 0.62 + 0.013*sl t r 0.17 0.09 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.09 + 0.023*sl 0.10 + 0.020*sl 0.10 + 0.020*sl d3 to qn3 t plh 0.50 0.45 + 0.023*sl 0.46 + 0.021*sl 0.46 + 0.021*sl t phl 0.40 0.36 + 0.021*sl 0.37 + 0.015*sl 0.38 + 0.013*sl t r 0.17 0.09 + 0.039*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.10 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.020*sl gn to qn3 t plh 0.75 0.71 + 0.023*sl 0.71 + 0.021*sl 0.71 + 0.021*sl t phl 0.63 0.59 + 0.020*sl 0.61 + 0.015*sl 0.62 + 0.013*sl t r 0.17 0.08 + 0.042*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.14 0.09 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-425 kg80/KGM80 ld5x4/ld5xd2 4-bit d latch with active low, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld5x4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to q0 t plh 0.74 0.64 + 0.049*sl 0.64 + 0.050*sl 0.64 + 0.050*sl t phl 0.83 0.77 + 0.032*sl 0.79 + 0.026*sl 0.81 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl gn to q0 t plh 1.07 0.97 + 0.049*sl 0.97 + 0.050*sl 0.97 + 0.050*sl t phl 1.19 1.13 + 0.032*sl 1.15 + 0.026*sl 1.17 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl d1 to q1 t plh 0.75 0.66 + 0.049*sl 0.65 + 0.050*sl 0.65 + 0.050*sl t phl 0.84 0.78 + 0.032*sl 0.79 + 0.026*sl 0.82 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.042*sl 0.11 + 0.042*sl gn to q1 t plh 1.08 0.98 + 0.049*sl 0.98 + 0.050*sl 0.98 + 0.050*sl t phl 1.20 1.14 + 0.032*sl 1.16 + 0.026*sl 1.18 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.042*sl 0.11 + 0.042*sl d2 to q2 t plh 0.75 0.65 + 0.049*sl 0.65 + 0.050*sl 0.65 + 0.050*sl t phl 0.84 0.77 + 0.033*sl 0.79 + 0.026*sl 0.82 + 0.023*sl t r 0.34 0.14 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl gn to q2 t plh 1.08 0.98 + 0.049*sl 0.98 + 0.050*sl 0.98 + 0.050*sl t phl 1.20 1.13 + 0.033*sl 1.15 + 0.026*sl 1.18 + 0.023*sl t r 0.34 0.14 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.11 + 0.042*sl 0.11 + 0.042*sl d3 to q3 t plh 0.74 0.64 + 0.049*sl 0.64 + 0.050*sl 0.64 + 0.050*sl t phl 0.83 0.76 + 0.033*sl 0.79 + 0.026*sl 0.81 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl gn to q3 t plh 1.07 0.97 + 0.049*sl 0.97 + 0.050*sl 0.97 + 0.050*sl t phl 1.19 1.13 + 0.032*sl 1.15 + 0.026*sl 1.17 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl d0 to qn0 t plh 0.71 0.61 + 0.051*sl 0.61 + 0.050*sl 0.62 + 0.050*sl t phl 0.55 0.48 + 0.034*sl 0.50 + 0.026*sl 0.54 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.042*sl 0.12 + 0.041*sl 0.11 + 0.042*sl gn to qn0 t plh 1.07 0.97 + 0.051*sl 0.98 + 0.050*sl 0.98 + 0.050*sl t phl 0.88 0.81 + 0.034*sl 0.83 + 0.026*sl 0.86 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.043*sl 0.12 + 0.041*sl 0.11 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-426 sec asic ld5x4/ld5xd2 4-bit d latch with active low, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld5x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d1 to qn1 t plh 0.71 0.61 + 0.051*sl 0.61 + 0.050*sl 0.62 + 0.050*sl t phl 0.55 0.48 + 0.034*sl 0.50 + 0.026*sl 0.53 + 0.023*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.042*sl 0.12 + 0.041*sl 0.11 + 0.042*sl gn to qn1 t plh 1.07 0.97 + 0.051*sl 0.97 + 0.050*sl 0.98 + 0.050*sl t phl 0.88 0.81 + 0.034*sl 0.83 + 0.026*sl 0.86 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.045*sl 0.12 + 0.041*sl 0.11 + 0.042*sl d2 to qn2 t plh 0.72 0.61 + 0.051*sl 0.62 + 0.050*sl 0.62 + 0.050*sl t phl 0.55 0.48 + 0.034*sl 0.51 + 0.026*sl 0.54 + 0.023*sl t r 0.36 0.15 + 0.105*sl 0.14 + 0.108*sl 0.13 + 0.109*sl t f 0.21 0.12 + 0.043*sl 0.12 + 0.041*sl 0.12 + 0.042*sl gn to qn2 t plh 1.08 0.97 + 0.051*sl 0.98 + 0.050*sl 0.98 + 0.050*sl t phl 0.88 0.81 + 0.034*sl 0.83 + 0.026*sl 0.86 + 0.023*sl t r 0.36 0.15 + 0.105*sl 0.14 + 0.108*sl 0.13 + 0.109*sl t f 0.20 0.12 + 0.044*sl 0.12 + 0.042*sl 0.12 + 0.042*sl d3 to qn3 t plh 0.71 0.61 + 0.051*sl 0.61 + 0.050*sl 0.62 + 0.050*sl t phl 0.55 0.48 + 0.034*sl 0.50 + 0.026*sl 0.54 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.042*sl 0.12 + 0.041*sl 0.11 + 0.042*sl gn to qn3 t plh 1.07 0.97 + 0.051*sl 0.98 + 0.050*sl 0.98 + 0.050*sl t phl 0.88 0.81 + 0.034*sl 0.83 + 0.026*sl 0.86 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-427 kg80/KGM80 ld5x4/ld5xd2 4-bit d latch with active low, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld5x4d2 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to q0 t plh 0.78 0.74 + 0.024*sl 0.74 + 0.024*sl 0.73 + 0.025*sl t phl 0.89 0.84 + 0.022*sl 0.86 + 0.016*sl 0.89 + 0.013*sl t r 0.21 0.11 + 0.051*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.021*sl gn to q0 t plh 1.12 1.07 + 0.024*sl 1.07 + 0.024*sl 1.06 + 0.025*sl t phl 1.25 1.21 + 0.021*sl 1.23 + 0.016*sl 1.26 + 0.013*sl t r 0.21 0.11 + 0.050*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.020*sl d1 to q1 t plh 0.79 0.75 + 0.024*sl 0.75 + 0.024*sl 0.74 + 0.025*sl t phl 0.90 0.85 + 0.022*sl 0.87 + 0.016*sl 0.90 + 0.013*sl t r 0.22 0.12 + 0.051*sl 0.11 + 0.052*sl 0.10 + 0.054*sl t f 0.17 0.11 + 0.025*sl 0.13 + 0.021*sl 0.13 + 0.021*sl gn to q1 t plh 1.13 1.08 + 0.025*sl 1.08 + 0.024*sl 1.07 + 0.025*sl t phl 1.26 1.22 + 0.021*sl 1.24 + 0.016*sl 1.27 + 0.013*sl t r 0.22 0.12 + 0.051*sl 0.11 + 0.052*sl 0.10 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.13 + 0.021*sl 0.13 + 0.021*sl d2 to q2 t plh 0.81 0.76 + 0.023*sl 0.76 + 0.024*sl 0.75 + 0.025*sl t phl 0.91 0.87 + 0.020*sl 0.88 + 0.015*sl 0.91 + 0.013*sl t r 0.25 0.15 + 0.051*sl 0.14 + 0.053*sl 0.13 + 0.054*sl t f 0.18 0.13 + 0.024*sl 0.14 + 0.021*sl 0.14 + 0.021*sl gn to q2 t plh 1.14 1.09 + 0.024*sl 1.09 + 0.024*sl 1.09 + 0.025*sl t phl 1.28 1.24 + 0.019*sl 1.25 + 0.015*sl 1.28 + 0.013*sl t r 0.25 0.15 + 0.051*sl 0.14 + 0.053*sl 0.13 + 0.054*sl t f 0.18 0.13 + 0.024*sl 0.14 + 0.021*sl 0.15 + 0.021*sl d3 to q3 t plh 0.78 0.73 + 0.025*sl 0.74 + 0.024*sl 0.73 + 0.025*sl t phl 0.89 0.84 + 0.021*sl 0.86 + 0.016*sl 0.89 + 0.013*sl t r 0.21 0.11 + 0.051*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.021*sl gn to q3 t plh 1.11 1.07 + 0.024*sl 1.07 + 0.024*sl 1.06 + 0.025*sl t phl 1.25 1.21 + 0.021*sl 1.23 + 0.016*sl 1.26 + 0.013*sl t r 0.21 0.11 + 0.050*sl 0.11 + 0.052*sl 0.09 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.021*sl 0.13 + 0.021*sl d0 to qn0 t plh 0.69 0.63 + 0.028*sl 0.64 + 0.025*sl 0.64 + 0.025*sl t phl 0.55 0.51 + 0.023*sl 0.52 + 0.017*sl 0.56 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.11 + 0.026*sl 0.13 + 0.021*sl 0.14 + 0.020*sl gn to qn0 t plh 1.05 1.00 + 0.028*sl 1.00 + 0.025*sl 1.01 + 0.025*sl t phl 0.88 0.84 + 0.023*sl 0.85 + 0.016*sl 0.89 + 0.013*sl t r 0.22 0.12 + 0.051*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.022*sl 0.13 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-428 sec asic ld5x4/ld5xd2 4-bit d latch with active low, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld5x4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d1 to qn1 t plh 0.69 0.63 + 0.028*sl 0.64 + 0.025*sl 0.64 + 0.025*sl t phl 0.55 0.51 + 0.023*sl 0.53 + 0.016*sl 0.56 + 0.013*sl t r 0.22 0.12 + 0.049*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.024*sl 0.12 + 0.022*sl 0.14 + 0.021*sl gn to qn1 t plh 1.06 1.00 + 0.028*sl 1.01 + 0.025*sl 1.01 + 0.025*sl t phl 0.89 0.84 + 0.023*sl 0.86 + 0.016*sl 0.89 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.12 + 0.022*sl 0.14 + 0.021*sl d2 to qn2 t plh 0.69 0.63 + 0.028*sl 0.64 + 0.025*sl 0.64 + 0.025*sl t phl 0.55 0.51 + 0.023*sl 0.53 + 0.016*sl 0.56 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.022*sl 0.14 + 0.021*sl gn to qn2 t plh 1.06 1.00 + 0.028*sl 1.01 + 0.025*sl 1.01 + 0.025*sl t phl 0.89 0.84 + 0.023*sl 0.86 + 0.017*sl 0.89 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.12 + 0.025*sl 0.12 + 0.022*sl 0.14 + 0.021*sl d3 to qn3 t plh 0.69 0.63 + 0.028*sl 0.64 + 0.025*sl 0.64 + 0.025*sl t phl 0.55 0.50 + 0.023*sl 0.52 + 0.016*sl 0.56 + 0.013*sl t r 0.22 0.12 + 0.050*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.17 0.11 + 0.026*sl 0.13 + 0.021*sl 0.13 + 0.021*sl gn to qn3 t plh 1.05 1.00 + 0.028*sl 1.00 + 0.025*sl 1.01 + 0.025*sl t phl 0.88 0.84 + 0.023*sl 0.85 + 0.017*sl 0.89 + 0.013*sl t r 0.22 0.12 + 0.051*sl 0.11 + 0.053*sl 0.10 + 0.054*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.022*sl 0.14 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-429 kg80/KGM80 ld6/ld6d2 d latch with active low, reset, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 ld6 ld6d2 ld6 ld6d2 d gn rn d gn rn 0.9 0.9 0.5 0.9 0.9 0.5 6.0 7.0 KGM80 ld6 ld6d2 ld6 ld6d2 d gn rn d gn rn 1.0 1.0 1.0 1.0 1.0 1.0 6.0 7.0 parameter symbol kg80 KGM80 ld6 ld6d2 ld6 ld6d2 pulse width low (gn) t pwl 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 0.99 input setup time (d to gn) t su 0.47 0.50 0.80 0.83 input hold time (d to gn) t hd 0.15 0.15 0.33 0.33 recovery time (rn) t rc 0.15 0.15 0.33 0.33 input hold time (rn to gn) t hd 0.20 0.15 0.41 0.41 d gn q qn rn gn gn gnb rn rn d gnb gn q rn gn gnb qn truth table d gn rn q (n+1) qn (n+1) 00101 10110 x 1 1 q (n) qn (n) xx001
kg80/KGM80 3-430 sec asic ld6/ld6d2 d latch with active low, reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.55 0.46 + 0.044*sl 0.47 + 0.042*sl 0.47 + 0.042*sl t phl 0.58 0.51 + 0.032*sl 0.53 + 0.026*sl 0.54 + 0.024*sl t r 0.28 0.11 + 0.087*sl 0.11 + 0.088*sl 0.09 + 0.090*sl t f 0.18 0.10 + 0.042*sl 0.10 + 0.039*sl 0.09 + 0.041*sl gn to q t plh 0.63 0.54 + 0.044*sl 0.55 + 0.042*sl 0.55 + 0.042*sl t phl 0.56 0.49 + 0.032*sl 0.51 + 0.026*sl 0.53 + 0.023*sl t r 0.28 0.11 + 0.086*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.18 0.10 + 0.041*sl 0.10 + 0.039*sl 0.09 + 0.041*sl rn to q t plh 0.31 0.22 + 0.044*sl 0.22 + 0.042*sl 0.23 + 0.041*sl t phl 0.30 0.24 + 0.030*sl 0.25 + 0.025*sl 0.27 + 0.023*sl t r 0.28 0.11 + 0.087*sl 0.11 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.10 + 0.039*sl 0.10 + 0.039*sl 0.08 + 0.041*sl d to qn t plh 0.72 0.64 + 0.040*sl 0.63 + 0.041*sl 0.63 + 0.042*sl t phl 0.63 0.57 + 0.030*sl 0.59 + 0.025*sl 0.60 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.08 + 0.041*sl gn to qn t plh 0.70 0.62 + 0.040*sl 0.61 + 0.041*sl 0.61 + 0.042*sl t phl 0.71 0.65 + 0.030*sl 0.66 + 0.025*sl 0.67 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.16 0.09 + 0.040*sl 0.08 + 0.040*sl 0.08 + 0.041*sl rn to qn t plh 0.51 0.43 + 0.042*sl 0.43 + 0.041*sl 0.43 + 0.041*sl t phl 0.39 0.33 + 0.030*sl 0.34 + 0.025*sl 0.35 + 0.023*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.042*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-431 kg80/KGM80 ld6/ld6d2 d latch with active low, reset, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld6d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.55 0.50 + 0.024*sl 0.50 + 0.022*sl 0.51 + 0.021*sl t phl 0.58 0.54 + 0.020*sl 0.55 + 0.016*sl 0.56 + 0.013*sl t r 0.21 0.12 + 0.043*sl 0.12 + 0.043*sl 0.11 + 0.044*sl t f 0.16 0.12 + 0.021*sl 0.12 + 0.020*sl 0.12 + 0.020*sl gn to q t plh 0.62 0.58 + 0.022*sl 0.58 + 0.021*sl 0.58 + 0.021*sl t phl 0.56 0.52 + 0.020*sl 0.53 + 0.015*sl 0.54 + 0.014*sl t r 0.21 0.12 + 0.043*sl 0.12 + 0.043*sl 0.11 + 0.044*sl t f 0.16 0.11 + 0.021*sl 0.12 + 0.020*sl 0.12 + 0.019*sl rn to q t plh 0.30 0.26 + 0.022*sl 0.26 + 0.022*sl 0.26 + 0.021*sl t phl 0.30 0.26 + 0.020*sl 0.28 + 0.015*sl 0.29 + 0.013*sl t r 0.21 0.12 + 0.042*sl 0.12 + 0.043*sl 0.11 + 0.044*sl t f 0.15 0.11 + 0.021*sl 0.11 + 0.019*sl 0.11 + 0.019*sl d to qn t plh 0.75 0.71 + 0.019*sl 0.71 + 0.019*sl 0.70 + 0.020*sl t phl 0.68 0.64 + 0.018*sl 0.65 + 0.014*sl 0.66 + 0.013*sl t r 0.19 0.10 + 0.041*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.15 0.11 + 0.020*sl 0.11 + 0.019*sl 0.11 + 0.020*sl gn to qn t plh 0.73 0.69 + 0.019*sl 0.69 + 0.019*sl 0.68 + 0.020*sl t phl 0.76 0.73 + 0.015*sl 0.73 + 0.014*sl 0.74 + 0.013*sl t r 0.19 0.10 + 0.042*sl 0.10 + 0.042*sl 0.09 + 0.044*sl t f 0.15 0.11 + 0.020*sl 0.11 + 0.019*sl 0.11 + 0.020*sl rn to qn t plh 0.54 0.50 + 0.022*sl 0.50 + 0.020*sl 0.50 + 0.020*sl t phl 0.43 0.40 + 0.016*sl 0.41 + 0.015*sl 0.42 + 0.013*sl t r 0.20 0.12 + 0.041*sl 0.12 + 0.042*sl 0.11 + 0.043*sl t f 0.15 0.10 + 0.022*sl 0.11 + 0.019*sl 0.11 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-432 sec asic ld6/ld6d2 d latch with active low, reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.79 0.68 + 0.054*sl 0.69 + 0.051*sl 0.70 + 0.050*sl t phl 0.78 0.71 + 0.035*sl 0.73 + 0.027*sl 0.77 + 0.023*sl t r 0.37 0.16 + 0.105*sl 0.15 + 0.107*sl 0.14 + 0.108*sl t f 0.21 0.13 + 0.044*sl 0.13 + 0.041*sl 0.12 + 0.042*sl gn to q t plh 0.87 0.76 + 0.054*sl 0.77 + 0.051*sl 0.78 + 0.050*sl t phl 0.76 0.69 + 0.036*sl 0.71 + 0.027*sl 0.75 + 0.023*sl t r 0.37 0.16 + 0.105*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.21 0.13 + 0.043*sl 0.13 + 0.041*sl 0.12 + 0.042*sl rn to q t plh 0.40 0.29 + 0.053*sl 0.30 + 0.051*sl 0.31 + 0.050*sl t phl 0.39 0.32 + 0.034*sl 0.34 + 0.026*sl 0.37 + 0.023*sl t r 0.37 0.15 + 0.106*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.20 0.12 + 0.043*sl 0.12 + 0.041*sl 0.11 + 0.042*sl d to qn t plh 0.98 0.88 + 0.049*sl 0.88 + 0.050*sl 0.88 + 0.050*sl t phl 0.92 0.85 + 0.033*sl 0.87 + 0.026*sl 0.90 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.11 + 0.041*sl 0.11 + 0.042*sl gn to qn t plh 0.96 0.86 + 0.049*sl 0.86 + 0.050*sl 0.86 + 0.050*sl t phl 1.00 0.93 + 0.033*sl 0.95 + 0.026*sl 0.98 + 0.023*sl t r 0.34 0.13 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.043*sl 0.11 + 0.041*sl 0.11 + 0.042*sl rn to qn t plh 0.67 0.56 + 0.054*sl 0.57 + 0.050*sl 0.57 + 0.050*sl t phl 0.53 0.46 + 0.033*sl 0.48 + 0.026*sl 0.51 + 0.023*sl t r 0.37 0.16 + 0.103*sl 0.15 + 0.106*sl 0.13 + 0.108*sl t f 0.20 0.11 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-433 kg80/KGM80 ld6/ld6d2 d latch with active low, reset, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld6d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.79 0.73 + 0.030*sl 0.74 + 0.026*sl 0.75 + 0.025*sl t phl 0.79 0.74 + 0.023*sl 0.76 + 0.016*sl 0.80 + 0.013*sl t r 0.28 0.17 + 0.053*sl 0.17 + 0.052*sl 0.16 + 0.053*sl t f 0.19 0.14 + 0.024*sl 0.15 + 0.021*sl 0.16 + 0.020*sl gn to q t plh 0.86 0.80 + 0.030*sl 0.81 + 0.026*sl 0.82 + 0.025*sl t phl 0.77 0.72 + 0.023*sl 0.74 + 0.016*sl 0.78 + 0.013*sl t r 0.27 0.17 + 0.052*sl 0.17 + 0.053*sl 0.16 + 0.053*sl t f 0.19 0.14 + 0.024*sl 0.15 + 0.021*sl 0.16 + 0.020*sl rn to q t plh 0.39 0.33 + 0.029*sl 0.34 + 0.026*sl 0.35 + 0.025*sl t phl 0.40 0.36 + 0.021*sl 0.37 + 0.016*sl 0.40 + 0.013*sl t r 0.27 0.17 + 0.052*sl 0.17 + 0.053*sl 0.16 + 0.053*sl t f 0.18 0.13 + 0.023*sl 0.14 + 0.021*sl 0.15 + 0.020*sl d to qn t plh 1.03 0.98 + 0.024*sl 0.98 + 0.024*sl 0.97 + 0.025*sl t phl 0.99 0.95 + 0.020*sl 0.97 + 0.015*sl 0.99 + 0.013*sl t r 0.24 0.14 + 0.051*sl 0.14 + 0.052*sl 0.12 + 0.054*sl t f 0.18 0.13 + 0.023*sl 0.14 + 0.021*sl 0.14 + 0.020*sl gn to qn t plh 1.01 0.96 + 0.024*sl 0.96 + 0.024*sl 0.95 + 0.025*sl t phl 1.07 1.03 + 0.019*sl 1.04 + 0.015*sl 1.07 + 0.013*sl t r 0.24 0.14 + 0.051*sl 0.14 + 0.052*sl 0.12 + 0.054*sl t f 0.18 0.13 + 0.023*sl 0.14 + 0.021*sl 0.14 + 0.020*sl rn to qn t plh 0.72 0.66 + 0.028*sl 0.67 + 0.025*sl 0.67 + 0.024*sl t phl 0.60 0.56 + 0.019*sl 0.57 + 0.015*sl 0.60 + 0.013*sl t r 0.27 0.17 + 0.052*sl 0.17 + 0.052*sl 0.16 + 0.053*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.021*sl 0.15 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-434 sec asic ld7/ld7d2 d latch with active low, set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 ld7 ld7d2 ld7 ld7d2 d gn sn d gn sn 0.8 0.8 0.7 0.8 0.8 0.7 6.0 7.0 KGM80 ld7 ld7d2 ld7 ld7d2 d gn sn d gn sn 0.9 0.9 0.9 0.9 0.9 0.9 6.0 7.0 parameter symbol kg80 KGM80 ld7 ld7d2 ld7 ld7d2 pulse width low (gn) t pwl 0.61 0.61 0.99 0.99 pulse width low (sn) t pwl 0.61 0.61 0.99 0.99 input setup time (d to gn) t su 0.42 0.45 0.74 0.80 input hold time (d to gn) t hd 0.15 0.15 0.33 0.33 recovery time (sn) t rc 0.15 0.15 0.33 0.33 input hold time (sn to ck) t hd 0.15 0.15 0.41 0.41 d gn q qn sn gn gn gnb sn sn d gnb gn qn sn gn gnb q truth table d gn sn q (n+1) qn (n+1) 00101 10110 x 1 1 q (n) qn (n) xx010
sec asic 3-435 kg80/KGM80 ld7/ld7d2 d latch with active low, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld7 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.54 0.46 + 0.040*sl 0.45 + 0.041*sl 0.45 + 0.042*sl t phl 0.65 0.59 + 0.028*sl 0.60 + 0.025*sl 0.61 + 0.023*sl t r 0.26 0.08 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl gn to q t plh 0.66 0.58 + 0.040*sl 0.57 + 0.041*sl 0.57 + 0.042*sl t phl 0.70 0.64 + 0.028*sl 0.65 + 0.025*sl 0.66 + 0.023*sl t r 0.26 0.08 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl sn to q t plh 0.55 0.46 + 0.042*sl 0.47 + 0.041*sl 0.47 + 0.041*sl t phl 0.37 0.31 + 0.028*sl 0.32 + 0.025*sl 0.33 + 0.023*sl t r 0.28 0.11 + 0.085*sl 0.11 + 0.087*sl 0.09 + 0.090*sl t f 0.16 0.08 + 0.041*sl 0.08 + 0.040*sl 0.07 + 0.042*sl d to qn t plh 0.58 0.49 + 0.044*sl 0.50 + 0.042*sl 0.50 + 0.041*sl t phl 0.41 0.35 + 0.031*sl 0.36 + 0.026*sl 0.38 + 0.024*sl t r 0.28 0.11 + 0.087*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.08 + 0.041*sl gn to qn t plh 0.63 0.54 + 0.045*sl 0.55 + 0.042*sl 0.55 + 0.042*sl t phl 0.53 0.47 + 0.031*sl 0.48 + 0.026*sl 0.50 + 0.023*sl t r 0.28 0.11 + 0.086*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.08 + 0.041*sl sn to qn t plh 0.30 0.21 + 0.045*sl 0.22 + 0.042*sl 0.22 + 0.042*sl t phl 0.34 0.27 + 0.032*sl 0.29 + 0.026*sl 0.30 + 0.023*sl t r 0.28 0.11 + 0.087*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.19 0.11 + 0.039*sl 0.11 + 0.039*sl 0.10 + 0.040*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-436 sec asic ld7/ld7d2 d latch with active low, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld7d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.56 0.53 + 0.018*sl 0.52 + 0.020*sl 0.52 + 0.021*sl t phl 0.69 0.66 + 0.016*sl 0.66 + 0.014*sl 0.67 + 0.012*sl t r 0.18 0.09 + 0.042*sl 0.09 + 0.044*sl 0.08 + 0.046*sl t f 0.14 0.10 + 0.020*sl 0.10 + 0.019*sl 0.10 + 0.020*sl gn to q t plh 0.68 0.64 + 0.019*sl 0.64 + 0.020*sl 0.64 + 0.021*sl t phl 0.74 0.71 + 0.016*sl 0.72 + 0.014*sl 0.73 + 0.012*sl t r 0.18 0.10 + 0.041*sl 0.09 + 0.044*sl 0.08 + 0.045*sl t f 0.14 0.10 + 0.019*sl 0.10 + 0.019*sl 0.09 + 0.020*sl sn to q t plh 0.58 0.53 + 0.021*sl 0.54 + 0.020*sl 0.54 + 0.020*sl t phl 0.40 0.37 + 0.016*sl 0.38 + 0.014*sl 0.39 + 0.012*sl t r 0.20 0.12 + 0.043*sl 0.12 + 0.043*sl 0.11 + 0.044*sl t f 0.14 0.10 + 0.019*sl 0.10 + 0.019*sl 0.10 + 0.020*sl d to qn t plh 0.58 0.53 + 0.024*sl 0.54 + 0.022*sl 0.54 + 0.021*sl t phl 0.41 0.37 + 0.019*sl 0.38 + 0.015*sl 0.40 + 0.013*sl t r 0.21 0.12 + 0.044*sl 0.12 + 0.044*sl 0.11 + 0.045*sl t f 0.15 0.10 + 0.021*sl 0.11 + 0.020*sl 0.11 + 0.020*sl gn to qn t plh 0.63 0.58 + 0.024*sl 0.59 + 0.022*sl 0.59 + 0.021*sl t phl 0.53 0.49 + 0.019*sl 0.50 + 0.015*sl 0.52 + 0.013*sl t r 0.20 0.12 + 0.043*sl 0.12 + 0.044*sl 0.11 + 0.044*sl t f 0.14 0.10 + 0.023*sl 0.11 + 0.020*sl 0.11 + 0.020*sl sn to qn t plh 0.29 0.24 + 0.024*sl 0.25 + 0.022*sl 0.25 + 0.021*sl t phl 0.33 0.29 + 0.020*sl 0.30 + 0.015*sl 0.32 + 0.013*sl t r 0.20 0.12 + 0.042*sl 0.12 + 0.043*sl 0.11 + 0.045*sl t f 0.16 0.12 + 0.020*sl 0.12 + 0.019*sl 0.12 + 0.019*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-437 kg80/KGM80 ld7/ld7d2 d latch with active low, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld7 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.75 0.65 + 0.049*sl 0.65 + 0.050*sl 0.65 + 0.050*sl t phl 0.92 0.85 + 0.032*sl 0.87 + 0.025*sl 0.89 + 0.023*sl t r 0.33 0.12 + 0.105*sl 0.11 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.041*sl 0.09 + 0.043*sl gn to q t plh 0.90 0.81 + 0.049*sl 0.80 + 0.050*sl 0.80 + 0.050*sl t phl 0.99 0.92 + 0.032*sl 0.94 + 0.025*sl 0.96 + 0.023*sl t r 0.33 0.12 + 0.105*sl 0.11 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.042*sl 0.10 + 0.042*sl 0.09 + 0.043*sl sn to q t plh 0.73 0.62 + 0.054*sl 0.63 + 0.050*sl 0.63 + 0.050*sl t phl 0.51 0.45 + 0.032*sl 0.47 + 0.025*sl 0.49 + 0.023*sl t r 0.37 0.16 + 0.103*sl 0.16 + 0.106*sl 0.13 + 0.108*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.041*sl 0.10 + 0.042*sl d to qn t plh 0.81 0.70 + 0.055*sl 0.71 + 0.051*sl 0.72 + 0.050*sl t phl 0.57 0.50 + 0.035*sl 0.52 + 0.027*sl 0.56 + 0.023*sl t r 0.37 0.16 + 0.105*sl 0.15 + 0.107*sl 0.13 + 0.108*sl t f 0.20 0.11 + 0.045*sl 0.12 + 0.041*sl 0.12 + 0.042*sl gn to qn t plh 0.88 0.77 + 0.054*sl 0.78 + 0.051*sl 0.80 + 0.050*sl t phl 0.72 0.65 + 0.035*sl 0.68 + 0.027*sl 0.71 + 0.023*sl t r 0.37 0.16 + 0.105*sl 0.15 + 0.107*sl 0.13 + 0.108*sl t f 0.20 0.11 + 0.045*sl 0.12 + 0.041*sl 0.12 + 0.042*sl sn to qn t plh 0.41 0.30 + 0.055*sl 0.31 + 0.051*sl 0.32 + 0.050*sl t phl 0.44 0.37 + 0.037*sl 0.39 + 0.027*sl 0.43 + 0.023*sl t r 0.36 0.15 + 0.105*sl 0.15 + 0.107*sl 0.13 + 0.108*sl t f 0.22 0.13 + 0.043*sl 0.14 + 0.040*sl 0.13 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-438 sec asic ld7/ld7d2 d latch with active low, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld7d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.79 0.75 + 0.023*sl 0.74 + 0.024*sl 0.74 + 0.025*sl t phl 0.99 0.95 + 0.018*sl 0.96 + 0.015*sl 0.98 + 0.012*sl t r 0.24 0.13 + 0.051*sl 0.13 + 0.053*sl 0.11 + 0.054*sl t f 0.17 0.12 + 0.023*sl 0.13 + 0.020*sl 0.13 + 0.020*sl gn to q t plh 0.95 0.90 + 0.023*sl 0.90 + 0.024*sl 0.89 + 0.025*sl t phl 1.06 1.02 + 0.018*sl 1.03 + 0.015*sl 1.05 + 0.012*sl t r 0.24 0.13 + 0.051*sl 0.13 + 0.053*sl 0.11 + 0.054*sl t f 0.17 0.12 + 0.023*sl 0.13 + 0.020*sl 0.13 + 0.020*sl sn to q t plh 0.77 0.71 + 0.029*sl 0.72 + 0.025*sl 0.73 + 0.024*sl t phl 0.57 0.54 + 0.018*sl 0.55 + 0.015*sl 0.57 + 0.012*sl t r 0.27 0.16 + 0.052*sl 0.17 + 0.051*sl 0.15 + 0.053*sl t f 0.17 0.12 + 0.023*sl 0.13 + 0.020*sl 0.13 + 0.020*sl d to qn t plh 0.81 0.75 + 0.030*sl 0.76 + 0.026*sl 0.77 + 0.025*sl t phl 0.58 0.54 + 0.021*sl 0.55 + 0.016*sl 0.58 + 0.013*sl t r 0.27 0.16 + 0.052*sl 0.16 + 0.052*sl 0.15 + 0.053*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.021*sl 0.15 + 0.020*sl gn to qn t plh 0.88 0.82 + 0.030*sl 0.83 + 0.026*sl 0.84 + 0.025*sl t phl 0.73 0.69 + 0.022*sl 0.71 + 0.016*sl 0.74 + 0.013*sl t r 0.27 0.16 + 0.052*sl 0.16 + 0.052*sl 0.16 + 0.053*sl t f 0.18 0.13 + 0.023*sl 0.13 + 0.021*sl 0.15 + 0.020*sl sn to qn t plh 0.40 0.34 + 0.030*sl 0.35 + 0.026*sl 0.36 + 0.025*sl t phl 0.44 0.40 + 0.023*sl 0.41 + 0.016*sl 0.45 + 0.013*sl t r 0.26 0.16 + 0.052*sl 0.16 + 0.052*sl 0.15 + 0.053*sl t f 0.19 0.14 + 0.024*sl 0.15 + 0.021*sl 0.17 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-439 kg80/KGM80 ld8/ld8d2 d latch with active low, reset, set, 1x/2x drive logic symbol cell data schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) input load (sl) gate count kg80 ld8 ld8d2 ld8 ld8d2 d gn rn sn d gn rn sn 0.8 0.8 0.7 0.7 0.8 0.8 0.7 0.7 6.0 7.0 KGM80 ld8 ld8d2 ld8 ld8d2 d gn rn sn d gn rn sn 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 6.0 7.0 parameter symbol kg80 KGM80 ld8 ld8d2 ld8 ld8d2 pulse width low (gn) t pwl 0.61 0.61 0.99 0.99 pulse width low (rn) t pwl 0.61 0.61 0.99 0.99 pulse width low (sn) t pwl 0.61 0.61 0.99 0.99 input setup time (d to gn) t su 0.50 0.53 0.83 0.86 input hold time (d to gn) t hd 0.15 0.15 0.33 0.33 recovery time (rn) t rc 0.17 0.20 0.36 0.43 input hold time (rn to gn) t hd 0.15 0.15 0.41 0.41 recovery time (sn) t rc 0.15 0.15 0.33 0.33 input hold time (sn to gn) t hd 0.20 0.15 0.41 0.41 d gn q qn rn sn gn gn gnb rn rn d gnb gn qn rn gn gnb q sn sn sn truth table dgnrnsn q (n+1) qn (n+1) 001101 101110 x 1 1 1 q (n) qn (n) xx1010 xx0101 xx0010
kg80/KGM80 3-440 sec asic ld8/ld8d2 d latch with active low, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.73 0.65 + 0.040*sl 0.65 + 0.041*sl 0.65 + 0.042*sl t phl 0.77 0.71 + 0.030*sl 0.73 + 0.025*sl 0.74 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.041*sl 0.08 + 0.040*sl 0.07 + 0.041*sl gn to q t plh 0.81 0.72 + 0.041*sl 0.72 + 0.041*sl 0.72 + 0.042*sl t phl 0.76 0.69 + 0.030*sl 0.71 + 0.025*sl 0.72 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.17 0.08 + 0.041*sl 0.09 + 0.040*sl 0.07 + 0.041*sl sn to q t plh 0.47 0.38 + 0.040*sl 0.38 + 0.041*sl 0.38 + 0.042*sl t phl 0.37 0.31 + 0.030*sl 0.33 + 0.025*sl 0.34 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.040*sl 0.07 + 0.041*sl rn to q t plh 0.48 0.40 + 0.041*sl 0.39 + 0.041*sl 0.39 + 0.042*sl t phl 0.56 0.51 + 0.027*sl 0.51 + 0.025*sl 0.52 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl d to qn t plh 0.70 0.61 + 0.045*sl 0.62 + 0.042*sl 0.62 + 0.042*sl t phl 0.61 0.54 + 0.031*sl 0.56 + 0.026*sl 0.57 + 0.024*sl t r 0.28 0.10 + 0.086*sl 0.10 + 0.089*sl 0.09 + 0.090*sl t f 0.17 0.08 + 0.043*sl 0.09 + 0.040*sl 0.08 + 0.041*sl gn to qn t plh 0.68 0.59 + 0.045*sl 0.60 + 0.042*sl 0.60 + 0.042*sl t phl 0.68 0.62 + 0.031*sl 0.63 + 0.026*sl 0.65 + 0.023*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.089*sl 0.09 + 0.090*sl t f 0.17 0.08 + 0.043*sl 0.09 + 0.040*sl 0.08 + 0.041*sl sn to qn t plh 0.30 0.21 + 0.044*sl 0.22 + 0.042*sl 0.22 + 0.042*sl t phl 0.34 0.27 + 0.033*sl 0.29 + 0.026*sl 0.31 + 0.024*sl t r 0.28 0.11 + 0.086*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.039*sl 0.10 + 0.041*sl rn to qn t plh 0.49 0.41 + 0.042*sl 0.40 + 0.042*sl 0.41 + 0.042*sl t phl 0.35 0.29 + 0.031*sl 0.30 + 0.026*sl 0.32 + 0.024*sl t r 0.28 0.10 + 0.088*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.17 0.08 + 0.043*sl 0.09 + 0.040*sl 0.08 + 0.041*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-441 kg80/KGM80 ld8/ld8d2 d latch with active low, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ld8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.76 0.72 + 0.019*sl 0.72 + 0.020*sl 0.71 + 0.021*sl t phl 0.81 0.78 + 0.017*sl 0.79 + 0.014*sl 0.80 + 0.012*sl t r 0.18 0.10 + 0.040*sl 0.09 + 0.044*sl 0.08 + 0.045*sl t f 0.14 0.10 + 0.021*sl 0.11 + 0.019*sl 0.11 + 0.019*sl gn to q t plh 0.83 0.79 + 0.019*sl 0.79 + 0.020*sl 0.79 + 0.021*sl t phl 0.79 0.76 + 0.017*sl 0.77 + 0.014*sl 0.78 + 0.013*sl t r 0.18 0.09 + 0.043*sl 0.09 + 0.044*sl 0.08 + 0.045*sl t f 0.14 0.10 + 0.021*sl 0.11 + 0.019*sl 0.10 + 0.020*sl sn to q t plh 0.49 0.45 + 0.019*sl 0.45 + 0.020*sl 0.44 + 0.021*sl t phl 0.41 0.38 + 0.017*sl 0.39 + 0.014*sl 0.39 + 0.013*sl t r 0.18 0.10 + 0.043*sl 0.09 + 0.044*sl 0.08 + 0.045*sl t f 0.14 0.10 + 0.021*sl 0.11 + 0.020*sl 0.11 + 0.019*sl rn to q t plh 0.50 0.46 + 0.019*sl 0.46 + 0.020*sl 0.46 + 0.021*sl t phl 0.60 0.57 + 0.016*sl 0.57 + 0.014*sl 0.59 + 0.012*sl t r 0.18 0.10 + 0.043*sl 0.09 + 0.044*sl 0.08 + 0.045*sl t f 0.14 0.10 + 0.020*sl 0.10 + 0.019*sl 0.10 + 0.020*sl d to qn t plh 0.69 0.65 + 0.024*sl 0.65 + 0.022*sl 0.65 + 0.021*sl t phl 0.61 0.57 + 0.019*sl 0.58 + 0.015*sl 0.59 + 0.013*sl t r 0.20 0.12 + 0.042*sl 0.11 + 0.044*sl 0.11 + 0.045*sl t f 0.14 0.10 + 0.020*sl 0.10 + 0.021*sl 0.11 + 0.019*sl gn to qn t plh 0.67 0.62 + 0.025*sl 0.63 + 0.022*sl 0.64 + 0.021*sl t phl 0.68 0.64 + 0.019*sl 0.65 + 0.015*sl 0.66 + 0.013*sl t r 0.20 0.12 + 0.041*sl 0.11 + 0.044*sl 0.10 + 0.045*sl t f 0.14 0.10 + 0.022*sl 0.10 + 0.020*sl 0.11 + 0.020*sl sn to qn t plh 0.29 0.24 + 0.024*sl 0.25 + 0.021*sl 0.25 + 0.021*sl t phl 0.33 0.29 + 0.021*sl 0.30 + 0.016*sl 0.32 + 0.014*sl t r 0.20 0.12 + 0.043*sl 0.11 + 0.044*sl 0.11 + 0.045*sl t f 0.16 0.12 + 0.022*sl 0.12 + 0.020*sl 0.13 + 0.019*sl rn to qn t plh 0.48 0.43 + 0.024*sl 0.44 + 0.022*sl 0.45 + 0.021*sl t phl 0.35 0.31 + 0.019*sl 0.32 + 0.015*sl 0.33 + 0.013*sl t r 0.20 0.12 + 0.043*sl 0.11 + 0.044*sl 0.11 + 0.045*sl t f 0.15 0.10 + 0.023*sl 0.11 + 0.020*sl 0.11 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-442 sec asic ld8/ld8d2 d latch with active low, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 1.08 0.98 + 0.050*sl 0.98 + 0.050*sl 0.98 + 0.050*sl t phl 1.07 1.00 + 0.033*sl 1.02 + 0.026*sl 1.05 + 0.023*sl t r 0.34 0.13 + 0.105*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.041*sl 0.10 + 0.042*sl gn to q t plh 1.14 1.04 + 0.050*sl 1.04 + 0.050*sl 1.04 + 0.050*sl t phl 1.05 0.98 + 0.033*sl 1.00 + 0.026*sl 1.03 + 0.023*sl t r 0.34 0.13 + 0.105*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.041*sl 0.10 + 0.042*sl sn to q t plh 0.62 0.52 + 0.049*sl 0.52 + 0.050*sl 0.52 + 0.050*sl t phl 0.52 0.45 + 0.033*sl 0.47 + 0.026*sl 0.50 + 0.023*sl t r 0.34 0.13 + 0.105*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.20 0.11 + 0.044*sl 0.12 + 0.041*sl 0.10 + 0.042*sl rn to q t plh 0.67 0.57 + 0.050*sl 0.57 + 0.050*sl 0.58 + 0.050*sl t phl 0.77 0.70 + 0.032*sl 0.72 + 0.026*sl 0.74 + 0.023*sl t r 0.34 0.13 + 0.105*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl d to qn t plh 0.96 0.85 + 0.054*sl 0.86 + 0.051*sl 0.87 + 0.050*sl t phl 0.90 0.83 + 0.035*sl 0.85 + 0.027*sl 0.88 + 0.023*sl t r 0.36 0.15 + 0.105*sl 0.14 + 0.107*sl 0.13 + 0.109*sl t f 0.20 0.11 + 0.045*sl 0.12 + 0.041*sl 0.12 + 0.042*sl gn to qn t plh 0.94 0.83 + 0.054*sl 0.84 + 0.051*sl 0.85 + 0.050*sl t phl 0.96 0.89 + 0.035*sl 0.91 + 0.027*sl 0.95 + 0.024*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.107*sl 0.13 + 0.109*sl t f 0.20 0.11 + 0.045*sl 0.12 + 0.041*sl 0.12 + 0.042*sl sn to qn t plh 0.41 0.30 + 0.054*sl 0.31 + 0.051*sl 0.32 + 0.050*sl t phl 0.44 0.37 + 0.037*sl 0.39 + 0.027*sl 0.43 + 0.024*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.107*sl 0.13 + 0.109*sl t f 0.22 0.13 + 0.044*sl 0.14 + 0.041*sl 0.13 + 0.042*sl rn to qn t plh 0.66 0.55 + 0.054*sl 0.56 + 0.051*sl 0.57 + 0.050*sl t phl 0.49 0.43 + 0.035*sl 0.45 + 0.027*sl 0.48 + 0.023*sl t r 0.36 0.15 + 0.105*sl 0.14 + 0.107*sl 0.13 + 0.109*sl t f 0.20 0.12 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-443 kg80/KGM80 ld8/ld8d2 d latch with active low, reset, set, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ld8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 1.12 1.07 + 0.023*sl 1.07 + 0.024*sl 1.06 + 0.025*sl t phl 1.13 1.09 + 0.019*sl 1.10 + 0.015*sl 1.13 + 0.012*sl t r 0.24 0.14 + 0.051*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.17 0.13 + 0.024*sl 0.14 + 0.020*sl 0.14 + 0.020*sl gn to q t plh 1.18 1.14 + 0.023*sl 1.13 + 0.024*sl 1.13 + 0.025*sl t phl 1.11 1.07 + 0.019*sl 1.08 + 0.015*sl 1.11 + 0.013*sl t r 0.24 0.14 + 0.051*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.17 0.13 + 0.025*sl 0.14 + 0.020*sl 0.14 + 0.020*sl sn to q t plh 0.66 0.62 + 0.023*sl 0.62 + 0.024*sl 0.61 + 0.025*sl t phl 0.58 0.54 + 0.019*sl 0.55 + 0.015*sl 0.58 + 0.012*sl t r 0.24 0.14 + 0.051*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.18 0.12 + 0.025*sl 0.14 + 0.020*sl 0.14 + 0.020*sl rn to q t plh 0.72 0.67 + 0.023*sl 0.67 + 0.024*sl 0.66 + 0.025*sl t phl 0.83 0.79 + 0.019*sl 0.80 + 0.015*sl 0.83 + 0.013*sl t r 0.24 0.14 + 0.051*sl 0.13 + 0.053*sl 0.12 + 0.054*sl t f 0.17 0.13 + 0.023*sl 0.13 + 0.020*sl 0.13 + 0.020*sl d to qn t plh 0.95 0.89 + 0.030*sl 0.90 + 0.026*sl 0.91 + 0.025*sl t phl 0.90 0.86 + 0.021*sl 0.87 + 0.016*sl 0.91 + 0.013*sl t r 0.26 0.16 + 0.053*sl 0.16 + 0.052*sl 0.15 + 0.053*sl t f 0.17 0.13 + 0.025*sl 0.13 + 0.021*sl 0.15 + 0.020*sl gn to qn t plh 0.93 0.87 + 0.030*sl 0.88 + 0.026*sl 0.89 + 0.025*sl t phl 0.97 0.92 + 0.022*sl 0.94 + 0.016*sl 0.97 + 0.013*sl t r 0.26 0.16 + 0.053*sl 0.16 + 0.052*sl 0.15 + 0.053*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.021*sl 0.15 + 0.020*sl sn to qn t plh 0.39 0.33 + 0.030*sl 0.35 + 0.026*sl 0.36 + 0.025*sl t phl 0.44 0.40 + 0.023*sl 0.42 + 0.017*sl 0.45 + 0.013*sl t r 0.26 0.16 + 0.053*sl 0.16 + 0.052*sl 0.15 + 0.053*sl t f 0.19 0.15 + 0.024*sl 0.15 + 0.021*sl 0.17 + 0.020*sl rn to qn t plh 0.65 0.59 + 0.030*sl 0.60 + 0.026*sl 0.61 + 0.025*sl t phl 0.50 0.46 + 0.022*sl 0.47 + 0.016*sl 0.51 + 0.013*sl t r 0.26 0.16 + 0.052*sl 0.16 + 0.052*sl 0.15 + 0.053*sl t f 0.18 0.13 + 0.024*sl 0.14 + 0.021*sl 0.14 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-444 sec asic lds2 d latch with active high, synchronous clear logic symbol schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 pulse width high (g) t pwh 0.61 0.99 input setup time (d to g) t su 0.31 0.55 input hold time (d to g) t hd 0.15 0.33 input setup time (crn to g) t su 0.31 0.55 input hold time (crn to g) t hd 0.15 0.33 d crn g q qn qn q d g gb g gb g g gb crn truth table cell data d crn g q (n+1) qn (n+1) 01101 11110 x x 0 q (n) qn (n) x0101 input load (sl) gate count kg80 d crn g 5.0 0.9 0.8 0.9 KGM80 d crn g 5.0 1.0 1.0 1.0
sec asic 3-445 kg80/KGM80 lds2 d latch with active high, synchronous clear switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 lds2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.61 0.53 + 0.040*sl 0.53 + 0.041*sl 0.53 + 0.042*sl t phl 0.59 0.53 + 0.029*sl 0.54 + 0.025*sl 0.55 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.041*sl 0.07 + 0.042*sl crn to q t plh 0.59 0.51 + 0.040*sl 0.51 + 0.041*sl 0.50 + 0.042*sl t phl 0.62 0.56 + 0.029*sl 0.57 + 0.025*sl 0.58 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl g to q t plh 0.63 0.55 + 0.040*sl 0.55 + 0.041*sl 0.54 + 0.042*sl t phl 0.53 0.47 + 0.030*sl 0.48 + 0.025*sl 0.49 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl d to qn t plh 0.51 0.43 + 0.042*sl 0.43 + 0.042*sl 0.43 + 0.042*sl t phl 0.48 0.41 + 0.031*sl 0.43 + 0.026*sl 0.44 + 0.023*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.08 + 0.041*sl crn to qn t plh 0.54 0.46 + 0.042*sl 0.46 + 0.041*sl 0.46 + 0.042*sl t phl 0.45 0.39 + 0.031*sl 0.40 + 0.026*sl 0.42 + 0.023*sl t r 0.27 0.10 + 0.087*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.18 0.10 + 0.042*sl 0.10 + 0.039*sl 0.09 + 0.041*sl g to qn t plh 0.45 0.37 + 0.042*sl 0.37 + 0.042*sl 0.37 + 0.042*sl t phl 0.50 0.43 + 0.031*sl 0.45 + 0.026*sl 0.46 + 0.023*sl t r 0.27 0.09 + 0.087*sl 0.09 + 0.090*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.08 + 0.041*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-446 sec asic lds2 d latch with active high, synchronous clear switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 lds2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.84 0.75 + 0.049*sl 0.74 + 0.050*sl 0.74 + 0.050*sl t phl 0.83 0.77 + 0.032*sl 0.78 + 0.026*sl 0.81 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl crn to q t plh 0.84 0.74 + 0.049*sl 0.74 + 0.050*sl 0.73 + 0.050*sl t phl 0.87 0.81 + 0.033*sl 0.83 + 0.025*sl 0.85 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl g to q t plh 0.89 0.79 + 0.049*sl 0.79 + 0.050*sl 0.79 + 0.050*sl t phl 0.74 0.68 + 0.032*sl 0.70 + 0.026*sl 0.72 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl d to qn t plh 0.71 0.61 + 0.051*sl 0.61 + 0.050*sl 0.62 + 0.050*sl t phl 0.65 0.58 + 0.035*sl 0.61 + 0.026*sl 0.64 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.11 + 0.042*sl crn to qn t plh 0.75 0.65 + 0.051*sl 0.65 + 0.050*sl 0.66 + 0.050*sl t phl 0.64 0.57 + 0.035*sl 0.59 + 0.026*sl 0.63 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl g to qn t plh 0.62 0.52 + 0.051*sl 0.52 + 0.050*sl 0.53 + 0.050*sl t phl 0.69 0.63 + 0.034*sl 0.65 + 0.026*sl 0.68 + 0.023*sl t r 0.34 0.13 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-447 kg80/KGM80 lds6 d latch with active low, synchronous clear logic symbol schematic diagram timing requirements (typical process, 25 c, 5v, 3.3v, unit = ns) parameter symbol kg80 KGM80 pulse width low (gn) t pwl 0.61 0.99 input setup time (d to gn) t su 0.42 0.74 input hold time (d to gn) t hd 0.15 0.33 input setup time (crn to gn) t su 0.42 0.74 input hold time (crn to gn) t hd 0.15 0.33 d crn gn q qn qn q d gnb gn gn gnb gn gn gnb crn truth table cell data d crn gn q (n+1) qn (n+1) 01001 11010 x x 1 q (n) qn (n) x0001 input load (sl) gate count kg80 d crn gn 5.0 0.9 0.8 0.9 KGM80 d crn gn 5.0 1.0 1.0 1.0
kg80/KGM80 3-448 sec asic lds6 d latch with active low, synchronous clear switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 lds6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.61 0.53 + 0.040*sl 0.53 + 0.041*sl 0.53 + 0.042*sl t phl 0.59 0.53 + 0.029*sl 0.54 + 0.025*sl 0.55 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.041*sl 0.08 + 0.040*sl 0.07 + 0.042*sl crn to q t plh 0.59 0.51 + 0.040*sl 0.51 + 0.041*sl 0.51 + 0.042*sl t phl 0.62 0.56 + 0.029*sl 0.57 + 0.025*sl 0.58 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl gn to q t plh 0.69 0.61 + 0.040*sl 0.60 + 0.041*sl 0.60 + 0.042*sl t phl 0.63 0.57 + 0.030*sl 0.58 + 0.025*sl 0.59 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.041*sl 0.07 + 0.042*sl d to qn t plh 0.51 0.43 + 0.042*sl 0.43 + 0.042*sl 0.43 + 0.042*sl t phl 0.48 0.41 + 0.031*sl 0.43 + 0.026*sl 0.44 + 0.023*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.08 + 0.041*sl crn to qn t plh 0.54 0.46 + 0.042*sl 0.46 + 0.041*sl 0.46 + 0.042*sl t phl 0.46 0.40 + 0.031*sl 0.41 + 0.026*sl 0.43 + 0.023*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.08 + 0.041*sl gn to qn t plh 0.56 0.47 + 0.042*sl 0.47 + 0.042*sl 0.47 + 0.042*sl t phl 0.55 0.49 + 0.031*sl 0.50 + 0.025*sl 0.52 + 0.024*sl t r 0.27 0.09 + 0.087*sl 0.09 + 0.090*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.042*sl 0.10 + 0.040*sl 0.08 + 0.041*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-449 kg80/KGM80 lds6 d latch with active low, synchronous clear switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 lds6 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d to q t plh 0.85 0.75 + 0.049*sl 0.75 + 0.050*sl 0.74 + 0.050*sl t phl 0.83 0.77 + 0.033*sl 0.79 + 0.026*sl 0.81 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.044*sl 0.11 + 0.042*sl 0.10 + 0.042*sl crn to q t plh 0.84 0.74 + 0.049*sl 0.74 + 0.050*sl 0.74 + 0.050*sl t phl 0.87 0.81 + 0.032*sl 0.83 + 0.026*sl 0.85 + 0.023*sl t r 0.34 0.13 + 0.104*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl gn to q t plh 0.94 0.84 + 0.047*sl 0.84 + 0.050*sl 0.84 + 0.050*sl t phl 0.88 0.81 + 0.033*sl 0.83 + 0.026*sl 0.85 + 0.023*sl t r 0.34 0.13 + 0.103*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.10 + 0.042*sl d to qn t plh 0.71 0.61 + 0.051*sl 0.61 + 0.050*sl 0.62 + 0.050*sl t phl 0.65 0.58 + 0.035*sl 0.61 + 0.026*sl 0.64 + 0.023*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.12 + 0.042*sl crn to qn t plh 0.75 0.65 + 0.051*sl 0.65 + 0.050*sl 0.66 + 0.050*sl t phl 0.64 0.57 + 0.035*sl 0.60 + 0.026*sl 0.63 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl gn to qn t plh 0.76 0.65 + 0.051*sl 0.66 + 0.050*sl 0.66 + 0.050*sl t phl 0.74 0.68 + 0.033*sl 0.70 + 0.026*sl 0.73 + 0.023*sl t r 0.34 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.12 + 0.044*sl 0.12 + 0.041*sl 0.11 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-450 sec asic ls0/ls0d2 sr latch with 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 ls0 ls0d2 ls0 ls0d2 rn sn rn sn 0.8 0.5 1.5 1.5 5.0 6.0 KGM80 ls0 ls0d2 ls0 ls0d2 rn sn rn sn 1.0 1.0 2.0 2.0 5.0 6.0 q qn rn sn sn qn q rn truth table * both q and qn outputs will remain high during rn and sn are low. however, if rn and sn go high simultaneously, the output states are unpredictable. rn sn q (n+1) qn (n+1) 00* * 1010 0101 1 1 q (n) qn (n)
sec asic 3-451 kg80/KGM80 ls0/ls0d2 sr latch with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ls0 kg80 ls0d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* sn to q t plh 0.24 0.16 + 0.042*sl 0.16 + 0.040*sl 0.16 + 0.041*sl t phl 0.17 0.09 + 0.041*sl 0.11 + 0.034*sl 0.11 + 0.034*sl t r 0.36 0.21 + 0.077*sl 0.19 + 0.085*sl 0.17 + 0.088*sl t f 0.33 0.22 + 0.055*sl 0.20 + 0.062*sl 0.18 + 0.065*sl rn to q t phl 0.45 0.29 + 0.081*sl 0.29 + 0.080*sl 0.29 + 0.081*sl t f 0.29 0.14 + 0.077*sl 0.13 + 0.079*sl 0.13 + 0.080*sl sn to qn t phl 0.43 0.25 + 0.090*sl 0.26 + 0.088*sl 0.25 + 0.089*sl t f 0.32 0.15 + 0.082*sl 0.15 + 0.084*sl 0.15 + 0.084*sl rn to qn t plh 0.28 0.20 + 0.039*sl 0.20 + 0.040*sl 0.19 + 0.041*sl t phl 0.17 0.09 + 0.038*sl 0.10 + 0.034*sl 0.10 + 0.034*sl t r 0.43 0.28 + 0.078*sl 0.26 + 0.084*sl 0.23 + 0.088*sl t f 0.32 0.21 + 0.058*sl 0.19 + 0.064*sl 0.17 + 0.066*sl *g 1 sl 2 *g 2 2 sl 7 *g 3 7 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* sn to q t plh 0.23 0.19 + 0.022*sl 0.19 + 0.020*sl 0.19 + 0.020*sl t phl 0.12 0.08 + 0.022*sl 0.09 + 0.019*sl 0.10 + 0.017*sl t r 0.33 0.26 + 0.038*sl 0.25 + 0.040*sl 0.23 + 0.042*sl t f 0.25 0.19 + 0.028*sl 0.19 + 0.029*sl 0.17 + 0.032*sl rn to q t phl 0.37 0.28 + 0.045*sl 0.28 + 0.044*sl 0.28 + 0.044*sl t f 0.22 0.13 + 0.042*sl 0.13 + 0.041*sl 0.13 + 0.042*sl sn to qn t phl 0.37 0.28 + 0.044*sl 0.28 + 0.044*sl 0.28 + 0.044*sl t f 0.22 0.13 + 0.042*sl 0.13 + 0.041*sl 0.13 + 0.042*sl rn to qn t plh 0.23 0.19 + 0.021*sl 0.19 + 0.020*sl 0.19 + 0.020*sl t phl 0.12 0.08 + 0.021*sl 0.09 + 0.019*sl 0.09 + 0.017*sl t r 0.33 0.26 + 0.036*sl 0.25 + 0.040*sl 0.23 + 0.042*sl t f 0.25 0.19 + 0.028*sl 0.19 + 0.029*sl 0.17 + 0.032*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-452 sec asic ls0/ls0d2 sr latch with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ls0 KGM80 ls0d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* sn to q t plh 0.30 0.20 + 0.051*sl 0.20 + 0.049*sl 0.20 + 0.050*sl t phl 0.21 0.12 + 0.044*sl 0.14 + 0.038*sl 0.15 + 0.037*sl t r 0.45 0.25 + 0.100*sl 0.24 + 0.105*sl 0.21 + 0.108*sl t f 0.36 0.23 + 0.066*sl 0.22 + 0.070*sl 0.19 + 0.073*sl rn to q t phl 0.58 0.38 + 0.099*sl 0.39 + 0.098*sl 0.39 + 0.097*sl t f 0.34 0.18 + 0.084*sl 0.17 + 0.086*sl 0.16 + 0.087*sl sn to qn t phl 0.55 0.33 + 0.109*sl 0.34 + 0.107*sl 0.34 + 0.107*sl t f 0.38 0.20 + 0.091*sl 0.19 + 0.093*sl 0.19 + 0.094*sl rn to qn t plh 0.35 0.25 + 0.050*sl 0.25 + 0.049*sl 0.25 + 0.050*sl t phl 0.22 0.13 + 0.042*sl 0.15 + 0.038*sl 0.15 + 0.037*sl t r 0.54 0.33 + 0.100*sl 0.32 + 0.106*sl 0.29 + 0.108*sl t f 0.36 0.23 + 0.067*sl 0.21 + 0.072*sl 0.19 + 0.074*sl *g 1 sl 3 *g 2 3 sl 11 *g 3 11 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* sn to q t plh 0.29 0.24 + 0.026*sl 0.24 + 0.025*sl 0.24 + 0.025*sl t phl 0.16 0.12 + 0.023*sl 0.13 + 0.020*sl 0.14 + 0.019*sl t r 0.40 0.31 + 0.048*sl 0.30 + 0.051*sl 0.28 + 0.053*sl t f 0.27 0.20 + 0.035*sl 0.20 + 0.034*sl 0.19 + 0.036*sl rn to q t phl 0.48 0.37 + 0.054*sl 0.37 + 0.054*sl 0.37 + 0.053*sl t f 0.26 0.17 + 0.045*sl 0.17 + 0.046*sl 0.17 + 0.047*sl sn to qn t phl 0.48 0.37 + 0.055*sl 0.37 + 0.054*sl 0.37 + 0.053*sl t f 0.26 0.17 + 0.045*sl 0.17 + 0.046*sl 0.17 + 0.047*sl rn to qn t plh 0.29 0.24 + 0.026*sl 0.24 + 0.025*sl 0.24 + 0.025*sl t phl 0.16 0.12 + 0.023*sl 0.13 + 0.020*sl 0.14 + 0.019*sl t r 0.40 0.31 + 0.048*sl 0.30 + 0.051*sl 0.28 + 0.053*sl t f 0.27 0.20 + 0.034*sl 0.20 + 0.034*sl 0.18 + 0.036*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-453 kg80/KGM80 ls1 sr latch with separate inputs logic symbol cell data schematic diagram input load (sl) gate count kg80 rn rn1 rn2 sn sn1 sn2 4.0 0.8 0.6 0.6 0.9 0.6 0.6 KGM80 rn rn1 rn2 sn sn1 sn2 4.0 1.0 0.7 0.7 1.0 1.0 1.0 q qn sn1 rn1 rn2 sn2 sn rn rn1 q qn rn rn2 sn1 sn sn2 truth table rn* = rn1 + rn2, sn* = sn1 + sn2 * both q and qn outputs will be unknown when rn (rn*) and sn (sn*) are low. rn sn rn* sn* q (n+1) qn (n+1) 00xx * * x00x* * xx00* * 0xx0* * 101x10 01x101 1x1010 x10101 1111q (n)qn (n)
kg80/KGM80 3-454 sec asic ls1 sr latch with separate inputs switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ls1 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* sn1 to q t plh 0.39 0.25 + 0.070*sl 0.25 + 0.070*sl 0.25 + 0.071*sl t phl 0.24 0.15 + 0.046*sl 0.15 + 0.045*sl 0.15 + 0.045*sl t r 0.72 0.41 + 0.155*sl 0.40 + 0.160*sl 0.38 + 0.163*sl t f 0.47 0.30 + 0.085*sl 0.29 + 0.089*sl 0.26 + 0.093*sl sn2 to q t plh 0.39 0.25 + 0.070*sl 0.25 + 0.071*sl 0.25 + 0.071*sl t phl 0.27 0.18 + 0.045*sl 0.18 + 0.045*sl 0.18 + 0.045*sl t r 0.72 0.41 + 0.155*sl 0.40 + 0.160*sl 0.38 + 0.163*sl t f 0.53 0.36 + 0.084*sl 0.35 + 0.089*sl 0.32 + 0.092*sl sn to q t plh 0.31 0.23 + 0.040*sl 0.23 + 0.041*sl 0.23 + 0.041*sl t phl 0.26 0.17 + 0.047*sl 0.17 + 0.045*sl 0.17 + 0.045*sl t r 0.50 0.34 + 0.078*sl 0.32 + 0.085*sl 0.30 + 0.089*sl t f 0.46 0.29 + 0.085*sl 0.28 + 0.091*sl 0.26 + 0.093*sl rn1 to q t phl 0.66 0.42 + 0.116*sl 0.42 + 0.118*sl 0.42 + 0.118*sl t f 0.49 0.27 + 0.111*sl 0.27 + 0.112*sl 0.26 + 0.113*sl rn2 to q t phl 0.66 0.42 + 0.118*sl 0.42 + 0.118*sl 0.42 + 0.118*sl t f 0.49 0.27 + 0.110*sl 0.27 + 0.112*sl 0.26 + 0.113*sl rn to q t phl 0.57 0.39 + 0.090*sl 0.40 + 0.088*sl 0.40 + 0.088*sl t f 0.46 0.26 + 0.100*sl 0.26 + 0.102*sl 0.25 + 0.103*sl sn1 to qn t phl 0.66 0.42 + 0.117*sl 0.42 + 0.118*sl 0.42 + 0.118*sl t f 0.49 0.27 + 0.111*sl 0.27 + 0.112*sl 0.26 + 0.113*sl sn2 to qn t phl 0.66 0.42 + 0.118*sl 0.42 + 0.118*sl 0.42 + 0.118*sl t f 0.49 0.27 + 0.110*sl 0.27 + 0.112*sl 0.26 + 0.113*sl sn to qn t phl 0.57 0.39 + 0.089*sl 0.40 + 0.088*sl 0.40 + 0.088*sl t f 0.46 0.26 + 0.100*sl 0.26 + 0.102*sl 0.25 + 0.103*sl rn1 to qn t plh 0.39 0.25 + 0.070*sl 0.25 + 0.070*sl 0.25 + 0.071*sl t phl 0.24 0.15 + 0.046*sl 0.15 + 0.045*sl 0.15 + 0.045*sl t r 0.72 0.41 + 0.154*sl 0.40 + 0.160*sl 0.38 + 0.163*sl t f 0.47 0.30 + 0.085*sl 0.29 + 0.089*sl 0.27 + 0.093*sl rn2 to qn t plh 0.39 0.26 + 0.070*sl 0.25 + 0.071*sl 0.25 + 0.071*sl t phl 0.27 0.18 + 0.045*sl 0.18 + 0.045*sl 0.18 + 0.045*sl t r 0.72 0.41 + 0.156*sl 0.40 + 0.160*sl 0.38 + 0.163*sl t f 0.53 0.36 + 0.084*sl 0.35 + 0.089*sl 0.32 + 0.092*sl rn to qn t plh 0.31 0.23 + 0.040*sl 0.23 + 0.041*sl 0.23 + 0.041*sl t phl 0.26 0.17 + 0.046*sl 0.17 + 0.045*sl 0.17 + 0.045*sl t r 0.50 0.34 + 0.078*sl 0.32 + 0.085*sl 0.30 + 0.088*sl t f 0.47 0.30 + 0.085*sl 0.28 + 0.091*sl 0.26 + 0.093*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-455 kg80/KGM80 ls1 sr latch with separate inputs switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ls1 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* sn1 to q t plh 0.54 0.35 + 0.095*sl 0.35 + 0.094*sl 0.35 + 0.094*sl t phl 0.30 0.20 + 0.052*sl 0.20 + 0.051*sl 0.20 + 0.051*sl t r 1.01 0.60 + 0.202*sl 0.59 + 0.207*sl 0.58 + 0.208*sl t f 0.56 0.37 + 0.099*sl 0.36 + 0.103*sl 0.33 + 0.105*sl sn2 to q t plh 0.57 0.37 + 0.096*sl 0.38 + 0.095*sl 0.38 + 0.094*sl t phl 0.34 0.24 + 0.051*sl 0.24 + 0.051*sl 0.24 + 0.051*sl t r 1.01 0.60 + 0.203*sl 0.59 + 0.207*sl 0.58 + 0.208*sl t f 0.63 0.43 + 0.097*sl 0.42 + 0.102*sl 0.39 + 0.105*sl sn to q t plh 0.40 0.30 + 0.050*sl 0.31 + 0.050*sl 0.31 + 0.050*sl t phl 0.35 0.24 + 0.053*sl 0.25 + 0.051*sl 0.25 + 0.051*sl t r 0.63 0.43 + 0.101*sl 0.42 + 0.106*sl 0.39 + 0.109*sl t f 0.56 0.36 + 0.100*sl 0.35 + 0.103*sl 0.33 + 0.105*sl rn1 to q t phl 0.91 0.61 + 0.153*sl 0.61 + 0.153*sl 0.61 + 0.153*sl t f 0.61 0.36 + 0.123*sl 0.36 + 0.125*sl 0.35 + 0.126*sl rn2 to q t phl 0.94 0.64 + 0.154*sl 0.64 + 0.153*sl 0.64 + 0.153*sl t f 0.61 0.36 + 0.122*sl 0.36 + 0.125*sl 0.35 + 0.126*sl rn to q t phl 0.77 0.56 + 0.107*sl 0.56 + 0.106*sl 0.56 + 0.106*sl t f 0.57 0.34 + 0.112*sl 0.34 + 0.113*sl 0.33 + 0.114*sl sn1 to qn t phl 0.91 0.61 + 0.153*sl 0.61 + 0.153*sl 0.61 + 0.153*sl t f 0.61 0.37 + 0.122*sl 0.36 + 0.125*sl 0.35 + 0.126*sl sn2 to qn t phl 0.94 0.63 + 0.154*sl 0.64 + 0.153*sl 0.64 + 0.153*sl t f 0.61 0.37 + 0.122*sl 0.36 + 0.125*sl 0.35 + 0.126*sl sn to qn t phl 0.77 0.56 + 0.108*sl 0.56 + 0.106*sl 0.56 + 0.106*sl t f 0.57 0.34 + 0.112*sl 0.34 + 0.113*sl 0.34 + 0.114*sl rn1 to qn t plh 0.54 0.35 + 0.095*sl 0.35 + 0.094*sl 0.36 + 0.094*sl t phl 0.30 0.20 + 0.052*sl 0.20 + 0.051*sl 0.20 + 0.051*sl t r 1.01 0.61 + 0.202*sl 0.59 + 0.207*sl 0.58 + 0.208*sl t f 0.57 0.37 + 0.098*sl 0.36 + 0.103*sl 0.33 + 0.105*sl rn2 to qn t plh 0.57 0.38 + 0.096*sl 0.38 + 0.095*sl 0.38 + 0.094*sl t phl 0.34 0.24 + 0.051*sl 0.24 + 0.051*sl 0.24 + 0.051*sl t r 1.01 0.61 + 0.203*sl 0.60 + 0.207*sl 0.58 + 0.208*sl t f 0.63 0.43 + 0.097*sl 0.42 + 0.102*sl 0.39 + 0.105*sl rn to qn t plh 0.40 0.30 + 0.050*sl 0.30 + 0.050*sl 0.31 + 0.050*sl t phl 0.35 0.24 + 0.053*sl 0.25 + 0.051*sl 0.25 + 0.051*sl t r 0.64 0.43 + 0.102*sl 0.42 + 0.106*sl 0.39 + 0.109*sl t f 0.56 0.36 + 0.101*sl 0.35 + 0.103*sl 0.33 + 0.105*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-456 sec asic ls2 sr latch with common inputs logic symbol cell data schematic diagram input load (sl) gate count kg80 gn rn sn 5.0 1.1 0.8 0.8 KGM80 gn rn sn 5.0 2.1 1.0 1.0 gn q qn rn sn sn qn q rn gn truth table * both q and qn outputs will be unknown when gn, rn, and sn are low. however, if gn goes high, or rn and sn go high simultaneously, the output states are unpredictable. gn rn sn q (n+1) qn (n+1) 1 x x q (n) qn (n) 0 1 1 q (n) qn (n) 00101 01010 000* *
sec asic 3-457 kg80/KGM80 ls2 sr latch with common inputs switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ls2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* sn to q t plh 0.50 0.41 + 0.042*sl 0.41 + 0.042*sl 0.41 + 0.042*sl t phl 0.34 0.27 + 0.036*sl 0.27 + 0.034*sl 0.27 + 0.034*sl t r 0.36 0.18 + 0.088*sl 0.18 + 0.090*sl 0.17 + 0.091*sl t f 0.26 0.13 + 0.066*sl 0.12 + 0.068*sl 0.12 + 0.069*sl rn to q t phl 0.70 0.52 + 0.091*sl 0.52 + 0.089*sl 0.52 + 0.089*sl t f 0.30 0.14 + 0.082*sl 0.13 + 0.084*sl 0.13 + 0.085*sl gn to q t plh 0.50 0.42 + 0.042*sl 0.42 + 0.042*sl 0.42 + 0.042*sl t phl 0.70 0.52 + 0.091*sl 0.52 + 0.089*sl 0.52 + 0.089*sl t r 0.36 0.20 + 0.080*sl 0.19 + 0.083*sl 0.19 + 0.084*sl t f 0.30 0.13 + 0.085*sl 0.13 + 0.084*sl 0.13 + 0.085*sl sn to qn t phl 0.70 0.52 + 0.090*sl 0.52 + 0.089*sl 0.52 + 0.089*sl t f 0.30 0.14 + 0.083*sl 0.13 + 0.084*sl 0.13 + 0.085*sl rn to qn t plh 0.50 0.42 + 0.042*sl 0.42 + 0.042*sl 0.42 + 0.042*sl t phl 0.35 0.27 + 0.036*sl 0.28 + 0.035*sl 0.28 + 0.034*sl t r 0.36 0.19 + 0.088*sl 0.18 + 0.090*sl 0.18 + 0.091*sl t f 0.26 0.13 + 0.066*sl 0.13 + 0.068*sl 0.12 + 0.069*sl gn to qn t plh 0.51 0.43 + 0.042*sl 0.43 + 0.042*sl 0.43 + 0.042*sl t phl 0.70 0.52 + 0.090*sl 0.52 + 0.089*sl 0.52 + 0.089*sl t r 0.37 0.21 + 0.080*sl 0.20 + 0.083*sl 0.19 + 0.084*sl t f 0.30 0.14 + 0.081*sl 0.13 + 0.085*sl 0.13 + 0.085*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 7, *grou p 3 : 7 < sl < < = =
kg80/KGM80 3-458 sec asic ls2 sr latch with common inputs switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ls2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* sn to q t plh 0.70 0.60 + 0.051*sl 0.60 + 0.050*sl 0.60 + 0.050*sl t phl 0.46 0.38 + 0.040*sl 0.38 + 0.038*sl 0.39 + 0.037*sl t r 0.47 0.26 + 0.106*sl 0.25 + 0.109*sl 0.25 + 0.109*sl t f 0.32 0.17 + 0.072*sl 0.17 + 0.074*sl 0.16 + 0.075*sl rn to q t phl 0.96 0.74 + 0.109*sl 0.75 + 0.107*sl 0.75 + 0.107*sl t f 0.36 0.18 + 0.092*sl 0.18 + 0.093*sl 0.17 + 0.093*sl gn to q t plh 0.68 0.58 + 0.051*sl 0.58 + 0.050*sl 0.59 + 0.050*sl t phl 0.94 0.72 + 0.109*sl 0.73 + 0.107*sl 0.73 + 0.107*sl t r 0.49 0.29 + 0.099*sl 0.28 + 0.103*sl 0.27 + 0.104*sl t f 0.36 0.18 + 0.092*sl 0.18 + 0.093*sl 0.17 + 0.093*sl sn to qn t phl 0.96 0.74 + 0.108*sl 0.74 + 0.107*sl 0.75 + 0.107*sl t f 0.37 0.18 + 0.091*sl 0.18 + 0.093*sl 0.18 + 0.093*sl rn to qn t plh 0.70 0.60 + 0.051*sl 0.60 + 0.050*sl 0.61 + 0.050*sl t phl 0.47 0.39 + 0.040*sl 0.39 + 0.038*sl 0.40 + 0.037*sl t r 0.47 0.26 + 0.106*sl 0.26 + 0.109*sl 0.25 + 0.109*sl t f 0.32 0.18 + 0.071*sl 0.17 + 0.074*sl 0.16 + 0.075*sl gn to qn t plh 0.69 0.59 + 0.051*sl 0.59 + 0.050*sl 0.59 + 0.050*sl t phl 0.94 0.72 + 0.109*sl 0.72 + 0.107*sl 0.73 + 0.107*sl t r 0.50 0.30 + 0.099*sl 0.29 + 0.103*sl 0.28 + 0.104*sl t f 0.36 0.18 + 0.093*sl 0.18 + 0.093*sl 0.18 + 0.093*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 11, *grou p 3 : 11 < sl < < = =
sec asic 3-459 kg80/KGM80 bus holder cell list logic symbol cell name function description busholder bus holder y cell data input load (sl) gate count kg80 y 2.0 3.8 KGM80 y 2.0 4.7
kg80/KGM80 3-460 sec asic internal clock drivers cell list logic symbol cell data cell name function description kg80 ck2 internal clock driver cmos 2ma ck4 internal clock driver cmos 4ma ck8 internal clock driver cmos 8ma ck12 internal clock driver cmos 12ma KGM80 ck2 internal clock driver cmos 2ma ck4 internal clock driver cmos 4ma ck6 internal clock driver cmos 6ma ck8 internal clock driver cmos 8ma input load (sl) gate count kg80 ck2 ck4 ck8 ck12 ck2 ck4 ck8 ck12 aaaa 3.1 3.1 5.5 5.5 1.0 1.0 1.0 1.0 KGM80 ck2 ck4 ck6 ck8 ck2 ck4 ck6 ck8 aaaa 3.5 3.5 6.1 6.1 1.0 1.0 1.0 1.0 a y truth table ay 00 11
sec asic 3-461 kg80/KGM80 ck2/ck4/ck8/ck12 internal clock driver cmos 2/4/8/12ma switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ck2 kg80 ck4 kg80 ck8 kg80 ck12 path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* a to y t plh 0.66 0.20 + 0.005*sl 0.20 + 0.005*sl 0.20 + 0.005*sl t phl 0.60 0.18 + 0.005*sl 0.18 + 0.005*sl 0.18 + 0.005*sl t r 1.07 0.08 + 0.012*sl 0.07 + 0.012*sl 0.06 + 0.012*sl t f 0.82 0.06 + 0.009*sl 0.06 + 0.009*sl 0.05 + 0.009*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* a to y t plh 0.71 0.26 + 0.003*sl 0.26 + 0.003*sl 0.26 + 0.003*sl t phl 0.64 0.23 + 0.003*sl 0.24 + 0.002*sl 0.23 + 0.003*sl t r 1.06 0.09 + 0.006*sl 0.08 + 0.006*sl 0.08 + 0.006*sl t f 0.82 0.08 + 0.004*sl 0.07 + 0.005*sl 0.06 + 0.005*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* a to y t plh 0.70 0.25 + 0.001*sl 0.25 + 0.001*sl 0.25 + 0.001*sl t phl 0.67 0.26 + 0.001*sl 0.26 + 0.001*sl 0.26 + 0.001*sl t r 1.05 0.09 + 0.003*sl 0.08 + 0.003*sl 0.08 + 0.003*sl t f 0.82 0.09 + 0.002*sl 0.08 + 0.002*sl 0.07 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* a to y t plh 0.75 0.31 + 0.001*sl 0.31 + 0.001*sl 0.31 + 0.001*sl t phl 0.72 0.31 + 0.001*sl 0.32 + 0.001*sl 0.32 + 0.001*sl t r 1.06 0.12 + 0.002*sl 0.10 + 0.002*sl 0.09 + 0.002*sl t f 0.83 0.11 + 0.001*sl 0.10 + 0.001*sl 0.09 + 0.002*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
kg80/KGM80 3-462 sec asic ck2/ck4/ck6/ck8 internal clock driver cmos 2/4/6/8ma switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ck2 KGM80 ck4 KGM80 ck6 KGM80 ck8 path parameter delay [ns] sl = 194 delay equations [ns] group1* group2* group3* a to y t plh 1.13 0.28 + 0.004*sl 0.28 + 0.004*sl 0.28 + 0.004*sl t phl 0.93 0.29 + 0.003*sl 0.29 + 0.003*sl 0.29 + 0.003*sl t r 1.95 0.13 + 0.009*sl 0.10 + 0.010*sl 0.09 + 0.010*sl t f 1.30 0.10 + 0.006*sl 0.09 + 0.006*sl 0.09 + 0.006*sl *group1 : sl < 130, *group2 : 130 sl 194, *group3 : 194 < sl < < = = path parameter delay [ns] sl = 385 delay equations [ns] group1* group2* group3* a to y t plh 1.23 0.39 + 0.002*sl 0.39 + 0.002*sl 0.39 + 0.002*sl t phl 1.03 0.39 + 0.002*sl 0.40 + 0.002*sl 0.40 + 0.002*sl t r 1.95 0.17 + 0.005*sl 0.13 + 0.005*sl 0.13 + 0.005*sl t f 1.31 0.16 + 0.003*sl 0.13 + 0.003*sl 0.10 + 0.003*sl *group1 : sl < 257, *group2 : 257 sl 385, *group3 : 385 < sl < < = = path parameter delay [ns] sl = 580 delay equations [ns] group1* group2* group3* a to y t plh 1.17 0.33 + 0.001*sl 0.33 + 0.001*sl 0.33 + 0.001*sl t phl 1.02 0.38 + 0.001*sl 0.38 + 0.001*sl 0.39 + 0.001*sl t r 1.95 0.14 + 0.003*sl 0.12 + 0.003*sl 0.11 + 0.003*sl t f 1.32 0.12 + 0.002*sl 0.13 + 0.002*sl 0.13 + 0.002*sl *group1 : sl < 386, *group2 : 386 sl 580, *group3 : 580 < sl < < = = path parameter delay [ns] sl = 770 delay equations [ns] group1* group2* group3* a to y t plh 1.22 0.38 + 0.001*sl 0.38 + 0.001*sl 0.38 + 0.001*sl t phl 1.08 0.43 + 0.001*sl 0.44 + 0.001*sl 0.45 + 0.001*sl t r 1.95 0.17 + 0.002*sl 0.14 + 0.002*sl 0.13 + 0.002*sl t f 1.33 0.15 + 0.002*sl 0.16 + 0.002*sl 0.15 + 0.002*sl *group1 : sl < 514, *group2 : 514 sl 770, *group3 : 770 < sl < < = =
sec asic 3-463 kg80/KGM80 decoders cell list cell name function description dc4 2 > 4 non-inverting decoder dc4i 2 > 4 inverting decoder dc8i 3 > 8 inverting decoder
kg80/KGM80 3-464 sec asic dc4 2 > 4 non-inverting decoder logic symbol schematic diagram s0 s1 y0 y1 y2 y3 y0 y1 y2 y3 s0 s1 truth table cell data s1 s0 y0 y1 y2 y3 001000 010100 100010 110001 input load (sl) gate count kg80 s0 s1 7.0 2.3 2.6 KGM80 s0 s1 7.0 2.7 3.1
sec asic 3-465 kg80/KGM80 dc4 2 > 4 non-inverting decoder switching characteristics (typical process, 25c , 5v, t r /t f = 0.40ns, sl: standard load) kg80 dc4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s0 to y0 t plh 0.46 0.37 + 0.043*sl 0.37 + 0.042*sl 0.37 + 0.042*sl t phl 0.30 0.25 + 0.028*sl 0.25 + 0.024*sl 0.26 + 0.023*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.09 + 0.090*sl t f 0.15 0.07 + 0.040*sl 0.07 + 0.041*sl 0.06 + 0.042*sl s1 to y0 t plh 0.46 0.37 + 0.043*sl 0.38 + 0.041*sl 0.38 + 0.042*sl t phl 0.33 0.27 + 0.029*sl 0.28 + 0.024*sl 0.29 + 0.023*sl t r 0.27 0.10 + 0.087*sl 0.09 + 0.089*sl 0.09 + 0.090*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl s0 to y1 t plh 0.26 0.17 + 0.043*sl 0.18 + 0.041*sl 0.18 + 0.042*sl t phl 0.26 0.20 + 0.028*sl 0.21 + 0.024*sl 0.22 + 0.023*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.089*sl 0.09 + 0.090*sl t f 0.16 0.09 + 0.035*sl 0.08 + 0.040*sl 0.06 + 0.042*sl s1 to y1 t plh 0.46 0.37 + 0.042*sl 0.38 + 0.042*sl 0.37 + 0.042*sl t phl 0.33 0.27 + 0.029*sl 0.28 + 0.024*sl 0.29 + 0.023*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.07 + 0.042*sl s0 to y2 t plh 0.46 0.36 + 0.046*sl 0.37 + 0.042*sl 0.38 + 0.042*sl t phl 0.30 0.25 + 0.028*sl 0.25 + 0.024*sl 0.26 + 0.023*sl t r 0.28 0.13 + 0.074*sl 0.09 + 0.089*sl 0.09 + 0.090*sl t f 0.15 0.07 + 0.040*sl 0.07 + 0.041*sl 0.06 + 0.042*sl s1 to y2 t plh 0.25 0.17 + 0.043*sl 0.17 + 0.041*sl 0.17 + 0.041*sl t phl 0.29 0.24 + 0.029*sl 0.25 + 0.024*sl 0.25 + 0.023*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.089*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.037*sl 0.09 + 0.039*sl 0.07 + 0.042*sl s0 to y3 t plh 0.26 0.18 + 0.043*sl 0.18 + 0.041*sl 0.18 + 0.042*sl t phl 0.26 0.21 + 0.028*sl 0.21 + 0.024*sl 0.22 + 0.023*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.089*sl 0.09 + 0.090*sl t f 0.16 0.09 + 0.035*sl 0.08 + 0.040*sl 0.07 + 0.042*sl s1 to y3 t plh 0.25 0.17 + 0.043*sl 0.17 + 0.041*sl 0.17 + 0.042*sl t phl 0.30 0.24 + 0.029*sl 0.25 + 0.024*sl 0.26 + 0.023*sl t r 0.28 0.10 + 0.087*sl 0.10 + 0.089*sl 0.09 + 0.090*sl t f 0.17 0.09 + 0.038*sl 0.09 + 0.039*sl 0.07 + 0.042*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-466 sec asic dc4 2 > 4 non-inverting decoder switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 dc4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s0 to y0 t plh 0.61 0.50 + 0.052*sl 0.51 + 0.050*sl 0.51 + 0.050*sl t phl 0.40 0.34 + 0.030*sl 0.36 + 0.024*sl 0.37 + 0.023*sl t r 0.36 0.15 + 0.105*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.18 0.09 + 0.042*sl 0.09 + 0.042*sl 0.08 + 0.043*sl s1 to y0 t plh 0.61 0.50 + 0.052*sl 0.51 + 0.050*sl 0.51 + 0.050*sl t phl 0.45 0.38 + 0.031*sl 0.40 + 0.025*sl 0.42 + 0.023*sl t r 0.36 0.15 + 0.105*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.19 0.11 + 0.042*sl 0.11 + 0.041*sl 0.09 + 0.043*sl s0 to y1 t plh 0.34 0.24 + 0.052*sl 0.24 + 0.050*sl 0.25 + 0.050*sl t phl 0.33 0.27 + 0.030*sl 0.28 + 0.024*sl 0.30 + 0.023*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.18 0.10 + 0.041*sl 0.10 + 0.041*sl 0.08 + 0.043*sl s1 to y1 t plh 0.60 0.50 + 0.052*sl 0.51 + 0.050*sl 0.51 + 0.050*sl t phl 0.44 0.38 + 0.031*sl 0.40 + 0.025*sl 0.42 + 0.023*sl t r 0.35 0.15 + 0.105*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.19 0.11 + 0.042*sl 0.11 + 0.041*sl 0.09 + 0.043*sl s0 to y2 t plh 0.60 0.50 + 0.052*sl 0.51 + 0.050*sl 0.51 + 0.050*sl t phl 0.40 0.34 + 0.030*sl 0.36 + 0.024*sl 0.37 + 0.023*sl t r 0.36 0.15 + 0.105*sl 0.14 + 0.108*sl 0.13 + 0.109*sl t f 0.18 0.09 + 0.043*sl 0.09 + 0.042*sl 0.08 + 0.043*sl s1 to y2 t plh 0.34 0.24 + 0.052*sl 0.25 + 0.050*sl 0.25 + 0.050*sl t phl 0.37 0.31 + 0.031*sl 0.33 + 0.025*sl 0.35 + 0.023*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.108*sl 0.13 + 0.109*sl t f 0.19 0.11 + 0.039*sl 0.11 + 0.041*sl 0.09 + 0.043*sl s0 to y3 t plh 0.35 0.24 + 0.052*sl 0.25 + 0.050*sl 0.25 + 0.050*sl t phl 0.33 0.27 + 0.030*sl 0.28 + 0.024*sl 0.30 + 0.023*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.18 0.10 + 0.041*sl 0.10 + 0.041*sl 0.08 + 0.043*sl s1 to y3 t plh 0.34 0.24 + 0.052*sl 0.25 + 0.050*sl 0.25 + 0.050*sl t phl 0.38 0.31 + 0.031*sl 0.33 + 0.025*sl 0.35 + 0.023*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.19 0.11 + 0.040*sl 0.11 + 0.041*sl 0.09 + 0.043*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-467 kg80/KGM80 dc4i 2 > 4 inverting decoder logic symbol schematic diagram s0 s1 yn0 yn1 yn2 yn3 yn0 yn1 yn2 yn3 s0 s1 truth table cell data s1 s0 yn0 yn1 yn2 yn3 000111 011011 101101 111110 input load (sl) gate count kg80 s0 s1 5.0 2.3 2.6 KGM80 s0 s1 5.0 2.7 3.0
kg80/KGM80 3-468 sec asic dc4i 2 > 4 inverting decoder switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 dc4i path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s0 to yn0 t plh 0.25 0.16 + 0.042*sl 0.17 + 0.041*sl 0.16 + 0.042*sl t phl 0.34 0.26 + 0.039*sl 0.27 + 0.035*sl 0.28 + 0.034*sl t r 0.27 0.11 + 0.082*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.24 0.11 + 0.063*sl 0.10 + 0.066*sl 0.09 + 0.068*sl s1 to yn0 t plh 0.27 0.19 + 0.041*sl 0.19 + 0.041*sl 0.19 + 0.042*sl t phl 0.34 0.27 + 0.038*sl 0.27 + 0.035*sl 0.28 + 0.034*sl t r 0.31 0.14 + 0.084*sl 0.13 + 0.089*sl 0.12 + 0.091*sl t f 0.23 0.11 + 0.061*sl 0.10 + 0.066*sl 0.08 + 0.068*sl s0 to yn1 t plh 0.22 0.12 + 0.046*sl 0.14 + 0.040*sl 0.13 + 0.041*sl t phl 0.15 0.06 + 0.045*sl 0.08 + 0.035*sl 0.09 + 0.034*sl t r 0.32 0.17 + 0.076*sl 0.15 + 0.084*sl 0.12 + 0.088*sl t f 0.29 0.17 + 0.059*sl 0.16 + 0.061*sl 0.13 + 0.065*sl s1 to yn1 t plh 0.28 0.19 + 0.041*sl 0.19 + 0.041*sl 0.19 + 0.042*sl t phl 0.34 0.27 + 0.037*sl 0.27 + 0.035*sl 0.28 + 0.034*sl t r 0.31 0.15 + 0.084*sl 0.13 + 0.089*sl 0.12 + 0.091*sl t f 0.23 0.11 + 0.062*sl 0.10 + 0.066*sl 0.08 + 0.068*sl s0 to yn2 t plh 0.25 0.16 + 0.042*sl 0.17 + 0.041*sl 0.16 + 0.042*sl t phl 0.34 0.26 + 0.039*sl 0.27 + 0.035*sl 0.27 + 0.034*sl t r 0.27 0.11 + 0.082*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.23 0.11 + 0.062*sl 0.10 + 0.066*sl 0.09 + 0.068*sl s1 to yn2 t plh 0.24 0.16 + 0.042*sl 0.16 + 0.040*sl 0.16 + 0.041*sl t phl 0.14 0.05 + 0.041*sl 0.07 + 0.035*sl 0.08 + 0.034*sl t r 0.36 0.21 + 0.074*sl 0.19 + 0.083*sl 0.16 + 0.088*sl t f 0.27 0.15 + 0.056*sl 0.14 + 0.062*sl 0.11 + 0.066*sl s0 to yn3 t plh 0.22 0.12 + 0.046*sl 0.14 + 0.040*sl 0.13 + 0.041*sl t phl 0.15 0.06 + 0.045*sl 0.08 + 0.035*sl 0.09 + 0.034*sl t r 0.32 0.17 + 0.075*sl 0.15 + 0.084*sl 0.12 + 0.088*sl t f 0.29 0.17 + 0.059*sl 0.16 + 0.061*sl 0.13 + 0.065*sl s1 to yn3 t plh 0.24 0.16 + 0.041*sl 0.16 + 0.040*sl 0.16 + 0.041*sl t phl 0.14 0.06 + 0.041*sl 0.07 + 0.035*sl 0.08 + 0.034*sl t r 0.36 0.21 + 0.075*sl 0.19 + 0.083*sl 0.16 + 0.088*sl t f 0.27 0.16 + 0.055*sl 0.14 + 0.062*sl 0.11 + 0.066*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-469 kg80/KGM80 dc4i 2 > 4 inverting decoder switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 dc4i path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s0 to yn0 t plh 0.33 0.22 + 0.051*sl 0.23 + 0.050*sl 0.23 + 0.050*sl t phl 0.43 0.34 + 0.044*sl 0.36 + 0.038*sl 0.37 + 0.037*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.28 0.14 + 0.071*sl 0.14 + 0.072*sl 0.12 + 0.074*sl s1 to yn0 t plh 0.36 0.26 + 0.051*sl 0.26 + 0.050*sl 0.27 + 0.050*sl t phl 0.43 0.35 + 0.042*sl 0.36 + 0.038*sl 0.37 + 0.037*sl t r 0.40 0.18 + 0.105*sl 0.18 + 0.108*sl 0.17 + 0.109*sl t f 0.27 0.13 + 0.070*sl 0.12 + 0.072*sl 0.10 + 0.074*sl s0 to yn1 t plh 0.26 0.15 + 0.055*sl 0.16 + 0.049*sl 0.16 + 0.050*sl t phl 0.18 0.09 + 0.047*sl 0.11 + 0.038*sl 0.12 + 0.037*sl t r 0.38 0.19 + 0.099*sl 0.17 + 0.105*sl 0.14 + 0.108*sl t f 0.31 0.17 + 0.068*sl 0.17 + 0.070*sl 0.13 + 0.073*sl s1 to yn1 t plh 0.37 0.26 + 0.051*sl 0.27 + 0.050*sl 0.27 + 0.050*sl t phl 0.43 0.35 + 0.042*sl 0.36 + 0.038*sl 0.37 + 0.037*sl t r 0.40 0.19 + 0.106*sl 0.18 + 0.108*sl 0.17 + 0.109*sl t f 0.27 0.13 + 0.069*sl 0.12 + 0.072*sl 0.11 + 0.074*sl s0 to yn2 t plh 0.32 0.22 + 0.052*sl 0.23 + 0.050*sl 0.23 + 0.050*sl t phl 0.43 0.34 + 0.045*sl 0.36 + 0.038*sl 0.37 + 0.037*sl t r 0.35 0.14 + 0.105*sl 0.13 + 0.108*sl 0.11 + 0.109*sl t f 0.28 0.14 + 0.070*sl 0.14 + 0.072*sl 0.12 + 0.074*sl s1 to yn2 t plh 0.30 0.19 + 0.052*sl 0.20 + 0.049*sl 0.20 + 0.050*sl t phl 0.18 0.09 + 0.044*sl 0.11 + 0.038*sl 0.11 + 0.037*sl t r 0.43 0.23 + 0.099*sl 0.22 + 0.105*sl 0.18 + 0.108*sl t f 0.29 0.15 + 0.066*sl 0.14 + 0.071*sl 0.11 + 0.074*sl s0 to yn3 t plh 0.26 0.15 + 0.055*sl 0.17 + 0.049*sl 0.16 + 0.050*sl t phl 0.18 0.09 + 0.047*sl 0.11 + 0.038*sl 0.12 + 0.037*sl t r 0.39 0.19 + 0.098*sl 0.17 + 0.105*sl 0.14 + 0.108*sl t f 0.31 0.17 + 0.068*sl 0.17 + 0.070*sl 0.13 + 0.073*sl s1 to yn3 t plh 0.30 0.20 + 0.051*sl 0.20 + 0.049*sl 0.20 + 0.050*sl t phl 0.18 0.09 + 0.044*sl 0.10 + 0.038*sl 0.11 + 0.037*sl t r 0.43 0.23 + 0.099*sl 0.22 + 0.105*sl 0.18 + 0.108*sl t f 0.29 0.15 + 0.067*sl 0.14 + 0.071*sl 0.11 + 0.074*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-470 sec asic dc8i 3 > 8 inverting decoder logic symbol schematic diagram s0 s2 yn0 yn2 yn4 yn6 s1 yn1 yn3 yn5 yn7 yn0 yn1 yn2 yn3 s2 s0 yn4 yn5 yn6 yn7 s1 truth table cell data s0 s1 s2 yn 0 yn 1 yn 2 yn 3 yn 4 yn 5 yn 6 yn 7 00001111111 10010111111 01011011111 11011101111 00111110111 10111111011 01111111101 11111111110 input load (sl) gate count kg80 s0 s1 s2 14.0 3.5 3.2 2.9 KGM80 s0 s1 s2 14.0 4.1 3.8 3.4
sec asic 3-471 kg80/KGM80 dc8i 3 > 8 inverting decoder switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 dc8i (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s0 to yn0 t plh 0.38 0.29 + 0.043*sl 0.29 + 0.042*sl 0.29 + 0.042*sl t phl 0.48 0.38 + 0.047*sl 0.39 + 0.046*sl 0.39 + 0.045*sl t r 0.44 0.27 + 0.084*sl 0.26 + 0.088*sl 0.25 + 0.090*sl t f 0.37 0.19 + 0.088*sl 0.18 + 0.092*sl 0.17 + 0.094*sl s1 to yn0 t plh 0.34 0.26 + 0.042*sl 0.26 + 0.042*sl 0.26 + 0.042*sl t phl 0.46 0.36 + 0.047*sl 0.37 + 0.045*sl 0.37 + 0.045*sl t r 0.38 0.21 + 0.085*sl 0.20 + 0.089*sl 0.19 + 0.090*sl t f 0.37 0.20 + 0.087*sl 0.19 + 0.092*sl 0.18 + 0.094*sl s2 to yn0 t plh 0.29 0.21 + 0.042*sl 0.21 + 0.041*sl 0.21 + 0.042*sl t phl 0.43 0.34 + 0.047*sl 0.34 + 0.045*sl 0.34 + 0.045*sl t r 0.33 0.16 + 0.084*sl 0.15 + 0.089*sl 0.14 + 0.090*sl t f 0.37 0.19 + 0.089*sl 0.19 + 0.092*sl 0.17 + 0.094*sl s0 to yn1 t plh 0.30 0.21 + 0.041*sl 0.21 + 0.041*sl 0.21 + 0.041*sl t phl 0.22 0.13 + 0.047*sl 0.13 + 0.045*sl 0.13 + 0.045*sl t r 0.48 0.32 + 0.078*sl 0.31 + 0.083*sl 0.28 + 0.088*sl t f 0.38 0.21 + 0.084*sl 0.19 + 0.091*sl 0.17 + 0.094*sl s1 to yn1 t plh 0.34 0.26 + 0.042*sl 0.26 + 0.042*sl 0.26 + 0.042*sl t phl 0.46 0.36 + 0.048*sl 0.37 + 0.045*sl 0.37 + 0.045*sl t r 0.38 0.21 + 0.085*sl 0.20 + 0.089*sl 0.19 + 0.090*sl t f 0.37 0.20 + 0.088*sl 0.19 + 0.092*sl 0.17 + 0.094*sl s2 to yn1 t plh 0.29 0.21 + 0.042*sl 0.21 + 0.042*sl 0.21 + 0.042*sl t phl 0.43 0.34 + 0.047*sl 0.34 + 0.045*sl 0.34 + 0.045*sl t r 0.33 0.16 + 0.084*sl 0.15 + 0.089*sl 0.14 + 0.091*sl t f 0.37 0.19 + 0.089*sl 0.19 + 0.092*sl 0.17 + 0.094*sl s0 to yn2 t plh 0.38 0.29 + 0.043*sl 0.29 + 0.042*sl 0.29 + 0.042*sl t phl 0.48 0.38 + 0.047*sl 0.39 + 0.046*sl 0.39 + 0.045*sl t r 0.44 0.27 + 0.084*sl 0.26 + 0.088*sl 0.25 + 0.090*sl t f 0.37 0.19 + 0.088*sl 0.18 + 0.092*sl 0.17 + 0.094*sl s1 to yn2 t plh 0.27 0.19 + 0.041*sl 0.19 + 0.041*sl 0.18 + 0.041*sl t phl 0.22 0.13 + 0.048*sl 0.13 + 0.045*sl 0.13 + 0.045*sl t r 0.42 0.27 + 0.076*sl 0.25 + 0.084*sl 0.22 + 0.088*sl t f 0.39 0.23 + 0.083*sl 0.21 + 0.090*sl 0.18 + 0.093*sl s2 to yn2 t plh 0.29 0.21 + 0.042*sl 0.21 + 0.042*sl 0.21 + 0.042*sl t phl 0.43 0.34 + 0.047*sl 0.34 + 0.045*sl 0.34 + 0.045*sl t r 0.33 0.16 + 0.084*sl 0.15 + 0.089*sl 0.14 + 0.090*sl t f 0.37 0.20 + 0.089*sl 0.19 + 0.092*sl 0.17 + 0.094*sl s0 to yn3 t plh 0.29 0.21 + 0.041*sl 0.21 + 0.041*sl 0.21 + 0.041*sl t phl 0.22 0.13 + 0.047*sl 0.13 + 0.045*sl 0.13 + 0.045*sl t r 0.48 0.32 + 0.078*sl 0.31 + 0.083*sl 0.28 + 0.088*sl t f 0.38 0.21 + 0.085*sl 0.19 + 0.091*sl 0.17 + 0.094*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-472 sec asic dc8i 3 > 8 inverting decoder switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 dc8i (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s1 to yn3 t plh 0.27 0.19 + 0.041*sl 0.19 + 0.041*sl 0.18 + 0.041*sl t phl 0.22 0.13 + 0.048*sl 0.13 + 0.045*sl 0.13 + 0.045*sl t r 0.42 0.27 + 0.076*sl 0.25 + 0.084*sl 0.22 + 0.088*sl t f 0.39 0.23 + 0.082*sl 0.21 + 0.090*sl 0.18 + 0.093*sl s2 to yn3 t plh 0.29 0.21 + 0.042*sl 0.21 + 0.042*sl 0.21 + 0.042*sl t phl 0.43 0.34 + 0.047*sl 0.34 + 0.045*sl 0.34 + 0.045*sl t r 0.33 0.16 + 0.084*sl 0.15 + 0.089*sl 0.14 + 0.090*sl t f 0.37 0.19 + 0.089*sl 0.19 + 0.092*sl 0.17 + 0.094*sl s0 to yn4 t plh 0.38 0.29 + 0.043*sl 0.29 + 0.042*sl 0.29 + 0.042*sl t phl 0.48 0.39 + 0.047*sl 0.39 + 0.046*sl 0.39 + 0.045*sl t r 0.44 0.27 + 0.085*sl 0.26 + 0.088*sl 0.25 + 0.090*sl t f 0.37 0.19 + 0.088*sl 0.18 + 0.093*sl 0.17 + 0.094*sl s1 to yn4 t plh 0.34 0.26 + 0.041*sl 0.26 + 0.041*sl 0.25 + 0.042*sl t phl 0.46 0.36 + 0.048*sl 0.37 + 0.046*sl 0.37 + 0.045*sl t r 0.38 0.21 + 0.084*sl 0.20 + 0.089*sl 0.19 + 0.090*sl t f 0.37 0.20 + 0.087*sl 0.19 + 0.092*sl 0.17 + 0.094*sl s2 to yn4 t plh 0.23 0.14 + 0.045*sl 0.15 + 0.041*sl 0.15 + 0.041*sl t phl 0.21 0.12 + 0.048*sl 0.13 + 0.044*sl 0.12 + 0.045*sl t r 0.37 0.21 + 0.077*sl 0.20 + 0.084*sl 0.17 + 0.088*sl t f 0.40 0.23 + 0.082*sl 0.22 + 0.089*sl 0.19 + 0.093*sl s0 to yn5 t plh 0.30 0.21 + 0.041*sl 0.21 + 0.041*sl 0.21 + 0.041*sl t phl 0.22 0.13 + 0.047*sl 0.13 + 0.045*sl 0.13 + 0.045*sl t r 0.48 0.32 + 0.078*sl 0.31 + 0.083*sl 0.28 + 0.088*sl t f 0.38 0.21 + 0.085*sl 0.19 + 0.091*sl 0.17 + 0.094*sl s1 to yn5 t plh 0.34 0.26 + 0.041*sl 0.26 + 0.041*sl 0.25 + 0.042*sl t phl 0.46 0.36 + 0.048*sl 0.37 + 0.046*sl 0.37 + 0.045*sl t r 0.38 0.21 + 0.084*sl 0.20 + 0.089*sl 0.19 + 0.090*sl t f 0.37 0.20 + 0.088*sl 0.19 + 0.092*sl 0.17 + 0.094*sl s2 to yn5 t plh 0.23 0.14 + 0.045*sl 0.15 + 0.041*sl 0.15 + 0.041*sl t phl 0.21 0.12 + 0.048*sl 0.13 + 0.044*sl 0.12 + 0.045*sl t r 0.37 0.21 + 0.077*sl 0.20 + 0.084*sl 0.17 + 0.088*sl t f 0.40 0.24 + 0.081*sl 0.22 + 0.089*sl 0.19 + 0.093*sl s0 to yn6 t plh 0.38 0.29 + 0.043*sl 0.29 + 0.042*sl 0.30 + 0.042*sl t phl 0.48 0.38 + 0.047*sl 0.39 + 0.046*sl 0.39 + 0.045*sl t r 0.44 0.27 + 0.084*sl 0.26 + 0.088*sl 0.25 + 0.090*sl t f 0.37 0.19 + 0.089*sl 0.18 + 0.093*sl 0.17 + 0.094*sl s1 to yn6 t plh 0.27 0.19 + 0.041*sl 0.19 + 0.041*sl 0.18 + 0.041*sl t phl 0.22 0.13 + 0.048*sl 0.13 + 0.045*sl 0.13 + 0.045*sl t r 0.42 0.27 + 0.076*sl 0.25 + 0.084*sl 0.22 + 0.088*sl t f 0.39 0.22 + 0.083*sl 0.21 + 0.090*sl 0.18 + 0.093*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-473 kg80/KGM80 dc8i 3 > 8 inverting decoder switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 dc8i path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s2 to yn6 t plh 0.23 0.14 + 0.045*sl 0.15 + 0.041*sl 0.15 + 0.041*sl t phl 0.21 0.12 + 0.048*sl 0.13 + 0.044*sl 0.13 + 0.045*sl t r 0.37 0.21 + 0.077*sl 0.19 + 0.084*sl 0.17 + 0.088*sl t f 0.40 0.24 + 0.082*sl 0.22 + 0.089*sl 0.19 + 0.092*sl s0 to yn7 t plh 0.29 0.21 + 0.040*sl 0.21 + 0.041*sl 0.21 + 0.041*sl t phl 0.22 0.13 + 0.047*sl 0.13 + 0.045*sl 0.13 + 0.045*sl t r 0.48 0.32 + 0.079*sl 0.31 + 0.083*sl 0.28 + 0.088*sl t f 0.38 0.20 + 0.086*sl 0.19 + 0.092*sl 0.18 + 0.094*sl s1 to yn7 t plh 0.27 0.19 + 0.041*sl 0.19 + 0.041*sl 0.18 + 0.041*sl t phl 0.22 0.12 + 0.048*sl 0.13 + 0.045*sl 0.13 + 0.045*sl t r 0.42 0.27 + 0.076*sl 0.25 + 0.084*sl 0.22 + 0.088*sl t f 0.39 0.22 + 0.083*sl 0.21 + 0.090*sl 0.18 + 0.093*sl s2 to yn7 t plh 0.23 0.14 + 0.045*sl 0.15 + 0.041*sl 0.15 + 0.041*sl t phl 0.21 0.12 + 0.048*sl 0.13 + 0.044*sl 0.13 + 0.045*sl t r 0.37 0.21 + 0.076*sl 0.19 + 0.084*sl 0.17 + 0.088*sl t f 0.40 0.23 + 0.082*sl 0.22 + 0.089*sl 0.19 + 0.092*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-474 sec asic dc8i 3 > 8 inverting decoder switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 dc8i (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s0 to yn0 t plh 0.51 0.40 + 0.053*sl 0.41 + 0.051*sl 0.41 + 0.050*sl t phl 0.64 0.53 + 0.054*sl 0.54 + 0.052*sl 0.54 + 0.051*sl t r 0.58 0.37 + 0.105*sl 0.36 + 0.107*sl 0.35 + 0.109*sl t f 0.46 0.26 + 0.100*sl 0.25 + 0.103*sl 0.24 + 0.105*sl s1 to yn0 t plh 0.45 0.35 + 0.051*sl 0.36 + 0.050*sl 0.36 + 0.050*sl t phl 0.61 0.50 + 0.055*sl 0.51 + 0.051*sl 0.51 + 0.051*sl t r 0.50 0.29 + 0.105*sl 0.29 + 0.108*sl 0.28 + 0.109*sl t f 0.47 0.27 + 0.100*sl 0.26 + 0.103*sl 0.24 + 0.105*sl s2 to yn0 t plh 0.39 0.29 + 0.052*sl 0.29 + 0.050*sl 0.29 + 0.050*sl t phl 0.57 0.46 + 0.054*sl 0.47 + 0.051*sl 0.47 + 0.051*sl t r 0.44 0.23 + 0.105*sl 0.22 + 0.108*sl 0.21 + 0.109*sl t f 0.47 0.27 + 0.101*sl 0.26 + 0.103*sl 0.23 + 0.105*sl s0 to yn1 t plh 0.38 0.28 + 0.052*sl 0.29 + 0.050*sl 0.29 + 0.050*sl t phl 0.31 0.20 + 0.054*sl 0.21 + 0.051*sl 0.21 + 0.051*sl t r 0.60 0.41 + 0.100*sl 0.39 + 0.105*sl 0.36 + 0.108*sl t f 0.46 0.26 + 0.099*sl 0.25 + 0.103*sl 0.23 + 0.105*sl s1 to yn1 t plh 0.45 0.35 + 0.051*sl 0.36 + 0.050*sl 0.36 + 0.050*sl t phl 0.61 0.50 + 0.055*sl 0.51 + 0.051*sl 0.51 + 0.051*sl t r 0.50 0.29 + 0.105*sl 0.29 + 0.108*sl 0.28 + 0.109*sl t f 0.47 0.27 + 0.100*sl 0.26 + 0.103*sl 0.24 + 0.105*sl s2 to yn1 t plh 0.39 0.29 + 0.051*sl 0.29 + 0.050*sl 0.29 + 0.050*sl t phl 0.57 0.46 + 0.054*sl 0.47 + 0.051*sl 0.47 + 0.051*sl t r 0.44 0.23 + 0.105*sl 0.22 + 0.108*sl 0.21 + 0.109*sl t f 0.47 0.27 + 0.099*sl 0.26 + 0.103*sl 0.23 + 0.105*sl s0 to yn2 t plh 0.51 0.40 + 0.052*sl 0.41 + 0.051*sl 0.41 + 0.050*sl t phl 0.64 0.53 + 0.054*sl 0.54 + 0.052*sl 0.54 + 0.051*sl t r 0.58 0.37 + 0.104*sl 0.36 + 0.107*sl 0.35 + 0.109*sl t f 0.46 0.26 + 0.100*sl 0.25 + 0.103*sl 0.24 + 0.105*sl s1 to yn2 t plh 0.34 0.24 + 0.050*sl 0.25 + 0.050*sl 0.24 + 0.050*sl t phl 0.30 0.19 + 0.054*sl 0.20 + 0.051*sl 0.20 + 0.051*sl t r 0.53 0.33 + 0.100*sl 0.31 + 0.106*sl 0.28 + 0.108*sl t f 0.46 0.27 + 0.097*sl 0.25 + 0.103*sl 0.23 + 0.105*sl s2 to yn2 t plh 0.39 0.29 + 0.051*sl 0.29 + 0.050*sl 0.29 + 0.050*sl t phl 0.57 0.46 + 0.054*sl 0.47 + 0.051*sl 0.47 + 0.051*sl t r 0.44 0.23 + 0.105*sl 0.22 + 0.108*sl 0.21 + 0.109*sl t f 0.47 0.27 + 0.100*sl 0.26 + 0.103*sl 0.24 + 0.105*sl s0 to yn3 t plh 0.38 0.28 + 0.051*sl 0.29 + 0.050*sl 0.29 + 0.050*sl t phl 0.31 0.20 + 0.054*sl 0.21 + 0.051*sl 0.21 + 0.051*sl t r 0.60 0.40 + 0.101*sl 0.39 + 0.105*sl 0.35 + 0.108*sl t f 0.45 0.25 + 0.100*sl 0.24 + 0.104*sl 0.23 + 0.105*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-475 kg80/KGM80 dc8i 3 > 8 inverting decoder switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 dc8i (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s1 to yn3 t plh 0.34 0.24 + 0.050*sl 0.25 + 0.050*sl 0.24 + 0.050*sl t phl 0.30 0.19 + 0.054*sl 0.20 + 0.051*sl 0.19 + 0.051*sl t r 0.53 0.33 + 0.100*sl 0.31 + 0.106*sl 0.28 + 0.109*sl t f 0.46 0.27 + 0.097*sl 0.25 + 0.103*sl 0.23 + 0.105*sl s2 to yn3 t plh 0.39 0.29 + 0.051*sl 0.29 + 0.050*sl 0.29 + 0.050*sl t phl 0.57 0.46 + 0.054*sl 0.47 + 0.051*sl 0.47 + 0.051*sl t r 0.44 0.23 + 0.105*sl 0.22 + 0.108*sl 0.21 + 0.109*sl t f 0.47 0.27 + 0.100*sl 0.26 + 0.103*sl 0.24 + 0.105*sl s0 to yn4 t plh 0.51 0.40 + 0.052*sl 0.41 + 0.051*sl 0.41 + 0.050*sl t phl 0.64 0.53 + 0.054*sl 0.54 + 0.052*sl 0.54 + 0.051*sl t r 0.58 0.37 + 0.105*sl 0.36 + 0.108*sl 0.35 + 0.109*sl t f 0.46 0.26 + 0.101*sl 0.25 + 0.104*sl 0.24 + 0.105*sl s1 to yn4 t plh 0.46 0.35 + 0.051*sl 0.36 + 0.050*sl 0.36 + 0.050*sl t phl 0.61 0.50 + 0.055*sl 0.51 + 0.052*sl 0.51 + 0.051*sl t r 0.50 0.30 + 0.104*sl 0.28 + 0.108*sl 0.28 + 0.109*sl t f 0.47 0.27 + 0.100*sl 0.26 + 0.103*sl 0.24 + 0.105*sl s2 to yn4 t plh 0.29 0.19 + 0.052*sl 0.20 + 0.050*sl 0.19 + 0.050*sl t phl 0.27 0.16 + 0.054*sl 0.17 + 0.050*sl 0.16 + 0.051*sl t r 0.46 0.27 + 0.100*sl 0.25 + 0.105*sl 0.22 + 0.108*sl t f 0.47 0.28 + 0.097*sl 0.26 + 0.102*sl 0.23 + 0.105*sl s0 to yn5 t plh 0.38 0.28 + 0.052*sl 0.29 + 0.050*sl 0.29 + 0.050*sl t phl 0.31 0.20 + 0.054*sl 0.21 + 0.051*sl 0.21 + 0.051*sl t r 0.61 0.40 + 0.100*sl 0.39 + 0.105*sl 0.36 + 0.108*sl t f 0.45 0.25 + 0.100*sl 0.24 + 0.104*sl 0.23 + 0.105*sl s1 to yn5 t plh 0.46 0.35 + 0.051*sl 0.36 + 0.050*sl 0.36 + 0.050*sl t phl 0.61 0.50 + 0.055*sl 0.51 + 0.052*sl 0.51 + 0.051*sl t r 0.50 0.30 + 0.104*sl 0.29 + 0.108*sl 0.27 + 0.109*sl t f 0.47 0.27 + 0.100*sl 0.26 + 0.103*sl 0.24 + 0.105*sl s2 to yn5 t plh 0.29 0.19 + 0.052*sl 0.20 + 0.050*sl 0.19 + 0.050*sl t phl 0.27 0.16 + 0.054*sl 0.17 + 0.051*sl 0.17 + 0.051*sl t r 0.46 0.26 + 0.100*sl 0.25 + 0.105*sl 0.22 + 0.108*sl t f 0.47 0.28 + 0.098*sl 0.27 + 0.102*sl 0.23 + 0.105*sl s0 to yn6 t plh 0.51 0.40 + 0.053*sl 0.41 + 0.051*sl 0.41 + 0.050*sl t phl 0.64 0.53 + 0.055*sl 0.54 + 0.052*sl 0.54 + 0.051*sl t r 0.58 0.37 + 0.105*sl 0.36 + 0.107*sl 0.35 + 0.109*sl t f 0.46 0.26 + 0.101*sl 0.25 + 0.104*sl 0.24 + 0.105*sl s1 to yn6 t plh 0.34 0.24 + 0.050*sl 0.25 + 0.050*sl 0.24 + 0.050*sl t phl 0.29 0.19 + 0.054*sl 0.19 + 0.051*sl 0.20 + 0.051*sl t r 0.53 0.33 + 0.100*sl 0.31 + 0.106*sl 0.28 + 0.109*sl t f 0.46 0.27 + 0.098*sl 0.25 + 0.103*sl 0.24 + 0.105*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-476 sec asic dc8i 3 > 8 inverting decoder switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 dc8i path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* s2 to yn6 t plh 0.29 0.19 + 0.052*sl 0.20 + 0.050*sl 0.19 + 0.050*sl t phl 0.27 0.16 + 0.055*sl 0.17 + 0.051*sl 0.17 + 0.051*sl t r 0.46 0.27 + 0.100*sl 0.25 + 0.105*sl 0.22 + 0.108*sl t f 0.48 0.28 + 0.097*sl 0.27 + 0.102*sl 0.24 + 0.105*sl s0 to yn7 t plh 0.38 0.28 + 0.051*sl 0.29 + 0.050*sl 0.29 + 0.050*sl t phl 0.31 0.20 + 0.053*sl 0.21 + 0.051*sl 0.21 + 0.051*sl t r 0.61 0.40 + 0.101*sl 0.39 + 0.105*sl 0.35 + 0.108*sl t f 0.45 0.25 + 0.101*sl 0.24 + 0.104*sl 0.23 + 0.105*sl s1 to yn7 t plh 0.34 0.24 + 0.050*sl 0.25 + 0.050*sl 0.24 + 0.050*sl t phl 0.29 0.19 + 0.054*sl 0.19 + 0.051*sl 0.20 + 0.051*sl t r 0.53 0.33 + 0.100*sl 0.31 + 0.106*sl 0.28 + 0.109*sl t f 0.46 0.27 + 0.098*sl 0.25 + 0.103*sl 0.24 + 0.105*sl s2 to yn7 t plh 0.29 0.19 + 0.052*sl 0.20 + 0.050*sl 0.19 + 0.050*sl t phl 0.27 0.16 + 0.054*sl 0.17 + 0.051*sl 0.17 + 0.051*sl t r 0.46 0.26 + 0.100*sl 0.25 + 0.105*sl 0.22 + 0.108*sl t f 0.47 0.28 + 0.097*sl 0.27 + 0.102*sl 0.24 + 0.105*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-477 kg80/KGM80 adders cell list cell name function description fa full adder fad2 full adder with 2x drive ha half adder had2 half adder with 2x drive
kg80/KGM80 3-478 sec asic fa/fad2 full adder with 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 fa fad2 fa fad2 ci a b ci a b 1.7 0.8 1.7 1.8 0.8 1.7 7.0 8.0 KGM80 fa fad2 fa fad2 ci a b ci a b 2.0 1.0 2.0 2.1 1.0 2.0 7.0 8.0 ci a b s co a ci b bb b b bb s co cib ci b cib ci ci truth table ci a b s co 00000 10010 00110 10101 01010 11001 01101 11111
sec asic 3-479 kg80/KGM80 fa/fad2 full adder with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fa path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t plh 0.84 0.75 + 0.043*sl 0.75 + 0.041*sl 0.75 + 0.042*sl t phl 0.78 0.70 + 0.037*sl 0.72 + 0.028*sl 0.75 + 0.025*sl t r 0.27 0.10 + 0.086*sl 0.10 + 0.088*sl 0.08 + 0.090*sl t f 0.20 0.12 + 0.043*sl 0.12 + 0.041*sl 0.12 + 0.041*sl b to s t plh 0.74 0.65 + 0.043*sl 0.66 + 0.041*sl 0.66 + 0.042*sl t phl 0.69 0.62 + 0.036*sl 0.64 + 0.028*sl 0.66 + 0.025*sl t r 0.27 0.10 + 0.085*sl 0.10 + 0.088*sl 0.08 + 0.090*sl t f 0.20 0.12 + 0.044*sl 0.12 + 0.041*sl 0.12 + 0.041*sl ci to s t plh 0.47 0.38 + 0.043*sl 0.39 + 0.041*sl 0.39 + 0.041*sl t phl 0.35 0.27 + 0.038*sl 0.29 + 0.028*sl 0.32 + 0.025*sl t r 0.29 0.12 + 0.086*sl 0.11 + 0.087*sl 0.10 + 0.090*sl t f 0.20 0.11 + 0.043*sl 0.12 + 0.041*sl 0.12 + 0.041*sl a to co t plh 0.66 0.58 + 0.042*sl 0.58 + 0.041*sl 0.58 + 0.041*sl t phl 0.73 0.65 + 0.037*sl 0.67 + 0.028*sl 0.69 + 0.025*sl t r 0.29 0.12 + 0.084*sl 0.12 + 0.087*sl 0.10 + 0.090*sl t f 0.22 0.13 + 0.043*sl 0.14 + 0.040*sl 0.14 + 0.040*sl b to co t plh 0.56 0.48 + 0.043*sl 0.48 + 0.041*sl 0.48 + 0.041*sl t phl 0.56 0.50 + 0.033*sl 0.51 + 0.027*sl 0.53 + 0.025*sl t r 0.29 0.13 + 0.084*sl 0.12 + 0.087*sl 0.10 + 0.090*sl t f 0.19 0.10 + 0.045*sl 0.11 + 0.041*sl 0.11 + 0.041*sl ci to co t plh 0.35 0.26 + 0.044*sl 0.27 + 0.042*sl 0.27 + 0.041*sl t phl 0.41 0.34 + 0.039*sl 0.36 + 0.030*sl 0.39 + 0.025*sl t r 0.29 0.13 + 0.080*sl 0.11 + 0.088*sl 0.10 + 0.090*sl t f 0.23 0.14 + 0.046*sl 0.15 + 0.041*sl 0.15 + 0.040*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-480 sec asic fa/fad2 full adder with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 fad2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t plh 0.82 0.77 + 0.023*sl 0.78 + 0.021*sl 0.78 + 0.021*sl t phl 0.77 0.72 + 0.023*sl 0.73 + 0.018*sl 0.75 + 0.015*sl t r 0.18 0.10 + 0.042*sl 0.09 + 0.043*sl 0.08 + 0.044*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.022*sl 0.14 + 0.020*sl b to s t plh 0.72 0.67 + 0.024*sl 0.68 + 0.021*sl 0.68 + 0.021*sl t phl 0.69 0.64 + 0.023*sl 0.65 + 0.018*sl 0.68 + 0.015*sl t r 0.18 0.10 + 0.042*sl 0.10 + 0.042*sl 0.08 + 0.044*sl t f 0.17 0.12 + 0.026*sl 0.13 + 0.022*sl 0.14 + 0.020*sl ci to s t plh 0.47 0.43 + 0.023*sl 0.43 + 0.021*sl 0.44 + 0.021*sl t phl 0.34 0.29 + 0.024*sl 0.30 + 0.018*sl 0.33 + 0.015*sl t r 0.20 0.12 + 0.040*sl 0.12 + 0.042*sl 0.11 + 0.043*sl t f 0.17 0.12 + 0.023*sl 0.12 + 0.023*sl 0.14 + 0.021*sl a to co t plh 0.67 0.62 + 0.024*sl 0.63 + 0.021*sl 0.63 + 0.020*sl t phl 0.72 0.67 + 0.025*sl 0.68 + 0.019*sl 0.71 + 0.015*sl t r 0.21 0.13 + 0.040*sl 0.12 + 0.041*sl 0.11 + 0.043*sl t f 0.19 0.13 + 0.027*sl 0.14 + 0.022*sl 0.16 + 0.020*sl b to co t plh 0.57 0.52 + 0.024*sl 0.53 + 0.021*sl 0.54 + 0.020*sl t phl 0.58 0.53 + 0.023*sl 0.55 + 0.018*sl 0.57 + 0.015*sl t r 0.21 0.13 + 0.040*sl 0.12 + 0.041*sl 0.11 + 0.043*sl t f 0.16 0.12 + 0.024*sl 0.12 + 0.022*sl 0.13 + 0.021*sl ci to co t plh 0.33 0.28 + 0.026*sl 0.29 + 0.022*sl 0.30 + 0.021*sl t phl 0.40 0.36 + 0.025*sl 0.37 + 0.019*sl 0.39 + 0.016*sl t r 0.19 0.11 + 0.037*sl 0.10 + 0.043*sl 0.10 + 0.044*sl t f 0.19 0.14 + 0.028*sl 0.15 + 0.023*sl 0.17 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-481 kg80/KGM80 fa/fad2 full adder with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fa path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t plh 1.16 1.05 + 0.053*sl 1.06 + 0.050*sl 1.06 + 0.050*sl t phl 1.12 1.03 + 0.044*sl 1.07 + 0.030*sl 1.12 + 0.025*sl t r 0.35 0.15 + 0.104*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.26 0.16 + 0.048*sl 0.18 + 0.042*sl 0.19 + 0.041*sl b to s t plh 1.03 0.92 + 0.053*sl 0.93 + 0.050*sl 0.93 + 0.050*sl t phl 0.99 0.90 + 0.044*sl 0.94 + 0.030*sl 1.00 + 0.025*sl t r 0.35 0.15 + 0.104*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.26 0.16 + 0.049*sl 0.18 + 0.042*sl 0.19 + 0.041*sl ci to s t plh 0.64 0.53 + 0.053*sl 0.54 + 0.050*sl 0.54 + 0.050*sl t phl 0.46 0.38 + 0.043*sl 0.41 + 0.030*sl 0.46 + 0.025*sl t r 0.37 0.16 + 0.104*sl 0.15 + 0.107*sl 0.13 + 0.108*sl t f 0.25 0.15 + 0.050*sl 0.17 + 0.042*sl 0.18 + 0.041*sl a to co t plh 0.92 0.82 + 0.052*sl 0.83 + 0.050*sl 0.83 + 0.050*sl t phl 1.04 0.96 + 0.042*sl 0.99 + 0.030*sl 1.04 + 0.025*sl t r 0.37 0.17 + 0.102*sl 0.16 + 0.107*sl 0.14 + 0.109*sl t f 0.26 0.17 + 0.048*sl 0.18 + 0.042*sl 0.19 + 0.041*sl b to co t plh 0.80 0.70 + 0.052*sl 0.71 + 0.050*sl 0.71 + 0.050*sl t phl 0.78 0.71 + 0.038*sl 0.73 + 0.029*sl 0.78 + 0.025*sl t r 0.37 0.17 + 0.103*sl 0.16 + 0.106*sl 0.14 + 0.109*sl t f 0.23 0.13 + 0.048*sl 0.15 + 0.043*sl 0.16 + 0.042*sl ci to co t plh 0.46 0.36 + 0.053*sl 0.36 + 0.050*sl 0.37 + 0.050*sl t phl 0.56 0.47 + 0.047*sl 0.51 + 0.032*sl 0.58 + 0.025*sl t r 0.36 0.15 + 0.105*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.28 0.18 + 0.053*sl 0.21 + 0.042*sl 0.23 + 0.041*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-482 sec asic fa/fad2 full adder with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 fad2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t plh 1.13 1.07 + 0.030*sl 1.08 + 0.026*sl 1.10 + 0.025*sl t phl 1.11 1.05 + 0.030*sl 1.08 + 0.020*sl 1.14 + 0.015*sl t r 0.23 0.13 + 0.053*sl 0.13 + 0.052*sl 0.11 + 0.054*sl t f 0.22 0.16 + 0.031*sl 0.18 + 0.023*sl 0.21 + 0.021*sl b to s t plh 1.00 0.94 + 0.030*sl 0.95 + 0.026*sl 0.96 + 0.025*sl t phl 0.99 0.93 + 0.030*sl 0.96 + 0.020*sl 1.01 + 0.015*sl t r 0.23 0.13 + 0.052*sl 0.13 + 0.052*sl 0.11 + 0.054*sl t f 0.22 0.16 + 0.030*sl 0.18 + 0.024*sl 0.21 + 0.021*sl ci to s t plh 0.65 0.59 + 0.029*sl 0.60 + 0.026*sl 0.61 + 0.025*sl t phl 0.45 0.39 + 0.030*sl 0.42 + 0.020*sl 0.47 + 0.015*sl t r 0.25 0.14 + 0.053*sl 0.15 + 0.052*sl 0.13 + 0.053*sl t f 0.22 0.15 + 0.032*sl 0.18 + 0.024*sl 0.21 + 0.021*sl a to co t plh 0.94 0.88 + 0.030*sl 0.89 + 0.026*sl 0.90 + 0.025*sl t phl 1.04 0.98 + 0.031*sl 1.01 + 0.021*sl 1.07 + 0.016*sl t r 0.26 0.16 + 0.050*sl 0.15 + 0.051*sl 0.13 + 0.053*sl t f 0.24 0.18 + 0.030*sl 0.19 + 0.024*sl 0.22 + 0.021*sl b to co t plh 0.82 0.76 + 0.029*sl 0.77 + 0.026*sl 0.78 + 0.025*sl t phl 0.82 0.77 + 0.027*sl 0.79 + 0.019*sl 0.84 + 0.015*sl t r 0.26 0.16 + 0.050*sl 0.15 + 0.051*sl 0.13 + 0.053*sl t f 0.21 0.15 + 0.027*sl 0.16 + 0.024*sl 0.19 + 0.021*sl ci to co t plh 0.44 0.38 + 0.030*sl 0.39 + 0.026*sl 0.40 + 0.025*sl t phl 0.56 0.50 + 0.032*sl 0.52 + 0.022*sl 0.59 + 0.016*sl t r 0.24 0.13 + 0.053*sl 0.13 + 0.052*sl 0.12 + 0.053*sl t f 0.25 0.18 + 0.034*sl 0.20 + 0.025*sl 0.25 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-483 kg80/KGM80 ha/had2 half adder with 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 ha had2 ha had2 abab 1.7 2.1 1.7 2.3 5.0 6.0 KGM80 ha had2 ha had2 abab 2.0 2.7 2.0 2.7 5.0 6.0 a b s co a s co b truth table absco 0000 0110 1010 1101
kg80/KGM80 3-484 sec asic ha/had2 half adder with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ha kg80 had2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t plh 0.53 0.44 + 0.042*sl 0.44 + 0.041*sl 0.44 + 0.042*sl t phl 0.44 0.37 + 0.036*sl 0.38 + 0.029*sl 0.41 + 0.025*sl t r 0.33 0.16 + 0.086*sl 0.15 + 0.089*sl 0.14 + 0.090*sl t f 0.25 0.17 + 0.043*sl 0.17 + 0.040*sl 0.18 + 0.040*sl b to s t plh 0.41 0.32 + 0.043*sl 0.32 + 0.041*sl 0.32 + 0.042*sl t phl 0.33 0.27 + 0.031*sl 0.28 + 0.027*sl 0.30 + 0.025*sl t r 0.33 0.16 + 0.083*sl 0.15 + 0.089*sl 0.14 + 0.090*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.042*sl 0.13 + 0.041*sl a to co t plh 0.25 0.17 + 0.043*sl 0.17 + 0.041*sl 0.17 + 0.041*sl t phl 0.30 0.24 + 0.029*sl 0.25 + 0.024*sl 0.26 + 0.023*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.17 0.09 + 0.038*sl 0.09 + 0.039*sl 0.07 + 0.041*sl b to co t plh 0.26 0.18 + 0.043*sl 0.18 + 0.041*sl 0.18 + 0.041*sl t phl 0.26 0.20 + 0.028*sl 0.22 + 0.024*sl 0.22 + 0.023*sl t r 0.27 0.10 + 0.087*sl 0.10 + 0.089*sl 0.08 + 0.090*sl t f 0.16 0.09 + 0.036*sl 0.08 + 0.040*sl 0.06 + 0.042*sl [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t plh 0.48 0.43 + 0.024*sl 0.44 + 0.021*sl 0.44 + 0.021*sl t phl 0.40 0.35 + 0.025*sl 0.37 + 0.019*sl 0.40 + 0.016*sl t r 0.18 0.09 + 0.043*sl 0.09 + 0.043*sl 0.08 + 0.044*sl t f 0.20 0.14 + 0.028*sl 0.15 + 0.022*sl 0.17 + 0.020*sl b to s t plh 0.36 0.31 + 0.025*sl 0.31 + 0.022*sl 0.32 + 0.021*sl t phl 0.30 0.26 + 0.022*sl 0.27 + 0.018*sl 0.29 + 0.015*sl t r 0.18 0.11 + 0.036*sl 0.09 + 0.043*sl 0.09 + 0.044*sl t f 0.15 0.10 + 0.027*sl 0.11 + 0.023*sl 0.11 + 0.022*sl a to co t plh 0.24 0.19 + 0.024*sl 0.20 + 0.021*sl 0.21 + 0.021*sl t phl 0.29 0.25 + 0.020*sl 0.27 + 0.015*sl 0.28 + 0.012*sl t r 0.18 0.09 + 0.042*sl 0.09 + 0.043*sl 0.08 + 0.044*sl t f 0.14 0.10 + 0.021*sl 0.10 + 0.019*sl 0.10 + 0.019*sl b to co t plh 0.25 0.21 + 0.024*sl 0.21 + 0.021*sl 0.22 + 0.021*sl t phl 0.27 0.23 + 0.018*sl 0.24 + 0.014*sl 0.25 + 0.012*sl t r 0.18 0.10 + 0.041*sl 0.09 + 0.043*sl 0.08 + 0.044*sl t f 0.13 0.09 + 0.018*sl 0.09 + 0.019*sl 0.09 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-485 kg80/KGM80 ha/had2 half adder with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ha KGM80 had2 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t plh 0.71 0.61 + 0.051*sl 0.61 + 0.050*sl 0.61 + 0.050*sl t phl 0.61 0.52 + 0.042*sl 0.55 + 0.030*sl 0.61 + 0.025*sl t r 0.44 0.23 + 0.105*sl 0.22 + 0.108*sl 0.21 + 0.109*sl t f 0.33 0.23 + 0.047*sl 0.25 + 0.041*sl 0.26 + 0.040*sl b to s t plh 0.54 0.44 + 0.052*sl 0.44 + 0.050*sl 0.44 + 0.050*sl t phl 0.44 0.37 + 0.035*sl 0.39 + 0.028*sl 0.42 + 0.025*sl t r 0.44 0.23 + 0.105*sl 0.23 + 0.108*sl 0.21 + 0.109*sl t f 0.26 0.17 + 0.049*sl 0.18 + 0.043*sl 0.19 + 0.042*sl a to co t plh 0.34 0.24 + 0.052*sl 0.24 + 0.050*sl 0.25 + 0.050*sl t phl 0.38 0.31 + 0.032*sl 0.33 + 0.025*sl 0.35 + 0.023*sl t r 0.35 0.14 + 0.103*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.19 0.11 + 0.041*sl 0.11 + 0.041*sl 0.09 + 0.043*sl b to co t plh 0.34 0.24 + 0.052*sl 0.25 + 0.050*sl 0.25 + 0.050*sl t phl 0.33 0.27 + 0.031*sl 0.29 + 0.024*sl 0.30 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.18 0.10 + 0.041*sl 0.10 + 0.041*sl 0.08 + 0.043*sl [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* a to s t plh 0.64 0.58 + 0.031*sl 0.59 + 0.026*sl 0.60 + 0.025*sl t phl 0.56 0.49 + 0.033*sl 0.52 + 0.022*sl 0.59 + 0.016*sl t r 0.23 0.12 + 0.053*sl 0.13 + 0.052*sl 0.11 + 0.054*sl t f 0.25 0.18 + 0.032*sl 0.21 + 0.024*sl 0.24 + 0.021*sl b to s t plh 0.47 0.40 + 0.031*sl 0.42 + 0.026*sl 0.43 + 0.025*sl t phl 0.41 0.36 + 0.027*sl 0.38 + 0.020*sl 0.43 + 0.015*sl t r 0.23 0.12 + 0.053*sl 0.13 + 0.052*sl 0.11 + 0.053*sl t f 0.19 0.13 + 0.030*sl 0.14 + 0.025*sl 0.18 + 0.022*sl a to co t plh 0.32 0.26 + 0.030*sl 0.28 + 0.026*sl 0.29 + 0.025*sl t phl 0.38 0.34 + 0.022*sl 0.36 + 0.015*sl 0.39 + 0.013*sl t r 0.23 0.12 + 0.052*sl 0.12 + 0.052*sl 0.11 + 0.054*sl t f 0.16 0.11 + 0.024*sl 0.12 + 0.020*sl 0.12 + 0.020*sl b to co t plh 0.33 0.27 + 0.030*sl 0.28 + 0.026*sl 0.29 + 0.025*sl t phl 0.34 0.30 + 0.021*sl 0.32 + 0.015*sl 0.34 + 0.012*sl t r 0.23 0.12 + 0.052*sl 0.12 + 0.052*sl 0.11 + 0.054*sl t f 0.15 0.10 + 0.023*sl 0.11 + 0.020*sl 0.11 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-486 sec asic multiplexers cell list cell name function description mx2 2 > 1 non-inverting mux mx2d3 2 > 1 non-inverting mux with 3x drive mx2x4 4-bit 2 > 1 non-inverting mux ymx2 fast 2 > 1 non-inverting mux ymx2d2 fast 2 > 1 non-inverting mux with 2x drive mx2i 2 > 1 inverting mux mx2id2 2 > 1 inverting mux with 2x drive mx2ia 2 > 1 inverting mux with separate s and sn inputs mx2id2a 2 > 1 inverting mux with separate s and sn inputs, 2x drive mx2ix4 4-bit 2 > 1 inverting mux mx3i 3 > 1 inverting mux mx3id2 3 > 1 inverting mux with 2x drive mx4 4 > 1 non-inverting mux mx4d2 4 > 1 non-inverting mux with 2x drive ymx4 fast 4 > 1 non-inverting mux ymx4d2 fast 4 > 1 non-inverting mux with 2x drive mx5 5 > 1 non-inverting mux mx5d2 5 > 1 non-inverting mux with 2x drive mx8 8 > 1 non-inverting mux mx8d2 8 > 1 non-inverting mux with 2x drive ymx8 fast 8 > 1 non-inverting mux ymx8d2 fast 8 > 1 non-inverting mux with 2x drive
sec asic 3-487 kg80/KGM80 mx2/mx2d3 2 > 1 non-inverting mux with 1x/3x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 mx2 mx2d3 mx2 mx2d3 d0 d1 s d0 d1 s 0.9 0.9 1.4 0.9 0.9 1.4 3.0 4.0 KGM80 mx2 mx2d3 mx2 mx2d3 d0 d1 s d0 d1 s 1.0 1.0 2.1 1.0 1.0 2.1 3.0 4.0 d0 d1 y s s sb y sb s s d0 d1 truth table d0 d1 s y 0x00 1x01 x010 x111
kg80/KGM80 3-488 sec asic mx2/mx2d3 2 > 1 non-inverting mux with 1x/3x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 mx2 kg80 mx2d3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.32 0.23 + 0.044*sl 0.24 + 0.041*sl 0.24 + 0.041*sl t phl 0.38 0.31 + 0.036*sl 0.32 + 0.028*sl 0.35 + 0.025*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.041*sl 0.13 + 0.040*sl d1 to y t plh 0.32 0.23 + 0.043*sl 0.24 + 0.041*sl 0.23 + 0.041*sl t phl 0.38 0.30 + 0.037*sl 0.32 + 0.028*sl 0.35 + 0.025*sl t r 0.28 0.11 + 0.083*sl 0.10 + 0.088*sl 0.08 + 0.090*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.041*sl 0.13 + 0.040*sl s to y t plh 0.38 0.29 + 0.043*sl 0.29 + 0.041*sl 0.29 + 0.042*sl t phl 0.31 0.25 + 0.033*sl 0.26 + 0.028*sl 0.28 + 0.025*sl t r 0.27 0.10 + 0.087*sl 0.10 + 0.089*sl 0.08 + 0.090*sl t f 0.18 0.10 + 0.044*sl 0.10 + 0.042*sl 0.10 + 0.041*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.33 0.29 + 0.017*sl 0.30 + 0.015*sl 0.30 + 0.014*sl t phl 0.39 0.36 + 0.018*sl 0.37 + 0.014*sl 0.38 + 0.012*sl t r 0.17 0.12 + 0.027*sl 0.12 + 0.028*sl 0.12 + 0.028*sl t f 0.19 0.15 + 0.018*sl 0.15 + 0.016*sl 0.17 + 0.014*sl d1 to y t plh 0.32 0.29 + 0.017*sl 0.29 + 0.015*sl 0.30 + 0.014*sl t phl 0.39 0.36 + 0.018*sl 0.37 + 0.014*sl 0.38 + 0.012*sl t r 0.17 0.12 + 0.028*sl 0.12 + 0.028*sl 0.12 + 0.028*sl t f 0.18 0.15 + 0.019*sl 0.15 + 0.016*sl 0.16 + 0.015*sl s to y t plh 0.37 0.34 + 0.017*sl 0.34 + 0.015*sl 0.35 + 0.014*sl t phl 0.32 0.29 + 0.017*sl 0.30 + 0.014*sl 0.31 + 0.011*sl t r 0.17 0.12 + 0.026*sl 0.12 + 0.028*sl 0.11 + 0.028*sl t f 0.16 0.12 + 0.019*sl 0.12 + 0.017*sl 0.14 + 0.015*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-489 kg80/KGM80 mx2/mx2d3 2 > 1 non-inverting mux with 1x/3x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 mx2 KGM80 mx2d3 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.43 0.32 + 0.053*sl 0.33 + 0.050*sl 0.33 + 0.050*sl t phl 0.51 0.42 + 0.043*sl 0.46 + 0.030*sl 0.52 + 0.025*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.26 0.16 + 0.049*sl 0.18 + 0.042*sl 0.19 + 0.041*sl d1 to y t plh 0.42 0.32 + 0.052*sl 0.32 + 0.050*sl 0.32 + 0.050*sl t phl 0.51 0.42 + 0.043*sl 0.46 + 0.030*sl 0.51 + 0.025*sl t r 0.35 0.15 + 0.103*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.26 0.16 + 0.048*sl 0.18 + 0.042*sl 0.19 + 0.041*sl s to y t plh 0.49 0.39 + 0.053*sl 0.39 + 0.050*sl 0.40 + 0.050*sl t phl 0.41 0.34 + 0.038*sl 0.36 + 0.029*sl 0.41 + 0.025*sl t r 0.35 0.15 + 0.104*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.23 0.13 + 0.049*sl 0.15 + 0.043*sl 0.16 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.43 0.39 + 0.021*sl 0.39 + 0.018*sl 0.41 + 0.017*sl t phl 0.55 0.50 + 0.022*sl 0.52 + 0.016*sl 0.56 + 0.012*sl t r 0.22 0.15 + 0.035*sl 0.15 + 0.035*sl 0.15 + 0.035*sl t f 0.24 0.20 + 0.023*sl 0.21 + 0.018*sl 0.24 + 0.015*sl d1 to y t plh 0.42 0.38 + 0.021*sl 0.39 + 0.018*sl 0.40 + 0.017*sl t phl 0.55 0.50 + 0.023*sl 0.52 + 0.016*sl 0.56 + 0.012*sl t r 0.22 0.15 + 0.036*sl 0.15 + 0.035*sl 0.15 + 0.035*sl t f 0.24 0.19 + 0.023*sl 0.21 + 0.018*sl 0.24 + 0.015*sl s to y t plh 0.49 0.45 + 0.021*sl 0.45 + 0.018*sl 0.47 + 0.017*sl t phl 0.45 0.41 + 0.021*sl 0.43 + 0.016*sl 0.46 + 0.012*sl t r 0.22 0.15 + 0.036*sl 0.15 + 0.035*sl 0.15 + 0.035*sl t f 0.21 0.16 + 0.024*sl 0.18 + 0.019*sl 0.21 + 0.016*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-490 sec asic mx2x4 4-bit 2 > 1 non-inverting mux logic symbol cell data input load (sl) gate count kg80 mx2x4 mx2x4 d00 d10 d01 d11 d02 d12 d03 d13 s 0.9 1.0 0.9 1.0 0.9 1.0 0.8 1.0 3.4 9.0 KGM80 mx2x4 mx2x4 d00 d10 d01 d11 d02 d12 d03 d13 s 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 4.4 9.0 y0 y1 y2 y3 d00 d10 d01 d11 d02 d12 d03 d13 s truth table s y0y1y2y3 0 d00 d01 d02 d03 1 d10 d11 d12 d13
sec asic 3-491 kg80/KGM80 mx2x4 4-bit 2 > 1 non-inverting mux switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 mx2x4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d00 to y0 t plh 0.32 0.23 + 0.043*sl 0.23 + 0.041*sl 0.23 + 0.041*sl t phl 0.37 0.30 + 0.037*sl 0.32 + 0.028*sl 0.34 + 0.025*sl t r 0.28 0.11 + 0.083*sl 0.10 + 0.088*sl 0.08 + 0.090*sl t f 0.20 0.12 + 0.043*sl 0.12 + 0.041*sl 0.13 + 0.040*sl d10 to y0 t plh 0.32 0.23 + 0.043*sl 0.24 + 0.041*sl 0.23 + 0.042*sl t phl 0.37 0.30 + 0.037*sl 0.32 + 0.028*sl 0.35 + 0.025*sl t r 0.27 0.11 + 0.081*sl 0.09 + 0.089*sl 0.08 + 0.090*sl t f 0.21 0.12 + 0.043*sl 0.12 + 0.041*sl 0.13 + 0.040*sl s to y0 t plh 0.46 0.37 + 0.043*sl 0.38 + 0.041*sl 0.38 + 0.041*sl t phl 0.33 0.26 + 0.036*sl 0.28 + 0.028*sl 0.30 + 0.025*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.19 0.10 + 0.045*sl 0.11 + 0.041*sl 0.11 + 0.041*sl d01 to y1 t plh 0.32 0.23 + 0.043*sl 0.24 + 0.041*sl 0.24 + 0.041*sl t phl 0.38 0.30 + 0.036*sl 0.32 + 0.028*sl 0.35 + 0.025*sl t r 0.28 0.11 + 0.088*sl 0.11 + 0.087*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.041*sl 0.13 + 0.040*sl d11 to y1 t plh 0.32 0.23 + 0.043*sl 0.24 + 0.041*sl 0.23 + 0.042*sl t phl 0.38 0.30 + 0.037*sl 0.32 + 0.028*sl 0.35 + 0.025*sl t r 0.28 0.11 + 0.083*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.040*sl 0.13 + 0.040*sl s to y1 t plh 0.46 0.37 + 0.043*sl 0.38 + 0.041*sl 0.38 + 0.041*sl t phl 0.33 0.26 + 0.036*sl 0.28 + 0.028*sl 0.30 + 0.025*sl t r 0.28 0.11 + 0.085*sl 0.11 + 0.088*sl 0.09 + 0.090*sl t f 0.19 0.10 + 0.045*sl 0.11 + 0.041*sl 0.12 + 0.041*sl d02 to y2 t plh 0.32 0.23 + 0.043*sl 0.24 + 0.041*sl 0.24 + 0.041*sl t phl 0.38 0.30 + 0.036*sl 0.32 + 0.028*sl 0.35 + 0.025*sl t r 0.28 0.11 + 0.088*sl 0.11 + 0.087*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.041*sl 0.13 + 0.040*sl d12 to y2 t plh 0.32 0.23 + 0.043*sl 0.24 + 0.041*sl 0.24 + 0.041*sl t phl 0.38 0.30 + 0.037*sl 0.32 + 0.028*sl 0.35 + 0.025*sl t r 0.28 0.11 + 0.082*sl 0.10 + 0.089*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.040*sl 0.13 + 0.040*sl s to y2 t plh 0.46 0.37 + 0.043*sl 0.38 + 0.041*sl 0.38 + 0.041*sl t phl 0.33 0.26 + 0.035*sl 0.28 + 0.028*sl 0.30 + 0.025*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.19 0.10 + 0.045*sl 0.11 + 0.041*sl 0.12 + 0.041*sl d03 to y3 t plh 0.32 0.23 + 0.043*sl 0.24 + 0.041*sl 0.23 + 0.042*sl t phl 0.38 0.30 + 0.036*sl 0.32 + 0.028*sl 0.35 + 0.025*sl t r 0.28 0.11 + 0.087*sl 0.11 + 0.087*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.041*sl 0.13 + 0.040*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-492 sec asic mx2x4 4-bit 2 > 1 non-inverting mux switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 mx2x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d13 to y3 t plh 0.32 0.23 + 0.043*sl 0.24 + 0.041*sl 0.24 + 0.041*sl t phl 0.38 0.31 + 0.036*sl 0.32 + 0.028*sl 0.35 + 0.025*sl t r 0.28 0.11 + 0.083*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.040*sl 0.13 + 0.040*sl s to y3 t plh 0.46 0.37 + 0.043*sl 0.38 + 0.041*sl 0.38 + 0.041*sl t phl 0.33 0.26 + 0.036*sl 0.28 + 0.028*sl 0.30 + 0.025*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.19 0.10 + 0.045*sl 0.11 + 0.042*sl 0.12 + 0.041*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-493 kg80/KGM80 mx2x4 4-bit 2 > 1 non-inverting mux switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 mx2x4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d00 to y0 t plh 0.42 0.31 + 0.052*sl 0.32 + 0.050*sl 0.32 + 0.050*sl t phl 0.50 0.42 + 0.043*sl 0.45 + 0.030*sl 0.51 + 0.025*sl t r 0.35 0.14 + 0.103*sl 0.13 + 0.107*sl 0.12 + 0.109*sl t f 0.26 0.16 + 0.049*sl 0.18 + 0.042*sl 0.19 + 0.041*sl d10 to y0 t plh 0.42 0.31 + 0.052*sl 0.32 + 0.050*sl 0.32 + 0.050*sl t phl 0.51 0.42 + 0.043*sl 0.46 + 0.030*sl 0.51 + 0.025*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.107*sl 0.12 + 0.109*sl t f 0.26 0.16 + 0.048*sl 0.18 + 0.042*sl 0.19 + 0.041*sl s to y0 t plh 0.62 0.52 + 0.052*sl 0.52 + 0.050*sl 0.53 + 0.050*sl t phl 0.44 0.36 + 0.042*sl 0.39 + 0.030*sl 0.45 + 0.025*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.24 0.14 + 0.051*sl 0.16 + 0.042*sl 0.17 + 0.041*sl d01 to y1 t plh 0.42 0.32 + 0.053*sl 0.33 + 0.050*sl 0.33 + 0.050*sl t phl 0.51 0.42 + 0.043*sl 0.46 + 0.030*sl 0.51 + 0.025*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.26 0.16 + 0.049*sl 0.18 + 0.042*sl 0.19 + 0.041*sl d11 to y1 t plh 0.42 0.32 + 0.052*sl 0.32 + 0.050*sl 0.33 + 0.050*sl t phl 0.51 0.43 + 0.043*sl 0.46 + 0.030*sl 0.52 + 0.025*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.26 0.17 + 0.048*sl 0.18 + 0.042*sl 0.19 + 0.041*sl s to y1 t plh 0.62 0.52 + 0.052*sl 0.53 + 0.050*sl 0.53 + 0.050*sl t phl 0.45 0.36 + 0.042*sl 0.40 + 0.029*sl 0.45 + 0.025*sl t r 0.37 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.25 0.14 + 0.050*sl 0.17 + 0.042*sl 0.18 + 0.041*sl d02 to y2 t plh 0.42 0.32 + 0.052*sl 0.32 + 0.050*sl 0.33 + 0.050*sl t phl 0.51 0.42 + 0.043*sl 0.46 + 0.030*sl 0.51 + 0.025*sl t r 0.36 0.15 + 0.105*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.26 0.16 + 0.049*sl 0.18 + 0.042*sl 0.19 + 0.041*sl d12 to y2 t plh 0.42 0.32 + 0.052*sl 0.32 + 0.050*sl 0.32 + 0.050*sl t phl 0.51 0.43 + 0.043*sl 0.46 + 0.030*sl 0.52 + 0.025*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.26 0.17 + 0.047*sl 0.18 + 0.042*sl 0.19 + 0.041*sl s to y2 t plh 0.62 0.52 + 0.052*sl 0.53 + 0.050*sl 0.53 + 0.050*sl t phl 0.45 0.36 + 0.042*sl 0.40 + 0.030*sl 0.45 + 0.025*sl t r 0.36 0.16 + 0.102*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.24 0.14 + 0.050*sl 0.17 + 0.042*sl 0.17 + 0.042*sl d03 to y3 t plh 0.42 0.32 + 0.052*sl 0.32 + 0.050*sl 0.32 + 0.050*sl t phl 0.51 0.42 + 0.043*sl 0.46 + 0.030*sl 0.51 + 0.025*sl t r 0.35 0.15 + 0.104*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.26 0.16 + 0.049*sl 0.18 + 0.042*sl 0.19 + 0.041*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-494 sec asic mx2x4 4-bit 2 > 1 non-inverting mux switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 mx2x4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d13 to y3 t plh 0.42 0.32 + 0.052*sl 0.32 + 0.050*sl 0.32 + 0.050*sl t phl 0.51 0.42 + 0.043*sl 0.46 + 0.030*sl 0.52 + 0.025*sl t r 0.35 0.15 + 0.103*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.26 0.17 + 0.048*sl 0.18 + 0.042*sl 0.19 + 0.041*sl s to y3 t plh 0.62 0.52 + 0.053*sl 0.53 + 0.050*sl 0.53 + 0.050*sl t phl 0.45 0.36 + 0.042*sl 0.40 + 0.030*sl 0.45 + 0.025*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.24 0.14 + 0.050*sl 0.17 + 0.042*sl 0.17 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-495 kg80/KGM80 ymx2/ymx2d2 fast 2 > 1 non-inverting mux with 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 ymx2 ymx2d2 ymx2 ymx2d2 d0d1sd0d1s 2.9 2.9 1.5 2.9 2.9 1.5 3.0 30 KGM80 ymx2 ymx2d2 ymx2 ymx2d2 d0d1sd0d1s 3.7 3.7 1.7 3.7 3.7 1.7 3.0 3.0 d0 d1 y s y d0 d1 s truth table d0 d1 s y 0x00 1x01 x010 x111
kg80/KGM80 3-496 sec asic ymx2/ymx2d2 fast 2 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ymx2 kg80 ymx2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.23 0.15 + 0.041*sl 0.15 + 0.041*sl 0.15 + 0.042*sl t phl 0.29 0.23 + 0.027*sl 0.24 + 0.024*sl 0.25 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.15 0.08 + 0.037*sl 0.07 + 0.041*sl 0.06 + 0.042*sl d1 to y t plh 0.24 0.15 + 0.042*sl 0.15 + 0.042*sl 0.15 + 0.042*sl t phl 0.28 0.23 + 0.028*sl 0.24 + 0.024*sl 0.24 + 0.023*sl t r 0.26 0.09 + 0.086*sl 0.08 + 0.090*sl 0.07 + 0.091*sl t f 0.15 0.07 + 0.039*sl 0.07 + 0.041*sl 0.06 + 0.042*sl s to y t plh 0.37 0.29 + 0.042*sl 0.29 + 0.042*sl 0.29 + 0.042*sl t phl 0.39 0.33 + 0.027*sl 0.34 + 0.024*sl 0.35 + 0.023*sl t r 0.26 0.09 + 0.085*sl 0.08 + 0.089*sl 0.07 + 0.091*sl t f 0.14 0.06 + 0.040*sl 0.06 + 0.041*sl 0.05 + 0.042*sl *g 1 sl 2 *g 2 2 sl 7 *g 3 7 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.23 0.19 + 0.021*sl 0.19 + 0.021*sl 0.19 + 0.021*sl t phl 0.29 0.26 + 0.016*sl 0.27 + 0.014*sl 0.28 + 0.012*sl t r 0.18 0.09 + 0.044*sl 0.09 + 0.044*sl 0.08 + 0.045*sl t f 0.13 0.08 + 0.021*sl 0.09 + 0.019*sl 0.08 + 0.020*sl d1 to y t plh 0.23 0.19 + 0.021*sl 0.19 + 0.021*sl 0.19 + 0.021*sl t phl 0.29 0.26 + 0.017*sl 0.27 + 0.013*sl 0.27 + 0.012*sl t r 0.18 0.09 + 0.043*sl 0.09 + 0.044*sl 0.08 + 0.045*sl t f 0.12 0.09 + 0.019*sl 0.09 + 0.019*sl 0.08 + 0.020*sl s to y t plh 0.36 0.32 + 0.021*sl 0.32 + 0.021*sl 0.32 + 0.021*sl t phl 0.39 0.36 + 0.016*sl 0.36 + 0.014*sl 0.37 + 0.012*sl t r 0.17 0.09 + 0.042*sl 0.08 + 0.045*sl 0.08 + 0.046*sl t f 0.12 0.08 + 0.019*sl 0.08 + 0.020*sl 0.08 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-497 kg80/KGM80 ymx2/ymx2d2 fast 2 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ymx2 KGM80 ymx2d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.34 0.24 + 0.051*sl 0.24 + 0.050*sl 0.24 + 0.050*sl t phl 0.37 0.31 + 0.030*sl 0.33 + 0.024*sl 0.34 + 0.023*sl t r 0.33 0.13 + 0.104*sl 0.11 + 0.108*sl 0.11 + 0.109*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.042*sl 0.07 + 0.043*sl d1 to y t plh 0.35 0.25 + 0.050*sl 0.25 + 0.050*sl 0.25 + 0.050*sl t phl 0.37 0.31 + 0.030*sl 0.32 + 0.024*sl 0.33 + 0.023*sl t r 0.33 0.12 + 0.105*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.042*sl 0.07 + 0.043*sl s to y t plh 0.49 0.39 + 0.051*sl 0.39 + 0.050*sl 0.39 + 0.050*sl t phl 0.51 0.45 + 0.029*sl 0.46 + 0.024*sl 0.47 + 0.023*sl t r 0.33 0.12 + 0.107*sl 0.11 + 0.109*sl 0.11 + 0.109*sl t f 0.16 0.08 + 0.042*sl 0.08 + 0.042*sl 0.07 + 0.043*sl *g 1 sl 3 *g 2 3 sl 11 *g 3 11 sl << path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.33 0.28 + 0.026*sl 0.29 + 0.025*sl 0.29 + 0.025*sl t phl 0.39 0.35 + 0.019*sl 0.37 + 0.014*sl 0.39 + 0.012*sl t r 0.23 0.13 + 0.050*sl 0.12 + 0.053*sl 0.11 + 0.054*sl t f 0.15 0.10 + 0.023*sl 0.11 + 0.020*sl 0.11 + 0.020*sl d1 to y t plh 0.34 0.29 + 0.026*sl 0.29 + 0.025*sl 0.29 + 0.025*sl t phl 0.39 0.35 + 0.019*sl 0.36 + 0.014*sl 0.38 + 0.012*sl t r 0.23 0.13 + 0.050*sl 0.12 + 0.053*sl 0.11 + 0.054*sl t f 0.15 0.10 + 0.023*sl 0.11 + 0.020*sl 0.11 + 0.020*sl s to y t plh 0.47 0.42 + 0.025*sl 0.42 + 0.025*sl 0.42 + 0.025*sl t phl 0.52 0.48 + 0.019*sl 0.50 + 0.014*sl 0.52 + 0.012*sl t r 0.22 0.12 + 0.051*sl 0.12 + 0.053*sl 0.11 + 0.054*sl t f 0.14 0.10 + 0.022*sl 0.10 + 0.020*sl 0.10 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-498 sec asic mx2i/mx2id2 2 > 1 inverting mux with 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 mx2i mx2id2 mx2i mx2id2 d0d1sd0d1s 0.9 0.8 1.7 0.9 0.9 1.4 3.0 4.0 KGM80 mx2i mx2id2 mx2i mx2id2 d0d1sd0d1s 1.0 1.0 2.0 1.0 1.0 2.1 3.0 4.0 d0 d1 yn s yn d0 s d1 truth table d0 d1 s yn 0x01 1x00 x011 x110
sec asic 3-499 kg80/KGM80 mx2i/mx2id2 2 > 1 inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 mx2i kg80 mx2id2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.36 0.22 + 0.068*sl 0.22 + 0.070*sl 0.21 + 0.071*sl t phl 0.17 0.09 + 0.043*sl 0.11 + 0.034*sl 0.11 + 0.034*sl t r 0.64 0.33 + 0.155*sl 0.32 + 0.160*sl 0.29 + 0.163*sl t f 0.34 0.23 + 0.056*sl 0.21 + 0.062*sl 0.19 + 0.065*sl d1 to yn t plh 0.41 0.27 + 0.072*sl 0.27 + 0.071*sl 0.27 + 0.072*sl t phl 0.23 0.15 + 0.039*sl 0.16 + 0.035*sl 0.16 + 0.034*sl t r 0.65 0.34 + 0.155*sl 0.33 + 0.160*sl 0.31 + 0.163*sl t f 0.39 0.27 + 0.059*sl 0.26 + 0.062*sl 0.24 + 0.066*sl s to yn t plh 0.40 0.26 + 0.070*sl 0.26 + 0.071*sl 0.25 + 0.071*sl t phl 0.31 0.24 + 0.035*sl 0.24 + 0.034*sl 0.24 + 0.034*sl t r 0.65 0.34 + 0.155*sl 0.32 + 0.160*sl 0.31 + 0.163*sl t f 0.24 0.11 + 0.064*sl 0.10 + 0.067*sl 0.09 + 0.069*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.46 0.42 + 0.023*sl 0.42 + 0.020*sl 0.42 + 0.021*sl t phl 0.36 0.33 + 0.018*sl 0.34 + 0.014*sl 0.35 + 0.012*sl t r 0.16 0.08 + 0.040*sl 0.08 + 0.043*sl 0.06 + 0.044*sl t f 0.12 0.08 + 0.020*sl 0.08 + 0.020*sl 0.08 + 0.020*sl d1 to yn t plh 0.46 0.42 + 0.023*sl 0.42 + 0.021*sl 0.42 + 0.021*sl t phl 0.36 0.32 + 0.018*sl 0.33 + 0.014*sl 0.35 + 0.012*sl t r 0.16 0.08 + 0.040*sl 0.08 + 0.043*sl 0.06 + 0.044*sl t f 0.12 0.08 + 0.020*sl 0.08 + 0.019*sl 0.08 + 0.020*sl s to yn t plh 0.40 0.35 + 0.022*sl 0.35 + 0.021*sl 0.36 + 0.021*sl t phl 0.42 0.38 + 0.018*sl 0.39 + 0.014*sl 0.41 + 0.012*sl t r 0.16 0.08 + 0.040*sl 0.07 + 0.043*sl 0.06 + 0.045*sl t f 0.12 0.08 + 0.021*sl 0.08 + 0.019*sl 0.08 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-500 sec asic mx2i/mx2id2 2 > 1 inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 mx2i KGM80 mx2id2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.48 0.30 + 0.093*sl 0.29 + 0.094*sl 0.30 + 0.094*sl t phl 0.21 0.11 + 0.046*sl 0.14 + 0.038*sl 0.14 + 0.037*sl t r 0.88 0.47 + 0.204*sl 0.46 + 0.208*sl 0.45 + 0.209*sl t f 0.38 0.25 + 0.064*sl 0.24 + 0.070*sl 0.20 + 0.073*sl d1 to yn t plh 0.61 0.42 + 0.096*sl 0.42 + 0.095*sl 0.43 + 0.094*sl t phl 0.28 0.20 + 0.043*sl 0.21 + 0.038*sl 0.22 + 0.037*sl t r 0.89 0.49 + 0.202*sl 0.47 + 0.207*sl 0.46 + 0.208*sl t f 0.44 0.31 + 0.067*sl 0.30 + 0.070*sl 0.27 + 0.073*sl s to yn t plh 0.59 0.40 + 0.095*sl 0.40 + 0.094*sl 0.40 + 0.094*sl t phl 0.38 0.30 + 0.039*sl 0.31 + 0.037*sl 0.31 + 0.037*sl t r 0.89 0.49 + 0.202*sl 0.47 + 0.207*sl 0.46 + 0.208*sl t f 0.28 0.14 + 0.071*sl 0.13 + 0.073*sl 0.12 + 0.074*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.64 0.58 + 0.027*sl 0.59 + 0.025*sl 0.59 + 0.025*sl t phl 0.50 0.46 + 0.021*sl 0.47 + 0.015*sl 0.50 + 0.012*sl t r 0.21 0.11 + 0.051*sl 0.10 + 0.053*sl 0.09 + 0.054*sl t f 0.14 0.09 + 0.025*sl 0.10 + 0.021*sl 0.11 + 0.020*sl d1 to yn t plh 0.64 0.59 + 0.027*sl 0.59 + 0.025*sl 0.59 + 0.025*sl t phl 0.49 0.45 + 0.021*sl 0.47 + 0.015*sl 0.50 + 0.012*sl t r 0.21 0.11 + 0.050*sl 0.10 + 0.053*sl 0.09 + 0.054*sl t f 0.14 0.10 + 0.022*sl 0.10 + 0.021*sl 0.10 + 0.021*sl s to yn t plh 0.54 0.48 + 0.028*sl 0.49 + 0.025*sl 0.49 + 0.025*sl t phl 0.56 0.52 + 0.021*sl 0.54 + 0.015*sl 0.56 + 0.012*sl t r 0.21 0.10 + 0.052*sl 0.10 + 0.053*sl 0.08 + 0.054*sl t f 0.14 0.09 + 0.024*sl 0.10 + 0.021*sl 0.10 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-501 kg80/KGM80 mx2ia/mx2id2a 2 > 1 inverting mux with separate s and sn inputs, 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 mx2ia mx2id2a mx2ia mx2id2a d0 d1 s sn d0 d1 s sn 0.6 0.7 0.7 0.5 1.0 1.0 0.8 0.8 2.0 4.0 KGM80 mx2ia mx2id2a mx2ia mx2id2a d0 d1 s sn d0 d1 s sn 1.0 1.0 1.0 1.0 1.0 1.0 0.9 0.9 2.0 4.0 yn d0 d1 s sn yn d0 sn d1 s truth table d0 d1 s sn yn 0 x 011 1 x 010 x 0 101 x 1 100
kg80/KGM80 3-502 sec asic mx2ia/mx2id2a 2 > 1 inverting mux with separate s and sn inputs, 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 mx2ia kg80 mx2id2a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.36 0.22 + 0.068*sl 0.22 + 0.070*sl 0.21 + 0.071*sl t phl 0.17 0.09 + 0.043*sl 0.11 + 0.034*sl 0.11 + 0.034*sl t r 0.64 0.33 + 0.155*sl 0.31 + 0.160*sl 0.29 + 0.163*sl t f 0.34 0.23 + 0.056*sl 0.21 + 0.062*sl 0.19 + 0.065*sl d1 to yn t plh 0.41 0.27 + 0.072*sl 0.27 + 0.071*sl 0.27 + 0.072*sl t phl 0.22 0.15 + 0.037*sl 0.16 + 0.034*sl 0.16 + 0.034*sl t r 0.64 0.33 + 0.155*sl 0.32 + 0.160*sl 0.31 + 0.163*sl t f 0.39 0.27 + 0.062*sl 0.27 + 0.062*sl 0.24 + 0.065*sl s to yn t plh 0.40 0.26 + 0.070*sl 0.26 + 0.071*sl 0.26 + 0.071*sl t phl 0.19 0.11 + 0.039*sl 0.12 + 0.035*sl 0.13 + 0.034*sl t r 0.65 0.34 + 0.155*sl 0.32 + 0.160*sl 0.31 + 0.162*sl t f 0.37 0.25 + 0.059*sl 0.24 + 0.064*sl 0.22 + 0.066*sl sn to yn t plh 0.40 0.26 + 0.070*sl 0.26 + 0.071*sl 0.26 + 0.071*sl t phl 0.19 0.11 + 0.039*sl 0.12 + 0.035*sl 0.13 + 0.034*sl t r 0.65 0.34 + 0.155*sl 0.32 + 0.160*sl 0.31 + 0.162*sl t f 0.37 0.25 + 0.059*sl 0.24 + 0.064*sl 0.22 + 0.066*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.46 0.42 + 0.022*sl 0.42 + 0.021*sl 0.42 + 0.021*sl t phl 0.36 0.32 + 0.018*sl 0.33 + 0.014*sl 0.35 + 0.012*sl t r 0.16 0.08 + 0.041*sl 0.08 + 0.043*sl 0.06 + 0.044*sl t f 0.12 0.08 + 0.020*sl 0.08 + 0.020*sl 0.08 + 0.020*sl d1 to yn t plh 0.46 0.42 + 0.022*sl 0.42 + 0.021*sl 0.42 + 0.021*sl t phl 0.35 0.32 + 0.016*sl 0.33 + 0.015*sl 0.33 + 0.013*sl t r 0.16 0.08 + 0.041*sl 0.08 + 0.043*sl 0.06 + 0.044*sl t f 0.13 0.09 + 0.021*sl 0.09 + 0.019*sl 0.09 + 0.019*sl s to yn t plh 0.36 0.32 + 0.022*sl 0.32 + 0.021*sl 0.32 + 0.021*sl t phl 0.29 0.25 + 0.018*sl 0.26 + 0.014*sl 0.27 + 0.012*sl t r 0.16 0.08 + 0.041*sl 0.07 + 0.043*sl 0.06 + 0.045*sl t f 0.12 0.08 + 0.021*sl 0.08 + 0.020*sl 0.08 + 0.020*sl sn to yn t plh 0.36 0.32 + 0.022*sl 0.32 + 0.021*sl 0.32 + 0.021*sl t phl 0.29 0.25 + 0.018*sl 0.26 + 0.014*sl 0.27 + 0.012*sl t r 0.16 0.08 + 0.041*sl 0.07 + 0.043*sl 0.06 + 0.045*sl t f 0.12 0.08 + 0.021*sl 0.08 + 0.020*sl 0.08 + 0.020*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-503 kg80/KGM80 mx2ia/mx2id2a 2 > 1 inverting mux with separate s and sn inputs, 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 mx2ia KGM80 mx2id2a path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.48 0.30 + 0.093*sl 0.29 + 0.094*sl 0.29 + 0.094*sl t phl 0.21 0.11 + 0.046*sl 0.14 + 0.038*sl 0.14 + 0.037*sl t r 0.87 0.47 + 0.204*sl 0.46 + 0.208*sl 0.44 + 0.209*sl t f 0.38 0.25 + 0.064*sl 0.24 + 0.070*sl 0.20 + 0.073*sl d1 to yn t plh 0.61 0.41 + 0.096*sl 0.42 + 0.095*sl 0.42 + 0.094*sl t phl 0.28 0.20 + 0.042*sl 0.21 + 0.038*sl 0.22 + 0.037*sl t r 0.89 0.49 + 0.202*sl 0.47 + 0.207*sl 0.46 + 0.208*sl t f 0.44 0.31 + 0.067*sl 0.30 + 0.070*sl 0.27 + 0.073*sl s to yn t plh 0.59 0.40 + 0.095*sl 0.40 + 0.094*sl 0.40 + 0.094*sl t phl 0.25 0.16 + 0.043*sl 0.17 + 0.038*sl 0.18 + 0.037*sl t r 0.89 0.49 + 0.202*sl 0.48 + 0.206*sl 0.46 + 0.208*sl t f 0.42 0.29 + 0.067*sl 0.28 + 0.072*sl 0.25 + 0.074*sl sn to yn t plh 0.59 0.40 + 0.095*sl 0.40 + 0.094*sl 0.40 + 0.094*sl t phl 0.25 0.16 + 0.043*sl 0.17 + 0.038*sl 0.18 + 0.037*sl t r 0.89 0.49 + 0.202*sl 0.48 + 0.206*sl 0.46 + 0.208*sl t f 0.42 0.29 + 0.067*sl 0.28 + 0.072*sl 0.25 + 0.074*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.64 0.59 + 0.027*sl 0.59 + 0.025*sl 0.59 + 0.025*sl t phl 0.49 0.45 + 0.021*sl 0.47 + 0.015*sl 0.50 + 0.012*sl t r 0.21 0.11 + 0.050*sl 0.10 + 0.053*sl 0.09 + 0.054*sl t f 0.14 0.10 + 0.023*sl 0.10 + 0.021*sl 0.10 + 0.021*sl d1 to yn t plh 0.64 0.58 + 0.027*sl 0.59 + 0.025*sl 0.59 + 0.025*sl t phl 0.49 0.45 + 0.021*sl 0.47 + 0.015*sl 0.49 + 0.012*sl t r 0.21 0.11 + 0.051*sl 0.10 + 0.053*sl 0.09 + 0.054*sl t f 0.14 0.10 + 0.023*sl 0.10 + 0.021*sl 0.10 + 0.021*sl s to yn t plh 0.48 0.43 + 0.027*sl 0.43 + 0.025*sl 0.44 + 0.025*sl t phl 0.40 0.36 + 0.021*sl 0.38 + 0.015*sl 0.41 + 0.012*sl t r 0.21 0.11 + 0.050*sl 0.10 + 0.053*sl 0.08 + 0.054*sl t f 0.14 0.09 + 0.024*sl 0.10 + 0.021*sl 0.11 + 0.020*sl sn to yn t plh 0.48 0.43 + 0.027*sl 0.43 + 0.025*sl 0.44 + 0.025*sl t phl 0.40 0.36 + 0.021*sl 0.38 + 0.015*sl 0.41 + 0.012*sl t r 0.21 0.11 + 0.050*sl 0.10 + 0.053*sl 0.08 + 0.054*sl t f 0.14 0.09 + 0.024*sl 0.10 + 0.021*sl 0.11 + 0.020*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-504 sec asic mx2ix4 4-bit 2 > 1 inverting mux logic symbol cell data input load (sl) gate count kg80 mx2ix4 mx2ix4 d00 d10 d01 d11 d02 d12 d03 d13 s 0.9 0.7 0.9 0.5 0.9 0.5 0.9 0.5 4.3 9.0 KGM80 mx2ix4 mx2ix4 d00 d10 d01 d11 d02 d12 d03 d13 s 1.0 0.9 1.0 0.9 1.0 0.7 1.0 0.7 5.0 9.0 yn0 yn1 yn2 yn3 d00 d10 d01 d11 d02 d12 d03 d13 s truth table s yn0 yn1 yn2 yn3 0 d00 d01 d02 d03 1 d10 d11 d12 d13
sec asic 3-505 kg80/KGM80 mx2ix4 4-bit 2 > 1 inverting mux switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 mx2ix4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d00 to yn0 t plh 0.27 0.17 + 0.053*sl 0.17 + 0.053*sl 0.16 + 0.054*sl t phl 0.16 0.07 + 0.044*sl 0.09 + 0.034*sl 0.10 + 0.034*sl t r 0.44 0.22 + 0.112*sl 0.20 + 0.119*sl 0.17 + 0.122*sl t f 0.30 0.18 + 0.058*sl 0.18 + 0.062*sl 0.15 + 0.065*sl d10 to yn0 t plh 0.32 0.21 + 0.056*sl 0.21 + 0.055*sl 0.21 + 0.055*sl t phl 0.23 0.15 + 0.039*sl 0.16 + 0.035*sl 0.16 + 0.034*sl t r 0.52 0.29 + 0.114*sl 0.28 + 0.120*sl 0.26 + 0.123*sl t f 0.39 0.27 + 0.058*sl 0.26 + 0.063*sl 0.24 + 0.066*sl s to yn0 t plh 0.45 0.32 + 0.069*sl 0.31 + 0.071*sl 0.31 + 0.071*sl t phl 0.43 0.35 + 0.040*sl 0.36 + 0.036*sl 0.37 + 0.034*sl t r 0.63 0.31 + 0.160*sl 0.30 + 0.163*sl 0.29 + 0.164*sl t f 0.28 0.16 + 0.062*sl 0.15 + 0.064*sl 0.13 + 0.067*sl d01 to yn1 t plh 0.27 0.17 + 0.053*sl 0.17 + 0.053*sl 0.16 + 0.054*sl t phl 0.16 0.07 + 0.044*sl 0.10 + 0.034*sl 0.10 + 0.034*sl t r 0.45 0.22 + 0.112*sl 0.21 + 0.119*sl 0.18 + 0.122*sl t f 0.30 0.19 + 0.058*sl 0.18 + 0.062*sl 0.15 + 0.065*sl d11 to yn1 t plh 0.32 0.21 + 0.056*sl 0.21 + 0.055*sl 0.22 + 0.055*sl t phl 0.23 0.15 + 0.038*sl 0.16 + 0.035*sl 0.16 + 0.034*sl t r 0.53 0.30 + 0.114*sl 0.28 + 0.120*sl 0.26 + 0.123*sl t f 0.39 0.27 + 0.059*sl 0.26 + 0.063*sl 0.24 + 0.066*sl s to yn1 t plh 0.46 0.32 + 0.069*sl 0.32 + 0.071*sl 0.31 + 0.071*sl t phl 0.43 0.35 + 0.039*sl 0.36 + 0.036*sl 0.37 + 0.034*sl t r 0.63 0.31 + 0.160*sl 0.31 + 0.163*sl 0.30 + 0.164*sl t f 0.28 0.16 + 0.061*sl 0.15 + 0.064*sl 0.13 + 0.067*sl d02 to yn2 t plh 0.27 0.17 + 0.053*sl 0.17 + 0.053*sl 0.16 + 0.054*sl t phl 0.16 0.07 + 0.044*sl 0.10 + 0.034*sl 0.10 + 0.034*sl t r 0.45 0.22 + 0.112*sl 0.21 + 0.119*sl 0.18 + 0.123*sl t f 0.30 0.19 + 0.058*sl 0.18 + 0.062*sl 0.15 + 0.065*sl d12 to yn2 t plh 0.32 0.21 + 0.056*sl 0.21 + 0.055*sl 0.22 + 0.055*sl t phl 0.23 0.15 + 0.038*sl 0.16 + 0.035*sl 0.16 + 0.034*sl t r 0.53 0.30 + 0.114*sl 0.28 + 0.120*sl 0.26 + 0.123*sl t f 0.39 0.27 + 0.059*sl 0.26 + 0.063*sl 0.24 + 0.066*sl s to yn2 t plh 0.46 0.32 + 0.069*sl 0.32 + 0.071*sl 0.31 + 0.071*sl t phl 0.43 0.35 + 0.040*sl 0.36 + 0.036*sl 0.37 + 0.034*sl t r 0.63 0.31 + 0.160*sl 0.31 + 0.163*sl 0.30 + 0.164*sl t f 0.28 0.16 + 0.061*sl 0.15 + 0.064*sl 0.13 + 0.067*sl d03 to yn3 t plh 0.27 0.17 + 0.053*sl 0.17 + 0.053*sl 0.16 + 0.054*sl t phl 0.16 0.07 + 0.044*sl 0.09 + 0.034*sl 0.10 + 0.034*sl t r 0.44 0.22 + 0.112*sl 0.20 + 0.119*sl 0.17 + 0.122*sl t f 0.30 0.18 + 0.058*sl 0.18 + 0.062*sl 0.15 + 0.065*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-506 sec asic mx2ix4 4-bit 2 > 1 inverting mux switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 mx2ix4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d13 to yn3 t plh 0.32 0.21 + 0.056*sl 0.21 + 0.055*sl 0.21 + 0.055*sl t phl 0.23 0.15 + 0.039*sl 0.16 + 0.035*sl 0.16 + 0.034*sl t r 0.52 0.29 + 0.114*sl 0.28 + 0.120*sl 0.26 + 0.123*sl t f 0.39 0.27 + 0.058*sl 0.26 + 0.063*sl 0.24 + 0.066*sl s to yn3 t plh 0.45 0.32 + 0.069*sl 0.31 + 0.071*sl 0.31 + 0.071*sl t phl 0.43 0.35 + 0.040*sl 0.36 + 0.036*sl 0.37 + 0.034*sl t r 0.63 0.31 + 0.160*sl 0.30 + 0.163*sl 0.29 + 0.164*sl t f 0.28 0.16 + 0.062*sl 0.15 + 0.064*sl 0.13 + 0.067*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-507 kg80/KGM80 mx2ix4 4-bit 2 > 1 inverting mux switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 mx2ix4 (continued) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d00 to yn0 t plh 0.35 0.21 + 0.070*sl 0.21 + 0.070*sl 0.20 + 0.070*sl t phl 0.20 0.10 + 0.046*sl 0.13 + 0.038*sl 0.13 + 0.037*sl t r 0.59 0.29 + 0.149*sl 0.27 + 0.154*sl 0.24 + 0.157*sl t f 0.33 0.20 + 0.067*sl 0.19 + 0.070*sl 0.15 + 0.073*sl d10 to yn0 t plh 0.45 0.30 + 0.074*sl 0.31 + 0.073*sl 0.31 + 0.072*sl t phl 0.28 0.20 + 0.041*sl 0.21 + 0.038*sl 0.22 + 0.037*sl t r 0.71 0.41 + 0.149*sl 0.39 + 0.155*sl 0.37 + 0.157*sl t f 0.44 0.31 + 0.067*sl 0.30 + 0.071*sl 0.27 + 0.073*sl s to yn0 t plh 0.63 0.44 + 0.094*sl 0.44 + 0.094*sl 0.44 + 0.094*sl t phl 0.57 0.48 + 0.045*sl 0.49 + 0.039*sl 0.51 + 0.037*sl t r 0.87 0.46 + 0.207*sl 0.45 + 0.209*sl 0.45 + 0.209*sl t f 0.34 0.20 + 0.069*sl 0.19 + 0.071*sl 0.17 + 0.073*sl d01 to yn1 t plh 0.35 0.21 + 0.070*sl 0.21 + 0.070*sl 0.21 + 0.070*sl t phl 0.20 0.11 + 0.046*sl 0.13 + 0.038*sl 0.13 + 0.037*sl t r 0.59 0.29 + 0.149*sl 0.28 + 0.154*sl 0.25 + 0.157*sl t f 0.33 0.20 + 0.066*sl 0.19 + 0.070*sl 0.16 + 0.073*sl d11 to yn1 t plh 0.46 0.31 + 0.075*sl 0.31 + 0.073*sl 0.32 + 0.072*sl t phl 0.29 0.20 + 0.041*sl 0.21 + 0.038*sl 0.22 + 0.037*sl t r 0.71 0.42 + 0.148*sl 0.40 + 0.155*sl 0.37 + 0.157*sl t f 0.45 0.31 + 0.067*sl 0.30 + 0.071*sl 0.27 + 0.073*sl s to yn1 t plh 0.63 0.44 + 0.094*sl 0.44 + 0.094*sl 0.45 + 0.094*sl t phl 0.57 0.48 + 0.045*sl 0.50 + 0.039*sl 0.52 + 0.037*sl t r 0.88 0.47 + 0.208*sl 0.46 + 0.209*sl 0.47 + 0.209*sl t f 0.34 0.20 + 0.068*sl 0.20 + 0.071*sl 0.17 + 0.073*sl d02 to yn2 t plh 0.35 0.21 + 0.070*sl 0.21 + 0.070*sl 0.21 + 0.070*sl t phl 0.20 0.11 + 0.046*sl 0.13 + 0.038*sl 0.13 + 0.037*sl t r 0.59 0.29 + 0.149*sl 0.28 + 0.154*sl 0.25 + 0.157*sl t f 0.33 0.20 + 0.066*sl 0.19 + 0.070*sl 0.16 + 0.073*sl d12 to yn2 t plh 0.46 0.31 + 0.075*sl 0.31 + 0.073*sl 0.32 + 0.072*sl t phl 0.29 0.20 + 0.041*sl 0.21 + 0.038*sl 0.22 + 0.037*sl t r 0.71 0.42 + 0.148*sl 0.40 + 0.155*sl 0.37 + 0.157*sl t f 0.45 0.31 + 0.067*sl 0.30 + 0.071*sl 0.27 + 0.073*sl s to yn2 t plh 0.63 0.44 + 0.094*sl 0.44 + 0.094*sl 0.45 + 0.094*sl t phl 0.57 0.48 + 0.045*sl 0.50 + 0.039*sl 0.52 + 0.037*sl t r 0.88 0.47 + 0.207*sl 0.46 + 0.209*sl 0.46 + 0.209*sl t f 0.34 0.20 + 0.068*sl 0.20 + 0.071*sl 0.17 + 0.073*sl d03 to yn3 t plh 0.35 0.21 + 0.070*sl 0.21 + 0.070*sl 0.20 + 0.070*sl t phl 0.20 0.10 + 0.046*sl 0.13 + 0.038*sl 0.13 + 0.037*sl t r 0.59 0.29 + 0.149*sl 0.27 + 0.154*sl 0.24 + 0.157*sl t f 0.33 0.20 + 0.067*sl 0.19 + 0.070*sl 0.15 + 0.073*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-508 sec asic mx2ix4 4-bit 2 > 1 inverting mux switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 mx2ix4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d13 to yn3 t plh 0.45 0.30 + 0.074*sl 0.31 + 0.073*sl 0.31 + 0.072*sl t phl 0.28 0.20 + 0.041*sl 0.21 + 0.038*sl 0.22 + 0.037*sl t r 0.71 0.41 + 0.149*sl 0.39 + 0.155*sl 0.37 + 0.157*sl t f 0.44 0.31 + 0.067*sl 0.30 + 0.071*sl 0.27 + 0.073*sl s to yn3 t plh 0.63 0.44 + 0.094*sl 0.44 + 0.094*sl 0.44 + 0.094*sl t phl 0.57 0.48 + 0.045*sl 0.49 + 0.039*sl 0.51 + 0.037*sl t r 0.87 0.46 + 0.207*sl 0.45 + 0.209*sl 0.45 + 0.209*sl t f 0.34 0.20 + 0.069*sl 0.19 + 0.071*sl 0.17 + 0.073*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-509 kg80/KGM80 mx3i/mx3id2 3 > 1 inverting mux with 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 mx3i mx3id2 mx3i mx3id2 d0 d1 d2 s0 s1 d0 d1 d2 s0 s1 1.0 1.0 0.9 1.1 1.4 1.0 1.0 0.9 1.1 1.4 6.0 6.0 KGM80 mx3i mx3id2 mx3i mx3id2 d0 d1 d2 s0 s1 d0 d1 d2 s0 s1 1.0 1.0 1.0 2.1 2.0 1.0 1.0 1.0 2.1 2.0 6.0 6.0 d0 d1 d2 yn s0 s1 d0 d1 s0 s1 d2 yn truth table s0 s1 yn 00 d0 10 d1 x1 d2
kg80/KGM80 3-510 sec asic mx3i/mx3id2 3 > 1 inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 mx3i kg80 mx3id2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.60 0.51 + 0.042*sl 0.51 + 0.041*sl 0.51 + 0.042*sl t phl 0.48 0.42 + 0.028*sl 0.43 + 0.024*sl 0.44 + 0.023*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.15 0.08 + 0.038*sl 0.07 + 0.041*sl 0.06 + 0.042*sl d1 to yn t plh 0.60 0.51 + 0.042*sl 0.51 + 0.041*sl 0.51 + 0.042*sl t phl 0.48 0.42 + 0.028*sl 0.43 + 0.024*sl 0.44 + 0.023*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.15 0.08 + 0.038*sl 0.07 + 0.041*sl 0.06 + 0.042*sl d2 to yn t plh 0.48 0.39 + 0.042*sl 0.39 + 0.042*sl 0.40 + 0.042*sl t phl 0.36 0.30 + 0.028*sl 0.31 + 0.024*sl 0.32 + 0.023*sl t r 0.26 0.09 + 0.087*sl 0.08 + 0.090*sl 0.08 + 0.091*sl t f 0.15 0.07 + 0.041*sl 0.07 + 0.041*sl 0.06 + 0.042*sl s0 to yn t plh 0.52 0.44 + 0.042*sl 0.44 + 0.042*sl 0.44 + 0.042*sl t phl 0.52 0.47 + 0.028*sl 0.48 + 0.024*sl 0.48 + 0.023*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.15 0.07 + 0.040*sl 0.07 + 0.040*sl 0.06 + 0.042*sl s1 to yn t plh 0.43 0.35 + 0.042*sl 0.35 + 0.042*sl 0.35 + 0.042*sl t phl 0.44 0.38 + 0.028*sl 0.39 + 0.024*sl 0.40 + 0.023*sl t r 0.27 0.09 + 0.087*sl 0.08 + 0.090*sl 0.08 + 0.091*sl t f 0.16 0.08 + 0.040*sl 0.08 + 0.040*sl 0.06 + 0.042*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.59 0.54 + 0.023*sl 0.55 + 0.021*sl 0.55 + 0.021*sl t phl 0.48 0.45 + 0.018*sl 0.46 + 0.014*sl 0.47 + 0.012*sl t r 0.17 0.09 + 0.040*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.021*sl 0.09 + 0.019*sl 0.08 + 0.020*sl d1 to yn t plh 0.59 0.54 + 0.023*sl 0.55 + 0.021*sl 0.55 + 0.021*sl t phl 0.48 0.44 + 0.019*sl 0.45 + 0.014*sl 0.46 + 0.012*sl t r 0.17 0.09 + 0.040*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.09 + 0.020*sl 0.09 + 0.019*sl 0.08 + 0.020*sl d2 to yn t plh 0.46 0.42 + 0.022*sl 0.42 + 0.020*sl 0.42 + 0.021*sl t phl 0.36 0.32 + 0.018*sl 0.33 + 0.014*sl 0.34 + 0.012*sl t r 0.16 0.08 + 0.040*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.12 0.08 + 0.020*sl 0.08 + 0.020*sl 0.08 + 0.020*sl s0 to yn t plh 0.52 0.47 + 0.023*sl 0.47 + 0.021*sl 0.47 + 0.021*sl t phl 0.53 0.49 + 0.018*sl 0.50 + 0.014*sl 0.51 + 0.012*sl t r 0.17 0.09 + 0.041*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.13 0.08 + 0.022*sl 0.09 + 0.019*sl 0.08 + 0.020*sl s1 to yn t plh 0.42 0.37 + 0.023*sl 0.38 + 0.021*sl 0.38 + 0.021*sl t phl 0.44 0.41 + 0.018*sl 0.42 + 0.014*sl 0.43 + 0.012*sl t r 0.16 0.08 + 0.042*sl 0.08 + 0.043*sl 0.07 + 0.044*sl t f 0.12 0.08 + 0.021*sl 0.08 + 0.019*sl 0.08 + 0.020*sl *grou p 1 : sl < 2, *grou p 2 : 2 sl 7, *grou p 3 : 7 < sl < < = =
sec asic 3-511 kg80/KGM80 mx3i/mx3id2 3 > 1 inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 mx3i KGM80 mx3id2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.86 0.75 + 0.051*sl 0.76 + 0.050*sl 0.76 + 0.050*sl t phl 0.66 0.60 + 0.031*sl 0.61 + 0.024*sl 0.63 + 0.023*sl t r 0.35 0.15 + 0.104*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.041*sl 0.08 + 0.043*sl d1 to yn t plh 0.86 0.76 + 0.051*sl 0.76 + 0.050*sl 0.76 + 0.050*sl t phl 0.65 0.59 + 0.030*sl 0.60 + 0.024*sl 0.62 + 0.023*sl t r 0.35 0.15 + 0.104*sl 0.14 + 0.108*sl 0.12 + 0.109*sl t f 0.18 0.10 + 0.042*sl 0.10 + 0.042*sl 0.08 + 0.043*sl d2 to yn t plh 0.66 0.56 + 0.050*sl 0.56 + 0.050*sl 0.56 + 0.050*sl t phl 0.48 0.42 + 0.030*sl 0.44 + 0.024*sl 0.45 + 0.023*sl t r 0.34 0.13 + 0.105*sl 0.12 + 0.108*sl 0.11 + 0.109*sl t f 0.18 0.09 + 0.043*sl 0.10 + 0.041*sl 0.08 + 0.043*sl s0 to yn t plh 0.76 0.66 + 0.051*sl 0.66 + 0.050*sl 0.66 + 0.050*sl t phl 0.71 0.65 + 0.031*sl 0.67 + 0.024*sl 0.68 + 0.023*sl t r 0.35 0.14 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.041*sl 0.08 + 0.043*sl s1 to yn t plh 0.58 0.48 + 0.050*sl 0.48 + 0.050*sl 0.49 + 0.050*sl t phl 0.58 0.52 + 0.030*sl 0.54 + 0.024*sl 0.55 + 0.023*sl t r 0.34 0.13 + 0.105*sl 0.12 + 0.109*sl 0.12 + 0.109*sl t f 0.18 0.10 + 0.042*sl 0.10 + 0.042*sl 0.08 + 0.043*sl path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to yn t plh 0.85 0.80 + 0.028*sl 0.80 + 0.025*sl 0.81 + 0.025*sl t phl 0.67 0.63 + 0.021*sl 0.65 + 0.015*sl 0.68 + 0.012*sl t r 0.22 0.13 + 0.049*sl 0.12 + 0.052*sl 0.10 + 0.054*sl t f 0.15 0.10 + 0.023*sl 0.11 + 0.020*sl 0.11 + 0.020*sl d1 to yn t plh 0.86 0.80 + 0.028*sl 0.81 + 0.025*sl 0.81 + 0.025*sl t phl 0.67 0.62 + 0.021*sl 0.64 + 0.015*sl 0.67 + 0.012*sl t r 0.22 0.13 + 0.049*sl 0.12 + 0.052*sl 0.10 + 0.054*sl t f 0.15 0.10 + 0.023*sl 0.11 + 0.021*sl 0.11 + 0.020*sl d2 to yn t plh 0.64 0.58 + 0.027*sl 0.59 + 0.025*sl 0.59 + 0.025*sl t phl 0.49 0.45 + 0.021*sl 0.47 + 0.015*sl 0.49 + 0.012*sl t r 0.21 0.11 + 0.050*sl 0.10 + 0.053*sl 0.09 + 0.054*sl t f 0.14 0.10 + 0.024*sl 0.11 + 0.020*sl 0.10 + 0.021*sl s0 to yn t plh 0.75 0.70 + 0.028*sl 0.71 + 0.025*sl 0.71 + 0.025*sl t phl 0.73 0.69 + 0.021*sl 0.70 + 0.015*sl 0.73 + 0.012*sl t r 0.22 0.12 + 0.049*sl 0.12 + 0.052*sl 0.10 + 0.054*sl t f 0.15 0.10 + 0.024*sl 0.11 + 0.020*sl 0.11 + 0.020*sl s1 to yn t plh 0.57 0.51 + 0.028*sl 0.52 + 0.025*sl 0.52 + 0.025*sl t phl 0.60 0.56 + 0.021*sl 0.57 + 0.015*sl 0.60 + 0.012*sl t r 0.21 0.11 + 0.050*sl 0.11 + 0.053*sl 0.09 + 0.054*sl t f 0.15 0.10 + 0.024*sl 0.11 + 0.021*sl 0.11 + 0.020*sl *grou p 1 : sl < 3, *grou p 2 : 3 sl 11, *grou p 3 : 11 < sl < < = =
kg80/KGM80 3-512 sec asic mx4/mx4d2 4 > 1 non-inverting mux with 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 mx4 mx4d2 mx4 mx4d 2 d0 d1 d2 d3 s0 s1 d0 d1 d2 d3 s0 s1 0.9 0.9 0.9 0.8 2.1 1.2 0.9 0.9 0.9 0.8 2.1 1.2 7.0 7.0 KGM80 mx4 mx4d2 mx4 mx4d 2 d0 d1 d2 d3 s0 s1 d0 d1 d2 d3 s0 s1 1.0 1.0 1.0 1.0 2.8 2.1 1.0 1.0 1.0 .10 2.8 2.1 7.0 7.0 y d0 d1 d2 d3 s0 s1 s0b s0 s0 s1b s1 s1 d0 d1 d2 d3 y s0 s0 s0b s0 s0b s1 s1b s1b s1 truth table s0 s1 y 00d0 10d1 01d2 11d3
sec asic 3-513 kg80/KGM80 mx4/mx4d2 4 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 mx4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.44 0.35 + 0.045*sl 0.36 + 0.042*sl 0.36 + 0.041*sl t phl 0.50 0.41 + 0.045*sl 0.43 + 0.034*sl 0.47 + 0.028*sl t r 0.30 0.14 + 0.084*sl 0.13 + 0.087*sl 0.11 + 0.089*sl t f 0.27 0.17 + 0.051*sl 0.19 + 0.043*sl 0.20 + 0.041*sl d1 to y t plh 0.44 0.35 + 0.045*sl 0.35 + 0.042*sl 0.36 + 0.041*sl t phl 0.50 0.41 + 0.045*sl 0.43 + 0.034*sl 0.47 + 0.028*sl t r 0.30 0.13 + 0.084*sl 0.13 + 0.087*sl 0.11 + 0.089*sl t f 0.27 0.17 + 0.051*sl 0.19 + 0.043*sl 0.20 + 0.041*sl d2 to y t plh 0.44 0.35 + 0.046*sl 0.35 + 0.042*sl 0.36 + 0.041*sl t phl 0.49 0.40 + 0.045*sl 0.43 + 0.034*sl 0.47 + 0.028*sl t r 0.30 0.13 + 0.084*sl 0.13 + 0.087*sl 0.11 + 0.089*sl t f 0.27 0.17 + 0.052*sl 0.19 + 0.043*sl 0.21 + 0.041*sl d3 to y t plh 0.44 0.34 + 0.046*sl 0.35 + 0.042*sl 0.36 + 0.041*sl t phl 0.50 0.41 + 0.045*sl 0.43 + 0.034*sl 0.47 + 0.028*sl t r 0.30 0.13 + 0.084*sl 0.13 + 0.087*sl 0.11 + 0.089*sl t f 0.27 0.17 + 0.050*sl 0.19 + 0.043*sl 0.20 + 0.041*sl s0 to y t plh 0.52 0.43 + 0.046*sl 0.44 + 0.042*sl 0.44 + 0.041*sl t phl 0.40 0.31 + 0.044*sl 0.33 + 0.034*sl 0.38 + 0.028*sl t r 0.30 0.14 + 0.084*sl 0.13 + 0.087*sl 0.11 + 0.089*sl t f 0.26 0.15 + 0.053*sl 0.17 + 0.044*sl 0.19 + 0.041*sl s1 to y t plh 0.40 0.30 + 0.046*sl 0.31 + 0.043*sl 0.32 + 0.042*sl t phl 0.29 0.21 + 0.039*sl 0.23 + 0.031*sl 0.26 + 0.027*sl t r 0.29 0.12 + 0.087*sl 0.12 + 0.088*sl 0.10 + 0.090*sl t f 0.21 0.11 + 0.053*sl 0.13 + 0.045*sl 0.14 + 0.043*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-514 sec asic mx4/mx4d2 4 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 mx4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.44 0.39 + 0.026*sl 0.40 + 0.022*sl 0.41 + 0.021*sl t phl 0.50 0.44 + 0.028*sl 0.46 + 0.021*sl 0.48 + 0.017*sl t r 0.23 0.15 + 0.042*sl 0.15 + 0.042*sl 0.14 + 0.043*sl t f 0.25 0.19 + 0.029*sl 0.20 + 0.025*sl 0.22 + 0.022*sl d1 to y t plh 0.44 0.39 + 0.025*sl 0.39 + 0.022*sl 0.40 + 0.021*sl t phl 0.50 0.44 + 0.027*sl 0.46 + 0.021*sl 0.48 + 0.018*sl t r 0.23 0.15 + 0.041*sl 0.15 + 0.042*sl 0.14 + 0.043*sl t f 0.25 0.19 + 0.030*sl 0.20 + 0.025*sl 0.22 + 0.022*sl d2 to y t plh 0.44 0.38 + 0.025*sl 0.39 + 0.022*sl 0.40 + 0.021*sl t phl 0.49 0.44 + 0.027*sl 0.45 + 0.021*sl 0.48 + 0.018*sl t r 0.23 0.15 + 0.041*sl 0.15 + 0.043*sl 0.15 + 0.043*sl t f 0.25 0.19 + 0.030*sl 0.20 + 0.025*sl 0.22 + 0.022*sl d3 to y t plh 0.43 0.38 + 0.026*sl 0.39 + 0.022*sl 0.40 + 0.021*sl t phl 0.50 0.44 + 0.027*sl 0.46 + 0.021*sl 0.48 + 0.018*sl t r 0.23 0.15 + 0.042*sl 0.15 + 0.043*sl 0.15 + 0.043*sl t f 0.25 0.19 + 0.030*sl 0.20 + 0.025*sl 0.22 + 0.022*sl s0 to y t plh 0.52 0.47 + 0.026*sl 0.47 + 0.022*sl 0.48 + 0.021*sl t phl 0.39 0.34 + 0.027*sl 0.35 + 0.021*sl 0.38 + 0.018*sl t r 0.24 0.15 + 0.041*sl 0.15 + 0.042*sl 0.14 + 0.043*sl t f 0.23 0.17 + 0.031*sl 0.19 + 0.025*sl 0.21 + 0.022*sl s1 to y t plh 0.39 0.34 + 0.026*sl 0.35 + 0.023*sl 0.36 + 0.021*sl t phl 0.28 0.23 + 0.024*sl 0.24 + 0.020*sl 0.26 + 0.017*sl t r 0.22 0.14 + 0.045*sl 0.14 + 0.043*sl 0.14 + 0.043*sl t f 0.19 0.13 + 0.030*sl 0.14 + 0.026*sl 0.16 + 0.023*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-515 kg80/KGM80 mx4/mx4d2 4 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 mx4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.60 0.48 + 0.058*sl 0.50 + 0.051*sl 0.51 + 0.050*sl t phl 0.71 0.60 + 0.057*sl 0.65 + 0.038*sl 0.75 + 0.029*sl t r 0.39 0.18 + 0.105*sl 0.18 + 0.106*sl 0.15 + 0.108*sl t f 0.36 0.24 + 0.061*sl 0.28 + 0.046*sl 0.33 + 0.041*sl d1 to y t plh 0.59 0.48 + 0.058*sl 0.50 + 0.051*sl 0.51 + 0.050*sl t phl 0.71 0.60 + 0.057*sl 0.65 + 0.038*sl 0.75 + 0.029*sl t r 0.39 0.18 + 0.106*sl 0.18 + 0.106*sl 0.15 + 0.108*sl t f 0.36 0.24 + 0.060*sl 0.28 + 0.046*sl 0.33 + 0.041*sl d2 to y t plh 0.59 0.48 + 0.058*sl 0.49 + 0.051*sl 0.51 + 0.050*sl t phl 0.71 0.59 + 0.057*sl 0.64 + 0.038*sl 0.74 + 0.029*sl t r 0.39 0.18 + 0.105*sl 0.18 + 0.106*sl 0.15 + 0.108*sl t f 0.36 0.24 + 0.060*sl 0.28 + 0.046*sl 0.33 + 0.041*sl d3 to y t plh 0.59 0.47 + 0.057*sl 0.49 + 0.051*sl 0.50 + 0.050*sl t phl 0.71 0.60 + 0.057*sl 0.65 + 0.038*sl 0.75 + 0.029*sl t r 0.39 0.18 + 0.105*sl 0.18 + 0.106*sl 0.15 + 0.108*sl t f 0.36 0.24 + 0.060*sl 0.28 + 0.045*sl 0.33 + 0.041*sl s0 to y t plh 0.71 0.59 + 0.058*sl 0.61 + 0.051*sl 0.62 + 0.050*sl t phl 0.58 0.47 + 0.056*sl 0.52 + 0.037*sl 0.62 + 0.029*sl t r 0.39 0.19 + 0.103*sl 0.18 + 0.105*sl 0.15 + 0.108*sl t f 0.35 0.22 + 0.062*sl 0.27 + 0.046*sl 0.32 + 0.041*sl s1 to y t plh 0.52 0.40 + 0.058*sl 0.42 + 0.051*sl 0.44 + 0.050*sl t phl 0.40 0.31 + 0.048*sl 0.35 + 0.034*sl 0.42 + 0.028*sl t r 0.38 0.17 + 0.107*sl 0.17 + 0.106*sl 0.15 + 0.108*sl t f 0.28 0.16 + 0.059*sl 0.19 + 0.048*sl 0.24 + 0.043*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-516 sec asic mx4/mx4d2 4 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 mx4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.60 0.54 + 0.032*sl 0.55 + 0.027*sl 0.57 + 0.025*sl t phl 0.72 0.65 + 0.035*sl 0.68 + 0.025*sl 0.75 + 0.019*sl t r 0.30 0.19 + 0.054*sl 0.20 + 0.052*sl 0.19 + 0.053*sl t f 0.34 0.27 + 0.037*sl 0.29 + 0.028*sl 0.34 + 0.023*sl d1 to y t plh 0.59 0.53 + 0.032*sl 0.54 + 0.028*sl 0.57 + 0.025*sl t phl 0.72 0.65 + 0.035*sl 0.68 + 0.026*sl 0.75 + 0.019*sl t r 0.30 0.19 + 0.054*sl 0.20 + 0.052*sl 0.19 + 0.053*sl t f 0.34 0.27 + 0.037*sl 0.29 + 0.027*sl 0.35 + 0.023*sl d2 to y t plh 0.59 0.53 + 0.032*sl 0.54 + 0.027*sl 0.56 + 0.025*sl t phl 0.72 0.65 + 0.035*sl 0.67 + 0.025*sl 0.74 + 0.019*sl t r 0.30 0.19 + 0.054*sl 0.20 + 0.052*sl 0.19 + 0.053*sl t f 0.34 0.26 + 0.037*sl 0.29 + 0.028*sl 0.34 + 0.023*sl d3 to y t plh 0.59 0.52 + 0.032*sl 0.54 + 0.027*sl 0.56 + 0.025*sl t phl 0.72 0.65 + 0.035*sl 0.68 + 0.025*sl 0.75 + 0.019*sl t r 0.30 0.19 + 0.054*sl 0.20 + 0.052*sl 0.19 + 0.053*sl t f 0.34 0.27 + 0.037*sl 0.29 + 0.028*sl 0.35 + 0.023*sl s0 to y t plh 0.71 0.64 + 0.032*sl 0.65 + 0.028*sl 0.68 + 0.025*sl t phl 0.59 0.52 + 0.035*sl 0.54 + 0.025*sl 0.61 + 0.019*sl t r 0.30 0.19 + 0.054*sl 0.20 + 0.052*sl 0.19 + 0.053*sl t f 0.33 0.25 + 0.037*sl 0.28 + 0.028*sl 0.34 + 0.023*sl s1 to y t plh 0.52 0.45 + 0.032*sl 0.46 + 0.028*sl 0.49 + 0.025*sl t phl 0.41 0.35 + 0.031*sl 0.37 + 0.024*sl 0.43 + 0.018*sl t r 0.29 0.18 + 0.056*sl 0.19 + 0.053*sl 0.19 + 0.053*sl t f 0.26 0.19 + 0.038*sl 0.21 + 0.029*sl 0.27 + 0.024*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-517 kg80/KGM80 ymx4/ymx4d2 fast 4 > 1 non-inverting mux with 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 ymx4 ymx4d2 ymx4 ymx4d2 d0 d1 d2 d3 s0 s1 d0 d1 d2 d3 s0 s1 2.9 2.9 2.9 2.9 2.3 1.5 2.9 2.9 2.9 2.9 2.3 1.5 6.0 6.0 KGM80 ymx4 ymx4d2 ymx4 ymx4d2 d0 d1 d2 d3 s0 s1 d0 d1 d2 d3 s0 s1 3.7 3.7 3.7 3.7 2.7 1.7 3.7 3.7 3.7 3.7 2.7 1.7 6.0 6.0 y d0 d1 d2 d3 s0 s1 d0 d1 d2 d3 y s0 s1 truth table s0 s1 y 00d0 10d1 01d2 11d3
kg80/KGM80 3-518 sec asic ymx4/ymx4d2 fast 4 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ymx4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.37 0.28 + 0.045*sl 0.29 + 0.041*sl 0.28 + 0.042*sl t phl 0.41 0.34 + 0.037*sl 0.36 + 0.029*sl 0.39 + 0.025*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.041*sl 0.13 + 0.040*sl d1 to y t plh 0.37 0.28 + 0.043*sl 0.29 + 0.041*sl 0.29 + 0.041*sl t phl 0.41 0.34 + 0.037*sl 0.36 + 0.029*sl 0.39 + 0.025*sl t r 0.28 0.11 + 0.086*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.045*sl 0.13 + 0.041*sl 0.13 + 0.041*sl d2 to y t plh 0.37 0.28 + 0.044*sl 0.29 + 0.041*sl 0.28 + 0.041*sl t phl 0.42 0.34 + 0.037*sl 0.36 + 0.029*sl 0.39 + 0.025*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.045*sl 0.13 + 0.041*sl 0.13 + 0.040*sl d3 to y t plh 0.37 0.28 + 0.045*sl 0.29 + 0.041*sl 0.29 + 0.041*sl t phl 0.42 0.34 + 0.038*sl 0.36 + 0.029*sl 0.39 + 0.025*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.13 + 0.040*sl s0 to y t plh 0.49 0.40 + 0.043*sl 0.41 + 0.041*sl 0.41 + 0.041*sl t phl 0.39 0.31 + 0.038*sl 0.34 + 0.029*sl 0.36 + 0.025*sl t r 0.27 0.10 + 0.085*sl 0.10 + 0.088*sl 0.08 + 0.090*sl t f 0.21 0.12 + 0.045*sl 0.12 + 0.041*sl 0.13 + 0.041*sl s1 to y t plh 0.38 0.29 + 0.043*sl 0.29 + 0.041*sl 0.29 + 0.042*sl t phl 0.27 0.20 + 0.035*sl 0.22 + 0.028*sl 0.24 + 0.025*sl t r 0.27 0.10 + 0.087*sl 0.10 + 0.088*sl 0.08 + 0.090*sl t f 0.19 0.10 + 0.046*sl 0.11 + 0.042*sl 0.11 + 0.041*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-519 kg80/KGM80 ymx4/ymx4d2 4 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ymx4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.36 0.31 + 0.024*sl 0.32 + 0.021*sl 0.32 + 0.021*sl t phl 0.41 0.36 + 0.023*sl 0.38 + 0.018*sl 0.40 + 0.015*sl t r 0.20 0.12 + 0.042*sl 0.12 + 0.043*sl 0.10 + 0.045*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.022*sl 0.15 + 0.021*sl d1 to y t plh 0.36 0.32 + 0.023*sl 0.32 + 0.021*sl 0.32 + 0.021*sl t phl 0.41 0.36 + 0.023*sl 0.37 + 0.018*sl 0.39 + 0.015*sl t r 0.20 0.12 + 0.043*sl 0.11 + 0.043*sl 0.10 + 0.045*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.022*sl 0.15 + 0.020*sl d2 to y t plh 0.36 0.31 + 0.024*sl 0.32 + 0.021*sl 0.32 + 0.021*sl t phl 0.41 0.37 + 0.022*sl 0.38 + 0.018*sl 0.40 + 0.015*sl t r 0.20 0.12 + 0.043*sl 0.12 + 0.043*sl 0.11 + 0.044*sl t f 0.18 0.14 + 0.025*sl 0.14 + 0.022*sl 0.15 + 0.021*sl d3 to y t plh 0.36 0.31 + 0.024*sl 0.32 + 0.021*sl 0.32 + 0.021*sl t phl 0.41 0.36 + 0.023*sl 0.38 + 0.018*sl 0.40 + 0.015*sl t r 0.20 0.12 + 0.043*sl 0.12 + 0.043*sl 0.11 + 0.044*sl t f 0.18 0.14 + 0.025*sl 0.14 + 0.022*sl 0.15 + 0.021*sl s0 to y t plh 0.48 0.43 + 0.023*sl 0.43 + 0.022*sl 0.44 + 0.021*sl t phl 0.38 0.34 + 0.023*sl 0.35 + 0.018*sl 0.37 + 0.015*sl t r 0.20 0.11 + 0.042*sl 0.11 + 0.044*sl 0.10 + 0.045*sl t f 0.18 0.13 + 0.026*sl 0.14 + 0.022*sl 0.15 + 0.021*sl s1 to y t plh 0.36 0.32 + 0.023*sl 0.32 + 0.022*sl 0.32 + 0.021*sl t phl 0.26 0.22 + 0.021*sl 0.23 + 0.018*sl 0.25 + 0.015*sl t r 0.20 0.12 + 0.041*sl 0.11 + 0.044*sl 0.10 + 0.045*sl t f 0.17 0.12 + 0.023*sl 0.12 + 0.022*sl 0.13 + 0.021*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-520 sec asic ymx4/ymx4d2 fast 4 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ymx4 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.53 0.42 + 0.054*sl 0.43 + 0.050*sl 0.43 + 0.050*sl t phl 0.59 0.50 + 0.045*sl 0.53 + 0.031*sl 0.60 + 0.025*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.27 0.16 + 0.050*sl 0.19 + 0.042*sl 0.20 + 0.041*sl d1 to y t plh 0.53 0.43 + 0.053*sl 0.44 + 0.050*sl 0.44 + 0.050*sl t phl 0.58 0.49 + 0.045*sl 0.53 + 0.031*sl 0.59 + 0.025*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.27 0.16 + 0.050*sl 0.19 + 0.042*sl 0.20 + 0.041*sl d2 to y t plh 0.53 0.42 + 0.054*sl 0.43 + 0.050*sl 0.43 + 0.050*sl t phl 0.59 0.50 + 0.045*sl 0.54 + 0.031*sl 0.60 + 0.025*sl t r 0.36 0.15 + 0.102*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.27 0.17 + 0.050*sl 0.19 + 0.042*sl 0.20 + 0.041*sl d3 to y t plh 0.53 0.43 + 0.054*sl 0.43 + 0.050*sl 0.44 + 0.050*sl t phl 0.59 0.50 + 0.045*sl 0.53 + 0.031*sl 0.60 + 0.025*sl t r 0.36 0.15 + 0.102*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.27 0.17 + 0.050*sl 0.19 + 0.042*sl 0.20 + 0.041*sl s0 to y t plh 0.65 0.54 + 0.054*sl 0.55 + 0.050*sl 0.56 + 0.050*sl t phl 0.57 0.48 + 0.045*sl 0.52 + 0.031*sl 0.58 + 0.025*sl t r 0.35 0.15 + 0.104*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.27 0.17 + 0.050*sl 0.19 + 0.042*sl 0.20 + 0.041*sl s1 to y t plh 0.49 0.39 + 0.054*sl 0.40 + 0.050*sl 0.40 + 0.050*sl t phl 0.39 0.31 + 0.042*sl 0.34 + 0.030*sl 0.39 + 0.025*sl t r 0.35 0.15 + 0.104*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.24 0.14 + 0.051*sl 0.16 + 0.043*sl 0.18 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-521 kg80/KGM80 ymx4/ymx4d2 4 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ymx4d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.52 0.46 + 0.030*sl 0.47 + 0.026*sl 0.48 + 0.025*sl t phl 0.59 0.53 + 0.028*sl 0.55 + 0.020*sl 0.60 + 0.015*sl t r 0.26 0.15 + 0.054*sl 0.16 + 0.052*sl 0.14 + 0.053*sl t f 0.24 0.18 + 0.030*sl 0.20 + 0.024*sl 0.23 + 0.021*sl d1 to y t plh 0.52 0.46 + 0.030*sl 0.47 + 0.026*sl 0.48 + 0.025*sl t phl 0.58 0.53 + 0.028*sl 0.55 + 0.020*sl 0.60 + 0.015*sl t r 0.26 0.16 + 0.052*sl 0.16 + 0.052*sl 0.14 + 0.053*sl t f 0.24 0.18 + 0.030*sl 0.20 + 0.024*sl 0.23 + 0.021*sl d2 to y t plh 0.51 0.45 + 0.030*sl 0.46 + 0.026*sl 0.47 + 0.025*sl t phl 0.59 0.53 + 0.029*sl 0.56 + 0.020*sl 0.61 + 0.015*sl t r 0.26 0.16 + 0.052*sl 0.16 + 0.052*sl 0.14 + 0.053*sl t f 0.24 0.18 + 0.030*sl 0.20 + 0.024*sl 0.23 + 0.021*sl d3 to y t plh 0.52 0.46 + 0.030*sl 0.47 + 0.026*sl 0.48 + 0.025*sl t phl 0.59 0.53 + 0.029*sl 0.55 + 0.020*sl 0.60 + 0.015*sl t r 0.26 0.16 + 0.052*sl 0.16 + 0.052*sl 0.14 + 0.053*sl t f 0.24 0.18 + 0.030*sl 0.20 + 0.024*sl 0.23 + 0.021*sl s0 to y t plh 0.64 0.58 + 0.030*sl 0.59 + 0.026*sl 0.60 + 0.025*sl t phl 0.57 0.51 + 0.029*sl 0.54 + 0.020*sl 0.59 + 0.015*sl t r 0.26 0.15 + 0.052*sl 0.15 + 0.052*sl 0.14 + 0.053*sl t f 0.24 0.18 + 0.030*sl 0.20 + 0.024*sl 0.23 + 0.021*sl s1 to y t plh 0.48 0.42 + 0.030*sl 0.43 + 0.026*sl 0.44 + 0.025*sl t phl 0.39 0.33 + 0.027*sl 0.35 + 0.020*sl 0.40 + 0.015*sl t r 0.26 0.15 + 0.053*sl 0.15 + 0.052*sl 0.14 + 0.053*sl t f 0.22 0.16 + 0.029*sl 0.17 + 0.024*sl 0.21 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-522 sec asic mx5/mx5d2 5 > 1 non-inverting mux with 1x/2x drive logic symbol cell data schematic diagram input load (sl) gate count kg80 mx5 mx5d2 mx5 mx5d2 d0 d1 d2 d3 d4 s0 s1 s2 d0 d1 d2 d3 d4 s0 s1 s2 0.9 0.9 0.9 0.9 1.0 0.9 1.7 1.2 0.9 0.9 0.9 0.9 1.0 0.9 1.7 1.2 11.0 11.0 KGM80 mx5 mx5d2 mx5 mx5d2 d0 d1 d2 d3 d4 s0 s1 s2 d0 d1 d2 d3 d4 s0 s1 s2 1.0 1.0 1.0 1.0 1.0 1.0 2.0 1.8 1.0 1.0 1.0 1.0 1.0 1.0 2.0 1.8 11.0 11.0 y s0 s1 s2 d0 d1 d2 d3 d4 d0 d1 d2 d3 s0 s0b s0 s0b s0 s0 s0b s0 d4 s2 s2b s1b s1 s1 s1b s2b s2 y s1b s1 s1 s2b s2 s2 truth table s0 s1 s2 y 000d0 100d1 010d2 110d3 xx1d4
sec asic 3-523 kg80/KGM80 mx5/mx5d2 5 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 mx5 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.70 0.62 + 0.043*sl 0.62 + 0.041*sl 0.62 + 0.041*sl t phl 0.76 0.68 + 0.036*sl 0.70 + 0.028*sl 0.73 + 0.025*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.043*sl 0.12 + 0.041*sl 0.13 + 0.041*sl d1 to y t plh 0.71 0.62 + 0.043*sl 0.62 + 0.041*sl 0.62 + 0.041*sl t phl 0.76 0.69 + 0.036*sl 0.71 + 0.028*sl 0.73 + 0.025*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.045*sl 0.13 + 0.040*sl 0.13 + 0.041*sl d2 to y t plh 0.69 0.61 + 0.043*sl 0.61 + 0.041*sl 0.61 + 0.042*sl t phl 0.75 0.68 + 0.036*sl 0.69 + 0.028*sl 0.72 + 0.025*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.045*sl 0.13 + 0.040*sl 0.13 + 0.041*sl d3 to y t plh 0.70 0.61 + 0.043*sl 0.61 + 0.041*sl 0.61 + 0.042*sl t phl 0.75 0.68 + 0.036*sl 0.70 + 0.028*sl 0.72 + 0.025*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.040*sl 0.12 + 0.041*sl d4 to y t plh 0.32 0.24 + 0.043*sl 0.24 + 0.041*sl 0.24 + 0.042*sl t phl 0.38 0.31 + 0.036*sl 0.33 + 0.028*sl 0.35 + 0.025*sl t r 0.28 0.13 + 0.079*sl 0.11 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.13 + 0.043*sl 0.13 + 0.041*sl 0.13 + 0.040*sl s0 to y t plh 0.87 0.78 + 0.043*sl 0.78 + 0.041*sl 0.78 + 0.041*sl t phl 0.75 0.68 + 0.036*sl 0.69 + 0.028*sl 0.72 + 0.025*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.040*sl 0.13 + 0.041*sl s1 to y t plh 0.52 0.44 + 0.043*sl 0.44 + 0.041*sl 0.44 + 0.041*sl t phl 0.40 0.33 + 0.036*sl 0.35 + 0.028*sl 0.38 + 0.025*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.043*sl 0.13 + 0.041*sl 0.13 + 0.040*sl s2 to y t plh 0.38 0.29 + 0.043*sl 0.30 + 0.041*sl 0.29 + 0.042*sl t phl 0.27 0.20 + 0.035*sl 0.22 + 0.028*sl 0.24 + 0.025*sl t r 0.28 0.10 + 0.087*sl 0.10 + 0.089*sl 0.09 + 0.090*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.042*sl 0.11 + 0.041*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-524 sec asic mx5/mx5d2 5 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 mx5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.68 0.64 + 0.024*sl 0.64 + 0.022*sl 0.65 + 0.021*sl t phl 0.75 0.70 + 0.024*sl 0.71 + 0.018*sl 0.74 + 0.015*sl t r 0.19 0.10 + 0.041*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.022*sl 0.14 + 0.021*sl d1 to y t plh 0.69 0.64 + 0.024*sl 0.65 + 0.021*sl 0.65 + 0.021*sl t phl 0.75 0.70 + 0.025*sl 0.72 + 0.018*sl 0.74 + 0.015*sl t r 0.19 0.10 + 0.041*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.022*sl 0.14 + 0.021*sl d2 to y t plh 0.68 0.63 + 0.024*sl 0.63 + 0.022*sl 0.64 + 0.021*sl t phl 0.74 0.69 + 0.025*sl 0.70 + 0.018*sl 0.73 + 0.015*sl t r 0.18 0.10 + 0.042*sl 0.10 + 0.042*sl 0.09 + 0.044*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.022*sl 0.14 + 0.021*sl d3 to y t plh 0.68 0.63 + 0.025*sl 0.64 + 0.021*sl 0.64 + 0.021*sl t phl 0.74 0.69 + 0.024*sl 0.71 + 0.018*sl 0.73 + 0.015*sl t r 0.18 0.10 + 0.041*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.022*sl 0.14 + 0.020*sl d4 to y t plh 0.30 0.26 + 0.024*sl 0.26 + 0.021*sl 0.27 + 0.021*sl t phl 0.37 0.32 + 0.026*sl 0.34 + 0.018*sl 0.36 + 0.015*sl t r 0.18 0.10 + 0.040*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.18 0.14 + 0.022*sl 0.14 + 0.022*sl 0.15 + 0.020*sl s0 to y t plh 0.85 0.80 + 0.025*sl 0.81 + 0.021*sl 0.81 + 0.021*sl t phl 0.74 0.69 + 0.024*sl 0.70 + 0.018*sl 0.73 + 0.015*sl t r 0.18 0.10 + 0.042*sl 0.10 + 0.042*sl 0.09 + 0.044*sl t f 0.17 0.12 + 0.026*sl 0.13 + 0.022*sl 0.14 + 0.021*sl s1 to y t plh 0.51 0.46 + 0.024*sl 0.46 + 0.022*sl 0.47 + 0.021*sl t phl 0.40 0.35 + 0.024*sl 0.36 + 0.018*sl 0.38 + 0.015*sl t r 0.18 0.10 + 0.040*sl 0.10 + 0.043*sl 0.09 + 0.044*sl t f 0.17 0.12 + 0.025*sl 0.13 + 0.022*sl 0.14 + 0.021*sl s2 to y t plh 0.35 0.31 + 0.023*sl 0.31 + 0.022*sl 0.32 + 0.021*sl t phl 0.26 0.21 + 0.023*sl 0.22 + 0.018*sl 0.25 + 0.015*sl t r 0.18 0.09 + 0.042*sl 0.09 + 0.043*sl 0.08 + 0.044*sl t f 0.16 0.11 + 0.025*sl 0.11 + 0.022*sl 0.12 + 0.021*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-525 kg80/KGM80 mx5/mx5d2 5 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 mx5 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 1.01 0.90 + 0.053*sl 0.91 + 0.050*sl 0.91 + 0.050*sl t phl 1.09 1.00 + 0.043*sl 1.04 + 0.030*sl 1.09 + 0.025*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.26 0.16 + 0.049*sl 0.18 + 0.042*sl 0.19 + 0.041*sl d1 to y t plh 1.01 0.90 + 0.053*sl 0.91 + 0.050*sl 0.91 + 0.050*sl t phl 1.09 1.01 + 0.043*sl 1.04 + 0.030*sl 1.10 + 0.025*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.26 0.16 + 0.049*sl 0.18 + 0.042*sl 0.19 + 0.041*sl d2 to y t plh 1.00 0.89 + 0.053*sl 0.90 + 0.050*sl 0.90 + 0.050*sl t phl 1.07 0.98 + 0.043*sl 1.02 + 0.030*sl 1.08 + 0.025*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.26 0.16 + 0.049*sl 0.18 + 0.042*sl 0.19 + 0.041*sl d3 to y t plh 1.00 0.89 + 0.053*sl 0.90 + 0.050*sl 0.90 + 0.050*sl t phl 1.07 0.99 + 0.043*sl 1.02 + 0.030*sl 1.08 + 0.025*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.26 0.16 + 0.049*sl 0.18 + 0.042*sl 0.19 + 0.041*sl d4 to y t plh 0.43 0.32 + 0.051*sl 0.33 + 0.050*sl 0.33 + 0.050*sl t phl 0.52 0.43 + 0.043*sl 0.47 + 0.030*sl 0.52 + 0.025*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.27 0.17 + 0.049*sl 0.19 + 0.042*sl 0.19 + 0.041*sl s0 to y t plh 1.23 1.12 + 0.053*sl 1.13 + 0.050*sl 1.13 + 0.050*sl t phl 1.08 0.99 + 0.043*sl 1.03 + 0.030*sl 1.08 + 0.025*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.26 0.16 + 0.049*sl 0.18 + 0.042*sl 0.19 + 0.041*sl s1 to y t plh 0.72 0.61 + 0.053*sl 0.62 + 0.050*sl 0.62 + 0.050*sl t phl 0.59 0.50 + 0.043*sl 0.54 + 0.030*sl 0.59 + 0.025*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.109*sl t f 0.26 0.16 + 0.049*sl 0.18 + 0.042*sl 0.19 + 0.041*sl s2 to y t plh 0.49 0.39 + 0.052*sl 0.39 + 0.050*sl 0.40 + 0.050*sl t phl 0.38 0.30 + 0.040*sl 0.33 + 0.029*sl 0.38 + 0.025*sl t r 0.36 0.15 + 0.104*sl 0.14 + 0.107*sl 0.13 + 0.109*sl t f 0.24 0.14 + 0.050*sl 0.16 + 0.043*sl 0.17 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-526 sec asic mx5/mx5d2 5 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 mx5d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.98 0.92 + 0.031*sl 0.93 + 0.026*sl 0.95 + 0.025*sl t phl 1.08 1.02 + 0.030*sl 1.05 + 0.021*sl 1.10 + 0.016*sl t r 0.24 0.13 + 0.053*sl 0.13 + 0.052*sl 0.12 + 0.053*sl t f 0.22 0.16 + 0.031*sl 0.18 + 0.024*sl 0.21 + 0.021*sl d1 to y t plh 0.99 0.92 + 0.031*sl 0.94 + 0.026*sl 0.95 + 0.025*sl t phl 1.09 1.03 + 0.030*sl 1.05 + 0.021*sl 1.11 + 0.015*sl t r 0.24 0.13 + 0.053*sl 0.13 + 0.052*sl 0.12 + 0.053*sl t f 0.22 0.16 + 0.031*sl 0.18 + 0.024*sl 0.21 + 0.021*sl d2 to y t plh 0.97 0.91 + 0.031*sl 0.92 + 0.026*sl 0.94 + 0.025*sl t phl 1.07 1.01 + 0.030*sl 1.03 + 0.021*sl 1.09 + 0.016*sl t r 0.24 0.13 + 0.053*sl 0.13 + 0.052*sl 0.12 + 0.053*sl t f 0.22 0.16 + 0.031*sl 0.18 + 0.024*sl 0.21 + 0.021*sl d3 to y t plh 0.97 0.91 + 0.031*sl 0.92 + 0.026*sl 0.94 + 0.025*sl t phl 1.07 1.01 + 0.030*sl 1.03 + 0.021*sl 1.09 + 0.016*sl t r 0.24 0.13 + 0.052*sl 0.13 + 0.052*sl 0.12 + 0.053*sl t f 0.22 0.16 + 0.031*sl 0.18 + 0.024*sl 0.21 + 0.021*sl d4 to y t plh 0.40 0.34 + 0.029*sl 0.35 + 0.026*sl 0.36 + 0.025*sl t phl 0.51 0.45 + 0.030*sl 0.48 + 0.021*sl 0.53 + 0.016*sl t r 0.23 0.13 + 0.053*sl 0.13 + 0.052*sl 0.11 + 0.054*sl t f 0.23 0.17 + 0.031*sl 0.19 + 0.024*sl 0.22 + 0.021*sl s0 to y t plh 1.20 1.14 + 0.030*sl 1.15 + 0.026*sl 1.16 + 0.025*sl t phl 1.07 1.01 + 0.030*sl 1.04 + 0.021*sl 1.09 + 0.015*sl t r 0.24 0.13 + 0.052*sl 0.13 + 0.052*sl 0.12 + 0.053*sl t f 0.22 0.16 + 0.032*sl 0.18 + 0.024*sl 0.21 + 0.021*sl s1 to y t plh 0.69 0.63 + 0.031*sl 0.64 + 0.026*sl 0.65 + 0.025*sl t phl 0.58 0.52 + 0.030*sl 0.55 + 0.021*sl 0.60 + 0.015*sl t r 0.23 0.13 + 0.053*sl 0.13 + 0.052*sl 0.12 + 0.053*sl t f 0.22 0.16 + 0.032*sl 0.18 + 0.024*sl 0.22 + 0.021*sl s2 to y t plh 0.46 0.40 + 0.030*sl 0.41 + 0.026*sl 0.42 + 0.025*sl t phl 0.37 0.31 + 0.029*sl 0.33 + 0.020*sl 0.38 + 0.015*sl t r 0.23 0.13 + 0.052*sl 0.13 + 0.052*sl 0.11 + 0.054*sl t f 0.20 0.14 + 0.032*sl 0.16 + 0.024*sl 0.19 + 0.022*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-527 kg80/KGM80 mx8/mx8d2 8 > 1 non-inverting mux with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 mx8 mx8 d0 d1 d2 d3 d4 d5 d6 d7 s0 s1 s2 0.8 0.9 1.0 0.9 0.9 0.9 1.0 0.9 0.9 1.8 1.2 14.0 mx8d2 mx8d2 d0 d1 d2 d3 d4 d5 d6 d7 s0 s1 s2 0.8 0.9 1.0 0.9 0.9 0.9 1.0 0.9 0.9 1.8 1.2 15.0 KGM80 mx8 mx8 d0 d1 d2 d3 d4 d5 d6 d7 s0 s1 s2 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.1 2.8 1.8 14.0 mx8d2 mx8d2 d0 d1 d2 d3 d4 d5 d6 d7 s0 s1 s2 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.1 2.8 1.8 15.0 y d0 d1 d2 d3 d4 d5 d6 d7 s0 s1 s2 truth table s0 s1 s2 y 000d0 100d1 010d2 110d3 001d4 101d5 011d6 111d7
kg80/KGM80 3-528 sec asic mx8/mx8d2 8 > 1 non-inverting mux with 1x/2x drive schematic diagram d0 d1 d2 d3 s0 s0b s0 s0b s0 s0 s0b s1b s1 s1 s0 s1b s1 s1 s1b s2b s2 y d4 d5 d6 d7 s0 s0b s0 s0b s1b s1 s1 s1b s2 s2b s2b s2 s2
sec asic 3-529 kg80/KGM80 mx8/mx8d2 8 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 mx8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.59 0.49 + 0.050*sl 0.51 + 0.044*sl 0.52 + 0.042*sl t phl 0.63 0.53 + 0.053*sl 0.56 + 0.040*sl 0.61 + 0.032*sl t r 0.34 0.17 + 0.085*sl 0.17 + 0.085*sl 0.15 + 0.087*sl t f 0.34 0.23 + 0.058*sl 0.25 + 0.048*sl 0.29 + 0.043*sl d1 to y t plh 0.59 0.49 + 0.050*sl 0.51 + 0.044*sl 0.52 + 0.042*sl t phl 0.64 0.53 + 0.052*sl 0.56 + 0.040*sl 0.61 + 0.032*sl t r 0.34 0.17 + 0.085*sl 0.17 + 0.085*sl 0.15 + 0.087*sl t f 0.34 0.23 + 0.058*sl 0.25 + 0.048*sl 0.29 + 0.043*sl d2 to y t plh 0.59 0.49 + 0.049*sl 0.50 + 0.044*sl 0.52 + 0.042*sl t phl 0.63 0.53 + 0.053*sl 0.56 + 0.040*sl 0.61 + 0.032*sl t r 0.34 0.17 + 0.086*sl 0.17 + 0.085*sl 0.15 + 0.087*sl t f 0.34 0.23 + 0.058*sl 0.25 + 0.048*sl 0.29 + 0.042*sl d3 to y t plh 0.59 0.49 + 0.049*sl 0.50 + 0.044*sl 0.52 + 0.042*sl t phl 0.63 0.53 + 0.053*sl 0.56 + 0.040*sl 0.61 + 0.032*sl t r 0.34 0.17 + 0.085*sl 0.17 + 0.086*sl 0.15 + 0.087*sl t f 0.34 0.23 + 0.058*sl 0.25 + 0.048*sl 0.29 + 0.042*sl d4 to y t plh 0.59 0.49 + 0.049*sl 0.50 + 0.044*sl 0.52 + 0.042*sl t phl 0.63 0.53 + 0.052*sl 0.56 + 0.040*sl 0.61 + 0.032*sl t r 0.34 0.17 + 0.084*sl 0.17 + 0.085*sl 0.15 + 0.088*sl t f 0.34 0.22 + 0.059*sl 0.25 + 0.048*sl 0.29 + 0.043*sl d5 to y t plh 0.59 0.49 + 0.049*sl 0.50 + 0.044*sl 0.52 + 0.042*sl t phl 0.63 0.53 + 0.053*sl 0.56 + 0.040*sl 0.61 + 0.032*sl t r 0.34 0.17 + 0.083*sl 0.17 + 0.085*sl 0.15 + 0.087*sl t f 0.34 0.22 + 0.059*sl 0.25 + 0.048*sl 0.29 + 0.043*sl d6 to y t plh 0.58 0.48 + 0.050*sl 0.50 + 0.044*sl 0.51 + 0.042*sl t phl 0.63 0.52 + 0.052*sl 0.55 + 0.040*sl 0.60 + 0.032*sl t r 0.34 0.17 + 0.083*sl 0.17 + 0.085*sl 0.15 + 0.087*sl t f 0.34 0.22 + 0.060*sl 0.25 + 0.047*sl 0.29 + 0.042*sl d7 to y t plh 0.58 0.48 + 0.050*sl 0.50 + 0.044*sl 0.51 + 0.042*sl t phl 0.63 0.52 + 0.052*sl 0.55 + 0.040*sl 0.61 + 0.032*sl t r 0.34 0.17 + 0.085*sl 0.17 + 0.085*sl 0.15 + 0.087*sl t f 0.34 0.22 + 0.059*sl 0.25 + 0.047*sl 0.28 + 0.043*sl s0 to y t plh 0.85 0.75 + 0.050*sl 0.76 + 0.044*sl 0.78 + 0.042*sl t phl 0.72 0.62 + 0.052*sl 0.65 + 0.040*sl 0.70 + 0.032*sl t r 0.34 0.17 + 0.085*sl 0.17 + 0.085*sl 0.15 + 0.087*sl t f 0.33 0.22 + 0.059*sl 0.24 + 0.048*sl 0.28 + 0.043*sl s1 to y t plh 0.56 0.46 + 0.050*sl 0.48 + 0.044*sl 0.49 + 0.042*sl t phl 0.42 0.32 + 0.051*sl 0.35 + 0.039*sl 0.40 + 0.032*sl t r 0.34 0.17 + 0.085*sl 0.16 + 0.086*sl 0.15 + 0.088*sl t f 0.30 0.17 + 0.063*sl 0.21 + 0.050*sl 0.25 + 0.044*sl s2 to y t plh 0.42 0.32 + 0.050*sl 0.33 + 0.044*sl 0.35 + 0.042*sl t phl 0.29 0.21 + 0.042*sl 0.23 + 0.035*sl 0.26 + 0.030*sl t r 0.31 0.13 + 0.089*sl 0.13 + 0.088*sl 0.13 + 0.089*sl t f 0.23 0.11 + 0.058*sl 0.13 + 0.050*sl 0.16 + 0.045*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-530 sec asic mx8/mx8d2 8 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 mx8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.60 0.54 + 0.029*sl 0.55 + 0.024*sl 0.57 + 0.022*sl t phl 0.63 0.57 + 0.031*sl 0.59 + 0.025*sl 0.62 + 0.021*sl t r 0.28 0.20 + 0.038*sl 0.19 + 0.042*sl 0.19 + 0.043*sl t f 0.32 0.25 + 0.034*sl 0.27 + 0.028*sl 0.29 + 0.024*sl d1 to y t plh 0.60 0.54 + 0.029*sl 0.55 + 0.024*sl 0.57 + 0.022*sl t phl 0.64 0.57 + 0.031*sl 0.59 + 0.025*sl 0.62 + 0.021*sl t r 0.28 0.20 + 0.039*sl 0.19 + 0.043*sl 0.19 + 0.042*sl t f 0.32 0.25 + 0.034*sl 0.27 + 0.028*sl 0.29 + 0.024*sl d2 to y t plh 0.59 0.54 + 0.029*sl 0.55 + 0.024*sl 0.56 + 0.022*sl t phl 0.63 0.57 + 0.031*sl 0.59 + 0.025*sl 0.62 + 0.020*sl t r 0.28 0.20 + 0.040*sl 0.19 + 0.042*sl 0.19 + 0.042*sl t f 0.32 0.25 + 0.033*sl 0.26 + 0.028*sl 0.29 + 0.024*sl d3 to y t plh 0.59 0.54 + 0.028*sl 0.55 + 0.024*sl 0.56 + 0.022*sl t phl 0.63 0.57 + 0.031*sl 0.59 + 0.025*sl 0.62 + 0.021*sl t r 0.28 0.20 + 0.040*sl 0.20 + 0.042*sl 0.19 + 0.043*sl t f 0.32 0.25 + 0.033*sl 0.26 + 0.028*sl 0.29 + 0.024*sl d4 to y t plh 0.60 0.54 + 0.029*sl 0.55 + 0.024*sl 0.56 + 0.022*sl t phl 0.63 0.57 + 0.031*sl 0.59 + 0.025*sl 0.62 + 0.021*sl t r 0.28 0.20 + 0.040*sl 0.20 + 0.042*sl 0.19 + 0.043*sl t f 0.32 0.25 + 0.035*sl 0.26 + 0.028*sl 0.29 + 0.024*sl d5 to y t plh 0.59 0.54 + 0.029*sl 0.55 + 0.024*sl 0.56 + 0.022*sl t phl 0.63 0.57 + 0.031*sl 0.58 + 0.025*sl 0.62 + 0.020*sl t r 0.28 0.20 + 0.041*sl 0.20 + 0.042*sl 0.19 + 0.043*sl t f 0.32 0.25 + 0.034*sl 0.26 + 0.028*sl 0.29 + 0.024*sl d6 to y t plh 0.59 0.53 + 0.028*sl 0.54 + 0.024*sl 0.55 + 0.022*sl t phl 0.63 0.56 + 0.031*sl 0.58 + 0.025*sl 0.61 + 0.020*sl t r 0.28 0.20 + 0.040*sl 0.19 + 0.042*sl 0.19 + 0.043*sl t f 0.32 0.25 + 0.034*sl 0.26 + 0.028*sl 0.29 + 0.024*sl d7 to y t plh 0.59 0.53 + 0.028*sl 0.54 + 0.024*sl 0.55 + 0.022*sl t phl 0.63 0.57 + 0.031*sl 0.58 + 0.025*sl 0.61 + 0.020*sl t r 0.28 0.20 + 0.041*sl 0.19 + 0.042*sl 0.19 + 0.042*sl t f 0.32 0.25 + 0.034*sl 0.26 + 0.028*sl 0.29 + 0.025*sl s0 to y t plh 0.85 0.80 + 0.028*sl 0.81 + 0.024*sl 0.82 + 0.022*sl t phl 0.72 0.66 + 0.031*sl 0.67 + 0.025*sl 0.70 + 0.020*sl t r 0.28 0.20 + 0.040*sl 0.19 + 0.042*sl 0.19 + 0.042*sl t f 0.31 0.24 + 0.034*sl 0.26 + 0.028*sl 0.28 + 0.025*sl s1 to y t plh 0.57 0.51 + 0.029*sl 0.52 + 0.024*sl 0.53 + 0.022*sl t phl 0.42 0.36 + 0.031*sl 0.37 + 0.025*sl 0.40 + 0.020*sl t r 0.28 0.20 + 0.040*sl 0.19 + 0.043*sl 0.19 + 0.043*sl t f 0.28 0.21 + 0.036*sl 0.22 + 0.029*sl 0.25 + 0.026*sl s2 to y t plh 0.42 0.36 + 0.028*sl 0.37 + 0.024*sl 0.39 + 0.022*sl t phl 0.29 0.24 + 0.026*sl 0.25 + 0.022*sl 0.27 + 0.019*sl t r 0.25 0.17 + 0.043*sl 0.17 + 0.044*sl 0.17 + 0.043*sl t f 0.21 0.14 + 0.034*sl 0.15 + 0.030*sl 0.18 + 0.026*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-531 kg80/KGM80 mx8/mx8d2 8 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 mx8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.82 0.69 + 0.063*sl 0.72 + 0.053*sl 0.76 + 0.050*sl t phl 0.94 0.80 + 0.070*sl 0.87 + 0.047*sl 1.01 + 0.034*sl t r 0.43 0.21 + 0.109*sl 0.22 + 0.105*sl 0.21 + 0.106*sl t f 0.48 0.33 + 0.075*sl 0.39 + 0.052*sl 0.48 + 0.044*sl d1 to y t plh 0.82 0.70 + 0.063*sl 0.72 + 0.053*sl 0.76 + 0.050*sl t phl 0.95 0.80 + 0.070*sl 0.87 + 0.047*sl 1.01 + 0.034*sl t r 0.43 0.21 + 0.109*sl 0.22 + 0.105*sl 0.21 + 0.106*sl t f 0.48 0.33 + 0.073*sl 0.39 + 0.052*sl 0.48 + 0.044*sl d2 to y t plh 0.81 0.69 + 0.063*sl 0.71 + 0.053*sl 0.75 + 0.050*sl t phl 0.94 0.80 + 0.070*sl 0.87 + 0.047*sl 1.01 + 0.034*sl t r 0.43 0.21 + 0.109*sl 0.22 + 0.105*sl 0.20 + 0.106*sl t f 0.48 0.33 + 0.074*sl 0.39 + 0.052*sl 0.48 + 0.044*sl d3 to y t plh 0.81 0.69 + 0.063*sl 0.71 + 0.053*sl 0.75 + 0.050*sl t phl 0.94 0.80 + 0.070*sl 0.86 + 0.047*sl 1.01 + 0.034*sl t r 0.43 0.21 + 0.109*sl 0.22 + 0.105*sl 0.20 + 0.106*sl t f 0.48 0.33 + 0.074*sl 0.39 + 0.052*sl 0.48 + 0.044*sl d4 to y t plh 0.82 0.69 + 0.063*sl 0.72 + 0.053*sl 0.75 + 0.050*sl t phl 0.94 0.80 + 0.070*sl 0.86 + 0.047*sl 1.00 + 0.034*sl t r 0.43 0.21 + 0.108*sl 0.22 + 0.105*sl 0.21 + 0.106*sl t f 0.48 0.33 + 0.074*sl 0.39 + 0.052*sl 0.48 + 0.044*sl d5 to y t plh 0.81 0.69 + 0.063*sl 0.71 + 0.053*sl 0.75 + 0.050*sl t phl 0.94 0.80 + 0.070*sl 0.86 + 0.047*sl 1.00 + 0.034*sl t r 0.43 0.21 + 0.108*sl 0.22 + 0.105*sl 0.21 + 0.106*sl t f 0.48 0.33 + 0.074*sl 0.39 + 0.052*sl 0.48 + 0.044*sl d6 to y t plh 0.80 0.68 + 0.063*sl 0.70 + 0.053*sl 0.74 + 0.050*sl t phl 0.93 0.79 + 0.070*sl 0.86 + 0.047*sl 1.00 + 0.034*sl t r 0.43 0.21 + 0.108*sl 0.22 + 0.105*sl 0.20 + 0.106*sl t f 0.47 0.33 + 0.074*sl 0.39 + 0.052*sl 0.48 + 0.043*sl d7 to y t plh 0.80 0.68 + 0.063*sl 0.70 + 0.053*sl 0.74 + 0.050*sl t phl 0.93 0.79 + 0.070*sl 0.86 + 0.047*sl 1.00 + 0.034*sl t r 0.43 0.21 + 0.108*sl 0.22 + 0.105*sl 0.20 + 0.106*sl t f 0.47 0.33 + 0.074*sl 0.39 + 0.052*sl 0.48 + 0.043*sl s0 to y t plh 1.18 1.06 + 0.063*sl 1.08 + 0.053*sl 1.12 + 0.050*sl t phl 1.10 0.96 + 0.069*sl 1.02 + 0.046*sl 1.16 + 0.034*sl t r 0.43 0.22 + 0.108*sl 0.22 + 0.105*sl 0.21 + 0.106*sl t f 0.46 0.32 + 0.074*sl 0.38 + 0.052*sl 0.47 + 0.044*sl s1 to y t plh 0.77 0.64 + 0.063*sl 0.67 + 0.053*sl 0.70 + 0.050*sl t phl 0.64 0.50 + 0.068*sl 0.56 + 0.046*sl 0.70 + 0.034*sl t r 0.43 0.21 + 0.109*sl 0.22 + 0.105*sl 0.20 + 0.106*sl t f 0.43 0.27 + 0.076*sl 0.33 + 0.053*sl 0.44 + 0.044*sl s2 to y t plh 0.55 0.42 + 0.063*sl 0.45 + 0.053*sl 0.49 + 0.050*sl t phl 0.42 0.31 + 0.052*sl 0.35 + 0.039*sl 0.43 + 0.031*sl t r 0.40 0.18 + 0.111*sl 0.19 + 0.106*sl 0.19 + 0.107*sl t f 0.30 0.16 + 0.068*sl 0.20 + 0.053*sl 0.28 + 0.046*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-532 sec asic mx8/mx8d2 8 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 mx8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.83 0.76 + 0.035*sl 0.78 + 0.030*sl 0.81 + 0.026*sl t phl 0.96 0.88 + 0.042*sl 0.91 + 0.031*sl 0.99 + 0.023*sl t r 0.35 0.23 + 0.058*sl 0.24 + 0.053*sl 0.25 + 0.052*sl t f 0.46 0.37 + 0.043*sl 0.40 + 0.033*sl 0.48 + 0.026*sl d1 to y t plh 0.83 0.76 + 0.035*sl 0.78 + 0.030*sl 0.81 + 0.026*sl t phl 0.96 0.88 + 0.042*sl 0.91 + 0.031*sl 0.99 + 0.023*sl t r 0.35 0.23 + 0.058*sl 0.24 + 0.053*sl 0.25 + 0.052*sl t f 0.46 0.37 + 0.044*sl 0.40 + 0.033*sl 0.48 + 0.026*sl d2 to y t plh 0.82 0.76 + 0.035*sl 0.77 + 0.030*sl 0.80 + 0.026*sl t phl 0.96 0.87 + 0.042*sl 0.90 + 0.031*sl 0.99 + 0.023*sl t r 0.34 0.23 + 0.057*sl 0.24 + 0.053*sl 0.25 + 0.052*sl t f 0.46 0.37 + 0.043*sl 0.40 + 0.033*sl 0.47 + 0.026*sl d3 to y t plh 0.82 0.76 + 0.034*sl 0.77 + 0.030*sl 0.80 + 0.026*sl t phl 0.96 0.87 + 0.042*sl 0.90 + 0.031*sl 0.99 + 0.023*sl t r 0.34 0.23 + 0.057*sl 0.24 + 0.053*sl 0.25 + 0.052*sl t f 0.46 0.37 + 0.044*sl 0.40 + 0.033*sl 0.48 + 0.026*sl d4 to y t plh 0.83 0.76 + 0.035*sl 0.77 + 0.030*sl 0.81 + 0.026*sl t phl 0.96 0.87 + 0.042*sl 0.90 + 0.031*sl 0.99 + 0.023*sl t r 0.35 0.23 + 0.057*sl 0.24 + 0.053*sl 0.25 + 0.052*sl t f 0.45 0.36 + 0.045*sl 0.40 + 0.033*sl 0.48 + 0.026*sl d5 to y t plh 0.83 0.76 + 0.035*sl 0.77 + 0.030*sl 0.80 + 0.026*sl t phl 0.96 0.87 + 0.042*sl 0.90 + 0.031*sl 0.98 + 0.023*sl t r 0.35 0.23 + 0.057*sl 0.24 + 0.053*sl 0.25 + 0.052*sl t f 0.45 0.36 + 0.044*sl 0.40 + 0.033*sl 0.47 + 0.026*sl d6 to y t plh 0.81 0.74 + 0.035*sl 0.76 + 0.030*sl 0.79 + 0.026*sl t phl 0.95 0.86 + 0.042*sl 0.90 + 0.031*sl 0.98 + 0.023*sl t r 0.35 0.23 + 0.056*sl 0.24 + 0.053*sl 0.25 + 0.052*sl t f 0.45 0.36 + 0.044*sl 0.40 + 0.033*sl 0.47 + 0.025*sl d7 to y t plh 0.81 0.74 + 0.035*sl 0.76 + 0.030*sl 0.79 + 0.026*sl t phl 0.95 0.87 + 0.042*sl 0.90 + 0.031*sl 0.98 + 0.023*sl t r 0.34 0.23 + 0.057*sl 0.24 + 0.053*sl 0.25 + 0.052*sl t f 0.45 0.36 + 0.044*sl 0.39 + 0.033*sl 0.47 + 0.026*sl s0 to y t plh 1.19 1.12 + 0.035*sl 1.14 + 0.029*sl 1.17 + 0.026*sl t phl 1.11 1.03 + 0.041*sl 1.06 + 0.031*sl 1.14 + 0.023*sl t r 0.35 0.23 + 0.057*sl 0.24 + 0.053*sl 0.25 + 0.052*sl t f 0.44 0.35 + 0.045*sl 0.39 + 0.033*sl 0.46 + 0.026*sl s1 to y t plh 0.78 0.71 + 0.035*sl 0.72 + 0.030*sl 0.75 + 0.026*sl t phl 0.65 0.57 + 0.042*sl 0.60 + 0.030*sl 0.68 + 0.023*sl t r 0.34 0.23 + 0.055*sl 0.24 + 0.053*sl 0.25 + 0.052*sl t f 0.41 0.32 + 0.046*sl 0.35 + 0.034*sl 0.43 + 0.026*sl s2 to y t plh 0.55 0.49 + 0.035*sl 0.50 + 0.030*sl 0.53 + 0.027*sl t phl 0.43 0.36 + 0.034*sl 0.38 + 0.026*sl 0.44 + 0.021*sl t r 0.32 0.21 + 0.058*sl 0.22 + 0.054*sl 0.23 + 0.053*sl t f 0.29 0.20 + 0.043*sl 0.23 + 0.034*sl 0.30 + 0.027*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 3-533 kg80/KGM80 ymx8/ymx8d2 fast 8 > 1 non-inverting mux with 1x/2x drive logic symbol cell data input load (sl) gate count kg80 ymx8/ymx8d2 ymx8 d0 d1 d2 d3 d4 d5 d6 d7 s0 s1 s2 5.1 5.1 5.1 5.1 5.1 5.1 5.1 5.1 0.8 2.0 1.2 11.0 KGM80 ymx8/ymx8d2 ymx8d2 d0 d1 d2 d3 d4 d5 d6 d7 s0 s1 s2 6.4 6.4 6.4 6.4 6.4 6.4 6.4 6.4 0.9 2.3 1.5 11.0 y d0 d1 d2 d3 d4 d5 d6 d7 s0 s1 s2 truth table s0 s1 s2 y 000d0 100d1 010d2 110d3 001d4 101d5 011d6 111d7
kg80/KGM80 3-534 sec asic ymx8/ymx8d2 fast 8 > 1 non-inverting mux with 1x/2x drive schematic diagram d0 d1 d2 d3 y s0 s1 d4 d5 d6 d7 s2
sec asic 3-535 kg80/KGM80 ymx8/ymx8d2 fast 8 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ymx8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.45 0.36 + 0.043*sl 0.37 + 0.041*sl 0.37 + 0.041*sl t phl 0.49 0.42 + 0.038*sl 0.44 + 0.029*sl 0.47 + 0.025*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.045*sl 0.13 + 0.041*sl 0.13 + 0.041*sl d1 to y t plh 0.45 0.36 + 0.043*sl 0.37 + 0.041*sl 0.37 + 0.042*sl t phl 0.49 0.42 + 0.037*sl 0.44 + 0.029*sl 0.47 + 0.025*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.045*sl 0.13 + 0.041*sl 0.13 + 0.041*sl d2 to y t plh 0.45 0.36 + 0.044*sl 0.37 + 0.041*sl 0.37 + 0.041*sl t phl 0.49 0.42 + 0.037*sl 0.44 + 0.029*sl 0.47 + 0.025*sl t r 0.28 0.11 + 0.084*sl 0.11 + 0.087*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.046*sl 0.13 + 0.041*sl 0.14 + 0.040*sl d3 to y t plh 0.45 0.37 + 0.043*sl 0.37 + 0.041*sl 0.37 + 0.041*sl t phl 0.49 0.42 + 0.037*sl 0.44 + 0.029*sl 0.46 + 0.025*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.046*sl 0.13 + 0.041*sl 0.14 + 0.040*sl d4 to y t plh 0.45 0.36 + 0.043*sl 0.37 + 0.041*sl 0.37 + 0.041*sl t phl 0.50 0.42 + 0.038*sl 0.44 + 0.029*sl 0.47 + 0.025*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.13 + 0.040*sl d5 to y t plh 0.45 0.36 + 0.044*sl 0.37 + 0.041*sl 0.37 + 0.041*sl t phl 0.50 0.42 + 0.038*sl 0.44 + 0.029*sl 0.47 + 0.025*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.045*sl 0.13 + 0.041*sl 0.14 + 0.040*sl d6 to y t plh 0.45 0.36 + 0.043*sl 0.37 + 0.041*sl 0.37 + 0.041*sl t phl 0.49 0.42 + 0.037*sl 0.44 + 0.029*sl 0.47 + 0.025*sl t r 0.28 0.11 + 0.084*sl 0.11 + 0.087*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.046*sl 0.13 + 0.041*sl 0.14 + 0.040*sl d7 to y t plh 0.45 0.36 + 0.043*sl 0.37 + 0.041*sl 0.37 + 0.041*sl t phl 0.49 0.42 + 0.037*sl 0.44 + 0.029*sl 0.47 + 0.025*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.087*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.046*sl 0.13 + 0.041*sl 0.14 + 0.040*sl s0 to y t plh 0.83 0.74 + 0.043*sl 0.74 + 0.041*sl 0.74 + 0.042*sl t phl 0.74 0.67 + 0.038*sl 0.69 + 0.029*sl 0.72 + 0.025*sl t r 0.28 0.11 + 0.084*sl 0.10 + 0.088*sl 0.09 + 0.090*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.13 + 0.041*sl s1 to y t plh 0.55 0.46 + 0.043*sl 0.47 + 0.041*sl 0.47 + 0.041*sl t phl 0.43 0.36 + 0.037*sl 0.38 + 0.029*sl 0.40 + 0.025*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.088*sl 0.08 + 0.090*sl t f 0.21 0.12 + 0.045*sl 0.13 + 0.041*sl 0.13 + 0.041*sl s2 to y t plh 0.38 0.29 + 0.043*sl 0.29 + 0.041*sl 0.29 + 0.042*sl t phl 0.27 0.20 + 0.035*sl 0.22 + 0.028*sl 0.24 + 0.025*sl t r 0.27 0.10 + 0.087*sl 0.10 + 0.088*sl 0.08 + 0.090*sl t f 0.19 0.10 + 0.045*sl 0.11 + 0.042*sl 0.11 + 0.041*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 3-536 sec asic ymx8/ymx8d2 fast 8 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 ymx8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.44 0.40 + 0.023*sl 0.40 + 0.022*sl 0.41 + 0.021*sl t phl 0.49 0.44 + 0.023*sl 0.46 + 0.018*sl 0.48 + 0.015*sl t r 0.21 0.12 + 0.042*sl 0.12 + 0.043*sl 0.11 + 0.044*sl t f 0.18 0.13 + 0.026*sl 0.14 + 0.022*sl 0.15 + 0.020*sl d1 to y t plh 0.44 0.40 + 0.023*sl 0.40 + 0.022*sl 0.41 + 0.021*sl t phl 0.49 0.44 + 0.022*sl 0.45 + 0.018*sl 0.48 + 0.015*sl t r 0.21 0.12 + 0.042*sl 0.12 + 0.043*sl 0.11 + 0.044*sl t f 0.19 0.14 + 0.024*sl 0.14 + 0.022*sl 0.15 + 0.021*sl d2 to y t plh 0.45 0.40 + 0.024*sl 0.40 + 0.021*sl 0.41 + 0.021*sl t phl 0.49 0.44 + 0.023*sl 0.45 + 0.018*sl 0.48 + 0.015*sl t r 0.21 0.12 + 0.043*sl 0.12 + 0.043*sl 0.11 + 0.044*sl t f 0.19 0.14 + 0.024*sl 0.14 + 0.022*sl 0.15 + 0.021*sl d3 to y t plh 0.45 0.40 + 0.024*sl 0.40 + 0.021*sl 0.41 + 0.021*sl t phl 0.49 0.44 + 0.023*sl 0.45 + 0.018*sl 0.48 + 0.015*sl t r 0.21 0.12 + 0.043*sl 0.12 + 0.043*sl 0.11 + 0.044*sl t f 0.19 0.14 + 0.024*sl 0.14 + 0.022*sl 0.15 + 0.021*sl d4 to y t plh 0.44 0.40 + 0.023*sl 0.40 + 0.022*sl 0.41 + 0.021*sl t phl 0.49 0.45 + 0.023*sl 0.46 + 0.018*sl 0.48 + 0.015*sl t r 0.21 0.12 + 0.042*sl 0.12 + 0.043*sl 0.11 + 0.044*sl t f 0.19 0.13 + 0.025*sl 0.14 + 0.022*sl 0.15 + 0.020*sl d5 to y t plh 0.44 0.40 + 0.023*sl 0.40 + 0.022*sl 0.41 + 0.021*sl t phl 0.49 0.45 + 0.022*sl 0.46 + 0.018*sl 0.48 + 0.015*sl t r 0.21 0.12 + 0.042*sl 0.12 + 0.043*sl 0.11 + 0.044*sl t f 0.19 0.14 + 0.024*sl 0.14 + 0.022*sl 0.15 + 0.021*sl d6 to y t plh 0.44 0.40 + 0.024*sl 0.40 + 0.021*sl 0.41 + 0.021*sl t phl 0.49 0.44 + 0.023*sl 0.45 + 0.018*sl 0.48 + 0.015*sl t r 0.21 0.12 + 0.041*sl 0.12 + 0.043*sl 0.11 + 0.044*sl t f 0.19 0.14 + 0.025*sl 0.14 + 0.022*sl 0.15 + 0.020*sl d7 to y t plh 0.44 0.40 + 0.024*sl 0.40 + 0.021*sl 0.41 + 0.021*sl t phl 0.49 0.44 + 0.023*sl 0.45 + 0.018*sl 0.48 + 0.015*sl t r 0.21 0.12 + 0.041*sl 0.12 + 0.043*sl 0.11 + 0.044*sl t f 0.19 0.14 + 0.025*sl 0.14 + 0.022*sl 0.15 + 0.020*sl s0 to y t plh 0.82 0.77 + 0.024*sl 0.77 + 0.022*sl 0.78 + 0.021*sl t phl 0.74 0.69 + 0.023*sl 0.70 + 0.018*sl 0.73 + 0.015*sl t r 0.20 0.12 + 0.042*sl 0.12 + 0.043*sl 0.11 + 0.044*sl t f 0.18 0.13 + 0.026*sl 0.14 + 0.022*sl 0.15 + 0.020*sl s1 to y t plh 0.54 0.49 + 0.024*sl 0.50 + 0.022*sl 0.50 + 0.021*sl t phl 0.43 0.38 + 0.023*sl 0.39 + 0.018*sl 0.41 + 0.015*sl t r 0.20 0.12 + 0.042*sl 0.11 + 0.044*sl 0.11 + 0.044*sl t f 0.19 0.13 + 0.026*sl 0.14 + 0.022*sl 0.15 + 0.020*sl s2 to y t plh 0.36 0.31 + 0.024*sl 0.32 + 0.022*sl 0.32 + 0.021*sl t phl 0.26 0.22 + 0.021*sl 0.23 + 0.017*sl 0.25 + 0.015*sl t r 0.20 0.11 + 0.043*sl 0.11 + 0.044*sl 0.10 + 0.045*sl t f 0.17 0.12 + 0.023*sl 0.12 + 0.022*sl 0.13 + 0.021*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 3-537 kg80/KGM80 ymx8/ymx8d2 fast 8 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) ymx8 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.69 0.58 + 0.054*sl 0.59 + 0.050*sl 0.60 + 0.050*sl t phl 0.72 0.63 + 0.045*sl 0.67 + 0.031*sl 0.73 + 0.025*sl t r 0.36 0.16 + 0.102*sl 0.15 + 0.107*sl 0.13 + 0.108*sl t f 0.27 0.16 + 0.050*sl 0.19 + 0.043*sl 0.20 + 0.041*sl d1 to y t plh 0.69 0.58 + 0.054*sl 0.59 + 0.050*sl 0.60 + 0.050*sl t phl 0.72 0.63 + 0.045*sl 0.67 + 0.031*sl 0.73 + 0.025*sl t r 0.36 0.16 + 0.102*sl 0.15 + 0.106*sl 0.13 + 0.108*sl t f 0.27 0.16 + 0.050*sl 0.19 + 0.043*sl 0.20 + 0.041*sl d2 to y t plh 0.70 0.59 + 0.054*sl 0.60 + 0.050*sl 0.60 + 0.050*sl t phl 0.72 0.63 + 0.045*sl 0.67 + 0.031*sl 0.73 + 0.025*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.13 + 0.108*sl t f 0.27 0.16 + 0.051*sl 0.19 + 0.042*sl 0.20 + 0.041*sl d3 to y t plh 0.70 0.59 + 0.054*sl 0.60 + 0.050*sl 0.60 + 0.050*sl t phl 0.72 0.63 + 0.045*sl 0.67 + 0.031*sl 0.73 + 0.025*sl t r 0.36 0.16 + 0.102*sl 0.15 + 0.106*sl 0.12 + 0.109*sl t f 0.27 0.16 + 0.051*sl 0.19 + 0.043*sl 0.20 + 0.041*sl d4 to y t plh 0.69 0.58 + 0.054*sl 0.59 + 0.050*sl 0.60 + 0.050*sl t phl 0.73 0.64 + 0.045*sl 0.67 + 0.031*sl 0.74 + 0.025*sl t r 0.36 0.16 + 0.102*sl 0.15 + 0.106*sl 0.12 + 0.109*sl t f 0.27 0.17 + 0.050*sl 0.19 + 0.042*sl 0.20 + 0.041*sl d5 to y t plh 0.69 0.58 + 0.054*sl 0.59 + 0.050*sl 0.60 + 0.050*sl t phl 0.73 0.64 + 0.045*sl 0.68 + 0.031*sl 0.74 + 0.025*sl t r 0.36 0.16 + 0.102*sl 0.15 + 0.106*sl 0.12 + 0.109*sl t f 0.27 0.17 + 0.050*sl 0.19 + 0.042*sl 0.20 + 0.041*sl d6 to y t plh 0.69 0.59 + 0.054*sl 0.60 + 0.050*sl 0.60 + 0.050*sl t phl 0.72 0.63 + 0.045*sl 0.67 + 0.031*sl 0.73 + 0.025*sl t r 0.36 0.16 + 0.102*sl 0.15 + 0.106*sl 0.12 + 0.109*sl t f 0.27 0.16 + 0.052*sl 0.19 + 0.042*sl 0.20 + 0.041*sl d7 to y t plh 0.69 0.59 + 0.054*sl 0.60 + 0.050*sl 0.60 + 0.050*sl t phl 0.72 0.63 + 0.045*sl 0.67 + 0.031*sl 0.73 + 0.025*sl t r 0.36 0.16 + 0.102*sl 0.15 + 0.106*sl 0.12 + 0.109*sl t f 0.27 0.17 + 0.050*sl 0.19 + 0.042*sl 0.20 + 0.041*sl s0 to y t plh 1.18 1.07 + 0.054*sl 1.08 + 0.050*sl 1.09 + 0.050*sl t phl 1.09 0.99 + 0.046*sl 1.03 + 0.031*sl 1.10 + 0.025*sl t r 0.36 0.16 + 0.103*sl 0.15 + 0.107*sl 0.12 + 0.109*sl t f 0.27 0.17 + 0.051*sl 0.19 + 0.042*sl 0.20 + 0.041*sl s1 to y t plh 0.77 0.66 + 0.054*sl 0.67 + 0.050*sl 0.67 + 0.050*sl t phl 0.63 0.54 + 0.045*sl 0.58 + 0.031*sl 0.64 + 0.025*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.27 0.17 + 0.051*sl 0.19 + 0.042*sl 0.20 + 0.041*sl s2 to y t plh 0.49 0.39 + 0.054*sl 0.40 + 0.050*sl 0.40 + 0.050*sl t phl 0.39 0.31 + 0.042*sl 0.34 + 0.030*sl 0.39 + 0.025*sl t r 0.35 0.15 + 0.104*sl 0.14 + 0.107*sl 0.12 + 0.109*sl t f 0.24 0.14 + 0.052*sl 0.16 + 0.043*sl 0.18 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 3-538 sec asic ymx8/ymx8d2 fast 8 > 1 non-inverting mux with 1x/2x drive switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 ymx8d2 path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* d0 to y t plh 0.68 0.62 + 0.030*sl 0.63 + 0.026*sl 0.65 + 0.025*sl t phl 0.72 0.67 + 0.029*sl 0.69 + 0.020*sl 0.74 + 0.015*sl t r 0.27 0.17 + 0.051*sl 0.17 + 0.052*sl 0.15 + 0.053*sl t f 0.24 0.18 + 0.030*sl 0.20 + 0.024*sl 0.23 + 0.021*sl d1 to y t plh 0.68 0.62 + 0.030*sl 0.63 + 0.026*sl 0.65 + 0.025*sl t phl 0.72 0.67 + 0.029*sl 0.69 + 0.020*sl 0.74 + 0.015*sl t r 0.27 0.16 + 0.053*sl 0.17 + 0.052*sl 0.15 + 0.053*sl t f 0.24 0.18 + 0.030*sl 0.20 + 0.024*sl 0.23 + 0.021*sl d2 to y t plh 0.69 0.63 + 0.030*sl 0.64 + 0.026*sl 0.65 + 0.025*sl t phl 0.72 0.66 + 0.028*sl 0.69 + 0.020*sl 0.74 + 0.015*sl t r 0.27 0.16 + 0.053*sl 0.17 + 0.052*sl 0.15 + 0.053*sl t f 0.24 0.18 + 0.030*sl 0.20 + 0.024*sl 0.23 + 0.021*sl d3 to y t plh 0.69 0.63 + 0.030*sl 0.64 + 0.026*sl 0.65 + 0.025*sl t phl 0.72 0.66 + 0.028*sl 0.69 + 0.020*sl 0.74 + 0.015*sl t r 0.27 0.16 + 0.052*sl 0.16 + 0.052*sl 0.15 + 0.053*sl t f 0.24 0.18 + 0.030*sl 0.20 + 0.024*sl 0.23 + 0.021*sl d4 to y t plh 0.68 0.62 + 0.030*sl 0.63 + 0.026*sl 0.64 + 0.025*sl t phl 0.73 0.67 + 0.029*sl 0.69 + 0.020*sl 0.74 + 0.015*sl t r 0.27 0.17 + 0.051*sl 0.16 + 0.052*sl 0.15 + 0.053*sl t f 0.24 0.18 + 0.030*sl 0.20 + 0.024*sl 0.23 + 0.021*sl d5 to y t plh 0.68 0.62 + 0.030*sl 0.63 + 0.026*sl 0.64 + 0.025*sl t phl 0.73 0.67 + 0.029*sl 0.69 + 0.020*sl 0.75 + 0.015*sl t r 0.27 0.17 + 0.051*sl 0.16 + 0.052*sl 0.15 + 0.053*sl t f 0.24 0.18 + 0.030*sl 0.20 + 0.024*sl 0.23 + 0.021*sl d6 to y t plh 0.69 0.63 + 0.030*sl 0.64 + 0.026*sl 0.65 + 0.025*sl t phl 0.72 0.67 + 0.029*sl 0.69 + 0.020*sl 0.74 + 0.015*sl t r 0.27 0.16 + 0.052*sl 0.17 + 0.052*sl 0.15 + 0.053*sl t f 0.24 0.18 + 0.030*sl 0.20 + 0.024*sl 0.23 + 0.021*sl d7 to y t plh 0.69 0.62 + 0.030*sl 0.64 + 0.026*sl 0.65 + 0.025*sl t phl 0.73 0.67 + 0.028*sl 0.69 + 0.020*sl 0.74 + 0.015*sl t r 0.27 0.16 + 0.052*sl 0.17 + 0.052*sl 0.15 + 0.053*sl t f 0.24 0.18 + 0.030*sl 0.20 + 0.024*sl 0.23 + 0.021*sl s0 to y t plh 1.17 1.11 + 0.030*sl 1.12 + 0.026*sl 1.13 + 0.025*sl t phl 1.09 1.03 + 0.029*sl 1.05 + 0.020*sl 1.10 + 0.015*sl t r 0.27 0.16 + 0.052*sl 0.16 + 0.052*sl 0.15 + 0.053*sl t f 0.24 0.18 + 0.030*sl 0.20 + 0.024*sl 0.23 + 0.021*sl s1 to y t plh 0.75 0.69 + 0.030*sl 0.71 + 0.026*sl 0.72 + 0.025*sl t phl 0.63 0.58 + 0.028*sl 0.60 + 0.020*sl 0.65 + 0.015*sl t r 0.26 0.16 + 0.053*sl 0.16 + 0.052*sl 0.15 + 0.053*sl t f 0.24 0.18 + 0.030*sl 0.20 + 0.024*sl 0.23 + 0.021*sl s2 to y t plh 0.48 0.42 + 0.030*sl 0.43 + 0.026*sl 0.44 + 0.025*sl t phl 0.39 0.33 + 0.027*sl 0.35 + 0.020*sl 0.40 + 0.015*sl t r 0.26 0.15 + 0.053*sl 0.15 + 0.052*sl 0.14 + 0.053*sl t f 0.22 0.16 + 0.030*sl 0.17 + 0.024*sl 0.21 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
input/output cells 4
contents overview...............................................................................................................................4-1 summary tables ...................................................................................................................4-2 input buffers .........................................................................................................................4-8 output buffers.......................................................................................................................4-23 bi-directional buffers ............................................................................................................4-97 input clock drivers ...............................................................................................................4-99 oscillators .............................................................................................................................4-122 pci buffers ...........................................................................................................................4-129 pcmcia buffers ...................................................................................................................4-136 cardbus i/o buffers..............................................................................................................4-143 voltage detector (under development).................................................................................4-152 power pads...........................................................................................................................4-153
input/output cells overview sec asic 4-1 kg80/KGM80 overview the fourth chapter describes various kinds of input/output cells (5v/3.3v, normal and interface operations) in kg80/KGM80 libraries. the switching characteristics of each cell are attached to its basic cell information. the ac characteristics of bi-directional buffers are not included in this data sheet, however, they can be derived from different combinations of input and output buffers. there are so many possible combinations of input/output cells, therefore, the naming conventions are adopted to help you memorize and use this cell library ef?ciently. you can refer to the naming conventions contained in summary tables section. the summary tables section shows the list of 5v and 3.3v i/o cells separated by the category (input, output, bi-directional, etc.), and the more detailed description tables can be found on the leading part of each category.
summary tables input/output cells kg80/KGM80 4-2 sec asic summary tables input buffers output buffers cell type cell name kg80 KGM80 page cmos level pic/picd/picu o o 4-9 phic/phicd/phicu C o plic/plicd/plicu o C ttl schmitt trigger level pil/pild/pilu o C 4-13 phil/phild/philu C o cmos schmitt trigger level pis/pisd/pisu o o 4-16 phis/phisd/phisu C o plis/plisd/plisu o C ttl level pit/pitd/pitu o C 4-20 phit/phitd/phitu C o p v i a b va none normal operation c cmos level h 5v interface in KGM80 l ttl schmitt trigger level l 3.3v interface in kg80 s cmos schmitt trigger level b t ttl level none no resistor d pull-down resistor u pull-up resistor cell type cell name current drive (ma) page kg80 KGM80 normal poby 1/2/4/8/12/16/20/24 1/2/4/6/8/10/12/16 4-24 pobysh 12/16/20/24 C pobysm 4/8/12/16/20/24 4/6/8/10/12/16 phoby C 1/2/4/8/12/16/20/24 phobysh C 12/16/20/24 phobysm C 4/8/12/16/20/24 ploby 1/2/4/6/8/10/12/16 C plobysm 4/6/8/10/12/16 C
input/output cells summary tables sec asic 4-3 kg80/KGM80 open drain pody 1/2/4/8/12/16/20/24 1/2/4/6/8/10/12/16 4-41 podysh 12/16/20/24 C podysm 4/8/12/16/20/24 4/6/8/10/12/16 phody C 1/2/4/8/12/16/20/24 phodysh C 12/16/20/24 phodysm C 4/8/12/16/20/24 plody 1/2/4/6/8/10/12/16 C plodysm 4/6/8/10/12/16 C tri-state poty 1/2/4/8/12/16/20/24 1/2/4/6/8/10/12/16 4-64 potysh 12/16/20/24 C potysm 4/8/12/16/20/24 4/6/8/10/12/16 photy C 1/2/4/8/12/16/20/24 photysh C 12/16/20/24 photysm C 4/8/12/16/20/24 ploty 1/2/4/6/8/10/12/16 C plotysm 4/6/8/10/12/16 C p v o x y z vy none normal operation 1 1ma drive h 5v interface in KGM80 2 2ma drive l 3.3v interface in kg80 4 4ma drive x 6 6ma drive b normal buffer 8 8ma drive d open drain buffer 10 10ma drive t tri-state buffer 12 12ma drive z 16 16ma drive none no slew-rate control 20 20ma drive sh high slew-rate control 24 24ma drive sm medium slew-rate control cell type cell name current drive (ma) page kg80 KGM80
summary tables input/output cells kg80/KGM80 4-4 sec asic bi-directional buffers cell type cell name kg80 KGM80 page open drain pbadyz/pbaudyz o o 4-98 phbadyz/phbaudyz C o plbadyz/plbaudyz o C tri-state pbatyz/pbadtyz/pbautyz o o phbatyz/phbadtyz/phbautyz C o plbatyz/plbadtyz/plbautyz o C p v b a b x y z va none normal operation c cmos level h 5v interface in KGM80 l ttl schmitt trigger level l 3.3v interface in kg80 s cmos schmitt trigger level b t ttl level none no resistor y d pull-down resistor 1 1ma drive u pull-up resistor 2 2ma drive x 4 4ma drive d open drain buffer 6 6ma drive t tri-state buffer 8 8ma drive z 10 10ma drive none no slew-rate control 12 12ma drive sh high slew-rate control 16 16ma drive sm medium slew-rate control 20 20ma drive 24 24ma drive
input/output cells summary tables sec asic 4-5 kg80/KGM80 input clock drivers oscillators cell type cell name current drive (ma) page kg80 KGM80 cmos level psckdcy 2/4/8/12 2/4/6/8 4-100 psckdcdy 2/4/8/12 2/4/6/8 psckdcuy 2/4/8/12 2/4/6/8 ttl schmitt trigger level psckdly 2/4/8/12 C 4-107 psckdldy 2/4/8/12 C psckdluy 2/4/8/12 C cmos schmitt trigger level psckdsy 2/4/8/12 2/4/6/8 4-111 psckdsdy 2/4/8/12 2/4/6/8 psckdsuy 2/4/8/12 2/4/6/8 ttl level psckdty 2/4/8/12 C 4-118 psckdtdy 2/4/8/12 C psckdtuy 2/4/8/12 C psckd a b y ay c cmos level 2 2ma drive l ttl schmitt trigger level 4 4ma drive s cmos schmitt trigger level 6 6ma drive t ttl level 8 8ma drive b 12 12ma drive none no resistor d pull-down resistor u pull-up resistor cell type cell name page kg80 KGM80 oscillator with enable psoscm(1/2/3/4/5/6) psoscm(1/2/3/4/5) 4-122
summary tables input/output cells kg80/KGM80 4-6 sec asic pci buffers pcmcia buffers cardbus i/o buffers cell type cell name page kg80 KGM80 pci input psipcia/plsipcia psipcia3/phsipcia 4-132 pci output psopcia/plsopcia psopcia3/phsopcia 4-133 universal pci input psipciau psipciau 4-134 universal pci output psopciau psopciau 4-135 cell type cell name page pcmcia input pvic(5/3) 4-139 pvil/pvild/pvilu(5/3) pvit/pvitd/pitu(5/3) pcmcia output pvob4/pvob8/pvob12(5/3) 4-140 pvod4/pvod8/pvod12(5/3) pvot4/pvot8/pvot12(5/3) 4-141 pvot8sm/pvot12sm(5/3) pcmcia bi-directional pvbtt4/pvbtt8/pvbtt12(5/3) 4-142 pvbtdt8sm/pvbct8sm(5/3) cell type cell name page kg80 KGM80 cardbus input plitcbu pitcbu 4-146 cardbus output plotcbu/ plotcckcbu/ plotcvscbu potcbu/ potcckcbu/ potcvscbu 4-147 plodcckcbu podcckcbu 4-148 cardbus bi-directional plbttcbu/ plbtcckcbu/ plbtcvscbu pbttcbu/ pbtcckcbu/ pbtcvscbu 4-149 plbdcckcbu pbdcckcbu 4-150 level shifter plscb plscb 4-151
input/output cells summary tables sec asic 4-7 kg80/KGM80 voltage detector (under development) power pads cell type cell name page voltage detector vdet 4-152 cell type cell name page kg80 KGM80 5v vdd vdd5(i/p/o/ip/oi/op/t) vdd5(p/o/op) 4-153 3.3v vdd vdd3(p/o/op) vdd3(i/p/o/ip/oi/op/t) 5v vss vss5(i/p/o/ip/oi/op/t) vss5(p/o/op) 3.3v vss vss3(p/o/op) vss3(i/p/o/ip/oi/op/t)
kg80/KGM80 4-8 sec asic input buffers cell list cell name function description kg80 pic/picd/picu 5v cmos level input buffers pil/pild/pilu 5v ttl schmitt trigger level input buffers pis/pisd/pisu 5v cmos schmitt trigger level input buffers pit/pitd/pitu 5v ttl level input buffers plic/plicd/plicu 3.3v interface cmos level input buffers plis/plisd/plisu 3.3v interface cmos schmitt trigger level input buffers KGM80 pic/picd/picu 3.3v cmos level input buffers pis/pisd/pisu 3.3v cmos schmitt trigger level input buffers phic/phicd/phicu 5v interface cmos level input buffers phil/phild/philu 5v interface ttl schmitt trigger level input buffers phis/phisd/phisu 5v interface cmos schmitt trigger level input buffers phit/phitd/phitu 5v interface ttl level input buffers
sec asic 4-9 kg80/KGM80 pvic/pvicd/pvicu cmos level input buffers cell availability logic symbol notes: 1. kg80 3.3v interface input buffers (plic/plicd/plicu) are not available to receive input signals from 5v devices. 2. fail-safe input buffers are available to receive signals from 5v devices without reducing reliability. however, if you want to use fail-safe input buffers, please contact to sec asic ?rst. library 5v operation 3.3v operation kg80 pic/picd/picu plic/plicd/plicu KGM80 phic/phicd/phicu pic/picd/picu y po pi pa d y po pi pa d y po pi pa d truth table input load (sl) i/o slot pa d p i y p o 1110 0x01 1011 kg80 pi pic/picd/picu 1.6 plic/plicd/plicu 1.2 KGM80 pi pic/picd/picu 1.9 phic/phicd/phicu 1.4 kg80/KGM80 pvic/pvicd/pvicu 1.0
kg80/KGM80 4-10 sec asic pvic/pvicd/pvicu cmos level input buffers kg80 pic switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.23 0.21 + 0.009*sl 0.22 + 0.008*sl 0.22 + 0.008*sl t phl 0.24 0.21 + 0.011*sl 0.21 + 0.010*sl 0.22 + 0.010*sl t r 0.13 0.10 + 0.014*sl 0.10 + 0.014*sl 0.09 + 0.015*sl t f 0.13 0.10 + 0.016*sl 0.10 + 0.018*sl 0.09 + 0.018*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = kg80 picd switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.24 0.23 + 0.008*sl 0.23 + 0.008*sl 0.23 + 0.008*sl t phl 0.24 0.22 + 0.011*sl 0.22 + 0.011*sl 0.22 + 0.010*sl t r 0.13 0.10 + 0.013*sl 0.10 + 0.015*sl 0.09 + 0.016*sl t f 0.13 0.10 + 0.015*sl 0.10 + 0.018*sl 0.09 + 0.018*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = kg80 picu switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.23 0.21 + 0.010*sl 0.22 + 0.008*sl 0.22 + 0.007*sl t phl 0.24 0.22 + 0.012*sl 0.22 + 0.010*sl 0.22 + 0.010*sl t r 0.13 0.11 + 0.014*sl 0.11 + 0.014*sl 0.10 + 0.015*sl t f 0.13 0.10 + 0.018*sl 0.10 + 0.017*sl 0.09 + 0.018*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = kg80 plic switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.49 0.47 + 0.009*sl 0.48 + 0.007*sl 0.48 + 0.007*sl t phl 0.78 0.76 + 0.010*sl 0.76 + 0.012*sl 0.80 + 0.005*sl t r 0.15 0.13 + 0.011*sl 0.12 + 0.012*sl 0.12 + 0.013*sl t f 0.16 0.13 + 0.012*sl 0.13 + 0.014*sl 0.15 + 0.011*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 4-11 kg80/KGM80 pvic/pvicd/pvicu cmos level input buffers kg80 plicd switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.48 0.47 + 0.008*sl 0.47 + 0.007*sl 0.47 + 0.007*sl t phl 0.79 0.77 + 0.011*sl 0.76 + 0.012*sl 0.81 + 0.006*sl t r 0.15 0.12 + 0.012*sl 0.12 + 0.012*sl 0.12 + 0.013*sl t f 0.17 0.15 + 0.012*sl 0.15 + 0.012*sl 0.16 + 0.010*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = kg80 plicu switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.49 0.48 + 0.008*sl 0.48 + 0.008*sl 0.49 + 0.006*sl t phl 0.78 0.76 + 0.011*sl 0.77 + 0.007*sl 0.74 + 0.011*sl t r 0.15 0.12 + 0.013*sl 0.13 + 0.011*sl 0.11 + 0.014*sl t f 0.17 0.15 + 0.012*sl 0.14 + 0.016*sl 0.19 + 0.009*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = KGM80 pic switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.27 0.25 + 0.011*sl 0.25 + 0.009*sl 0.26 + 0.009*sl t phl 0.28 0.26 + 0.012*sl 0.26 + 0.010*sl 0.27 + 0.010*sl t r 0.17 0.14 + 0.016*sl 0.13 + 0.019*sl 0.13 + 0.019*sl t f 0.16 0.12 + 0.019*sl 0.11 + 0.023*sl 0.19 + 0.015*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = KGM80 picd switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.26 0.24 + 0.007*sl 0.23 + 0.011*sl 0.26 + 0.009*sl t phl 0.29 0.26 + 0.013*sl 0.27 + 0.011*sl 0.27 + 0.010*sl t r 0.18 0.14 + 0.019*sl 0.15 + 0.016*sl 0.11 + 0.020*sl t f 0.17 0.13 + 0.020*sl 0.13 + 0.018*sl 0.11 + 0.019*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 4-12 sec asic pvic/pvicd/pvicu cmos level input buffers KGM80 picu switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.28 0.25 + 0.011*sl 0.26 + 0.009*sl 0.26 + 0.009*sl t phl 0.29 0.27 + 0.009*sl 0.26 + 0.011*sl 0.27 + 0.010*sl t r 0.17 0.14 + 0.016*sl 0.13 + 0.018*sl 0.11 + 0.019*sl t f 0.17 0.12 + 0.022*sl 0.13 + 0.021*sl 0.19 + 0.015*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = KGM80 phic switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.43 0.42 + 0.010*sl 0.42 + 0.009*sl 0.43 + 0.008*sl t phl 0.63 0.63 + 0.003*sl 0.60 + 0.012*sl 0.64 + 0.008*sl t r 0.16 0.11 + 0.022*sl 0.13 + 0.017*sl 0.13 + 0.017*sl t f 0.20 0.17 + 0.012*sl 0.17 + 0.014*sl 0.18 + 0.012*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = KGM80 phicd switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.44 0.43 + 0.005*sl 0.42 + 0.009*sl 0.44 + 0.007*sl t phl 0.64 0.63 + 0.004*sl 0.61 + 0.012*sl 0.64 + 0.009*sl t r 0.15 0.13 + 0.013*sl 0.12 + 0.017*sl 0.12 + 0.017*sl t f 0.20 0.17 + 0.014*sl 0.17 + 0.014*sl 0.17 + 0.014*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = KGM80 phicu switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.44 0.42 + 0.009*sl 0.42 + 0.009*sl 0.43 + 0.008*sl t phl 0.64 0.63 + 0.002*sl 0.61 + 0.013*sl 0.65 + 0.008*sl t r 0.15 0.12 + 0.016*sl 0.11 + 0.019*sl 0.15 + 0.015*sl t f 0.20 0.16 + 0.018*sl 0.18 + 0.013*sl 0.16 + 0.014*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 4-13 kg80/KGM80 pvil/pvild/pvilu ttl schmitt trigger level input buffers cell availability logic symbol library 5v operation 3.3v operation kg80 pil/pild/pilu C KGM80 phil/phild/philu C y po pi pa d y po pi pa d y po pi pa d truth table input load (sl) i/o slot pa d p i y p o 1110 0x01 1011 kg80 pi pil/pild/pilu 1.6 KGM80 pi phil/phild/philu 1.4 kg80/KGM80 pvil/pvild/pvilu 1.0
kg80/KGM80 4-14 sec asic pvil/pvild/pvilu ttl schmitt trigger level input buffers kg80 pil switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.44 0.43 + 0.009*sl 0.43 + 0.008*sl 0.43 + 0.008*sl t phl 1.52 1.49 + 0.014*sl 1.49 + 0.013*sl 1.51 + 0.011*sl t r 0.16 0.14 + 0.014*sl 0.13 + 0.015*sl 0.13 + 0.015*sl t f 0.52 0.49 + 0.013*sl 0.50 + 0.011*sl 0.51 + 0.010*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = kg80 pild switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.46 0.44 + 0.009*sl 0.44 + 0.008*sl 0.44 + 0.008*sl t phl 1.53 1.50 + 0.014*sl 1.51 + 0.013*sl 1.52 + 0.011*sl t r 0.17 0.14 + 0.014*sl 0.14 + 0.015*sl 0.14 + 0.015*sl t f 0.52 0.50 + 0.012*sl 0.50 + 0.012*sl 0.51 + 0.010*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = kg80 pilu switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.45 0.43 + 0.009*sl 0.43 + 0.008*sl 0.44 + 0.008*sl t phl 1.55 1.52 + 0.014*sl 1.53 + 0.013*sl 1.54 + 0.011*sl t r 0.17 0.14 + 0.015*sl 0.14 + 0.014*sl 0.14 + 0.015*sl t f 0.52 0.50 + 0.013*sl 0.50 + 0.012*sl 0.51 + 0.010*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = KGM80 phil switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.53 0.51 + 0.009*sl 0.51 + 0.009*sl 0.51 + 0.008*sl t phl 2.21 2.19 + 0.010*sl 2.19 + 0.010*sl 2.21 + 0.008*sl t r 0.15 0.12 + 0.016*sl 0.12 + 0.017*sl 0.11 + 0.017*sl t f 0.20 0.15 + 0.024*sl 0.19 + 0.012*sl 0.11 + 0.019*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 4-15 kg80/KGM80 pvil/pvild/pvilu ttl schmitt trigger level input buffers KGM80 phild switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.54 0.52 + 0.009*sl 0.52 + 0.008*sl 0.53 + 0.008*sl t phl 2.22 2.20 + 0.013*sl 2.21 + 0.010*sl 2.22 + 0.008*sl t r 0.15 0.12 + 0.017*sl 0.12 + 0.016*sl 0.10 + 0.019*sl t f 0.20 0.16 + 0.020*sl 0.18 + 0.012*sl 0.16 + 0.014*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = KGM80 philu switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.53 0.51 + 0.009*sl 0.51 + 0.008*sl 0.52 + 0.008*sl t phl 2.24 2.22 + 0.013*sl 2.22 + 0.010*sl 2.24 + 0.009*sl t r 0.15 0.12 + 0.017*sl 0.12 + 0.017*sl 0.10 + 0.018*sl t f 0.22 0.19 + 0.016*sl 0.20 + 0.010*sl 0.16 + 0.014*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 4-16 sec asic pvis/pvisd/pvisu cmos schmitt trigger level input buffers cell availability logic symbol notes: 1. kg80 3.3v interface input buffers (plis/plisd/plisu) are not available to receive input signals from 5v devices. 2. fail-safe input buffers are available to receive signals from 5v devices without reducing reliability. however, if you want to use fail-safe input buffers, please contact to sec asic ?rst. library 5v operation 3.3v operation kg80 pis/pisd/pisu plis/plisd/plisu KGM80 phis/phisd/phisu pis/pisd/pisu y po pi pa d y po pi pa d y po pi pa d truth table input load (sl) i/o slot pa d p i y p o 1110 0x01 1011 kg80 pi pis/pisd/pisu 1.6 plis/plisd/plisu 1.2 KGM80 pi pis/pisd/pisu 1.9 phis/phisd/phisu 1.2 kg80/KGM80 pvis/pvisd/pvisu 1.0
sec asic 4-17 kg80/KGM80 pvis/pvisd/pvisu cmos schmitt trigger level input buffers kg80 pis switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.28 0.26 + 0.013*sl 0.26 + 0.011*sl 0.26 + 0.011*sl t phl 0.43 0.40 + 0.015*sl 0.40 + 0.013*sl 0.41 + 0.012*sl t r 0.16 0.12 + 0.023*sl 0.12 + 0.022*sl 0.11 + 0.023*sl t f 0.20 0.17 + 0.018*sl 0.17 + 0.017*sl 0.17 + 0.017*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = kg80 pisd switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.29 0.27 + 0.012*sl 0.27 + 0.012*sl 0.27 + 0.011*sl t phl 0.44 0.41 + 0.015*sl 0.41 + 0.013*sl 0.42 + 0.012*sl t r 0.16 0.12 + 0.020*sl 0.11 + 0.023*sl 0.12 + 0.023*sl t f 0.20 0.17 + 0.018*sl 0.17 + 0.017*sl 0.16 + 0.017*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = kg80 pisu switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.29 0.26 + 0.013*sl 0.27 + 0.012*sl 0.27 + 0.011*sl t phl 0.44 0.40 + 0.015*sl 0.41 + 0.013*sl 0.42 + 0.012*sl t r 0.16 0.12 + 0.023*sl 0.12 + 0.022*sl 0.11 + 0.023*sl t f 0.20 0.17 + 0.018*sl 0.17 + 0.017*sl 0.17 + 0.017*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = kg80 plis switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.75 0.73 + 0.008*sl 0.73 + 0.008*sl 0.74 + 0.006*sl t phl 1.63 1.61 + 0.010*sl 1.61 + 0.011*sl 1.65 + 0.006*sl t r 0.15 0.13 + 0.013*sl 0.13 + 0.011*sl 0.11 + 0.014*sl t f 0.17 0.12 + 0.023*sl 0.15 + 0.013*sl 0.18 + 0.009*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 4-18 sec asic pvis/pvisd/pvisu cmos schmitt trigger level input buffers kg80 plisd switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.77 0.75 + 0.008*sl 0.75 + 0.007*sl 0.76 + 0.007*sl t phl 1.65 1.63 + 0.011*sl 1.63 + 0.011*sl 1.66 + 0.007*sl t r 0.15 0.13 + 0.012*sl 0.13 + 0.011*sl 0.11 + 0.013*sl t f 0.17 0.15 + 0.014*sl 0.15 + 0.010*sl 0.15 + 0.011*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = kg80 plisu switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.76 0.75 + 0.008*sl 0.75 + 0.007*sl 0.75 + 0.007*sl t phl 1.64 1.62 + 0.010*sl 1.62 + 0.012*sl 1.66 + 0.006*sl t r 0.15 0.13 + 0.011*sl 0.13 + 0.012*sl 0.13 + 0.012*sl t f 0.16 0.14 + 0.011*sl 0.13 + 0.013*sl 0.13 + 0.013*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = KGM80 pis switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.51 0.50 + 0.009*sl 0.50 + 0.008*sl 0.51 + 0.007*sl t phl 1.11 1.09 + 0.012*sl 1.09 + 0.009*sl 1.11 + 0.008*sl t r 0.25 0.22 + 0.018*sl 0.24 + 0.008*sl 0.20 + 0.012*sl t f 0.34 0.32 + 0.010*sl 0.32 + 0.010*sl 0.32 + 0.010*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = KGM80 pisd switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.53 0.52 + 0.008*sl 0.52 + 0.008*sl 0.53 + 0.007*sl t phl 1.13 1.11 + 0.010*sl 1.11 + 0.010*sl 1.13 + 0.008*sl t r 0.24 0.20 + 0.017*sl 0.22 + 0.011*sl 0.22 + 0.011*sl t f 0.34 0.32 + 0.012*sl 0.32 + 0.010*sl 0.33 + 0.009*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 4-19 kg80/KGM80 pvis/pvisd/pvisu cmos schmitt trigger level input buffers KGM80 pisu switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.53 0.51 + 0.009*sl 0.52 + 0.008*sl 0.53 + 0.007*sl t phl 1.12 1.10 + 0.011*sl 1.10 + 0.009*sl 1.12 + 0.008*sl t r 0.23 0.22 + 0.008*sl 0.21 + 0.011*sl 0.21 + 0.011*sl t f 0.36 0.34 + 0.010*sl 0.34 + 0.008*sl 0.33 + 0.010*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = KGM80 phis switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.55 0.53 + 0.009*sl 0.53 + 0.009*sl 0.54 + 0.008*sl t phl 1.07 1.06 + 0.005*sl 1.04 + 0.011*sl 1.07 + 0.009*sl t r 0.16 0.11 + 0.022*sl 0.13 + 0.016*sl 0.13 + 0.016*sl t f 0.19 0.17 + 0.014*sl 0.17 + 0.014*sl 0.17 + 0.014*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = KGM80 phisd switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.55 0.53 + 0.009*sl 0.53 + 0.009*sl 0.53 + 0.008*sl t phl 1.08 1.06 + 0.009*sl 1.06 + 0.011*sl 1.08 + 0.009*sl t r 0.15 0.12 + 0.014*sl 0.12 + 0.017*sl 0.09 + 0.019*sl t f 0.19 0.17 + 0.015*sl 0.17 + 0.013*sl 0.16 + 0.014*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = KGM80 phisu switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.56 0.54 + 0.009*sl 0.54 + 0.009*sl 0.54 + 0.008*sl t phl 1.08 1.06 + 0.009*sl 1.05 + 0.011*sl 1.08 + 0.009*sl t r 0.16 0.11 + 0.023*sl 0.13 + 0.015*sl 0.09 + 0.019*sl t f 0.20 0.17 + 0.013*sl 0.17 + 0.013*sl 0.16 + 0.014*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 4-20 sec asic pvit/pvitd/pvitu ttl level input buffers cell availability logic symbol library 5v operation 3.3v operation kg80 pit/pitd/pitu C KGM80 phit/phitd/phitu C y po pi pa d y po pi pa d y po pi pa d truth table input load (sl) i/o slot pa d p i y p o 1110 0x01 1011 kg80 pi pit/pitd/pitu 1.6 KGM80 pi phit/phitd/phitu 1.4 kg80/KGM80 pvit/pvitd/pvitu 1.0
sec asic 4-21 kg80/KGM80 pvit/pvitd/pvitu ttl level input buffers kg80 pit switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.25 0.23 + 0.011*sl 0.23 + 0.011*sl 0.23 + 0.011*sl t phl 0.32 0.30 + 0.011*sl 0.31 + 0.009*sl 0.32 + 0.008*sl t r 0.15 0.11 + 0.023*sl 0.11 + 0.023*sl 0.10 + 0.024*sl t f 0.17 0.15 + 0.010*sl 0.15 + 0.010*sl 0.15 + 0.009*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = kg80 pitd switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.26 0.24 + 0.011*sl 0.24 + 0.011*sl 0.24 + 0.011*sl t phl 0.34 0.31 + 0.011*sl 0.32 + 0.009*sl 0.33 + 0.008*sl t r 0.15 0.11 + 0.023*sl 0.11 + 0.023*sl 0.10 + 0.024*sl t f 0.17 0.15 + 0.010*sl 0.15 + 0.010*sl 0.15 + 0.009*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = kg80 pitu switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.25 0.23 + 0.011*sl 0.23 + 0.011*sl 0.23 + 0.011*sl t phl 0.33 0.31 + 0.011*sl 0.31 + 0.009*sl 0.32 + 0.007*sl t r 0.15 0.11 + 0.024*sl 0.11 + 0.023*sl 0.10 + 0.024*sl t f 0.17 0.15 + 0.009*sl 0.15 + 0.010*sl 0.15 + 0.009*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = KGM80 phit switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.25 0.23 + 0.009*sl 0.23 + 0.009*sl 0.23 + 0.008*sl t phl 0.93 0.91 + 0.007*sl 0.90 + 0.011*sl 0.93 + 0.008*sl t r 0.17 0.16 + 0.004*sl 0.12 + 0.016*sl 0.11 + 0.017*sl t f 0.20 0.17 + 0.012*sl 0.17 + 0.014*sl 0.15 + 0.016*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 4-22 sec asic pvit/pvitd/pvitu ttl level input buffers KGM80 phitd switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.27 0.26 + 0.009*sl 0.26 + 0.009*sl 0.26 + 0.008*sl t phl 0.93 0.92 + 0.006*sl 0.91 + 0.011*sl 0.94 + 0.009*sl t r 0.16 0.13 + 0.014*sl 0.12 + 0.016*sl 0.11 + 0.017*sl t f 0.20 0.17 + 0.017*sl 0.17 + 0.014*sl 0.17 + 0.014*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = = KGM80 phitu switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pad to y t plh 0.25 0.23 + 0.009*sl 0.23 + 0.009*sl 0.23 + 0.008*sl t phl 0.93 0.92 + 0.008*sl 0.91 + 0.011*sl 0.94 + 0.008*sl t r 0.17 0.16 + 0.004*sl 0.12 + 0.016*sl 0.11 + 0.018*sl t f 0.20 0.17 + 0.013*sl 0.17 + 0.013*sl 0.15 + 0.015*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
sec asic 4-23 kg80/KGM80 output buffers cell list cell name function description kg80 pob(1/2/4/8/12/16/20/24) 5v normal output buffers pob(12/16/20/24)sh 5v normal output buffers with high slew-rate pob(4/8/12/16/20/24)sm 5v normal output buffers with medium slew-rate pod(1/2/4/8/12/16/20/24) 5v open drain output buffers pod(12/16/20/24)sh 5v open drain output buffers with high slew-rate pod(4/8/12/16/20/24)sm 5v open drain output buffers with medium slew-rate pot(1/2/4/8/12/16/20/24) 5v tri-state output buffers pot(12/16/20/24)sh 5v tri-state output buffers with high slew-rate pot(4/8/12/16/20/24)sm 5v tri-state output buffers with medium slew-rate plob(1/2/4/6/8/10/12/16) 3.3v interface normal output buffers plob(4/6/8/10/12/16)sm 3.3v interface normal output buffers with medium slew-rate plod(1/2/4/6/8/10/12/16) 3.3v interface open drain output buffers plod(4/6/8/10/12/16)sm 3.3v interface open drain output buffers with medium slew-rate plot(1/2/4/6/8/10/12/16) 3.3v interface tri-state output buffers plot(4/6/8/10/12/16)sm 3.3v interface tri-state output buffers with medium slew-rate KGM80 pob(1/2/4/6/8/10/12/16) 3.3v normal output buffers pob(4/6/8/10/12/16)sm 3.3v normal output buffers with medium slew-rate control pod(1/2/4/6/8/10/12/16) 3.3v open drain output buffers pod(4/6/8/10/12/16)sm 3.3v open drain output buffers with medium slew-rate control pot(1/2/4/6/8/10/12/16) 3.3v tri-state output buffers pot(4/6/8/10/12/16)sm 3.3v tri-state output buffers with medium slew-rate control phob(1/2/4/8/12/16/20/24) 5v interface normal output buffers phob(12/16/20/24)sh 5v interface normal output buffers with high slew-rate control phob(4/8/12/16/20/24)sm 5v interface normal output buffers with medium slew-rate control phod(1/2/4/8/12/16/20/24) 5v interface open drain output buffers phod(12/16/20/24)sh 5v interface open drain output buffers with high slew-rate control phod(4/8/12/16/20/24)sm 5v interface open drain output buffers with medium slew-rate control phot(1/2/4/8/12/16/20/24) 5v interface tri-state output buffers phot(12/16/20/24)sh 5v interface tri-state output buffers with high slew-rate control phot(4/8/12/16/20/24)sm 5v interface tri-state output buffers with medium slew-rate control
kg80/KGM80 4-24 sec asic pvobyz normal output buffers cell availability logic symbol truth table i/o slot library 5v operation 3.3v operation kg80 pob(1/2/4/8/12/16/20/24) pob(12/16/20/24)sh pob(4/8/12/16/20/24)sm plob(1/2/4/6/8/10/12/16) plob(4/6/8/10/12/16)sm KGM80 phob(1/2/4/8/12/16/20/24) phob(12/16/20/24)sh phob(4/8/12/16/20/24)sm pob(1/2/4/6/8/10/12/16) pob(4/6/8/10/12/16)sm apad 00 11 kg80/KGM80 pvobyz 1.0 pa d a input load (sl) kg80 a pob(1/2/4/8/12/16) 5.5 pob20 9.5 pob24 10.2 pob12sh 20.6 pob16sh 20.0 pob(20/24)sh 10.44 pob4sm 21.3 pob(8/12)sm 20.6 pob16sm 20.0 pob(20/24)sm 11.7 plob(1/2/4/6/8/10/12/16) 2.3 plob(4/6/8/10/12/16)sm 2.3 KGM80 a pob1 6.5 pob(2/12/16) 6.1 pob(4/6) 4.8 pob8 4.6 pob10 5.2 pob(4/6/8/10/12)sm 13.3 pob16sm 13.4 phob(1/2/4/8/12/16/20/24) 2.8 phob(12/16/20/24)sh 2.8 phob(4/8/12/16/20/24)sm 2.8
sec asic 4-25 kg80/KGM80 pvobyz normal output buffers kg80 pob1 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 14.98 0.36 + 0.292*cl 0.37 + 0.292*cl 0.37 + 0.292*cl t phl 12.03 0.39 + 0.233*cl 0.39 + 0.233*cl 0.39 + 0.233*cl t r 33.59 0.59 + 0.660*cl 0.60 + 0.660*cl 0.59 + 0.660*cl t f 24.65 0.40 + 0.485*cl 0.40 + 0.485*cl 0.40 + 0.485*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pob2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 7.60 0.30 + 0.146*cl 0.29 + 0.146*cl 0.30 + 0.146*cl t phl 6.13 0.31 + 0.116*cl 0.31 + 0.116*cl 0.31 + 0.116*cl t r 16.81 0.31 + 0.330*cl 0.31 + 0.330*cl 0.31 + 0.330*cl t f 12.34 0.21 + 0.243*cl 0.21 + 0.242*cl 0.21 + 0.243*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pob4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 4.98 0.29 + 0.094*cl 0.29 + 0.094*cl 0.29 + 0.094*cl t phl 4.02 0.31 + 0.074*cl 0.30 + 0.074*cl 0.31 + 0.074*cl t r 10.81 0.21 + 0.212*cl 0.21 + 0.212*cl 0.21 + 0.212*cl t f 7.88 0.14 + 0.155*cl 0.15 + 0.155*cl 0.14 + 0.155*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pob8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.70 0.36 + 0.047*cl 0.36 + 0.047*cl 0.36 + 0.047*cl t phl 2.22 0.36 + 0.037*cl 0.36 + 0.037*cl 0.36 + 0.037*cl t r 5.43 0.13 + 0.106*cl 0.13 + 0.106*cl 0.13 + 0.106*cl t f 3.96 0.10 + 0.077*cl 0.09 + 0.077*cl 0.09 + 0.077*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-26 sec asic pvobyz normal output buffers kg80 pob12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.14 0.42 + 0.034*cl 0.42 + 0.034*cl 0.41 + 0.035*cl t phl 1.78 0.42 + 0.027*cl 0.42 + 0.027*cl 0.41 + 0.027*cl t r 4.02 0.12 + 0.078*cl 0.12 + 0.078*cl 0.11 + 0.078*cl t f 2.93 0.11 + 0.056*cl 0.10 + 0.057*cl 0.09 + 0.057*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pob16 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.77 0.52 + 0.025*cl 0.52 + 0.025*cl 0.51 + 0.025*cl t phl 1.49 0.50 + 0.020*cl 0.50 + 0.020*cl 0.50 + 0.020*cl t r 2.97 0.13 + 0.057*cl 0.12 + 0.057*cl 0.12 + 0.057*cl t f 2.19 0.14 + 0.041*cl 0.13 + 0.041*cl 0.12 + 0.041*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pob20 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.36 0.37 + 0.020*cl 0.37 + 0.020*cl 0.36 + 0.020*cl t phl 1.24 0.45 + 0.016*cl 0.45 + 0.016*cl 0.45 + 0.016*cl t r 2.33 0.10 + 0.045*cl 0.08 + 0.045*cl 0.09 + 0.045*cl t f 1.74 0.13 + 0.032*cl 0.12 + 0.032*cl 0.11 + 0.032*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pob24 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.28 0.41 + 0.017*cl 0.41 + 0.017*cl 0.40 + 0.017*cl t phl 1.17 0.48 + 0.014*cl 0.48 + 0.014*cl 0.48 + 0.014*cl t r 2.07 0.10 + 0.039*cl 0.09 + 0.039*cl 0.09 + 0.039*cl t f 1.56 0.15 + 0.028*cl 0.14 + 0.028*cl 0.13 + 0.028*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-27 kg80/KGM80 pvobyz normal output buffers kg80 pob12sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.78 1.00 + 0.036*cl 1.02 + 0.035*cl 1.03 + 0.035*cl t phl 3.24 1.65 + 0.032*cl 1.76 + 0.030*cl 1.81 + 0.030*cl t r 4.33 0.48 + 0.077*cl 0.44 + 0.078*cl 0.41 + 0.078*cl t f 3.73 0.96 + 0.055*cl 0.97 + 0.055*cl 0.97 + 0.055*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pob16sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.57 1.22 + 0.027*cl 1.28 + 0.026*cl 1.31 + 0.026*cl t phl 2.95 1.70 + 0.025*cl 1.82 + 0.024*cl 1.87 + 0.023*cl t r 3.42 0.69 + 0.055*cl 0.66 + 0.055*cl 0.65 + 0.055*cl t f 2.99 0.95 + 0.041*cl 1.01 + 0.040*cl 1.02 + 0.040*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pob20sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.03 0.98 + 0.021*cl 1.03 + 0.020*cl 1.04 + 0.020*cl t phl 2.09 1.22 + 0.017*cl 1.26 + 0.017*cl 1.28 + 0.017*cl t r 2.70 0.56 + 0.043*cl 0.53 + 0.043*cl 0.52 + 0.043*cl t f 2.22 0.69 + 0.031*cl 0.68 + 0.031*cl 0.67 + 0.031*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pob24sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.03 1.06 + 0.019*cl 1.12 + 0.019*cl 1.15 + 0.018*cl t phl 2.15 1.36 + 0.016*cl 1.40 + 0.015*cl 1.42 + 0.015*cl t r 2.52 0.63 + 0.038*cl 0.63 + 0.038*cl 0.61 + 0.038*cl t f 2.14 0.79 + 0.027*cl 0.79 + 0.027*cl 0.78 + 0.027*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-28 sec asic pvobyz normal output buffers kg80 pob4sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.22 0.53 + 0.094*cl 0.53 + 0.094*cl 0.53 + 0.094*cl t phl 4.76 1.03 + 0.074*cl 1.04 + 0.074*cl 1.05 + 0.074*cl t r 10.83 0.24 + 0.212*cl 0.23 + 0.212*cl 0.24 + 0.212*cl t f 8.05 0.42 + 0.153*cl 0.37 + 0.153*cl 0.35 + 0.154*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pob8sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.16 0.81 + 0.047*cl 0.82 + 0.047*cl 0.82 + 0.047*cl t phl 3.37 1.41 + 0.039*cl 1.48 + 0.038*cl 1.52 + 0.038*cl t r 5.57 0.34 + 0.105*cl 0.29 + 0.105*cl 0.28 + 0.105*cl t f 4.46 0.74 + 0.074*cl 0.72 + 0.075*cl 0.69 + 0.075*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pob12sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.59 0.85 + 0.035*cl 0.87 + 0.035*cl 0.86 + 0.035*cl t phl 2.88 1.34 + 0.031*cl 1.44 + 0.029*cl 1.48 + 0.029*cl t r 4.21 0.40 + 0.076*cl 0.36 + 0.077*cl 0.34 + 0.077*cl t f 3.54 0.80 + 0.055*cl 0.82 + 0.055*cl 0.82 + 0.055*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pob16sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.27 0.96 + 0.026*cl 1.00 + 0.026*cl 1.01 + 0.026*cl t phl 2.46 1.28 + 0.024*cl 1.36 + 0.022*cl 1.41 + 0.022*cl t r 3.27 0.52 + 0.055*cl 0.49 + 0.055*cl 0.48 + 0.056*cl t f 2.77 0.73 + 0.041*cl 0.77 + 0.040*cl 0.78 + 0.040*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-29 kg80/KGM80 pvobyz normal output buffers kg80 pob20sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.70 0.69 + 0.020*cl 0.70 + 0.020*cl 0.70 + 0.020*cl t phl 1.72 0.83 + 0.018*cl 0.88 + 0.017*cl 0.92 + 0.017*cl t r 2.52 0.35 + 0.043*cl 0.33 + 0.044*cl 0.31 + 0.044*cl t f 2.10 0.54 + 0.031*cl 0.55 + 0.031*cl 0.55 + 0.031*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pob24sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.68 0.77 + 0.018*cl 0.79 + 0.018*cl 0.81 + 0.018*cl t phl 1.74 0.91 + 0.017*cl 0.98 + 0.016*cl 1.02 + 0.015*cl t r 2.31 0.42 + 0.038*cl 0.40 + 0.038*cl 0.39 + 0.038*cl t f 2.01 0.62 + 0.028*cl 0.63 + 0.028*cl 0.64 + 0.027*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plob1 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 21.37 0.92 + 0.409*cl 0.93 + 0.409*cl 0.92 + 0.409*cl t phl 13.83 0.63 + 0.264*cl 0.63 + 0.264*cl 0.63 + 0.264*cl t r 47.48 0.91 + 0.931*cl 0.91 + 0.931*cl 0.91 + 0.931*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plob2 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 10.45 0.80 + 0.193*cl 0.80 + 0.193*cl 0.80 + 0.193*cl t phl 6.71 0.54 + 0.124*cl 0.54 + 0.123*cl 0.53 + 0.124*cl t r 22.42 0.45 + 0.439*cl 0.45 + 0.439*cl 0.45 + 0.439*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-30 sec asic pvobyz normal output buffers kg80 plob4 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.52 0.70 + 0.096*cl 0.69 + 0.097*cl 0.70 + 0.096*cl t phl 3.66 0.58 + 0.062*cl 0.58 + 0.062*cl 0.58 + 0.062*cl t r 11.24 0.25 + 0.220*cl 0.25 + 0.220*cl 0.25 + 0.220*cl t f 6.81 0.16 + 0.133*cl 0.15 + 0.133*cl 0.16 + 0.133*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plob6 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.98 0.76 + 0.064*cl 0.76 + 0.064*cl 0.76 + 0.064*cl t phl 2.73 0.69 + 0.041*cl 0.67 + 0.041*cl 0.67 + 0.041*cl t r 7.52 0.20 + 0.146*cl 0.19 + 0.147*cl 0.20 + 0.146*cl t f 4.58 0.17 + 0.088*cl 0.14 + 0.089*cl 0.13 + 0.089*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plob8 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.24 0.84 + 0.048*cl 0.83 + 0.048*cl 0.83 + 0.048*cl t phl 2.33 0.81 + 0.030*cl 0.81 + 0.030*cl 0.79 + 0.031*cl t r 5.66 0.18 + 0.110*cl 0.17 + 0.110*cl 0.17 + 0.110*cl t f 3.51 0.24 + 0.065*cl 0.22 + 0.066*cl 0.17 + 0.066*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plob10 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.90 0.98 + 0.038*cl 0.97 + 0.039*cl 0.97 + 0.039*cl t phl 2.06 0.83 + 0.025*cl 0.83 + 0.025*cl 0.83 + 0.025*cl t r 4.56 0.18 + 0.088*cl 0.18 + 0.088*cl 0.16 + 0.088*cl t f 2.83 0.21 + 0.052*cl 0.21 + 0.052*cl 0.17 + 0.053*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-31 kg80/KGM80 pvobyz normal output buffers kg80 plob12 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.72 1.11 + 0.032*cl 1.11 + 0.032*cl 1.11 + 0.032*cl t phl 1.94 0.90 + 0.021*cl 0.92 + 0.021*cl 0.92 + 0.021*cl t r 3.84 0.20 + 0.073*cl 0.18 + 0.073*cl 0.18 + 0.073*cl t f 2.43 0.27 + 0.043*cl 0.24 + 0.044*cl 0.24 + 0.044*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plob16 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.49 1.28 + 0.024*cl 1.26 + 0.024*cl 1.27 + 0.024*cl t phl 1.86 1.04 + 0.016*cl 1.07 + 0.016*cl 1.08 + 0.016*cl t r 3.00 0.25 + 0.055*cl 0.23 + 0.055*cl 0.24 + 0.055*cl t f 1.98 0.36 + 0.033*cl 0.38 + 0.032*cl 0.32 + 0.033*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plob4sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 6.25 1.29 + 0.099*cl 1.28 + 0.099*cl 1.29 + 0.099*cl t phl 4.16 0.97 + 0.064*cl 0.97 + 0.064*cl 0.98 + 0.064*cl t r 11.58 0.28 + 0.226*cl 0.27 + 0.226*cl 0.28 + 0.226*cl t f 7.10 0.26 + 0.137*cl 0.23 + 0.137*cl 0.22 + 0.137*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plob6sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 4.76 1.48 + 0.066*cl 1.48 + 0.066*cl 1.48 + 0.066*cl t phl 3.43 1.31 + 0.042*cl 1.32 + 0.042*cl 1.32 + 0.042*cl t r 7.71 0.27 + 0.149*cl 0.24 + 0.149*cl 0.25 + 0.149*cl t f 4.88 0.46 + 0.088*cl 0.41 + 0.089*cl 0.37 + 0.089*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-32 sec asic pvobyz normal output buffers kg80 plob8sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 4.11 1.66 + 0.049*cl 1.66 + 0.049*cl 1.67 + 0.049*cl t phl 3.21 1.58 + 0.033*cl 1.63 + 0.032*cl 1.65 + 0.032*cl t r 5.86 0.35 + 0.110*cl 0.30 + 0.111*cl 0.29 + 0.111*cl t f 3.91 0.69 + 0.065*cl 0.65 + 0.065*cl 0.60 + 0.066*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plob10sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.60 1.67 + 0.039*cl 1.67 + 0.039*cl 1.67 + 0.039*cl t phl 2.85 1.50 + 0.027*cl 1.57 + 0.026*cl 1.61 + 0.026*cl t r 4.72 0.42 + 0.086*cl 0.36 + 0.087*cl 0.34 + 0.087*cl t f 3.34 0.85 + 0.050*cl 0.78 + 0.051*cl 0.80 + 0.050*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plob12sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.46 1.83 + 0.032*cl 1.85 + 0.032*cl 1.85 + 0.032*cl t phl 2.89 1.66 + 0.025*cl 1.77 + 0.023*cl 1.83 + 0.022*cl t r 4.07 0.54 + 0.071*cl 0.46 + 0.072*cl 0.46 + 0.072*cl t f 3.09 1.01 + 0.042*cl 1.04 + 0.041*cl 1.00 + 0.042*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plob16sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.40 2.11 + 0.026*cl 2.17 + 0.025*cl 2.18 + 0.025*cl t phl 3.07 1.95 + 0.022*cl 2.09 + 0.020*cl 2.17 + 0.020*cl t r 3.39 0.75 + 0.053*cl 0.68 + 0.054*cl 0.66 + 0.054*cl t f 2.88 1.24 + 0.033*cl 1.35 + 0.031*cl 1.28 + 0.032*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-33 kg80/KGM80 pvobyz normal output buffers KGM80 pob1 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 20.96 0.52 + 0.409*cl 0.52 + 0.409*cl 0.52 + 0.409*cl t phl 13.70 0.50 + 0.264*cl 0.50 + 0.264*cl 0.50 + 0.264*cl t r 47.48 0.91 + 0.931*cl 0.91 + 0.931*cl 0.91 + 0.931*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pob2 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 10.05 0.40 + 0.193*cl 0.40 + 0.193*cl 0.40 + 0.193*cl t phl 6.58 0.41 + 0.124*cl 0.41 + 0.124*cl 0.41 + 0.124*cl t r 22.42 0.45 + 0.439*cl 0.45 + 0.439*cl 0.45 + 0.439*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pob4 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.18 0.36 + 0.096*cl 0.36 + 0.096*cl 0.36 + 0.096*cl t phl 3.54 0.46 + 0.062*cl 0.46 + 0.062*cl 0.45 + 0.062*cl t r 11.24 0.25 + 0.220*cl 0.25 + 0.220*cl 0.26 + 0.220*cl t f 6.81 0.16 + 0.133*cl 0.15 + 0.133*cl 0.15 + 0.133*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pob6 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.63 0.41 + 0.064*cl 0.41 + 0.064*cl 0.41 + 0.064*cl t phl 2.60 0.56 + 0.041*cl 0.55 + 0.041*cl 0.55 + 0.041*cl t r 7.52 0.20 + 0.146*cl 0.19 + 0.147*cl 0.20 + 0.146*cl t f 4.58 0.16 + 0.088*cl 0.15 + 0.089*cl 0.13 + 0.089*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-34 sec asic pvobyz normal output buffers KGM80 pob8 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.89 0.48 + 0.048*cl 0.48 + 0.048*cl 0.48 + 0.048*cl t phl 2.20 0.69 + 0.030*cl 0.68 + 0.030*cl 0.66 + 0.031*cl t r 5.67 0.18 + 0.110*cl 0.16 + 0.110*cl 0.17 + 0.110*cl t f 3.51 0.24 + 0.065*cl 0.20 + 0.066*cl 0.19 + 0.066*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pob10 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.50 0.58 + 0.038*cl 0.57 + 0.039*cl 0.57 + 0.039*cl t phl 1.94 0.71 + 0.025*cl 0.71 + 0.025*cl 0.71 + 0.025*cl t r 4.56 0.18 + 0.088*cl 0.17 + 0.088*cl 0.17 + 0.088*cl t f 2.84 0.22 + 0.052*cl 0.21 + 0.052*cl 0.18 + 0.053*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pob12 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.27 0.67 + 0.032*cl 0.67 + 0.032*cl 0.66 + 0.032*cl t phl 1.82 0.78 + 0.021*cl 0.78 + 0.021*cl 0.79 + 0.021*cl t r 3.84 0.20 + 0.073*cl 0.19 + 0.073*cl 0.17 + 0.073*cl t f 2.43 0.28 + 0.043*cl 0.25 + 0.043*cl 0.24 + 0.044*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pob16 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.04 0.83 + 0.024*cl 0.83 + 0.024*cl 0.82 + 0.024*cl t phl 1.73 0.92 + 0.016*cl 0.94 + 0.016*cl 0.95 + 0.016*cl t r 3.00 0.26 + 0.055*cl 0.23 + 0.055*cl 0.23 + 0.055*cl t f 1.99 0.37 + 0.032*cl 0.37 + 0.032*cl 0.34 + 0.033*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-35 kg80/KGM80 pvobyz normal output buffers KGM80 pob4sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.50 0.54 + 0.099*cl 0.54 + 0.099*cl 0.54 + 0.099*cl t phl 3.98 0.79 + 0.064*cl 0.78 + 0.064*cl 0.79 + 0.064*cl t r 11.58 0.28 + 0.226*cl 0.27 + 0.226*cl 0.28 + 0.226*cl t f 7.10 0.26 + 0.137*cl 0.24 + 0.137*cl 0.22 + 0.137*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pob6sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.98 0.72 + 0.065*cl 0.69 + 0.066*cl 0.70 + 0.066*cl t phl 3.24 1.12 + 0.042*cl 1.14 + 0.042*cl 1.14 + 0.042*cl t r 7.71 0.26 + 0.149*cl 0.26 + 0.149*cl 0.24 + 0.149*cl t f 4.88 0.46 + 0.088*cl 0.41 + 0.089*cl 0.38 + 0.089*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pob8sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.32 0.87 + 0.049*cl 0.87 + 0.049*cl 0.87 + 0.049*cl t phl 3.02 1.39 + 0.033*cl 1.43 + 0.032*cl 1.46 + 0.032*cl t r 5.85 0.32 + 0.110*cl 0.29 + 0.111*cl 0.27 + 0.111*cl t f 3.91 0.69 + 0.064*cl 0.62 + 0.065*cl 0.60 + 0.066*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pob10sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.82 0.88 + 0.039*cl 0.89 + 0.039*cl 0.88 + 0.039*cl t phl 2.66 1.31 + 0.027*cl 1.38 + 0.026*cl 1.43 + 0.026*cl t r 4.70 0.38 + 0.086*cl 0.33 + 0.087*cl 0.32 + 0.087*cl t f 3.34 0.85 + 0.050*cl 0.79 + 0.051*cl 0.80 + 0.050*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-36 sec asic pvobyz normal output buffers KGM80 pob12sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.66 1.04 + 0.032*cl 1.06 + 0.032*cl 1.06 + 0.032*cl t phl 2.70 1.47 + 0.025*cl 1.58 + 0.023*cl 1.63 + 0.022*cl t r 4.05 0.50 + 0.071*cl 0.45 + 0.072*cl 0.42 + 0.072*cl t f 3.09 1.03 + 0.041*cl 1.02 + 0.041*cl 1.00 + 0.042*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pob16sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.59 1.31 + 0.026*cl 1.35 + 0.025*cl 1.37 + 0.025*cl t phl 2.87 1.76 + 0.022*cl 1.89 + 0.020*cl 1.98 + 0.020*cl t r 3.36 0.70 + 0.053*cl 0.66 + 0.054*cl 0.66 + 0.054*cl t f 2.88 1.25 + 0.033*cl 1.30 + 0.032*cl 1.31 + 0.032*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phob1 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 15.36 0.75 + 0.292*cl 0.75 + 0.292*cl 0.75 + 0.292*cl t phl 12.37 0.73 + 0.233*cl 0.61 + 0.234*cl 0.83 + 0.232*cl t r 33.59 0.59 + 0.660*cl 0.59 + 0.660*cl 0.59 + 0.660*cl t f 24.65 0.40 + 0.485*cl 0.40 + 0.485*cl 0.40 + 0.485*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phob2 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 7.99 0.68 + 0.146*cl 0.68 + 0.146*cl 0.68 + 0.146*cl t phl 6.46 0.61 + 0.117*cl 0.65 + 0.116*cl 0.75 + 0.115*cl t r 16.81 0.31 + 0.330*cl 0.31 + 0.330*cl 0.31 + 0.330*cl t f 12.34 0.21 + 0.243*cl 0.21 + 0.243*cl 0.21 + 0.243*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-37 kg80/KGM80 pvobyz normal output buffers KGM80 phob4 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.37 0.68 + 0.094*cl 0.68 + 0.094*cl 0.68 + 0.094*cl t phl 4.35 0.64 + 0.074*cl 0.64 + 0.074*cl 0.56 + 0.075*cl t r 10.81 0.21 + 0.212*cl 0.22 + 0.212*cl 0.21 + 0.212*cl t f 7.88 0.14 + 0.155*cl 0.14 + 0.155*cl 0.15 + 0.155*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phob8 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.09 0.75 + 0.047*cl 0.74 + 0.047*cl 0.75 + 0.047*cl t phl 2.56 0.70 + 0.037*cl 0.70 + 0.037*cl 0.76 + 0.036*cl t r 5.43 0.13 + 0.106*cl 0.12 + 0.106*cl 0.13 + 0.106*cl t f 3.96 0.09 + 0.077*cl 0.10 + 0.077*cl 0.10 + 0.077*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phob12 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.53 0.81 + 0.034*cl 0.81 + 0.034*cl 0.81 + 0.035*cl t phl 2.11 0.73 + 0.028*cl 0.76 + 0.027*cl 0.81 + 0.027*cl t r 4.02 0.12 + 0.078*cl 0.12 + 0.078*cl 0.11 + 0.078*cl t f 2.93 0.11 + 0.056*cl 0.12 + 0.056*cl 0.08 + 0.057*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phob16 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.16 0.91 + 0.025*cl 0.91 + 0.025*cl 0.91 + 0.025*cl t phl 1.83 0.83 + 0.020*cl 0.77 + 0.021*cl 0.88 + 0.019*cl t r 2.97 0.14 + 0.057*cl 0.12 + 0.057*cl 0.11 + 0.057*cl t f 2.20 0.15 + 0.041*cl 0.14 + 0.041*cl 0.14 + 0.041*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-38 sec asic pvobyz normal output buffers KGM80 phob20 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.90 0.91 + 0.020*cl 0.90 + 0.020*cl 0.91 + 0.020*cl t phl 1.65 0.87 + 0.016*cl 0.87 + 0.016*cl 0.86 + 0.016*cl t r 2.34 0.11 + 0.045*cl 0.08 + 0.045*cl 0.10 + 0.045*cl t f 1.75 0.15 + 0.032*cl 0.10 + 0.033*cl 0.13 + 0.032*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phob24 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.85 0.99 + 0.017*cl 0.98 + 0.017*cl 0.98 + 0.017*cl t phl 1.60 0.91 + 0.014*cl 0.92 + 0.014*cl 0.91 + 0.014*cl t r 2.08 0.12 + 0.039*cl 0.11 + 0.039*cl 0.08 + 0.040*cl t f 1.57 0.17 + 0.028*cl 0.13 + 0.028*cl 0.13 + 0.028*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phob12sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.76 1.98 + 0.036*cl 2.00 + 0.035*cl 2.01 + 0.035*cl t phl 3.90 2.31 + 0.032*cl 2.42 + 0.030*cl 2.47 + 0.030*cl t r 4.37 0.54 + 0.077*cl 0.48 + 0.077*cl 0.46 + 0.078*cl t f 3.74 0.96 + 0.056*cl 0.99 + 0.055*cl 0.98 + 0.055*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phob16sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.54 2.19 + 0.027*cl 2.25 + 0.026*cl 2.28 + 0.026*cl t phl 3.60 2.35 + 0.025*cl 2.46 + 0.024*cl 2.52 + 0.023*cl t r 3.47 0.76 + 0.054*cl 0.73 + 0.055*cl 0.69 + 0.055*cl t f 3.00 0.96 + 0.041*cl 1.00 + 0.040*cl 1.04 + 0.040*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-39 kg80/KGM80 pvobyz normal output buffers KGM80 phob20sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.62 1.56 + 0.021*cl 1.61 + 0.020*cl 1.63 + 0.020*cl t phl 2.54 1.67 + 0.017*cl 1.71 + 0.017*cl 1.73 + 0.017*cl t r 2.73 0.60 + 0.043*cl 0.54 + 0.043*cl 0.56 + 0.043*cl t f 2.23 0.71 + 0.031*cl 0.71 + 0.030*cl 0.65 + 0.031*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phob24sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.62 1.65 + 0.019*cl 1.71 + 0.019*cl 1.73 + 0.018*cl t phl 2.60 1.81 + 0.016*cl 1.85 + 0.015*cl 1.86 + 0.015*cl t r 2.54 0.67 + 0.037*cl 0.63 + 0.038*cl 0.65 + 0.038*cl t f 2.15 0.82 + 0.027*cl 0.78 + 0.027*cl 0.80 + 0.027*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phob4sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 6.14 1.45 + 0.094*cl 1.44 + 0.094*cl 1.46 + 0.094*cl t phl 5.43 1.71 + 0.074*cl 1.72 + 0.074*cl 1.72 + 0.074*cl t r 10.84 0.25 + 0.212*cl 0.25 + 0.212*cl 0.24 + 0.212*cl t f 8.06 0.43 + 0.153*cl 0.39 + 0.153*cl 0.36 + 0.154*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phob8sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 4.12 1.77 + 0.047*cl 1.78 + 0.047*cl 1.78 + 0.047*cl t phl 4.04 2.08 + 0.039*cl 2.14 + 0.038*cl 2.18 + 0.038*cl t r 5.60 0.38 + 0.104*cl 0.34 + 0.105*cl 0.32 + 0.105*cl t f 4.47 0.74 + 0.074*cl 0.73 + 0.075*cl 0.69 + 0.075*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-40 sec asic pvobyz normal output buffers KGM80 phob12sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.54 1.79 + 0.035*cl 1.81 + 0.035*cl 1.82 + 0.035*cl t phl 3.53 2.00 + 0.031*cl 2.09 + 0.030*cl 2.13 + 0.029*cl t r 4.25 0.46 + 0.076*cl 0.41 + 0.077*cl 0.40 + 0.077*cl t f 3.56 0.83 + 0.055*cl 0.81 + 0.055*cl 0.83 + 0.055*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phob16sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.19 1.87 + 0.026*cl 1.92 + 0.026*cl 1.93 + 0.026*cl t phl 3.10 1.91 + 0.024*cl 2.01 + 0.022*cl 2.05 + 0.022*cl t r 3.32 0.59 + 0.055*cl 0.56 + 0.055*cl 0.53 + 0.055*cl t f 2.78 0.74 + 0.041*cl 0.77 + 0.040*cl 0.80 + 0.040*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phob20sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.35 1.33 + 0.020*cl 1.36 + 0.020*cl 1.36 + 0.020*cl t phl 2.19 1.30 + 0.018*cl 1.35 + 0.017*cl 1.39 + 0.017*cl t r 2.54 0.39 + 0.043*cl 0.35 + 0.044*cl 0.33 + 0.044*cl t f 2.12 0.56 + 0.031*cl 0.57 + 0.031*cl 0.56 + 0.031*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phob24sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.33 1.42 + 0.018*cl 1.44 + 0.018*cl 1.47 + 0.018*cl t phl 2.21 1.38 + 0.017*cl 1.45 + 0.016*cl 1.48 + 0.015*cl t r 2.34 0.46 + 0.038*cl 0.44 + 0.038*cl 0.42 + 0.038*cl t f 2.02 0.65 + 0.028*cl 0.65 + 0.027*cl 0.66 + 0.027*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-41 kg80/KGM80 pvodyz open drain output buffers cell availability logic symbol notes: 1. kg80 standard open-drain output buffers, pod(1/2/4/8/12/16/20/24), cannot tolerate external pull-ups to more than 5.5v. and KGM80 standard open-drain output buffers, pod(1/2/4/6/8/10/12/16), cannot tolerate external pull-ups to more than 3.6v. 2. fail-safe open-drain output buffers with external pull-ups to more than 5.5 v (in case of kg80) / 3.6v (in case of KGM80) can drive signals to that voltage range. however, if you want to use fail-safe open-drains, please contact to sec asic ?rst. i/o slot library 5v operation 3.3v operation kg80 pod(1/2/4/8/12/16/20/24) pod(12/16/20/24)sh pod(4/8/12/16/20/24)sm plod(1/2/4/6/8/10/12/16) plod(4/6/8/10/12/16)sm KGM80 phod(1/2/4/8/12/16/20/24) phod(12/16/20/24)sh phod(4/8/12/16/20/24)sm pod(1/2/4/6/8/10/12/16) pod(4/6/8/10/12/16)sm kg80/KGM80 pvodyz 1.0 pa d tn en truth table input load (sl) tn en pad 100 0 x hi-z x 1 hi-z kg80 tn en pod(1/2/4/8/12/16/20/24) 1.4 1.6 pod(12/16/20/24)sh 1.4 1.6 pod(4/8/12/16/20/24)sm 1.4 1.6 plod(1/2/4/6/8/10/12/16) 1.2 1.2 plod(4/6/8/10/12/16)sm 1.2 1.2 KGM80 tn en pod(1/2/4/6/8/10/12/16) 1.8 1.8 pod(4/6/8/10/12/16)sm 1.8 1.8 phod(1/2/4/8/12/16/20/24) 1.4 1.4 phod(12/16/20/24)sh 1.4 1.4 phod(4/8/12/16/20/24)sm 1.4 1.4
kg80/KGM80 4-42 sec asic pvodyz open drain output buffers kg80 pod1 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 12.21 0.56 + 0.233*cl 0.57 + 0.233*cl 0.56 + 0.233*cl t f 24.65 0.40 + 0.485*cl 0.40 + 0.485*cl 0.39 + 0.485*cl t plz 0.50 0.50 + 0.000*cl 0.50 + 0.000*cl 0.50 + 0.000*cl en to pad t phl 12.36 0.72 + 0.233*cl 0.71 + 0.233*cl 0.73 + 0.233*cl t f 24.65 0.40 + 0.485*cl 0.40 + 0.485*cl 0.39 + 0.485*cl t plz 0.41 0.41 + 0.000*cl 0.41 + 0.000*cl 0.41 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pod2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 6.29 0.47 + 0.116*cl 0.47 + 0.116*cl 0.47 + 0.116*cl t f 12.34 0.21 + 0.243*cl 0.20 + 0.243*cl 0.21 + 0.243*cl t plz 0.53 0.53 + 0.000*cl 0.53 + 0.000*cl 0.53 + 0.000*cl en to pad t phl 6.45 0.63 + 0.116*cl 0.63 + 0.116*cl 0.62 + 0.116*cl t f 12.34 0.21 + 0.243*cl 0.20 + 0.243*cl 0.21 + 0.243*cl t plz 0.44 0.44 + 0.000*cl 0.44 + 0.000*cl 0.44 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pod4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 4.19 0.48 + 0.074*cl 0.48 + 0.074*cl 0.47 + 0.074*cl t f 7.88 0.14 + 0.155*cl 0.15 + 0.155*cl 0.14 + 0.155*cl t plz 0.54 0.54 + 0.000*cl 0.54 + 0.000*cl 0.54 + 0.000*cl en to pad t phl 4.34 0.63 + 0.074*cl 0.64 + 0.074*cl 0.63 + 0.074*cl t f 7.88 0.14 + 0.155*cl 0.15 + 0.155*cl 0.14 + 0.155*cl t plz 0.45 0.45 + 0.000*cl 0.45 + 0.000*cl 0.45 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-43 kg80/KGM80 pvodyz open drain output buffers kg80 pod8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.38 0.53 + 0.037*cl 0.53 + 0.037*cl 0.53 + 0.037*cl t f 3.96 0.10 + 0.077*cl 0.09 + 0.077*cl 0.09 + 0.077*cl t plz 0.62 0.62 + 0.000*cl 0.62 + 0.000*cl 0.62 + 0.000*cl en to pad t phl 2.54 0.69 + 0.037*cl 0.69 + 0.037*cl 0.69 + 0.037*cl t f 3.96 0.10 + 0.077*cl 0.09 + 0.077*cl 0.09 + 0.077*cl t plz 0.54 0.54 + 0.000*cl 0.54 + 0.000*cl 0.54 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pod12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 1.95 0.58 + 0.027*cl 0.58 + 0.027*cl 0.58 + 0.027*cl t f 2.93 0.11 + 0.056*cl 0.10 + 0.057*cl 0.10 + 0.057*cl t plz 0.68 0.68 + 0.000*cl 0.68 + 0.000*cl 0.68 + 0.000*cl en to pad t phl 2.10 0.74 + 0.027*cl 0.74 + 0.027*cl 0.74 + 0.027*cl t f 2.93 0.11 + 0.056*cl 0.10 + 0.057*cl 0.10 + 0.057*cl t plz 0.60 0.60 + 0.000*cl 0.60 + 0.000*cl 0.60 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pod16 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 1.66 0.66 + 0.020*cl 0.66 + 0.020*cl 0.67 + 0.020*cl t f 2.19 0.15 + 0.041*cl 0.13 + 0.041*cl 0.12 + 0.041*cl t plz 0.76 0.76 + 0.000*cl 0.76 + 0.000*cl 0.76 + 0.000*cl en to pad t phl 1.82 0.82 + 0.020*cl 0.83 + 0.020*cl 0.82 + 0.020*cl t f 2.19 0.15 + 0.041*cl 0.13 + 0.041*cl 0.12 + 0.041*cl t plz 0.68 0.68 + 0.000*cl 0.68 + 0.000*cl 0.67 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-44 sec asic pvodyz open drain output buffers kg80 pod20 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 1.53 0.74 + 0.016*cl 0.74 + 0.016*cl 0.75 + 0.016*cl t f 1.79 0.20 + 0.032*cl 0.19 + 0.032*cl 0.17 + 0.032*cl t plz 0.85 0.84 + 0.000*cl 0.85 + 0.000*cl 0.85 + 0.000*cl en to pad t phl 1.69 0.89 + 0.016*cl 0.90 + 0.016*cl 0.90 + 0.016*cl t f 1.79 0.20 + 0.032*cl 0.19 + 0.032*cl 0.17 + 0.032*cl t plz 0.76 0.76 + 0.000*cl 0.76 + 0.000*cl 0.76 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pod24 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 1.48 0.77 + 0.014*cl 0.79 + 0.014*cl 0.79 + 0.014*cl t f 1.62 0.23 + 0.028*cl 0.22 + 0.028*cl 0.21 + 0.028*cl t plz 0.90 0.90 + 0.000*cl 0.90 + 0.000*cl 0.90 + 0.000*cl en to pad t phl 1.64 0.93 + 0.014*cl 0.95 + 0.014*cl 0.95 + 0.014*cl t f 1.62 0.23 + 0.028*cl 0.22 + 0.028*cl 0.21 + 0.028*cl t plz 0.81 0.81 + 0.000*cl 0.82 + 0.000*cl 0.82 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pod12sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.58 1.17 + 0.028*cl 1.19 + 0.028*cl 1.20 + 0.028*cl t f 3.19 0.41 + 0.056*cl 0.37 + 0.056*cl 0.35 + 0.056*cl t plz 0.52 0.52 + 0.000*cl 0.52 + 0.000*cl 0.52 + 0.000*cl en to pad t phl 2.74 1.33 + 0.028*cl 1.35 + 0.028*cl 1.35 + 0.028*cl t f 3.19 0.41 + 0.056*cl 0.37 + 0.056*cl 0.35 + 0.056*cl t plz 0.44 0.44 + 0.000*cl 0.44 + 0.000*cl 0.44 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-45 kg80/KGM80 pvodyz open drain output buffers kg80 pod16sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.45 1.36 + 0.022*cl 1.42 + 0.021*cl 1.44 + 0.021*cl t f 2.56 0.60 + 0.039*cl 0.57 + 0.040*cl 0.56 + 0.040*cl t plz 0.52 0.52 + 0.000*cl 0.52 + 0.000*cl 0.52 + 0.000*cl en to pad t phl 2.61 1.52 + 0.022*cl 1.57 + 0.021*cl 1.61 + 0.021*cl t f 2.56 0.60 + 0.039*cl 0.57 + 0.040*cl 0.56 + 0.040*cl t plz 0.44 0.44 + 0.000*cl 0.44 + 0.000*cl 0.44 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pod20sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.27 1.34 + 0.019*cl 1.42 + 0.018*cl 1.45 + 0.017*cl t f 2.26 0.73 + 0.031*cl 0.73 + 0.031*cl 0.72 + 0.031*cl t plz 0.56 0.56 + 0.000*cl 0.56 + 0.000*cl 0.56 + 0.000*cl en to pad t phl 2.43 1.49 + 0.019*cl 1.57 + 0.018*cl 1.62 + 0.017*cl t f 2.26 0.73 + 0.031*cl 0.73 + 0.031*cl 0.72 + 0.031*cl t plz 0.47 0.47 + 0.000*cl 0.47 + 0.000*cl 0.47 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pod24sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.29 1.40 + 0.018*cl 1.50 + 0.017*cl 1.54 + 0.016*cl t f 2.17 0.81 + 0.027*cl 0.82 + 0.027*cl 0.82 + 0.027*cl t plz 0.56 0.56 + 0.000*cl 0.56 + 0.000*cl 0.56 + 0.000*cl en to pad t phl 2.45 1.56 + 0.018*cl 1.66 + 0.016*cl 1.70 + 0.016*cl t f 2.17 0.81 + 0.027*cl 0.82 + 0.027*cl 0.82 + 0.027*cl t plz 0.47 0.47 + 0.000*cl 0.47 + 0.000*cl 0.47 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-46 sec asic pvodyz open drain output buffers kg80 pod4sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 4.43 0.71 + 0.074*cl 0.72 + 0.074*cl 0.71 + 0.074*cl t f 7.89 0.16 + 0.155*cl 0.15 + 0.155*cl 0.16 + 0.155*cl t plz 0.57 0.57 + 0.000*cl 0.57 + 0.000*cl 0.57 + 0.000*cl en to pad t phl 4.58 0.87 + 0.074*cl 0.87 + 0.074*cl 0.87 + 0.074*cl t f 7.89 0.16 + 0.155*cl 0.15 + 0.155*cl 0.16 + 0.155*cl t plz 0.49 0.49 + 0.000*cl 0.49 + 0.000*cl 0.49 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pod8sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.87 1.01 + 0.037*cl 1.01 + 0.037*cl 1.02 + 0.037*cl t f 4.07 0.27 + 0.076*cl 0.24 + 0.076*cl 0.22 + 0.077*cl t plz 0.57 0.57 + 0.000*cl 0.57 + 0.000*cl 0.57 + 0.000*cl en to pad t phl 3.03 1.17 + 0.037*cl 1.17 + 0.037*cl 1.17 + 0.037*cl t f 4.07 0.27 + 0.076*cl 0.24 + 0.076*cl 0.22 + 0.077*cl t plz 0.49 0.49 + 0.000*cl 0.49 + 0.000*cl 0.49 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pod12sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.38 1.00 + 0.028*cl 1.01 + 0.027*cl 1.03 + 0.027*cl t f 3.10 0.36 + 0.055*cl 0.33 + 0.055*cl 0.30 + 0.056*cl t plz 0.56 0.56 + 0.000*cl 0.56 + 0.000*cl 0.56 + 0.000*cl en to pad t phl 2.54 1.16 + 0.028*cl 1.17 + 0.027*cl 1.18 + 0.027*cl t f 3.10 0.36 + 0.055*cl 0.33 + 0.055*cl 0.30 + 0.056*cl t plz 0.48 0.48 + 0.000*cl 0.48 + 0.000*cl 0.48 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-47 kg80/KGM80 pvodyz open drain output buffers kg80 pod16sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.12 1.06 + 0.021*cl 1.10 + 0.021*cl 1.12 + 0.020*cl t f 2.47 0.51 + 0.039*cl 0.48 + 0.040*cl 0.46 + 0.040*cl t plz 0.59 0.59 + 0.000*cl 0.59 + 0.000*cl 0.59 + 0.000*cl en to pad t phl 2.27 1.21 + 0.021*cl 1.26 + 0.021*cl 1.28 + 0.020*cl t f 2.47 0.51 + 0.039*cl 0.48 + 0.040*cl 0.46 + 0.040*cl t plz 0.51 0.51 + 0.000*cl 0.51 + 0.000*cl 0.51 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pod20sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 1.98 1.08 + 0.018*cl 1.15 + 0.017*cl 1.17 + 0.017*cl t f 2.15 0.62 + 0.031*cl 0.61 + 0.031*cl 0.60 + 0.031*cl t plz 0.62 0.62 + 0.000*cl 0.62 + 0.000*cl 0.62 + 0.000*cl en to pad t phl 2.14 1.24 + 0.018*cl 1.30 + 0.017*cl 1.34 + 0.017*cl t f 2.15 0.62 + 0.031*cl 0.61 + 0.031*cl 0.60 + 0.031*cl t plz 0.53 0.53 + 0.000*cl 0.53 + 0.000*cl 0.53 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pod24sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.00 1.14 + 0.017*cl 1.22 + 0.016*cl 1.27 + 0.016*cl t f 2.07 0.71 + 0.027*cl 0.73 + 0.027*cl 0.73 + 0.027*cl t plz 0.62 0.62 + 0.000*cl 0.62 + 0.000*cl 0.62 + 0.000*cl en to pad t phl 2.16 1.30 + 0.017*cl 1.38 + 0.016*cl 1.42 + 0.016*cl t f 2.07 0.71 + 0.027*cl 0.73 + 0.027*cl 0.73 + 0.027*cl t plz 0.53 0.53 + 0.000*cl 0.53 + 0.000*cl 0.53 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-48 sec asic pvodyz open drain output buffers kg80 plod1 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 14.09 0.89 + 0.264*cl 0.88 + 0.264*cl 0.88 + 0.264*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl t plz 0.80 0.80 + 0.000*cl 0.80 + 0.000*cl 0.80 + 0.000*cl en to pad t phl 14.20 1.00 + 0.264*cl 1.00 + 0.264*cl 1.00 + 0.264*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl t plz 0.73 0.73 + 0.000*cl 0.73 + 0.000*cl 0.73 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plod2 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 6.97 0.79 + 0.124*cl 0.79 + 0.124*cl 0.80 + 0.123*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl t plz 0.84 0.84 + 0.000*cl 0.84 + 0.000*cl 0.84 + 0.000*cl en to pad t phl 7.08 0.91 + 0.123*cl 0.90 + 0.124*cl 0.90 + 0.124*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl t plz 0.78 0.78 + 0.000*cl 0.78 + 0.000*cl 0.78 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plod4 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.92 0.83 + 0.062*cl 0.83 + 0.062*cl 0.82 + 0.062*cl t f 6.81 0.15 + 0.133*cl 0.15 + 0.133*cl 0.16 + 0.133*cl t plz 0.91 0.91 + 0.000*cl 0.91 + 0.000*cl 0.91 + 0.000*cl en to pad t phl 4.03 0.94 + 0.062*cl 0.94 + 0.062*cl 0.94 + 0.062*cl t f 6.81 0.16 + 0.133*cl 0.16 + 0.133*cl 0.15 + 0.133*cl t plz 0.85 0.85 + 0.000*cl 0.85 + 0.000*cl 0.85 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-49 kg80/KGM80 pvodyz open drain output buffers kg80 plod6 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.96 0.90 + 0.041*cl 0.90 + 0.041*cl 0.91 + 0.041*cl t f 4.57 0.14 + 0.089*cl 0.13 + 0.089*cl 0.13 + 0.089*cl t plz 0.98 0.98 + 0.000*cl 0.98 + 0.000*cl 0.98 + 0.000*cl en to pad t phl 3.07 1.01 + 0.041*cl 1.02 + 0.041*cl 1.01 + 0.041*cl t f 4.57 0.14 + 0.089*cl 0.12 + 0.089*cl 0.13 + 0.089*cl t plz 0.92 0.92 + 0.000*cl 0.92 + 0.000*cl 0.92 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plod8 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.54 0.99 + 0.031*cl 0.99 + 0.031*cl 0.99 + 0.031*cl t f 3.48 0.18 + 0.066*cl 0.15 + 0.066*cl 0.16 + 0.066*cl t plz 1.05 1.05 + 0.000*cl 1.05 + 0.000*cl 1.05 + 0.000*cl en to pad t phl 2.65 1.10 + 0.031*cl 1.10 + 0.031*cl 1.11 + 0.031*cl t f 3.47 0.18 + 0.066*cl 0.15 + 0.066*cl 0.13 + 0.066*cl t plz 0.98 0.98 + 0.000*cl 0.98 + 0.000*cl 0.98 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plod10 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.32 1.08 + 0.025*cl 1.08 + 0.025*cl 1.09 + 0.025*cl t f 2.84 0.24 + 0.052*cl 0.17 + 0.053*cl 0.19 + 0.053*cl t plz 1.12 1.12 + 0.000*cl 1.12 + 0.000*cl 1.12 + 0.000*cl en to pad t phl 2.43 1.19 + 0.025*cl 1.20 + 0.025*cl 1.19 + 0.025*cl t f 2.84 0.23 + 0.052*cl 0.19 + 0.053*cl 0.19 + 0.053*cl t plz 1.05 1.05 + 0.000*cl 1.05 + 0.000*cl 1.05 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-50 sec asic pvodyz open drain output buffers kg80 plod12 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.20 1.16 + 0.021*cl 1.17 + 0.021*cl 1.18 + 0.021*cl t f 2.43 0.28 + 0.043*cl 0.25 + 0.044*cl 0.26 + 0.043*cl t plz 1.19 1.19 + 0.000*cl 1.19 + 0.000*cl 1.19 + 0.000*cl en to pad t phl 2.31 1.27 + 0.021*cl 1.28 + 0.021*cl 1.28 + 0.021*cl t f 2.44 0.28 + 0.043*cl 0.27 + 0.043*cl 0.26 + 0.043*cl t plz 1.12 1.12 + 0.000*cl 1.12 + 0.000*cl 1.12 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plod16 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.11 1.29 + 0.016*cl 1.32 + 0.016*cl 1.32 + 0.016*cl t f 1.99 0.37 + 0.032*cl 0.38 + 0.032*cl 0.34 + 0.033*cl t plz 1.31 1.31 + 0.000*cl 1.31 + 0.000*cl 1.31 + 0.000*cl en to pad t phl 2.22 1.40 + 0.016*cl 1.42 + 0.016*cl 1.44 + 0.016*cl t f 2.00 0.39 + 0.032*cl 0.37 + 0.032*cl 0.36 + 0.033*cl t plz 1.25 1.24 + 0.000*cl 1.25 + 0.000*cl 1.25 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plod4sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 4.51 1.32 + 0.064*cl 1.32 + 0.064*cl 1.32 + 0.064*cl t f 7.11 0.28 + 0.137*cl 0.24 + 0.137*cl 0.22 + 0.137*cl t plz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl en to pad t phl 4.62 1.43 + 0.064*cl 1.43 + 0.064*cl 1.43 + 0.064*cl t f 7.10 0.27 + 0.137*cl 0.24 + 0.137*cl 0.23 + 0.137*cl t plz 0.81 0.81 + 0.000*cl 0.81 + 0.000*cl 0.81 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-51 kg80/KGM80 pvodyz open drain output buffers kg80 plod6sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.77 1.65 + 0.042*cl 1.66 + 0.042*cl 1.67 + 0.042*cl t f 4.89 0.48 + 0.088*cl 0.44 + 0.089*cl 0.39 + 0.089*cl t plz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl en to pad t phl 3.88 1.76 + 0.042*cl 1.78 + 0.042*cl 1.79 + 0.042*cl t f 4.89 0.48 + 0.088*cl 0.42 + 0.089*cl 0.39 + 0.089*cl t plz 0.81 0.81 + 0.000*cl 0.81 + 0.000*cl 0.81 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plod8sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.56 1.92 + 0.033*cl 1.98 + 0.032*cl 1.99 + 0.032*cl t f 3.93 0.72 + 0.064*cl 0.65 + 0.065*cl 0.61 + 0.066*cl t plz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl en to pad t phl 3.67 2.03 + 0.033*cl 2.09 + 0.032*cl 2.10 + 0.032*cl t f 3.93 0.72 + 0.064*cl 0.65 + 0.065*cl 0.62 + 0.066*cl t plz 0.81 0.81 + 0.000*cl 0.81 + 0.000*cl 0.81 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plod10sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.20 1.83 + 0.027*cl 1.92 + 0.026*cl 1.95 + 0.026*cl t f 3.38 0.91 + 0.049*cl 0.84 + 0.050*cl 0.82 + 0.050*cl t plz 0.92 0.92 + 0.000*cl 0.92 + 0.000*cl 0.92 + 0.000*cl en to pad t phl 3.31 1.94 + 0.027*cl 2.03 + 0.026*cl 2.07 + 0.026*cl t f 3.38 0.92 + 0.049*cl 0.88 + 0.050*cl 0.82 + 0.050*cl t plz 0.85 0.85 + 0.000*cl 0.85 + 0.000*cl 0.85 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-52 sec asic pvodyz open drain output buffers kg80 plod12sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.23 1.99 + 0.025*cl 2.10 + 0.023*cl 2.16 + 0.023*cl t f 3.15 1.12 + 0.041*cl 1.06 + 0.041*cl 1.08 + 0.041*cl t plz 0.92 0.92 + 0.000*cl 0.92 + 0.000*cl 0.92 + 0.000*cl en to pad t phl 3.34 2.10 + 0.025*cl 2.21 + 0.023*cl 2.28 + 0.023*cl t f 3.15 1.12 + 0.041*cl 1.11 + 0.041*cl 1.06 + 0.041*cl t plz 0.85 0.85 + 0.000*cl 0.85 + 0.000*cl 0.85 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plod16sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.38 2.23 + 0.023*cl 2.41 + 0.021*cl 2.48 + 0.020*cl t f 2.98 1.43 + 0.031*cl 1.44 + 0.031*cl 1.41 + 0.031*cl t plz 0.91 0.91 + 0.000*cl 0.91 + 0.000*cl 0.91 + 0.000*cl en to pad t phl 3.50 2.35 + 0.023*cl 2.51 + 0.021*cl 2.60 + 0.020*cl t f 2.99 1.45 + 0.031*cl 1.42 + 0.031*cl 1.42 + 0.031*cl t plz 0.85 0.85 + 0.000*cl 0.85 + 0.000*cl 0.85 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pod1 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 13.96 0.76 + 0.264*cl 0.76 + 0.264*cl 0.76 + 0.264*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl t plz 0.64 0.64 + 0.000*cl 0.64 + 0.000*cl 0.64 + 0.000*cl en to pad t phl 14.16 0.96 + 0.264*cl 0.96 + 0.264*cl 0.96 + 0.264*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl t plz 0.53 0.53 + 0.000*cl 0.53 + 0.000*cl 0.53 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-53 kg80/KGM80 pvodyz open drain output buffers KGM80 pod2 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 6.85 0.68 + 0.124*cl 0.67 + 0.124*cl 0.68 + 0.123*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl t plz 0.68 0.68 + 0.000*cl 0.68 + 0.000*cl 0.68 + 0.000*cl en to pad t phl 7.04 0.87 + 0.124*cl 0.87 + 0.123*cl 0.87 + 0.124*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl t plz 0.57 0.57 + 0.000*cl 0.57 + 0.000*cl 0.57 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pod4 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.80 0.71 + 0.062*cl 0.71 + 0.062*cl 0.71 + 0.062*cl t f 6.81 0.15 + 0.133*cl 0.15 + 0.133*cl 0.15 + 0.133*cl t plz 0.75 0.75 + 0.000*cl 0.75 + 0.000*cl 0.75 + 0.000*cl en to pad t phl 3.99 0.90 + 0.062*cl 0.90 + 0.062*cl 0.90 + 0.062*cl t f 6.81 0.15 + 0.133*cl 0.15 + 0.133*cl 0.15 + 0.133*cl t plz 0.64 0.64 + 0.000*cl 0.64 + 0.000*cl 0.64 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pod6 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.85 0.79 + 0.041*cl 0.79 + 0.041*cl 0.79 + 0.041*cl t f 4.57 0.14 + 0.089*cl 0.14 + 0.089*cl 0.13 + 0.089*cl t plz 0.82 0.82 + 0.000*cl 0.82 + 0.000*cl 0.82 + 0.000*cl en to pad t phl 3.04 0.98 + 0.041*cl 0.98 + 0.041*cl 0.98 + 0.041*cl t f 4.57 0.14 + 0.089*cl 0.13 + 0.089*cl 0.14 + 0.089*cl t plz 0.71 0.71 + 0.000*cl 0.71 + 0.000*cl 0.71 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-54 sec asic pvodyz open drain output buffers KGM80 pod8 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.40 0.86 + 0.031*cl 0.85 + 0.031*cl 0.86 + 0.031*cl t f 3.49 0.21 + 0.066*cl 0.18 + 0.066*cl 0.16 + 0.066*cl t plz 0.89 0.89 + 0.000*cl 0.89 + 0.000*cl 0.89 + 0.000*cl en to pad t phl 2.61 1.07 + 0.031*cl 1.06 + 0.031*cl 1.07 + 0.031*cl t f 3.47 0.18 + 0.066*cl 0.15 + 0.066*cl 0.15 + 0.066*cl t plz 0.78 0.78 + 0.000*cl 0.78 + 0.000*cl 0.78 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pod10 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.18 0.95 + 0.025*cl 0.95 + 0.025*cl 0.95 + 0.025*cl t f 2.86 0.27 + 0.052*cl 0.22 + 0.052*cl 0.21 + 0.053*cl t plz 0.95 0.95 + 0.000*cl 0.95 + 0.000*cl 0.95 + 0.000*cl en to pad t phl 2.39 1.15 + 0.025*cl 1.16 + 0.025*cl 1.15 + 0.025*cl t f 2.84 0.24 + 0.052*cl 0.19 + 0.053*cl 0.20 + 0.053*cl t plz 0.85 0.84 + 0.000*cl 0.84 + 0.000*cl 0.85 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pod12 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.07 1.03 + 0.021*cl 1.03 + 0.021*cl 1.03 + 0.021*cl t f 2.46 0.33 + 0.043*cl 0.30 + 0.043*cl 0.25 + 0.044*cl t plz 1.02 1.02 + 0.000*cl 1.02 + 0.000*cl 1.02 + 0.000*cl en to pad t phl 2.27 1.23 + 0.021*cl 1.25 + 0.021*cl 1.25 + 0.021*cl t f 2.44 0.28 + 0.043*cl 0.25 + 0.044*cl 0.26 + 0.043*cl t plz 0.91 0.91 + 0.000*cl 0.91 + 0.000*cl 0.91 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-55 kg80/KGM80 pvodyz open drain output buffers KGM80 pod16 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 1.98 1.16 + 0.016*cl 1.18 + 0.016*cl 1.20 + 0.016*cl t f 2.01 0.39 + 0.032*cl 0.39 + 0.032*cl 0.38 + 0.032*cl t plz 1.15 1.15 + 0.000*cl 1.15 + 0.000*cl 1.15 + 0.000*cl en to pad t phl 2.18 1.36 + 0.016*cl 1.40 + 0.016*cl 1.39 + 0.016*cl t f 2.00 0.39 + 0.032*cl 0.36 + 0.033*cl 0.34 + 0.033*cl t plz 1.04 1.04 + 0.000*cl 1.04 + 0.000*cl 1.04 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pod4sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 4.39 1.20 + 0.064*cl 1.20 + 0.064*cl 1.20 + 0.064*cl t f 7.11 0.28 + 0.137*cl 0.24 + 0.137*cl 0.22 + 0.137*cl t plz 0.70 0.70 + 0.000*cl 0.70 + 0.000*cl 0.70 + 0.000*cl en to pad t phl 4.58 1.39 + 0.064*cl 1.39 + 0.064*cl 1.39 + 0.064*cl t f 7.10 0.27 + 0.137*cl 0.24 + 0.137*cl 0.22 + 0.137*cl t plz 0.60 0.60 + 0.000*cl 0.60 + 0.000*cl 0.60 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pod6sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.65 1.54 + 0.042*cl 1.55 + 0.042*cl 1.55 + 0.042*cl t f 4.89 0.48 + 0.088*cl 0.43 + 0.089*cl 0.39 + 0.089*cl t plz 0.70 0.70 + 0.000*cl 0.70 + 0.000*cl 0.70 + 0.000*cl en to pad t phl 3.85 1.73 + 0.042*cl 1.74 + 0.042*cl 1.74 + 0.042*cl t f 4.89 0.48 + 0.088*cl 0.43 + 0.089*cl 0.39 + 0.089*cl t plz 0.60 0.60 + 0.000*cl 0.60 + 0.000*cl 0.60 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-56 sec asic pvodyz open drain output buffers KGM80 pod8sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.44 1.80 + 0.033*cl 1.85 + 0.032*cl 1.88 + 0.032*cl t f 3.93 0.73 + 0.064*cl 0.64 + 0.065*cl 0.63 + 0.065*cl t plz 0.70 0.70 + 0.000*cl 0.70 + 0.000*cl 0.70 + 0.000*cl en to pad t phl 3.63 2.00 + 0.033*cl 2.04 + 0.032*cl 2.07 + 0.032*cl t f 3.93 0.72 + 0.064*cl 0.66 + 0.065*cl 0.62 + 0.065*cl t plz 0.60 0.60 + 0.000*cl 0.60 + 0.000*cl 0.60 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pod10sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.08 1.72 + 0.027*cl 1.80 + 0.026*cl 1.84 + 0.026*cl t f 3.38 0.91 + 0.049*cl 0.86 + 0.050*cl 0.83 + 0.050*cl t plz 0.75 0.75 + 0.000*cl 0.75 + 0.000*cl 0.75 + 0.000*cl en to pad t phl 3.27 1.91 + 0.027*cl 1.99 + 0.026*cl 2.03 + 0.026*cl t f 3.38 0.92 + 0.049*cl 0.87 + 0.050*cl 0.83 + 0.050*cl t plz 0.65 0.65 + 0.000*cl 0.65 + 0.000*cl 0.65 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pod12sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.11 1.87 + 0.025*cl 1.99 + 0.023*cl 2.04 + 0.023*cl t f 3.15 1.13 + 0.040*cl 1.07 + 0.041*cl 1.07 + 0.041*cl t plz 0.75 0.75 + 0.000*cl 0.75 + 0.000*cl 0.75 + 0.000*cl en to pad t phl 3.30 2.06 + 0.025*cl 2.18 + 0.023*cl 2.24 + 0.023*cl t f 3.15 1.12 + 0.041*cl 1.09 + 0.041*cl 1.08 + 0.041*cl t plz 0.65 0.65 + 0.000*cl 0.65 + 0.000*cl 0.65 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-57 kg80/KGM80 pvodyz open drain output buffers KGM80 pod16sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.27 2.12 + 0.023*cl 2.28 + 0.021*cl 2.37 + 0.020*cl t f 2.98 1.43 + 0.031*cl 1.46 + 0.031*cl 1.43 + 0.031*cl t plz 0.75 0.75 + 0.000*cl 0.75 + 0.000*cl 0.75 + 0.000*cl en to pad t phl 3.46 2.31 + 0.023*cl 2.48 + 0.021*cl 2.56 + 0.020*cl t f 2.98 1.43 + 0.031*cl 1.45 + 0.031*cl 1.43 + 0.031*cl t plz 0.65 0.65 + 0.000*cl 0.65 + 0.000*cl 0.65 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phod1 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 12.57 0.93 + 0.233*cl 0.93 + 0.233*cl 0.93 + 0.233*cl t f 24.65 0.40 + 0.485*cl 0.40 + 0.485*cl 0.40 + 0.485*cl t plz 0.84 0.84 + 0.000*cl 0.84 + 0.000*cl 0.84 + 0.000*cl en to pad t phl 12.75 1.10 + 0.233*cl 1.10 + 0.233*cl 1.10 + 0.233*cl t f 24.65 0.40 + 0.485*cl 0.40 + 0.485*cl 0.40 + 0.485*cl t plz 0.77 0.77 + 0.000*cl 0.77 + 0.000*cl 0.77 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phod2 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 6.66 0.84 + 0.116*cl 0.84 + 0.116*cl 0.84 + 0.116*cl t f 12.34 0.21 + 0.243*cl 0.21 + 0.243*cl 0.21 + 0.243*cl t plz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl en to pad t phl 6.83 1.01 + 0.116*cl 1.01 + 0.116*cl 1.01 + 0.116*cl t f 12.34 0.21 + 0.243*cl 0.21 + 0.243*cl 0.21 + 0.243*cl t plz 0.80 0.80 + 0.000*cl 0.80 + 0.000*cl 0.80 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-58 sec asic pvodyz open drain output buffers KGM80 phod4 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 4.56 0.85 + 0.074*cl 0.85 + 0.074*cl 0.85 + 0.074*cl t f 7.88 0.14 + 0.155*cl 0.14 + 0.155*cl 0.15 + 0.155*cl t plz 0.88 0.88 + 0.000*cl 0.88 + 0.000*cl 0.88 + 0.000*cl en to pad t phl 4.73 1.02 + 0.074*cl 1.02 + 0.074*cl 1.02 + 0.074*cl t f 7.88 0.15 + 0.155*cl 0.15 + 0.155*cl 0.15 + 0.155*cl t plz 0.80 0.80 + 0.000*cl 0.80 + 0.000*cl 0.80 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phod8 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.76 0.90 + 0.037*cl 0.90 + 0.037*cl 0.90 + 0.037*cl t f 3.96 0.10 + 0.077*cl 0.10 + 0.077*cl 0.10 + 0.077*cl t plz 0.96 0.96 + 0.000*cl 0.96 + 0.000*cl 0.96 + 0.000*cl en to pad t phl 2.93 1.07 + 0.037*cl 1.07 + 0.037*cl 1.07 + 0.037*cl t f 3.96 0.10 + 0.077*cl 0.10 + 0.077*cl 0.10 + 0.077*cl t plz 0.89 0.89 + 0.000*cl 0.89 + 0.000*cl 0.89 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phod12 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.32 0.95 + 0.027*cl 0.96 + 0.027*cl 0.96 + 0.027*cl t f 2.93 0.11 + 0.056*cl 0.12 + 0.056*cl 0.09 + 0.057*cl t plz 1.03 1.03 + 0.000*cl 1.03 + 0.000*cl 1.03 + 0.000*cl en to pad t phl 2.49 1.13 + 0.027*cl 1.13 + 0.027*cl 1.13 + 0.027*cl t f 2.94 0.12 + 0.056*cl 0.09 + 0.057*cl 0.10 + 0.057*cl t plz 0.95 0.95 + 0.000*cl 0.95 + 0.000*cl 0.95 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-59 kg80/KGM80 pvodyz open drain output buffers KGM80 phod16 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.03 1.04 + 0.020*cl 1.03 + 0.020*cl 1.04 + 0.020*cl t f 2.20 0.15 + 0.041*cl 0.15 + 0.041*cl 0.15 + 0.041*cl t plz 1.11 1.11 + 0.000*cl 1.10 + 0.000*cl 1.11 + 0.000*cl en to pad t phl 2.21 1.21 + 0.020*cl 1.21 + 0.020*cl 1.20 + 0.020*cl t f 2.20 0.15 + 0.041*cl 0.16 + 0.041*cl 0.14 + 0.041*cl t plz 1.03 1.03 + 0.000*cl 1.03 + 0.000*cl 1.03 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phod20 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 1.90 1.11 + 0.016*cl 1.12 + 0.016*cl 1.12 + 0.016*cl t f 1.80 0.23 + 0.031*cl 0.18 + 0.032*cl 0.18 + 0.032*cl t plz 1.19 1.19 + 0.000*cl 1.18 + 0.000*cl 1.19 + 0.000*cl en to pad t phl 2.08 1.28 + 0.016*cl 1.29 + 0.016*cl 1.29 + 0.016*cl t f 1.80 0.22 + 0.032*cl 0.19 + 0.032*cl 0.20 + 0.032*cl t plz 1.12 1.11 + 0.000*cl 1.12 + 0.000*cl 1.12 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phod24 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 1.86 1.15 + 0.014*cl 1.16 + 0.014*cl 1.16 + 0.014*cl t f 1.63 0.24 + 0.028*cl 0.22 + 0.028*cl 0.22 + 0.028*cl t plz 1.24 1.24 + 0.000*cl 1.24 + 0.000*cl 1.24 + 0.000*cl en to pad t phl 2.03 1.32 + 0.014*cl 1.33 + 0.014*cl 1.34 + 0.014*cl t f 1.64 0.25 + 0.028*cl 0.23 + 0.028*cl 0.24 + 0.028*cl t plz 1.17 1.17 + 0.000*cl 1.17 + 0.000*cl 1.17 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-60 sec asic pvodyz open drain output buffers KGM80 phod12sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.95 1.54 + 0.028*cl 1.57 + 0.028*cl 1.57 + 0.028*cl t f 3.20 0.42 + 0.056*cl 0.37 + 0.056*cl 0.35 + 0.056*cl t plz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl en to pad t phl 3.13 1.71 + 0.028*cl 1.74 + 0.028*cl 1.75 + 0.028*cl t f 3.20 0.42 + 0.056*cl 0.38 + 0.056*cl 0.34 + 0.057*cl t plz 0.79 0.79 + 0.000*cl 0.79 + 0.000*cl 0.79 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phod16sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.82 1.73 + 0.022*cl 1.79 + 0.021*cl 1.81 + 0.021*cl t f 2.57 0.61 + 0.039*cl 0.57 + 0.040*cl 0.57 + 0.040*cl t plz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl en to pad t phl 2.99 1.90 + 0.022*cl 1.96 + 0.021*cl 1.99 + 0.021*cl t f 2.57 0.62 + 0.039*cl 0.57 + 0.040*cl 0.56 + 0.040*cl t plz 0.79 0.79 + 0.000*cl 0.79 + 0.000*cl 0.79 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phod20sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.64 1.70 + 0.019*cl 1.78 + 0.018*cl 1.83 + 0.017*cl t f 2.27 0.74 + 0.031*cl 0.76 + 0.030*cl 0.72 + 0.031*cl t plz 0.90 0.90 + 0.000*cl 0.90 + 0.000*cl 0.90 + 0.000*cl en to pad t phl 2.82 1.88 + 0.019*cl 1.95 + 0.018*cl 2.00 + 0.017*cl t f 2.27 0.75 + 0.030*cl 0.73 + 0.031*cl 0.74 + 0.031*cl t plz 0.83 0.83 + 0.000*cl 0.83 + 0.000*cl 0.83 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-61 kg80/KGM80 pvodyz open drain output buffers KGM80 phod24sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.66 1.77 + 0.018*cl 1.87 + 0.017*cl 1.91 + 0.016*cl t f 2.18 0.82 + 0.027*cl 0.81 + 0.027*cl 0.84 + 0.027*cl t plz 0.90 0.90 + 0.000*cl 0.90 + 0.000*cl 0.90 + 0.000*cl en to pad t phl 2.83 1.94 + 0.018*cl 2.04 + 0.017*cl 2.08 + 0.016*cl t f 2.18 0.84 + 0.027*cl 0.84 + 0.027*cl 0.86 + 0.027*cl t plz 0.83 0.83 + 0.000*cl 0.83 + 0.000*cl 0.83 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phod4sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 4.80 1.08 + 0.074*cl 1.09 + 0.074*cl 1.08 + 0.074*cl t f 7.89 0.16 + 0.155*cl 0.15 + 0.155*cl 0.16 + 0.155*cl t plz 0.92 0.92 + 0.000*cl 0.92 + 0.000*cl 0.92 + 0.000*cl en to pad t phl 4.97 1.26 + 0.074*cl 1.25 + 0.074*cl 1.26 + 0.074*cl t f 7.89 0.16 + 0.155*cl 0.15 + 0.155*cl 0.16 + 0.155*cl t plz 0.84 0.84 + 0.000*cl 0.84 + 0.000*cl 0.84 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phod8sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 3.24 1.38 + 0.037*cl 1.38 + 0.037*cl 1.39 + 0.037*cl t f 4.08 0.28 + 0.076*cl 0.25 + 0.076*cl 0.23 + 0.077*cl t plz 0.92 0.92 + 0.000*cl 0.92 + 0.000*cl 0.92 + 0.000*cl en to pad t phl 3.41 1.55 + 0.037*cl 1.56 + 0.037*cl 1.56 + 0.037*cl t f 4.08 0.28 + 0.076*cl 0.24 + 0.076*cl 0.23 + 0.077*cl t plz 0.84 0.84 + 0.000*cl 0.84 + 0.000*cl 0.84 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-62 sec asic pvodyz open drain output buffers KGM80 phod12sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.75 1.37 + 0.028*cl 1.39 + 0.027*cl 1.40 + 0.027*cl t f 3.11 0.37 + 0.055*cl 0.33 + 0.055*cl 0.30 + 0.056*cl t plz 0.90 0.90 + 0.000*cl 0.90 + 0.000*cl 0.90 + 0.000*cl en to pad t phl 2.92 1.54 + 0.028*cl 1.56 + 0.027*cl 1.57 + 0.027*cl t f 3.11 0.36 + 0.055*cl 0.33 + 0.055*cl 0.30 + 0.056*cl t plz 0.83 0.83 + 0.000*cl 0.83 + 0.000*cl 0.83 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phod16sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.49 1.43 + 0.021*cl 1.47 + 0.021*cl 1.50 + 0.020*cl t f 2.48 0.52 + 0.039*cl 0.49 + 0.040*cl 0.46 + 0.040*cl t plz 0.93 0.93 + 0.000*cl 0.93 + 0.000*cl 0.93 + 0.000*cl en to pad t phl 2.66 1.60 + 0.021*cl 1.65 + 0.021*cl 1.66 + 0.020*cl t f 2.48 0.52 + 0.039*cl 0.51 + 0.039*cl 0.47 + 0.040*cl t plz 0.86 0.86 + 0.000*cl 0.86 + 0.000*cl 0.86 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phod20sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.35 1.45 + 0.018*cl 1.52 + 0.017*cl 1.55 + 0.017*cl t f 2.16 0.62 + 0.031*cl 0.63 + 0.031*cl 0.61 + 0.031*cl t plz 0.96 0.96 + 0.000*cl 0.96 + 0.000*cl 0.96 + 0.000*cl en to pad t phl 2.52 1.62 + 0.018*cl 1.69 + 0.017*cl 1.72 + 0.017*cl t f 2.16 0.64 + 0.031*cl 0.60 + 0.031*cl 0.61 + 0.031*cl t plz 0.89 0.89 + 0.000*cl 0.89 + 0.000*cl 0.89 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-63 kg80/KGM80 pvodyz open drain output buffers KGM80 phod24sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* tn to pad t phl 2.37 1.51 + 0.017*cl 1.59 + 0.016*cl 1.63 + 0.016*cl t f 2.08 0.72 + 0.027*cl 0.74 + 0.027*cl 0.74 + 0.027*cl t plz 0.96 0.96 + 0.000*cl 0.96 + 0.000*cl 0.96 + 0.000*cl en to pad t phl 2.54 1.68 + 0.017*cl 1.76 + 0.016*cl 1.81 + 0.016*cl t f 2.08 0.73 + 0.027*cl 0.72 + 0.027*cl 0.74 + 0.027*cl t plz 0.89 0.89 + 0.000*cl 0.89 + 0.000*cl 0.89 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-64 sec asic pvotyz tri-state output buffers cell availability logic symbol truth table i/o slot library 5v operation 3.3v operation kg80 pot(1/2/4/8/12/16/20/24) pot(12/16/20/24)sh pot(4/8/12/16/20/24)sm plot(1/2/4/6/8/10/12/16) plot(4/6/8/10/12/16)sm KGM80 phot(1/2/4/8/12/16/20/24) phot(12/16/20/24)sh phot(4/8/12/16/20/24)sm pot(1/2/4/6/8/10/12/16) pot(4/6/8/10/12/16)sm tn en a pad 1000 1011 x 1 x hi-z 0 x x hi-z kg80/KGM80 pvotyz 1.0 pa d a tn en input load (sl) kg80 tn en a pot(1/2/4/8/12/16/20/24) 1.4 1.6 2.4 pot(12/16/20/24)sh 1.4 1.6 2.4 pot(4/8/12/16/20/24)sm 1.4 1.6 2.4 plot(1/2/4/6/8/10/12/16) 1.2 1.2 2.3 plot(4/6/8/10/12/16)sm 1.2 1.2 2.3 KGM80 tn en a pot(1/2/4/6/8/10/12/16) 1.8 1.8 2.6 pot(4/6/8/10/12/16)sm 1.8 1.8 2.6 phot(1/2/4/8/12/16/20/24) 1.4 1.4 2.8 phot(12/16/20/24)sh 1.4 1.4 2.8 phot(4/8/12/16/20/24)sm 1.4 1.4 2.8
sec asic 4-65 kg80/KGM80 pvotyz tri-state output buffers kg80 pot1 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 15.24 0.63 + 0.292*cl 0.63 + 0.292*cl 0.63 + 0.292*cl t phl 12.28 0.63 + 0.233*cl 0.63 + 0.233*cl 0.63 + 0.233*cl t r 33.59 0.59 + 0.660*cl 0.59 + 0.660*cl 0.59 + 0.660*cl t f 24.65 0.40 + 0.485*cl 0.40 + 0.485*cl 0.40 + 0.485*cl tn to pad t plh 15.23 0.73 + 0.290*cl 1.33 + 0.282*cl 2.49 + 0.268*cl t phl 12.30 0.65 + 0.233*cl 0.65 + 0.233*cl 0.65 + 0.233*cl t r 33.59 0.59 + 0.660*cl 0.60 + 0.660*cl 0.59 + 0.660*cl t f 24.65 0.40 + 0.485*cl 0.40 + 0.485*cl 0.40 + 0.485*cl t plz 0.63 0.63 + 0.000*cl 0.63 + 0.000*cl 0.63 + 0.000*cl t phz 0.58 0.58 + 0.000*cl 0.58 + 0.000*cl 0.58 + 0.000*cl en to pad t plh 15.39 0.88 + 0.290*cl 1.49 + 0.282*cl 2.68 + 0.268*cl t phl 12.45 0.81 + 0.233*cl 0.81 + 0.233*cl 0.81 + 0.233*cl t r 33.59 0.59 + 0.660*cl 0.60 + 0.660*cl 0.59 + 0.660*cl t f 24.65 0.40 + 0.485*cl 0.40 + 0.485*cl 0.40 + 0.485*cl t plz 0.55 0.55 + 0.000*cl 0.55 + 0.000*cl 0.55 + 0.000*cl t phz 0.50 0.50 + 0.000*cl 0.50 + 0.000*cl 0.50 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pot2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 7.86 0.56 + 0.146*cl 0.55 + 0.146*cl 0.56 + 0.146*cl t phl 6.37 0.55 + 0.116*cl 0.55 + 0.116*cl 0.55 + 0.116*cl t r 16.81 0.31 + 0.330*cl 0.31 + 0.330*cl 0.31 + 0.330*cl t f 12.34 0.21 + 0.243*cl 0.21 + 0.242*cl 0.21 + 0.243*cl tn to pad t plh 7.86 0.55 + 0.146*cl 0.54 + 0.146*cl 0.56 + 0.146*cl t phl 6.39 0.57 + 0.116*cl 0.57 + 0.116*cl 0.57 + 0.116*cl t r 16.81 0.31 + 0.330*cl 0.31 + 0.330*cl 0.31 + 0.330*cl t f 12.34 0.21 + 0.243*cl 0.21 + 0.242*cl 0.21 + 0.243*cl t plz 0.69 0.69 + 0.000*cl 0.69 + 0.000*cl 0.69 + 0.000*cl t phz 0.63 0.63 + 0.000*cl 0.63 + 0.000*cl 0.63 + 0.000*cl en to pad t plh 8.01 0.70 + 0.146*cl 0.71 + 0.146*cl 0.70 + 0.146*cl t phl 6.55 0.73 + 0.116*cl 0.72 + 0.117*cl 0.73 + 0.116*cl t r 16.81 0.31 + 0.330*cl 0.31 + 0.330*cl 0.31 + 0.330*cl t f 12.34 0.21 + 0.243*cl 0.21 + 0.242*cl 0.21 + 0.243*cl t plz 0.61 0.61 + 0.000*cl 0.61 + 0.000*cl 0.61 + 0.000*cl t phz 0.55 0.55 + 0.000*cl 0.55 + 0.000*cl 0.55 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-66 sec asic pvotyz tri-state output buffers kg80 pot4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.25 0.56 + 0.094*cl 0.56 + 0.094*cl 0.56 + 0.094*cl t phl 4.25 0.54 + 0.074*cl 0.54 + 0.074*cl 0.55 + 0.074*cl t r 10.81 0.21 + 0.212*cl 0.21 + 0.212*cl 0.21 + 0.212*cl t f 7.88 0.14 + 0.155*cl 0.15 + 0.155*cl 0.14 + 0.155*cl tn to pad t plh 5.24 0.55 + 0.094*cl 0.55 + 0.094*cl 0.55 + 0.094*cl t phl 4.27 0.56 + 0.074*cl 0.56 + 0.074*cl 0.57 + 0.074*cl t r 10.81 0.21 + 0.212*cl 0.21 + 0.212*cl 0.21 + 0.212*cl t f 7.88 0.14 + 0.155*cl 0.15 + 0.155*cl 0.14 + 0.155*cl t plz 0.75 0.75 + 0.000*cl 0.75 + 0.000*cl 0.75 + 0.000*cl t phz 0.68 0.68 + 0.000*cl 0.68 + 0.000*cl 0.68 + 0.000*cl en to pad t plh 5.39 0.70 + 0.094*cl 0.70 + 0.094*cl 0.70 + 0.094*cl t phl 4.43 0.72 + 0.074*cl 0.71 + 0.074*cl 0.72 + 0.074*cl t r 10.81 0.21 + 0.212*cl 0.21 + 0.212*cl 0.21 + 0.212*cl t f 7.88 0.14 + 0.155*cl 0.15 + 0.155*cl 0.14 + 0.155*cl t plz 0.67 0.67 + 0.000*cl 0.67 + 0.000*cl 0.67 + 0.000*cl t phz 0.60 0.60 + 0.000*cl 0.60 + 0.000*cl 0.60 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pot8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.96 0.62 + 0.047*cl 0.62 + 0.047*cl 0.62 + 0.047*cl t phl 2.45 0.60 + 0.037*cl 0.60 + 0.037*cl 0.60 + 0.037*cl t r 5.43 0.13 + 0.106*cl 0.13 + 0.106*cl 0.13 + 0.106*cl t f 3.96 0.10 + 0.077*cl 0.09 + 0.077*cl 0.09 + 0.077*cl tn to pad t plh 2.95 0.61 + 0.047*cl 0.61 + 0.047*cl 0.61 + 0.047*cl t phl 2.47 0.62 + 0.037*cl 0.61 + 0.037*cl 0.62 + 0.037*cl t r 5.43 0.13 + 0.106*cl 0.13 + 0.106*cl 0.13 + 0.106*cl t f 3.96 0.10 + 0.077*cl 0.09 + 0.077*cl 0.09 + 0.077*cl t plz 0.92 0.92 + 0.000*cl 0.92 + 0.000*cl 0.92 + 0.000*cl t phz 0.82 0.82 + 0.000*cl 0.82 + 0.000*cl 0.82 + 0.000*cl en to pad t plh 3.11 0.76 + 0.047*cl 0.76 + 0.047*cl 0.76 + 0.047*cl t phl 2.63 0.77 + 0.037*cl 0.77 + 0.037*cl 0.77 + 0.037*cl t r 5.43 0.13 + 0.106*cl 0.13 + 0.106*cl 0.13 + 0.106*cl t f 3.96 0.10 + 0.077*cl 0.09 + 0.077*cl 0.09 + 0.077*cl t plz 0.84 0.84 + 0.000*cl 0.83 + 0.000*cl 0.84 + 0.000*cl t phz 0.74 0.74 + 0.000*cl 0.74 + 0.000*cl 0.74 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-67 kg80/KGM80 pvotyz tri-state output buffers kg80 pot12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.41 0.68 + 0.035*cl 0.68 + 0.035*cl 0.68 + 0.035*cl t phl 2.02 0.66 + 0.027*cl 0.66 + 0.027*cl 0.66 + 0.027*cl t r 4.02 0.12 + 0.078*cl 0.12 + 0.078*cl 0.11 + 0.078*cl t f 2.93 0.11 + 0.056*cl 0.10 + 0.057*cl 0.09 + 0.057*cl tn to pad t plh 2.39 0.66 + 0.035*cl 0.67 + 0.035*cl 0.66 + 0.035*cl t phl 2.03 0.67 + 0.027*cl 0.67 + 0.027*cl 0.67 + 0.027*cl t r 4.02 0.12 + 0.078*cl 0.12 + 0.078*cl 0.11 + 0.078*cl t f 2.93 0.11 + 0.056*cl 0.10 + 0.057*cl 0.09 + 0.057*cl t plz 1.04 1.04 + 0.000*cl 1.04 + 0.000*cl 1.04 + 0.000*cl t phz 0.93 0.93 + 0.000*cl 0.93 + 0.000*cl 0.93 + 0.000*cl en to pad t plh 2.54 0.82 + 0.035*cl 0.81 + 0.035*cl 0.82 + 0.035*cl t phl 2.19 0.82 + 0.027*cl 0.83 + 0.027*cl 0.83 + 0.027*cl t r 4.02 0.12 + 0.078*cl 0.12 + 0.078*cl 0.11 + 0.078*cl t f 2.93 0.11 + 0.056*cl 0.10 + 0.057*cl 0.09 + 0.057*cl t plz 0.96 0.96 + 0.000*cl 0.96 + 0.000*cl 0.96 + 0.000*cl t phz 0.85 0.85 + 0.000*cl 0.85 + 0.000*cl 0.84 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pot16 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.03 0.78 + 0.025*cl 0.77 + 0.025*cl 0.77 + 0.025*cl t phl 1.74 0.75 + 0.020*cl 0.74 + 0.020*cl 0.74 + 0.020*cl t r 2.97 0.13 + 0.057*cl 0.13 + 0.057*cl 0.12 + 0.057*cl t f 2.19 0.14 + 0.041*cl 0.13 + 0.041*cl 0.12 + 0.041*cl tn to pad t plh 2.01 0.75 + 0.025*cl 0.74 + 0.025*cl 0.75 + 0.025*cl t phl 1.75 0.75 + 0.020*cl 0.75 + 0.020*cl 0.75 + 0.020*cl t r 2.97 0.14 + 0.057*cl 0.12 + 0.057*cl 0.12 + 0.057*cl t f 2.19 0.14 + 0.041*cl 0.13 + 0.041*cl 0.12 + 0.041*cl t plz 1.20 1.20 + 0.000*cl 1.20 + 0.000*cl 1.20 + 0.000*cl t phz 1.07 1.07 + 0.000*cl 1.07 + 0.000*cl 1.07 + 0.000*cl en to pad t plh 2.16 0.90 + 0.025*cl 0.91 + 0.025*cl 0.90 + 0.025*cl t phl 1.90 0.91 + 0.020*cl 0.90 + 0.020*cl 0.91 + 0.020*cl t r 2.97 0.14 + 0.057*cl 0.13 + 0.057*cl 0.12 + 0.057*cl t f 2.19 0.14 + 0.041*cl 0.13 + 0.041*cl 0.12 + 0.041*cl t plz 1.12 1.12 + 0.000*cl 1.11 + 0.000*cl 1.12 + 0.000*cl t phz 0.99 0.99 + 0.000*cl 0.99 + 0.000*cl 0.99 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-68 sec asic pvotyz tri-state output buffers kg80 pot20 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.66 0.67 + 0.020*cl 0.67 + 0.020*cl 0.66 + 0.020*cl t phl 1.51 0.72 + 0.016*cl 0.73 + 0.016*cl 0.72 + 0.016*cl t r 2.33 0.09 + 0.045*cl 0.09 + 0.045*cl 0.08 + 0.045*cl t f 1.74 0.13 + 0.032*cl 0.11 + 0.032*cl 0.11 + 0.032*cl tn to pad t plh 1.65 0.65 + 0.020*cl 0.65 + 0.020*cl 0.65 + 0.020*cl t phl 1.52 0.73 + 0.016*cl 0.74 + 0.016*cl 0.73 + 0.016*cl t r 2.33 0.10 + 0.045*cl 0.09 + 0.045*cl 0.08 + 0.045*cl t f 1.74 0.13 + 0.032*cl 0.12 + 0.032*cl 0.11 + 0.032*cl t plz 1.01 1.01 + 0.000*cl 1.01 + 0.000*cl 1.01 + 0.000*cl t phz 0.98 0.98 + 0.000*cl 0.98 + 0.000*cl 0.98 + 0.000*cl en to pad t plh 1.80 0.81 + 0.020*cl 0.81 + 0.020*cl 0.81 + 0.020*cl t phl 1.67 0.88 + 0.016*cl 0.89 + 0.016*cl 0.89 + 0.016*cl t r 2.33 0.10 + 0.045*cl 0.09 + 0.045*cl 0.08 + 0.045*cl t f 1.74 0.13 + 0.032*cl 0.12 + 0.032*cl 0.11 + 0.032*cl t plz 0.93 0.93 + 0.000*cl 0.93 + 0.000*cl 0.93 + 0.000*cl t phz 0.90 0.90 + 0.000*cl 0.90 + 0.000*cl 0.90 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pot24 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.59 0.72 + 0.017*cl 0.72 + 0.018*cl 0.72 + 0.018*cl t phl 1.45 0.75 + 0.014*cl 0.76 + 0.014*cl 0.75 + 0.014*cl t r 2.07 0.11 + 0.039*cl 0.09 + 0.039*cl 0.09 + 0.039*cl t f 1.56 0.15 + 0.028*cl 0.13 + 0.028*cl 0.13 + 0.028*cl tn to pad t plh 1.58 0.70 + 0.018*cl 0.71 + 0.017*cl 0.70 + 0.018*cl t phl 1.46 0.76 + 0.014*cl 0.77 + 0.014*cl 0.77 + 0.014*cl t r 2.07 0.11 + 0.039*cl 0.09 + 0.039*cl 0.09 + 0.039*cl t f 1.56 0.15 + 0.028*cl 0.14 + 0.028*cl 0.13 + 0.028*cl t plz 1.07 1.07 + 0.000*cl 1.06 + 0.000*cl 1.07 + 0.000*cl t phz 0.97 0.97 + 0.000*cl 0.97 + 0.000*cl 0.96 + 0.000*cl en to pad t plh 1.73 0.86 + 0.018*cl 0.86 + 0.018*cl 0.86 + 0.018*cl t phl 1.62 0.92 + 0.014*cl 0.92 + 0.014*cl 0.93 + 0.014*cl t r 2.07 0.11 + 0.039*cl 0.09 + 0.039*cl 0.09 + 0.039*cl t f 1.56 0.15 + 0.028*cl 0.14 + 0.028*cl 0.13 + 0.028*cl t plz 0.99 0.99 + 0.000*cl 0.99 + 0.000*cl 0.99 + 0.000*cl t phz 0.89 0.89 + 0.000*cl 0.89 + 0.000*cl 0.89 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-69 kg80/KGM80 pvotyz tri-state output buffers kg80 pot12sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.17 1.39 + 0.036*cl 1.41 + 0.035*cl 1.42 + 0.035*cl t phl 3.66 2.06 + 0.032*cl 2.17 + 0.030*cl 2.23 + 0.030*cl t r 4.34 0.49 + 0.077*cl 0.44 + 0.078*cl 0.43 + 0.078*cl t f 3.73 0.96 + 0.055*cl 0.97 + 0.055*cl 0.98 + 0.055*cl tn to pad t plh 3.12 1.34 + 0.036*cl 1.37 + 0.035*cl 1.37 + 0.035*cl t phl 3.67 2.07 + 0.032*cl 2.18 + 0.031*cl 2.24 + 0.030*cl t r 4.34 0.49 + 0.077*cl 0.44 + 0.078*cl 0.43 + 0.078*cl t f 3.74 0.98 + 0.055*cl 0.98 + 0.055*cl 0.98 + 0.055*cl t plz 1.30 1.30 + 0.000*cl 1.30 + 0.000*cl 1.30 + 0.000*cl t phz 1.09 1.09 + 0.000*cl 1.09 + 0.000*cl 1.09 + 0.000*cl en to pad t plh 3.28 1.50 + 0.036*cl 1.53 + 0.035*cl 1.53 + 0.035*cl t phl 3.82 2.22 + 0.032*cl 2.34 + 0.031*cl 2.39 + 0.030*cl t r 4.34 0.49 + 0.077*cl 0.44 + 0.078*cl 0.43 + 0.078*cl t f 3.74 0.98 + 0.055*cl 0.98 + 0.055*cl 0.98 + 0.055*cl t plz 1.22 1.22 + 0.000*cl 1.22 + 0.000*cl 1.22 + 0.000*cl t phz 1.01 1.01 + 0.000*cl 1.01 + 0.000*cl 1.01 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pot16sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.97 1.61 + 0.027*cl 1.68 + 0.026*cl 1.70 + 0.026*cl t phl 3.36 2.11 + 0.025*cl 2.21 + 0.024*cl 2.28 + 0.023*cl t r 3.43 0.70 + 0.055*cl 0.68 + 0.055*cl 0.66 + 0.055*cl t f 3.00 0.95 + 0.041*cl 1.01 + 0.040*cl 1.02 + 0.040*cl tn to pad t plh 2.92 1.56 + 0.027*cl 1.63 + 0.026*cl 1.65 + 0.026*cl t phl 3.35 2.07 + 0.025*cl 2.21 + 0.024*cl 2.26 + 0.023*cl t r 3.43 0.71 + 0.055*cl 0.68 + 0.055*cl 0.66 + 0.055*cl t f 3.03 1.01 + 0.040*cl 1.05 + 0.040*cl 1.06 + 0.040*cl t plz 1.27 1.27 + 0.000*cl 1.27 + 0.000*cl 1.27 + 0.000*cl t phz 1.09 1.09 + 0.000*cl 1.09 + 0.000*cl 1.09 + 0.000*cl en to pad t plh 3.07 1.72 + 0.027*cl 1.78 + 0.026*cl 1.80 + 0.026*cl t phl 3.50 2.23 + 0.025*cl 2.36 + 0.024*cl 2.42 + 0.023*cl t r 3.43 0.71 + 0.055*cl 0.68 + 0.055*cl 0.66 + 0.055*cl t f 3.03 1.01 + 0.040*cl 1.05 + 0.040*cl 1.06 + 0.040*cl t plz 1.19 1.19 + 0.000*cl 1.19 + 0.000*cl 1.19 + 0.000*cl t phz 1.01 1.01 + 0.000*cl 1.01 + 0.000*cl 1.01 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-70 sec asic pvotyz tri-state output buffers kg80 pot20sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.36 1.30 + 0.021*cl 1.35 + 0.021*cl 1.36 + 0.020*cl t phl 2.38 1.52 + 0.017*cl 1.55 + 0.017*cl 1.57 + 0.017*cl t r 2.71 0.57 + 0.043*cl 0.55 + 0.043*cl 0.53 + 0.043*cl t f 2.23 0.71 + 0.030*cl 0.69 + 0.031*cl 0.68 + 0.031*cl tn to pad t plh 2.31 1.25 + 0.021*cl 1.29 + 0.021*cl 1.32 + 0.020*cl t phl 2.29 1.35 + 0.019*cl 1.43 + 0.018*cl 1.47 + 0.017*cl t r 2.72 0.59 + 0.043*cl 0.55 + 0.043*cl 0.54 + 0.043*cl t f 2.22 0.67 + 0.031*cl 0.68 + 0.031*cl 0.67 + 0.031*cl t plz 0.71 0.71 + 0.000*cl 0.71 + 0.000*cl 0.71 + 0.000*cl t phz 0.91 0.91 + 0.000*cl 0.91 + 0.000*cl 0.91 + 0.000*cl en to pad t plh 2.47 1.41 + 0.021*cl 1.46 + 0.021*cl 1.47 + 0.020*cl t phl 2.44 1.51 + 0.019*cl 1.58 + 0.018*cl 1.63 + 0.017*cl t r 2.72 0.59 + 0.043*cl 0.55 + 0.043*cl 0.54 + 0.043*cl t f 2.22 0.67 + 0.031*cl 0.68 + 0.031*cl 0.67 + 0.031*cl t plz 0.62 0.62 + 0.000*cl 0.62 + 0.000*cl 0.62 + 0.000*cl t phz 0.83 0.83 + 0.000*cl 0.83 + 0.000*cl 0.83 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pot24sh switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.35 1.38 + 0.019*cl 1.44 + 0.019*cl 1.47 + 0.018*cl t phl 2.45 1.66 + 0.016*cl 1.69 + 0.015*cl 1.72 + 0.015*cl t r 2.53 0.65 + 0.038*cl 0.64 + 0.038*cl 0.63 + 0.038*cl t f 2.15 0.82 + 0.027*cl 0.81 + 0.027*cl 0.79 + 0.027*cl tn to pad t plh 2.30 1.33 + 0.020*cl 1.39 + 0.019*cl 1.42 + 0.018*cl t phl 2.30 1.42 + 0.018*cl 1.52 + 0.016*cl 1.55 + 0.016*cl t r 2.55 0.68 + 0.037*cl 0.66 + 0.038*cl 0.64 + 0.038*cl t f 2.12 0.74 + 0.028*cl 0.77 + 0.027*cl 0.76 + 0.027*cl t plz 0.71 0.71 + 0.000*cl 0.71 + 0.000*cl 0.70 + 0.000*cl t phz 0.91 0.91 + 0.000*cl 0.91 + 0.000*cl 0.91 + 0.000*cl en to pad t plh 2.46 1.48 + 0.020*cl 1.54 + 0.019*cl 1.58 + 0.018*cl t phl 2.46 1.57 + 0.018*cl 1.67 + 0.016*cl 1.71 + 0.016*cl t r 2.55 0.68 + 0.037*cl 0.66 + 0.037*cl 0.64 + 0.038*cl t f 2.12 0.74 + 0.028*cl 0.77 + 0.027*cl 0.76 + 0.027*cl t plz 0.62 0.62 + 0.000*cl 0.63 + 0.000*cl 0.63 + 0.000*cl t phz 0.83 0.83 + 0.000*cl 0.83 + 0.000*cl 0.83 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-71 kg80/KGM80 pvotyz tri-state output buffers kg80 pot4sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.59 0.90 + 0.094*cl 0.90 + 0.094*cl 0.90 + 0.094*cl t phl 5.18 1.45 + 0.074*cl 1.46 + 0.074*cl 1.47 + 0.074*cl t r 10.83 0.24 + 0.212*cl 0.24 + 0.212*cl 0.23 + 0.212*cl t f 8.06 0.42 + 0.153*cl 0.38 + 0.153*cl 0.35 + 0.154*cl tn to pad t plh 5.55 0.85 + 0.094*cl 0.86 + 0.094*cl 0.86 + 0.094*cl t phl 5.19 1.47 + 0.074*cl 1.48 + 0.074*cl 1.49 + 0.074*cl t r 10.83 0.24 + 0.212*cl 0.24 + 0.212*cl 0.23 + 0.212*cl t f 8.06 0.42 + 0.153*cl 0.38 + 0.153*cl 0.35 + 0.154*cl t plz 1.33 1.33 + 0.000*cl 1.33 + 0.000*cl 1.33 + 0.000*cl t phz 1.10 1.10 + 0.000*cl 1.10 + 0.000*cl 1.10 + 0.000*cl en to pad t plh 5.70 1.01 + 0.094*cl 1.01 + 0.094*cl 1.01 + 0.094*cl t phl 5.35 1.63 + 0.074*cl 1.64 + 0.074*cl 1.64 + 0.074*cl t r 10.83 0.24 + 0.212*cl 0.24 + 0.212*cl 0.23 + 0.212*cl t f 8.06 0.42 + 0.153*cl 0.38 + 0.153*cl 0.35 + 0.154*cl t plz 1.25 1.25 + 0.000*cl 1.25 + 0.000*cl 1.25 + 0.000*cl t phz 1.01 1.01 + 0.000*cl 1.01 + 0.000*cl 1.01 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pot8sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.55 1.20 + 0.047*cl 1.20 + 0.047*cl 1.21 + 0.047*cl t phl 3.79 1.83 + 0.039*cl 1.89 + 0.038*cl 1.93 + 0.038*cl t r 5.57 0.34 + 0.105*cl 0.31 + 0.105*cl 0.28 + 0.105*cl t f 4.46 0.74 + 0.074*cl 0.72 + 0.075*cl 0.69 + 0.075*cl tn to pad t plh 3.51 1.16 + 0.047*cl 1.16 + 0.047*cl 1.16 + 0.047*cl t phl 3.80 1.84 + 0.039*cl 1.91 + 0.038*cl 1.94 + 0.038*cl t r 5.57 0.34 + 0.105*cl 0.31 + 0.105*cl 0.28 + 0.105*cl t f 4.47 0.74 + 0.074*cl 0.72 + 0.075*cl 0.70 + 0.075*cl t plz 1.30 1.30 + 0.000*cl 1.30 + 0.000*cl 1.30 + 0.000*cl t phz 1.09 1.09 + 0.000*cl 1.09 + 0.000*cl 1.09 + 0.000*cl en to pad t plh 3.66 1.31 + 0.047*cl 1.31 + 0.047*cl 1.32 + 0.047*cl t phl 3.96 1.99 + 0.039*cl 2.07 + 0.038*cl 2.10 + 0.038*cl t r 5.57 0.34 + 0.105*cl 0.31 + 0.105*cl 0.28 + 0.105*cl t f 4.47 0.74 + 0.074*cl 0.72 + 0.075*cl 0.70 + 0.075*cl t plz 1.22 1.22 + 0.000*cl 1.22 + 0.000*cl 1.22 + 0.000*cl t phz 1.01 1.01 + 0.000*cl 1.01 + 0.000*cl 1.01 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-72 sec asic pvotyz tri-state output buffers kg80 pot12sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.98 1.24 + 0.035*cl 1.25 + 0.035*cl 1.26 + 0.035*cl t phl 3.29 1.75 + 0.031*cl 1.85 + 0.029*cl 1.89 + 0.029*cl t r 4.22 0.41 + 0.076*cl 0.37 + 0.077*cl 0.35 + 0.077*cl t f 3.55 0.81 + 0.055*cl 0.82 + 0.055*cl 0.82 + 0.055*cl tn to pad t plh 2.93 1.19 + 0.035*cl 1.20 + 0.035*cl 1.21 + 0.035*cl t phl 3.30 1.76 + 0.031*cl 1.86 + 0.030*cl 1.91 + 0.029*cl t r 4.22 0.41 + 0.076*cl 0.37 + 0.077*cl 0.36 + 0.077*cl t f 3.55 0.82 + 0.055*cl 0.83 + 0.055*cl 0.82 + 0.055*cl t plz 1.54 1.54 + 0.000*cl 1.54 + 0.000*cl 1.54 + 0.000*cl t phz 1.39 1.39 + 0.000*cl 1.39 + 0.000*cl 1.38 + 0.000*cl en to pad t plh 3.09 1.34 + 0.035*cl 1.36 + 0.035*cl 1.36 + 0.035*cl t phl 3.46 1.92 + 0.031*cl 2.02 + 0.030*cl 2.06 + 0.029*cl t r 4.22 0.41 + 0.076*cl 0.37 + 0.077*cl 0.36 + 0.077*cl t f 3.55 0.82 + 0.055*cl 0.83 + 0.055*cl 0.82 + 0.055*cl t plz 1.46 1.45 + 0.000*cl 1.45 + 0.000*cl 1.45 + 0.000*cl t phz 1.31 1.30 + 0.000*cl 1.31 + 0.000*cl 1.31 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pot16sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.66 1.34 + 0.026*cl 1.38 + 0.026*cl 1.40 + 0.026*cl t phl 2.86 1.68 + 0.024*cl 1.76 + 0.022*cl 1.81 + 0.022*cl t r 3.28 0.53 + 0.055*cl 0.51 + 0.055*cl 0.49 + 0.056*cl t f 2.77 0.73 + 0.041*cl 0.77 + 0.040*cl 0.78 + 0.040*cl tn to pad t plh 2.61 1.29 + 0.026*cl 1.33 + 0.026*cl 1.34 + 0.026*cl t phl 2.86 1.66 + 0.024*cl 1.76 + 0.023*cl 1.80 + 0.022*cl t r 3.29 0.54 + 0.055*cl 0.51 + 0.055*cl 0.49 + 0.056*cl t f 2.79 0.76 + 0.040*cl 0.79 + 0.040*cl 0.80 + 0.040*cl t plz 1.72 1.72 + 0.000*cl 1.71 + 0.000*cl 1.72 + 0.000*cl t phz 1.65 1.65 + 0.000*cl 1.64 + 0.000*cl 1.65 + 0.000*cl en to pad t plh 2.76 1.44 + 0.026*cl 1.49 + 0.026*cl 1.50 + 0.026*cl t phl 3.02 1.82 + 0.024*cl 1.91 + 0.023*cl 1.97 + 0.022*cl t r 3.29 0.54 + 0.055*cl 0.51 + 0.055*cl 0.49 + 0.056*cl t f 2.79 0.76 + 0.040*cl 0.79 + 0.040*cl 0.80 + 0.040*cl t plz 1.64 1.64 + 0.000*cl 1.64 + 0.000*cl 1.63 + 0.000*cl t phz 1.57 1.57 + 0.000*cl 1.57 + 0.000*cl 1.56 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-73 kg80/KGM80 pvotyz tri-state output buffers kg80 pot20sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.03 1.02 + 0.020*cl 1.04 + 0.020*cl 1.04 + 0.020*cl t phl 2.01 1.13 + 0.018*cl 1.18 + 0.017*cl 1.21 + 0.017*cl t r 2.53 0.36 + 0.043*cl 0.33 + 0.044*cl 0.32 + 0.044*cl t f 2.11 0.54 + 0.031*cl 0.55 + 0.031*cl 0.54 + 0.031*cl tn to pad t plh 2.00 0.99 + 0.020*cl 1.01 + 0.020*cl 1.01 + 0.020*cl t phl 2.01 1.11 + 0.018*cl 1.17 + 0.017*cl 1.21 + 0.017*cl t r 2.53 0.37 + 0.043*cl 0.34 + 0.044*cl 0.32 + 0.044*cl t f 2.12 0.57 + 0.031*cl 0.57 + 0.031*cl 0.57 + 0.031*cl t plz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl t phz 0.79 0.79 + 0.000*cl 0.79 + 0.000*cl 0.78 + 0.000*cl en to pad t plh 2.16 1.14 + 0.020*cl 1.16 + 0.020*cl 1.17 + 0.020*cl t phl 2.17 1.27 + 0.018*cl 1.33 + 0.017*cl 1.37 + 0.017*cl t r 2.53 0.37 + 0.043*cl 0.34 + 0.044*cl 0.32 + 0.044*cl t f 2.12 0.57 + 0.031*cl 0.57 + 0.031*cl 0.57 + 0.031*cl t plz 0.79 0.79 + 0.000*cl 0.78 + 0.000*cl 0.79 + 0.000*cl t phz 0.71 0.71 + 0.000*cl 0.71 + 0.000*cl 0.71 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 pot24sm switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.01 1.10 + 0.018*cl 1.12 + 0.018*cl 1.14 + 0.018*cl t phl 2.04 1.21 + 0.017*cl 1.27 + 0.016*cl 1.31 + 0.015*cl t r 2.33 0.44 + 0.038*cl 0.42 + 0.038*cl 0.40 + 0.038*cl t f 2.01 0.62 + 0.028*cl 0.64 + 0.028*cl 0.64 + 0.027*cl tn to pad t plh 1.98 1.06 + 0.018*cl 1.10 + 0.018*cl 1.10 + 0.018*cl t phl 2.03 1.17 + 0.017*cl 1.25 + 0.016*cl 1.29 + 0.016*cl t r 2.34 0.46 + 0.038*cl 0.43 + 0.038*cl 0.41 + 0.038*cl t f 2.04 0.66 + 0.027*cl 0.67 + 0.027*cl 0.68 + 0.027*cl t plz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl t phz 0.79 0.79 + 0.000*cl 0.79 + 0.000*cl 0.79 + 0.000*cl en to pad t plh 2.13 1.21 + 0.018*cl 1.25 + 0.018*cl 1.26 + 0.018*cl t phl 2.18 1.33 + 0.017*cl 1.41 + 0.016*cl 1.45 + 0.016*cl t r 2.34 0.46 + 0.038*cl 0.43 + 0.038*cl 0.41 + 0.038*cl t f 2.04 0.66 + 0.027*cl 0.67 + 0.027*cl 0.68 + 0.027*cl t plz 0.79 0.79 + 0.000*cl 0.79 + 0.000*cl 0.79 + 0.000*cl t phz 0.71 0.71 + 0.000*cl 0.71 + 0.000*cl 0.71 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-74 sec asic pvotyz tri-state output buffers kg80 plot1 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 21.62 1.17 + 0.409*cl 1.17 + 0.409*cl 1.17 + 0.409*cl t phl 14.16 0.96 + 0.264*cl 0.96 + 0.264*cl 0.96 + 0.264*cl t r 47.48 0.91 + 0.931*cl 0.91 + 0.931*cl 0.91 + 0.931*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl tn to pad t plh 21.41 1.49 + 0.398*cl 3.49 + 0.372*cl 6.57 + 0.335*cl t phl 14.16 0.96 + 0.264*cl 0.96 + 0.264*cl 0.96 + 0.264*cl t r 47.48 0.91 + 0.931*cl 0.91 + 0.931*cl 0.91 + 0.931*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl t plz 1.04 1.04 + 0.000*cl 1.04 + 0.000*cl 1.04 + 0.000*cl t phz 0.98 0.98 + 0.000*cl 0.98 + 0.000*cl 0.98 + 0.000*cl en to pad t plh 21.52 1.61 + 0.398*cl 3.63 + 0.371*cl 6.73 + 0.335*cl t phl 14.29 1.09 + 0.264*cl 1.08 + 0.264*cl 1.08 + 0.264*cl t r 47.48 0.91 + 0.931*cl 0.91 + 0.931*cl 0.91 + 0.931*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl t plz 0.98 0.93 + 0.001*cl 1.00 + 0.000*cl 1.00 + 0.000*cl t phz 0.93 0.93 + 0.000*cl 0.93 + 0.000*cl 0.93 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plot2 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 10.70 1.05 + 0.193*cl 1.05 + 0.193*cl 1.05 + 0.193*cl t phl 7.04 0.87 + 0.124*cl 0.87 + 0.124*cl 0.87 + 0.124*cl t r 22.42 0.45 + 0.439*cl 0.45 + 0.439*cl 0.45 + 0.439*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl tn to pad t plh 10.50 0.85 + 0.193*cl 0.85 + 0.193*cl 0.87 + 0.193*cl t phl 7.05 0.87 + 0.124*cl 0.87 + 0.124*cl 0.87 + 0.124*cl t r 22.42 0.45 + 0.439*cl 0.45 + 0.439*cl 0.45 + 0.439*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl t plz 1.13 1.13 + 0.000*cl 1.13 + 0.000*cl 1.13 + 0.000*cl t phz 1.06 1.06 + 0.000*cl 1.05 + 0.000*cl 1.06 + 0.000*cl en to pad t plh 10.63 1.02 + 0.192*cl 0.84 + 0.195*cl 1.10 + 0.192*cl t phl 7.17 1.00 + 0.124*cl 1.00 + 0.124*cl 0.99 + 0.124*cl t r 22.42 0.45 + 0.439*cl 0.45 + 0.439*cl 0.45 + 0.439*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl t plz 1.06 1.06 + 0.000*cl 1.06 + 0.000*cl 1.06 + 0.000*cl t phz 1.02 1.05 + -0.001*cl 0.88 + 0.002*cl 1.02 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-75 kg80/KGM80 pvotyz tri-state output buffers kg80 plot4 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.81 0.98 + 0.096*cl 0.98 + 0.097*cl 0.98 + 0.096*cl t phl 4.00 0.92 + 0.062*cl 0.91 + 0.062*cl 0.91 + 0.062*cl t r 11.24 0.25 + 0.220*cl 0.25 + 0.220*cl 0.25 + 0.220*cl t f 6.81 0.16 + 0.133*cl 0.16 + 0.133*cl 0.15 + 0.133*cl tn to pad t plh 5.60 0.78 + 0.096*cl 0.78 + 0.096*cl 0.78 + 0.096*cl t phl 4.00 0.92 + 0.062*cl 0.91 + 0.062*cl 0.92 + 0.062*cl t r 11.24 0.25 + 0.220*cl 0.25 + 0.220*cl 0.25 + 0.220*cl t f 6.81 0.15 + 0.133*cl 0.16 + 0.133*cl 0.15 + 0.133*cl t plz 1.25 1.25 + 0.000*cl 1.25 + 0.000*cl 1.25 + 0.000*cl t phz 1.70 1.70 + 0.000*cl 1.70 + 0.000*cl 1.70 + 0.000*cl en to pad t plh 5.72 0.90 + 0.096*cl 0.90 + 0.097*cl 0.90 + 0.096*cl t phl 4.14 1.06 + 0.062*cl 1.05 + 0.062*cl 1.06 + 0.062*cl t r 11.24 0.25 + 0.220*cl 0.25 + 0.220*cl 0.25 + 0.220*cl t f 6.81 0.15 + 0.133*cl 0.14 + 0.133*cl 0.16 + 0.133*cl t plz 1.19 1.19 + 0.000*cl 1.14 + 0.001*cl 1.19 + 0.000*cl t phz 1.65 1.65 + 0.000*cl 1.72 + -0.001*cl 1.64 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plot6 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 4.26 1.04 + 0.064*cl 1.04 + 0.064*cl 1.05 + 0.064*cl t phl 3.07 1.02 + 0.041*cl 1.01 + 0.041*cl 1.01 + 0.041*cl t r 7.52 0.20 + 0.146*cl 0.19 + 0.146*cl 0.20 + 0.146*cl t f 4.58 0.17 + 0.088*cl 0.14 + 0.089*cl 0.14 + 0.089*cl tn to pad t plh 4.05 0.84 + 0.064*cl 0.82 + 0.064*cl 0.85 + 0.064*cl t phl 3.05 0.99 + 0.041*cl 0.99 + 0.041*cl 0.99 + 0.041*cl t r 7.52 0.19 + 0.146*cl 0.19 + 0.146*cl 0.20 + 0.146*cl t f 4.57 0.14 + 0.089*cl 0.12 + 0.089*cl 0.13 + 0.089*cl t plz 1.40 1.40 + 0.000*cl 1.54 + -0.002*cl 1.38 + 0.000*cl t phz 2.09 2.09 + 0.000*cl 2.09 + 0.000*cl 2.09 + 0.000*cl en to pad t plh 4.17 0.95 + 0.064*cl 0.94 + 0.064*cl 0.96 + 0.064*cl t phl 3.19 1.13 + 0.041*cl 1.13 + 0.041*cl 1.14 + 0.041*cl t r 7.52 0.19 + 0.146*cl 0.19 + 0.147*cl 0.20 + 0.146*cl t f 4.57 0.14 + 0.089*cl 0.14 + 0.089*cl 0.12 + 0.089*cl t plz 1.35 1.41 + -0.001*cl 1.32 + 0.000*cl 1.32 + 0.000*cl t phz 2.02 2.02 + 0.000*cl 2.02 + 0.000*cl 2.02 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-76 sec asic pvotyz tri-state output buffers kg80 plot8 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.52 1.11 + 0.048*cl 1.11 + 0.048*cl 1.11 + 0.048*cl t phl 2.67 1.15 + 0.030*cl 1.14 + 0.031*cl 1.13 + 0.031*cl t r 5.66 0.18 + 0.110*cl 0.16 + 0.110*cl 0.17 + 0.110*cl t f 3.51 0.24 + 0.065*cl 0.20 + 0.066*cl 0.18 + 0.066*cl tn to pad t plh 3.32 0.90 + 0.048*cl 0.89 + 0.048*cl 0.92 + 0.048*cl t phl 2.62 1.08 + 0.031*cl 1.08 + 0.031*cl 1.08 + 0.031*cl t r 5.66 0.18 + 0.110*cl 0.17 + 0.110*cl 0.16 + 0.110*cl t f 3.47 0.17 + 0.066*cl 0.15 + 0.066*cl 0.14 + 0.066*cl t plz 1.51 1.47 + 0.001*cl 1.68 + -0.002*cl 1.40 + 0.001*cl t phz 2.48 2.47 + 0.000*cl 2.48 + 0.000*cl 2.48 + 0.000*cl en to pad t plh 3.45 1.07 + 0.048*cl 0.89 + 0.050*cl 1.14 + 0.047*cl t phl 2.77 1.22 + 0.031*cl 1.22 + 0.031*cl 1.22 + 0.031*cl t r 5.66 0.18 + 0.110*cl 0.17 + 0.110*cl 0.17 + 0.110*cl t f 3.47 0.17 + 0.066*cl 0.14 + 0.066*cl 0.15 + 0.066*cl t plz 1.45 1.45 + 0.000*cl 1.44 + 0.000*cl 1.31 + 0.002*cl t phz 2.41 2.41 + 0.000*cl 2.41 + 0.000*cl 2.40 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plot10 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.16 1.23 + 0.039*cl 1.23 + 0.039*cl 1.23 + 0.039*cl t phl 2.41 1.18 + 0.025*cl 1.17 + 0.025*cl 1.18 + 0.025*cl t r 4.56 0.18 + 0.088*cl 0.18 + 0.088*cl 0.16 + 0.088*cl t f 2.83 0.21 + 0.052*cl 0.17 + 0.053*cl 0.20 + 0.053*cl tn to pad t plh 2.95 1.01 + 0.039*cl 1.02 + 0.039*cl 0.99 + 0.039*cl t phl 2.40 1.16 + 0.025*cl 1.18 + 0.025*cl 1.17 + 0.025*cl t r 4.56 0.18 + 0.088*cl 0.18 + 0.088*cl 0.16 + 0.088*cl t f 2.84 0.23 + 0.052*cl 0.18 + 0.053*cl 0.20 + 0.053*cl t plz 1.65 1.68 + -0.001*cl 1.55 + 0.001*cl 1.72 + -0.001*cl t phz 1.88 1.88 + 0.000*cl 1.88 + 0.000*cl 1.88 + 0.000*cl en to pad t plh 3.07 1.13 + 0.039*cl 1.14 + 0.039*cl 1.13 + 0.039*cl t phl 2.55 1.31 + 0.025*cl 1.30 + 0.025*cl 1.31 + 0.025*cl t r 4.56 0.19 + 0.088*cl 0.18 + 0.088*cl 0.16 + 0.088*cl t f 2.83 0.21 + 0.052*cl 0.21 + 0.052*cl 0.17 + 0.053*cl t plz 1.57 1.53 + 0.001*cl 1.77 + -0.002*cl 1.57 + 0.000*cl t phz 1.82 1.82 + 0.000*cl 1.82 + 0.000*cl 1.82 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-77 kg80/KGM80 pvotyz tri-state output buffers kg80 plot12 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.95 1.34 + 0.032*cl 1.34 + 0.032*cl 1.34 + 0.032*cl t phl 2.28 1.24 + 0.021*cl 1.25 + 0.021*cl 1.25 + 0.021*cl t r 3.84 0.21 + 0.073*cl 0.20 + 0.073*cl 0.16 + 0.073*cl t f 2.43 0.26 + 0.043*cl 0.26 + 0.043*cl 0.22 + 0.044*cl tn to pad t plh 2.74 1.12 + 0.032*cl 1.13 + 0.032*cl 1.14 + 0.032*cl t phl 2.28 1.24 + 0.021*cl 1.26 + 0.021*cl 1.26 + 0.021*cl t r 3.84 0.21 + 0.073*cl 0.18 + 0.073*cl 0.18 + 0.073*cl t f 2.43 0.27 + 0.043*cl 0.25 + 0.043*cl 0.24 + 0.044*cl t plz 1.76 1.74 + 0.000*cl 1.77 + 0.000*cl 1.76 + 0.000*cl t phz 1.69 1.69 + 0.000*cl 1.69 + 0.000*cl 1.69 + 0.000*cl en to pad t plh 2.86 1.25 + 0.032*cl 1.13 + 0.034*cl 1.36 + 0.031*cl t phl 2.40 1.37 + 0.021*cl 1.37 + 0.021*cl 1.37 + 0.021*cl t r 3.84 0.20 + 0.073*cl 0.19 + 0.073*cl 0.18 + 0.073*cl t f 2.43 0.26 + 0.043*cl 0.26 + 0.043*cl 0.22 + 0.044*cl t plz 1.73 1.72 + 0.000*cl 1.72 + 0.000*cl 1.85 + -0.002*cl t phz 1.63 1.63 + 0.000*cl 1.63 + 0.000*cl 1.63 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plot16 switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.71 1.49 + 0.024*cl 1.49 + 0.024*cl 1.49 + 0.024*cl t phl 2.20 1.38 + 0.016*cl 1.40 + 0.016*cl 1.41 + 0.016*cl t r 3.00 0.26 + 0.055*cl 0.24 + 0.055*cl 0.23 + 0.055*cl t f 1.98 0.36 + 0.032*cl 0.38 + 0.032*cl 0.31 + 0.033*cl tn to pad t plh 2.49 1.26 + 0.025*cl 1.26 + 0.025*cl 1.26 + 0.025*cl t phl 2.19 1.37 + 0.016*cl 1.40 + 0.016*cl 1.40 + 0.016*cl t r 3.01 0.27 + 0.055*cl 0.27 + 0.055*cl 0.23 + 0.055*cl t f 1.99 0.36 + 0.032*cl 0.38 + 0.032*cl 0.35 + 0.033*cl t plz 2.01 1.99 + 0.000*cl 2.00 + 0.000*cl 2.00 + 0.000*cl t phz 1.94 1.93 + 0.000*cl 1.93 + 0.000*cl 1.93 + 0.000*cl en to pad t plh 2.61 1.38 + 0.025*cl 1.38 + 0.025*cl 1.39 + 0.025*cl t phl 2.31 1.49 + 0.016*cl 1.52 + 0.016*cl 1.53 + 0.016*cl t r 3.01 0.28 + 0.055*cl 0.23 + 0.055*cl 0.23 + 0.055*cl t f 1.99 0.37 + 0.032*cl 0.32 + 0.033*cl 0.35 + 0.033*cl t plz 1.96 1.99 + -0.001*cl 1.94 + 0.000*cl 1.81 + 0.002*cl t phz 1.88 1.87 + 0.000*cl 1.87 + 0.000*cl 1.87 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-78 sec asic pvotyz tri-state output buffers kg80 plot4sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 6.25 1.28 + 0.099*cl 1.28 + 0.099*cl 1.28 + 0.099*cl t phl 4.52 1.33 + 0.064*cl 1.33 + 0.064*cl 1.33 + 0.064*cl t r 11.58 0.27 + 0.226*cl 0.27 + 0.226*cl 0.28 + 0.226*cl t f 7.10 0.27 + 0.137*cl 0.23 + 0.137*cl 0.22 + 0.137*cl tn to pad t plh 6.03 1.06 + 0.099*cl 1.06 + 0.099*cl 1.06 + 0.099*cl t phl 4.53 1.34 + 0.064*cl 1.34 + 0.064*cl 1.34 + 0.064*cl t r 11.58 0.28 + 0.226*cl 0.27 + 0.226*cl 0.27 + 0.226*cl t f 7.10 0.27 + 0.137*cl 0.23 + 0.137*cl 0.23 + 0.137*cl t plz 1.19 1.16 + 0.001*cl 1.20 + 0.000*cl 1.20 + 0.000*cl t phz 1.09 1.09 + 0.000*cl 1.09 + 0.000*cl 1.09 + 0.000*cl en to pad t plh 6.15 1.18 + 0.099*cl 1.18 + 0.099*cl 1.18 + 0.099*cl t phl 4.67 1.48 + 0.064*cl 1.47 + 0.064*cl 1.48 + 0.064*cl t r 11.58 0.27 + 0.226*cl 0.27 + 0.226*cl 0.28 + 0.226*cl t f 7.10 0.26 + 0.137*cl 0.23 + 0.137*cl 0.22 + 0.137*cl t plz 1.15 1.20 + -0.001*cl 1.12 + 0.000*cl 1.12 + 0.000*cl t phz 1.03 1.03 + 0.000*cl 1.03 + 0.000*cl 1.03 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plot6sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 4.76 1.48 + 0.066*cl 1.48 + 0.066*cl 1.48 + 0.066*cl t phl 3.76 1.65 + 0.042*cl 1.66 + 0.042*cl 1.67 + 0.042*cl t r 7.71 0.26 + 0.149*cl 0.24 + 0.149*cl 0.24 + 0.149*cl t f 4.88 0.46 + 0.088*cl 0.41 + 0.089*cl 0.37 + 0.089*cl tn to pad t plh 4.53 1.25 + 0.066*cl 1.25 + 0.066*cl 1.25 + 0.066*cl t phl 3.77 1.65 + 0.042*cl 1.66 + 0.042*cl 1.68 + 0.042*cl t r 7.71 0.26 + 0.149*cl 0.25 + 0.149*cl 0.24 + 0.149*cl t f 4.88 0.47 + 0.088*cl 0.41 + 0.089*cl 0.39 + 0.089*cl t plz 1.14 1.14 + 0.000*cl 1.14 + 0.000*cl 1.14 + 0.000*cl t phz 1.06 1.06 + 0.000*cl 1.06 + 0.000*cl 1.06 + 0.000*cl en to pad t plh 4.65 1.37 + 0.066*cl 1.37 + 0.066*cl 1.37 + 0.066*cl t phl 3.89 1.78 + 0.042*cl 1.78 + 0.042*cl 1.79 + 0.042*cl t r 7.71 0.27 + 0.149*cl 0.24 + 0.149*cl 0.24 + 0.149*cl t f 4.88 0.46 + 0.088*cl 0.40 + 0.089*cl 0.39 + 0.089*cl t plz 1.09 1.09 + 0.000*cl 1.26 + -0.002*cl 1.06 + 0.000*cl t phz 1.00 1.00 + 0.000*cl 1.00 + 0.000*cl 1.00 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-79 kg80/KGM80 pvotyz tri-state output buffers kg80 plot8sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 4.10 1.65 + 0.049*cl 1.65 + 0.049*cl 1.66 + 0.049*cl t phl 3.55 1.92 + 0.033*cl 1.97 + 0.032*cl 1.99 + 0.032*cl t r 5.85 0.33 + 0.110*cl 0.29 + 0.111*cl 0.28 + 0.111*cl t f 3.91 0.68 + 0.065*cl 0.64 + 0.065*cl 0.58 + 0.066*cl tn to pad t plh 3.88 1.42 + 0.049*cl 1.43 + 0.049*cl 1.43 + 0.049*cl t phl 3.56 1.92 + 0.033*cl 1.97 + 0.032*cl 1.99 + 0.032*cl t r 5.85 0.33 + 0.110*cl 0.30 + 0.111*cl 0.29 + 0.111*cl t f 3.91 0.68 + 0.065*cl 0.67 + 0.065*cl 0.60 + 0.066*cl t plz 1.12 1.12 + 0.000*cl 1.12 + 0.000*cl 1.12 + 0.000*cl t phz 1.06 1.06 + 0.000*cl 1.06 + 0.000*cl 1.06 + 0.000*cl en to pad t plh 3.99 1.54 + 0.049*cl 1.55 + 0.049*cl 1.55 + 0.049*cl t phl 3.68 2.04 + 0.033*cl 2.09 + 0.032*cl 2.11 + 0.032*cl t r 5.85 0.33 + 0.110*cl 0.30 + 0.111*cl 0.29 + 0.111*cl t f 3.91 0.68 + 0.065*cl 0.64 + 0.065*cl 0.61 + 0.065*cl t plz 1.09 1.14 + -0.001*cl 1.07 + 0.000*cl 1.07 + 0.000*cl t phz 1.00 1.00 + 0.000*cl 1.00 + 0.000*cl 1.00 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plot10sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.57 1.64 + 0.039*cl 1.64 + 0.039*cl 1.65 + 0.039*cl t phl 3.21 1.86 + 0.027*cl 1.94 + 0.026*cl 1.97 + 0.026*cl t r 4.71 0.40 + 0.086*cl 0.34 + 0.087*cl 0.34 + 0.087*cl t f 3.35 0.86 + 0.050*cl 0.85 + 0.050*cl 0.78 + 0.051*cl tn to pad t plh 3.35 1.41 + 0.039*cl 1.43 + 0.039*cl 1.41 + 0.039*cl t phl 3.21 1.85 + 0.027*cl 1.93 + 0.026*cl 1.97 + 0.026*cl t r 4.70 0.39 + 0.086*cl 0.35 + 0.087*cl 0.32 + 0.087*cl t f 3.35 0.87 + 0.050*cl 0.85 + 0.050*cl 0.80 + 0.051*cl t plz 1.26 1.24 + 0.000*cl 1.27 + 0.000*cl 1.27 + 0.000*cl t phz 1.19 1.19 + 0.000*cl 1.19 + 0.000*cl 1.19 + 0.000*cl en to pad t plh 3.46 1.53 + 0.039*cl 1.53 + 0.039*cl 1.53 + 0.039*cl t phl 3.33 1.97 + 0.027*cl 2.06 + 0.026*cl 2.09 + 0.026*cl t r 4.70 0.40 + 0.086*cl 0.35 + 0.087*cl 0.32 + 0.087*cl t f 3.35 0.88 + 0.050*cl 0.85 + 0.050*cl 0.80 + 0.050*cl t plz 1.23 1.28 + -0.001*cl 1.01 + 0.003*cl 1.38 + -0.002*cl t phz 1.13 1.13 + 0.000*cl 1.13 + 0.000*cl 1.13 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-80 sec asic pvotyz tri-state output buffers kg80 plot12sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.42 1.79 + 0.033*cl 1.80 + 0.032*cl 1.82 + 0.032*cl t phl 3.25 2.02 + 0.025*cl 2.13 + 0.023*cl 2.19 + 0.022*cl t r 4.06 0.50 + 0.071*cl 0.46 + 0.072*cl 0.43 + 0.072*cl t f 3.10 1.03 + 0.041*cl 1.03 + 0.041*cl 1.02 + 0.041*cl tn to pad t plh 3.19 1.56 + 0.033*cl 1.56 + 0.033*cl 1.60 + 0.032*cl t phl 3.24 2.00 + 0.025*cl 2.12 + 0.023*cl 2.17 + 0.023*cl t r 4.06 0.52 + 0.071*cl 0.44 + 0.072*cl 0.45 + 0.072*cl t f 3.12 1.08 + 0.041*cl 1.07 + 0.041*cl 1.04 + 0.041*cl t plz 1.27 1.27 + 0.000*cl 1.27 + 0.000*cl 1.27 + 0.000*cl t phz 1.19 1.19 + 0.000*cl 1.19 + 0.000*cl 1.19 + 0.000*cl en to pad t plh 3.31 1.68 + 0.033*cl 1.69 + 0.032*cl 1.71 + 0.032*cl t phl 3.36 2.12 + 0.025*cl 2.24 + 0.023*cl 2.30 + 0.023*cl t r 4.06 0.51 + 0.071*cl 0.47 + 0.072*cl 0.43 + 0.072*cl t f 3.11 1.07 + 0.041*cl 1.04 + 0.041*cl 1.04 + 0.041*cl t plz 1.23 1.28 + -0.001*cl 1.20 + 0.000*cl 1.06 + 0.002*cl t phz 1.13 1.13 + 0.000*cl 1.13 + 0.000*cl 1.13 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 plot16sm switching characteristics [delays for typical process, 25 c, 3.3v*, 5.0v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.35 2.06 + 0.026*cl 2.11 + 0.025*cl 2.13 + 0.025*cl t phl 3.43 2.31 + 0.022*cl 2.45 + 0.020*cl 2.53 + 0.020*cl t r 3.38 0.74 + 0.053*cl 0.69 + 0.053*cl 0.64 + 0.054*cl t f 2.88 1.25 + 0.033*cl 1.31 + 0.032*cl 1.29 + 0.032*cl tn to pad t plh 3.11 1.82 + 0.026*cl 1.86 + 0.025*cl 1.90 + 0.025*cl t phl 3.40 2.26 + 0.023*cl 2.42 + 0.021*cl 2.50 + 0.020*cl t r 3.39 0.76 + 0.053*cl 0.71 + 0.053*cl 0.68 + 0.054*cl t f 2.94 1.37 + 0.031*cl 1.40 + 0.031*cl 1.38 + 0.031*cl t plz 1.25 1.25 + 0.000*cl 1.25 + 0.000*cl 1.17 + 0.001*cl t phz 1.18 1.18 + 0.000*cl 1.18 + 0.000*cl 1.18 + 0.000*cl en to pad t plh 3.23 1.93 + 0.026*cl 1.98 + 0.025*cl 2.01 + 0.025*cl t phl 3.52 2.38 + 0.023*cl 2.54 + 0.021*cl 2.63 + 0.020*cl t r 3.38 0.76 + 0.053*cl 0.70 + 0.053*cl 0.67 + 0.054*cl t f 2.94 1.36 + 0.032*cl 1.40 + 0.031*cl 1.38 + 0.031*cl t plz 1.20 1.19 + 0.000*cl 1.19 + 0.000*cl 1.19 + 0.000*cl t phz 1.12 1.12 + 0.000*cl 1.12 + 0.000*cl 1.12 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-81 kg80/KGM80 pvotyz tri-state output buffers KGM80 pot1 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 21.36 0.92 + 0.409*cl 0.92 + 0.409*cl 0.92 + 0.409*cl t phl 14.04 0.84 + 0.264*cl 0.84 + 0.264*cl 0.84 + 0.264*cl t r 47.48 0.91 + 0.931*cl 0.91 + 0.931*cl 0.91 + 0.931*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl tn to pad t plh 21.33 1.42 + 0.398*cl 3.44 + 0.371*cl 6.52 + 0.335*cl t phl 14.08 0.88 + 0.264*cl 0.88 + 0.264*cl 0.88 + 0.264*cl t r 47.48 0.91 + 0.931*cl 0.91 + 0.931*cl 0.91 + 0.931*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl t plz 0.86 0.86 + 0.000*cl 0.86 + 0.000*cl 0.86 + 0.000*cl t phz 0.79 0.79 + 0.000*cl 0.79 + 0.000*cl 0.79 + 0.000*cl en to pad t plh 21.52 1.61 + 0.398*cl 3.67 + 0.371*cl 6.79 + 0.334*cl t phl 14.28 1.08 + 0.264*cl 1.08 + 0.264*cl 1.08 + 0.264*cl t r 47.48 0.91 + 0.931*cl 0.91 + 0.931*cl 0.91 + 0.931*cl t f 28.97 0.52 + 0.569*cl 0.51 + 0.569*cl 0.52 + 0.569*cl t plz 0.77 0.77 + 0.000*cl 0.76 + 0.000*cl 0.76 + 0.000*cl t phz 0.71 0.71 + 0.000*cl 0.71 + 0.000*cl 0.71 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pot2 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 10.45 0.80 + 0.193*cl 0.80 + 0.193*cl 0.80 + 0.193*cl t phl 6.93 0.75 + 0.124*cl 0.75 + 0.124*cl 0.75 + 0.124*cl t r 22.42 0.45 + 0.439*cl 0.45 + 0.439*cl 0.45 + 0.439*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl tn to pad t plh 10.43 0.78 + 0.193*cl 0.78 + 0.193*cl 0.79 + 0.193*cl t phl 6.97 0.79 + 0.124*cl 0.80 + 0.123*cl 0.79 + 0.124*cl t r 22.42 0.45 + 0.439*cl 0.45 + 0.439*cl 0.45 + 0.439*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl t plz 0.95 0.95 + 0.000*cl 0.95 + 0.000*cl 0.95 + 0.000*cl t phz 0.86 0.86 + 0.000*cl 0.86 + 0.000*cl 0.86 + 0.000*cl en to pad t plh 10.62 0.97 + 0.193*cl 0.97 + 0.193*cl 0.99 + 0.193*cl t phl 7.16 0.99 + 0.124*cl 0.98 + 0.124*cl 0.99 + 0.123*cl t r 22.42 0.45 + 0.439*cl 0.45 + 0.439*cl 0.45 + 0.439*cl t f 13.57 0.26 + 0.266*cl 0.26 + 0.266*cl 0.26 + 0.266*cl t plz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl t phz 0.79 0.79 + 0.000*cl 0.78 + 0.000*cl 0.79 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-82 sec asic pvotyz tri-state output buffers KGM80 pot4 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf ] path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.55 0.72 + 0.097*cl 0.73 + 0.096*cl 0.73 + 0.096*cl t phl 3.89 0.80 + 0.062*cl 0.80 + 0.062*cl 0.80 + 0.062*cl t r 11.24 0.25 + 0.220*cl 0.25 + 0.220*cl 0.25 + 0.220*cl t f 6.81 0.16 + 0.133*cl 0.16 + 0.133*cl 0.15 + 0.133*cl tn to pad t plh 5.53 0.71 + 0.096*cl 0.71 + 0.097*cl 0.71 + 0.097*cl t phl 3.92 0.83 + 0.062*cl 0.83 + 0.062*cl 0.83 + 0.062*cl t r 11.24 0.25 + 0.220*cl 0.25 + 0.220*cl 0.25 + 0.220*cl t f 6.81 0.15 + 0.133*cl 0.15 + 0.133*cl 0.15 + 0.133*cl t plz 1.08 1.07 + 0.000*cl 1.08 + 0.000*cl 1.06 + 0.000*cl t phz 1.52 1.50 + 0.000*cl 1.51 + 0.000*cl 1.51 + 0.000*cl en to pad t plh 5.72 0.89 + 0.097*cl 0.89 + 0.097*cl 0.89 + 0.097*cl t phl 4.11 1.02 + 0.062*cl 1.02 + 0.062*cl 1.03 + 0.062*cl t r 11.24 0.25 + 0.220*cl 0.25 + 0.220*cl 0.25 + 0.220*cl t f 6.81 0.15 + 0.133*cl 0.16 + 0.133*cl 0.15 + 0.133*cl t plz 0.98 0.98 + 0.000*cl 0.98 + 0.000*cl 0.98 + 0.000*cl t phz 1.40 1.40 + 0.000*cl 1.40 + 0.000*cl 1.40 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pot6 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 4.00 0.79 + 0.064*cl 0.79 + 0.064*cl 0.78 + 0.064*cl t phl 2.95 0.91 + 0.041*cl 0.90 + 0.041*cl 0.90 + 0.041*cl t r 7.52 0.19 + 0.146*cl 0.20 + 0.146*cl 0.20 + 0.146*cl t f 4.58 0.16 + 0.088*cl 0.15 + 0.089*cl 0.13 + 0.089*cl tn to pad t plh 3.98 0.77 + 0.064*cl 0.76 + 0.064*cl 0.77 + 0.064*cl t phl 2.97 0.91 + 0.041*cl 0.91 + 0.041*cl 0.91 + 0.041*cl t r 7.52 0.19 + 0.146*cl 0.19 + 0.147*cl 0.20 + 0.146*cl t f 4.57 0.14 + 0.089*cl 0.13 + 0.089*cl 0.13 + 0.089*cl t plz 1.21 1.21 + 0.000*cl 1.21 + 0.000*cl 1.20 + 0.000*cl t phz 1.89 1.89 + 0.000*cl 1.89 + 0.000*cl 1.89 + 0.000*cl en to pad t plh 4.17 0.95 + 0.064*cl 0.95 + 0.064*cl 0.95 + 0.064*cl t phl 3.16 1.10 + 0.041*cl 1.10 + 0.041*cl 1.11 + 0.041*cl t r 7.52 0.19 + 0.146*cl 0.20 + 0.146*cl 0.19 + 0.146*cl t f 4.57 0.14 + 0.089*cl 0.14 + 0.089*cl 0.13 + 0.089*cl t plz 1.13 1.18 + -0.001*cl 1.11 + 0.000*cl 1.11 + 0.000*cl t phz 1.79 1.78 + 0.000*cl 1.78 + 0.000*cl 1.78 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-83 kg80/KGM80 pvotyz tri-state output buffers KGM80 pot8 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.27 0.86 + 0.048*cl 0.85 + 0.048*cl 0.86 + 0.048*cl t phl 2.55 1.04 + 0.030*cl 1.02 + 0.031*cl 1.01 + 0.031*cl t r 5.66 0.17 + 0.110*cl 0.17 + 0.110*cl 0.17 + 0.110*cl t f 3.51 0.25 + 0.065*cl 0.20 + 0.066*cl 0.18 + 0.066*cl tn to pad t plh 3.25 0.83 + 0.048*cl 0.83 + 0.048*cl 0.83 + 0.048*cl t phl 2.54 1.00 + 0.031*cl 0.99 + 0.031*cl 1.00 + 0.031*cl t r 5.66 0.17 + 0.110*cl 0.17 + 0.110*cl 0.17 + 0.110*cl t f 3.47 0.17 + 0.066*cl 0.15 + 0.066*cl 0.15 + 0.066*cl t plz 1.33 1.32 + 0.000*cl 1.39 + -0.001*cl 1.33 + 0.000*cl t phz 2.28 2.28 + 0.000*cl 2.28 + 0.000*cl 2.28 + 0.000*cl en to pad t plh 3.43 1.02 + 0.048*cl 1.02 + 0.048*cl 1.02 + 0.048*cl t phl 2.73 1.18 + 0.031*cl 1.19 + 0.031*cl 1.18 + 0.031*cl t r 5.66 0.17 + 0.110*cl 0.17 + 0.110*cl 0.17 + 0.110*cl t f 3.47 0.17 + 0.066*cl 0.16 + 0.066*cl 0.14 + 0.066*cl t plz 1.24 1.24 + 0.000*cl 1.24 + 0.000*cl 1.24 + 0.000*cl t phz 2.17 2.17 + 0.000*cl 2.17 + 0.000*cl 2.17 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pot10 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.90 0.97 + 0.039*cl 0.97 + 0.039*cl 0.97 + 0.039*cl t phl 2.29 1.06 + 0.025*cl 1.05 + 0.025*cl 1.06 + 0.025*cl t r 4.56 0.18 + 0.088*cl 0.18 + 0.088*cl 0.16 + 0.088*cl t f 2.83 0.22 + 0.052*cl 0.17 + 0.053*cl 0.19 + 0.053*cl tn to pad t plh 2.88 0.95 + 0.039*cl 0.94 + 0.039*cl 0.95 + 0.039*cl t phl 2.32 1.08 + 0.025*cl 1.09 + 0.025*cl 1.09 + 0.025*cl t r 4.56 0.18 + 0.088*cl 0.17 + 0.088*cl 0.16 + 0.088*cl t f 2.84 0.22 + 0.052*cl 0.18 + 0.053*cl 0.19 + 0.053*cl t plz 1.46 1.46 + 0.000*cl 1.44 + 0.000*cl 1.45 + 0.000*cl t phz 1.69 1.69 + 0.000*cl 1.69 + 0.000*cl 1.69 + 0.000*cl en to pad t plh 3.07 1.14 + 0.039*cl 1.13 + 0.039*cl 1.14 + 0.039*cl t phl 2.51 1.28 + 0.025*cl 1.28 + 0.025*cl 1.28 + 0.025*cl t r 4.56 0.18 + 0.088*cl 0.16 + 0.088*cl 0.17 + 0.088*cl t f 2.83 0.22 + 0.052*cl 0.19 + 0.053*cl 0.18 + 0.053*cl t plz 1.37 1.37 + 0.000*cl 1.36 + 0.000*cl 1.37 + 0.000*cl t phz 1.58 1.58 + 0.000*cl 1.58 + 0.000*cl 1.58 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-84 sec asic pvotyz tri-state output buffers KGM80 pot12 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.70 1.09 + 0.032*cl 1.09 + 0.032*cl 1.08 + 0.032*cl t phl 2.16 1.13 + 0.021*cl 1.14 + 0.021*cl 1.13 + 0.021*cl t r 3.84 0.20 + 0.073*cl 0.18 + 0.073*cl 0.17 + 0.073*cl t f 2.42 0.26 + 0.043*cl 0.23 + 0.044*cl 0.24 + 0.044*cl tn to pad t plh 2.67 1.06 + 0.032*cl 1.06 + 0.032*cl 1.07 + 0.032*cl t phl 2.20 1.16 + 0.021*cl 1.18 + 0.021*cl 1.17 + 0.021*cl t r 3.84 0.21 + 0.073*cl 0.18 + 0.073*cl 0.18 + 0.073*cl t f 2.43 0.26 + 0.043*cl 0.26 + 0.043*cl 0.24 + 0.044*cl t plz 1.59 1.58 + 0.000*cl 1.58 + 0.000*cl 1.59 + 0.000*cl t phz 1.50 1.50 + 0.000*cl 1.50 + 0.000*cl 1.50 + 0.000*cl en to pad t plh 2.86 1.25 + 0.032*cl 1.25 + 0.032*cl 1.25 + 0.032*cl t phl 2.39 1.36 + 0.021*cl 1.36 + 0.021*cl 1.37 + 0.021*cl t r 3.84 0.21 + 0.073*cl 0.18 + 0.073*cl 0.18 + 0.073*cl t f 2.43 0.28 + 0.043*cl 0.26 + 0.043*cl 0.24 + 0.044*cl t plz 1.49 1.49 + 0.000*cl 1.49 + 0.000*cl 1.49 + 0.000*cl t phz 1.43 1.38 + 0.001*cl 1.45 + 0.000*cl 1.45 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pot16 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.46 1.24 + 0.024*cl 1.24 + 0.024*cl 1.24 + 0.024*cl t phl 2.08 1.27 + 0.016*cl 1.29 + 0.016*cl 1.30 + 0.016*cl t r 3.00 0.26 + 0.055*cl 0.23 + 0.055*cl 0.23 + 0.055*cl t f 1.98 0.34 + 0.033*cl 0.34 + 0.033*cl 0.34 + 0.033*cl tn to pad t plh 2.42 1.19 + 0.025*cl 1.20 + 0.025*cl 1.20 + 0.025*cl t phl 2.11 1.29 + 0.016*cl 1.32 + 0.016*cl 1.33 + 0.016*cl t r 3.01 0.27 + 0.055*cl 0.24 + 0.055*cl 0.24 + 0.055*cl t f 1.98 0.35 + 0.033*cl 0.35 + 0.033*cl 0.32 + 0.033*cl t plz 1.83 1.83 + 0.000*cl 1.83 + 0.000*cl 1.83 + 0.000*cl t phz 1.74 1.74 + 0.000*cl 1.74 + 0.000*cl 1.74 + 0.000*cl en to pad t plh 2.61 1.38 + 0.025*cl 1.38 + 0.025*cl 1.39 + 0.025*cl t phl 2.30 1.48 + 0.016*cl 1.51 + 0.016*cl 1.52 + 0.016*cl t r 3.01 0.28 + 0.055*cl 0.24 + 0.055*cl 0.23 + 0.055*cl t f 1.98 0.36 + 0.032*cl 0.36 + 0.032*cl 0.32 + 0.033*cl t plz 1.73 1.73 + 0.000*cl 1.73 + 0.000*cl 1.72 + 0.000*cl t phz 1.66 1.65 + 0.000*cl 1.66 + 0.000*cl 1.65 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-85 kg80/KGM80 pvotyz tri-state output buffers KGM80 pot4sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.99 1.03 + 0.099*cl 1.03 + 0.099*cl 1.03 + 0.099*cl t phl 4.41 1.22 + 0.064*cl 1.22 + 0.064*cl 1.22 + 0.064*cl t r 11.58 0.28 + 0.226*cl 0.28 + 0.226*cl 0.28 + 0.226*cl t f 7.10 0.27 + 0.137*cl 0.23 + 0.137*cl 0.22 + 0.137*cl tn to pad t plh 5.96 1.00 + 0.099*cl 1.00 + 0.099*cl 1.00 + 0.099*cl t phl 4.45 1.26 + 0.064*cl 1.25 + 0.064*cl 1.26 + 0.064*cl t r 11.58 0.28 + 0.226*cl 0.27 + 0.226*cl 0.27 + 0.226*cl t f 7.10 0.27 + 0.137*cl 0.23 + 0.137*cl 0.22 + 0.137*cl t plz 1.01 1.01 + 0.000*cl 1.01 + 0.000*cl 1.01 + 0.000*cl t phz 0.90 0.90 + 0.000*cl 0.90 + 0.000*cl 0.90 + 0.000*cl en to pad t plh 6.15 1.18 + 0.099*cl 1.19 + 0.099*cl 1.15 + 0.100*cl t phl 4.64 1.45 + 0.064*cl 1.45 + 0.064*cl 1.45 + 0.064*cl t r 11.58 0.28 + 0.226*cl 0.27 + 0.226*cl 0.27 + 0.226*cl t f 7.10 0.27 + 0.137*cl 0.23 + 0.137*cl 0.23 + 0.137*cl t plz 0.91 0.85 + 0.001*cl 0.94 + 0.000*cl 0.94 + 0.000*cl t phz 0.81 0.81 + 0.000*cl 0.81 + 0.000*cl 0.81 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pot6sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 4.51 1.23 + 0.066*cl 1.23 + 0.066*cl 1.23 + 0.066*cl t phl 3.65 1.53 + 0.042*cl 1.55 + 0.042*cl 1.55 + 0.042*cl t r 7.71 0.27 + 0.149*cl 0.24 + 0.149*cl 0.24 + 0.149*cl t f 4.88 0.46 + 0.088*cl 0.42 + 0.089*cl 0.38 + 0.089*cl tn to pad t plh 4.47 1.19 + 0.066*cl 1.20 + 0.066*cl 1.19 + 0.066*cl t phl 3.69 1.58 + 0.042*cl 1.59 + 0.042*cl 1.59 + 0.042*cl t r 7.71 0.26 + 0.149*cl 0.25 + 0.149*cl 0.24 + 0.149*cl t f 4.88 0.46 + 0.088*cl 0.42 + 0.089*cl 0.37 + 0.089*cl t plz 0.95 0.95 + 0.000*cl 0.95 + 0.000*cl 0.95 + 0.000*cl t phz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl en to pad t plh 4.66 1.38 + 0.066*cl 1.38 + 0.066*cl 1.38 + 0.066*cl t phl 3.89 1.77 + 0.042*cl 1.78 + 0.042*cl 1.79 + 0.042*cl t r 7.71 0.26 + 0.149*cl 0.25 + 0.149*cl 0.24 + 0.149*cl t f 4.88 0.46 + 0.088*cl 0.41 + 0.089*cl 0.38 + 0.089*cl t plz 0.85 0.85 + 0.000*cl 0.85 + 0.000*cl 0.85 + 0.000*cl t phz 0.77 0.77 + 0.000*cl 0.77 + 0.000*cl 0.77 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-86 sec asic pvotyz tri-state output buffers KGM80 pot8sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.85 1.40 + 0.049*cl 1.40 + 0.049*cl 1.40 + 0.049*cl t phl 3.44 1.80 + 0.033*cl 1.85 + 0.032*cl 1.87 + 0.032*cl t r 5.85 0.33 + 0.110*cl 0.30 + 0.111*cl 0.28 + 0.111*cl t f 3.91 0.68 + 0.065*cl 0.63 + 0.065*cl 0.61 + 0.066*cl tn to pad t plh 3.81 1.36 + 0.049*cl 1.22 + 0.051*cl 1.39 + 0.049*cl t phl 3.48 1.84 + 0.033*cl 1.89 + 0.032*cl 1.91 + 0.032*cl t r 5.85 0.33 + 0.110*cl 0.29 + 0.111*cl 0.28 + 0.111*cl t f 3.91 0.68 + 0.065*cl 0.63 + 0.065*cl 0.62 + 0.065*cl t plz 0.95 0.95 + 0.000*cl 0.93 + 0.000*cl 0.95 + 0.000*cl t phz 0.87 0.87 + 0.000*cl 0.87 + 0.000*cl 0.87 + 0.000*cl en to pad t plh 4.00 1.55 + 0.049*cl 1.55 + 0.049*cl 1.55 + 0.049*cl t phl 3.67 2.04 + 0.033*cl 2.08 + 0.032*cl 2.10 + 0.032*cl t r 5.85 0.33 + 0.110*cl 0.29 + 0.111*cl 0.28 + 0.111*cl t f 3.91 0.69 + 0.064*cl 0.61 + 0.065*cl 0.62 + 0.065*cl t plz 0.88 0.93 + -0.001*cl 0.85 + 0.000*cl 0.85 + 0.000*cl t phz 0.77 0.77 + 0.000*cl 0.77 + 0.000*cl 0.77 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pot10sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.32 1.38 + 0.039*cl 1.39 + 0.039*cl 1.39 + 0.039*cl t phl 3.10 1.74 + 0.027*cl 1.82 + 0.026*cl 1.86 + 0.026*cl t r 4.70 0.39 + 0.086*cl 0.35 + 0.087*cl 0.34 + 0.087*cl t f 3.34 0.85 + 0.050*cl 0.83 + 0.050*cl 0.80 + 0.050*cl tn to pad t plh 3.28 1.35 + 0.039*cl 1.35 + 0.039*cl 1.35 + 0.039*cl t phl 3.13 1.77 + 0.027*cl 1.86 + 0.026*cl 1.89 + 0.026*cl t r 4.71 0.40 + 0.086*cl 0.35 + 0.087*cl 0.32 + 0.087*cl t f 3.36 0.88 + 0.049*cl 0.84 + 0.050*cl 0.79 + 0.051*cl t plz 1.09 1.09 + 0.000*cl 1.08 + 0.000*cl 1.08 + 0.000*cl t phz 1.00 1.00 + 0.000*cl 1.00 + 0.000*cl 1.00 + 0.000*cl en to pad t plh 3.47 1.53 + 0.039*cl 1.54 + 0.039*cl 1.54 + 0.039*cl t phl 3.33 1.97 + 0.027*cl 2.05 + 0.026*cl 2.08 + 0.026*cl t r 4.70 0.39 + 0.086*cl 0.35 + 0.087*cl 0.32 + 0.087*cl t f 3.36 0.88 + 0.049*cl 0.84 + 0.050*cl 0.80 + 0.051*cl t plz 0.99 0.99 + 0.000*cl 0.99 + 0.000*cl 0.99 + 0.000*cl t phz 0.90 0.90 + 0.000*cl 0.90 + 0.000*cl 0.90 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-87 kg80/KGM80 pvotyz tri-state output buffers KGM80 pot12sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.17 1.54 + 0.033*cl 1.55 + 0.032*cl 1.56 + 0.032*cl t phl 3.14 1.91 + 0.025*cl 2.02 + 0.023*cl 2.07 + 0.022*cl t r 4.06 0.51 + 0.071*cl 0.45 + 0.072*cl 0.44 + 0.072*cl t f 3.10 1.03 + 0.041*cl 1.00 + 0.042*cl 1.01 + 0.042*cl tn to pad t plh 3.14 1.51 + 0.033*cl 1.64 + 0.031*cl 1.43 + 0.033*cl t phl 3.17 1.93 + 0.025*cl 2.04 + 0.023*cl 2.10 + 0.023*cl t r 4.06 0.51 + 0.071*cl 0.46 + 0.072*cl 0.43 + 0.072*cl t f 3.12 1.08 + 0.041*cl 1.06 + 0.041*cl 1.02 + 0.042*cl t plz 1.09 1.09 + 0.000*cl 1.07 + 0.000*cl 1.07 + 0.000*cl t phz 1.00 1.00 + 0.000*cl 1.00 + 0.000*cl 1.00 + 0.000*cl en to pad t plh 3.32 1.69 + 0.033*cl 1.70 + 0.032*cl 1.70 + 0.032*cl t phl 3.36 2.12 + 0.025*cl 2.24 + 0.023*cl 2.29 + 0.023*cl t r 4.06 0.52 + 0.071*cl 0.46 + 0.072*cl 0.43 + 0.072*cl t f 3.12 1.08 + 0.041*cl 1.06 + 0.041*cl 1.03 + 0.041*cl t plz 0.99 0.98 + 0.000*cl 0.99 + 0.000*cl 0.99 + 0.000*cl t phz 0.90 0.90 + 0.000*cl 0.90 + 0.000*cl 0.90 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 pot16sm switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.10 1.80 + 0.026*cl 1.86 + 0.025*cl 1.87 + 0.025*cl t phl 3.31 2.19 + 0.022*cl 2.33 + 0.020*cl 2.41 + 0.020*cl t r 3.37 0.73 + 0.053*cl 0.70 + 0.053*cl 0.66 + 0.054*cl t f 2.88 1.25 + 0.033*cl 1.32 + 0.032*cl 1.30 + 0.032*cl tn to pad t plh 3.05 1.72 + 0.026*cl 1.82 + 0.025*cl 1.84 + 0.025*cl t phl 3.32 2.18 + 0.023*cl 2.34 + 0.021*cl 2.43 + 0.020*cl t r 3.38 0.76 + 0.052*cl 0.70 + 0.053*cl 0.67 + 0.054*cl t f 2.95 1.38 + 0.031*cl 1.41 + 0.031*cl 1.37 + 0.031*cl t plz 1.08 1.07 + 0.000*cl 1.08 + 0.000*cl 1.08 + 0.000*cl t phz 0.99 0.99 + 0.000*cl 0.99 + 0.000*cl 0.99 + 0.000*cl en to pad t plh 3.23 1.94 + 0.026*cl 2.00 + 0.025*cl 2.01 + 0.025*cl t phl 3.52 2.37 + 0.023*cl 2.54 + 0.021*cl 2.62 + 0.020*cl t r 3.39 0.77 + 0.052*cl 0.69 + 0.053*cl 0.68 + 0.054*cl t f 2.94 1.37 + 0.031*cl 1.41 + 0.031*cl 1.37 + 0.031*cl t plz 0.99 0.98 + 0.000*cl 0.98 + 0.000*cl 0.98 + 0.000*cl t phz 0.89 0.88 + 0.000*cl 0.90 + 0.000*cl 0.90 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-88 sec asic pvotyz tri-state output buffers KGM80 phot1 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 15.51 0.90 + 0.292*cl 0.90 + 0.292*cl 0.89 + 0.292*cl t phl 12.56 0.91 + 0.233*cl 0.92 + 0.233*cl 0.91 + 0.233*cl t r 33.59 0.59 + 0.660*cl 0.60 + 0.660*cl 0.59 + 0.660*cl t f 24.65 0.40 + 0.485*cl 0.40 + 0.485*cl 0.40 + 0.485*cl tn to pad t plh 10.17 1.03 + 0.183*cl 1.63 + 0.175*cl 2.79 + 0.161*cl t phl 17.31 1.10 + 0.324*cl 1.11 + 0.324*cl 1.10 + 0.324*cl t r 16.39 0.24 + 0.323*cl 0.24 + 0.323*cl 0.24 + 0.323*cl t f 20.78 0.31 + 0.409*cl 0.31 + 0.409*cl 0.31 + 0.409*cl t plz 1.00 1.00 + 0.000*cl 1.00 + 0.000*cl 1.00 + 0.000*cl t phz 0.91 0.91 + 0.000*cl 0.91 + 0.000*cl 0.91 + 0.000*cl en to pad t plh 10.34 1.19 + 0.183*cl 1.80 + 0.175*cl 2.98 + 0.161*cl t phl 17.47 1.27 + 0.324*cl 1.27 + 0.324*cl 1.27 + 0.324*cl t r 16.39 0.24 + 0.323*cl 0.24 + 0.323*cl 0.24 + 0.323*cl t f 20.78 0.31 + 0.409*cl 0.31 + 0.409*cl 0.31 + 0.409*cl t plz 0.93 0.93 + 0.000*cl 0.93 + 0.000*cl 0.93 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phot2 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 8.13 0.83 + 0.146*cl 0.82 + 0.146*cl 0.83 + 0.146*cl t phl 6.65 0.83 + 0.116*cl 0.84 + 0.116*cl 0.84 + 0.116*cl t r 16.81 0.31 + 0.330*cl 0.30 + 0.330*cl 0.31 + 0.330*cl t f 12.34 0.21 + 0.243*cl 0.21 + 0.243*cl 0.21 + 0.243*cl tn to pad t plh 5.51 0.88 + 0.093*cl 0.88 + 0.093*cl 0.89 + 0.093*cl t phl 9.09 0.99 + 0.162*cl 0.99 + 0.162*cl 0.99 + 0.162*cl t r 8.20 0.12 + 0.161*cl 0.13 + 0.161*cl 0.12 + 0.161*cl t f 10.40 0.17 + 0.205*cl 0.17 + 0.205*cl 0.17 + 0.205*cl t plz 1.06 1.06 + 0.000*cl 1.06 + 0.000*cl 1.05 + 0.000*cl t phz 0.93 0.93 + 0.000*cl 0.93 + 0.000*cl 0.93 + 0.000*cl en to pad t plh 5.68 1.05 + 0.093*cl 1.05 + 0.093*cl 1.05 + 0.093*cl t phl 9.25 1.15 + 0.162*cl 1.15 + 0.162*cl 1.15 + 0.162*cl t r 8.20 0.12 + 0.161*cl 0.13 + 0.161*cl 0.12 + 0.161*cl t f 10.40 0.17 + 0.205*cl 0.17 + 0.205*cl 0.17 + 0.205*cl t plz 0.99 0.99 + 0.000*cl 0.99 + 0.000*cl 0.99 + 0.000*cl t phz 0.85 0.85 + 0.000*cl 0.85 + 0.000*cl 0.85 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-89 kg80/KGM80 pvotyz tri-state output buffers KGM80 phot4 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.52 0.83 + 0.094*cl 0.83 + 0.094*cl 0.83 + 0.094*cl t phl 4.54 0.83 + 0.074*cl 0.82 + 0.074*cl 0.83 + 0.074*cl t r 10.81 0.21 + 0.212*cl 0.21 + 0.212*cl 0.21 + 0.212*cl t f 7.88 0.15 + 0.155*cl 0.14 + 0.155*cl 0.15 + 0.155*cl tn to pad t plh 3.87 0.90 + 0.059*cl 0.90 + 0.059*cl 0.89 + 0.059*cl t phl 6.14 0.97 + 0.103*cl 0.97 + 0.103*cl 0.98 + 0.103*cl t r 5.27 0.09 + 0.104*cl 0.09 + 0.104*cl 0.09 + 0.104*cl t f 6.64 0.12 + 0.130*cl 0.12 + 0.130*cl 0.11 + 0.131*cl t plz 1.13 1.12 + 0.000*cl 1.12 + 0.000*cl 1.07 + 0.001*cl t phz 0.96 0.96 + 0.000*cl 0.96 + 0.000*cl 0.96 + 0.000*cl en to pad t plh 4.03 1.06 + 0.059*cl 1.03 + 0.060*cl 1.08 + 0.059*cl t phl 6.30 1.13 + 0.103*cl 1.14 + 0.103*cl 1.13 + 0.103*cl t r 5.27 0.09 + 0.104*cl 0.09 + 0.104*cl 0.08 + 0.104*cl t f 6.64 0.12 + 0.130*cl 0.13 + 0.130*cl 0.11 + 0.131*cl t plz 1.06 1.06 + 0.000*cl 1.06 + 0.000*cl 1.06 + 0.000*cl t phz 0.88 0.88 + 0.000*cl 0.88 + 0.000*cl 0.88 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phot8 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.23 0.89 + 0.047*cl 0.89 + 0.047*cl 0.89 + 0.047*cl t phl 2.74 0.88 + 0.037*cl 0.88 + 0.037*cl 0.89 + 0.037*cl t r 5.43 0.13 + 0.106*cl 0.13 + 0.106*cl 0.13 + 0.106*cl t f 3.96 0.10 + 0.077*cl 0.10 + 0.077*cl 0.10 + 0.077*cl tn to pad t plh 2.45 0.97 + 0.030*cl 0.96 + 0.030*cl 0.97 + 0.030*cl t phl 3.61 1.03 + 0.052*cl 1.02 + 0.052*cl 1.07 + 0.051*cl t r 2.64 0.06 + 0.052*cl 0.05 + 0.052*cl 0.05 + 0.052*cl t f 3.34 0.08 + 0.065*cl 0.09 + 0.065*cl 0.08 + 0.065*cl t plz 1.30 1.30 + 0.000*cl 1.29 + 0.000*cl 1.30 + 0.000*cl t phz 1.04 1.04 + 0.000*cl 1.04 + 0.000*cl 1.04 + 0.000*cl en to pad t plh 2.62 1.13 + 0.030*cl 1.13 + 0.030*cl 1.13 + 0.030*cl t phl 3.77 1.18 + 0.052*cl 1.19 + 0.052*cl 1.18 + 0.052*cl t r 2.64 0.06 + 0.052*cl 0.05 + 0.052*cl 0.05 + 0.052*cl t f 3.34 0.08 + 0.065*cl 0.08 + 0.065*cl 0.08 + 0.065*cl t plz 1.25 1.28 + -0.001*cl 1.23 + 0.000*cl 1.23 + 0.000*cl t phz 0.96 0.96 + 0.000*cl 0.96 + 0.000*cl 0.96 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-90 sec asic pvotyz tri-state output buffers KGM80 phot12 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.68 0.95 + 0.034*cl 0.95 + 0.035*cl 0.95 + 0.035*cl t phl 2.30 0.94 + 0.027*cl 0.95 + 0.027*cl 0.94 + 0.027*cl t r 4.02 0.12 + 0.078*cl 0.11 + 0.078*cl 0.11 + 0.078*cl t f 2.93 0.11 + 0.056*cl 0.11 + 0.056*cl 0.09 + 0.057*cl tn to pad t plh 2.12 1.03 + 0.022*cl 1.03 + 0.022*cl 1.03 + 0.022*cl t phl 2.97 1.07 + 0.038*cl 1.07 + 0.038*cl 1.04 + 0.038*cl t r 1.96 0.06 + 0.038*cl 0.05 + 0.038*cl 0.05 + 0.038*cl t f 2.47 0.08 + 0.048*cl 0.08 + 0.048*cl 0.08 + 0.048*cl t plz 1.43 1.42 + 0.000*cl 1.33 + 0.001*cl 1.50 + -0.001*cl t phz 1.10 1.10 + 0.000*cl 1.10 + 0.000*cl 1.10 + 0.000*cl en to pad t plh 2.29 1.19 + 0.022*cl 1.19 + 0.022*cl 1.19 + 0.022*cl t phl 3.14 1.24 + 0.038*cl 1.24 + 0.038*cl 1.24 + 0.038*cl t r 1.96 0.06 + 0.038*cl 0.06 + 0.038*cl 0.05 + 0.038*cl t f 2.47 0.08 + 0.048*cl 0.09 + 0.048*cl 0.07 + 0.048*cl t plz 1.37 1.35 + 0.000*cl 1.36 + 0.000*cl 1.36 + 0.000*cl t phz 1.02 1.02 + 0.000*cl 1.02 + 0.000*cl 1.02 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phot16 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.30 1.05 + 0.025*cl 1.05 + 0.025*cl 1.04 + 0.025*cl t phl 2.02 1.03 + 0.020*cl 1.04 + 0.020*cl 1.02 + 0.020*cl t r 2.97 0.14 + 0.057*cl 0.12 + 0.057*cl 0.12 + 0.057*cl t f 2.19 0.15 + 0.041*cl 0.14 + 0.041*cl 0.14 + 0.041*cl tn to pad t plh 1.91 1.11 + 0.016*cl 1.11 + 0.016*cl 1.11 + 0.016*cl t phl 2.54 1.16 + 0.028*cl 1.15 + 0.028*cl 1.17 + 0.028*cl t r 1.47 0.10 + 0.027*cl 0.09 + 0.027*cl 0.08 + 0.028*cl t f 1.82 0.07 + 0.035*cl 0.08 + 0.035*cl 0.07 + 0.035*cl t plz 1.60 1.58 + 0.000*cl 1.68 + -0.001*cl 1.60 + 0.000*cl t phz 1.18 1.18 + 0.000*cl 1.18 + 0.000*cl 1.18 + 0.000*cl en to pad t plh 2.08 1.27 + 0.016*cl 1.28 + 0.016*cl 1.27 + 0.016*cl t phl 2.71 1.33 + 0.028*cl 1.27 + 0.028*cl 1.32 + 0.028*cl t r 1.47 0.10 + 0.027*cl 0.09 + 0.028*cl 0.08 + 0.028*cl t f 1.82 0.07 + 0.035*cl 0.07 + 0.035*cl 0.08 + 0.035*cl t plz 1.53 1.53 + 0.000*cl 1.53 + 0.000*cl 1.53 + 0.000*cl t phz 1.10 1.10 + 0.000*cl 1.10 + 0.000*cl 1.10 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-91 kg80/KGM80 pvotyz tri-state output buffers KGM80 phot20 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.93 0.94 + 0.020*cl 0.94 + 0.020*cl 0.94 + 0.020*cl t phl 1.79 1.01 + 0.016*cl 1.01 + 0.016*cl 1.00 + 0.016*cl t r 2.34 0.10 + 0.045*cl 0.10 + 0.045*cl 0.08 + 0.045*cl t f 1.75 0.16 + 0.032*cl 0.14 + 0.032*cl 0.12 + 0.032*cl tn to pad t plh 1.65 1.02 + 0.013*cl 1.02 + 0.013*cl 1.02 + 0.013*cl t phl 2.23 1.14 + 0.022*cl 1.13 + 0.022*cl 1.12 + 0.022*cl t r 1.15 0.07 + 0.022*cl 0.05 + 0.022*cl 0.05 + 0.022*cl t f 1.44 0.06 + 0.028*cl 0.06 + 0.028*cl 0.06 + 0.028*cl t plz 1.40 1.39 + 0.000*cl 1.47 + -0.001*cl 1.40 + 0.000*cl t phz 1.15 1.15 + 0.000*cl 1.14 + 0.000*cl 1.15 + 0.000*cl en to pad t plh 1.82 1.18 + 0.013*cl 1.22 + 0.012*cl 1.19 + 0.013*cl t phl 2.39 1.29 + 0.022*cl 1.29 + 0.022*cl 1.29 + 0.022*cl t r 1.15 0.07 + 0.022*cl 0.06 + 0.022*cl 0.05 + 0.022*cl t f 1.44 0.07 + 0.028*cl 0.05 + 0.028*cl 0.06 + 0.028*cl t plz 1.33 1.29 + 0.001*cl 1.51 + -0.002*cl 1.33 + 0.000*cl t phz 1.07 1.07 + 0.000*cl 1.07 + 0.000*cl 1.07 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phot24 switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 1.86 0.99 + 0.017*cl 0.98 + 0.018*cl 0.99 + 0.018*cl t phl 1.73 1.04 + 0.014*cl 1.04 + 0.014*cl 1.04 + 0.014*cl t r 2.07 0.10 + 0.039*cl 0.12 + 0.039*cl 0.09 + 0.040*cl t f 1.57 0.17 + 0.028*cl 0.16 + 0.028*cl 0.15 + 0.028*cl tn to pad t plh 1.62 1.07 + 0.011*cl 1.07 + 0.011*cl 1.07 + 0.011*cl t phl 2.13 1.16 + 0.019*cl 1.17 + 0.019*cl 1.17 + 0.019*cl t r 1.03 0.09 + 0.019*cl 0.06 + 0.019*cl 0.07 + 0.019*cl t f 1.28 0.07 + 0.024*cl 0.09 + 0.024*cl 0.05 + 0.024*cl t plz 1.46 1.45 + 0.000*cl 1.40 + 0.001*cl 1.46 + 0.000*cl t phz 1.14 1.14 + 0.000*cl 1.14 + 0.000*cl 1.14 + 0.000*cl en to pad t plh 1.79 1.23 + 0.011*cl 1.23 + 0.011*cl 1.23 + 0.011*cl t phl 2.29 1.33 + 0.019*cl 1.31 + 0.020*cl 1.33 + 0.019*cl t r 1.03 0.09 + 0.019*cl 0.07 + 0.019*cl 0.07 + 0.019*cl t f 1.28 0.07 + 0.024*cl 0.06 + 0.024*cl 0.05 + 0.024*cl t plz 1.39 1.39 + 0.000*cl 1.38 + 0.000*cl 1.39 + 0.000*cl t phz 1.07 1.07 + 0.000*cl 1.07 + 0.000*cl 1.06 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-92 sec asic pvotyz tri-state output buffers KGM80 phot12sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.44 1.66 + 0.036*cl 1.69 + 0.035*cl 1.69 + 0.035*cl t phl 3.94 2.34 + 0.032*cl 2.45 + 0.031*cl 2.51 + 0.030*cl t r 4.34 0.50 + 0.077*cl 0.44 + 0.078*cl 0.43 + 0.078*cl t f 3.74 0.97 + 0.055*cl 1.00 + 0.055*cl 0.99 + 0.055*cl tn to pad t plh 2.80 1.64 + 0.023*cl 1.68 + 0.023*cl 1.70 + 0.022*cl t phl 4.69 2.58 + 0.042*cl 2.69 + 0.041*cl 2.74 + 0.040*cl t r 2.26 0.43 + 0.037*cl 0.41 + 0.037*cl 0.38 + 0.037*cl t f 2.79 0.45 + 0.047*cl 0.43 + 0.047*cl 0.39 + 0.048*cl t plz 1.75 1.74 + 0.000*cl 1.71 + 0.001*cl 1.81 + -0.001*cl t phz 1.25 1.25 + 0.000*cl 1.25 + 0.000*cl 1.25 + 0.000*cl en to pad t plh 2.97 1.81 + 0.023*cl 1.85 + 0.023*cl 1.86 + 0.022*cl t phl 4.86 2.75 + 0.042*cl 2.84 + 0.041*cl 2.90 + 0.040*cl t r 2.26 0.43 + 0.037*cl 0.40 + 0.037*cl 0.38 + 0.037*cl t f 2.79 0.45 + 0.047*cl 0.40 + 0.047*cl 0.41 + 0.047*cl t plz 1.68 1.68 + 0.000*cl 1.68 + 0.000*cl 1.68 + 0.000*cl t phz 1.18 1.18 + 0.000*cl 1.18 + 0.000*cl 1.18 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phot16sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.24 1.89 + 0.027*cl 1.94 + 0.026*cl 1.97 + 0.026*cl t phl 3.64 2.39 + 0.025*cl 2.50 + 0.024*cl 2.56 + 0.023*cl t r 3.43 0.71 + 0.055*cl 0.68 + 0.055*cl 0.67 + 0.055*cl t f 3.00 0.96 + 0.041*cl 1.01 + 0.040*cl 1.02 + 0.040*cl tn to pad t plh 2.73 1.81 + 0.019*cl 1.88 + 0.017*cl 1.91 + 0.017*cl t phl 4.24 2.60 + 0.033*cl 2.72 + 0.031*cl 2.78 + 0.030*cl t r 1.90 0.61 + 0.026*cl 0.60 + 0.026*cl 0.59 + 0.026*cl t f 2.17 0.50 + 0.033*cl 0.47 + 0.034*cl 0.47 + 0.034*cl t plz 1.72 1.72 + 0.000*cl 1.72 + 0.000*cl 1.72 + 0.000*cl t phz 1.25 1.25 + 0.000*cl 1.25 + 0.000*cl 1.25 + 0.000*cl en to pad t plh 2.90 1.97 + 0.018*cl 2.04 + 0.018*cl 2.08 + 0.017*cl t phl 4.40 2.77 + 0.033*cl 2.89 + 0.031*cl 2.94 + 0.031*cl t r 1.90 0.61 + 0.026*cl 0.61 + 0.026*cl 0.59 + 0.026*cl t f 2.17 0.49 + 0.033*cl 0.48 + 0.034*cl 0.47 + 0.034*cl t plz 1.65 1.65 + 0.000*cl 1.65 + 0.000*cl 1.65 + 0.000*cl t phz 1.18 1.18 + 0.000*cl 1.18 + 0.000*cl 1.18 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-93 kg80/KGM80 pvotyz tri-state output buffers KGM80 phot20sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.63 1.57 + 0.021*cl 1.62 + 0.021*cl 1.63 + 0.020*cl t phl 2.66 1.80 + 0.017*cl 1.84 + 0.017*cl 1.85 + 0.017*cl t r 2.72 0.58 + 0.043*cl 0.55 + 0.043*cl 0.55 + 0.043*cl t f 2.24 0.72 + 0.030*cl 0.70 + 0.031*cl 0.69 + 0.031*cl tn to pad t plh 2.25 1.52 + 0.015*cl 1.58 + 0.014*cl 1.61 + 0.014*cl t phl 3.05 1.82 + 0.024*cl 1.91 + 0.023*cl 1.93 + 0.023*cl t r 1.53 0.53 + 0.020*cl 0.50 + 0.020*cl 0.51 + 0.020*cl t f 1.63 0.32 + 0.026*cl 0.29 + 0.027*cl 0.27 + 0.027*cl t plz 1.08 1.06 + 0.000*cl 1.16 + -0.001*cl 1.08 + 0.000*cl t phz 1.12 1.12 + 0.000*cl 1.12 + 0.000*cl 1.12 + 0.000*cl en to pad t plh 2.42 1.69 + 0.015*cl 1.75 + 0.014*cl 1.78 + 0.013*cl t phl 3.21 1.98 + 0.025*cl 2.07 + 0.023*cl 2.09 + 0.023*cl t r 1.53 0.53 + 0.020*cl 0.50 + 0.020*cl 0.50 + 0.020*cl t f 1.63 0.30 + 0.026*cl 0.32 + 0.026*cl 0.27 + 0.027*cl t plz 1.00 1.00 + 0.000*cl 1.00 + 0.000*cl 1.00 + 0.000*cl t phz 1.05 1.05 + 0.000*cl 1.05 + 0.000*cl 1.05 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phot24sh switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.62 1.65 + 0.019*cl 1.72 + 0.019*cl 1.73 + 0.018*cl t phl 2.73 1.94 + 0.016*cl 1.97 + 0.015*cl 1.99 + 0.015*cl t r 2.54 0.66 + 0.038*cl 0.67 + 0.037*cl 0.63 + 0.038*cl t f 2.15 0.81 + 0.027*cl 0.82 + 0.027*cl 0.79 + 0.027*cl tn to pad t plh 2.27 1.58 + 0.014*cl 1.65 + 0.013*cl 1.68 + 0.012*cl t phl 3.04 1.90 + 0.023*cl 1.99 + 0.022*cl 2.04 + 0.021*cl t r 1.47 0.59 + 0.018*cl 0.60 + 0.018*cl 0.57 + 0.018*cl t f 1.52 0.37 + 0.023*cl 0.38 + 0.023*cl 0.34 + 0.023*cl t plz 1.08 1.08 + 0.000*cl 1.08 + 0.000*cl 1.08 + 0.000*cl t phz 1.12 1.12 + 0.000*cl 1.12 + 0.000*cl 1.12 + 0.000*cl en to pad t plh 2.43 1.74 + 0.014*cl 1.82 + 0.013*cl 1.84 + 0.012*cl t phl 3.20 2.07 + 0.023*cl 2.16 + 0.021*cl 2.19 + 0.021*cl t r 1.48 0.60 + 0.018*cl 0.61 + 0.017*cl 0.57 + 0.018*cl t f 1.52 0.37 + 0.023*cl 0.35 + 0.023*cl 0.35 + 0.023*cl t plz 1.00 1.00 + 0.000*cl 1.00 + 0.000*cl 1.00 + 0.000*cl t phz 1.05 1.05 + 0.000*cl 1.05 + 0.000*cl 1.05 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-94 sec asic pvotyz tri-state output buffers KGM80 phot4sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 5.86 1.16 + 0.094*cl 1.17 + 0.094*cl 1.17 + 0.094*cl t phl 5.46 1.74 + 0.074*cl 1.75 + 0.074*cl 1.75 + 0.074*cl t r 10.83 0.24 + 0.212*cl 0.23 + 0.212*cl 0.24 + 0.212*cl t f 8.06 0.43 + 0.153*cl 0.38 + 0.153*cl 0.36 + 0.153*cl tn to pad t plh 4.17 1.20 + 0.059*cl 1.20 + 0.059*cl 1.20 + 0.059*cl t phl 7.07 1.90 + 0.103*cl 1.90 + 0.103*cl 1.91 + 0.103*cl t r 5.29 0.13 + 0.103*cl 0.11 + 0.103*cl 0.11 + 0.104*cl t f 6.69 0.18 + 0.130*cl 0.16 + 0.130*cl 0.16 + 0.130*cl t plz 1.77 1.77 + 0.000*cl 1.77 + 0.000*cl 1.77 + 0.000*cl t phz 1.26 1.26 + 0.000*cl 1.26 + 0.000*cl 1.26 + 0.000*cl en to pad t plh 4.33 1.36 + 0.059*cl 1.36 + 0.060*cl 1.37 + 0.059*cl t phl 7.24 2.07 + 0.103*cl 2.04 + 0.104*cl 2.07 + 0.103*cl t r 5.29 0.13 + 0.103*cl 0.11 + 0.103*cl 0.11 + 0.104*cl t f 6.69 0.17 + 0.130*cl 0.16 + 0.130*cl 0.16 + 0.130*cl t plz 1.71 1.70 + 0.000*cl 1.71 + 0.000*cl 1.71 + 0.000*cl t phz 1.18 1.18 + 0.000*cl 1.18 + 0.000*cl 1.18 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phot8sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.82 1.47 + 0.047*cl 1.48 + 0.047*cl 1.48 + 0.047*cl t phl 4.07 2.11 + 0.039*cl 2.18 + 0.038*cl 2.21 + 0.038*cl t r 5.58 0.35 + 0.105*cl 0.31 + 0.105*cl 0.29 + 0.105*cl t f 4.47 0.75 + 0.074*cl 0.72 + 0.075*cl 0.70 + 0.075*cl tn to pad t plh 2.99 1.49 + 0.030*cl 1.50 + 0.030*cl 1.50 + 0.030*cl t phl 4.98 2.31 + 0.053*cl 2.37 + 0.053*cl 2.38 + 0.052*cl t r 2.80 0.29 + 0.050*cl 0.26 + 0.051*cl 0.23 + 0.051*cl t f 3.50 0.31 + 0.064*cl 0.28 + 0.064*cl 0.25 + 0.065*cl t plz 1.76 1.74 + 0.000*cl 1.66 + 0.001*cl 1.76 + 0.000*cl t phz 1.25 1.25 + 0.000*cl 1.25 + 0.000*cl 1.25 + 0.000*cl en to pad t plh 3.15 1.65 + 0.030*cl 1.67 + 0.030*cl 1.67 + 0.030*cl t phl 5.14 2.48 + 0.053*cl 2.54 + 0.053*cl 2.56 + 0.052*cl t r 2.80 0.29 + 0.050*cl 0.26 + 0.051*cl 0.23 + 0.051*cl t f 3.50 0.31 + 0.064*cl 0.28 + 0.064*cl 0.25 + 0.065*cl t plz 1.71 1.70 + 0.000*cl 1.69 + 0.000*cl 1.69 + 0.000*cl t phz 1.18 1.18 + 0.000*cl 1.18 + 0.000*cl 1.18 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-95 kg80/KGM80 pvotyz tri-state output buffers KGM80 phot12sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 3.25 1.51 + 0.035*cl 1.52 + 0.035*cl 1.53 + 0.035*cl t phl 3.57 2.04 + 0.031*cl 2.13 + 0.029*cl 2.18 + 0.029*cl t r 4.22 0.41 + 0.076*cl 0.37 + 0.077*cl 0.35 + 0.077*cl t f 3.55 0.81 + 0.055*cl 0.83 + 0.055*cl 0.82 + 0.055*cl tn to pad t plh 2.63 1.50 + 0.023*cl 1.53 + 0.022*cl 1.55 + 0.022*cl t phl 4.30 2.26 + 0.041*cl 2.35 + 0.040*cl 2.39 + 0.039*cl t r 2.18 0.37 + 0.036*cl 0.32 + 0.037*cl 0.32 + 0.037*cl t f 2.69 0.39 + 0.046*cl 0.37 + 0.046*cl 0.33 + 0.047*cl t plz 1.99 1.99 + 0.000*cl 1.93 + 0.001*cl 2.05 + -0.001*cl t phz 1.42 1.42 + 0.000*cl 1.41 + 0.000*cl 1.42 + 0.000*cl en to pad t plh 2.80 1.67 + 0.022*cl 1.67 + 0.022*cl 1.71 + 0.022*cl t phl 4.47 2.42 + 0.041*cl 2.51 + 0.040*cl 2.55 + 0.039*cl t r 2.18 0.37 + 0.036*cl 0.33 + 0.037*cl 0.32 + 0.037*cl t f 2.69 0.38 + 0.046*cl 0.36 + 0.047*cl 0.34 + 0.047*cl t plz 1.92 1.92 + 0.000*cl 1.92 + 0.000*cl 1.84 + 0.001*cl t phz 1.35 1.35 + 0.000*cl 1.35 + 0.000*cl 1.35 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phot16sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.93 1.61 + 0.026*cl 1.65 + 0.026*cl 1.67 + 0.026*cl t phl 3.14 1.96 + 0.024*cl 2.05 + 0.023*cl 2.09 + 0.022*cl t r 3.29 0.54 + 0.055*cl 0.50 + 0.056*cl 0.50 + 0.055*cl t f 2.77 0.74 + 0.041*cl 0.77 + 0.040*cl 0.79 + 0.040*cl tn to pad t plh 2.45 1.56 + 0.018*cl 1.59 + 0.017*cl 1.67 + 0.016*cl t phl 3.72 2.16 + 0.031*cl 2.25 + 0.030*cl 2.30 + 0.029*cl t r 1.77 0.45 + 0.026*cl 0.46 + 0.026*cl 0.46 + 0.026*cl t f 2.07 0.38 + 0.034*cl 0.38 + 0.034*cl 0.36 + 0.034*cl t plz 2.19 2.23 + -0.001*cl 2.17 + 0.000*cl 2.11 + 0.001*cl t phz 1.56 1.56 + 0.000*cl 1.56 + 0.000*cl 1.56 + 0.000*cl en to pad t plh 2.61 1.73 + 0.018*cl 1.78 + 0.017*cl 1.80 + 0.017*cl t phl 3.89 2.32 + 0.031*cl 2.41 + 0.030*cl 2.47 + 0.029*cl t r 1.77 0.46 + 0.026*cl 0.47 + 0.026*cl 0.45 + 0.026*cl t f 2.07 0.38 + 0.034*cl 0.39 + 0.034*cl 0.36 + 0.034*cl t plz 2.12 2.10 + 0.000*cl 2.11 + 0.000*cl 2.11 + 0.000*cl t phz 1.49 1.49 + 0.000*cl 1.49 + 0.000*cl 1.49 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
kg80/KGM80 4-96 sec asic pvotyz tri-state output buffers KGM80 phot20sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.30 1.29 + 0.020*cl 1.30 + 0.020*cl 1.31 + 0.020*cl t phl 2.30 1.41 + 0.018*cl 1.46 + 0.017*cl 1.49 + 0.017*cl t r 2.53 0.36 + 0.043*cl 0.34 + 0.044*cl 0.31 + 0.044*cl t f 2.11 0.54 + 0.031*cl 0.56 + 0.031*cl 0.56 + 0.031*cl tn to pad t plh 1.98 1.30 + 0.013*cl 1.34 + 0.013*cl 1.34 + 0.013*cl t phl 2.76 1.57 + 0.024*cl 1.61 + 0.023*cl 1.64 + 0.023*cl t r 1.36 0.35 + 0.020*cl 0.32 + 0.021*cl 0.30 + 0.021*cl t f 1.58 0.26 + 0.026*cl 0.24 + 0.027*cl 0.22 + 0.027*cl t plz 1.25 1.24 + 0.000*cl 1.18 + 0.001*cl 1.31 + -0.001*cl t phz 1.05 1.05 + 0.000*cl 1.05 + 0.000*cl 1.05 + 0.000*cl en to pad t plh 2.14 1.47 + 0.013*cl 1.50 + 0.013*cl 1.51 + 0.013*cl t phl 2.92 1.74 + 0.024*cl 1.79 + 0.023*cl 1.83 + 0.023*cl t r 1.35 0.33 + 0.020*cl 0.34 + 0.020*cl 0.29 + 0.021*cl t f 1.59 0.28 + 0.026*cl 0.24 + 0.027*cl 0.22 + 0.027*cl t plz 1.18 1.15 + 0.001*cl 1.19 + 0.000*cl 1.19 + 0.000*cl t phz 0.97 0.97 + 0.000*cl 0.97 + 0.000*cl 0.97 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 phot24sm switching characteristics [delays for typical process, 25 c, 5.0v*, 3.3v*,when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* a to pad t plh 2.28 1.36 + 0.018*cl 1.40 + 0.018*cl 1.41 + 0.018*cl t phl 2.32 1.49 + 0.017*cl 1.56 + 0.016*cl 1.59 + 0.015*cl t r 2.33 0.44 + 0.038*cl 0.43 + 0.038*cl 0.41 + 0.038*cl t f 2.01 0.62 + 0.028*cl 0.66 + 0.027*cl 0.65 + 0.027*cl tn to pad t plh 1.98 1.35 + 0.013*cl 1.40 + 0.012*cl 1.42 + 0.012*cl t phl 2.75 1.65 + 0.022*cl 1.73 + 0.021*cl 1.76 + 0.021*cl t r 1.30 0.42 + 0.018*cl 0.43 + 0.017*cl 0.39 + 0.018*cl t f 1.47 0.32 + 0.023*cl 0.32 + 0.023*cl 0.31 + 0.023*cl t plz 1.25 1.24 + 0.000*cl 1.24 + 0.000*cl 1.25 + 0.000*cl t phz 1.05 1.05 + 0.000*cl 1.05 + 0.000*cl 1.05 + 0.000*cl en to pad t plh 2.14 1.52 + 0.013*cl 1.56 + 0.012*cl 1.58 + 0.012*cl t phl 2.92 1.80 + 0.022*cl 1.93 + 0.021*cl 1.94 + 0.020*cl t r 1.29 0.40 + 0.018*cl 0.43 + 0.017*cl 0.41 + 0.018*cl t f 1.47 0.33 + 0.023*cl 0.30 + 0.023*cl 0.31 + 0.023*cl t plz 1.18 1.18 + 0.000*cl 1.18 + 0.000*cl 1.17 + 0.000*cl t phz 0.97 0.97 + 0.000*cl 0.97 + 0.000*cl 0.97 + 0.000*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = =
sec asic 4-97 kg80/KGM80 bi-directional buffers cell list cell name function description kg80 pbadyz 5v open-drain bi-directional buffers pbaudyz 5v open-drain bi-directional buffers with pull-up pbatyz 5v tri-state bi-directional buffers pbadtyz 5v tri-state bi-directional buffers with pull-down pbautyz 5v tri-state bi-directional buffers with pull-up plbadyz 3.3v interface open-drain bi-directional buffers plbaudyz 3.3v interface open-drain bi-directional buffers with pull-up plbatyz 3.3v interface tri-state bi-directional buffers plbadtyz 3.3v interface tri-state bi-directional buffers with pull-down plbautyz 3.3v interface tri-state bi-directional buffers with pull-up KGM80 pbadyz 3.3v open-drain bi-directional buffers pbaudyz 3.3v open-drain bi-directional buffers with pull-up pbatyz 3.3v tri-state bi-directional buffers pbadtyz 3.3v tri-state bi-directional buffers with pull-down pbautyz 3.3v tri-state bi-directional buffers with pull-up phbadyz 5v interface open-drain bi-directional buffers phbaudyz 5v interface open-drain bi-directional buffers with pull-up phbatyz 5v interface tri-state bi-directional buffers phbadtyz 5v interface tri-state bi-directional buffers with pull-down phbautyz 5v interface tri-state bi-directional buffers with pull-up
kg80/KGM80 4-98 sec asic pvbadyz/pvbaudyz open drain bi-directional buffers pvbadyz pvbaudyz pa d tn en y po pi pa d tn en y po pi pvbatyz/pvbadtyz/pvbautyz tri-state bi-directional buffers pvbatyz pvbadtyz pvbautyz pa d a tn en y po pi pa d a tn en y po pi pa d a tn en y po pi
sec asic 4-99 kg80/KGM80 input clock drivers cell list cell name function description kg80 psckdc(2/4/8/12) 5v cmos level input clock drivers psckdcd(2/4/8/12) 5v cmos level input clock drivers with pull-down psckdcu(2/4/8/12) 5v cmos level input clock drivers with pull-up psckdl(2/4/8/12) 5v ttl schmitt trigger level input clock drivers psckdld(2/4/8/12) 5v ttl schmitt trigger level input clock drivers with pull-down psckdlu(2/4/8/12) 5v ttl schmitt trigger level input clock drivers with pull-up psckds(2/4/8/12) 5v cmos schmitt trigger level input clock drivers psckdsd(2/4/8/12) 5v cmos schmitt trigger level input clock drivers with pull-down psckdsu(2/4/8/12) 5v cmos schmitt trigger level input clock drivers with pull-up psckdt(2/4/8/12) 5v ttl level input clock drivers psckdtd(2/4/8/12) 5v ttl level input clock drivers with pull-down psckdtu(2/4/8/12) 5v ttl level input clock drivers with pull-up KGM80 psckdc(2/4/6/8) 3.3v cmos level input clock drivers psckdcd(2/4/6/8) 3.3v cmos level input clock drivers with pull-down psckdcu(2/4/6/8) 3.3v cmos level input clock drivers with pull-up psckds(2/4/6/8) 3.3v cmos schmitt trigger level input clock drivers psckdsd(2/4/6/8) 3.3v cmos schmitt trigger level input clock drivers with pull-down psckdsu(2/4/6/8) 3.3v cmos schmitt trigger level input clock drivers with pull-up
kg80/KGM80 4-100 sec asic psckdcy/psckdcdy/psckdcuy cmos level input clock drivers cell availability logic symbol library 5v operation 3.3v operation kg80 psckdc(2/4/8/12) psckdcd(2/4/8/12) psckdcu(2/4/8/12) C KGM80 C psckdc(2/4/6/8) psckdcd(2/4/6/8) psckdcu(2/4/6/8) y po pi pa d y po pi pa d y po pi pa d input load (sl) i/o slot kg80 pi psckdc(2/4/8/12) 1.6 psckdcd(2/4/8/12) 1.6 psckdcu(2/4/8/12) 1.6 KGM80 pi psckdc(2/4/6/8) 1.9 psckdcd(2/4/6/8) 1.9 psckdcu(2/4/6/8) 1.9 kg80/KGM80 psckdcy/psckdcdy/psckdcuy 1.0
sec asic 4-101 kg80/KGM80 psckdcy/psckdcdy/psckdcuy cmos level input clock drivers kg80 psckdc2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.70 0.24 + 0.005*sl 0.24 + 0.006*sl 0.24 + 0.005*sl t phl 0.64 0.22 + 0.005*sl 0.22 + 0.005*sl 0.22 + 0.005*sl t r 1.08 0.09 + 0.012*sl 0.08 + 0.012*sl 0.07 + 0.012*sl t f 0.84 0.08 + 0.009*sl 0.07 + 0.009*sl 0.06 + 0.009*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = kg80 psckdc4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.75 0.30 + 0.003*sl 0.30 + 0.003*sl 0.30 + 0.003*sl t phl 0.68 0.27 + 0.003*sl 0.27 + 0.003*sl 0.27 + 0.002*sl t r 1.07 0.10 + 0.006*sl 0.09 + 0.006*sl 0.08 + 0.006*sl t f 0.83 0.09 + 0.004*sl 0.08 + 0.005*sl 0.07 + 0.005*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = kg80 psckdc8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.76 0.32 + 0.001*sl 0.32 + 0.001*sl 0.32 + 0.001*sl t phl 0.73 0.32 + 0.001*sl 0.32 + 0.001*sl 0.32 + 0.001*sl t r 1.06 0.10 + 0.003*sl 0.09 + 0.003*sl 0.08 + 0.003*sl t f 0.82 0.10 + 0.002*sl 0.09 + 0.002*sl 0.07 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = kg80 psckdc12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 0.82 0.38 + 0.001*sl 0.38 + 0.001*sl 0.38 + 0.001*sl t phl 0.78 0.37 + 0.001*sl 0.38 + 0.001*sl 0.38 + 0.001*sl t r 1.06 0.13 + 0.002*sl 0.11 + 0.002*sl 0.10 + 0.002*sl t f 0.84 0.12 + 0.001*sl 0.11 + 0.001*sl 0.10 + 0.002*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
kg80/KGM80 4-102 sec asic psckdcy/psckdcdy/psckdcuy cmos level input clock drivers kg80 psckdcd2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.71 0.26 + 0.005*sl 0.25 + 0.006*sl 0.26 + 0.005*sl t phl 0.64 0.22 + 0.005*sl 0.23 + 0.005*sl 0.22 + 0.005*sl t r 1.08 0.09 + 0.012*sl 0.08 + 0.012*sl 0.08 + 0.012*sl t f 0.84 0.08 + 0.009*sl 0.07 + 0.009*sl 0.06 + 0.009*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = kg80 psckdcd4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.76 0.31 + 0.003*sl 0.31 + 0.003*sl 0.31 + 0.003*sl t phl 0.68 0.27 + 0.003*sl 0.27 + 0.003*sl 0.28 + 0.002*sl t r 1.07 0.10 + 0.006*sl 0.09 + 0.006*sl 0.08 + 0.006*sl t f 0.83 0.09 + 0.004*sl 0.08 + 0.005*sl 0.07 + 0.005*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = kg80 psckdcd8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.78 0.33 + 0.001*sl 0.33 + 0.001*sl 0.33 + 0.001*sl t phl 0.73 0.32 + 0.001*sl 0.33 + 0.001*sl 0.32 + 0.001*sl t r 1.06 0.10 + 0.003*sl 0.09 + 0.003*sl 0.08 + 0.003*sl t f 0.83 0.10 + 0.002*sl 0.08 + 0.002*sl 0.08 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = kg80 psckdcd12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 0.83 0.39 + 0.001*sl 0.39 + 0.001*sl 0.39 + 0.001*sl t phl 0.79 0.38 + 0.001*sl 0.38 + 0.001*sl 0.39 + 0.001*sl t r 1.06 0.12 + 0.002*sl 0.11 + 0.002*sl 0.10 + 0.002*sl t f 0.84 0.13 + 0.001*sl 0.11 + 0.001*sl 0.10 + 0.002*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
sec asic 4-103 kg80/KGM80 psckdcy/psckdcdy/psckdcuy cmos level input clock drivers kg80 psckdcu2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.70 0.25 + 0.005*sl 0.25 + 0.005*sl 0.25 + 0.005*sl t phl 0.64 0.23 + 0.005*sl 0.23 + 0.005*sl 0.23 + 0.005*sl t r 1.08 0.09 + 0.012*sl 0.08 + 0.012*sl 0.08 + 0.012*sl t f 0.84 0.08 + 0.009*sl 0.07 + 0.009*sl 0.06 + 0.009*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = kg80 psckdcu4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.75 0.30 + 0.003*sl 0.30 + 0.003*sl 0.30 + 0.003*sl t phl 0.69 0.27 + 0.003*sl 0.28 + 0.002*sl 0.27 + 0.003*sl t r 1.07 0.10 + 0.006*sl 0.09 + 0.006*sl 0.08 + 0.006*sl t f 0.83 0.09 + 0.004*sl 0.08 + 0.005*sl 0.07 + 0.005*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = kg80 psckdcu8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.77 0.32 + 0.001*sl 0.32 + 0.001*sl 0.32 + 0.001*sl t phl 0.74 0.33 + 0.001*sl 0.33 + 0.001*sl 0.33 + 0.001*sl t r 1.06 0.10 + 0.003*sl 0.09 + 0.003*sl 0.08 + 0.003*sl t f 0.83 0.10 + 0.002*sl 0.08 + 0.002*sl 0.08 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = kg80 psckdcu12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 0.82 0.38 + 0.001*sl 0.38 + 0.001*sl 0.38 + 0.001*sl t phl 0.79 0.38 + 0.001*sl 0.39 + 0.001*sl 0.39 + 0.001*sl t r 1.06 0.13 + 0.002*sl 0.11 + 0.002*sl 0.10 + 0.002*sl t f 0.83 0.12 + 0.001*sl 0.11 + 0.001*sl 0.09 + 0.002*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
kg80/KGM80 4-104 sec asic psckdcy/psckdcdy/psckdcuy cmos level input clock drivers KGM80 psckdc2 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 194 delay equations [ns] group1* group2* group3* pad to y t plh 1.14 0.36 + 0.004*sl 0.29 + 0.004*sl 0.30 + 0.004*sl t phl 0.95 0.31 + 0.003*sl 0.31 + 0.003*sl 0.32 + 0.003*sl t r 1.97 0.14 + 0.009*sl 0.11 + 0.010*sl 0.14 + 0.009*sl t f 1.31 0.11 + 0.006*sl 0.09 + 0.006*sl 0.08 + 0.006*sl *group1 : sl < 130, *group2 : 130 sl 194, *group3 : 194 < sl < < = = KGM80 psckdc4 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 385 delay equations [ns] group1* group2* group3* pad to y t plh 1.26 0.42 + 0.002*sl 0.42 + 0.002*sl 0.43 + 0.002*sl t phl 1.05 0.41 + 0.002*sl 0.42 + 0.002*sl 0.41 + 0.002*sl t r 1.96 0.16 + 0.005*sl 0.14 + 0.005*sl 0.13 + 0.005*sl t f 1.32 0.13 + 0.003*sl 0.15 + 0.003*sl 0.13 + 0.003*sl *group1 : sl < 257, *group2 : 257 sl 385, *group3 : 385 < sl < < = = KGM80 psckdc6 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 580 delay equations [ns] group1* group2* group3* pad to y t plh 1.23 0.39 + 0.001*sl 0.38 + 0.001*sl 0.39 + 0.001*sl t phl 1.05 0.41 + 0.001*sl 0.41 + 0.001*sl 0.41 + 0.001*sl t r 1.96 0.14 + 0.003*sl 0.11 + 0.003*sl 0.14 + 0.003*sl t f 1.33 0.23 + 0.002*sl 0.17 + 0.002*sl 0.14 + 0.002*sl *group1 : sl < 386, *group2 : 386 sl 580, *group3 : 580 < sl < < = = KGM80 psckdc8 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 770 delay equations [ns] group1* group2* group3* pad to y t plh 1.28 0.44 + 0.001*sl 0.44 + 0.001*sl 0.44 + 0.001*sl t phl 1.13 0.49 + 0.001*sl 0.49 + 0.001*sl 0.49 + 0.001*sl t r 1.95 0.15 + 0.002*sl 0.14 + 0.002*sl 0.14 + 0.002*sl t f 1.33 0.17 + 0.001*sl 0.12 + 0.002*sl 0.15 + 0.002*sl *group1 : sl < 514, *group2 : 514 sl 770, *group3 : 770 < sl < < = =
sec asic 4-105 kg80/KGM80 psckdcy/psckdcdy/psckdcuy cmos level input clock drivers KGM80 psckdcd2 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 194 delay equations [ns] group1* group2* group3* pad to y t plh 1.17 0.32 + 0.004*sl 0.31 + 0.004*sl 0.33 + 0.004*sl t phl 0.96 0.32 + 0.003*sl 0.32 + 0.003*sl 0.32 + 0.003*sl t r 1.97 0.14 + 0.009*sl 0.10 + 0.010*sl 0.15 + 0.009*sl t f 1.30 0.12 + 0.006*sl 0.09 + 0.006*sl 0.08 + 0.006*sl *group1 : sl < 130, *group2 : 130 sl 194, *group3 : 194 < sl < < = = KGM80 psckdcd4 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 385 delay equations [ns] group1* group2* group3* pad to y t plh 1.27 0.43 + 0.002*sl 0.43 + 0.002*sl 0.44 + 0.002*sl t phl 1.06 0.42 + 0.002*sl 0.42 + 0.002*sl 0.42 + 0.002*sl t r 1.96 0.16 + 0.005*sl 0.15 + 0.005*sl 0.14 + 0.005*sl t f 1.31 0.18 + 0.003*sl 0.12 + 0.003*sl 0.11 + 0.003*sl *group1 : sl < 257, *group2 : 257 sl 385, *group3 : 385 < sl < < = = KGM80 psckdcd6 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 580 delay equations [ns] group1* group2* group3* pad to y t plh 1.24 0.40 + 0.001*sl 0.40 + 0.001*sl 0.41 + 0.001*sl t phl 1.08 0.43 + 0.001*sl 0.43 + 0.001*sl 0.44 + 0.001*sl t r 1.96 0.15 + 0.003*sl 0.11 + 0.003*sl 0.13 + 0.003*sl t f 1.32 0.15 + 0.002*sl 0.10 + 0.002*sl 0.12 + 0.002*sl *group1 : sl < 386, *group2 : 386 sl 580, *group3 : 580 < sl < < = = KGM80 psckdcd8 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 770 delay equations [ns] group1* group2* group3* pad to y t plh 1.28 0.44 + 0.001*sl 0.44 + 0.001*sl 0.44 + 0.001*sl t phl 1.13 0.49 + 0.001*sl 0.50 + 0.001*sl 0.50 + 0.001*sl t r 1.96 0.16 + 0.002*sl 0.12 + 0.002*sl 0.15 + 0.002*sl t f 1.31 0.16 + 0.001*sl 0.16 + 0.001*sl 0.10 + 0.002*sl *group1 : sl < 514, *group2 : 514 sl 770, *group3 : 770 < sl < < = =
kg80/KGM80 4-106 sec asic psckdcy/psckdcdy/psckdcuy cmos level input clock drivers KGM80 psckdcu2 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 194 delay equations [ns] group1* group2* group3* pad to y t plh 1.15 0.29 + 0.004*sl 0.30 + 0.004*sl 0.31 + 0.004*sl t phl 0.96 0.32 + 0.003*sl 0.32 + 0.003*sl 0.32 + 0.003*sl t r 1.98 0.14 + 0.009*sl 0.11 + 0.010*sl 0.16 + 0.009*sl t f 1.31 0.11 + 0.006*sl 0.10 + 0.006*sl 0.09 + 0.006*sl *group1 : sl < 130, *group2 : 130 sl 194, *group3 : 194 < sl < < = = KGM80 psckdcu4 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 385 delay equations [ns] group1* group2* group3* pad to y t plh 1.26 0.42 + 0.002*sl 0.43 + 0.002*sl 0.43 + 0.002*sl t phl 1.06 0.42 + 0.002*sl 0.42 + 0.002*sl 0.42 + 0.002*sl t r 1.96 0.18 + 0.005*sl 0.13 + 0.005*sl 0.14 + 0.005*sl t f 1.31 0.15 + 0.003*sl 0.13 + 0.003*sl 0.11 + 0.003*sl *group1 : sl < 257, *group2 : 257 sl 385, *group3 : 385 < sl < < = = KGM80 psckdcu6 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 580 delay equations [ns] group1* group2* group3* pad to y t plh 1.23 0.39 + 0.001*sl 0.39 + 0.001*sl 0.39 + 0.001*sl t phl 1.07 0.43 + 0.001*sl 0.43 + 0.001*sl 0.44 + 0.001*sl t r 1.96 0.16 + 0.003*sl 0.13 + 0.003*sl 0.13 + 0.003*sl t f 1.32 0.16 + 0.002*sl 0.13 + 0.002*sl 0.13 + 0.002*sl *group1 : sl < 386, *group2 : 386 sl 580, *group3 : 580 < sl < < = = KGM80 psckdcu8 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 770 delay equations [ns] group1* group2* group3* pad to y t plh 1.28 0.45 + 0.001*sl 0.45 + 0.001*sl 0.45 + 0.001*sl t phl 1.13 0.49 + 0.001*sl 0.49 + 0.001*sl 0.50 + 0.001*sl t r 1.95 0.15 + 0.002*sl 0.15 + 0.002*sl 0.13 + 0.002*sl t f 1.32 0.17 + 0.001*sl 0.12 + 0.002*sl 0.13 + 0.002*sl *group1 : sl < 514, *group2 : 514 sl 770, *group3 : 770 < sl < < = =
sec asic 4-107 kg80/KGM80 psckdly/psckdldy/psckdluy ttl schmitt trigger level input clock drivers cell availability logic symbol library 5v operation 3.3v operation kg80 psckdl(2/4/8/12) psckdld(2/4/8/12) psckdlu(2/4/8/12) C KGM80 C C y po pi pa d y po pi pa d y po pi pa d input load (sl) i/o slot kg80 pi psckdl(2/4/8/12) 1.6 psckdld(2/4/8/12) 1.6 psckdlu(2/4/8/12) 1.6 kg80/KGM80 psckdly/psckdldy/psckdluy 1.0
kg80/KGM80 4-108 sec asic psckdly/psckdldy/psckdluy ttl schmitt trigger level input clock drivers kg80 psckdl2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.90 0.44 + 0.006*sl 0.45 + 0.005*sl 0.45 + 0.005*sl t phl 2.28 1.75 + 0.007*sl 1.79 + 0.006*sl 1.82 + 0.006*sl t r 1.09 0.13 + 0.012*sl 0.11 + 0.012*sl 0.10 + 0.012*sl t f 1.24 0.58 + 0.008*sl 0.58 + 0.008*sl 0.57 + 0.008*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = kg80 psckdl4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.99 0.53 + 0.003*sl 0.54 + 0.003*sl 0.54 + 0.003*sl t phl 2.94 2.36 + 0.004*sl 2.42 + 0.003*sl 2.46 + 0.003*sl t r 1.10 0.16 + 0.006*sl 0.15 + 0.006*sl 0.13 + 0.006*sl t f 1.48 0.83 + 0.004*sl 0.84 + 0.004*sl 0.84 + 0.004*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = kg80 psckdl8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.92 0.47 + 0.001*sl 0.47 + 0.001*sl 0.47 + 0.001*sl t phl 2.51 1.99 + 0.002*sl 2.03 + 0.001*sl 2.06 + 0.001*sl t r 1.08 0.14 + 0.003*sl 0.13 + 0.003*sl 0.12 + 0.003*sl t f 1.36 0.73 + 0.002*sl 0.73 + 0.002*sl 0.72 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = kg80 psckdl12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 1.01 0.55 + 0.001*sl 0.56 + 0.001*sl 0.57 + 0.001*sl t phl 3.22 2.65 + 0.001*sl 2.70 + 0.001*sl 2.74 + 0.001*sl t r 1.10 0.18 + 0.002*sl 0.17 + 0.002*sl 0.15 + 0.002*sl t f 1.64 1.02 + 0.001*sl 1.03 + 0.001*sl 1.03 + 0.001*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
sec asic 4-109 kg80/KGM80 psckdly/psckdldy/psckdluy ttl schmitt trigger level input clock drivers kg80 psckdld2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.91 0.46 + 0.006*sl 0.46 + 0.005*sl 0.46 + 0.005*sl t phl 2.29 1.76 + 0.007*sl 1.80 + 0.006*sl 1.83 + 0.006*sl t r 1.09 0.13 + 0.012*sl 0.11 + 0.012*sl 0.10 + 0.012*sl t f 1.24 0.58 + 0.008*sl 0.58 + 0.008*sl 0.57 + 0.008*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = kg80 psckdld4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 1.00 0.54 + 0.003*sl 0.55 + 0.003*sl 0.55 + 0.003*sl t phl 2.95 2.38 + 0.004*sl 2.43 + 0.003*sl 2.47 + 0.003*sl t r 1.10 0.16 + 0.006*sl 0.15 + 0.006*sl 0.13 + 0.006*sl t f 1.48 0.83 + 0.004*sl 0.85 + 0.004*sl 0.83 + 0.004*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = kg80 psckdld8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.93 0.48 + 0.001*sl 0.48 + 0.001*sl 0.48 + 0.001*sl t phl 2.53 2.00 + 0.002*sl 2.05 + 0.001*sl 2.08 + 0.001*sl t r 1.08 0.14 + 0.003*sl 0.13 + 0.003*sl 0.12 + 0.003*sl t f 1.36 0.73 + 0.002*sl 0.73 + 0.002*sl 0.72 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = kg80 psckdld12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 1.02 0.57 + 0.001*sl 0.58 + 0.001*sl 0.58 + 0.001*sl t phl 3.24 2.67 + 0.001*sl 2.72 + 0.001*sl 2.76 + 0.001*sl t r 1.10 0.19 + 0.002*sl 0.17 + 0.002*sl 0.15 + 0.002*sl t f 1.64 1.01 + 0.001*sl 1.03 + 0.001*sl 1.03 + 0.001*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
kg80/KGM80 4-110 sec asic psckdly/psckdldy/psckdluy ttl schmitt trigger level input clock drivers kg80 psckdlu2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.90 0.45 + 0.005*sl 0.45 + 0.005*sl 0.45 + 0.005*sl t phl 2.32 1.78 + 0.007*sl 1.83 + 0.006*sl 1.85 + 0.006*sl t r 1.09 0.13 + 0.012*sl 0.11 + 0.012*sl 0.10 + 0.012*sl t f 1.24 0.59 + 0.008*sl 0.58 + 0.008*sl 0.57 + 0.008*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = kg80 psckdlu4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.99 0.53 + 0.003*sl 0.54 + 0.003*sl 0.54 + 0.003*sl t phl 2.98 2.41 + 0.004*sl 2.47 + 0.003*sl 2.50 + 0.003*sl t r 1.10 0.16 + 0.006*sl 0.15 + 0.006*sl 0.13 + 0.006*sl t f 1.48 0.83 + 0.004*sl 0.85 + 0.004*sl 0.84 + 0.004*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = kg80 psckdlu8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.92 0.47 + 0.001*sl 0.47 + 0.001*sl 0.47 + 0.001*sl t phl 2.55 2.03 + 0.002*sl 2.07 + 0.001*sl 2.10 + 0.001*sl t r 1.08 0.14 + 0.003*sl 0.13 + 0.003*sl 0.12 + 0.003*sl t f 1.36 0.74 + 0.002*sl 0.74 + 0.002*sl 0.72 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = kg80 psckdlu12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 1.01 0.56 + 0.001*sl 0.57 + 0.001*sl 0.57 + 0.001*sl t phl 3.27 2.70 + 0.001*sl 2.75 + 0.001*sl 2.79 + 0.001*sl t r 1.10 0.18 + 0.002*sl 0.17 + 0.002*sl 0.15 + 0.002*sl t f 1.65 1.02 + 0.001*sl 1.04 + 0.001*sl 1.04 + 0.001*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
sec asic 4-111 kg80/KGM80 psckdsy/psckdsdy/psckdsuy cmos schmitt trigger level input clock drivers cell availability logic symbol library 5v operation 3.3v operation kg80 psckds(2/4/8/12) psckdsd(2/4/8/12) psckdsu(2/4/8/12) C KGM80 C psckds(2/4/6/8) psckdsd(2/4/6/8) psckdsu(2/4/6/8) y po pi pa d y po pi pa d y po pi pa d input load (sl) i/o slot kg80 pi psckds(2/4/8/12) 1.6 psckdsd(2/4/8/12) 1.6 psckdsu(2/4/8/12) 1.6 KGM80 pi psckds(2/4/6/8) 1.9 psckdsd(2/4/6/8) 1.9 psckdsu(2/4/6/8) 1.9 kg80/KGM80 psckdsy/psckdsdy/psckdsuy 1.0
kg80/KGM80 4-112 sec asic psckdsy/psckdsdy/psckdsuy cmos schmitt trigger level input clock drivers kg80 psckds2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.77 0.32 + 0.005*sl 0.31 + 0.006*sl 0.32 + 0.005*sl t phl 1.00 0.55 + 0.006*sl 0.57 + 0.005*sl 0.58 + 0.005*sl t r 1.09 0.11 + 0.012*sl 0.10 + 0.012*sl 0.09 + 0.012*sl t f 0.93 0.22 + 0.009*sl 0.21 + 0.009*sl 0.19 + 0.009*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = kg80 psckds4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.88 0.43 + 0.003*sl 0.43 + 0.003*sl 0.43 + 0.003*sl t phl 1.27 0.79 + 0.003*sl 0.82 + 0.003*sl 0.84 + 0.003*sl t r 1.09 0.15 + 0.006*sl 0.13 + 0.006*sl 0.12 + 0.006*sl t f 1.02 0.35 + 0.004*sl 0.34 + 0.004*sl 0.32 + 0.004*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = kg80 psckds8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.92 0.48 + 0.001*sl 0.48 + 0.001*sl 0.48 + 0.001*sl t phl 1.31 0.84 + 0.002*sl 0.87 + 0.001*sl 0.89 + 0.001*sl t r 1.08 0.15 + 0.003*sl 0.13 + 0.003*sl 0.12 + 0.003*sl t f 1.02 0.35 + 0.002*sl 0.34 + 0.002*sl 0.33 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = kg80 psckds12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 1.04 0.59 + 0.001*sl 0.59 + 0.001*sl 0.60 + 0.001*sl t phl 1.58 1.08 + 0.001*sl 1.12 + 0.001*sl 1.14 + 0.001*sl t r 1.11 0.19 + 0.002*sl 0.17 + 0.002*sl 0.15 + 0.002*sl t f 1.14 0.49 + 0.001*sl 0.48 + 0.001*sl 0.47 + 0.001*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
sec asic 4-113 kg80/KGM80 psckdsy/psckdsdy/psckdsuy cmos schmitt trigger level input clock drivers kg80 psckdsd2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.78 0.33 + 0.005*sl 0.33 + 0.005*sl 0.33 + 0.005*sl t phl 1.01 0.56 + 0.006*sl 0.58 + 0.005*sl 0.59 + 0.005*sl t r 1.09 0.11 + 0.012*sl 0.10 + 0.012*sl 0.09 + 0.012*sl t f 0.93 0.22 + 0.009*sl 0.21 + 0.009*sl 0.19 + 0.009*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = kg80 psckdsd4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.89 0.44 + 0.003*sl 0.44 + 0.003*sl 0.44 + 0.003*sl t phl 1.28 0.81 + 0.003*sl 0.83 + 0.003*sl 0.85 + 0.003*sl t r 1.09 0.15 + 0.006*sl 0.13 + 0.006*sl 0.12 + 0.006*sl t f 1.02 0.35 + 0.004*sl 0.34 + 0.004*sl 0.33 + 0.004*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = kg80 psckdsd8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.94 0.49 + 0.001*sl 0.50 + 0.001*sl 0.50 + 0.001*sl t phl 1.33 0.85 + 0.001*sl 0.88 + 0.001*sl 0.90 + 0.001*sl t r 1.08 0.15 + 0.003*sl 0.13 + 0.003*sl 0.12 + 0.003*sl t f 1.02 0.35 + 0.002*sl 0.34 + 0.002*sl 0.33 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = kg80 psckdsd12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 1.06 0.60 + 0.001*sl 0.61 + 0.001*sl 0.61 + 0.001*sl t phl 1.59 1.10 + 0.001*sl 1.13 + 0.001*sl 1.15 + 0.001*sl t r 1.11 0.19 + 0.002*sl 0.18 + 0.002*sl 0.16 + 0.002*sl t f 1.14 0.48 + 0.001*sl 0.48 + 0.001*sl 0.47 + 0.001*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
kg80/KGM80 4-114 sec asic psckdsy/psckdsdy/psckdsuy cmos schmitt trigger level input clock drivers kg80 psckdsu2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.78 0.32 + 0.005*sl 0.33 + 0.005*sl 0.32 + 0.005*sl t phl 1.01 0.56 + 0.006*sl 0.58 + 0.005*sl 0.58 + 0.005*sl t r 1.09 0.11 + 0.012*sl 0.10 + 0.012*sl 0.09 + 0.012*sl t f 0.93 0.22 + 0.009*sl 0.21 + 0.009*sl 0.20 + 0.009*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = kg80 psckdsu4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.89 0.44 + 0.003*sl 0.44 + 0.003*sl 0.44 + 0.003*sl t phl 1.28 0.80 + 0.003*sl 0.83 + 0.003*sl 0.85 + 0.003*sl t r 1.09 0.15 + 0.006*sl 0.13 + 0.006*sl 0.12 + 0.006*sl t f 1.03 0.35 + 0.004*sl 0.34 + 0.004*sl 0.33 + 0.004*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = kg80 psckdsu8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.93 0.48 + 0.001*sl 0.49 + 0.001*sl 0.49 + 0.001*sl t phl 1.33 0.85 + 0.002*sl 0.88 + 0.001*sl 0.90 + 0.001*sl t r 1.08 0.15 + 0.003*sl 0.13 + 0.003*sl 0.12 + 0.003*sl t f 1.02 0.35 + 0.002*sl 0.34 + 0.002*sl 0.33 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = kg80 psckdsu12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 1.05 0.59 + 0.001*sl 0.60 + 0.001*sl 0.61 + 0.001*sl t phl 1.60 1.10 + 0.001*sl 1.13 + 0.001*sl 1.16 + 0.001*sl t r 1.11 0.19 + 0.002*sl 0.17 + 0.002*sl 0.15 + 0.002*sl t f 1.14 0.49 + 0.001*sl 0.48 + 0.001*sl 0.47 + 0.001*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
sec asic 4-115 kg80/KGM80 psckdsy/psckdsdy/psckdsuy cmos schmitt trigger level input clock drivers KGM80 psckds2 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 194 delay equations [ns] group1* group2* group3* pad to y t plh 1.48 0.62 + 0.004*sl 0.63 + 0.004*sl 0.63 + 0.004*sl t phl 2.03 1.28 + 0.004*sl 1.34 + 0.004*sl 1.37 + 0.003*sl t r 2.01 0.23 + 0.009*sl 0.21 + 0.009*sl 0.18 + 0.009*sl t f 1.52 0.39 + 0.006*sl 0.39 + 0.006*sl 0.42 + 0.006*sl *group1 : sl < 130, *group2 : 130 sl 194, *group3 : 194 < sl < < = = KGM80 psckds4 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 385 delay equations [ns] group1* group2* group3* pad to y t plh 1.73 0.84 + 0.002*sl 0.87 + 0.002*sl 0.88 + 0.002*sl t phl 2.70 1.86 + 0.002*sl 1.93 + 0.002*sl 1.99 + 0.002*sl t r 2.07 0.32 + 0.005*sl 0.31 + 0.005*sl 0.30 + 0.005*sl t f 1.74 0.62 + 0.003*sl 0.64 + 0.003*sl 0.64 + 0.003*sl *group1 : sl < 257, *group2 : 257 sl 385, *group3 : 385 < sl < < = = KGM80 psckds6 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 580 delay equations [ns] group1* group2* group3* pad to y t plh 1.62 0.75 + 0.002*sl 0.77 + 0.001*sl 0.78 + 0.001*sl t phl 2.37 1.57 + 0.001*sl 1.64 + 0.001*sl 1.68 + 0.001*sl t r 2.03 0.28 + 0.003*sl 0.23 + 0.003*sl 0.24 + 0.003*sl t f 1.61 0.51 + 0.002*sl 0.48 + 0.002*sl 0.49 + 0.002*sl *group1 : sl < 386, *group2 : 386 sl 580, *group3 : 580 < sl < < = = KGM80 psckds8 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 770 delay equations [ns] group1* group2* group3* pad to y t plh 1.74 0.86 + 0.001*sl 0.89 + 0.001*sl 0.90 + 0.001*sl t phl 2.70 1.87 + 0.001*sl 1.94 + 0.001*sl 2.00 + 0.001*sl t r 2.06 0.30 + 0.002*sl 0.31 + 0.002*sl 0.28 + 0.002*sl t f 1.72 0.61 + 0.001*sl 0.63 + 0.001*sl 0.63 + 0.001*sl *group1 : sl < 514, *group2 : 514 sl 770, *group3 : 770 < sl < < = =
kg80/KGM80 4-116 sec asic psckdsy/psckdsdy/psckdsuy cmos schmitt trigger level input clock drivers KGM80 psckdsd2 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 194 delay equations [ns] group1* group2* group3* pad to y t plh 1.50 0.63 + 0.004*sl 0.65 + 0.004*sl 0.65 + 0.004*sl t phl 2.05 1.30 + 0.004*sl 1.35 + 0.004*sl 1.39 + 0.003*sl t r 2.01 0.23 + 0.009*sl 0.21 + 0.009*sl 0.18 + 0.009*sl t f 1.51 0.39 + 0.006*sl 0.42 + 0.006*sl 0.37 + 0.006*sl *group1 : sl < 130, *group2 : 130 sl 194, *group3 : 194 < sl < < = = KGM80 psckdsd4 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 385 delay equations [ns] group1* group2* group3* pad to y t plh 1.74 0.85 + 0.002*sl 0.89 + 0.002*sl 0.91 + 0.002*sl t phl 2.72 1.88 + 0.002*sl 1.96 + 0.002*sl 2.01 + 0.002*sl t r 2.07 0.31 + 0.005*sl 0.35 + 0.004*sl 0.28 + 0.005*sl t f 1.73 0.63 + 0.003*sl 0.63 + 0.003*sl 0.62 + 0.003*sl *group1 : sl < 257, *group2 : 257 sl 385, *group3 : 385 < sl < < = = KGM80 psckdsd6 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 580 delay equations [ns] group1* group2* group3* pad to y t plh 1.63 0.76 + 0.002*sl 0.78 + 0.001*sl 0.79 + 0.001*sl t phl 2.39 1.59 + 0.001*sl 1.66 + 0.001*sl 1.70 + 0.001*sl t r 2.03 0.26 + 0.003*sl 0.25 + 0.003*sl 0.22 + 0.003*sl t f 1.62 0.51 + 0.002*sl 0.48 + 0.002*sl 0.50 + 0.002*sl *group1 : sl < 386, *group2 : 386 sl 580, *group3 : 580 < sl < < = = KGM80 psckdsd8 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 770 delay equations [ns] group1* group2* group3* pad to y t plh 1.76 0.87 + 0.001*sl 0.90 + 0.001*sl 0.91 + 0.001*sl t phl 2.72 1.88 + 0.001*sl 1.96 + 0.001*sl 2.02 + 0.001*sl t r 2.06 0.32 + 0.002*sl 0.31 + 0.002*sl 0.26 + 0.002*sl t f 1.72 0.64 + 0.001*sl 0.62 + 0.001*sl 0.60 + 0.001*sl *group1 : sl < 514, *group2 : 514 sl 770, *group3 : 770 < sl < < = =
sec asic 4-117 kg80/KGM80 psckdsy/psckdsdy/psckdsuy cmos schmitt trigger level input clock drivers KGM80 psckdsu2 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 194 delay equations [ns] group1* group2* group3* pad to y t plh 1.49 0.63 + 0.004*sl 0.64 + 0.004*sl 0.65 + 0.004*sl t phl 2.05 1.29 + 0.004*sl 1.35 + 0.004*sl 1.38 + 0.003*sl t r 2.01 0.24 + 0.009*sl 0.19 + 0.009*sl 0.20 + 0.009*sl t f 1.52 0.40 + 0.006*sl 0.41 + 0.006*sl 0.39 + 0.006*sl *group1 : sl < 130, *group2 : 130 sl 194, *group3 : 194 < sl < < = = KGM80 psckdsu4 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 385 delay equations [ns] group1* group2* group3* pad to y t plh 1.74 0.85 + 0.002*sl 0.88 + 0.002*sl 0.89 + 0.002*sl t phl 2.72 1.88 + 0.002*sl 1.96 + 0.002*sl 2.02 + 0.002*sl t r 2.06 0.32 + 0.005*sl 0.32 + 0.005*sl 0.28 + 0.005*sl t f 1.74 0.64 + 0.003*sl 0.65 + 0.003*sl 0.63 + 0.003*sl *group1 : sl < 257, *group2 : 257 sl 385, *group3 : 385 < sl < < = = KGM80 psckdsu6 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 580 delay equations [ns] group1* group2* group3* pad to y t plh 1.63 0.76 + 0.002*sl 0.78 + 0.001*sl 0.78 + 0.001*sl t phl 2.38 1.59 + 0.001*sl 1.66 + 0.001*sl 1.70 + 0.001*sl t r 2.03 0.28 + 0.003*sl 0.23 + 0.003*sl 0.24 + 0.003*sl t f 1.61 0.51 + 0.002*sl 0.49 + 0.002*sl 0.49 + 0.002*sl *group1 : sl < 386, *group2 : 386 sl 580, *group3 : 580 < sl < < = = KGM80 psckdsu8 switching characteristics [delays for typical process, 25 c, 3.3v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 770 delay equations [ns] group1* group2* group3* pad to y t plh 1.75 0.87 + 0.001*sl 0.90 + 0.001*sl 0.91 + 0.001*sl t phl 2.72 1.88 + 0.001*sl 1.96 + 0.001*sl 2.02 + 0.001*sl t r 2.06 0.30 + 0.002*sl 0.30 + 0.002*sl 0.27 + 0.002*sl t f 1.72 0.62 + 0.001*sl 0.63 + 0.001*sl 0.61 + 0.001*sl *group1 : sl < 514, *group2 : 514 sl 770, *group3 : 770 < sl < < = =
kg80/KGM80 4-118 sec asic psckdty/psckdtdy/psckdtuy ttl level input clock drivers cell availability logic symbol library 5v operation 3.3v operation kg80 psckdt(2/4/8/12) psckdtd(2/4/8/12) psckdtu(2/4/8/12) C KGM80 C C y po pi pa d y po pi pa d y po pi pa d input load (sl) i/o slot kg80 pi psckdt(2/4/8/12) 1.6 psckdtd(2/4/8/12) 1.6 psckdtu(2/4/8/12) 1.6 kg80/KGM80 psckdty/psckdtdy/psckdtuy 1.0
sec asic 4-119 kg80/KGM80 psckdty/psckdtdy/psckdtuy ttl level input clock drivers kg80 psckdt2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.68 0.23 + 0.005*sl 0.22 + 0.006*sl 0.22 + 0.006*sl t phl 0.90 0.45 + 0.006*sl 0.47 + 0.005*sl 0.48 + 0.005*sl t r 1.08 0.08 + 0.012*sl 0.08 + 0.012*sl 0.07 + 0.012*sl t f 0.92 0.20 + 0.009*sl 0.19 + 0.009*sl 0.18 + 0.009*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = kg80 psckdt4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.72 0.27 + 0.003*sl 0.27 + 0.003*sl 0.27 + 0.003*sl t phl 1.13 0.65 + 0.003*sl 0.68 + 0.003*sl 0.70 + 0.003*sl t r 1.06 0.08 + 0.006*sl 0.07 + 0.006*sl 0.07 + 0.006*sl t f 1.01 0.33 + 0.004*sl 0.31 + 0.004*sl 0.31 + 0.004*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = kg80 psckdt8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.75 0.30 + 0.001*sl 0.30 + 0.001*sl 0.30 + 0.001*sl t phl 1.17 0.69 + 0.001*sl 0.72 + 0.001*sl 0.74 + 0.001*sl t r 1.05 0.08 + 0.003*sl 0.07 + 0.003*sl 0.07 + 0.003*sl t f 1.00 0.32 + 0.002*sl 0.32 + 0.002*sl 0.30 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = kg80 psckdt12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 0.78 0.34 + 0.001*sl 0.34 + 0.001*sl 0.34 + 0.001*sl t phl 1.39 0.89 + 0.001*sl 0.92 + 0.001*sl 0.95 + 0.001*sl t r 1.05 0.09 + 0.002*sl 0.08 + 0.002*sl 0.07 + 0.002*sl t f 1.12 0.45 + 0.001*sl 0.45 + 0.001*sl 0.44 + 0.001*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
kg80/KGM80 4-120 sec asic psckdty/psckdtdy/psckdtuy ttl level input clock drivers kg80 psckdtd2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.70 0.24 + 0.005*sl 0.24 + 0.006*sl 0.24 + 0.005*sl t phl 0.91 0.46 + 0.006*sl 0.48 + 0.005*sl 0.49 + 0.005*sl t r 1.08 0.08 + 0.012*sl 0.08 + 0.012*sl 0.07 + 0.012*sl t f 0.92 0.20 + 0.009*sl 0.20 + 0.009*sl 0.18 + 0.009*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = kg80 psckdtd4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.73 0.28 + 0.003*sl 0.28 + 0.003*sl 0.28 + 0.003*sl t phl 1.14 0.66 + 0.003*sl 0.69 + 0.003*sl 0.71 + 0.003*sl t r 1.06 0.08 + 0.006*sl 0.07 + 0.006*sl 0.07 + 0.006*sl t f 1.01 0.33 + 0.004*sl 0.32 + 0.004*sl 0.31 + 0.004*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = kg80 psckdtd8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.76 0.32 + 0.001*sl 0.31 + 0.001*sl 0.31 + 0.001*sl t phl 1.18 0.70 + 0.002*sl 0.73 + 0.001*sl 0.75 + 0.001*sl t r 1.05 0.09 + 0.003*sl 0.07 + 0.003*sl 0.07 + 0.003*sl t f 1.00 0.32 + 0.002*sl 0.32 + 0.002*sl 0.31 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = kg80 psckdtd12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 0.80 0.35 + 0.001*sl 0.35 + 0.001*sl 0.35 + 0.001*sl t phl 1.40 0.90 + 0.001*sl 0.93 + 0.001*sl 0.95 + 0.001*sl t r 1.05 0.09 + 0.002*sl 0.08 + 0.002*sl 0.07 + 0.002*sl t f 1.12 0.45 + 0.001*sl 0.45 + 0.001*sl 0.43 + 0.001*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
sec asic 4-121 kg80/KGM80 psckdty/psckdtdy/psckdtuy ttl level input clock drivers kg80 psckdtu2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 83 delay equations [ns] group1* group2* group3* pad to y t plh 0.68 0.23 + 0.005*sl 0.22 + 0.006*sl 0.23 + 0.005*sl t phl 0.91 0.46 + 0.006*sl 0.48 + 0.005*sl 0.49 + 0.005*sl t r 1.08 0.08 + 0.012*sl 0.07 + 0.012*sl 0.07 + 0.012*sl t f 0.92 0.20 + 0.009*sl 0.19 + 0.009*sl 0.19 + 0.009*sl *group1 : sl < 56, *group2 : 56 sl 83, *group3 : 83 < sl < < = = kg80 psckdtu4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 164 delay equations [ns] group1* group2* group3* pad to y t plh 0.72 0.27 + 0.003*sl 0.27 + 0.003*sl 0.27 + 0.003*sl t phl 1.14 0.66 + 0.003*sl 0.69 + 0.003*sl 0.71 + 0.003*sl t r 1.06 0.08 + 0.006*sl 0.07 + 0.006*sl 0.07 + 0.006*sl t f 1.01 0.33 + 0.004*sl 0.32 + 0.004*sl 0.31 + 0.004*sl *group1 : sl < 109, *group2 : 109 sl 164, *group3 : 164 < sl < < = = kg80 psckdtu8 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 325 delay equations [ns] group1* group2* group3* pad to y t plh 0.75 0.30 + 0.001*sl 0.30 + 0.001*sl 0.30 + 0.001*sl t phl 1.18 0.70 + 0.002*sl 0.73 + 0.001*sl 0.75 + 0.001*sl t r 1.05 0.08 + 0.003*sl 0.07 + 0.003*sl 0.07 + 0.003*sl t f 1.01 0.33 + 0.002*sl 0.32 + 0.002*sl 0.31 + 0.002*sl *group1 : sl < 217, *group2 : 217 sl 325, *group3 : 325 < sl < < = = kg80 psckdtu12 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 486 delay equations [ns] group1* group2* group3* pad to y t plh 0.78 0.34 + 0.001*sl 0.34 + 0.001*sl 0.34 + 0.001*sl t phl 1.40 0.90 + 0.001*sl 0.93 + 0.001*sl 0.96 + 0.001*sl t r 1.05 0.09 + 0.002*sl 0.08 + 0.002*sl 0.07 + 0.002*sl t f 1.12 0.46 + 0.001*sl 0.45 + 0.001*sl 0.44 + 0.001*sl *group1 : sl < 324, *group2 : 324 sl 486, *group3 : 486 < sl < < = =
kg80/KGM80 4-122 sec asic oscillators cell list logic symbol input load (sl) cell name function description kg80 psoscm1 oscillator with enable (1m ~ 10mhz) psoscm2 oscillator with enable (10m ~ 30mhz) psoscm3 oscillator with enable (30m ~ 60mhz) psoscm4 oscillator with enable (60m ~ 80mhz) psoscm5 oscillator with enable (80m ~ 100mhz) psoscm6 oscillator with enable (50m ~ 100mhz) KGM80 psoscm1 oscillator with enable (1m ~ 10mhz) psoscm2 oscillator with enable (10m ~ 30mhz) psoscm3 oscillator with enable (30m ~ 60mhz) psoscm4 oscillator with enable (60m ~ 80mhz) psoscm5 oscillator with enable (80m ~ 100mhz) kg80 e psoscm(1/2/3/4/5/6) 2.7 KGM80 e psoscm(1/2/3/4/5) 2.7 yn e pa da pa dy truth table sec tester standard real application i/o slot pada e pady yn 0011 0111 10xx 1100 pada e pady yn 0011 0111 1011 1100 kg80 psoscm(1/2/3/4/5/6) 2.0 KGM80 psoscm(1/2/3/4/5) 2.0
sec asic 4-123 kg80/KGM80 psoscm(1/2/3/4/5/6) oscillators with enable kg80 psoscm1 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.50ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 2.67 0.12 + 0.051*cl 0.11 + 0.051*cl 0.11 + 0.051*cl t phl 4.01 0.14 + 0.078*cl 0.13 + 0.078*cl 0.13 + 0.078*cl t r 5.88 0.11 + 0.115*cl 0.10 + 0.115*cl 0.10 + 0.116*cl t f 8.21 0.13 + 0.162*cl 0.13 + 0.162*cl 0.13 + 0.162*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 psoscm1 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.50ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.21 0.21 + 0.003*sl 0.21 + 0.002*sl 0.19 + 0.004*sl t phl 0.25 0.25 + 0.006*sl 0.26 + 0.004*sl 0.25 + 0.005*sl t r 0.08 0.08 + 0.004*sl 0.09 + 0.004*sl 0.10 + 0.002*sl t f 0.07 0.07 + 0.007*sl 0.08 + 0.003*sl 0.08 + 0.003*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = kg80 psoscm2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.50ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 2.67 0.12 + 0.051*cl 0.11 + 0.051*cl 0.11 + 0.051*cl t phl 4.01 0.14 + 0.078*cl 0.13 + 0.078*cl 0.13 + 0.078*cl t r 5.88 0.11 + 0.115*cl 0.10 + 0.115*cl 0.10 + 0.116*cl t f 8.21 0.13 + 0.162*cl 0.13 + 0.162*cl 0.13 + 0.162*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 psoscm2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.50ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.21 0.21 + 0.003*sl 0.21 + 0.002*sl 0.19 + 0.004*sl t phl 0.25 0.25 + 0.006*sl 0.26 + 0.004*sl 0.25 + 0.005*sl t r 0.08 0.08 + 0.004*sl 0.09 + 0.004*sl 0.10 + 0.002*sl t f 0.07 0.07 + 0.007*sl 0.08 + 0.003*sl 0.08 + 0.003*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 4-124 sec asic psoscm(1/2/3/4/5/6) oscillators with enable kg80 psoscm3 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.50ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 1.38 0.11 + 0.026*cl 0.11 + 0.025*cl 0.10 + 0.026*cl t phl 2.06 0.13 + 0.039*cl 0.12 + 0.039*cl 0.12 + 0.039*cl t r 2.98 0.11 + 0.057*cl 0.10 + 0.058*cl 0.10 + 0.058*cl t f 4.14 0.11 + 0.081*cl 0.11 + 0.081*cl 0.10 + 0.081*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 psoscm3 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.50ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.19 0.19 + 0.003*sl 0.19 + 0.003*sl 0.19 + 0.003*sl t phl 0.23 0.23 + 0.003*sl 0.23 + 0.004*sl 0.23 + 0.004*sl t r 0.10 0.10 + -0.001*sl 0.09 + 0.001*sl 0.08 + 0.003*sl t f 0.08 0.08 + 0.003*sl 0.08 + 0.003*sl 0.08 + 0.003*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = kg80 psoscm4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.50ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 0.74 0.11 + 0.013*cl 0.10 + 0.013*cl 0.10 + 0.013*cl t phl 1.09 0.13 + 0.019*cl 0.12 + 0.019*cl 0.12 + 0.019*cl t r 1.55 0.13 + 0.028*cl 0.11 + 0.029*cl 0.11 + 0.029*cl t f 2.12 0.12 + 0.040*cl 0.11 + 0.040*cl 0.11 + 0.040*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 psoscm4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.50ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.20 0.20 + 0.002*sl 0.21 + 0.002*sl 0.21 + 0.002*sl t phl 0.25 0.25 + 0.003*sl 0.25 + 0.002*sl 0.25 + 0.002*sl t r 0.10 0.10 + 0.002*sl 0.10 + 0.001*sl 0.10 + 0.001*sl t f 0.08 0.08 + 0.002*sl 0.08 + 0.003*sl 0.09 + 0.002*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 4-125 kg80/KGM80 psoscm(1/2/3/4/5/6) oscillators with enable kg80 psoscm5 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.50ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 0.53 0.10 + 0.009*cl 0.11 + 0.008*cl 0.11 + 0.008*cl t phl 0.77 0.13 + 0.013*cl 0.13 + 0.013*cl 0.12 + 0.013*cl t r 1.08 0.15 + 0.019*cl 0.13 + 0.019*cl 0.13 + 0.019*cl t f 1.45 0.13 + 0.027*cl 0.12 + 0.027*cl 0.11 + 0.027*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 psoscm5 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.50ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.20 0.20 + 0.001*sl 0.20 + 0.002*sl 0.20 + 0.001*sl t phl 0.24 0.24 + 0.002*sl 0.24 + 0.002*sl 0.24 + 0.002*sl t r 0.10 0.10 + 0.001*sl 0.10 + 0.001*sl 0.10 + 0.001*sl t f 0.08 0.08 + 0.001*sl 0.08 + 0.002*sl 0.08 + 0.002*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = kg80 psoscm6 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.50ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 0.42 0.09 + 0.006*cl 0.10 + 0.006*cl 0.11 + 0.006*cl t phl 0.61 0.12 + 0.010*cl 0.13 + 0.010*cl 0.13 + 0.010*cl t r 0.85 0.16 + 0.014*cl 0.14 + 0.014*cl 0.14 + 0.014*cl t f 1.12 0.14 + 0.020*cl 0.12 + 0.020*cl 0.12 + 0.020*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = kg80 psoscm6 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.50ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.23 0.23 + 0.001*sl 0.23 + 0.001*sl 0.23 + 0.001*sl t phl 0.27 0.27 + 0.001*sl 0.27 + 0.001*sl 0.27 + 0.001*sl t r 0.12 0.12 + 0.001*sl 0.12 + 0.001*sl 0.12 + 0.001*sl t f 0.10 0.10 + 0.001*sl 0.10 + 0.001*sl 0.10 + 0.001*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 4-126 sec asic psoscm(1/2/3/4/5) oscillators with enable KGM80 psoscm1 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 2.72 0.13 + 0.052*cl 0.13 + 0.052*cl 0.13 + 0.052*cl t phl 3.62 0.13 + 0.070*cl 0.14 + 0.070*cl 0.13 + 0.070*cl t r 5.93 0.11 + 0.116*cl 0.11 + 0.116*cl 0.10 + 0.116*cl t f 7.85 0.13 + 0.154*cl 0.13 + 0.154*cl 0.13 + 0.154*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 psoscm1 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.22 0.22 + 0.004*sl 0.22 + 0.003*sl 0.22 + 0.003*sl t phl 0.24 0.24 + 0.005*sl 0.23 + 0.005*sl 0.24 + 0.003*sl t r 0.10 0.10 + 0.001*sl 0.10 + 0.001*sl 0.08 + 0.004*sl t f 0.08 0.08 + 0.003*sl 0.08 + 0.004*sl 0.09 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl 6, *group3 : 6 < sl < < = = KGM80 psoscm2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 2.72 0.13 + 0.052*cl 0.13 + 0.052*cl 0.13 + 0.052*cl t phl 3.62 0.13 + 0.070*cl 0.14 + 0.070*cl 0.13 + 0.070*cl t r 5.93 0.11 + 0.116*cl 0.11 + 0.116*cl 0.10 + 0.116*cl t f 7.85 0.13 + 0.154*cl 0.13 + 0.154*cl 0.13 + 0.154*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 psoscm2 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.22 0.22 + 0.004*sl 0.22 + 0.003*sl 0.22 + 0.003*sl t phl 0.24 0.24 + 0.005*sl 0.23 + 0.005*sl 0.24 + 0.003*sl t r 0.10 0.10 + 0.001*sl 0.10 + 0.001*sl 0.08 + 0.004*sl t f 0.08 0.08 + 0.003*sl 0.08 + 0.004*sl 0.09 + 0.002*sl *group1 : sl < 3, *group2 : 3 sl 6, *group3 : 6 < sl < < = =
sec asic 4-127 kg80/KGM80 psoscm(1/2/3/4/5) oscillators with enable KGM80 psoscm3 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 1.41 0.12 + 0.026*cl 0.12 + 0.026*cl 0.12 + 0.026*cl t phl 1.87 0.12 + 0.035*cl 0.12 + 0.035*cl 0.12 + 0.035*cl t r 3.00 0.10 + 0.058*cl 0.09 + 0.058*cl 0.09 + 0.058*cl t f 3.96 0.11 + 0.077*cl 0.11 + 0.077*cl 0.10 + 0.077*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 psoscm3 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.19 0.19 + 0.003*sl 0.19 + 0.002*sl 0.19 + 0.002*sl t phl 0.21 0.21 + 0.002*sl 0.21 + 0.003*sl 0.22 + 0.002*sl t r 0.10 0.10 + 0.002*sl 0.09 + 0.003*sl 0.11 + 0.001*sl t f 0.08 0.08 + 0.004*sl 0.09 + 0.001*sl 0.10 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 6, *group3 : 6 < sl < < = = KGM80 psoscm4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 0.76 0.12 + 0.013*cl 0.12 + 0.013*cl 0.12 + 0.013*cl t phl 0.99 0.12 + 0.017*cl 0.11 + 0.017*cl 0.12 + 0.017*cl t r 1.54 0.10 + 0.029*cl 0.09 + 0.029*cl 0.09 + 0.029*cl t f 2.02 0.10 + 0.038*cl 0.10 + 0.038*cl 0.10 + 0.038*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 psoscm4 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.22 0.22 + 0.001*sl 0.22 + 0.001*sl 0.22 + 0.001*sl t phl 0.23 0.23 + 0.001*sl 0.23 + 0.001*sl 0.23 + 0.001*sl t r 0.11 0.11 + 0.000*sl 0.11 + 0.000*sl 0.11 + 0.001*sl t f 0.09 0.09 + 0.001*sl 0.09 + 0.000*sl 0.09 + 0.001*sl *group1 : sl < 3, *group2 : 3 sl 6, *group3 : 6 < sl < < = =
kg80/KGM80 4-128 sec asic psoscm(1/2/3/4/5) oscillators with enable KGM80 psoscm5 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (cl : capacitive load [pf]) path parameter delay [ns] cl = 50.0pf delay equations [ns] group1* group2* group3* pada to pady t plh 0.55 0.11 + 0.009*cl 0.11 + 0.009*cl 0.12 + 0.009*cl t phl 0.70 0.12 + 0.012*cl 0.12 + 0.012*cl 0.11 + 0.012*cl t r 1.06 0.10 + 0.019*cl 0.09 + 0.019*cl 0.09 + 0.019*cl t f 1.38 0.10 + 0.025*cl 0.10 + 0.026*cl 0.09 + 0.026*cl *group1 : cl < 75, *group2 : 75 cl 85, *group3 : 85 < cl < < = = KGM80 psoscm5 switching characteristics [delays for typical process, 25 c, 5.0v, when t , t = 0.40ns] o r f (sl : standard load) path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* pada to yn t plh 0.22 0.22 + 0.001*sl 0.22 + 0.001*sl 0.22 + 0.001*sl t phl 0.23 0.23 + 0.001*sl 0.23 + 0.001*sl 0.23 + 0.001*sl t r 0.11 0.11 + 0.001*sl 0.11 + 0.000*sl 0.11 + 0.000*sl t f 0.10 0.10 + 0.001*sl 0.10 + 0.000*sl 0.10 + 0.000*sl *group1 : sl < 3, *group2 : 3 sl 6, *group3 : 6 < sl < < = =
sec asic 4-129 kg80/KGM80 pci buffers overview pci buffers are designed for pci local bus application which is an industry-standard, high-performance 32- or 64-bit bus architecture. sec asic supports 5v and 3.3v signalling environment pci bi-directional buffers including a universal buffer. the universal buffer requires a select control (en3v) signal. en3v pin should be tied to the voltage detector output directly. features C high performance C low cost C easy use C longevity: both 5v and 3.3v signalling environments speci?ed. general description the pci buffers signalling environment is controlled by en3v pin which is logically low in a 5v operation and logically high in a 3.3v operation. if you use a voltage detector cell with the pci buffer, you have to connect this en3v pin to vdet (voltage detector) output. do not use a level shifter buffer (plscb). cell list cell name function description kg80 psipcia 5v pci input buffer psopcia 5v pci output buffer plsipcia internal 5v/external 3.3v pci input buffer plsopcia internal 5v/external 3.3v pci output buffer psipciau universal pci input buffer psopciau universal pci output buffer KGM80 psipcia3 3.3v pci input buffer psopcia3 3.3v pci output buffer phsipcia internal 3.3v/external 5v pci input buffer phsopcia internal 3.3v/external 5v pci output buffer psipciau universal pci input buffer psopciau universal pci output buffer
kg80/KGM80 4-130 sec asic pci buffers electrical characteristics sec asic guarantees pci buffers electrical characteristics under all conditions (v cc = 3.6v, temp. = 0 c ~ v cc = 3.0v, temp. = 125 c). 5v dc speci?cations 5v ac speci?cations notes: 1. equation a :i oh = 11.9 * (v out C 5.25) * (v out + 2.45) for v cc > v out > 3.1v 2. equation b :i ol = 78.5 * v out * (4.4 C v out ) for 0v < v out < 0.71v 3. the minimum slew rate (slowest signal edge) is guaranteed. the maximum slew rate (fastest signal edge) is a guideline, and rise and fall times faster than the maximum can occur. designers should ensure that signal integrity modelling includes the potential for rise and fall times faster than the maximum shown in the table. symbol parameter condition min max unit v cc supply voltage 4.75 5.25 v v il input low voltage C0.5 0.8 v ih input high voltage 2.0 v cc + 0.5 i il input low leakage current v in = 0.5 C70 m a i ih input high leakage current v in = 2.7 70 v ol output low voltage i out = 3ma, 6ma 0.55 v v oh output high voltage i out = e2ma 2.4 c in input pin capacitance 10 pf c clk clk pin capacitance 5 12 c idsel idsel pin capacitance 8 l pin pin inductance 20 nh symbol parameter condition min max unit i oh (ac) switching current high 0 < v out 1.4 e44 ma 1.4 < v out < 2.4 e44 (vout e 1.4) / 0.024 3.1 < v out < v cc eqt?n a 1 (test point) v out = 3.1 e142 i ol (ac) switching current low v out 3 2.2 95 2.2 > v out > 0.55 v out /0.023 0.71 > v out > 0 eqt?n b 2 (test point) v out = 0.71 206 i cl low clamp current e5 < v in e1 e25 + (v in + 1) / 0.015 slew r 3 output rise slew rate 0.4v to 2.4v load 1 5 v/ns slew f 3 output fall slew rate 2.4v to 0.4v load 1 5
sec asic 4-131 kg80/KGM80 pci buffers 3.3v dc characteristics 3.3v ac characteristics notes: 1. equation c :i oh = (98.0 / v cc ) * (v out C v cc ) * (v out + 0.4v cc ) for v cc > v out > 0.7v 2. equation d :i ol = (256 / v cc ) * v out * (v cc C v out ) for 0v < v out < 0.18v cc 3. the minimum slew rate (slowest signal edge) is guaranteed. the maximum slew rate (fastest signal edge) is a guideline, and rise and fall times faster than the maximum can occur. designers should ensure that signal integrity modelling includes the potential for rise and fall times faster than the maximum shown in the table. symbol parameter condition min max unit v cc supply voltage 3.0 3.6 v v il input low voltage C0.5 0.3v cc v v ih input high voltage 0.5v cc v cc + 0.5 v v ipu input pull-up voltage 0.7v cc v i il input leakage current 0 < v in < v cc 10 m a v ol output low voltage i out = 1500 m a 0.1v cc v v oh output high voltage i out = e500 m a 0.9v cc v c in input pin capacitance 10 pf c clk clk pin capacitance 5 12 pf c idsel idsel pin capacitance 8 pf l pin pin inductance 20 nh symbol parameter condition min max unit i oh (ac) switching current high 0 < v out 0.3v cc e12v cc ma 0.3v cc < v out < 0.9v cc e17.1 (v cc e v out )ma 0.7v cc < v out < v cc eqt?n c 1 (test point) v out = 0.7v cc e32v cc ma i ol (ac) switching current low v cc > v out 3 0.6v cc 16v cc ma 0.6v cc > v out > 0.1v cc 26.7v out ma 0.18v cc > v out > 0 eqt?n d 2 (test point) v out = 0.18v cc 38v cc ma i cl low clamp current e3 < v in e1 e25 + (v in + 1) / 0.015 ma i ch high clamp current v cc + 4 > v in 3 v cc + 1 25 + (v in e v cc e 1) / 0.015 ma slew r 3 output rise slew rate 0.2v cc to 0.6v cc load 1 4 v/ns slew f 3 output fall slew rate 0.6v cc to 0.2v cc load 1 4 v/ns
kg80/KGM80 4-132 sec asic psipcia/plsipcia/psipcia3/phsipcia pci input buffers logic symbol input load (sl) kg80 tn en a pi psipcia/plsipcia 1.0 1.6 3.6 1.0 KGM80 tn en a pi psipcia3/phsipcia 1.0 1.6 3.6 1.0 pa d y po pi truth table input truth table output truth table i/o slot pa d p i y p o 1110 0x01 1011 aentnpad 0010 1011 x 1 x hi-z x x 0 hi-z kg80/KGM80 psipcia/plsipcia psipcia3/phsipcia 1.0
sec asic 4-133 kg80/KGM80 psopcia/plsopcia/psopcia3/phsopcia pci output buffers logic symbol input load (sl) kg80 tn en a pi psopcia/plsopcia 1.0 1.6 3.6 1.0 KGM80 tn en a pi psopcia3/phsopcia 1.0 1.6 3.6 1.0 pa d a tn en truth table input truth table output truth table i/o slot pa d p i y p o 1110 0x01 1011 aentnpad 0010 1011 x 1 x hi-z x x 0 hi-z kg80/KGM80 psopcia/plsopcia psopcia3/phsopcia 1.0
kg80/KGM80 4-134 sec asic psipciau universal pci input buffer logic symbol input load (sl) kg80/KGM80 tn en a pi psipciau 1.0 1.6 3.6 1.0 pa d y po pi en3v truth table input truth table output truth table * en3v (active-high) enables the 3.3v mode. i/o slot pa d p i y p o 1110 0x01 1011 aentnpad 0010 1011 x 1 x hi-z x x 0 hi-z kg80/KGM80 psipciau 1.0
sec asic 4-135 kg80/KGM80 psopciau universal pci output buffer logic symbol input load (sl) kg80/KGM80 tn en a pi psopciau 1.0 1.6 3.6 1.0 pa d a tn en en3v truth table input truth table output truth table * en3v (active-high) enables the 3.3v mode. i/o slot pa d p i y p o 1110 0x01 1011 aentnpad 0010 1011 x 1 x hi-z x x 0 hi-z kg80/KGM80 psopciau 1.0
kg80/KGM80 4-136 sec asic pcmcia buffers overview pc card technology is used in a wide variety of products including notebook computers, palmtop computers, pen computers, desktop computers, printers, telephones, medical instruments and others embedded application hosts. for pcmcia interface, sec asic supports various kinds of pcmcia buffers. these pcmcia buffers enable you to C maintain interface conditions and speed independent of battery voltage C allow groups of card interface input buffers to be powered down C use a voltage detector cell C select pull-up/pull-down option (50k/100k/200k, default = 100k). general description all of pcmcia buffers are controlled by s3v5v signal that is logically low in a 5v operation and logically high in a 3.3v operation. if you use a voltage detector cell with a pcmcia buffer, you have to connect the s3v5v pin to vdet (voltage detector) output. logic levels notes: 1. pcmcia input buffer is ttl compatible. 2. pcmcia output buffer has a balanced t r & t f . parameter min max v ih 2.0v v il 0.8v v oh 2.4v v ol 0.5v
sec asic 4-137 kg80/KGM80 pcmcia buffers cell list cell name function description kg80/KGM80 pvic(5/3) 5v/3.3v cmos level pcmcia input buffers pvil(5/3) 5v/3.3v ttl schmitt trigger level pcmcia input buffers pvild(5/3) 5v/3.3v ttl schmitt trigger level pcmcia input buffers with pull-down pvilu(5/3) 5v/3.3v ttl schmitt trigger level pcmcia input buffers with pull-up pvit(5/3) 5v/3.3v ttl level pcmcia input buffers pvitd(5/3) 5v/3.3v ttl level pcmcia input buffers with pull-down pvitu(5/3) 5v/3.3v ttl level pcmcia input buffers with pull-up pvob4(5/3) 5v/3.3v 4ma pcmcia output buffers without src pvob8(5/3) 5v/3.3v 8ma pcmcia output buffers without src pvob12(5/3) 5v/3.3v 12ma pcmcia output buffers without src pvod4(5/3) 5v/3.3v 4ma open-drain pcmcia output buffers without src pvod8(5/3) 5v/3.3v 8ma open-drain pcmcia output buffers without src pvod12(5/3) 5v/3.3v 12ma open-drain pcmcia output buffers without src pvot4(5/3) 5v/3.3v 4ma tri-state pcmcia output buffers without src pvot8(5/3) 5v/3.3v 8ma tri-state pcmcia output buffers without src pvot12(5/3) 5v/3.3v 12ma tri-state pcmcia output buffers without src pvot8sm(5/3) 5v/3.3v 8ma tri-state pcmcia output buffers with src pvot12sm(5/3) 5v/3.3v 12ma tri-state pcmcia output buffers with src pvbtt4(5/3) 5v/3.3v 4ma pcmcia bi-directional buffers without src pvbtt8(5/3) 5v/3.3v 8ma pcmcia bi-directional buffers without src pvbtt12(5/3) 5v/3.3v 12ma pcmcia bi-directional buffers without src pvbtdt8sm(5/3) 5v/3.3v 8ma pcmcia bi-directional buffers with src, pull-down pvbct8sm(5/3) 5v/3.3v 8ma pcmcia bi-directional buffers with src
kg80/KGM80 4-138 sec asic pcmcia buffers naming conventions pcmcia input buffers (pvi a b v) pcmcia output buffers (pvo x y z v) pcmcia bi-directional buffers (pvb a b x y z v) ab c cmos level none no resistor l ttl schmitt trigger level d pull-down resistor s cmos schmitt trigger level u pull-up resistor t ttl level y x 4 4ma drive b normal buffer 8 8ma drive d open-drain buffer 12 12ma drive t tri-state buffer v z 55v none no slew-rate control (fastest) 3 3.3v sm medium slew-rate control sh high slew-rate control
sec asic 4-139 kg80/KGM80 pvic(5/3) cmos level pcmcia input buffers logic symbol pin connection truth table cell availability input output pa d pi y po pa d p i y p o 1110 0x01 1011 5v operation 3.3v operation pvic5 pvic3 y po pi pa d pvil(d/u)(5/3)/pvit(d/u)(5/3) ttl level pcmcia input buffers logic symbol pin connection truth table cell availability input output pa d pi s3v5v y po pa d p i y p o 1110 0x01 1011 5v operation 3.3v operation pvil5 pvil3 pvild5 pvild3 pvilu5 pvilu3 pvit5 pvit3 pvitd5 pvitd3 pvitu5 pvitu3 s3v5v y po pi pa d
kg80/KGM80 4-140 sec asic pvob(4/8/12)(5/3) pcmcia output buffers logic symbol pin connection truth table cell availability input output a s3v5v pa d apad 00 11 5v operation 3.3v operation pvob45 pvob43 pvob85 pvob83 pvob125 pvob123 pa d a s3v5v pvod(4/8/12)(5/3) open drain pcmcia output buffers logic symbol pin connection truth table cell availability input output tn en s3v5v pa d tn en pad 100 0 x hi-z x 1 hi-z 5v operation 3.3v operation pvod45 pvod43 pvod85 pvod83 pvod125 pvod123 pa d s3v5v tn en
sec asic 4-141 kg80/KGM80 pvot(4/8/12)(5/3) tri-state pcmcia output buffers logic symbol pin connection truth table cell availability input output tn en a s3v5v pa d tn en a pad 1000 1011 x 1 x hi-z 0 x x hi-z 5v operation 3.3v operation pvot45 pvot43 pvot85 pvot83 pvot125 pvot123 pa d a s3v5v tn en pvot(8/12)sm(5/3) tri-state pcmcia output buffers logic symbol pin connection truth table cell availability input output tn en a s3v5v pa d tn en a pad 1000 1011 x 1 x hi-z 0 x x hi-z 5v operation 3.3v operation pvot8sm5 pvot8sm3 pvot12sm5 pvot12sm3 pa d a s3v5v tn en
kg80/KGM80 4-142 sec asic pvbtt(4/8/12)(5/3) pcmcia bi-directional buffers logic symbol pin connection cell availability input output tn en a s3v5v pi pa d y po 5v operation 3.3v operation pvbtt45 pvbtt43 pvbtt85 pvbtt83 pvbtt125 pvbtt123 pa d a tn en y po pi s3v5v pvbtdt8sm/pvbct8sm(5/3) pcmcia bi-directional buffers logic symbol pin connection cell availability input output tn en a s3v5v pi pa d y po 5v operation 3.3v operation pvbtdt8sm5 pvbtdt8sm3 pvbct8sm5 pvbct8sm3 pa d a tn en y po pi s3v5v
sec asic 4-143 kg80/KGM80 cardbus i/o buffers overview cardbus i/o buffers have 3.3v operation, 32-bit bus width and 33mhz of transmission speed. the latest version of the pc card standard adds information to improve compatibility with the standard by requiring a card information structure (cis) on every pc card. the standard has also been enhanced to support the following optional features: C low-voltage only operation (3.3v) C hardware direct memory access (dma) C multiple-function cards C industry standard power management interface (apm) C high throughput 32-bit bus mastering interface (cardbus) sec asic supports nine different cardbus i/o buffers. if necessary, a voltage detector cell can be used with them. for maximum ?exibility, cardbus i/o buffers have not only a level shifter but also a pull-up enable control pin. cardbus i/o buffers have only 3.3v electrical speci?cations, however, we can support 5v/3.3v ?exible operation by using of a level shifter. regardless of the i/o voltage, s3v5v pin controls the same input level and output driving current. s3v5v pin should be tied to the voltage detector in a mixed system, or ground in a 3.3v-only system. we can not attribute a level shifter to puen (pull-up enable) pin, because we have only four level shifters. in order to control the puen pin with an internal signal, you should use the level shifter butter (plscb) in a mixed system. for minimizing power consumption, cardbus i/o buffers have a nand type input with a control pin. therefore, the input buffers operate as active-high input buffers. however, if the control pin is in low state, the output y is low and not tri-state. general description the cardbus i/o buffer is controlled by s3v5v signal that is logically low in a 5v operation and logically high in a 3.3v operation. if you use a voltage detector cell with the cardbus i/o buffer, you have to connect this s3v5v pin to vdet (voltage detector) output. do not use a level shifter buffer (plscb). cstschg buffer speci?cation the cstschg pin can be used by the cardbus pc card to remotely power up the system. the design of the cardbus pc cards output buffer and the systems input buffer must ensure no electrical damage results. C an output buffer for cstschg pin never exceed 1ma. C an input buffer for cstschg pin is able to withstand sustained forward bias current of 1ma. cclk speci?cation the electrical characteristics of cclk follows 3.3v signalling of pci local bus speci?cation revision 2.1. refer to the pci buffer electrical characteristics.
kg80/KGM80 4-144 sec asic cardbus i/o buffers cell list cell name function description kg80 plitcbu 3.3v interface universal ttl cardbus input buffer with pull-up plotcbu 3.3v interface tri-state cardbus output buffer with pull-up plotcckcbu 3.3v interface tri-state cardbus output clock driver with pull-up plotcvscbu 3.3v interface tri-state output card voltage sense with pull-up plodcckcbu 3.3v interface open drain cardbus output clock driver with pull-up plbttcbu 3.3v interface tri-state cardbus bi-directional buffer with pull-up plbtcckcbu 3.3v interface cardbus bi-directional clock driver with pull-up plbtcvscbu 3.3v interface tri-state bi-directional card voltage sense with pull-up plbdcckcbu 3.3v interface open drain cardbus bi-directional clock driver with pull-up plscb 3.3v interface level shifter buffer KGM80 pitcbu universal ttl cardbus input buffer with pull-up potcbu tri-state cardbus output buffer with pull-up potcckcbu tri-state cardbus output clock driver with pull-up potcvscbu tri-state output card voltage sense with pull-up podcckcbu open drain cardbus output clock driver with pull-up pbttcbu tri-state cardbus bi-directional buffer with pull-up pbtcckcbu cardbus bi-directional clock driver with pull-up pbtcvscbu tri-state bi-directional card voltage sense with pull-up pbdcckcbu open drain cardbus bi-directional clock driver with pull-up plscb level shifter buffer
sec asic 4-145 kg80/KGM80 cardbus i/o buffers electrical characteristics (normal cardbus interface type buffers) 3.3v dc speci?cations notes: 1. this is determined solely by the maximum current capacity of the v cc pins on the connector. 2. input leakage currents include high-z output leakage for all bi-directional buffers with high-z outputs. ccd1#, ccd2#, cvs1 and cvs2 do not have to meet leakage requirements. 3.3v ac speci?cations note: 1. this does not apply to cclk . minimum and maximum rates are measured with the minimum capacitive load a driver will see (7pf). the values ensure the fastest edge rate will not switch rail-to-rail faster than 3.6ns. symbol parameter condition min max unit v cc supply voltage 3.0 3.6 v v ih input high voltage 0.475v cc v cc + 0.5 v il input low voltage C0.5 0.325v cc v oh output high voltage i out = C150 m a 0.9v cc v ol output low voltage i out = 700 m a 0.1v cc i cc 1 supply current 1 a i il 2 input leakage current 0 < v in < v cc 10 m a symbol parameter condition min max unit t rcb 1 output rise time 0.2v cc C 0.6v cc 0.25 1.0 v/ns t fcb 1 output fall time 0.6v cc C 0.2v cc 0.25 1.0 i cl low clamp current C3 < v in < C1 C25 + (v in + 1) / 0.015 ma i ch high clamp current v cc + 4 > v in > v cc + 1 25 + (v in C v cc C 1) / 0.015
kg80/KGM80 4-146 sec asic pvitcbu universal ttl cardbus input buffer with pull-up cell availability logic symbol library 5v operation 3.3v operation kg80 C plitcbu KGM80 C pitcbu level shifter pa d level shifter y po c s3v5v puen pi truth table * puen (pull-up control pin) is low enable. cell data pad c pi y po 11110 01x01 11011 x0x01 input load (sl) i/o slot cpi 1.0 4.0 1.6
sec asic 4-147 kg80/KGM80 pvotcbu/pvotcckcbu/pvotcvscbu tri-state cardbus output buffers with pull-up cell availability logic symbol plotcbu/plotcckcbu plotcvscbu library 5v operation 3.3v operation kg80 C plotcbu/plotcckcbu/plotcvscbu KGM80 C potcbu/potcckcbu/potcvscbu pa d level shifter level shifter tn en a puen s3v5v pa d level shifter level shifter tn en a puen truth table * puen (pull-up control pin) is low enable. cell data aentnpad 0010 1011 x 1 x hi-z x x 0 hi-z input load (sl) i/o slot a en tn puen 1.0 2.3 1.2 1.2 0.5
kg80/KGM80 4-148 sec asic pvodcckcbu open drain cardbus output clock driver with pull-up cell availability logic symbol library 5v operation 3.3v operation kg80 C plodcckcbu KGM80 C podcckcbu pa d level shifter tn en puen truth table * puen (pull-up control pin) is low enable. cell data en tn pad 010 1 x hi-z x 0 hi-z input load (sl) i/o slot en tn puen 1.0 1.2 1.2 0.5
sec asic 4-149 kg80/KGM80 pvbttcbu/pvbtcckcbu/pvbtcvscbu cardbus bi-directional buffers with pull-up cell availability logic symbol plbttcbu/plbtcckcbu plbtcvscbu library 5v operation 3.3v operation kg80 C plbttcbu/plbtcckcbu/plbtcvscbu KGM80 C podcckcbu pa d level shifter tn en puen level shifter level shifter level shifter pi po c y a s3v5v pa d level shifter tn en puen level shifter level shifter level shifter pi po c y a s3v5v truth table input truth table output truth table * puen (pull-up control pin) is low enable. cell data pad c pi y po 11110 01x01 11011 x0x01 aentnpad 0010 1011 x 1 x hi-z x x 0 hi-z input load (sl) i/o slot a en tn puen c pi 1.0 2.3 1.2 1.2 0.5 4.0 1.6
kg80/KGM80 4-150 sec asic pvbdcckcbu open drain cardbus bi-directional clock driver with pull-up cell availability logic symbol library 5v operation 3.3v operation kg80 C plbdcckcbu KGM80 C pbdcckcbu pa d level shifter tn en puen level shifter level shifter pi po c y s3v5v truth table input truth table output truth table * puen (pull-up control pin) is low enable. cell data pad c pi y po 11110 01x01 11011 x0x01 en tn pad 010 1 x hi-z x 0 hi-z input load (sl) i/o slot en tn puen c pi 1.0 1.2 1.2 0.5 4.0 1.6
sec asic 4-151 kg80/KGM80 plscb level shifter buffer cell availability logic symbol library 5v operation 3.3v operation kg80 C plscb KGM80 C plscb x1 z1 z2 x2 truth table cell data xn zn 00 1 (vddxi) 1 (vddxo) input load (sl) i/o slot x1 x2 1.0 2.4 2.4
kg80/KGM80 4-152 sec asic voltage detector C under development (available in january 1997) cell list ! caution: this voltage detector can be used in gate array as an embedded cell only. logic symbol * y pin should be connected to s3v5v pin directly. do not use a level shifter buffer (plscb). cell name function description vdet voltage detector reset y pin connection truth table * if i/o supply voltage is 3.3v, output y is high state. input output reset y reset y 00 1 0 (1) *
sec asic 4-153 kg80/KGM80 power pads cell list logic symbol cell name function description kg80 vdd power pads vss power pads vdd5i vss5i 5v internal vdd5p vss5p 5v pre-driver vdd5o vss5o 5v output-driver vdd5ip vss5ip 5v internal and pre-driver vdd5oi vss5oi 5v output-driver and internal vdd5op vss5op 5v output-driver and pre-driver vdd5t vss5t 5v total vdd3p vss3p 3.3v pre-driver vdd3o vss3o 3.3v output-driver vdd3op vss3op 3.3v output-driver and pre-driver KGM80 vdd power pads vss power pads vdd3i vss3i 3.3v internal vdd3p vss3p 3.3v pre-driver vdd3o vss3o 3.3v output-driver vdd3ip vss3ip 3.3v internal and pre-driver vdd3oi vss3oi 3.3v output-driver and internal vdd3op vss3op 3.3v output-driver and pre-driver vdd3t vss3t 3.3v total vdd5p vss5p 5v pre-driver vdd5o vss5o 5v output-driver vdd5op vss5op 5v output-driver and pre-driver
memory compilers 5
contents overview .............................................................................................................................. 5-1 rom ..................................................................................................................................... 5-2 ram ..................................................................................................................................... 5-7 1r1w dpram ..................................................................................................................... 5-13 1rw1r dpram ................................................................................................................... 5-19 fifo ..................................................................................................................................... 5-27 multiplier ............................................................................................................................... 5-29
memory compilers overview sec asic 5-1 kg80/KGM80 overview this chapter contains information for kg80/KGM80 memory compilers such as rom, single-port ram, dual-port rams, ram-based fifo and multiplier generators. cell names & function descriptions cell name function description rom asynchronous/synchronous rom generator ram asynchronous single-port ram generator 1r1w dpram asynchronous one read one write dual-port ram generator 1rw1r dpram asynchronous one read/write one read dual-port ram generator fifo ram-based first-in first-out memory generator multiplier multiplier generator
kg80/KGM80 5-2 sec asic rom asynchronous/synchronous rom generator logic symbol note : in kg80 re pin should be tied to vdd. description this is a high-speed, low-power rom with fully static and asynchronous operation, and one read address port and one data output port. the number of words and word width can be con?gured with the memgen memory compiler. rom code is contact layer programmable. four rom architectures (type 1, 2, 3 and 4) support variable cell aspect ratios consistent with word/bit con?guration limitations. features ? zero standby power ? high speed ? contact programmable rom code ? asynchronous and fully static operation ? parameter-driven compiler ? up to 36k bit block i/o pin description block diagram name i/o i/o cap. [pf] description addr0...addrkC1 i 0.042 read address re i 0.021 read enable dout0...doutnC1 o 0.041 data output rom addr0...addrkC1 dout0...doutnC1 k: n: the number of address bits the number of data bits re cell array column mux output buffer decoder addr [(kC1): 0] dout [(nC1):0] re ? variable word depth C 8, 16, 24, 32, 40,..., 256 ? variable word width C 4, 5, 6, 7, 8,..., 144 ? available architectures C type1, type 2, type 3 and type 4
sec asic 5-3 kg80/KGM80 rom asynchronous/synchronous rom generator gate count gate count = height x width size = (height x 19.0) x (width x 6.0) height calculation height = (words / (4 x type)) + a if (type = 1), then a = 7 else a = 5 width calculation width = type x bits x 2 + 1 + div (type x bits / 25) + b a = words / (2 x type) < example: rom32 x 19 (type = 2) > height = {32 / (4 x 2)} + 5 = 9 width = 2 x 19 x 2 + 1 + 1 + 8 = 86 gate count = (9 x 86) arrays size = (9 x 19.0) x (86 x 6.0) microns the table below shows the number of gates used for representative roms. although architecture type also affects the number of gates, this table shows the number of gates for type 2. gate counts for representative roms 1234 width<36 width>=36 width<18 width>=18 width<12 width>=12 width<9 width>=9 4 b = 5 b = 7 b = 7 b = 7 b = 9 b = 11 b = 10 b = 11 8 b = 6 b = 8 b = 7 b = 8 b = 9 b = 11 b = 10 b = 11 12 b = 8 b = 10 b = 8 b = 10 b = 9 b = 11 b = 10 b = 11 16 b = 8 b = 10 b = 8 b = 10 b = 9 b = 11 b = 10 b = 11 20 ~ 32 b = 10 b = 12 b = 10 b = 12 b = 10 b = 12 b = 10 b = 12 36 ~ 128 b = 11 b = 13 b = 11 b = 13 b = 11 b = 13 b = 11 b = 11 32 64 128 160 192 256 8 360 533 903 1100 1276 1628 16 657 9628 1596 1925 2233 2849 24 954 1404 2310 2775 3219 4107 32 1251 1833 3003 3600 4176 5328 36 1395 2745 3339 4000 4640 5920 a type bit word
kg80/KGM80 5-4 sec asic rom asynchronous/synchronous rom generator memgen-supported rom con?gurations note : parentheses indicate incomplete address decoding. address pin words type 1 (4 ~ 144) type 2 (4 ~ 72) type 3 (4 ~ 48) type 4 (4 ~ 36) 38o 416o o 5 (24) o o 32 o o o 6 (40) o (48) o o o (56) o 64 o o o 7 (72) o (80) o o (88) o (96) o o o o (104) o (112) o o (120) o 128 o o 8 (136) o (144) o o (152) o (160) o o o (168) o (176) o o (184) o (192) o o o o (200) o (208) o o (216) o (224) o o o (232) o (240) o o (248) o 256 o o o
sec asic 5-5 kg80/KGM80 rom asynchronous/synchronous rom generator ac parameters timing diagram read cycle note : re pin is tied to vdd. <KGM80> kg80 (typical process, 25?c, 5v, t r / t f = 1.2ns, sl = 20) symbol parameter tpd (ns) 32x8 (type=2) 128x8 (type=2) 256x8 (type=2) t rc read cycle time 2.401 3.012 3.468 t aa address access time 3.430 4.035 4.465 t oh output hold time from address change 1.000 1.000 1.000 KGM80 (typical process, 25?c, 3.3v, t r / t f = 1.2ns, sl = 20) symbol parameter tpd (ns) 32x8 (type=2) 128x8 (type=2) 256x8 (type=2) t rp read cycle time 1.160 1.160 1.160 t as address setup time 1.905 2.807 3.459 t ah address hold time 1.000 1.000 1.000 t re read enable access time 3.094 3.094 3.094 addr t rc t aa valid address dout valid data previous data t oh addr t re dout t as t rp t ah re valid address valid data
kg80/KGM80 5-6 sec asic rom asynchronous/synchronous rom generator architecture type 1 type 2 type 3 type 4 shortest word line longest bit line for type 1, the speci?ed number of words will equal the number of rows and the speci?ed number of bits will equal the number of columns in the rom array. for the same size rom, type 2 will have one-half the speci?ed number of rows and twice the speci?ed number of columns. for the same size rom, type 3 will have one-third the speci?ed number of rows and three times the speci?ed number of columns. longest word line shortest for the same size rom, type 4 will have one-fourth the speci?ed number of rows and four times the speci?ed number of columns. bit line rom rom rom rom
sec asic 5-7 kg80/KGM80 ram asynchronous single-port ram generator logic symbol description this is a high-speed, low-power, single-port ram with fully static and asynchronous operation. the number of words and word width can be con?gured with the memgen memory compiler. the design has one read/ write address port, one data input port, and one data output port. control pins are oen (output enable) and wen (write enable). during write operation, the data output port re?ects data at the input port if the output tri-state buffers are enabled. four ram architectures (type 1, 2, 3 and 4) support varying aspect ratios consistent with word/bit con?guration limitations. features ? 1 read/write address port ? 1 data input and 1 data output port ? zero standby power ? high speed ? asynchronous and fully static operation ? tri-state output buffers ? parameter-driven compiler ? up to 9k bit block i/o pin description truth table name i/o i/o cap. [pf] description din0...dinnC1 i 0.021 data input addr0...addrkC1 i 0.042 read/write address wen i 0.042 write enable memory write operation is enabled when wen is low. oen i 0.021 output enable when oen is high, the outputs are in high impedance state. when oen is low, the data outputs are enabled. dout0...doutnC1 o 0.042 data output wen oen mode l x write x l read x h output = high impedance ram addr0...addrkC1 dout0...doutnC1 k: n: the number of address bits the number of data bits din0...dinnC1 wen oen ? variable word depth C 8, 16, 24, 32, 40,..., 256 ? variable word width C 4, 5, 6, 7, 8,..., 72 ? available architectures C type1, type 2, type 3 and type 4
kg80/KGM80 5-8 sec asic ram asynchronous single-port ram generator block diagram gate count gate count = height x width size = (height x 19.0) x (width x 6.0) height calculation height = (bits x type) + a if (words / type = 8), then a = 5 else if {(words / type > 8) and (words / type < 72), then a = 6 else if (words / type >= 72), then a = 7 width calculation width = 3 x (words / type) + 2 + b if (type = 1), then b = 9 else if (type = 2), then b = 17 else if (type = 3), then b = 15 else if (type = 4), then b = 14 < example: ram176 x 16 (type = 2) > height = (16 x 2) +7 = 39 width = 3 x (176 / 2) + 2 + 17 = 283 gate count = (39 x 283) arrays size = (39 x 19.0) x (283 x 6.0) microns the table below shows the number of gates used for representative rams. although architecture type also affects the number of gates, this table shows the number of gates for type 2. gate counts for representative rams 16 32 64 128 160 256 8 903 1474 2530 4642 5957 9269 16 1591 2546 4370 8018 10101 15717 24 2279 3618 6210 11394 14245 22165 32 2967 4690 8050 14770 18389 28613 36 3311 5226 8970 16458 20461 31837 cell array column mux output decoder addr [(kC1): 0] dout [(nC1):0] buffer input buffer wen oen read/write control din [(nC1):0] bit word
sec asic 5-9 kg80/KGM80 ram asynchronous single-port ram generator memgen-supported ram con?gurations note : parentheses indicate incomplete address decoding. address pin words type 1 (4 ~ 72) type 2 (4 ~ 36) type 3 (4 ~ 24) type 4 (4 ~ 18) 38o 416o o 5 (24) o o 32 o o o 6 (40) o (48) o o o (56) o 64 o o o 7 (72) o (80) o o (88) o (96) o o o o (104) o (112) o o (120) o 128 o o o 8 (144) o (160) o o (176) o (192) o o o (208) o (224) o o (240) o 256 o o
kg80/KGM80 5-10 sec asic ram asynchronous single-port ram generator ac parameters kg80 (typical process, 25?c, 5v, t r / t f = 1.2ns, sl = 20) symbol parameter tpd (ns) 32x8 (type=2) 128x8 (type=2) 256x8 (type=2) read cycle t rc read cycle time 2.510 3.845 5.709 t aa address access time 3.104 4.457 6.334 t oh (a) output hold time from address change 1.000 1.000 1.000 t oe output enable time 1.188 1.188 1.188 t olz output enable to output low-z 0.734 0.734 0.734 t ohz output disable to output high-z 0.364 0.364 0.364 write cycle t wc write cycle time 3.358 4.989 9.199 t wa write enable access time 3.969 5.599 7.809 t da data-in access time 2.903 4.681 7.002 t wp write enable pulse width 2.314 2.777 3.428 t as address setup time 0.652 1.844 3.460 t ah address hold time 0.000 0.518 1.347 t dw data-in setup time 0.000 0.000 0.000 t dh data-in hold time 0.726 0.817 1.055 t oh (d) output hold time from din change 1.000 1.000 1.000 t oh (w) output hold time from wen change 0.588 0.578 0.565 KGM80 (typical process, 25?c, 3.3v, t r / t f = 1.2ns, sl = 20) symbol parameter tpd (ns) 32x8 (type=2) 128x8 (type=2) 256x8 (type=2) read cycle t rc read cycle time 3.454 5.180 7.613 t aa address access time 4.165 5.345 8.364 t oh (a) output hold time from address change 1.000 1.000 1.000 t oe output enable time 1.604 1.604 1.604 t olz output enable to output low-z 0.929 0.929 0.929 t ohz output disable to output high-z 0.561 0.561 0.561 write cycle t wc write cycle time 4.703 6.754 9.501 t wa write enable access time 5.429 7.480 10.228 t da data-in access time 3.883 6.116 9.053 t wp write enable pulse width 3.141 3.603 4.369 t as address setup time 0.978 2.593 4.813 t ah address hold time 0.187 0.982 2.121 t dw data-in setup time 0.000 0.000 0.000 t dh data-in hold time 1.224 1.498 1.960 t oh (d) output hold time from din change 1.000 1.000 1.000 t oh (w) output hold time from wen change 0.857 0.840 0.817
sec asic 5-11 kg80/KGM80 ram asynchronous single-port ram generator timing diagram read cycle write cycle addr t rc t aa valid address dout valid data t oh (a) oen t oe t olz t ohz a1(valid address) t as t wp t dw t da d1 (data-in valid) d1 (data valid) addr wen oen din dout t wa t dh t oh (a) t aa d (a1) d0 d0 t ah t wc * d (an): data which are stored in an address a0 a2 t oh (w) t oh (d) d (a0)
kg80/KGM80 5-12 sec asic ram asynchronous single-port ram generator architecture type 1 type 2 type 3 type 4 shortest bit line longest word line for type 1, the speci?ed number of words will equal the number of columns and the speci?ed number of bits will equal the number of rows in the ram array. for the same size ram, type 2 will have twice the speci?ed number of columns and one-half the speci?ed number of rows. for the same size ram, type 3 will have three times the speci?ed number of columns and one-third the speci?ed number of rows. longest bit line shortest for the same size ram, type 4 will have four times the speci?ed number of columns and one-fourth the speci?ed number of rows. word line ram ram ram ram
sec asic 5-13 kg80/KGM80 1r1w dpram asynchronous one read one write dual-port ram generator logic symbol description this high-speed, low-power, 1r1w dual-port ram has fully static and asynchronous operation. the number of words and word width can be con?gured with the memgenembedded memory compiler. the design has one read address port and one write address port, and one data input port and one data output port. control pins are oen (output enable) and wen (write enable). during a write operation, the data output ports re?ect the data which are stored in the read address, if the output tri-state buffers are enabled. four ram architectures (type 1, 2, 4 and 8) support varying aspect ratios consistent with word/bit con?guration limitations. features ? fully asynchronous read/write operation ? variable size dual-port ram with 1 read and 1 write address port, 1 data input and 1 data output port ? zero stand-by power ? high speed ? tri-state output buffers ? parameter-driven compiler ? up to 9k bit block i/o pin description truth table name i/o i/o cap. [pf] description din0...dinnC1 i 0.021 data input addrw0...addrwkC1 addrr0...addrrkC1 i 0.021 read/write address input wen i 0.042 read/write control oen i 0.021 tri-state control dout0...doutnC1 o 0.098 data output wen oen mode l x write x l read x h output = high impedance addrw0...addrwkC1 dout0...doutnC1 k: n: the number of address the number of data din0...dinnC1 wen oen addrr0...addrrkC1 dpram 1r1w ? variable word depth C 8, 16, 24, 32, 40,..., 1024 ? variable word width C 4, 5, 6, 7, 8,..., 72 ? available architectures C type1, type 2, type 4 and type 8
kg80/KGM80 5-14 sec asic 1r1w dpram asynchronous one read one write dual-port ram generator block diagram gate count gate count = height x width size = (height x 19.0) x (width x 6.0) height calculation height = (bits x type) + 2 x a + b a = div (type / 2) if (words / type = 8), then b = 8 else if {(words / type > 8) and (words / type < 40), then b = 9 else if {(words / type > 32) and (words / type < 72), then b = 10 else if (words / type >= 72), then b = 12 width calculation width = 3 x (words / type) + 15 + a if (type = 1), then a = 0 else if mod (bits / 3) = 0, then a = div (bits / 3) x 2 else if mod (bits / 3) = 1, then a = div (bits / 3) x 2 + 1 else if mod (bits / 3) = 2, then a = div (bits / 3) x 2 + 2 < example: 1r1w dpram 256 x 16 (type = 2) > height = (16 x 2) + 2 x 1 + 12 = 46 width = 3 x (256 / 2) + 14 + 12 = 410 gate count = (46 x 410) arrays size = (46 x 19.0) x (410 x 6.0) microns the table below shows the number of gates used for representative 1r1w dprams. although architecture type also affects the number of gates, this table shows the number of gates for type 2. gate counts for representative 1r1w dprams 16 32 64 128 160 256 8 1170 1863 3159 5964 7830 12150 16 2100 3182 5246 9592 12236 18860 24 3190 4661 7493 13380 16802 25730 32 4514 6375 9975 17404 21606 32838 36 5166 7221 11205 19404 23994 36378 wen oen dout [(nC1):0] data din [(nC1):0] in buffers data out buffers ram array addrw [(kC1):0] addrr [(kC1):0] decoder decoder bit word
sec asic 5-15 kg80/KGM80 1r1w dpram asynchronous one read one write dual-port ram generator memgen-supported 1r1w dpram con?gurations note : parentheses indicate incomplete address decoding. address pin words type 1 (4 ~ 72) type 2 (4 ~ 36) type 4 (4 ~ 18) type 8 (4 ~ 9) 38o 416o o 5 (24) o 32 o o o 6 (40) o (48) o o (56) o 64oooo 7 (72) o (80) o o (88) o (96) o o o (104) o (112) o o (120) o 128 o o o o 8 (144) o (160) o o (176) o (192) o o o (208) o (224) o o (240) o 256 o o o 9 (288) o (320) o o (352) o (384) o o (416) o (448) o o (480) o 512 o o 8 (576) o (640) o (704) o (768) o (832) o (896) o (960) o 1024 o
kg80/KGM80 5-16 sec asic 1r1w dpram asynchronous one read one write dual-port ram generator ac parameters kg80 (typical process, 25?c, 5v, t r / t f = 1.2ns, sl = 20) symbol parameter tpd (ns) 32x8 (type=2) 128x8 (type=2) 256x8 (type=2) read cycle t rc read cycle time 2.233 3.310 4.914 t aa address access time 2.634 3.712 5.335 t oh (a) output hold time from address change 1.000 1.000 1.000 t oe output enable time 1.744 1.744 1.744 t olz output enable to output low-z 1.182 1.182 1.182 t ohz output disable to output high-z 0.768 0.768 0.768 write cycle t wc write cycle time 3.682 4.091 4.851 t wa write enable access time 3.395 4.575 6.235 t da data-in access time 2.152 3.455 5.519 t wp write enable pulse width 1.954 2.230 2.667 t as address setup time 1.393 1.212 1.361 t ah address hold time 0.000 0.276 0.381 t dw data-in setup time 0.314 0.391 0.581 t dh data-in hold time 0.971 1.026 1.285 t oh (d) output hold time from din change 1.000 1.000 1.000 t oh (w) output hold time from wen change 0.000 0.000 0.000 KGM80 (typical process, 25?c, 3.3v, t r / t f = 1.2ns, sl = 20) symbol parameter tpd (ns) 32x8 (type=2) 128x8 (type=2) 256x8 (type=2) read cycle t rc read cycle time 3.147 4.594 6.765 t aa address access time 3.657 5.060 7.253 t oh (a) output hold time from address change 1.000 1.000 1.000 t oe output enable time 2.435 2.435 2.435 t olz output enable to output low-z 1.575 1.575 1.575 t ohz output disable to output high-z 1.136 1.136 1.136 write cycle t wc write cycle time 4.746 5.405 6.301 t wa write enable access time 4.685 6.214 8.327 t da data-in access time 2.896 4.562 7.149 t wp write enable pulse width 2.499 2.838 3.347 t as address setup time 1.717 1.538 1.783 t ah address hold time 0.097 0.537 0.597 t dw data-in setup time 0.154 0.267 0.963 t dh data-in hold time 1.535 1.655 2.003 t oh (d) output hold time from din change 1.000 1.000 1.000 t oh (w) output hold time from wen change 0.000 0.000 0.000
sec asic 5-17 kg80/KGM80 1r1w dpram asynchronous one read one write dual-port ram generator timing diagram read cycle write cycle addrr t rc t aa valid address dout valid data t oh (a) oen t oe t olz t ohz (addrr address) a1 (valid address) t as t wp t dw t da d1 (data-in valid) d1 (data valid) addrw wen oen din dout t wa t dh t oh (a) t aa d (a1) d0 d0 t ah t wc * d (an): data which are stored in an address a3 a4 t oh (w) t oh (d) d (a0) a1 addrr a0 a2
kg80/KGM80 5-18 sec asic 1r1w dpram asynchronous one read one write dual-port ram generator architecture type 1 type 2 type 4 type 8 shortest bit line longest word line for type 1, the speci?ed number of words will equal the number of columns and the speci?ed number of bits will equal the number of rows in the ram array. for the same size ram, type 2 will have and one-half the speci?ed number of rows. longest bit line shortest for the same size ram, type 8 will have eight times the speci?ed number of columns and one-eighth the speci?ed number of rows. word line ram ram ram ram twice the speci?ed number of columns for the same size ram, type 4 will have and one-fourth the speci?ed number of rows. four times the speci?ed number of columns
sec asic 5-19 kg80/KGM80 1rw1r dpram asynchronous one read/write one read dual-port ram generator logic symbol description this high-speed, low-power, 1rw1r dual-port ram has fully static and asynchronous operation. the number of words and word width can be con?gured with the memgenembedded memory compiler. this con?guration has one read/write address port and one read address port, and one data input port and two data output ports. control pins are oean / oebn (output enable) and wean (write enable). during a write operation, the data output ports re?ect the data which are stored in the read address, if the output tri- state buffers are enabled. four ram architectures (type 1, 2, 4 and 8) support varying aspect ratios consistent with word/bit con?guration limitations. features ? fully asynchronous read/write operation ? variable size dual-port ram with 1 read/write and 1 read address port ? 1 data input and 2 data output ports ? zero standby power ? high speed ? tri-state output buffers ? parameter-driven compiler ? up to 9k bit block i/o pin description name i/o i/o cap. [pf] description dia0...dian i 0.021 data input wean i 0.042 read/write port read/write control oean oebn i 0.021 read/write port tri-state control read port tri-state control aadr0...aadrk badr0...badrk i 0.021 read/write port address input read port address input doa dob o 0.098 read/write port output read port output dpram aadr0...aadrk doa0...doan k: n: the number of address the number of data dia0...dian wean oebn badr0...badrk 1rw1r oean dob0...dobn ? variable word depth C 8, 16, 24, 32, 40,..., 1024 ? variable word width C 4, 5, 6, 7, 8,..., 72 ? available architectures C type1, type 2, type 4 and type 8
kg80/KGM80 5-20 sec asic 1rw1r dpram asynchronous one read/write one read dual-port ram generator block diagram truth table oebn oean wean mode x l write l x read h x read/write port output = high impedance l read port read h read port output = high impedance ram array wean oean aadr [(kC1) = 0] badr [(ckC1) = 0] doa decoder decoder data dia oebn dob out buffers data out buffers data in buffers
sec asic 5-21 kg80/KGM80 1rw1r dpram asynchronous one read/write one read dual-port ram generator gate count gate count = height x width size = (height x 19.0) x (width x 6.0) height calculation height = (bits x type) + 2 x a + b a = div (type / 2) if {(words / type = 8) or (words / type = 16), then b = 8 else if (words / type > 16), then b = 10 width calculation width = 4 x (words / type) + a if (type = 1), then a = 34 else a = 34 + bits < example: 1rw1r dpram 256 x 16 (type = 2) > height = (16 x 2) +2 x 1 + 10 = 44 width = 4 x (256 / 2) + 34 +16 = 562 gate count = (44 x 562) arrays size = (44 x 19.0) x (562 x 6.0) microns the table below shows the number of gates used for representative 1rw1r dprams. although architecture type also affects the number of gates, this table shows the number of gates for type 2. gate counts for representative 1rw1r dprams 16 32 64 128 160 256 8 1924 2756 4760 8344 10136 15512 16 3444 4788 7832 13464 16280 24728 24 5220 7076 11160 18840 22680 35200 32 7252 9620 14744 24472 29336 43928 36 8364 10988 16632 27384 32760 48888 bit word
kg80/KGM80 5-22 sec asic 1rw1r dpram asynchronous one read/write one read dual-port ram generator memgen-supported 1rw1r dpram con?gurations note : parentheses indicate incomplete address decoding. address pin words type 1 (4 ~ 72) type 2 (4 ~ 36) type 4 (4 ~ 18) type 8 (4 ~ 9) 38o 416o o 5 (24) o 32 o o o 6 (40) o (48) o o (56) o 64oooo 7 (72) o (80) o o (88) o (96) o o o (104) o (112) o o (120) o 128 o o o o 8 (144) o (160) o o (176) o (192) o o o (208) o (224) o o (240) o 256 o o o 9 (288) o (320) o o (352) o (384) o o (416) o (448) o o (480) o 512 o o 8 (576) o (640) o (704) o (768) o (832) o (896) o (960) o 1024 o
sec asic 5-23 kg80/KGM80 1rw1r dpram asynchronous one read/write one read dual-port ram generator ac parameters kg80 (typical process, 25?c, 5v, t r / t f = 1.2ns, sl = 20) symbol parameter tpd (ns) 32x8 (type=2) 128x8 (type=2) 256x8 (type=2) read cycle t rc (a) read cycle time 2.211 3.273 4.852 t rc (b) 2.211 3.273 4.852 t aa (a) address access time 2.619 3.680 5.268 t aa (b) 2.217 3.672 5.260 t oh (aa) output hold time from aadr change 1.000 1.000 1.000 t oh (ba) output hold time from badr change 1.000 1.000 1.000 t oe (a) output enable time 1.675 1.675 1.675 t oe (b) 1.675 1.675 1.675 t olz (a) output enable to output low-z 1.175 1.175 1.175 t olz (b) 1.175 1.175 1.175 t ohz (a) output disable to output high-z 0.764 0.764 0.764 t ohz (b) 0.764 0.764 0.764 write cycle t wc write cycle time 3.758 4.074 4.873 t wa (a) write enable access time 3.450 4.464 6.274 t wa (b) 3.450 4.464 6.274 t da (a) data-in access time 2.217 3.525 5.328 t da (b) 2.217 3.525 5.328 t wp write enable pulse width 2.006 2.287 2.755 t as address setup time 1.410 1.224 1.317 t ah address hold time 0.000 0.193 0.357 t dw data-in setup time 0.174 0.218 0.375 t dh data-in hold time 1.025 1.081 1.347 t oh (ad) doa hold time from dia change 1.000 1.000 1.000 t oh (bd) dob hold time from dia change 1.000 1.000 1.000 t oh (aw) doa hold time from wean change 0.242 0.242 0.242 t oh (bw) dob hold time from wean change 0.242 0.242 0.242
kg80/KGM80 5-24 sec asic 1rw1r dpram asynchronous one read/write one read dual-port ram generator ac parameters (continued) KGM80 (typical process, 25?c, 3.3v, t r / t f = 1.2ns, sl = 20) symbol parameter tpd (ns) 32x8 (type=2) 128x8 (type=2) 256x8 (type=2) read cycle t rc (a) read cycle time 3.122 4.557 6.698 t rc (b) 3.122 4.557 6.698 t aa (a) address access time 3.596 5.140 7.437 t aa (b) 3.581 5.126 7.424 t oh (aa) output hold time from aadr change 1.000 1.000 1.000 t oh (ba) output hold time from badr change 1.000 1.000 1.000 t oe (a) output enable time 2.220 2.220 2.220 t oe (b) 2.220 2.220 2.220 t olz (a) output enable to output low-z 1.565 1.565 1.565 t olz (b) 1.565 1.565 1.565 t ohz (a) output disable to output high-z 1.135 1.135 1.135 t ohz (b) 1.135 1.135 1.135 write cycle t wc write cycle time 4.729 5.379 6.375 t wa (a) write enable access time 4.867 6.281 8.786 t wa (b) 4.867 6.281 8.786 t da (a) data-in access time 2.995 4.752 7.473 t da (b) 2.995 4.752 7.473 t wp write enable pulse width 2.570 2.911 3.452 t as address setup time 1.728 1.576 1.790 t ah address hold time 0.000 0.402 0.552 t dw data-in setup time 0.000 0.028 0.619 t dh data-in hold time 1.604 1.722 2.071 t oh (ad) doa hold time from dia change 1.000 1.000 1.000 t oh (bd) dob hold time from dia change 1.000 1000 1.000 t oh (aw) doa hold time from wean change 0.399 0.399 0.399 t oh (bw) dob hold time from wean change 0.399 0.399 0.399
sec asic 5-25 kg80/KGM80 1rw1r dpram asynchronous one read/write one read dual-port ram generator timing diagram read cycle write cycle aadr t rc (a) t aa (a) valid address doa valid data t oh (aa) oean t oe (a) t olz (a) t ohz (a) (aadr address) badr t rc (b) t aa (b) valid address dob valid data t oh (ba) oebn t oe (b) t olz (b) (badr address) t ohz (a) t wc t wp t dw d1 (data-in valid) wean oean/oebn dia badr dob t dh a1 (valid address) aadr a3 a4 t da (a) d1 (data valid) doa t wa (a) t oh (aa) t aa (a) d (a1) d0 t oh (aw) t oh (ad) d (a3) t as t ah d0 a1 (valid address) a0 a2 t da (b) d1 (data valid) t wa (b) t oh (ba) t aa (b) d (a1) d0 t oh (bw) d (a0) t oh (bd) * d (an): data which are stored in an address
kg80/KGM80 5-26 sec asic 1rw1r dpram asynchronous one read/write one read dual-port ram generator architecture type 1 type 2 type 4 type 8 shortest bit line longest word line for type 1, the speci?ed number of words will equal the number of columns and the speci?ed number of bits will equal the number of rows in the ram array. for the same size ram, type 2 will have and one-half the speci?ed number of rows. longest bit line shortest for the same size ram, type 8 will have eight times the speci?ed number of columns and one-eighth the speci?ed number of rows. word line ram ram ram ram columns twice the speci?ed number of for the same size ram, type 4 will have and one-fourth the speci?ed number of rows. four times the speci?ed number of columns
sec asic 5-27 kg80/KGM80 fifo ram-based first-in first-out memory generator logic symbol description fifo builder generates a compiled ?rst-in ?rst-out memory block. fifo is based on a dual-port ram that permits completely asynchronous read/write operation. read and write address values are stored in counters that can be cleared with the rn (reset) input. fifo builder also has status ?ags for empty and full. features ? fully asynchronous read/write operation ? 1 data input and 1 data output port ? zero standby power ? high speed ? parameter-driven compiler i/o pin description block diagram name i/o description din0...dinnC1 i data input ck i synchronous read/write operation write i asynchronous write operation read i asynchronous read operation oen i output enable rn i reset, status flag initialization dout0...doutnC1 o data output ffn o full flag fen o empty flag fifo dout0...doutnC1 n: the number of data bit din0...dinnC1 write oen ck read rn ffn fen dpram read counter write counter oen ck rn write read flag logic read/write control din [(nC1):0] dout [(nC1):0] ffn fen ? variable word depth C 8, 10, 12, 14, 16,..., 1024 ? variable word width C 4, 5, 6, 7, 8,..., 72
kg80/KGM80 5-28 sec asic fifo ram-based first-in first-out memory generator con?gurations ? word: all even numbers between 8 and 1024. timing diagram read cycle write cycle output disable to output low-z output disable to output high -z address access time t rc t rc read cycle time t olz t ohz t oe t olz t ohz output enable time ck read oen dout t rs t oe t aa t oh t rs read setup time t aa t oh output data hold time t wc write cycle time t dh data-in hold time t wc ck write din t dh t dw t dw data-in setup time t ws t ws write setup time ck write read rn ffn fen t ckfull t ckempty t ckfull t ckempty ck low to ffn low ck low to fen low ? bit: 4, 5, 6, 7,..., 69, 70, 71, 72
sec asic 5-29 kg80/KGM80 multiplier multiplier generator logic symbol description the function is p = a * b (a = multiplicand, b = multiplier and p = product of (a * b)). a, b and p are twos compliment formats. the width of a input = m bit, range from [2 ** (m C 1) C 1] to [C2 ** (m C 1)] and the width of b input = n bit, range from [2 ** (n C 1) C 1] to [C2 ** (n C 1)]. the smaller bit width between a and b will be the multiplier and of even bits. that is, the multiplier might be the sum of smaller bit width and one. the width of p output = (m + n) bit, assume that multiplicand is m bits and multiplier is n bits. m 3 n, range from [2 ^ (m + n e 2)] to [2 ^ (n e 1) e2 ^ (m + n e 2)], 4 m and n 32. you can choose a cell compiled with your bit request. this is the softmacro cell. features ? variable size multiplier and multiplicand bits ? zero standby power ? high speed ? parameter-driven compiler ? 32 bits of multiplier and multiplicand con?gurations ? a: 4,..., 32 ? b: 4,..., 32 standard design kit supports the following con?gurations: 8 8, 12 12, 16 16, 24 24, 32 32. other contgurations can be provided upon request. block diagram p0...p (m+n+1) n: the number of multiplier bit a0...a (mC1) b0...b (nC1) multipliler m: the number of multiplicand bit a0...a (mC1) b0...b (nC1) product generators (using modified booth algorithm) adder p0...p (m+nC1) ? variable bit size C multiplicand size: 4C32 bits C multiplier size: 4C32 bits
kg80/KGM80 5-30 sec asic multiplier multiplier generator timing diagram multiplier cycle t mt a0...a (mC1) b0...b (nC1) p0...p (m+nC1) t mt multiply time
jtag boundary scans 6
contents overview .............................................................................................................................. 6-1 boundary scan architecture................................................................................................. 6-2 boundary scan register macrocells .................................................................................... 6-4 jtbi1 ........................................................................................................................... 6-5 jtck............................................................................................................................ 6-12 jtin1 ........................................................................................................................... 6-14 jtint1 ......................................................................................................................... 6-18 jtout1 ....................................................................................................................... 6-24 jtag tap controller macrofunction..................................................................................... 6-28 instruction register/decoder macrofunction ........................................................................ 6-31 implementation of ieee p1149.1/jtag ............................................................................... 6-32 system clock considerations .............................................................................................. 6-32
jtag boundary scans overview sec asic 6-1 kg80/KGM80 overview a board test is typically achieved by using in-circuit test techniques. however, in-circuit test techniques demonstrate signi?cant limitations for surface mount technology (smt) and fine pitch technology (fpt) boards. the pin and pad spacings getting tighter make it dif?cult to test boards with traditional methods economically and reliably. a boundary scan design reduces the cost of a function test. a boundary scan design circuitry allows boards to be tested using the equivalent in-circuit test technique without bed-of-nails ?xture. in recognition of the increasing acceptance of the boundary scan test, ieee and jtag (joint test action group) developed ieee standard test access port and boundary scan architecture (ieee std 1149.1). a boundary scan technique requires to place a boundary scan cell adjacent to each component pin so that signals at component boundaries can be controlled and observed using scan testing principles. each boundary scan cell for a given component is able to capture data from an input pin or from its internal logic, and to drive its internal logic or an output pin. boundary scan cells for the pins of a given component are interconnected so as to form a shift-register chain around the border of the design, known as a boundary scan register. boundary scan registers for individual components can be connected in series to form a single path through the complete design as shown in the ?gure 9-1. alternatively, a board design can contain several independent boundary scan paths that allow individual components to be tested as well as the interconnections between components. to test component interconnections, test data are ?rst shifted into all boundary scan register cells associated with component output test pins. test data are then loaded into parallel inputs of boundary scan cells associated with input pins through the component interconnections, and data captured in these cells are shifted out from the boundary cells for evaluation. for an individual component test, a boundary scan register is used to isolate on-chip system logic from stimuli received from surrounding components. an actual test can be performed through the boundary scan path or the built-in self-test hardware. figure 6-1. board design for boundary scan logic logic logic logic data i n serial data out serial test interconnect system interconnect serial
boundary scan architecture jtag boundary scans kg80/KGM80 6-2 sec asic boundary scan architecture a boundary scan architecture contains tap (test access port), tap controller, instruction register and a group of test data registers. the instruction and test data registers are separate shift-register-based paths connected in parallel with a common serial data input and a common serial data output which are connected to tap, tdi and tdo signals. tap controller selects the alternative instruction and test data register paths between tdi and tdo. the schematic view of the top level design of the test logic architecture is shown in the ?gure 9-2. figure 6-2. jtag test access port (tap) block diagram boundary scan functional block descriptions tap (test access port) tap is a general-purpose port that can provide with an access to many test support functions built into a component, including the test logic. it includes three inputs (tck; test clock signal, tms; test mode signal and tdi; test data input) and one output (tdo; test data output) required by the test logic. an optional fourth input (trstn; test reset) is provided for the asynchronous initialization of the test logic. the values applied at tms and tdi pins are sampled on the rising edge of tck, and the value placed on tdo pin changes on the falling edge of tck. tap controller tap controller receives tck, interprets the signals on tms, and generates clock and control signals for both instruction and test data registers and for other parts of the test circuitries as required. instruction register/instruction decoder test instructions are shifted into and held by the instruction register. test instructions include a selection of tests to be performed or the test data register to be accessed. a basic 3-bit instruction register and its instruction decoder are provided as macrofunctions in the library. multiplexer scannable register device identity register bypass register instruction register ta p controller system logic boundary scan path tdi tms tck tdo test access port (tap) mux
jtag boundary scans boundary scan architecture sec asic 6-3 kg80/KGM80 test data registers data registers include a bypass register, a boundary scan register, a device identi?cation register and other design speci?c registers. only the bypass- and boundary scan registers are mandatory; the rest are optional. bypass register: the bypass register provides a single-bit serial connection through the circuit when none of the other test data registers is selected. it can be used to allow test data to ?ow through a given device to the other components in a product without affecting a normal operation. boundary scan register: the boundary scan register detects typical production defects in board interconnects, such as opens, shorts, etc. it also allows an access to component inputs and outputs when you test their logic or sample ?ow-through signals. special boundary scan register macrocells are provided for this purpose. these special registers is discussed in the next section of next pages. design-speci?c test data register: these optional registers may be provided to allow an access to design-speci?c test support features in the integrated circuit, such as self-test, scan test. device identi?cation register: this is an optional test data register that allows the manufacturer part number and variant of a components to be identi?ed. the 32-bit identi?cation register is partitioned into four ?elds: device version identi?er 1st ?eld the ?rst four bits beginning from msb device part number 2nd ?eld 16 bits manufacturers jedec number 3rd ?eld 11 bits lsb 4th ?eld 1 bit tied in high the asic designer is free to ?ll the version and part number in any manner as long as the total twenty bits are used. secs jedec code: 78 decimal = 1001110 continuation ?eld (4 bits) = 0000 contents of device identi?cation register: xxxx xxxxxxxxxxxxxxxx 0000 1001110 1 users can de?ne these two ?elds.
boundary scan register macrocells jtag boundary scans kg80/KGM80 6-4 sec asic boundary scan register macrocells the boundary scan register allows testing of circuitry external to the integrated circuit and provides for de?ned conditions to be established at the periphery of the on-chip system logic while it is tested itself. it also permits signals ?owing through system pins to be sampled and examined without interfering with the operation of the on-chip system logic. the boundary scan register has four capabilities: capture: loads data into the boundary scan register in parallel on the rising edge of tck. it does not affect the output until update is executed. shift: shifts data from one boundary scan register to the next register towards the serial data output pin on the rising edge of tck. update: loads data in the boundary scan register into the parallel data output pin on the falling edge of tck when extest or intest instruction is selected. set: sets the parallel output pin. sec supports ?ve types of boundary scan registers. four of them, jtck, jtbi1, jtin1 and jtout1 are to be implemented around the periphery of the die next to i/o cells. for this reason, two i/o pads at each corner, that is, the total of eight i/o pads for the entire chip are not scannable. an implementation is automatically performed during a placement to achieve the most optimum placement with a minimum performance penalty. the ?fth cell, jtint1, is to be placed in the core area of the die for tri-state i/o control. applications for each type of boundary scan register cell are summarized as follows. cell list cell name function description page jtbi1 bi-directional i/o boundary scan cell 6-5 jtck special input (such as clock input) boundary scan cell 6-12 jtin1 input boundary scan cell 6-14 jtint1 tri-state i/o control boundary scan cell 6-18 jtout1 output boundary scan cell 6-24
sec asic 6-5 kg80/KGM80 jtbi1 bi-directional i/o scan cell with capture, shift and update logic symbol pin description pin name i/o description dinp0n i parallel data input active low for the input part of the bi-directional pin tdi0 i serial test data input for input part of the bi-directional pin mode0 i mode select for input partlow for data input and high for internal register data value dinp1 i parallel data input active low for the output part of the bi-directional pin tdi1 i serial test data input for input part of the bi-directional pin mode1 i mode select for output partlow for data input and high for internal register data value shift i active high shift control input update i update latch inputlow for update tck i test clock input enb i active high test clock enable dout0 o parallel data output for input part of the bi-directional pin tdo0 o serial test data output for input part of the bi-directional pin dout1 o parallel data output for output part of the bi-directional pin tdo1 o serial test data output for output part of the bi-directional pin dinp0n tdi0 mode0 tdi1 mode1 tdo0 shift update enb dout1 dinp1 tck dout0 tdo1 cell data input loading (sl) dinp0n 3 tdi0 3 mode0 2 dinp1 4 tdi1 3 mode1 2 shift 3 update 3 tck 1 enb 1 gate count 33
kg80/KGM80 6-6 sec asic jtbi1 bi-directional i/o scan cell with capture, shift and update truth table notes: 1. outputs are de?ned in separate truth tables. in addition, the internal states known as latchq and latchqn are de?ned as the output of the latch in the logic diagram. 2. jtbi1 has a similar truth table to jtin1 and jtout1 macrocells without setn input. it has similar delays to jtin1 and jtout1. dinp0n tdi0 mode0 shift update tck enb output dout0 0x0xxxx1 1x0xxxx0 x x 1 x x x x latchqn tdo0 x x x x x 0 tdo0o 0x00x 11 1x00x 10 x x 1 0 x 1 latchqn x0x1x 10 x1x1x 11 x x x x x 0 x tdo0o x x x x x 1 x tdo0o x x x x x x tdo0o latchqn x x x x 0 x x tdo0 x x x x 1 x x latchqno dinp1 tdi1 mode1 shift update tck enb output dout1 0x0xxxx0 1x0xxxx1 xx1xxxx latchq tdo1 xxxxx 0 tdo1o 0xx0x 10 1xx0x 11 x0x1x 10 x1x1x 11 xxxxx0x tdo1o xxxxx1x tdo1o xxxxx x tdo1o latchq xxxx0xx tdo1 xxxx1xx latchqo
sec asic 6-7 kg80/KGM80 jtbi1 bi-directional i/o scan cell with capture, shift and update timing requirements (typical process, 25 c, 5v, 3.3v) parameter symbol value (ns) kg80 KGM80 input setup time (tdi0 to tck) t su 0.34 0.64 input hold time (tdi0 to tck) t hd 0.15 0.33 input setup time (tdi0 to enb) t su 0.34 0.64 input hold time (tdi0 to enb) t hd 0.15 0.33 input setup time (tdi1 to tck) t su 0.34 0.64 input hold time (tdi1 to tck) t hd 0.15 0.33 input setup time (tdi1 to enb) t su 0.34 0.64 input hold time (tdi1 to enb) t hd 0.15 0.33 input setup time (dinp0n to tck) t su 0.56 0.99 input hold time (dinp0n to tck) t hd 0.15 0.33 input setup time (dinp0n to enb) t su 0.56 0.99 input hold time (dinp0n to enb) t hd 0.15 0.33 input setup time (dinp1 to tck) t su 0.37 0.68 input hold time (dinp1 to tck) t hd 0.15 0.33 input setup time (dinp1 to enb) t su 0.34 0.64 input hold time (dinp1 to enb) t hd 0.15 0.33 input setup time (shift to tck) t su 0.45 0.80 input hold time (shift to tck) t hd 0.15 0.30 input setup time (shift to enb) t su 0.45 0.80 input hold time (shift to enb) t hd 0.15 0.33 input setup time (mode0 to tck) t su 0.64 1.08 input hold time (mode0 to tck) t hd 0.15 0.33 input setup time (mode0 to enb) t su 0.64 1.08 input hold time (mode0 to enb) t hd 0.15 0.33
kg80/KGM80 6-8 sec asic jtbi1 bi-directional i/o scan cell with capture, shift and update switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 jtbi1 (continued) [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to tdo0 t plh 0.85 0.76 + 0.043*sl 0.76 + 0.042*sl 0.76 + 0.042*sl t phl 0.73 0.66 + 0.034*sl 0.68 + 0.027*sl 0.70 + 0.024*sl t r 0.28 0.10 + 0.086*sl 0.10 + 0.089*sl 0.09 + 0.090*sl t f 0.19 0.10 + 0.043*sl 0.11 + 0.040*sl 0.11 + 0.041*sl enb to tdo0 t plh 0.84 0.75 + 0.043*sl 0.76 + 0.041*sl 0.75 + 0.042*sl t phl 0.71 0.64 + 0.034*sl 0.66 + 0.027*sl 0.68 + 0.024*sl t r 0.28 0.11 + 0.085*sl 0.10 + 0.089*sl 0.10 + 0.088*sl t f 0.19 0.11 + 0.043*sl 0.11 + 0.040*sl 0.10 + 0.042*sl tck to tdo1 t plh 0.81 0.73 + 0.042*sl 0.73 + 0.042*sl 0.73 + 0.042*sl t phl 0.68 0.62 + 0.031*sl 0.63 + 0.026*sl 0.65 + 0.023*sl t r 0.27 0.10 + 0.085*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.08 + 0.041*sl enb to tdo1 t plh 0.80 0.72 + 0.042*sl 0.72 + 0.042*sl 0.72 + 0.042*sl t phl 0.67 0.61 + 0.031*sl 0.62 + 0.026*sl 0.64 + 0.024*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.089*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.08 + 0.041*sl dinp0n to dout0 t plh 0.21 0.17 + 0.020*sl 0.17 + 0.021*sl 0.15 + 0.024*sl t phl 0.10 0.02 + 0.039*sl 0.07 + 0.019*sl 0.10 + 0.015*sl t r 0.22 0.13 + 0.044*sl 0.15 + 0.038*sl 0.12 + 0.041*sl t f 0.19 0.11 + 0.041*sl 0.16 + 0.019*sl 0.17 + 0.019*sl mode0 to dout0 t plh 0.27 0.22 + 0.025*sl 0.23 + 0.018*sl 0.21 + 0.022*sl t phl 0.26 0.22 + 0.021*sl 0.23 + 0.019*sl 0.26 + 0.014*sl t r 0.20 0.11 + 0.042*sl 0.11 + 0.044*sl 0.11 + 0.043*sl t f 0.14 0.10 + 0.022*sl 0.10 + 0.019*sl 0.09 + 0.021*sl update to dout0 t plh 0.58 0.53 + 0.024*sl 0.54 + 0.023*sl 0.55 + 0.021*sl t phl 0.64 0.56 + 0.037*sl 0.60 + 0.022*sl 0.66 + 0.014*sl t r 0.21 0.12 + 0.044*sl 0.10 + 0.052*sl 0.17 + 0.042*sl t f 0.22 0.16 + 0.030*sl 0.18 + 0.025*sl 0.21 + 0.020*sl tck to dout0 t plh 1.27 1.22 + 0.026*sl 1.23 + 0.022*sl 1.23 + 0.022*sl t phl 1.16 1.11 + 0.026*sl 1.12 + 0.021*sl 1.15 + 0.017*sl t r 0.21 0.12 + 0.043*sl 0.12 + 0.043*sl 0.11 + 0.045*sl t f 0.22 0.16 + 0.030*sl 0.18 + 0.024*sl 0.19 + 0.022*sl enb to dout0 t plh 1.27 1.22 + 0.025*sl 1.22 + 0.022*sl 1.23 + 0.021*sl t phl 1.15 1.10 + 0.026*sl 1.12 + 0.021*sl 1.14 + 0.017*sl t r 0.21 0.12 + 0.042*sl 0.12 + 0.044*sl 0.12 + 0.044*sl t f 0.22 0.16 + 0.031*sl 0.18 + 0.023*sl 0.19 + 0.022*sl dinp1 to dout1 t plh 0.31 0.23 + 0.043*sl 0.23 + 0.041*sl 0.23 + 0.041*sl t phl 0.36 0.30 + 0.027*sl 0.30 + 0.028*sl 0.33 + 0.025*sl t r 0.28 0.10 + 0.087*sl 0.10 + 0.089*sl 0.06 + 0.096*sl t f 0.21 0.12 + 0.048*sl 0.14 + 0.041*sl 0.13 + 0.041*sl
sec asic 6-9 kg80/KGM80 jtbi1 bi-directional i/o scan cell with capture, shift and update switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 jtbi1 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* mode1 to dout1 t plh 0.24 0.14 + 0.053*sl 0.17 + 0.038*sl 0.11 + 0.047*sl t phl 0.31 0.22 + 0.043*sl 0.27 + 0.024*sl 0.26 + 0.025*sl t r 0.29 0.11 + 0.088*sl 0.10 + 0.092*sl 0.15 + 0.085*sl t f 0.19 0.12 + 0.037*sl 0.10 + 0.042*sl 0.10 + 0.043*sl update to dout1 t plh 0.70 0.63 + 0.034*sl 0.61 + 0.042*sl 0.61 + 0.043*sl t phl 0.62 0.55 + 0.035*sl 0.57 + 0.030*sl 0.61 + 0.023*sl t r 0.28 0.11 + 0.083*sl 0.09 + 0.090*sl 0.10 + 0.090*sl t f 0.20 0.12 + 0.043*sl 0.12 + 0.043*sl 0.15 + 0.039*sl tck to dout1 t plh 1.40 1.31 + 0.045*sl 1.32 + 0.041*sl 1.31 + 0.043*sl t phl 1.28 1.21 + 0.035*sl 1.22 + 0.028*sl 1.24 + 0.025*sl t r 0.28 0.11 + 0.085*sl 0.09 + 0.094*sl 0.14 + 0.087*sl t f 0.21 0.12 + 0.046*sl 0.13 + 0.040*sl 0.13 + 0.041*sl enb to dout1 t plh 1.39 1.31 + 0.042*sl 1.30 + 0.042*sl 1.30 + 0.042*sl t phl 1.27 1.20 + 0.033*sl 1.21 + 0.029*sl 1.24 + 0.025*sl t r 0.28 0.11 + 0.085*sl 0.08 + 0.095*sl 0.14 + 0.088*sl t f 0.21 0.12 + 0.044*sl 0.13 + 0.041*sl 0.11 + 0.043*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 6-10 sec asic jtbi1 bi-directional i/o scan cell with capture, shift and update switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 jtbi1 (continued) [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to tdo0 t plh 1.20 1.09 + 0.053*sl 1.10 + 0.049*sl 1.10 + 0.050*sl t phl 1.02 0.96 + 0.030*sl 0.98 + 0.023*sl 0.90 + 0.030*sl t r 0.36 0.15 + 0.104*sl 0.13 + 0.110*sl 0.18 + 0.106*sl t f 0.21 0.14 + 0.034*sl 0.15 + 0.033*sl -0.09 + 0.054*sl enb to tdo0 t plh 1.20 1.10 + 0.049*sl 1.09 + 0.051*sl 1.11 + 0.049*sl t phl 1.01 0.93 + 0.039*sl 0.96 + 0.029*sl 1.01 + 0.024*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.109*sl 0.14 + 0.109*sl t f 0.23 0.14 + 0.047*sl 0.15 + 0.041*sl 0.14 + 0.042*sl tck to tdo1 t plh 1.15 1.06 + 0.048*sl 1.05 + 0.051*sl 1.06 + 0.050*sl t phl 0.96 0.89 + 0.036*sl 0.91 + 0.026*sl 0.95 + 0.023*sl t r 0.35 0.15 + 0.103*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.20 0.11 + 0.045*sl 0.12 + 0.041*sl 0.09 + 0.044*sl enb to tdo1 t plh 1.16 1.05 + 0.054*sl 1.06 + 0.050*sl 1.06 + 0.050*sl t phl 0.96 0.89 + 0.034*sl 0.92 + 0.026*sl 0.95 + 0.023*sl t r 0.36 0.16 + 0.100*sl 0.13 + 0.108*sl 0.09 + 0.112*sl t f 0.20 0.11 + 0.046*sl 0.13 + 0.041*sl 0.08 + 0.046*sl dinp0n to dout0 t plh 0.28 0.24 + 0.020*sl 0.23 + 0.025*sl 0.23 + 0.024*sl t phl 0.16 0.08 + 0.041*sl 0.14 + 0.017*sl 0.28 + 0.004*sl t r 0.25 0.16 + 0.044*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.23 0.15 + 0.043*sl 0.21 + 0.020*sl 0.36 + 0.007*sl mode0 to dout0 t plh 0.34 0.31 + 0.015*sl 0.28 + 0.028*sl 0.31 + 0.024*sl t phl 0.36 0.32 + 0.018*sl 0.32 + 0.018*sl 0.36 + 0.015*sl t r 0.25 0.14 + 0.055*sl 0.15 + 0.053*sl 0.11 + 0.056*sl t f 0.18 0.13 + 0.026*sl 0.14 + 0.020*sl 0.12 + 0.022*sl update to dout0 t plh 0.77 0.70 + 0.033*sl 0.72 + 0.028*sl 0.72 + 0.028*sl t phl 0.91 0.83 + 0.044*sl 0.88 + 0.025*sl 0.96 + 0.017*sl t r 0.26 0.15 + 0.055*sl 0.15 + 0.055*sl 0.17 + 0.053*sl t f 0.29 0.21 + 0.039*sl 0.24 + 0.028*sl 0.33 + 0.020*sl tck to dout0 t plh 1.83 1.77 + 0.031*sl 1.78 + 0.028*sl 1.81 + 0.025*sl t phl 1.69 1.62 + 0.034*sl 1.65 + 0.024*sl 1.72 + 0.018*sl t r 0.26 0.15 + 0.055*sl 0.16 + 0.052*sl 0.12 + 0.056*sl t f 0.29 0.22 + 0.035*sl 0.24 + 0.028*sl 0.32 + 0.021*sl enb to dout0 t plh 1.83 1.77 + 0.032*sl 1.78 + 0.028*sl 1.81 + 0.025*sl t phl 1.69 1.62 + 0.034*sl 1.65 + 0.024*sl 1.72 + 0.017*sl t r 0.26 0.15 + 0.058*sl 0.16 + 0.055*sl 0.17 + 0.053*sl t f 0.29 0.21 + 0.037*sl 0.24 + 0.027*sl 0.29 + 0.022*sl dinp1 to dout1 t plh 0.40 0.30 + 0.048*sl 0.29 + 0.051*sl 0.30 + 0.050*sl t phl 0.49 0.41 + 0.040*sl 0.43 + 0.032*sl 0.54 + 0.022*sl t r 0.37 0.15 + 0.114*sl 0.17 + 0.104*sl 0.11 + 0.110*sl t f 0.27 0.17 + 0.052*sl 0.19 + 0.042*sl 0.21 + 0.040*sl
sec asic 6-11 kg80/KGM80 jtbi1 bi-directional i/o scan cell with capture, shift and update switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 jtbi1 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* mode1 to dout1 t plh 0.31 0.23 + 0.040*sl 0.20 + 0.050*sl 0.22 + 0.049*sl t phl 0.39 0.31 + 0.039*sl 0.33 + 0.032*sl 0.43 + 0.022*sl t r 0.37 0.14 + 0.114*sl 0.16 + 0.108*sl 0.16 + 0.108*sl t f 0.25 0.15 + 0.048*sl 0.16 + 0.043*sl 0.15 + 0.044*sl update to dout1 t plh 0.97 0.85 + 0.062*sl 0.89 + 0.048*sl 0.84 + 0.052*sl t phl 0.86 0.77 + 0.044*sl 0.80 + 0.033*sl 0.91 + 0.023*sl t r 0.37 0.18 + 0.094*sl 0.14 + 0.108*sl 0.12 + 0.110*sl t f 0.27 0.17 + 0.047*sl 0.18 + 0.043*sl 0.21 + 0.040*sl tck to dout1 t plh 2.01 1.91 + 0.052*sl 1.92 + 0.050*sl 1.92 + 0.050*sl t phl 1.87 1.78 + 0.042*sl 1.81 + 0.031*sl 1.89 + 0.024*sl t r 0.36 0.15 + 0.106*sl 0.14 + 0.110*sl 0.16 + 0.108*sl t f 0.27 0.17 + 0.048*sl 0.18 + 0.044*sl 0.22 + 0.041*sl enb to dout1 t plh 2.02 1.91 + 0.053*sl 1.92 + 0.050*sl 1.92 + 0.050*sl t phl 1.88 1.79 + 0.042*sl 1.82 + 0.030*sl 1.88 + 0.025*sl t r 0.36 0.15 + 0.103*sl 0.13 + 0.111*sl 0.17 + 0.107*sl t f 0.28 0.18 + 0.048*sl 0.20 + 0.041*sl 0.18 + 0.043*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 6-12 sec asic jtck special input scan cell with capture and shift logic symbol general description jtck is a special input boundary scan cell for clock pad. it has capture and shift capabilities only. jtck doesnt have update and set capabilities, but has clock enable capability. pin description truth table pin name i/o description dinp i parallel system data input tdi i serial test data input shift i active high shift control input tck i test clock input enb i active high test clock enable input tdo o serial test data output dinp tdi shift tck enb tdo x x x 0 tdoo 0x0 10 1x0 11 x01 10 x11 11 x x x 0 x tdoo x x x 1 x tdoo x x x x tdoo dinp tdi shift enb tck tdo cell data input loading (sl) dinp 1 tdi 1 shift 2 tck 1 enb 1 gate count 9
sec asic 6-13 kg80/KGM80 jtck special input scan cell with capture and shift timing requirements (typical process, 25 c, 5v, 3.3v) switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 jtck switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 jtck parameter symbol value (ns) kg80 KGM80 input setup time (tdi to tck) t su 0.37 0.64 input hold time (tdi to tck) t hd 0.15 0.33 input setup time (tdi to enb) t su 0.34 0.64 input hold time (tdi to enb) t hd 0.15 0.33 input setup time (dinp to tck) t su 0.37 0.68 input hold time (dinp to tck) t hd 0.15 0.33 input setup time (dinp to enb) t su 0.34 0.64 input hold time (dinp to enb) t hd 0.15 0.33 input setup time (shift to tck) t su 0.45 0.80 input hold time (shift to tck) t hd 0.15 0.33 input setup time (shift to enb) t su 0.45 0.80 input hold time (shift to enb) t hd 0.15 0.33 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to tdo t plh 0.58 0.50 + 0.042*sl 0.50 + 0.041*sl 0.49 + 0.042*sl t phl 0.59 0.53 + 0.032*sl 0.54 + 0.026*sl 0.56 + 0.023*sl t r 0.27 0.10 + 0.087*sl 0.09 + 0.091*sl 0.11 + 0.089*sl t f 0.18 0.10 + 0.040*sl 0.10 + 0.039*sl 0.07 + 0.044*sl enb to tdo t plh 0.57 0.48 + 0.042*sl 0.48 + 0.042*sl 0.49 + 0.041*sl t phl 0.59 0.52 + 0.031*sl 0.54 + 0.026*sl 0.56 + 0.023*sl t r 0.28 0.09 + 0.093*sl 0.10 + 0.089*sl 0.11 + 0.088*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.041*sl 0.07 + 0.043*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = = [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to tdo t plh 0.78 0.68 + 0.051*sl 0.68 + 0.050*sl 0.68 + 0.050*sl t phl 0.81 0.74 + 0.035*sl 0.77 + 0.026*sl 0.80 + 0.024*sl t r 0.36 0.13 + 0.112*sl 0.15 + 0.107*sl 0.11 + 0.110*sl t f 0.21 0.11 + 0.047*sl 0.13 + 0.042*sl 0.10 + 0.044*sl enb to tdo t plh 0.76 0.66 + 0.052*sl 0.66 + 0.050*sl 0.67 + 0.050*sl t phl 0.81 0.74 + 0.035*sl 0.77 + 0.026*sl 0.79 + 0.024*sl t r 0.36 0.15 + 0.105*sl 0.14 + 0.108*sl 0.13 + 0.109*sl t f 0.21 0.11 + 0.050*sl 0.14 + 0.041*sl 0.12 + 0.042*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 6-14 sec asic jtin1 input scan cell with capture, shift, update and set logic symbol pin description pin name i/o description dinpn i parallel data input active low tdi i serial test data input mode i mode select inputlow for data input and high for internal register data value shift i active high shift control input update i update latch inputlow for update setn i active low set input tck i test clock input enb i active high test clock enable input dout o parallel data output tdo o serial test data output dinpn tdi mode update setn tdo tck enb shift dout cell data input loading (sl) dinpn 3 tdi 3 mode 2 shift 2 update 2 setn 1 tck 3 enb 1 gate count 16
sec asic 6-15 kg80/KGM80 jtin1 input scan cell with capture, shift, update and set truth table note : outputs are de?ned in separate truth tables. in addition, an internal state known as latchq is de?ned as the output of the latch in the logic diagram. timing requirements (typical process, 25 c, 5v, 3.3v) dinpn tdi mode shift update tck enb output dout 0x0xxxx1 1x0xxxx0 xx1xxxx latchq tdo xxxxx 0 tdoo 0x00x 11 1x00x 10 x x 1 0 x 1 latchq x0x1x 10 x1x1x 11 xxxxx0x tdoo xxxxx1x tdoo xxxxx x tdoo latchq xxxx0xx0 xxxx1 0xtdo xxxx1 1x latchqo parameter symbol value (ns) kg80 KGM80 input setup time (tdi to tck) t su 0.34 0.64 input hold time (tdi to tck) t hd 0.15 0.33 input setup time (tdi to enb) t su 0.34 0.64 input hold time (tdi to enb) t hd 0.15 0.33 input setup time (dinpn to tck) t su 0.56 0.99 input hold time (dinpn to tck) t hd 0.15 0.33 input setup time (dinpn to enb) t su 0.56 0.99 input hold time (dinpn to enb) t hd 0.15 0.33 input setup time (shift to tck) t su 0.45 0.80 input hold time (shift to tck) t hd 0.15 0.33 input setup time (shift to enb) t su 0.45 0.80 input hold time (shift to enb) t hd 0.15 0.33 input setup time (mode to tck) t su 0.64 1.08 input hold time (mode to tck) t hd 0.15 0.33 input setup time (mode to enb) t su 0.64 1.08 input hold time (mode to enb) t hd 0.15 0.33 recovery time (setn) t rc 0.15 0.33 input hold time (setn to update) t hd 0.15 0.33
kg80/KGM80 6-16 sec asic jtin1 input scan cell with capture, shift, update and set switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 jtin1 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to tdo t plh 0.60 0.51 + 0.041*sl 0.51 + 0.042*sl 0.51 + 0.042*sl t phl 0.61 0.55 + 0.033*sl 0.57 + 0.024*sl 0.57 + 0.023*sl t r 0.32 0.14 + 0.089*sl 0.14 + 0.090*sl 0.13 + 0.091*sl t f 0.19 0.11 + 0.041*sl 0.11 + 0.040*sl 0.10 + 0.042*sl enb to tdo t plh 0.58 0.50 + 0.042*sl 0.50 + 0.042*sl 0.50 + 0.042*sl t phl 0.60 0.55 + 0.029*sl 0.55 + 0.025*sl 0.57 + 0.023*sl t r 0.32 0.15 + 0.088*sl 0.14 + 0.090*sl 0.13 + 0.091*sl t f 0.20 0.12 + 0.041*sl 0.12 + 0.039*sl 0.10 + 0.042*sl dinpn to dout t plh 0.21 0.17 + 0.023*sl 0.17 + 0.021*sl 0.56 + -0.033*sl t phl 0.11 0.04 + 0.033*sl 0.08 + 0.019*sl 0.45 + -0.033*sl t r 0.21 0.14 + 0.035*sl 0.13 + 0.041*sl 0.83 + -0.058*sl t f 0.20 0.15 + 0.026*sl 0.16 + 0.021*sl 0.56 + -0.035*sl mode to dout t plh 0.34 0.29 + 0.023*sl 0.30 + 0.022*sl 0.68 + -0.033*sl t phl 0.27 0.22 + 0.020*sl 0.23 + 0.016*sl 0.53 + -0.026*sl t r 0.17 0.08 + 0.043*sl 0.09 + 0.042*sl 0.83 + -0.062*sl t f 0.14 0.10 + 0.025*sl 0.10 + 0.021*sl 0.49 + -0.033*sl update to dout t plh 0.69 0.63 + 0.025*sl 0.64 + 0.024*sl 1.06 + -0.035*sl t phl 0.69 0.65 + 0.020*sl 0.65 + 0.020*sl 1.05 + -0.036*sl t r 0.20 0.11 + 0.042*sl 0.10 + 0.047*sl 0.91 + -0.066*sl t f 0.21 0.16 + 0.025*sl 0.16 + 0.023*sl 0.59 + -0.037*sl setn to dout t plh 0.56 0.51 + 0.025*sl 0.52 + 0.022*sl 0.93 + -0.036*sl t phl 0.50 0.44 + 0.026*sl 0.46 + 0.021*sl 0.85 + -0.035*sl t r 0.20 0.12 + 0.040*sl 0.11 + 0.046*sl 0.89 + -0.065*sl t f 0.21 0.14 + 0.035*sl 0.17 + 0.022*sl 0.61 + -0.039*sl tck to dout t plh 1.19 1.14 + 0.025*sl 1.15 + 0.022*sl 1.56 + -0.036*sl t phl 1.30 1.23 + 0.031*sl 1.26 + 0.019*sl 1.64 + -0.035*sl t r 0.20 0.11 + 0.043*sl 0.11 + 0.043*sl 0.86 + -0.063*sl t f 0.21 0.15 + 0.028*sl 0.16 + 0.023*sl 0.60 + -0.038*sl enb to dout t plh 1.17 1.13 + 0.025*sl 1.13 + 0.022*sl 1.54 + -0.036*sl t phl 1.29 1.23 + 0.027*sl 1.25 + 0.020*sl 1.64 + -0.035*sl t r 0.20 0.11 + 0.042*sl 0.10 + 0.048*sl 0.91 + -0.067*sl t f 0.21 0.14 + 0.032*sl 0.16 + 0.024*sl 0.61 + -0.039*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 6-17 kg80/KGM80 jtin1 input scan cell with capture, shift, update and set switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 jtin1 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to tdo t plh 0.81 0.70 + 0.051*sl 0.71 + 0.050*sl 0.71 + 0.050*sl t phl 0.84 0.77 + 0.031*sl 0.79 + 0.026*sl 0.81 + 0.023*sl t r 0.43 0.22 + 0.106*sl 0.21 + 0.109*sl 0.22 + 0.108*sl t f 0.25 0.16 + 0.043*sl 0.17 + 0.040*sl 0.14 + 0.042*sl enb to tdo t plh 0.83 0.73 + 0.051*sl 0.73 + 0.050*sl 0.73 + 0.050*sl t phl 0.86 0.80 + 0.031*sl 0.81 + 0.026*sl 0.84 + 0.023*sl t r 0.43 0.22 + 0.106*sl 0.21 + 0.109*sl 0.20 + 0.110*sl t f 0.24 0.15 + 0.043*sl 0.16 + 0.041*sl 0.15 + 0.042*sl dinpn to dout t plh 0.28 0.22 + 0.029*sl 0.23 + 0.025*sl 0.89 + -0.035*sl t phl 0.17 0.11 + 0.029*sl 0.14 + 0.019*sl 0.66 + -0.029*sl t r 0.26 0.16 + 0.050*sl 0.15 + 0.051*sl 1.45 + -0.068*sl t f 0.24 0.18 + 0.029*sl 0.20 + 0.023*sl 0.84 + -0.035*sl mode to dout t plh 0.43 0.39 + 0.020*sl 0.37 + 0.028*sl 1.08 + -0.038*sl t phl 0.37 0.32 + 0.024*sl 0.34 + 0.017*sl 0.80 + -0.025*sl t r 0.24 0.10 + 0.074*sl 0.16 + 0.051*sl 1.51 + -0.073*sl t f 0.18 0.12 + 0.032*sl 0.15 + 0.022*sl 0.74 + -0.033*sl update to dout t plh 0.95 0.88 + 0.033*sl 0.90 + 0.025*sl 1.57 + -0.036*sl t phl 1.01 0.94 + 0.034*sl 0.98 + 0.021*sl 1.60 + -0.036*sl t r 0.26 0.15 + 0.054*sl 0.15 + 0.055*sl 1.56 + -0.074*sl t f 0.27 0.20 + 0.037*sl 0.23 + 0.026*sl 0.93 + -0.038*sl setn to dout t plh 0.73 0.67 + 0.032*sl 0.68 + 0.028*sl 1.41 + -0.039*sl t phl 0.73 0.66 + 0.034*sl 0.68 + 0.024*sl 1.34 + -0.036*sl t r 0.25 0.14 + 0.057*sl 0.15 + 0.053*sl 1.51 + -0.072*sl t f 0.27 0.20 + 0.036*sl 0.22 + 0.027*sl 0.96 + -0.040*sl tck to dout t plh 1.66 1.60 + 0.031*sl 1.61 + 0.027*sl 2.32 + -0.038*sl t phl 1.88 1.81 + 0.033*sl 1.84 + 0.023*sl 2.48 + -0.036*sl t r 0.26 0.16 + 0.050*sl 0.16 + 0.052*sl 1.50 + -0.071*sl t f 0.27 0.19 + 0.040*sl 0.23 + 0.025*sl 0.92 + -0.038*sl enb to dout t plh 1.68 1.62 + 0.031*sl 1.63 + 0.027*sl 2.35 + -0.039*sl t phl 1.90 1.83 + 0.035*sl 1.86 + 0.023*sl 2.50 + -0.036*sl t r 0.25 0.14 + 0.056*sl 0.15 + 0.053*sl 1.52 + -0.072*sl t f 0.27 0.19 + 0.038*sl 0.23 + 0.026*sl 0.93 + -0.039*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 6-18 sec asic jtint1 tri-state i/o control scan cell with capture, shift, update and set logic symbol pin description pin name i/o description dinp i parallel data input active low tdi i serial test data input mode i mode select inputlow for data input and high for internal register data value shift i active high shift control input update i update latch inputlow for update setn i active low set input tck i test clock input enb i active high test clock enable input dout o parallel data output tdo o serial test data output inst o updated instruction output dinp tdi mode update setn inst tck enb tdo shift dout cell data input loading (sl) dinp 4 tdi 3 inst 3 mode 2 shift 2 update 2 setn 1 tck 1 enb 1 gate count 17
sec asic 6-19 kg80/KGM80 jtint1 tri-state i/o control scan cell with capture, shift, update and set truth table note : outputs are de?ned in separate truth tables. timing requirements (typical process, 25 c, 5v, 3.3v) dinp tdi mode shift update setn tck enb output dout 0x0xxxxx0 1x0xxxxx1 x x 1 x x x x x inst tdo x x x x x x 0 tdoo 0xx0xx 10 1xx0xx 11 x0x1xx 10 x1x1xx 11 x x x x x x 0 x tdoo x x x x x x 1 x tdoo x x x x x x x tdoo inst xxxxx0xx1 xxxx0 1xxtdo x x x x 1 1 x x insto parameter symbol value (ns) kg80 KGM80 input setup time (tdi to tck) t su 0.34 0.64 input hold time (tdi to tck) t hd 0.15 0.33 input setup time (tdi to enb) t su 0.34 0.64 input hold time (tdi to enb) t hd 0.15 0.33 input setup time (dinpn to tck) t su 0.37 0.68 input hold time (dinpn to tck) t hd 0.15 0.33 input setup time (dinpn to enb) t su 0.34 0.64 input hold time (dinpn to enb) t hd 0.15 0.33 input setup time (shift to tck) t su 0.45 0.80 input hold time (shift to tck) t hd 0.15 0.33 input setup time (shift to enb) t su 0.45 0.80 input hold time (shift to enb) t hd 0.15 0.33 recovery time (setn) t rc 0.15 0.33 input hold time (setn to update) t hd 0.15 0.33
kg80/KGM80 6-20 sec asic jtint1 tri-state i/o control scan cell with capture, shift, update and set switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 jtint1 (continued) [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to tdo t plh 0.58 0.53 + 0.025*sl 0.48 + 0.045*sl 0.54 + 0.036*sl t phl 0.61 0.55 + 0.031*sl 0.57 + 0.025*sl 0.59 + 0.022*sl t r 0.32 0.14 + 0.089*sl 0.14 + 0.089*sl 0.13 + 0.091*sl t f 0.19 0.11 + 0.042*sl 0.11 + 0.040*sl 0.09 + 0.043*sl enb to tdo t plh 0.58 0.50 + 0.042*sl 0.49 + 0.043*sl 0.51 + 0.040*sl t phl 0.60 0.55 + 0.028*sl 0.56 + 0.025*sl 0.57 + 0.024*sl t r 0.32 0.15 + 0.087*sl 0.14 + 0.092*sl 0.13 + 0.093*sl t f 0.19 0.11 + 0.042*sl 0.11 + 0.040*sl 0.11 + 0.042*sl dinp to dout t plh 0.29 0.25 + 0.023*sl 0.25 + 0.022*sl 0.26 + 0.020*sl t phl 0.35 0.31 + 0.023*sl 0.31 + 0.022*sl 0.36 + 0.015*sl t r 0.19 0.12 + 0.034*sl 0.10 + 0.043*sl 0.10 + 0.043*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.021*sl 0.14 + 0.021*sl mode to dout t plh 0.35 0.31 + 0.023*sl 0.31 + 0.021*sl 0.31 + 0.021*sl t phl 0.25 0.19 + 0.031*sl 0.22 + 0.018*sl 0.23 + 0.015*sl t r 0.18 0.10 + 0.044*sl 0.09 + 0.045*sl 0.07 + 0.049*sl t f 0.16 0.11 + 0.025*sl 0.12 + 0.022*sl 0.11 + 0.022*sl update to dout t plh 0.66 0.61 + 0.024*sl 0.62 + 0.021*sl 0.61 + 0.022*sl t phl 0.65 0.60 + 0.025*sl 0.62 + 0.018*sl 0.62 + 0.018*sl t r 0.18 0.10 + 0.040*sl 0.09 + 0.047*sl 0.13 + 0.041*sl t f 0.18 0.13 + 0.026*sl 0.14 + 0.022*sl 0.14 + 0.022*sl setn to dout t plh 0.53 0.48 + 0.024*sl 0.49 + 0.022*sl 0.49 + 0.021*sl t phl 0.46 0.41 + 0.025*sl 0.42 + 0.018*sl 0.44 + 0.015*sl t r 0.18 0.11 + 0.035*sl 0.09 + 0.043*sl 0.08 + 0.046*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.022*sl 0.13 + 0.023*sl tck to dout t plh 1.16 1.11 + 0.025*sl 1.12 + 0.021*sl 1.12 + 0.021*sl t phl 1.25 1.15 + 0.049*sl 1.23 + 0.018*sl 1.25 + 0.015*sl t r 0.18 0.10 + 0.042*sl 0.09 + 0.046*sl 0.11 + 0.043*sl t f 0.18 0.13 + 0.026*sl 0.14 + 0.022*sl 0.15 + 0.020*sl enb to dout t plh 1.15 1.10 + 0.023*sl 1.11 + 0.022*sl 1.11 + 0.021*sl t phl 1.25 1.20 + 0.023*sl 1.21 + 0.018*sl 1.24 + 0.015*sl t r 0.19 0.10 + 0.044*sl 0.10 + 0.045*sl 0.11 + 0.043*sl t f 0.18 0.13 + 0.026*sl 0.14 + 0.022*sl 0.14 + 0.021*sl update to inst t plh 0.59 0.51 + 0.041*sl 0.51 + 0.041*sl 0.49 + 0.044*sl t phl 0.57 0.51 + 0.030*sl 0.53 + 0.025*sl 0.52 + 0.026*sl t r 0.27 0.10 + 0.084*sl 0.09 + 0.090*sl 0.07 + 0.092*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.08 + 0.041*sl setn to inst t plh 0.47 0.39 + 0.042*sl 0.39 + 0.041*sl 0.39 + 0.042*sl t phl 0.38 0.31 + 0.033*sl 0.33 + 0.026*sl 0.34 + 0.023*sl t r 0.27 0.09 + 0.087*sl 0.07 + 0.095*sl 0.12 + 0.089*sl t f 0.17 0.10 + 0.036*sl 0.10 + 0.039*sl 0.07 + 0.043*sl
sec asic 6-21 kg80/KGM80 jtint1 tri-state i/o control scan cell with capture, shift, update and set switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 jtint1 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to inst t plh 1.09 1.04 + 0.025*sl 1.00 + 0.045*sl 1.05 + 0.037*sl t phl 1.18 1.14 + 0.018*sl 1.11 + 0.028*sl 1.16 + 0.023*sl t r 0.27 0.09 + 0.090*sl 0.10 + 0.088*sl 0.08 + 0.091*sl t f 0.17 0.09 + 0.042*sl 0.09 + 0.040*sl 0.07 + 0.043*sl enb to inst t plh 1.09 1.01 + 0.041*sl 1.00 + 0.044*sl 1.03 + 0.040*sl t phl 1.18 1.12 + 0.029*sl 1.13 + 0.025*sl 1.14 + 0.023*sl t r 0.27 0.09 + 0.091*sl 0.08 + 0.096*sl 0.12 + 0.090*sl t f 0.17 0.09 + 0.040*sl 0.09 + 0.041*sl 0.07 + 0.043*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
kg80/KGM80 6-22 sec asic jtint1 tri-state i/o control scan cell with capture, shift, update and set switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 jtint1 (continued) [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to tdo t plh 0.83 0.69 + 0.066*sl 0.75 + 0.047*sl 0.71 + 0.050*sl t phl 0.84 0.78 + 0.031*sl 0.79 + 0.026*sl 0.81 + 0.023*sl t r 0.43 0.22 + 0.106*sl 0.22 + 0.108*sl 0.19 + 0.110*sl t f 0.24 0.15 + 0.041*sl 0.15 + 0.042*sl 0.15 + 0.042*sl enb to tdo t plh 0.81 0.74 + 0.034*sl 0.70 + 0.049*sl 0.65 + 0.054*sl t phl 0.86 0.81 + 0.023*sl 0.80 + 0.027*sl 0.84 + 0.023*sl t r 0.43 0.22 + 0.106*sl 0.22 + 0.109*sl 0.20 + 0.110*sl t f 0.24 0.15 + 0.044*sl 0.16 + 0.041*sl 0.15 + 0.042*sl dinp to dout t plh 0.37 0.30 + 0.034*sl 0.33 + 0.025*sl 0.33 + 0.025*sl t phl 0.49 0.45 + 0.019*sl 0.44 + 0.023*sl 0.55 + 0.013*sl t r 0.26 0.13 + 0.063*sl 0.17 + 0.050*sl 0.14 + 0.053*sl t f 0.23 0.16 + 0.034*sl 0.19 + 0.023*sl 0.21 + 0.022*sl mode to dout t plh 0.44 0.38 + 0.031*sl 0.39 + 0.026*sl 0.41 + 0.025*sl t phl 0.36 0.31 + 0.027*sl 0.34 + 0.017*sl 0.33 + 0.018*sl t r 0.25 0.13 + 0.060*sl 0.15 + 0.051*sl 0.12 + 0.054*sl t f 0.20 0.14 + 0.032*sl 0.15 + 0.027*sl 0.21 + 0.022*sl update to dout t plh 0.90 0.84 + 0.032*sl 0.86 + 0.025*sl 0.87 + 0.024*sl t phl 0.93 0.87 + 0.030*sl 0.90 + 0.021*sl 0.96 + 0.015*sl t r 0.29 0.14 + 0.072*sl 0.21 + 0.045*sl 0.07 + 0.059*sl t f 0.23 0.17 + 0.032*sl 0.19 + 0.024*sl 0.21 + 0.023*sl setn to dout t plh 0.70 0.66 + 0.020*sl 0.63 + 0.029*sl 0.68 + 0.025*sl t phl 0.66 0.60 + 0.031*sl 0.63 + 0.021*sl 0.68 + 0.016*sl t r 0.27 0.10 + 0.081*sl 0.20 + 0.047*sl 0.14 + 0.053*sl t f 0.23 0.17 + 0.031*sl 0.19 + 0.024*sl 0.21 + 0.022*sl tck to dout t plh 1.61 1.55 + 0.029*sl 1.56 + 0.026*sl 1.57 + 0.025*sl t phl 1.82 1.77 + 0.029*sl 1.79 + 0.020*sl 1.84 + 0.016*sl t r 0.27 0.11 + 0.079*sl 0.19 + 0.048*sl 0.15 + 0.052*sl t f 0.24 0.17 + 0.035*sl 0.20 + 0.023*sl 0.19 + 0.024*sl enb to dout t plh 1.64 1.58 + 0.031*sl 1.59 + 0.026*sl 1.60 + 0.025*sl t phl 1.84 1.78 + 0.029*sl 1.80 + 0.020*sl 1.86 + 0.015*sl t r 0.27 0.11 + 0.080*sl 0.19 + 0.048*sl 0.15 + 0.051*sl t f 0.23 0.17 + 0.034*sl 0.20 + 0.023*sl 0.20 + 0.023*sl update to inst t plh 0.81 0.70 + 0.051*sl 0.71 + 0.050*sl 0.68 + 0.052*sl t phl 0.80 0.73 + 0.034*sl 0.75 + 0.026*sl 0.78 + 0.024*sl t r 0.36 0.13 + 0.113*sl 0.14 + 0.110*sl 0.17 + 0.107*sl t f 0.20 0.11 + 0.044*sl 0.12 + 0.042*sl 0.12 + 0.042*sl setn to inst t plh 0.63 0.53 + 0.051*sl 0.54 + 0.050*sl 0.54 + 0.050*sl t phl 0.52 0.42 + 0.050*sl 0.49 + 0.023*sl 0.48 + 0.024*sl t r 0.38 0.11 + 0.132*sl 0.19 + 0.105*sl 0.16 + 0.108*sl t f 0.21 0.13 + 0.039*sl 0.12 + 0.043*sl 0.12 + 0.043*sl
sec asic 6-23 kg80/KGM80 jtint1 tri-state i/o control scan cell with capture, shift, update and set switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 jtint1 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to inst t plh 1.57 1.44 + 0.065*sl 1.49 + 0.047*sl 1.46 + 0.050*sl t phl 1.69 1.63 + 0.033*sl 1.65 + 0.026*sl 1.67 + 0.024*sl t r 0.37 0.12 + 0.122*sl 0.16 + 0.108*sl 0.18 + 0.107*sl t f 0.21 0.11 + 0.048*sl 0.13 + 0.042*sl 0.12 + 0.043*sl enb to inst t plh 1.56 1.49 + 0.034*sl 1.45 + 0.049*sl 1.39 + 0.055*sl t phl 1.71 1.66 + 0.025*sl 1.65 + 0.028*sl 1.70 + 0.024*sl t r 0.36 0.15 + 0.103*sl 0.14 + 0.110*sl 0.16 + 0.108*sl t f 0.21 0.11 + 0.048*sl 0.13 + 0.042*sl 0.12 + 0.043*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
kg80/KGM80 6-24 sec asic jtout1 output scan cell with capture, shift, update and set logic symbol pin description pin name i/o description dinp i parallel data input active low tdi i serial test data input mode i mode select inputlow for data input and high for internal register data value shift i active high shift control input update i update latch inputlow for update setn i active low set input tck i test clock input enb i active high test clock enable input dout o parallel data output tdo o serial test data output dinp tdi mode update setn tck enb tdo shift dout cell data input loading (sl) dinp 4 tdi 3 mode 2 shift 2 update 2 setn 1 tck 1 enb 1 gate count 15
sec asic 6-25 kg80/KGM80 jtout1 output scan cell with capture, shift, update and set truth table note : outputs are de?ned in separate truth tables. in addition, an internal state known as latchq is de?ned as the output of the latch in the logic diagram. timing requirements (typical process, 25 c, 5v, 3.3v) dinp tdi mode shift update setn tck enb output dout 0x0xxxxx0 1x0xxxxx1 x x 1 x x x x x latchq tdo x x x x x x 0 tdoo 0xx0xx 10 1xx0xx 11 x0x1xx 10 x1x1xx 11 x x x x x x 0 x tdoo x x x x x x 1 x tdoo x x x x x x x tdoo latchq xxxxx0xx1 xxxx0 1xxtdo x x x x 1 1 x x latchqo parameter symbol value (ns) kg80 KGM80 input setup time (tdi to tck) t su 0.34 0.64 input hold time (tdi to tck) t hd 0.15 0.33 input setup time (tdi to enb) t su 0.34 0.64 input hold time (tdi to enb) t hd 0.15 0.33 input setup time (dinp to tck) t su 0.37 0.68 input hold time (dinp to tck) t hd 0.15 0.33 input setup time (dinp to enb) t su 0.34 0.64 input hold time (dinp to enb) t hd 0.15 0.33 input setup time (shift to tck) t su 0.45 0.80 input hold time (shift to tck) t hd 0.15 0.33 input setup time (shift to enb) t su 0.45 0.80 input hold time (shift to enb) t hd 0.15 0.33 recovery time (setn) t rc 0.15 0.33 input hold time (setn to update) t hd 0.15 0.33
kg80/KGM80 6-26 sec asic jtout1 output scan cell with capture, shift, update and set switching characteristics (typical process, 25 c, 5v, t r /t f = 0.40ns, sl: standard load) kg80 jtout1 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to tdo t plh 0.58 0.50 + 0.043*sl 0.50 + 0.041*sl 0.49 + 0.042*sl t phl 0.60 0.54 + 0.030*sl 0.55 + 0.026*sl 0.57 + 0.023*sl t r 0.27 0.10 + 0.088*sl 0.09 + 0.089*sl 0.06 + 0.094*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.08 + 0.042*sl enb to tdo t plh 0.57 0.47 + 0.049*sl 0.49 + 0.042*sl 0.49 + 0.042*sl t phl 0.59 0.53 + 0.031*sl 0.54 + 0.026*sl 0.56 + 0.023*sl t r 0.27 0.10 + 0.086*sl 0.09 + 0.090*sl 0.07 + 0.093*sl t f 0.17 0.09 + 0.041*sl 0.09 + 0.040*sl 0.08 + 0.042*sl dinp to dout t plh 0.30 0.25 + 0.024*sl 0.25 + 0.022*sl 0.26 + 0.020*sl t phl 0.35 0.30 + 0.023*sl 0.31 + 0.018*sl 0.32 + 0.018*sl t r 0.19 0.11 + 0.037*sl 0.10 + 0.043*sl 0.07 + 0.047*sl t f 0.18 0.13 + 0.025*sl 0.14 + 0.022*sl 0.15 + 0.020*sl mode to dout t plh 0.34 0.31 + 0.015*sl 0.29 + 0.024*sl 0.31 + 0.021*sl t phl 0.25 0.21 + 0.020*sl 0.22 + 0.015*sl 0.20 + 0.018*sl t r 0.26 0.04 + 0.110*sl 0.25 + 0.022*sl 0.05 + 0.051*sl t f 0.16 0.11 + 0.022*sl 0.11 + 0.024*sl 0.13 + 0.021*sl update to dout t plh 0.64 0.59 + 0.024*sl 0.60 + 0.022*sl 0.61 + 0.021*sl t phl 0.64 0.60 + 0.023*sl 0.60 + 0.021*sl 0.65 + 0.013*sl t r 0.21 0.08 + 0.067*sl 0.15 + 0.035*sl 0.09 + 0.043*sl t f 0.18 0.12 + 0.028*sl 0.14 + 0.022*sl 0.14 + 0.021*sl setn to dout t plh 0.51 0.48 + 0.012*sl 0.45 + 0.026*sl 0.49 + 0.020*sl t phl 0.45 0.40 + 0.023*sl 0.41 + 0.018*sl 0.43 + 0.015*sl t r 0.19 0.10 + 0.043*sl 0.05 + 0.064*sl 0.35 + 0.022*sl t f 0.18 0.13 + 0.024*sl 0.14 + 0.023*sl 0.15 + 0.021*sl tck to dout t plh 1.16 1.11 + 0.025*sl 1.12 + 0.021*sl 1.11 + 0.021*sl t phl 1.25 1.20 + 0.025*sl 1.22 + 0.018*sl 1.24 + 0.015*sl t r 0.18 0.10 + 0.042*sl 0.09 + 0.046*sl 0.09 + 0.046*sl t f 0.18 0.14 + 0.022*sl 0.14 + 0.023*sl 0.16 + 0.020*sl enb to dout t plh 1.14 1.08 + 0.031*sl 1.10 + 0.022*sl 1.11 + 0.021*sl t phl 1.24 1.20 + 0.023*sl 1.21 + 0.018*sl 1.23 + 0.015*sl t r 0.18 0.10 + 0.042*sl 0.09 + 0.044*sl 0.07 + 0.047*sl t f 0.18 0.13 + 0.026*sl 0.14 + 0.023*sl 0.16 + 0.019*sl *group1 : sl < 2, *group2 : 2 sl 7, *group3 : 7 < sl < < = =
sec asic 6-27 kg80/KGM80 jtout1 output scan cell with capture, shift, update and set switching characteristics (typical process, 25 c, 3.3v, t r /t f = 0.40ns, sl: standard load) KGM80 jtout1 [y ypp ] r f () path parameter delay [ns] sl = 2 delay equations [ns] group1* group2* group3* tck to tdo t plh 0.78 0.68 + 0.051*sl 0.68 + 0.050*sl 0.68 + 0.050*sl t phl 0.81 0.74 + 0.035*sl 0.77 + 0.026*sl 0.80 + 0.023*sl t r 0.36 0.15 + 0.104*sl 0.13 + 0.108*sl 0.11 + 0.110*sl t f 0.21 0.13 + 0.040*sl 0.12 + 0.042*sl 0.13 + 0.042*sl enb to tdo t plh 0.80 0.70 + 0.051*sl 0.70 + 0.050*sl 0.71 + 0.050*sl t phl 0.83 0.76 + 0.034*sl 0.78 + 0.026*sl 0.81 + 0.023*sl t r 0.35 0.15 + 0.104*sl 0.13 + 0.108*sl 0.12 + 0.109*sl t f 0.21 0.12 + 0.046*sl 0.13 + 0.041*sl 0.12 + 0.042*sl dinp to dout t plh 0.37 0.31 + 0.029*sl 0.32 + 0.026*sl 0.33 + 0.025*sl t phl 0.49 0.46 + 0.015*sl 0.43 + 0.023*sl 0.55 + 0.012*sl t r 0.24 0.14 + 0.050*sl 0.14 + 0.052*sl 0.13 + 0.053*sl t f 0.23 0.16 + 0.036*sl 0.19 + 0.024*sl 0.23 + 0.020*sl mode to dout t plh 0.45 0.39 + 0.032*sl 0.40 + 0.027*sl 0.41 + 0.026*sl t phl 0.36 0.30 + 0.028*sl 0.32 + 0.021*sl 0.42 + 0.012*sl t r 0.28 0.13 + 0.073*sl 0.16 + 0.062*sl 0.29 + 0.051*sl t f 0.20 0.14 + 0.032*sl 0.15 + 0.026*sl 0.20 + 0.022*sl update to dout t plh 0.88 0.84 + 0.022*sl 0.85 + 0.016*sl 0.83 + 0.018*sl t phl 0.92 0.89 + 0.012*sl 0.88 + 0.015*sl 0.93 + 0.011*sl t r 0.22 0.15 + 0.037*sl 0.14 + 0.039*sl 0.14 + 0.039*sl t f 0.23 0.19 + 0.020*sl 0.19 + 0.019*sl 0.24 + 0.014*sl setn to dout t plh 0.69 0.63 + 0.031*sl 0.64 + 0.027*sl 0.68 + 0.024*sl t phl 0.65 0.59 + 0.030*sl 0.62 + 0.021*sl 0.67 + 0.016*sl t r 0.28 0.15 + 0.068*sl 0.21 + 0.047*sl 0.13 + 0.053*sl t f 0.23 0.17 + 0.033*sl 0.19 + 0.024*sl 0.22 + 0.022*sl tck to dout t plh 1.61 1.55 + 0.030*sl 1.57 + 0.026*sl 1.58 + 0.025*sl t phl 1.81 1.75 + 0.029*sl 1.77 + 0.021*sl 1.83 + 0.015*sl t r 0.24 0.13 + 0.052*sl 0.12 + 0.056*sl 0.19 + 0.050*sl t f 0.23 0.17 + 0.033*sl 0.19 + 0.025*sl 0.21 + 0.023*sl enb to dout t plh 1.64 1.58 + 0.029*sl 1.59 + 0.026*sl 1.61 + 0.025*sl t phl 1.82 1.76 + 0.028*sl 1.78 + 0.021*sl 1.84 + 0.015*sl t r 0.24 0.13 + 0.054*sl 0.13 + 0.056*sl 0.20 + 0.049*sl t f 0.24 0.18 + 0.028*sl 0.19 + 0.025*sl 0.23 + 0.021*sl *group1 : sl < 3, *group2 : 3 sl 11, *group3 : 11 < sl < < = =
jtag tap controller macrofunction jtag boundary scans kg80/KGM80 6-28 sec asic jtag tap controller macrofunction tap controller macrofunction consists of instruction register and data register scan paths, a bypass register, multiplexers and a 16-state ?nite state machine. the bypass register and instruction register are jtag devices. tap controller uses the largest available internal buffers (ivd8) to drive data register control signals. instruction register/decoder are external to tap controller since the register length and instruction codes vary from one asic design to another. the instruction register consists of three jtint1 macrocells. the instruction decoder is used to implement a minimum tap con?guration with a boundary scan register and an optional identi?cation register. tap controller input pin description name mandatory description bpsel bypass select dregdi data register scan path data-in iregdi instruction register scan path data-in tck ? test clock tdi ? test data input to the bypass register tms ? test mode select controlling state transitions of a finite state machine trstn test reset input tap controller output pin description name mandatory description dre data register enable control output ire instruction register enable control output rsto reset output shfdr data register shift control output shfir instruction register shift control output tdo ? test data output tdoe tdo tri-state enable output updatedr data register update control output updateir instruction register update control output the bulleted pins (tck, tdi, tms and tdo) are mandatory pins associated with the ieee p1149.1 standard test bus interface. trstn is an optional test reset input. it is possible to implement tap without the test reset input indicated in the ieee p1149.1 standard by setting trstn pin to high logic state. alternatively, if a power-on reset capability is desired, trstn pin should be set to active low and connected to the power-on reset circuitry. the 16 states of the ?nite state machine, diagrammed in the ?gure 9-3, also comply with the proposed ieee p1149.1 standard. state transitions occur on the rising edge of tck and are controlled by tms. to ensure stable state transitions, tms transitions occur on the falling edges of tck. capture, shift or update of test data take place on the next rising edge of tck after the state transition or on each subsequent rising edge of tck if no state transition occurs.
jtag boundary scans jtag tap controller macrofunction sec asic 6-29 kg80/KGM80 figure 6-3. tap controller i/o pin-out diagram figure 6-4. tap controller state diagram behavior of tap controller states test-logic-reset an initialization of the instruction register disables the test logic, allowing the on-chip system logic to operate normally. irrespective of its original state, tap controller reverts to test-logic-reset when tms is maintained high for ?ve rising edges of tck. run-test/idle idles in the state between scan operations or self-tests. capture-dr loads data parallelly into test data registers selected by the current instruction on the rising edge of tck. tdi bpsel dregdi trstn iregdi tms tck tdo shift-dr dre update-dr tdoe rsto shift-ir ire update-ir test-logic-reset run-test/idle select-dr scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 00 0 0 1 1 0 0 0 1 0 1
jtag tap controller macrofunction jtag boundary scans kg80/KGM80 6-30 sec asic shift-dr shifts data in the test data register between tdi and tdo one stage towards its serial output on each rising edge of tck. pause-dr temporarily halts test data register shifts in the serial path between tdi and tdo. update-dr latches the data from the shift register path to the parallel output of test data registers on the falling edge of tck. capture-ir the shift-register contained in the instruction register loads a pattern of ?xed logic value on the rising edge of tck. it is possible to load design-speci?c data into shift-register stages that are not set to ?xed values. shift-ir shifts data contained in the shift-register of the instruction register between tdi and tdo one stage towards its serial output on each rising edge of tck. pause-ir temporarily halts shifting of the instruction register. update-ir latches the instruction shifted into the instruction register to the parallel output from the shift register path on the falling edge of tck. select-dr-scan, select-ir-scan, exit1-dr, exit2-dr, exit1-ir, exit2-ir they are temporary controller states. state assignments for tap controller table 6-1. state assignments the bypass circuitry captures a low state during the data capture state of the ?nite state machine data cycle, as required by the proposed ieee 1149.1 standard. controller state state [3:0] controller state state [3:0] exit2-dr 0 exit2-ir 8 exit1-dr 1 exit1-ir 9 shift-dr 2 shift-ir a pause-dr 3 pause-ir b select-ir scan 4 run-test/idle c update-dr 5 update-ir d capture-dr 6 capture-ir e select-dr-scan 7 test-logic-reset f
jtag boundary scans instruction register/decoder macrofunction sec asic 6-31 kg80/KGM80 instruction register/decoder macrofunction instruction register macrofunction the instruction register provides eight instructions in a minimum 3-bit device. these 3 bits are suf?cient for operations of boundary scan cells and an instruction register, and three other operations such as the internal scan chains. devices requiring more than eight instructions need a customer-speci?c design. the instruction register allows an instruction to be shifted into the design. the instruction de?nes the test to be performed or the test data register to access or both. if a device identi?cation register is present, the output register must be initialized to idcode instruction when tap controller is in the test-logic-reset state. alternatively, it may be initialized to the bypass instruction. to support a fault isolation at the board-level, a constant binary 01 pattern is loaded into the least signi?cant bits of the instruction register when it is in the capture-ir state. instruction decoder macrofunction the instruction decoder operates with the instruction register to provide boundary scan control. designs requiring other options need a customer-speci?c design. instruction decoder input pin description: name descr iption inst (2:0) instruction register input instruction decoder output pin description: name descr iption 0_mode boundary scan output mode control i_mode boundary scan input mode control the instruction decoder has the following truth table. inst(2) inst(1) inst(0) i_mode 0_mode 00001 00111 01000 01100 10000 10100 11000 11100
implementation of ieee p1149.1/jtag jtag boundary scans kg80/KGM80 6-32 sec asic implementation of ieee p1149.1/jtag the following design procedures should be followed for asic implementation of ieee p1149.1/jtag using sec boundary scan cells: 1. allocate four (optionally ?ve) package pins for testing. 2. generate a bonding diagram, including provision for the corner pads that cannot be used for boundary scan i/os. 3. con?gure the top level device symbol with the same pin-out sequence as the packaged device. 4. select appropriate boundary scan macrocells, jtbi1, jtck, jtin1 and jtout1, for the boundary- scan i/o pads. jtck and jtin1 must be associated with inputs; jtout1 with outputs and jtbi1 with bi-directional inputs and outputs. 5. asic clock inputs generally use jtck macrocell, but it may be used for other critical inputs where performance considerations dominate. jtout1 macrocells are used for each output pin and jtbi1 macrocells are used by bi-directional pins. 6. jtag inputs (tdi, tck, tms), output (tdo) and optional trstn are connected to tap controller. the boundary scan register and the instruction register are connected to tdi and tck inputs. inputs, tdi, tms and trstn should have input pull-up resistors. 7. to start the boundary scan chain sequence, connect any tdi input to jtbi1, jtck, jtin1, or jtout1 macrocells. the chain sequence proceeds to each adjacent macrocell i/o pad until terminated. tdo output of the ?nal macrocell is connected to dregdi input of tap controller. similarly, the terminal tdo output of the instruction register is connected to iregdi of tap controller. 8. instruction register and data register control signals are connected to the instruction register and boundary scan registers, and inst signal lines from the instruction register are connected to the instruction decoder which supplies the control signals bpsel, i_mode and o_mode for tap controller and the boundary scan register. i_mode is connected to jtin1 macrocells and o_mode is connected to jtout1 macrocells. i_mode, o_mode and mode1 are also connected to the appropriate inputs of jtbi1 macrocells. 9. i_mode output is connected to a ivd8 macrocell and tn inputs of the bi-directional and tri-state output buffers associated with the respective i/o pads. other buffers may be required if there are a large number of bi-directional or tri-state pads. 10. if the design requires internal tri-state enable control signals, an additional jtint1 macrocell is needed for each enable. internal enable macrocells should be connected to tap controller rsto signal and o_mode control line. jtin1 macrocell is used for external tri-state enable input signals and should be connected to tap controller rsto signal and i_mode control line. 11. generate the test patterns to test jtag portion of the design. system clock considerations test and system clocks must be synchronized carefully. all phases of the system clock should be gated on and off at a central point within the system. when tms input is high, tck can run continuously and test modes is disabled.

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